projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 5e3dd157 KV |
1 | /* |
| 2 | * Copyright (c) 2005-2011 Atheros Communications Inc. | |
| 3 | * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. | |
| 4 | * | |
| 5 | * Permission to use, copy, modify, and/or distribute this software for any | |
| 6 | * purpose with or without fee is hereby granted, provided that the above | |
| 7 | * copyright notice and this permission notice appear in all copies. | |
| 8 | * | |
| 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
| 10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
| 11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
| 12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
| 13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
| 14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
| 15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
| 16 | */ | |
| 17 | ||
| 18 | #ifndef __TARGADDRS_H__ | |
| 19 | #define __TARGADDRS_H__ | |
| 20 | ||
| 21 | /* | |
| 22 | * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the | |
| 23 | * host_interest structure. It must match the address of the _host_interest | |
| 24 | * symbol (see linker script). | |
| 25 | * | |
| 26 | * Host Interest is shared between Host and Target in order to coordinate | |
| 27 | * between the two, and is intended to remain constant (with additions only | |
| 28 | * at the end) across software releases. | |
| 29 | * | |
| 30 | * All addresses are available here so that it's possible to | |
| 31 | * write a single binary that works with all Target Types. | |
| 32 | * May be used in assembler code as well as C. | |
| 33 | */ | |
| 34 | #define QCA988X_HOST_INTEREST_ADDRESS 0x00400800 | |
| 35 | #define HOST_INTEREST_MAX_SIZE 0x200 | |
| 36 | ||
| 37 | /* | |
| 38 | * These are items that the Host may need to access via BMI or via the | |
| 39 | * Diagnostic Window. The position of items in this structure must remain | |
| 40 | * constant across firmware revisions! Types for each item must be fixed | |
| 41 | * size across target and host platforms. More items may be added at the end. | |
| 42 | */ | |
| 43 | struct host_interest { | |
| 44 | /* | |
| 45 | * Pointer to application-defined area, if any. | |
| 46 | * Set by Target application during startup. | |
| 47 | */ | |
| 48 | u32 hi_app_host_interest; /* 0x00 */ | |
| 49 | ||
| 50 | /* Pointer to register dump area, valid after Target crash. */ | |
| 51 | u32 hi_failure_state; /* 0x04 */ | |
| 52 | ||
| 53 | /* Pointer to debug logging header */ | |
| 54 | u32 hi_dbglog_hdr; /* 0x08 */ | |
| 55 | ||
| 56 | u32 hi_unused0c; /* 0x0c */ | |
| 57 | ||
| 58 | /* | |
| 59 | * General-purpose flag bits, similar to SOC_OPTION_* flags. | |
| 60 | * Can be used by application rather than by OS. | |
| 61 | */ | |
| 62 | u32 hi_option_flag; /* 0x10 */ | |
| 63 | ||
| 64 | /* | |
| 65 | * Boolean that determines whether or not to | |
| 66 | * display messages on the serial port. | |
| 67 | */ | |
| 68 | u32 hi_serial_enable; /* 0x14 */ | |
| 69 | ||
| 70 | /* Start address of DataSet index, if any */ | |
| 71 | u32 hi_dset_list_head; /* 0x18 */ | |
| 72 | ||
| 73 | /* Override Target application start address */ | |
| 74 | u32 hi_app_start; /* 0x1c */ | |
| 75 | ||
| 76 | /* Clock and voltage tuning */ | |
| 77 | u32 hi_skip_clock_init; /* 0x20 */ | |
| 78 | u32 hi_core_clock_setting; /* 0x24 */ | |
| 79 | u32 hi_cpu_clock_setting; /* 0x28 */ | |
| 80 | u32 hi_system_sleep_setting; /* 0x2c */ | |
| 81 | u32 hi_xtal_control_setting; /* 0x30 */ | |
| 82 | u32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ | |
| 83 | u32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ | |
| 84 | u32 hi_ref_voltage_trim_setting; /* 0x3c */ | |
| 85 | u32 hi_clock_info; /* 0x40 */ | |
| 86 | ||
| 87 | /* Host uses BE CPU or not */ | |
| 88 | u32 hi_be; /* 0x44 */ | |
| 89 | ||
| 90 | u32 hi_stack; /* normal stack */ /* 0x48 */ | |
| 91 | u32 hi_err_stack; /* error stack */ /* 0x4c */ | |
| 92 | u32 hi_desired_cpu_speed_hz; /* 0x50 */ | |
| 93 | ||
| 94 | /* Pointer to Board Data */ | |
| 95 | u32 hi_board_data; /* 0x54 */ | |
| 96 | ||
| 97 | /* | |
| 98 | * Indication of Board Data state: | |
| 99 | * 0: board data is not yet initialized. | |
| 100 | * 1: board data is initialized; unknown size | |
| 101 | * >1: number of bytes of initialized board data | |
| 102 | */ | |
| 103 | u32 hi_board_data_initialized; /* 0x58 */ | |
| 104 | ||
| 105 | u32 hi_dset_ram_index_table; /* 0x5c */ | |
| 106 | ||
| 107 | u32 hi_desired_baud_rate; /* 0x60 */ | |
| 108 | u32 hi_dbglog_config; /* 0x64 */ | |
| 109 | u32 hi_end_ram_reserve_sz; /* 0x68 */ | |
| 110 | u32 hi_mbox_io_block_sz; /* 0x6c */ | |
| 111 | ||
| 112 | u32 hi_num_bpatch_streams; /* 0x70 -- unused */ | |
| 113 | u32 hi_mbox_isr_yield_limit; /* 0x74 */ | |
| 114 | ||
| 115 | u32 hi_refclk_hz; /* 0x78 */ | |
| 116 | u32 hi_ext_clk_detected; /* 0x7c */ | |
| 117 | u32 hi_dbg_uart_txpin; /* 0x80 */ | |
| 118 | u32 hi_dbg_uart_rxpin; /* 0x84 */ | |
| 119 | u32 hi_hci_uart_baud; /* 0x88 */ | |
| 120 | u32 hi_hci_uart_pin_assignments; /* 0x8C */ | |
| 121 | ||
| 122 | u32 hi_hci_uart_baud_scale_val; /* 0x90 */ | |
| 123 | u32 hi_hci_uart_baud_step_val; /* 0x94 */ | |
| 124 | ||
| 125 | u32 hi_allocram_start; /* 0x98 */ | |
| 126 | u32 hi_allocram_sz; /* 0x9c */ | |
| 127 | u32 hi_hci_bridge_flags; /* 0xa0 */ | |
| 128 | u32 hi_hci_uart_support_pins; /* 0xa4 */ | |
| 129 | ||
| 130 | u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */ | |
| 131 | ||
| 132 | /* | |
| 133 | * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high | |
| 134 | * [31:16]: wakeup timeout in ms | |
| 135 | */ | |
| 136 | /* Pointer to extended board Data */ | |
| 137 | u32 hi_board_ext_data; /* 0xac */ | |
| 138 | u32 hi_board_ext_data_config; /* 0xb0 */ | |
| 139 | /* | |
| 140 | * Bit [0] : valid | |
| 141 | * Bit[31:16: size | |
| 142 | */ | |
| 143 | /* | |
| 144 | * hi_reset_flag is used to do some stuff when target reset. | |
| 145 | * such as restore app_start after warm reset or | |
| 146 | * preserve host Interest area, or preserve ROM data, literals etc. | |
| 147 | */ | |
| 148 | u32 hi_reset_flag; /* 0xb4 */ | |
| 149 | /* indicate hi_reset_flag is valid */ | |
| 150 | u32 hi_reset_flag_valid; /* 0xb8 */ | |
| 151 | u32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */ | |
| 152 | /* 0xbc - [31:0]: idle timeout in ms */ | |
| 153 | /* ACS flags */ | |
| 154 | u32 hi_acs_flags; /* 0xc0 */ | |
| 155 | u32 hi_console_flags; /* 0xc4 */ | |
| 156 | u32 hi_nvram_state; /* 0xc8 */ | |
| 157 | u32 hi_option_flag2; /* 0xcc */ | |
| 158 | ||
| 159 | /* If non-zero, override values sent to Host in WMI_READY event. */ | |
| 160 | u32 hi_sw_version_override; /* 0xd0 */ | |
| 161 | u32 hi_abi_version_override; /* 0xd4 */ | |
| 162 | ||
| 163 | /* | |
| 164 | * Percentage of high priority RX traffic to total expected RX traffic | |
| 165 | * applicable only to ar6004 | |
| 166 | */ | |
| 167 | u32 hi_hp_rx_traffic_ratio; /* 0xd8 */ | |
| 168 | ||
| 169 | /* test applications flags */ | |
| 170 | u32 hi_test_apps_related; /* 0xdc */ | |
| 171 | /* location of test script */ | |
| 172 | u32 hi_ota_testscript; /* 0xe0 */ | |
| 173 | /* location of CAL data */ | |
| 174 | u32 hi_cal_data; /* 0xe4 */ | |
| 175 | ||
| 176 | /* Number of packet log buffers */ | |
| 177 | u32 hi_pktlog_num_buffers; /* 0xe8 */ | |
| 178 | ||
| 179 | /* wow extension configuration */ | |
| 180 | u32 hi_wow_ext_config; /* 0xec */ | |
| 181 | u32 hi_pwr_save_flags; /* 0xf0 */ | |
| 182 | ||
| 183 | /* Spatial Multiplexing Power Save (SMPS) options */ | |
| 184 | u32 hi_smps_options; /* 0xf4 */ | |
| 185 | ||
| 186 | /* Interconnect-specific state */ | |
| 187 | u32 hi_interconnect_state; /* 0xf8 */ | |
| 188 | ||
| 189 | /* Coex configuration flags */ | |
| 190 | u32 hi_coex_config; /* 0xfc */ | |
| 191 | ||
| 192 | /* Early allocation support */ | |
| 193 | u32 hi_early_alloc; /* 0x100 */ | |
| 194 | /* FW swap field */ | |
| 195 | /* | |
| 196 | * Bits of this 32bit word will be used to pass specific swap | |
| 197 | * instruction to FW | |
| 198 | */ | |
| 199 | /* | |
| 200 | * Bit 0 -- AP Nart descriptor no swap. When this bit is set | |
| 201 | * FW will not swap TX descriptor. Meaning packets are formed | |
| 202 | * on the target processor. | |
| 203 | */ | |
| 204 | /* Bit 1 - unused */ | |
| 205 | u32 hi_fw_swap; /* 0x104 */ | |
| 206 | } __packed; | |
| 207 | ||
| 208 | #define HI_ITEM(item) offsetof(struct host_interest, item) | |
| 209 | ||
| 210 | /* Bits defined in hi_option_flag */ | |
| 211 | ||
| 212 | /* Enable timer workaround */ | |
| 213 | #define HI_OPTION_TIMER_WAR 0x01 | |
| 214 | /* Limit BMI command credits */ | |
| 215 | #define HI_OPTION_BMI_CRED_LIMIT 0x02 | |
| 216 | /* Relay Dot11 hdr to/from host */ | |
| 217 | #define HI_OPTION_RELAY_DOT11_HDR 0x04 | |
| 218 | /* MAC addr method 0-locally administred 1-globally unique addrs */ | |
| 219 | #define HI_OPTION_MAC_ADDR_METHOD 0x08 | |
| 220 | /* Firmware Bridging */ | |
| 221 | #define HI_OPTION_FW_BRIDGE 0x10 | |
| 222 | /* Enable CPU profiling */ | |
| 223 | #define HI_OPTION_ENABLE_PROFILE 0x20 | |
| 224 | /* Disable debug logging */ | |
| 225 | #define HI_OPTION_DISABLE_DBGLOG 0x40 | |
| 226 | /* Skip Era Tracking */ | |
| 227 | #define HI_OPTION_SKIP_ERA_TRACKING 0x80 | |
| 228 | /* Disable PAPRD (debug) */ | |
| 229 | #define HI_OPTION_PAPRD_DISABLE 0x100 | |
| 230 | #define HI_OPTION_NUM_DEV_LSB 0x200 | |
| 231 | #define HI_OPTION_NUM_DEV_MSB 0x800 | |
| 232 | #define HI_OPTION_DEV_MODE_LSB 0x1000 | |
| 233 | #define HI_OPTION_DEV_MODE_MSB 0x8000000 | |
| 234 | /* Disable LowFreq Timer Stabilization */ | |
| 235 | #define HI_OPTION_NO_LFT_STBL 0x10000000 | |
| 236 | /* Skip regulatory scan */ | |
| 237 | #define HI_OPTION_SKIP_REG_SCAN 0x20000000 | |
| 238 | /* | |
| 239 | * Do regulatory scan during init before | |
| 240 | * sending WMI ready event to host | |
| 241 | */ | |
| 242 | #define HI_OPTION_INIT_REG_SCAN 0x40000000 | |
| 243 | ||
| 244 | /* REV6: Do not adjust memory map */ | |
| 245 | #define HI_OPTION_SKIP_MEMMAP 0x80000000 | |
| 246 | ||
| 247 | #define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3 | |
| 248 | ||
| 249 | /* 2 bits of hi_option_flag are used to represent 3 modes */ | |
| 250 | #define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */ | |
| 251 | #define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */ | |
| 252 | #define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */ | |
| 253 | #define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */ | |
| 254 | ||
| 255 | /* 2 bits of hi_option flag are usedto represent 4 submodes */ | |
| 256 | #define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */ | |
| 257 | #define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */ | |
| 258 | #define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */ | |
| 259 | #define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */ | |
| 260 | ||
| 261 | /* Num dev Mask */ | |
| 262 | #define HI_OPTION_NUM_DEV_MASK 0x7 | |
| 263 | #define HI_OPTION_NUM_DEV_SHIFT 0x9 | |
| 264 | ||
| 265 | /* firmware bridging */ | |
| 266 | #define HI_OPTION_FW_BRIDGE_SHIFT 0x04 | |
| 267 | ||
| 268 | /* | |
| 269 | Fw Mode/SubMode Mask | |
| 270 | |-----------------------------------------------------------------------------| | |
| 271 | | SUB | SUB | SUB | SUB | | | | | | |
| 272 | |MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0]| | |
| 273 | | (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) | | |
| 274 | |-----------------------------------------------------------------------------| | |
| 275 | */ | |
| 276 | #define HI_OPTION_FW_MODE_BITS 0x2 | |
| 277 | #define HI_OPTION_FW_MODE_MASK 0x3 | |
| 278 | #define HI_OPTION_FW_MODE_SHIFT 0xC | |
| 279 | #define HI_OPTION_ALL_FW_MODE_MASK 0xFF | |
| 280 | ||
| 281 | #define HI_OPTION_FW_SUBMODE_BITS 0x2 | |
| 282 | #define HI_OPTION_FW_SUBMODE_MASK 0x3 | |
| 283 | #define HI_OPTION_FW_SUBMODE_SHIFT 0x14 | |
| 284 | #define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00 | |
| 285 | #define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8 | |
| 286 | ||
| 5e3dd157 KV |
287 | /* hi_option_flag2 options */ |
| 288 | #define HI_OPTION_OFFLOAD_AMSDU 0x01 | |
| 289 | #define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */ | |
| 290 | #define HI_OPTION_ENABLE_RFKILL 0x04 /* RFKill Enable Feature*/ | |
| 291 | #define HI_OPTION_RADIO_RETENTION_DISABLE 0x08 /* Disable radio retention */ | |
| 292 | #define HI_OPTION_EARLY_CFG_DONE 0x10 /* Early configuration is complete */ | |
| 293 | ||
| 294 | #define HI_OPTION_RF_KILL_SHIFT 0x2 | |
| 295 | #define HI_OPTION_RF_KILL_MASK 0x1 | |
| 296 | ||
| 297 | /* hi_reset_flag */ | |
| 298 | /* preserve App Start address */ | |
| 299 | #define HI_RESET_FLAG_PRESERVE_APP_START 0x01 | |
| 300 | /* preserve host interest */ | |
| 301 | #define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02 | |
| 302 | /* preserve ROM data */ | |
| 303 | #define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 | |
| 304 | #define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08 | |
| 305 | #define HI_RESET_FLAG_PRESERVE_BOOT_INFO 0x10 | |
| 306 | #define HI_RESET_FLAG_WARM_RESET 0x20 | |
| 307 | ||
| 308 | /* define hi_fw_swap bits */ | |
| 309 | #define HI_DESC_IN_FW_BIT 0x01 | |
| 310 | ||
| 311 | /* indicate the reset flag is valid */ | |
| 312 | #define HI_RESET_FLAG_IS_VALID 0x12345678 | |
| 313 | ||
| 314 | /* ACS is enabled */ | |
| 315 | #define HI_ACS_FLAGS_ENABLED (1 << 0) | |
| 316 | /* Use physical WWAN device */ | |
| 317 | #define HI_ACS_FLAGS_USE_WWAN (1 << 1) | |
| 318 | /* Use test VAP */ | |
| 319 | #define HI_ACS_FLAGS_TEST_VAP (1 << 2) | |
| 320 | ||
| 321 | /* | |
| 322 | * CONSOLE FLAGS | |
| 323 | * | |
| 324 | * Bit Range Meaning | |
| 325 | * --------- -------------------------------- | |
| 326 | * 2..0 UART ID (0 = Default) | |
| 327 | * 3 Baud Select (0 = 9600, 1 = 115200) | |
| 328 | * 30..4 Reserved | |
| 329 | * 31 Enable Console | |
| 330 | * | |
| 331 | */ | |
| 332 | ||
| 333 | #define HI_CONSOLE_FLAGS_ENABLE (1 << 31) | |
| 334 | #define HI_CONSOLE_FLAGS_UART_MASK (0x7) | |
| 335 | #define HI_CONSOLE_FLAGS_UART_SHIFT 0 | |
| 336 | #define HI_CONSOLE_FLAGS_BAUD_SELECT (1 << 3) | |
| 337 | ||
| 338 | /* SM power save options */ | |
| 339 | #define HI_SMPS_ALLOW_MASK (0x00000001) | |
| 340 | #define HI_SMPS_MODE_MASK (0x00000002) | |
| 341 | #define HI_SMPS_MODE_STATIC (0x00000000) | |
| 342 | #define HI_SMPS_MODE_DYNAMIC (0x00000002) | |
| 343 | #define HI_SMPS_DISABLE_AUTO_MODE (0x00000004) | |
| 344 | #define HI_SMPS_DATA_THRESH_MASK (0x000007f8) | |
| 345 | #define HI_SMPS_DATA_THRESH_SHIFT (3) | |
| 346 | #define HI_SMPS_RSSI_THRESH_MASK (0x0007f800) | |
| 347 | #define HI_SMPS_RSSI_THRESH_SHIFT (11) | |
| 348 | #define HI_SMPS_LOWPWR_CM_MASK (0x00380000) | |
| 349 | #define HI_SMPS_LOWPWR_CM_SHIFT (15) | |
| 350 | #define HI_SMPS_HIPWR_CM_MASK (0x03c00000) | |
| 351 | #define HI_SMPS_HIPWR_CM_SHIFT (19) | |
| 352 | ||
| 353 | /* | |
| 354 | * WOW Extension configuration | |
| 355 | * | |
| 356 | * Bit Range Meaning | |
| 357 | * --------- -------------------------------- | |
| 358 | * 8..0 Size of each WOW pattern (max 511) | |
| 359 | * 15..9 Number of patterns per list (max 127) | |
| 360 | * 17..16 Number of lists (max 4) | |
| 361 | * 30..18 Reserved | |
| 362 | * 31 Enabled | |
| 363 | * | |
| 364 | * set values (except enable) to zeros for default settings | |
| 365 | */ | |
| 366 | ||
| 367 | #define HI_WOW_EXT_ENABLED_MASK (1 << 31) | |
| 368 | #define HI_WOW_EXT_NUM_LIST_SHIFT 16 | |
| 369 | #define HI_WOW_EXT_NUM_LIST_MASK (0x3 << HI_WOW_EXT_NUM_LIST_SHIFT) | |
| 370 | #define HI_WOW_EXT_NUM_PATTERNS_SHIFT 9 | |
| 371 | #define HI_WOW_EXT_NUM_PATTERNS_MASK (0x7F << HI_WOW_EXT_NUM_PATTERNS_SHIFT) | |
| 372 | #define HI_WOW_EXT_PATTERN_SIZE_SHIFT 0 | |
| 373 | #define HI_WOW_EXT_PATTERN_SIZE_MASK (0x1FF << HI_WOW_EXT_PATTERN_SIZE_SHIFT) | |
| 374 | ||
| 375 | #define HI_WOW_EXT_MAKE_CONFIG(num_lists, count, size) \ | |
| 376 | ((((num_lists) << HI_WOW_EXT_NUM_LIST_SHIFT) & \ | |
| 377 | HI_WOW_EXT_NUM_LIST_MASK) | \ | |
| 378 | (((count) << HI_WOW_EXT_NUM_PATTERNS_SHIFT) & \ | |
| 379 | HI_WOW_EXT_NUM_PATTERNS_MASK) | \ | |
| 380 | (((size) << HI_WOW_EXT_PATTERN_SIZE_SHIFT) & \ | |
| 381 | HI_WOW_EXT_PATTERN_SIZE_MASK)) | |
| 382 | ||
| 383 | #define HI_WOW_EXT_GET_NUM_LISTS(config) \ | |
| 384 | (((config) & HI_WOW_EXT_NUM_LIST_MASK) >> HI_WOW_EXT_NUM_LIST_SHIFT) | |
| 385 | #define HI_WOW_EXT_GET_NUM_PATTERNS(config) \ | |
| 386 | (((config) & HI_WOW_EXT_NUM_PATTERNS_MASK) >> \ | |
| 387 | HI_WOW_EXT_NUM_PATTERNS_SHIFT) | |
| 388 | #define HI_WOW_EXT_GET_PATTERN_SIZE(config) \ | |
| 389 | (((config) & HI_WOW_EXT_PATTERN_SIZE_MASK) >> \ | |
| 390 | HI_WOW_EXT_PATTERN_SIZE_SHIFT) | |
| 391 | ||
| 392 | /* | |
| 393 | * Early allocation configuration | |
| 394 | * Support RAM bank configuration before BMI done and this eases the memory | |
| 395 | * allocation at very early stage | |
| 396 | * Bit Range Meaning | |
| 397 | * --------- ---------------------------------- | |
| 398 | * [0:3] number of bank assigned to be IRAM | |
| 399 | * [4:15] reserved | |
| 400 | * [16:31] magic number | |
| 401 | * | |
| 402 | * Note: | |
| 403 | * 1. target firmware would check magic number and if it's a match, firmware | |
| 404 | * would consider the bits[0:15] are valid and base on that to calculate | |
| 405 | * the end of DRAM. Early allocation would be located at that area and | |
| 406 | * may be reclaimed when necesary | |
| 407 | * 2. if no magic number is found, early allocation would happen at "_end" | |
| 408 | * symbol of ROM which is located before the app-data and might NOT be | |
| 409 | * re-claimable. If this is adopted, link script should keep this in | |
| 410 | * mind to avoid data corruption. | |
| 411 | */ | |
| 412 | #define HI_EARLY_ALLOC_MAGIC 0x6d8a | |
| 413 | #define HI_EARLY_ALLOC_MAGIC_MASK 0xffff0000 | |
| 414 | #define HI_EARLY_ALLOC_MAGIC_SHIFT 16 | |
| 415 | #define HI_EARLY_ALLOC_IRAM_BANKS_MASK 0x0000000f | |
| 416 | #define HI_EARLY_ALLOC_IRAM_BANKS_SHIFT 0 | |
| 417 | ||
| 418 | #define HI_EARLY_ALLOC_VALID() \ | |
| 419 | ((((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_MAGIC_MASK) >> \ | |
| 420 | HI_EARLY_ALLOC_MAGIC_SHIFT) == (HI_EARLY_ALLOC_MAGIC)) | |
| 421 | #define HI_EARLY_ALLOC_GET_IRAM_BANKS() \ | |
| 422 | (((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_IRAM_BANKS_MASK) \ | |
| 423 | >> HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) | |
| 424 | ||
| 425 | /*power save flag bit definitions*/ | |
| 426 | #define HI_PWR_SAVE_LPL_ENABLED 0x1 | |
| 427 | /*b1-b3 reserved*/ | |
| 428 | /*b4-b5 : dev0 LPL type : 0 - none | |
| 429 | 1- Reduce Pwr Search | |
| 430 | 2- Reduce Pwr Listen*/ | |
| 431 | /*b6-b7 : dev1 LPL type and so on for Max 8 devices*/ | |
| 432 | #define HI_PWR_SAVE_LPL_DEV0_LSB 4 | |
| 433 | #define HI_PWR_SAVE_LPL_DEV_MASK 0x3 | |
| 434 | /*power save related utility macros*/ | |
| 435 | #define HI_LPL_ENABLED() \ | |
| 436 | ((HOST_INTEREST->hi_pwr_save_flags & HI_PWR_SAVE_LPL_ENABLED)) | |
| 437 | #define HI_DEV_LPL_TYPE_GET(_devix) \ | |
| 438 | (HOST_INTEREST->hi_pwr_save_flags & ((HI_PWR_SAVE_LPL_DEV_MASK) << \ | |
| 439 | (HI_PWR_SAVE_LPL_DEV0_LSB + (_devix)*2))) | |
| 440 | ||
| 441 | #define HOST_INTEREST_SMPS_IS_ALLOWED() \ | |
| 442 | ((HOST_INTEREST->hi_smps_options & HI_SMPS_ALLOW_MASK)) | |
| 443 | ||
| 444 | /* Reserve 1024 bytes for extended board data */ | |
| 445 | #define QCA988X_BOARD_DATA_SZ 7168 | |
| 446 | #define QCA988X_BOARD_EXT_DATA_SZ 0 | |
| 447 | ||
| 448 | #endif /* __TARGADDRS_H__ */ |