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ath10k: implement intermediate event args
[deliverable/linux.git] / drivers / net / wireless / ath / ath10k / wmi.c
CommitLineData
5e3dd157
KV		 1/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#include <linux/skbuff.h>
2fe5288c 19#include <linux/ctype.h>
5e3dd157
KV		 20
21#include "core.h"
22#include "htc.h"
23#include "debug.h"
24#include "wmi.h"
25#include "mac.h"
43d2a30f 26#include "testmode.h"
5e3dd157 27
ce42870e
BM		 28/* MAIN WMI cmd track */
29static struct wmi_cmd_map wmi_cmd_map = {
30 .init_cmdid = WMI_INIT_CMDID,
31 .start_scan_cmdid = WMI_START_SCAN_CMDID,
32 .stop_scan_cmdid = WMI_STOP_SCAN_CMDID,
33 .scan_chan_list_cmdid = WMI_SCAN_CHAN_LIST_CMDID,
34 .scan_sch_prio_tbl_cmdid = WMI_SCAN_SCH_PRIO_TBL_CMDID,
35 .pdev_set_regdomain_cmdid = WMI_PDEV_SET_REGDOMAIN_CMDID,
36 .pdev_set_channel_cmdid = WMI_PDEV_SET_CHANNEL_CMDID,
37 .pdev_set_param_cmdid = WMI_PDEV_SET_PARAM_CMDID,
38 .pdev_pktlog_enable_cmdid = WMI_PDEV_PKTLOG_ENABLE_CMDID,
39 .pdev_pktlog_disable_cmdid = WMI_PDEV_PKTLOG_DISABLE_CMDID,
40 .pdev_set_wmm_params_cmdid = WMI_PDEV_SET_WMM_PARAMS_CMDID,
41 .pdev_set_ht_cap_ie_cmdid = WMI_PDEV_SET_HT_CAP_IE_CMDID,
42 .pdev_set_vht_cap_ie_cmdid = WMI_PDEV_SET_VHT_CAP_IE_CMDID,
43 .pdev_set_dscp_tid_map_cmdid = WMI_PDEV_SET_DSCP_TID_MAP_CMDID,
44 .pdev_set_quiet_mode_cmdid = WMI_PDEV_SET_QUIET_MODE_CMDID,
45 .pdev_green_ap_ps_enable_cmdid = WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID,
46 .pdev_get_tpc_config_cmdid = WMI_PDEV_GET_TPC_CONFIG_CMDID,
47 .pdev_set_base_macaddr_cmdid = WMI_PDEV_SET_BASE_MACADDR_CMDID,
48 .vdev_create_cmdid = WMI_VDEV_CREATE_CMDID,
49 .vdev_delete_cmdid = WMI_VDEV_DELETE_CMDID,
50 .vdev_start_request_cmdid = WMI_VDEV_START_REQUEST_CMDID,
51 .vdev_restart_request_cmdid = WMI_VDEV_RESTART_REQUEST_CMDID,
52 .vdev_up_cmdid = WMI_VDEV_UP_CMDID,
53 .vdev_stop_cmdid = WMI_VDEV_STOP_CMDID,
54 .vdev_down_cmdid = WMI_VDEV_DOWN_CMDID,
55 .vdev_set_param_cmdid = WMI_VDEV_SET_PARAM_CMDID,
56 .vdev_install_key_cmdid = WMI_VDEV_INSTALL_KEY_CMDID,
57 .peer_create_cmdid = WMI_PEER_CREATE_CMDID,
58 .peer_delete_cmdid = WMI_PEER_DELETE_CMDID,
59 .peer_flush_tids_cmdid = WMI_PEER_FLUSH_TIDS_CMDID,
60 .peer_set_param_cmdid = WMI_PEER_SET_PARAM_CMDID,
61 .peer_assoc_cmdid = WMI_PEER_ASSOC_CMDID,
62 .peer_add_wds_entry_cmdid = WMI_PEER_ADD_WDS_ENTRY_CMDID,
63 .peer_remove_wds_entry_cmdid = WMI_PEER_REMOVE_WDS_ENTRY_CMDID,
64 .peer_mcast_group_cmdid = WMI_PEER_MCAST_GROUP_CMDID,
65 .bcn_tx_cmdid = WMI_BCN_TX_CMDID,
66 .pdev_send_bcn_cmdid = WMI_PDEV_SEND_BCN_CMDID,
67 .bcn_tmpl_cmdid = WMI_BCN_TMPL_CMDID,
68 .bcn_filter_rx_cmdid = WMI_BCN_FILTER_RX_CMDID,
69 .prb_req_filter_rx_cmdid = WMI_PRB_REQ_FILTER_RX_CMDID,
70 .mgmt_tx_cmdid = WMI_MGMT_TX_CMDID,
71 .prb_tmpl_cmdid = WMI_PRB_TMPL_CMDID,
72 .addba_clear_resp_cmdid = WMI_ADDBA_CLEAR_RESP_CMDID,
73 .addba_send_cmdid = WMI_ADDBA_SEND_CMDID,
74 .addba_status_cmdid = WMI_ADDBA_STATUS_CMDID,
75 .delba_send_cmdid = WMI_DELBA_SEND_CMDID,
76 .addba_set_resp_cmdid = WMI_ADDBA_SET_RESP_CMDID,
77 .send_singleamsdu_cmdid = WMI_SEND_SINGLEAMSDU_CMDID,
78 .sta_powersave_mode_cmdid = WMI_STA_POWERSAVE_MODE_CMDID,
79 .sta_powersave_param_cmdid = WMI_STA_POWERSAVE_PARAM_CMDID,
80 .sta_mimo_ps_mode_cmdid = WMI_STA_MIMO_PS_MODE_CMDID,
81 .pdev_dfs_enable_cmdid = WMI_PDEV_DFS_ENABLE_CMDID,
82 .pdev_dfs_disable_cmdid = WMI_PDEV_DFS_DISABLE_CMDID,
83 .roam_scan_mode = WMI_ROAM_SCAN_MODE,
84 .roam_scan_rssi_threshold = WMI_ROAM_SCAN_RSSI_THRESHOLD,
85 .roam_scan_period = WMI_ROAM_SCAN_PERIOD,
86 .roam_scan_rssi_change_threshold = WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD,
87 .roam_ap_profile = WMI_ROAM_AP_PROFILE,
88 .ofl_scan_add_ap_profile = WMI_ROAM_AP_PROFILE,
89 .ofl_scan_remove_ap_profile = WMI_OFL_SCAN_REMOVE_AP_PROFILE,
90 .ofl_scan_period = WMI_OFL_SCAN_PERIOD,
91 .p2p_dev_set_device_info = WMI_P2P_DEV_SET_DEVICE_INFO,
92 .p2p_dev_set_discoverability = WMI_P2P_DEV_SET_DISCOVERABILITY,
93 .p2p_go_set_beacon_ie = WMI_P2P_GO_SET_BEACON_IE,
94 .p2p_go_set_probe_resp_ie = WMI_P2P_GO_SET_PROBE_RESP_IE,
95 .p2p_set_vendor_ie_data_cmdid = WMI_P2P_SET_VENDOR_IE_DATA_CMDID,
96 .ap_ps_peer_param_cmdid = WMI_AP_PS_PEER_PARAM_CMDID,
97 .ap_ps_peer_uapsd_coex_cmdid = WMI_AP_PS_PEER_UAPSD_COEX_CMDID,
98 .peer_rate_retry_sched_cmdid = WMI_PEER_RATE_RETRY_SCHED_CMDID,
99 .wlan_profile_trigger_cmdid = WMI_WLAN_PROFILE_TRIGGER_CMDID,
100 .wlan_profile_set_hist_intvl_cmdid =
101 WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID,
102 .wlan_profile_get_profile_data_cmdid =
103 WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID,
104 .wlan_profile_enable_profile_id_cmdid =
105 WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID,
106 .wlan_profile_list_profile_id_cmdid =
107 WMI_WLAN_PROFILE_LIST_PROFILE_ID_CMDID,
108 .pdev_suspend_cmdid = WMI_PDEV_SUSPEND_CMDID,
109 .pdev_resume_cmdid = WMI_PDEV_RESUME_CMDID,
110 .add_bcn_filter_cmdid = WMI_ADD_BCN_FILTER_CMDID,
111 .rmv_bcn_filter_cmdid = WMI_RMV_BCN_FILTER_CMDID,
112 .wow_add_wake_pattern_cmdid = WMI_WOW_ADD_WAKE_PATTERN_CMDID,
113 .wow_del_wake_pattern_cmdid = WMI_WOW_DEL_WAKE_PATTERN_CMDID,
114 .wow_enable_disable_wake_event_cmdid =
115 WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID,
116 .wow_enable_cmdid = WMI_WOW_ENABLE_CMDID,
117 .wow_hostwakeup_from_sleep_cmdid = WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID,
118 .rtt_measreq_cmdid = WMI_RTT_MEASREQ_CMDID,
119 .rtt_tsf_cmdid = WMI_RTT_TSF_CMDID,
120 .vdev_spectral_scan_configure_cmdid =
121 WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID,
122 .vdev_spectral_scan_enable_cmdid = WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID,
123 .request_stats_cmdid = WMI_REQUEST_STATS_CMDID,
124 .set_arp_ns_offload_cmdid = WMI_SET_ARP_NS_OFFLOAD_CMDID,
125 .network_list_offload_config_cmdid =
126 WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID,
127 .gtk_offload_cmdid = WMI_GTK_OFFLOAD_CMDID,
128 .csa_offload_enable_cmdid = WMI_CSA_OFFLOAD_ENABLE_CMDID,
129 .csa_offload_chanswitch_cmdid = WMI_CSA_OFFLOAD_CHANSWITCH_CMDID,
130 .chatter_set_mode_cmdid = WMI_CHATTER_SET_MODE_CMDID,
131 .peer_tid_addba_cmdid = WMI_PEER_TID_ADDBA_CMDID,
132 .peer_tid_delba_cmdid = WMI_PEER_TID_DELBA_CMDID,
133 .sta_dtim_ps_method_cmdid = WMI_STA_DTIM_PS_METHOD_CMDID,
134 .sta_uapsd_auto_trig_cmdid = WMI_STA_UAPSD_AUTO_TRIG_CMDID,
135 .sta_keepalive_cmd = WMI_STA_KEEPALIVE_CMD,
136 .echo_cmdid = WMI_ECHO_CMDID,
137 .pdev_utf_cmdid = WMI_PDEV_UTF_CMDID,
138 .dbglog_cfg_cmdid = WMI_DBGLOG_CFG_CMDID,
139 .pdev_qvit_cmdid = WMI_PDEV_QVIT_CMDID,
140 .pdev_ftm_intg_cmdid = WMI_PDEV_FTM_INTG_CMDID,
141 .vdev_set_keepalive_cmdid = WMI_VDEV_SET_KEEPALIVE_CMDID,
142 .vdev_get_keepalive_cmdid = WMI_VDEV_GET_KEEPALIVE_CMDID,
143 .force_fw_hang_cmdid = WMI_FORCE_FW_HANG_CMDID,
144 .gpio_config_cmdid = WMI_GPIO_CONFIG_CMDID,
145 .gpio_output_cmdid = WMI_GPIO_OUTPUT_CMDID,
146};
147
b7e3adf9
BM		 148/* 10.X WMI cmd track */
149static struct wmi_cmd_map wmi_10x_cmd_map = {
150 .init_cmdid = WMI_10X_INIT_CMDID,
151 .start_scan_cmdid = WMI_10X_START_SCAN_CMDID,
152 .stop_scan_cmdid = WMI_10X_STOP_SCAN_CMDID,
153 .scan_chan_list_cmdid = WMI_10X_SCAN_CHAN_LIST_CMDID,
34957b25 154 .scan_sch_prio_tbl_cmdid = WMI_CMD_UNSUPPORTED,
b7e3adf9
BM		 155 .pdev_set_regdomain_cmdid = WMI_10X_PDEV_SET_REGDOMAIN_CMDID,
156 .pdev_set_channel_cmdid = WMI_10X_PDEV_SET_CHANNEL_CMDID,
157 .pdev_set_param_cmdid = WMI_10X_PDEV_SET_PARAM_CMDID,
158 .pdev_pktlog_enable_cmdid = WMI_10X_PDEV_PKTLOG_ENABLE_CMDID,
159 .pdev_pktlog_disable_cmdid = WMI_10X_PDEV_PKTLOG_DISABLE_CMDID,
160 .pdev_set_wmm_params_cmdid = WMI_10X_PDEV_SET_WMM_PARAMS_CMDID,
161 .pdev_set_ht_cap_ie_cmdid = WMI_10X_PDEV_SET_HT_CAP_IE_CMDID,
162 .pdev_set_vht_cap_ie_cmdid = WMI_10X_PDEV_SET_VHT_CAP_IE_CMDID,
163 .pdev_set_dscp_tid_map_cmdid = WMI_10X_PDEV_SET_DSCP_TID_MAP_CMDID,
164 .pdev_set_quiet_mode_cmdid = WMI_10X_PDEV_SET_QUIET_MODE_CMDID,
165 .pdev_green_ap_ps_enable_cmdid = WMI_10X_PDEV_GREEN_AP_PS_ENABLE_CMDID,
166 .pdev_get_tpc_config_cmdid = WMI_10X_PDEV_GET_TPC_CONFIG_CMDID,
167 .pdev_set_base_macaddr_cmdid = WMI_10X_PDEV_SET_BASE_MACADDR_CMDID,
168 .vdev_create_cmdid = WMI_10X_VDEV_CREATE_CMDID,
169 .vdev_delete_cmdid = WMI_10X_VDEV_DELETE_CMDID,
170 .vdev_start_request_cmdid = WMI_10X_VDEV_START_REQUEST_CMDID,
171 .vdev_restart_request_cmdid = WMI_10X_VDEV_RESTART_REQUEST_CMDID,
172 .vdev_up_cmdid = WMI_10X_VDEV_UP_CMDID,
173 .vdev_stop_cmdid = WMI_10X_VDEV_STOP_CMDID,
174 .vdev_down_cmdid = WMI_10X_VDEV_DOWN_CMDID,
175 .vdev_set_param_cmdid = WMI_10X_VDEV_SET_PARAM_CMDID,
176 .vdev_install_key_cmdid = WMI_10X_VDEV_INSTALL_KEY_CMDID,
177 .peer_create_cmdid = WMI_10X_PEER_CREATE_CMDID,
178 .peer_delete_cmdid = WMI_10X_PEER_DELETE_CMDID,
179 .peer_flush_tids_cmdid = WMI_10X_PEER_FLUSH_TIDS_CMDID,
180 .peer_set_param_cmdid = WMI_10X_PEER_SET_PARAM_CMDID,
181 .peer_assoc_cmdid = WMI_10X_PEER_ASSOC_CMDID,
182 .peer_add_wds_entry_cmdid = WMI_10X_PEER_ADD_WDS_ENTRY_CMDID,
183 .peer_remove_wds_entry_cmdid = WMI_10X_PEER_REMOVE_WDS_ENTRY_CMDID,
184 .peer_mcast_group_cmdid = WMI_10X_PEER_MCAST_GROUP_CMDID,
185 .bcn_tx_cmdid = WMI_10X_BCN_TX_CMDID,
186 .pdev_send_bcn_cmdid = WMI_10X_PDEV_SEND_BCN_CMDID,
34957b25 187 .bcn_tmpl_cmdid = WMI_CMD_UNSUPPORTED,
b7e3adf9
BM		 188 .bcn_filter_rx_cmdid = WMI_10X_BCN_FILTER_RX_CMDID,
189 .prb_req_filter_rx_cmdid = WMI_10X_PRB_REQ_FILTER_RX_CMDID,
190 .mgmt_tx_cmdid = WMI_10X_MGMT_TX_CMDID,
34957b25 191 .prb_tmpl_cmdid = WMI_CMD_UNSUPPORTED,
b7e3adf9
BM		 192 .addba_clear_resp_cmdid = WMI_10X_ADDBA_CLEAR_RESP_CMDID,
193 .addba_send_cmdid = WMI_10X_ADDBA_SEND_CMDID,
194 .addba_status_cmdid = WMI_10X_ADDBA_STATUS_CMDID,
195 .delba_send_cmdid = WMI_10X_DELBA_SEND_CMDID,
196 .addba_set_resp_cmdid = WMI_10X_ADDBA_SET_RESP_CMDID,
197 .send_singleamsdu_cmdid = WMI_10X_SEND_SINGLEAMSDU_CMDID,
198 .sta_powersave_mode_cmdid = WMI_10X_STA_POWERSAVE_MODE_CMDID,
199 .sta_powersave_param_cmdid = WMI_10X_STA_POWERSAVE_PARAM_CMDID,
200 .sta_mimo_ps_mode_cmdid = WMI_10X_STA_MIMO_PS_MODE_CMDID,
201 .pdev_dfs_enable_cmdid = WMI_10X_PDEV_DFS_ENABLE_CMDID,
202 .pdev_dfs_disable_cmdid = WMI_10X_PDEV_DFS_DISABLE_CMDID,
203 .roam_scan_mode = WMI_10X_ROAM_SCAN_MODE,
204 .roam_scan_rssi_threshold = WMI_10X_ROAM_SCAN_RSSI_THRESHOLD,
205 .roam_scan_period = WMI_10X_ROAM_SCAN_PERIOD,
206 .roam_scan_rssi_change_threshold =
207 WMI_10X_ROAM_SCAN_RSSI_CHANGE_THRESHOLD,
208 .roam_ap_profile = WMI_10X_ROAM_AP_PROFILE,
209 .ofl_scan_add_ap_profile = WMI_10X_OFL_SCAN_ADD_AP_PROFILE,
210 .ofl_scan_remove_ap_profile = WMI_10X_OFL_SCAN_REMOVE_AP_PROFILE,
211 .ofl_scan_period = WMI_10X_OFL_SCAN_PERIOD,
212 .p2p_dev_set_device_info = WMI_10X_P2P_DEV_SET_DEVICE_INFO,
213 .p2p_dev_set_discoverability = WMI_10X_P2P_DEV_SET_DISCOVERABILITY,
214 .p2p_go_set_beacon_ie = WMI_10X_P2P_GO_SET_BEACON_IE,
215 .p2p_go_set_probe_resp_ie = WMI_10X_P2P_GO_SET_PROBE_RESP_IE,
34957b25 216 .p2p_set_vendor_ie_data_cmdid = WMI_CMD_UNSUPPORTED,
542fb174 217 .ap_ps_peer_param_cmdid = WMI_10X_AP_PS_PEER_PARAM_CMDID,
34957b25 218 .ap_ps_peer_uapsd_coex_cmdid = WMI_CMD_UNSUPPORTED,
b7e3adf9
BM		 219 .peer_rate_retry_sched_cmdid = WMI_10X_PEER_RATE_RETRY_SCHED_CMDID,
220 .wlan_profile_trigger_cmdid = WMI_10X_WLAN_PROFILE_TRIGGER_CMDID,
221 .wlan_profile_set_hist_intvl_cmdid =
222 WMI_10X_WLAN_PROFILE_SET_HIST_INTVL_CMDID,
223 .wlan_profile_get_profile_data_cmdid =
224 WMI_10X_WLAN_PROFILE_GET_PROFILE_DATA_CMDID,
225 .wlan_profile_enable_profile_id_cmdid =
226 WMI_10X_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID,
227 .wlan_profile_list_profile_id_cmdid =
228 WMI_10X_WLAN_PROFILE_LIST_PROFILE_ID_CMDID,
229 .pdev_suspend_cmdid = WMI_10X_PDEV_SUSPEND_CMDID,
230 .pdev_resume_cmdid = WMI_10X_PDEV_RESUME_CMDID,
231 .add_bcn_filter_cmdid = WMI_10X_ADD_BCN_FILTER_CMDID,
232 .rmv_bcn_filter_cmdid = WMI_10X_RMV_BCN_FILTER_CMDID,
233 .wow_add_wake_pattern_cmdid = WMI_10X_WOW_ADD_WAKE_PATTERN_CMDID,
234 .wow_del_wake_pattern_cmdid = WMI_10X_WOW_DEL_WAKE_PATTERN_CMDID,
235 .wow_enable_disable_wake_event_cmdid =
236 WMI_10X_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID,
237 .wow_enable_cmdid = WMI_10X_WOW_ENABLE_CMDID,
238 .wow_hostwakeup_from_sleep_cmdid =
239 WMI_10X_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID,
240 .rtt_measreq_cmdid = WMI_10X_RTT_MEASREQ_CMDID,
241 .rtt_tsf_cmdid = WMI_10X_RTT_TSF_CMDID,
242 .vdev_spectral_scan_configure_cmdid =
243 WMI_10X_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID,
244 .vdev_spectral_scan_enable_cmdid =
245 WMI_10X_VDEV_SPECTRAL_SCAN_ENABLE_CMDID,
246 .request_stats_cmdid = WMI_10X_REQUEST_STATS_CMDID,
34957b25
BM		 247 .set_arp_ns_offload_cmdid = WMI_CMD_UNSUPPORTED,
248 .network_list_offload_config_cmdid = WMI_CMD_UNSUPPORTED,
249 .gtk_offload_cmdid = WMI_CMD_UNSUPPORTED,
250 .csa_offload_enable_cmdid = WMI_CMD_UNSUPPORTED,
251 .csa_offload_chanswitch_cmdid = WMI_CMD_UNSUPPORTED,
252 .chatter_set_mode_cmdid = WMI_CMD_UNSUPPORTED,
253 .peer_tid_addba_cmdid = WMI_CMD_UNSUPPORTED,
254 .peer_tid_delba_cmdid = WMI_CMD_UNSUPPORTED,
255 .sta_dtim_ps_method_cmdid = WMI_CMD_UNSUPPORTED,
256 .sta_uapsd_auto_trig_cmdid = WMI_CMD_UNSUPPORTED,
257 .sta_keepalive_cmd = WMI_CMD_UNSUPPORTED,
b7e3adf9
BM		 258 .echo_cmdid = WMI_10X_ECHO_CMDID,
259 .pdev_utf_cmdid = WMI_10X_PDEV_UTF_CMDID,
260 .dbglog_cfg_cmdid = WMI_10X_DBGLOG_CFG_CMDID,
261 .pdev_qvit_cmdid = WMI_10X_PDEV_QVIT_CMDID,
34957b25
BM		 262 .pdev_ftm_intg_cmdid = WMI_CMD_UNSUPPORTED,
263 .vdev_set_keepalive_cmdid = WMI_CMD_UNSUPPORTED,
264 .vdev_get_keepalive_cmdid = WMI_CMD_UNSUPPORTED,
265 .force_fw_hang_cmdid = WMI_CMD_UNSUPPORTED,
b7e3adf9
BM		 266 .gpio_config_cmdid = WMI_10X_GPIO_CONFIG_CMDID,
267 .gpio_output_cmdid = WMI_10X_GPIO_OUTPUT_CMDID,
268};
ce42870e 269
6d1506e7
BM		 270/* MAIN WMI VDEV param map */
271static struct wmi_vdev_param_map wmi_vdev_param_map = {
272 .rts_threshold = WMI_VDEV_PARAM_RTS_THRESHOLD,
273 .fragmentation_threshold = WMI_VDEV_PARAM_FRAGMENTATION_THRESHOLD,
274 .beacon_interval = WMI_VDEV_PARAM_BEACON_INTERVAL,
275 .listen_interval = WMI_VDEV_PARAM_LISTEN_INTERVAL,
276 .multicast_rate = WMI_VDEV_PARAM_MULTICAST_RATE,
277 .mgmt_tx_rate = WMI_VDEV_PARAM_MGMT_TX_RATE,
278 .slot_time = WMI_VDEV_PARAM_SLOT_TIME,
279 .preamble = WMI_VDEV_PARAM_PREAMBLE,
280 .swba_time = WMI_VDEV_PARAM_SWBA_TIME,
281 .wmi_vdev_stats_update_period = WMI_VDEV_STATS_UPDATE_PERIOD,
282 .wmi_vdev_pwrsave_ageout_time = WMI_VDEV_PWRSAVE_AGEOUT_TIME,
283 .wmi_vdev_host_swba_interval = WMI_VDEV_HOST_SWBA_INTERVAL,
284 .dtim_period = WMI_VDEV_PARAM_DTIM_PERIOD,
285 .wmi_vdev_oc_scheduler_air_time_limit =
286 WMI_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT,
287 .wds = WMI_VDEV_PARAM_WDS,
288 .atim_window = WMI_VDEV_PARAM_ATIM_WINDOW,
289 .bmiss_count_max = WMI_VDEV_PARAM_BMISS_COUNT_MAX,
290 .bmiss_first_bcnt = WMI_VDEV_PARAM_BMISS_FIRST_BCNT,
291 .bmiss_final_bcnt = WMI_VDEV_PARAM_BMISS_FINAL_BCNT,
292 .feature_wmm = WMI_VDEV_PARAM_FEATURE_WMM,
293 .chwidth = WMI_VDEV_PARAM_CHWIDTH,
294 .chextoffset = WMI_VDEV_PARAM_CHEXTOFFSET,
295 .disable_htprotection = WMI_VDEV_PARAM_DISABLE_HTPROTECTION,
296 .sta_quickkickout = WMI_VDEV_PARAM_STA_QUICKKICKOUT,
297 .mgmt_rate = WMI_VDEV_PARAM_MGMT_RATE,
298 .protection_mode = WMI_VDEV_PARAM_PROTECTION_MODE,
299 .fixed_rate = WMI_VDEV_PARAM_FIXED_RATE,
300 .sgi = WMI_VDEV_PARAM_SGI,
301 .ldpc = WMI_VDEV_PARAM_LDPC,
302 .tx_stbc = WMI_VDEV_PARAM_TX_STBC,
303 .rx_stbc = WMI_VDEV_PARAM_RX_STBC,
304 .intra_bss_fwd = WMI_VDEV_PARAM_INTRA_BSS_FWD,
305 .def_keyid = WMI_VDEV_PARAM_DEF_KEYID,
306 .nss = WMI_VDEV_PARAM_NSS,
307 .bcast_data_rate = WMI_VDEV_PARAM_BCAST_DATA_RATE,
308 .mcast_data_rate = WMI_VDEV_PARAM_MCAST_DATA_RATE,
309 .mcast_indicate = WMI_VDEV_PARAM_MCAST_INDICATE,
310 .dhcp_indicate = WMI_VDEV_PARAM_DHCP_INDICATE,
311 .unknown_dest_indicate = WMI_VDEV_PARAM_UNKNOWN_DEST_INDICATE,
312 .ap_keepalive_min_idle_inactive_time_secs =
313 WMI_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS,
314 .ap_keepalive_max_idle_inactive_time_secs =
315 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS,
316 .ap_keepalive_max_unresponsive_time_secs =
317 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS,
318 .ap_enable_nawds = WMI_VDEV_PARAM_AP_ENABLE_NAWDS,
319 .mcast2ucast_set = WMI_VDEV_PARAM_UNSUPPORTED,
320 .enable_rtscts = WMI_VDEV_PARAM_ENABLE_RTSCTS,
321 .txbf = WMI_VDEV_PARAM_TXBF,
322 .packet_powersave = WMI_VDEV_PARAM_PACKET_POWERSAVE,
323 .drop_unencry = WMI_VDEV_PARAM_DROP_UNENCRY,
324 .tx_encap_type = WMI_VDEV_PARAM_TX_ENCAP_TYPE,
325 .ap_detect_out_of_sync_sleeping_sta_time_secs =
326 WMI_VDEV_PARAM_UNSUPPORTED,
327};
328
329/* 10.X WMI VDEV param map */
330static struct wmi_vdev_param_map wmi_10x_vdev_param_map = {
331 .rts_threshold = WMI_10X_VDEV_PARAM_RTS_THRESHOLD,
332 .fragmentation_threshold = WMI_10X_VDEV_PARAM_FRAGMENTATION_THRESHOLD,
333 .beacon_interval = WMI_10X_VDEV_PARAM_BEACON_INTERVAL,
334 .listen_interval = WMI_10X_VDEV_PARAM_LISTEN_INTERVAL,
335 .multicast_rate = WMI_10X_VDEV_PARAM_MULTICAST_RATE,
336 .mgmt_tx_rate = WMI_10X_VDEV_PARAM_MGMT_TX_RATE,
337 .slot_time = WMI_10X_VDEV_PARAM_SLOT_TIME,
338 .preamble = WMI_10X_VDEV_PARAM_PREAMBLE,
339 .swba_time = WMI_10X_VDEV_PARAM_SWBA_TIME,
340 .wmi_vdev_stats_update_period = WMI_10X_VDEV_STATS_UPDATE_PERIOD,
341 .wmi_vdev_pwrsave_ageout_time = WMI_10X_VDEV_PWRSAVE_AGEOUT_TIME,
342 .wmi_vdev_host_swba_interval = WMI_10X_VDEV_HOST_SWBA_INTERVAL,
343 .dtim_period = WMI_10X_VDEV_PARAM_DTIM_PERIOD,
344 .wmi_vdev_oc_scheduler_air_time_limit =
345 WMI_10X_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT,
346 .wds = WMI_10X_VDEV_PARAM_WDS,
347 .atim_window = WMI_10X_VDEV_PARAM_ATIM_WINDOW,
348 .bmiss_count_max = WMI_10X_VDEV_PARAM_BMISS_COUNT_MAX,
349 .bmiss_first_bcnt = WMI_VDEV_PARAM_UNSUPPORTED,
350 .bmiss_final_bcnt = WMI_VDEV_PARAM_UNSUPPORTED,
351 .feature_wmm = WMI_10X_VDEV_PARAM_FEATURE_WMM,
352 .chwidth = WMI_10X_VDEV_PARAM_CHWIDTH,
353 .chextoffset = WMI_10X_VDEV_PARAM_CHEXTOFFSET,
354 .disable_htprotection = WMI_10X_VDEV_PARAM_DISABLE_HTPROTECTION,
355 .sta_quickkickout = WMI_10X_VDEV_PARAM_STA_QUICKKICKOUT,
356 .mgmt_rate = WMI_10X_VDEV_PARAM_MGMT_RATE,
357 .protection_mode = WMI_10X_VDEV_PARAM_PROTECTION_MODE,
358 .fixed_rate = WMI_10X_VDEV_PARAM_FIXED_RATE,
359 .sgi = WMI_10X_VDEV_PARAM_SGI,
360 .ldpc = WMI_10X_VDEV_PARAM_LDPC,
361 .tx_stbc = WMI_10X_VDEV_PARAM_TX_STBC,
362 .rx_stbc = WMI_10X_VDEV_PARAM_RX_STBC,
363 .intra_bss_fwd = WMI_10X_VDEV_PARAM_INTRA_BSS_FWD,
364 .def_keyid = WMI_10X_VDEV_PARAM_DEF_KEYID,
365 .nss = WMI_10X_VDEV_PARAM_NSS,
366 .bcast_data_rate = WMI_10X_VDEV_PARAM_BCAST_DATA_RATE,
367 .mcast_data_rate = WMI_10X_VDEV_PARAM_MCAST_DATA_RATE,
368 .mcast_indicate = WMI_10X_VDEV_PARAM_MCAST_INDICATE,
369 .dhcp_indicate = WMI_10X_VDEV_PARAM_DHCP_INDICATE,
370 .unknown_dest_indicate = WMI_10X_VDEV_PARAM_UNKNOWN_DEST_INDICATE,
371 .ap_keepalive_min_idle_inactive_time_secs =
372 WMI_10X_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS,
373 .ap_keepalive_max_idle_inactive_time_secs =
374 WMI_10X_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS,
375 .ap_keepalive_max_unresponsive_time_secs =
376 WMI_10X_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS,
377 .ap_enable_nawds = WMI_10X_VDEV_PARAM_AP_ENABLE_NAWDS,
378 .mcast2ucast_set = WMI_10X_VDEV_PARAM_MCAST2UCAST_SET,
379 .enable_rtscts = WMI_10X_VDEV_PARAM_ENABLE_RTSCTS,
380 .txbf = WMI_VDEV_PARAM_UNSUPPORTED,
381 .packet_powersave = WMI_VDEV_PARAM_UNSUPPORTED,
382 .drop_unencry = WMI_VDEV_PARAM_UNSUPPORTED,
383 .tx_encap_type = WMI_VDEV_PARAM_UNSUPPORTED,
384 .ap_detect_out_of_sync_sleeping_sta_time_secs =
385 WMI_10X_VDEV_PARAM_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS,
386};
387
226a339b
BM		 388static struct wmi_pdev_param_map wmi_pdev_param_map = {
389 .tx_chain_mask = WMI_PDEV_PARAM_TX_CHAIN_MASK,
390 .rx_chain_mask = WMI_PDEV_PARAM_RX_CHAIN_MASK,
391 .txpower_limit2g = WMI_PDEV_PARAM_TXPOWER_LIMIT2G,
392 .txpower_limit5g = WMI_PDEV_PARAM_TXPOWER_LIMIT5G,
393 .txpower_scale = WMI_PDEV_PARAM_TXPOWER_SCALE,
394 .beacon_gen_mode = WMI_PDEV_PARAM_BEACON_GEN_MODE,
395 .beacon_tx_mode = WMI_PDEV_PARAM_BEACON_TX_MODE,
396 .resmgr_offchan_mode = WMI_PDEV_PARAM_RESMGR_OFFCHAN_MODE,
397 .protection_mode = WMI_PDEV_PARAM_PROTECTION_MODE,
398 .dynamic_bw = WMI_PDEV_PARAM_DYNAMIC_BW,
399 .non_agg_sw_retry_th = WMI_PDEV_PARAM_NON_AGG_SW_RETRY_TH,
400 .agg_sw_retry_th = WMI_PDEV_PARAM_AGG_SW_RETRY_TH,
401 .sta_kickout_th = WMI_PDEV_PARAM_STA_KICKOUT_TH,
402 .ac_aggrsize_scaling = WMI_PDEV_PARAM_AC_AGGRSIZE_SCALING,
403 .ltr_enable = WMI_PDEV_PARAM_LTR_ENABLE,
404 .ltr_ac_latency_be = WMI_PDEV_PARAM_LTR_AC_LATENCY_BE,
405 .ltr_ac_latency_bk = WMI_PDEV_PARAM_LTR_AC_LATENCY_BK,
406 .ltr_ac_latency_vi = WMI_PDEV_PARAM_LTR_AC_LATENCY_VI,
407 .ltr_ac_latency_vo = WMI_PDEV_PARAM_LTR_AC_LATENCY_VO,
408 .ltr_ac_latency_timeout = WMI_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT,
409 .ltr_sleep_override = WMI_PDEV_PARAM_LTR_SLEEP_OVERRIDE,
410 .ltr_rx_override = WMI_PDEV_PARAM_LTR_RX_OVERRIDE,
411 .ltr_tx_activity_timeout = WMI_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT,
412 .l1ss_enable = WMI_PDEV_PARAM_L1SS_ENABLE,
413 .dsleep_enable = WMI_PDEV_PARAM_DSLEEP_ENABLE,
414 .pcielp_txbuf_flush = WMI_PDEV_PARAM_PCIELP_TXBUF_FLUSH,
415 .pcielp_txbuf_watermark = WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_EN,
416 .pcielp_txbuf_tmo_en = WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_EN,
417 .pcielp_txbuf_tmo_value = WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_VALUE,
418 .pdev_stats_update_period = WMI_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD,
419 .vdev_stats_update_period = WMI_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD,
420 .peer_stats_update_period = WMI_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD,
421 .bcnflt_stats_update_period = WMI_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD,
422 .pmf_qos = WMI_PDEV_PARAM_PMF_QOS,
423 .arp_ac_override = WMI_PDEV_PARAM_ARP_AC_OVERRIDE,
226a339b
BM		 424 .dcs = WMI_PDEV_PARAM_DCS,
425 .ani_enable = WMI_PDEV_PARAM_ANI_ENABLE,
426 .ani_poll_period = WMI_PDEV_PARAM_ANI_POLL_PERIOD,
427 .ani_listen_period = WMI_PDEV_PARAM_ANI_LISTEN_PERIOD,
428 .ani_ofdm_level = WMI_PDEV_PARAM_ANI_OFDM_LEVEL,
429 .ani_cck_level = WMI_PDEV_PARAM_ANI_CCK_LEVEL,
430 .dyntxchain = WMI_PDEV_PARAM_DYNTXCHAIN,
431 .proxy_sta = WMI_PDEV_PARAM_PROXY_STA,
432 .idle_ps_config = WMI_PDEV_PARAM_IDLE_PS_CONFIG,
433 .power_gating_sleep = WMI_PDEV_PARAM_POWER_GATING_SLEEP,
434 .fast_channel_reset = WMI_PDEV_PARAM_UNSUPPORTED,
435 .burst_dur = WMI_PDEV_PARAM_UNSUPPORTED,
436 .burst_enable = WMI_PDEV_PARAM_UNSUPPORTED,
437};
438
439static struct wmi_pdev_param_map wmi_10x_pdev_param_map = {
440 .tx_chain_mask = WMI_10X_PDEV_PARAM_TX_CHAIN_MASK,
441 .rx_chain_mask = WMI_10X_PDEV_PARAM_RX_CHAIN_MASK,
442 .txpower_limit2g = WMI_10X_PDEV_PARAM_TXPOWER_LIMIT2G,
443 .txpower_limit5g = WMI_10X_PDEV_PARAM_TXPOWER_LIMIT5G,
444 .txpower_scale = WMI_10X_PDEV_PARAM_TXPOWER_SCALE,
445 .beacon_gen_mode = WMI_10X_PDEV_PARAM_BEACON_GEN_MODE,
446 .beacon_tx_mode = WMI_10X_PDEV_PARAM_BEACON_TX_MODE,
447 .resmgr_offchan_mode = WMI_10X_PDEV_PARAM_RESMGR_OFFCHAN_MODE,
448 .protection_mode = WMI_10X_PDEV_PARAM_PROTECTION_MODE,
449 .dynamic_bw = WMI_10X_PDEV_PARAM_DYNAMIC_BW,
450 .non_agg_sw_retry_th = WMI_10X_PDEV_PARAM_NON_AGG_SW_RETRY_TH,
451 .agg_sw_retry_th = WMI_10X_PDEV_PARAM_AGG_SW_RETRY_TH,
452 .sta_kickout_th = WMI_10X_PDEV_PARAM_STA_KICKOUT_TH,
453 .ac_aggrsize_scaling = WMI_10X_PDEV_PARAM_AC_AGGRSIZE_SCALING,
454 .ltr_enable = WMI_10X_PDEV_PARAM_LTR_ENABLE,
455 .ltr_ac_latency_be = WMI_10X_PDEV_PARAM_LTR_AC_LATENCY_BE,
456 .ltr_ac_latency_bk = WMI_10X_PDEV_PARAM_LTR_AC_LATENCY_BK,
457 .ltr_ac_latency_vi = WMI_10X_PDEV_PARAM_LTR_AC_LATENCY_VI,
458 .ltr_ac_latency_vo = WMI_10X_PDEV_PARAM_LTR_AC_LATENCY_VO,
459 .ltr_ac_latency_timeout = WMI_10X_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT,
460 .ltr_sleep_override = WMI_10X_PDEV_PARAM_LTR_SLEEP_OVERRIDE,
461 .ltr_rx_override = WMI_10X_PDEV_PARAM_LTR_RX_OVERRIDE,
462 .ltr_tx_activity_timeout = WMI_10X_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT,
463 .l1ss_enable = WMI_10X_PDEV_PARAM_L1SS_ENABLE,
464 .dsleep_enable = WMI_10X_PDEV_PARAM_DSLEEP_ENABLE,
465 .pcielp_txbuf_flush = WMI_PDEV_PARAM_UNSUPPORTED,
466 .pcielp_txbuf_watermark = WMI_PDEV_PARAM_UNSUPPORTED,
467 .pcielp_txbuf_tmo_en = WMI_PDEV_PARAM_UNSUPPORTED,
468 .pcielp_txbuf_tmo_value = WMI_PDEV_PARAM_UNSUPPORTED,
469 .pdev_stats_update_period = WMI_10X_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD,
470 .vdev_stats_update_period = WMI_10X_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD,
471 .peer_stats_update_period = WMI_10X_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD,
472 .bcnflt_stats_update_period =
473 WMI_10X_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD,
474 .pmf_qos = WMI_10X_PDEV_PARAM_PMF_QOS,
ab6258ed 475 .arp_ac_override = WMI_10X_PDEV_PARAM_ARPDHCP_AC_OVERRIDE,
226a339b
BM		 476 .dcs = WMI_10X_PDEV_PARAM_DCS,
477 .ani_enable = WMI_10X_PDEV_PARAM_ANI_ENABLE,
478 .ani_poll_period = WMI_10X_PDEV_PARAM_ANI_POLL_PERIOD,
479 .ani_listen_period = WMI_10X_PDEV_PARAM_ANI_LISTEN_PERIOD,
480 .ani_ofdm_level = WMI_10X_PDEV_PARAM_ANI_OFDM_LEVEL,
481 .ani_cck_level = WMI_10X_PDEV_PARAM_ANI_CCK_LEVEL,
482 .dyntxchain = WMI_10X_PDEV_PARAM_DYNTXCHAIN,
483 .proxy_sta = WMI_PDEV_PARAM_UNSUPPORTED,
484 .idle_ps_config = WMI_PDEV_PARAM_UNSUPPORTED,
485 .power_gating_sleep = WMI_PDEV_PARAM_UNSUPPORTED,
486 .fast_channel_reset = WMI_10X_PDEV_PARAM_FAST_CHANNEL_RESET,
487 .burst_dur = WMI_10X_PDEV_PARAM_BURST_DUR,
488 .burst_enable = WMI_10X_PDEV_PARAM_BURST_ENABLE,
489};
490
24c88f78
MK		 491/* firmware 10.2 specific mappings */
492static struct wmi_cmd_map wmi_10_2_cmd_map = {
493 .init_cmdid = WMI_10_2_INIT_CMDID,
494 .start_scan_cmdid = WMI_10_2_START_SCAN_CMDID,
495 .stop_scan_cmdid = WMI_10_2_STOP_SCAN_CMDID,
496 .scan_chan_list_cmdid = WMI_10_2_SCAN_CHAN_LIST_CMDID,
497 .scan_sch_prio_tbl_cmdid = WMI_CMD_UNSUPPORTED,
498 .pdev_set_regdomain_cmdid = WMI_10_2_PDEV_SET_REGDOMAIN_CMDID,
499 .pdev_set_channel_cmdid = WMI_10_2_PDEV_SET_CHANNEL_CMDID,
500 .pdev_set_param_cmdid = WMI_10_2_PDEV_SET_PARAM_CMDID,
501 .pdev_pktlog_enable_cmdid = WMI_10_2_PDEV_PKTLOG_ENABLE_CMDID,
502 .pdev_pktlog_disable_cmdid = WMI_10_2_PDEV_PKTLOG_DISABLE_CMDID,
503 .pdev_set_wmm_params_cmdid = WMI_10_2_PDEV_SET_WMM_PARAMS_CMDID,
504 .pdev_set_ht_cap_ie_cmdid = WMI_10_2_PDEV_SET_HT_CAP_IE_CMDID,
505 .pdev_set_vht_cap_ie_cmdid = WMI_10_2_PDEV_SET_VHT_CAP_IE_CMDID,
506 .pdev_set_quiet_mode_cmdid = WMI_10_2_PDEV_SET_QUIET_MODE_CMDID,
507 .pdev_green_ap_ps_enable_cmdid = WMI_10_2_PDEV_GREEN_AP_PS_ENABLE_CMDID,
508 .pdev_get_tpc_config_cmdid = WMI_10_2_PDEV_GET_TPC_CONFIG_CMDID,
509 .pdev_set_base_macaddr_cmdid = WMI_10_2_PDEV_SET_BASE_MACADDR_CMDID,
510 .vdev_create_cmdid = WMI_10_2_VDEV_CREATE_CMDID,
511 .vdev_delete_cmdid = WMI_10_2_VDEV_DELETE_CMDID,
512 .vdev_start_request_cmdid = WMI_10_2_VDEV_START_REQUEST_CMDID,
513 .vdev_restart_request_cmdid = WMI_10_2_VDEV_RESTART_REQUEST_CMDID,
514 .vdev_up_cmdid = WMI_10_2_VDEV_UP_CMDID,
515 .vdev_stop_cmdid = WMI_10_2_VDEV_STOP_CMDID,
516 .vdev_down_cmdid = WMI_10_2_VDEV_DOWN_CMDID,
517 .vdev_set_param_cmdid = WMI_10_2_VDEV_SET_PARAM_CMDID,
518 .vdev_install_key_cmdid = WMI_10_2_VDEV_INSTALL_KEY_CMDID,
519 .peer_create_cmdid = WMI_10_2_PEER_CREATE_CMDID,
520 .peer_delete_cmdid = WMI_10_2_PEER_DELETE_CMDID,
521 .peer_flush_tids_cmdid = WMI_10_2_PEER_FLUSH_TIDS_CMDID,
522 .peer_set_param_cmdid = WMI_10_2_PEER_SET_PARAM_CMDID,
523 .peer_assoc_cmdid = WMI_10_2_PEER_ASSOC_CMDID,
524 .peer_add_wds_entry_cmdid = WMI_10_2_PEER_ADD_WDS_ENTRY_CMDID,
525 .peer_remove_wds_entry_cmdid = WMI_10_2_PEER_REMOVE_WDS_ENTRY_CMDID,
526 .peer_mcast_group_cmdid = WMI_10_2_PEER_MCAST_GROUP_CMDID,
527 .bcn_tx_cmdid = WMI_10_2_BCN_TX_CMDID,
528 .pdev_send_bcn_cmdid = WMI_10_2_PDEV_SEND_BCN_CMDID,
529 .bcn_tmpl_cmdid = WMI_CMD_UNSUPPORTED,
530 .bcn_filter_rx_cmdid = WMI_10_2_BCN_FILTER_RX_CMDID,
531 .prb_req_filter_rx_cmdid = WMI_10_2_PRB_REQ_FILTER_RX_CMDID,
532 .mgmt_tx_cmdid = WMI_10_2_MGMT_TX_CMDID,
533 .prb_tmpl_cmdid = WMI_CMD_UNSUPPORTED,
534 .addba_clear_resp_cmdid = WMI_10_2_ADDBA_CLEAR_RESP_CMDID,
535 .addba_send_cmdid = WMI_10_2_ADDBA_SEND_CMDID,
536 .addba_status_cmdid = WMI_10_2_ADDBA_STATUS_CMDID,
537 .delba_send_cmdid = WMI_10_2_DELBA_SEND_CMDID,
538 .addba_set_resp_cmdid = WMI_10_2_ADDBA_SET_RESP_CMDID,
539 .send_singleamsdu_cmdid = WMI_10_2_SEND_SINGLEAMSDU_CMDID,
540 .sta_powersave_mode_cmdid = WMI_10_2_STA_POWERSAVE_MODE_CMDID,
541 .sta_powersave_param_cmdid = WMI_10_2_STA_POWERSAVE_PARAM_CMDID,
542 .sta_mimo_ps_mode_cmdid = WMI_10_2_STA_MIMO_PS_MODE_CMDID,
543 .pdev_dfs_enable_cmdid = WMI_10_2_PDEV_DFS_ENABLE_CMDID,
544 .pdev_dfs_disable_cmdid = WMI_10_2_PDEV_DFS_DISABLE_CMDID,
545 .roam_scan_mode = WMI_10_2_ROAM_SCAN_MODE,
546 .roam_scan_rssi_threshold = WMI_10_2_ROAM_SCAN_RSSI_THRESHOLD,
547 .roam_scan_period = WMI_10_2_ROAM_SCAN_PERIOD,
548 .roam_scan_rssi_change_threshold =
549 WMI_10_2_ROAM_SCAN_RSSI_CHANGE_THRESHOLD,
550 .roam_ap_profile = WMI_10_2_ROAM_AP_PROFILE,
551 .ofl_scan_add_ap_profile = WMI_10_2_OFL_SCAN_ADD_AP_PROFILE,
552 .ofl_scan_remove_ap_profile = WMI_10_2_OFL_SCAN_REMOVE_AP_PROFILE,
553 .ofl_scan_period = WMI_10_2_OFL_SCAN_PERIOD,
554 .p2p_dev_set_device_info = WMI_10_2_P2P_DEV_SET_DEVICE_INFO,
555 .p2p_dev_set_discoverability = WMI_10_2_P2P_DEV_SET_DISCOVERABILITY,
556 .p2p_go_set_beacon_ie = WMI_10_2_P2P_GO_SET_BEACON_IE,
557 .p2p_go_set_probe_resp_ie = WMI_10_2_P2P_GO_SET_PROBE_RESP_IE,
558 .p2p_set_vendor_ie_data_cmdid = WMI_CMD_UNSUPPORTED,
559 .ap_ps_peer_param_cmdid = WMI_10_2_AP_PS_PEER_PARAM_CMDID,
560 .ap_ps_peer_uapsd_coex_cmdid = WMI_CMD_UNSUPPORTED,
561 .peer_rate_retry_sched_cmdid = WMI_10_2_PEER_RATE_RETRY_SCHED_CMDID,
562 .wlan_profile_trigger_cmdid = WMI_10_2_WLAN_PROFILE_TRIGGER_CMDID,
563 .wlan_profile_set_hist_intvl_cmdid =
564 WMI_10_2_WLAN_PROFILE_SET_HIST_INTVL_CMDID,
565 .wlan_profile_get_profile_data_cmdid =
566 WMI_10_2_WLAN_PROFILE_GET_PROFILE_DATA_CMDID,
567 .wlan_profile_enable_profile_id_cmdid =
568 WMI_10_2_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID,
569 .wlan_profile_list_profile_id_cmdid =
570 WMI_10_2_WLAN_PROFILE_LIST_PROFILE_ID_CMDID,
571 .pdev_suspend_cmdid = WMI_10_2_PDEV_SUSPEND_CMDID,
572 .pdev_resume_cmdid = WMI_10_2_PDEV_RESUME_CMDID,
573 .add_bcn_filter_cmdid = WMI_10_2_ADD_BCN_FILTER_CMDID,
574 .rmv_bcn_filter_cmdid = WMI_10_2_RMV_BCN_FILTER_CMDID,
575 .wow_add_wake_pattern_cmdid = WMI_10_2_WOW_ADD_WAKE_PATTERN_CMDID,
576 .wow_del_wake_pattern_cmdid = WMI_10_2_WOW_DEL_WAKE_PATTERN_CMDID,
577 .wow_enable_disable_wake_event_cmdid =
578 WMI_10_2_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID,
579 .wow_enable_cmdid = WMI_10_2_WOW_ENABLE_CMDID,
580 .wow_hostwakeup_from_sleep_cmdid =
581 WMI_10_2_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID,
582 .rtt_measreq_cmdid = WMI_10_2_RTT_MEASREQ_CMDID,
583 .rtt_tsf_cmdid = WMI_10_2_RTT_TSF_CMDID,
584 .vdev_spectral_scan_configure_cmdid =
585 WMI_10_2_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID,
586 .vdev_spectral_scan_enable_cmdid =
587 WMI_10_2_VDEV_SPECTRAL_SCAN_ENABLE_CMDID,
588 .request_stats_cmdid = WMI_10_2_REQUEST_STATS_CMDID,
589 .set_arp_ns_offload_cmdid = WMI_CMD_UNSUPPORTED,
590 .network_list_offload_config_cmdid = WMI_CMD_UNSUPPORTED,
591 .gtk_offload_cmdid = WMI_CMD_UNSUPPORTED,
592 .csa_offload_enable_cmdid = WMI_CMD_UNSUPPORTED,
593 .csa_offload_chanswitch_cmdid = WMI_CMD_UNSUPPORTED,
594 .chatter_set_mode_cmdid = WMI_CMD_UNSUPPORTED,
595 .peer_tid_addba_cmdid = WMI_CMD_UNSUPPORTED,
596 .peer_tid_delba_cmdid = WMI_CMD_UNSUPPORTED,
597 .sta_dtim_ps_method_cmdid = WMI_CMD_UNSUPPORTED,
598 .sta_uapsd_auto_trig_cmdid = WMI_CMD_UNSUPPORTED,
599 .sta_keepalive_cmd = WMI_CMD_UNSUPPORTED,
600 .echo_cmdid = WMI_10_2_ECHO_CMDID,
601 .pdev_utf_cmdid = WMI_10_2_PDEV_UTF_CMDID,
602 .dbglog_cfg_cmdid = WMI_10_2_DBGLOG_CFG_CMDID,
603 .pdev_qvit_cmdid = WMI_10_2_PDEV_QVIT_CMDID,
604 .pdev_ftm_intg_cmdid = WMI_CMD_UNSUPPORTED,
605 .vdev_set_keepalive_cmdid = WMI_CMD_UNSUPPORTED,
606 .vdev_get_keepalive_cmdid = WMI_CMD_UNSUPPORTED,
607 .force_fw_hang_cmdid = WMI_CMD_UNSUPPORTED,
608 .gpio_config_cmdid = WMI_10_2_GPIO_CONFIG_CMDID,
609 .gpio_output_cmdid = WMI_10_2_GPIO_OUTPUT_CMDID,
610};
611
2d66721c
MK		 612static void
613ath10k_wmi_put_wmi_channel(struct wmi_channel *ch,
614 const struct wmi_channel_arg *arg)
615{
616 u32 flags = 0;
617
618 memset(ch, 0, sizeof(*ch));
619
620 if (arg->passive)
621 flags |= WMI_CHAN_FLAG_PASSIVE;
622 if (arg->allow_ibss)
623 flags |= WMI_CHAN_FLAG_ADHOC_ALLOWED;
624 if (arg->allow_ht)
625 flags |= WMI_CHAN_FLAG_ALLOW_HT;
626 if (arg->allow_vht)
627 flags |= WMI_CHAN_FLAG_ALLOW_VHT;
628 if (arg->ht40plus)
629 flags |= WMI_CHAN_FLAG_HT40_PLUS;
630 if (arg->chan_radar)
631 flags |= WMI_CHAN_FLAG_DFS;
632
633 ch->mhz = __cpu_to_le32(arg->freq);
634 ch->band_center_freq1 = __cpu_to_le32(arg->band_center_freq1);
635 ch->band_center_freq2 = 0;
636 ch->min_power = arg->min_power;
637 ch->max_power = arg->max_power;
638 ch->reg_power = arg->max_reg_power;
639 ch->antenna_max = arg->max_antenna_gain;
640
641 /* mode & flags share storage */
642 ch->mode = arg->mode;
643 ch->flags |= __cpu_to_le32(flags);
644}
645
5e3dd157
KV		 646int ath10k_wmi_wait_for_service_ready(struct ath10k *ar)
647{
648 int ret;
af762c0b 649
5e3dd157
KV		 650 ret = wait_for_completion_timeout(&ar->wmi.service_ready,
651 WMI_SERVICE_READY_TIMEOUT_HZ);
652 return ret;
653}
654
655int ath10k_wmi_wait_for_unified_ready(struct ath10k *ar)
656{
657 int ret;
af762c0b 658
5e3dd157
KV		 659 ret = wait_for_completion_timeout(&ar->wmi.unified_ready,
660 WMI_UNIFIED_READY_TIMEOUT_HZ);
661 return ret;
662}
663
666a73f3 664struct sk_buff *ath10k_wmi_alloc_skb(struct ath10k *ar, u32 len)
5e3dd157
KV		 665{
666 struct sk_buff *skb;
667 u32 round_len = roundup(len, 4);
668
7aa7a72a 669 skb = ath10k_htc_alloc_skb(ar, WMI_SKB_HEADROOM + round_len);
5e3dd157
KV		 670 if (!skb)
671 return NULL;
672
673 skb_reserve(skb, WMI_SKB_HEADROOM);
674 if (!IS_ALIGNED((unsigned long)skb->data, 4))
7aa7a72a 675 ath10k_warn(ar, "Unaligned WMI skb\n");
5e3dd157
KV		 676
677 skb_put(skb, round_len);
678 memset(skb->data, 0, round_len);
679
680 return skb;
681}
682
683static void ath10k_wmi_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb)
684{
685 dev_kfree_skb(skb);
5e3dd157
KV		 686}
687
be8b3943 688static int ath10k_wmi_cmd_send_nowait(struct ath10k *ar, struct sk_buff *skb,
ce42870e 689 u32 cmd_id)
5e3dd157
KV		 690{
691 struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(skb);
692 struct wmi_cmd_hdr *cmd_hdr;
be8b3943 693 int ret;
5e3dd157
KV		 694 u32 cmd = 0;
695
696 if (skb_push(skb, sizeof(struct wmi_cmd_hdr)) == NULL)
697 return -ENOMEM;
698
699 cmd |= SM(cmd_id, WMI_CMD_HDR_CMD_ID);
700
701 cmd_hdr = (struct wmi_cmd_hdr *)skb->data;
702 cmd_hdr->cmd_id = __cpu_to_le32(cmd);
703
5e3dd157 704 memset(skb_cb, 0, sizeof(*skb_cb));
be8b3943 705 ret = ath10k_htc_send(&ar->htc, ar->wmi.eid, skb);
d35a6c18 706 trace_ath10k_wmi_cmd(ar, cmd_id, skb->data, skb->len, ret);
5e3dd157 707
be8b3943
MK		 708 if (ret)
709 goto err_pull;
5e3dd157 710
be8b3943
MK		 711 return 0;
712
713err_pull:
714 skb_pull(skb, sizeof(struct wmi_cmd_hdr));
715 return ret;
716}
717
ed54388a
MK		 718static void ath10k_wmi_tx_beacon_nowait(struct ath10k_vif *arvif)
719{
ed54388a
MK		 720 int ret;
721
722 lockdep_assert_held(&arvif->ar->data_lock);
723
724 if (arvif->beacon == NULL)
725 return;
726
748afc47
MK		 727 if (arvif->beacon_sent)
728 return;
ed54388a 729
748afc47 730 ret = ath10k_wmi_beacon_send_ref_nowait(arvif);
ed54388a
MK		 731 if (ret)
732 return;
733
748afc47
MK		 734 /* We need to retain the arvif->beacon reference for DMA unmapping and
735 * freeing the skbuff later. */
736 arvif->beacon_sent = true;
ed54388a
MK		 737}
738
739static void ath10k_wmi_tx_beacons_iter(void *data, u8 *mac,
740 struct ieee80211_vif *vif)
741{
742 struct ath10k_vif *arvif = ath10k_vif_to_arvif(vif);
743
744 ath10k_wmi_tx_beacon_nowait(arvif);
745}
746
747static void ath10k_wmi_tx_beacons_nowait(struct ath10k *ar)
748{
749 spin_lock_bh(&ar->data_lock);
750 ieee80211_iterate_active_interfaces_atomic(ar->hw,
751 IEEE80211_IFACE_ITER_NORMAL,
752 ath10k_wmi_tx_beacons_iter,
753 NULL);
754 spin_unlock_bh(&ar->data_lock);
755}
756
12acbc43 757static void ath10k_wmi_op_ep_tx_credits(struct ath10k *ar)
be8b3943 758{
ed54388a
MK		 759 /* try to send pending beacons first. they take priority */
760 ath10k_wmi_tx_beacons_nowait(ar);
761
be8b3943
MK		 762 wake_up(&ar->wmi.tx_credits_wq);
763}
764
666a73f3 765int ath10k_wmi_cmd_send(struct ath10k *ar, struct sk_buff *skb, u32 cmd_id)
be8b3943 766{
34957b25 767 int ret = -EOPNOTSUPP;
be8b3943 768
56b84287
KV		 769 might_sleep();
770
34957b25 771 if (cmd_id == WMI_CMD_UNSUPPORTED) {
7aa7a72a 772 ath10k_warn(ar, "wmi command %d is not supported by firmware\n",
55321559
BM		 773 cmd_id);
774 return ret;
775 }
be8b3943
MK		 776
777 wait_event_timeout(ar->wmi.tx_credits_wq, ({
ed54388a
MK		 778 /* try to send pending beacons first. they take priority */
779 ath10k_wmi_tx_beacons_nowait(ar);
780
be8b3943 781 ret = ath10k_wmi_cmd_send_nowait(ar, skb, cmd_id);
7962b0d8
MK		 782
783 if (ret && test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags))
784 ret = -ESHUTDOWN;
785
be8b3943
MK		 786 (ret != -EAGAIN);
787 }), 3*HZ);
788
789 if (ret)
5e3dd157 790 dev_kfree_skb_any(skb);
5e3dd157 791
be8b3943 792 return ret;
5e3dd157
KV		 793}
794
5e00d31a
BM		 795int ath10k_wmi_mgmt_tx(struct ath10k *ar, struct sk_buff *skb)
796{
797 int ret = 0;
798 struct wmi_mgmt_tx_cmd *cmd;
799 struct ieee80211_hdr *hdr;
800 struct sk_buff *wmi_skb;
801 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
802 int len;
eeab266c 803 u32 buf_len = skb->len;
5e00d31a
BM		 804 u16 fc;
805
806 hdr = (struct ieee80211_hdr *)skb->data;
807 fc = le16_to_cpu(hdr->frame_control);
808
809 if (WARN_ON_ONCE(!ieee80211_is_mgmt(hdr->frame_control)))
810 return -EINVAL;
811
812 len = sizeof(cmd->hdr) + skb->len;
eeab266c
MK		 813
814 if ((ieee80211_is_action(hdr->frame_control) ||
815 ieee80211_is_deauth(hdr->frame_control) ||
816 ieee80211_is_disassoc(hdr->frame_control)) &&
817 ieee80211_has_protected(hdr->frame_control)) {
818 len += IEEE80211_CCMP_MIC_LEN;
819 buf_len += IEEE80211_CCMP_MIC_LEN;
820 }
821
5e00d31a
BM		 822 len = round_up(len, 4);
823
7aa7a72a 824 wmi_skb = ath10k_wmi_alloc_skb(ar, len);
5e00d31a
BM		 825 if (!wmi_skb)
826 return -ENOMEM;
827
828 cmd = (struct wmi_mgmt_tx_cmd *)wmi_skb->data;
829
830 cmd->hdr.vdev_id = __cpu_to_le32(ATH10K_SKB_CB(skb)->vdev_id);
831 cmd->hdr.tx_rate = 0;
832 cmd->hdr.tx_power = 0;
eeab266c 833 cmd->hdr.buf_len = __cpu_to_le32(buf_len);
5e00d31a 834
b25f32cb 835 ether_addr_copy(cmd->hdr.peer_macaddr.addr, ieee80211_get_DA(hdr));
5e00d31a
BM		 836 memcpy(cmd->buf, skb->data, skb->len);
837
7aa7a72a 838 ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi mgmt tx skb %p len %d ftype %02x stype %02x\n",
5e00d31a
BM		 839 wmi_skb, wmi_skb->len, fc & IEEE80211_FCTL_FTYPE,
840 fc & IEEE80211_FCTL_STYPE);
5ce8e7fd
RM		 841 trace_ath10k_tx_hdr(ar, skb->data, skb->len);
842 trace_ath10k_tx_payload(ar, skb->data, skb->len);
5e00d31a
BM		 843
844 /* Send the management frame buffer to the target */
845 ret = ath10k_wmi_cmd_send(ar, wmi_skb, ar->wmi.cmd->mgmt_tx_cmdid);
5fb5e41f 846 if (ret)
5e00d31a 847 return ret;
5e00d31a
BM		 848
849 /* TODO: report tx status to mac80211 - temporary just ACK */
850 info->flags |= IEEE80211_TX_STAT_ACK;
851 ieee80211_tx_status_irqsafe(ar->hw, skb);
852
853 return ret;
854}
855
5c81c7fd
MK		 856static void ath10k_wmi_event_scan_started(struct ath10k *ar)
857{
858 lockdep_assert_held(&ar->data_lock);
859
860 switch (ar->scan.state) {
861 case ATH10K_SCAN_IDLE:
862 case ATH10K_SCAN_RUNNING:
863 case ATH10K_SCAN_ABORTING:
7aa7a72a 864 ath10k_warn(ar, "received scan started event in an invalid scan state: %s (%d)\n",
5c81c7fd
MK		 865 ath10k_scan_state_str(ar->scan.state),
866 ar->scan.state);
867 break;
868 case ATH10K_SCAN_STARTING:
869 ar->scan.state = ATH10K_SCAN_RUNNING;
870
871 if (ar->scan.is_roc)
872 ieee80211_ready_on_channel(ar->hw);
873
874 complete(&ar->scan.started);
875 break;
876 }
877}
878
879static void ath10k_wmi_event_scan_completed(struct ath10k *ar)
880{
881 lockdep_assert_held(&ar->data_lock);
882
883 switch (ar->scan.state) {
884 case ATH10K_SCAN_IDLE:
885 case ATH10K_SCAN_STARTING:
886 /* One suspected reason scan can be completed while starting is
887 * if firmware fails to deliver all scan events to the host,
888 * e.g. when transport pipe is full. This has been observed
889 * with spectral scan phyerr events starving wmi transport
890 * pipe. In such case the "scan completed" event should be (and
891 * is) ignored by the host as it may be just firmware's scan
892 * state machine recovering.
893 */
7aa7a72a 894 ath10k_warn(ar, "received scan completed event in an invalid scan state: %s (%d)\n",
5c81c7fd
MK		 895 ath10k_scan_state_str(ar->scan.state),
896 ar->scan.state);
897 break;
898 case ATH10K_SCAN_RUNNING:
899 case ATH10K_SCAN_ABORTING:
900 __ath10k_scan_finish(ar);
901 break;
902 }
903}
904
905static void ath10k_wmi_event_scan_bss_chan(struct ath10k *ar)
906{
907 lockdep_assert_held(&ar->data_lock);
908
909 switch (ar->scan.state) {
910 case ATH10K_SCAN_IDLE:
911 case ATH10K_SCAN_STARTING:
7aa7a72a 912 ath10k_warn(ar, "received scan bss chan event in an invalid scan state: %s (%d)\n",
5c81c7fd
MK		 913 ath10k_scan_state_str(ar->scan.state),
914 ar->scan.state);
915 break;
916 case ATH10K_SCAN_RUNNING:
917 case ATH10K_SCAN_ABORTING:
918 ar->scan_channel = NULL;
919 break;
920 }
921}
922
923static void ath10k_wmi_event_scan_foreign_chan(struct ath10k *ar, u32 freq)
924{
925 lockdep_assert_held(&ar->data_lock);
926
927 switch (ar->scan.state) {
928 case ATH10K_SCAN_IDLE:
929 case ATH10K_SCAN_STARTING:
7aa7a72a 930 ath10k_warn(ar, "received scan foreign chan event in an invalid scan state: %s (%d)\n",
5c81c7fd
MK		 931 ath10k_scan_state_str(ar->scan.state),
932 ar->scan.state);
933 break;
934 case ATH10K_SCAN_RUNNING:
935 case ATH10K_SCAN_ABORTING:
936 ar->scan_channel = ieee80211_get_channel(ar->hw->wiphy, freq);
937
938 if (ar->scan.is_roc && ar->scan.roc_freq == freq)
939 complete(&ar->scan.on_channel);
940 break;
941 }
942}
943
9ff8b724
MK		 944static const char *
945ath10k_wmi_event_scan_type_str(enum wmi_scan_event_type type,
946 enum wmi_scan_completion_reason reason)
947{
948 switch (type) {
949 case WMI_SCAN_EVENT_STARTED:
950 return "started";
951 case WMI_SCAN_EVENT_COMPLETED:
952 switch (reason) {
953 case WMI_SCAN_REASON_COMPLETED:
954 return "completed";
955 case WMI_SCAN_REASON_CANCELLED:
956 return "completed [cancelled]";
957 case WMI_SCAN_REASON_PREEMPTED:
958 return "completed [preempted]";
959 case WMI_SCAN_REASON_TIMEDOUT:
960 return "completed [timedout]";
961 case WMI_SCAN_REASON_MAX:
962 break;
963 }
964 return "completed [unknown]";
965 case WMI_SCAN_EVENT_BSS_CHANNEL:
966 return "bss channel";
967 case WMI_SCAN_EVENT_FOREIGN_CHANNEL:
968 return "foreign channel";
969 case WMI_SCAN_EVENT_DEQUEUED:
970 return "dequeued";
971 case WMI_SCAN_EVENT_PREEMPTED:
972 return "preempted";
973 case WMI_SCAN_EVENT_START_FAILED:
974 return "start failed";
975 default:
976 return "unknown";
977 }
978}
979
32653cf1
MK		 980static int ath10k_wmi_pull_scan_ev(struct sk_buff *skb,
981 struct wmi_scan_ev_arg *arg)
982{
983 struct wmi_scan_event *ev = (void *)skb->data;
984
985 if (skb->len < sizeof(*ev))
986 return -EPROTO;
987
988 skb_pull(skb, sizeof(*ev));
989 arg->event_type = ev->event_type;
990 arg->reason = ev->reason;
991 arg->channel_freq = ev->channel_freq;
992 arg->scan_req_id = ev->scan_req_id;
993 arg->scan_id = ev->scan_id;
994 arg->vdev_id = ev->vdev_id;
995
996 return 0;
997}
998
5e3dd157
KV		 999static int ath10k_wmi_event_scan(struct ath10k *ar, struct sk_buff *skb)
1000{
32653cf1 1001 struct wmi_scan_ev_arg arg = {};
5e3dd157
KV		 1002 enum wmi_scan_event_type event_type;
1003 enum wmi_scan_completion_reason reason;
1004 u32 freq;
1005 u32 req_id;
1006 u32 scan_id;
1007 u32 vdev_id;
32653cf1 1008 int ret;
5e3dd157 1009
32653cf1
MK		 1010 ret = ath10k_wmi_pull_scan_ev(skb, &arg);
1011 if (ret) {
1012 ath10k_warn(ar, "failed to parse scan event: %d\n", ret);
1013 return ret;
1014 }
1015
1016 event_type = __le32_to_cpu(arg.event_type);
1017 reason = __le32_to_cpu(arg.reason);
1018 freq = __le32_to_cpu(arg.channel_freq);
1019 req_id = __le32_to_cpu(arg.scan_req_id);
1020 scan_id = __le32_to_cpu(arg.scan_id);
1021 vdev_id = __le32_to_cpu(arg.vdev_id);
5e3dd157 1022
5c81c7fd
MK		 1023 spin_lock_bh(&ar->data_lock);
1024
7aa7a72a 1025 ath10k_dbg(ar, ATH10K_DBG_WMI,
5c81c7fd 1026 "scan event %s type %d reason %d freq %d req_id %d scan_id %d vdev_id %d state %s (%d)\n",
9ff8b724 1027 ath10k_wmi_event_scan_type_str(event_type, reason),
5c81c7fd
MK		 1028 event_type, reason, freq, req_id, scan_id, vdev_id,
1029 ath10k_scan_state_str(ar->scan.state), ar->scan.state);
5e3dd157
KV		 1030
1031 switch (event_type) {
1032 case WMI_SCAN_EVENT_STARTED:
5c81c7fd 1033 ath10k_wmi_event_scan_started(ar);
5e3dd157
KV		 1034 break;
1035 case WMI_SCAN_EVENT_COMPLETED:
5c81c7fd 1036 ath10k_wmi_event_scan_completed(ar);
5e3dd157
KV		 1037 break;
1038 case WMI_SCAN_EVENT_BSS_CHANNEL:
5c81c7fd 1039 ath10k_wmi_event_scan_bss_chan(ar);
5e3dd157
KV		 1040 break;
1041 case WMI_SCAN_EVENT_FOREIGN_CHANNEL:
5c81c7fd
MK		 1042 ath10k_wmi_event_scan_foreign_chan(ar, freq);
1043 break;
1044 case WMI_SCAN_EVENT_START_FAILED:
7aa7a72a 1045 ath10k_warn(ar, "received scan start failure event\n");
5e3dd157
KV		 1046 break;
1047 case WMI_SCAN_EVENT_DEQUEUED:
5e3dd157 1048 case WMI_SCAN_EVENT_PREEMPTED:
5e3dd157
KV		 1049 default:
1050 break;
1051 }
1052
1053 spin_unlock_bh(&ar->data_lock);
1054 return 0;
1055}
1056
1057static inline enum ieee80211_band phy_mode_to_band(u32 phy_mode)
1058{
1059 enum ieee80211_band band;
1060
1061 switch (phy_mode) {
1062 case MODE_11A:
1063 case MODE_11NA_HT20:
1064 case MODE_11NA_HT40:
1065 case MODE_11AC_VHT20:
1066 case MODE_11AC_VHT40:
1067 case MODE_11AC_VHT80:
1068 band = IEEE80211_BAND_5GHZ;
1069 break;
1070 case MODE_11G:
1071 case MODE_11B:
1072 case MODE_11GONLY:
1073 case MODE_11NG_HT20:
1074 case MODE_11NG_HT40:
1075 case MODE_11AC_VHT20_2G:
1076 case MODE_11AC_VHT40_2G:
1077 case MODE_11AC_VHT80_2G:
1078 default:
1079 band = IEEE80211_BAND_2GHZ;
1080 }
1081
1082 return band;
1083}
1084
1085static inline u8 get_rate_idx(u32 rate, enum ieee80211_band band)
1086{
1087 u8 rate_idx = 0;
1088
1089 /* rate in Kbps */
1090 switch (rate) {
1091 case 1000:
1092 rate_idx = 0;
1093 break;
1094 case 2000:
1095 rate_idx = 1;
1096 break;
1097 case 5500:
1098 rate_idx = 2;
1099 break;
1100 case 11000:
1101 rate_idx = 3;
1102 break;
1103 case 6000:
1104 rate_idx = 4;
1105 break;
1106 case 9000:
1107 rate_idx = 5;
1108 break;
1109 case 12000:
1110 rate_idx = 6;
1111 break;
1112 case 18000:
1113 rate_idx = 7;
1114 break;
1115 case 24000:
1116 rate_idx = 8;
1117 break;
1118 case 36000:
1119 rate_idx = 9;
1120 break;
1121 case 48000:
1122 rate_idx = 10;
1123 break;
1124 case 54000:
1125 rate_idx = 11;
1126 break;
1127 default:
1128 break;
1129 }
1130
1131 if (band == IEEE80211_BAND_5GHZ) {
1132 if (rate_idx > 3)
1133 /* Omit CCK rates */
1134 rate_idx -= 4;
1135 else
1136 rate_idx = 0;
1137 }
1138
1139 return rate_idx;
1140}
1141
504f6cdf
SM		 1142/* If keys are configured, HW decrypts all frames
1143 * with protected bit set. Mark such frames as decrypted.
1144 */
1145static void ath10k_wmi_handle_wep_reauth(struct ath10k *ar,
1146 struct sk_buff *skb,
1147 struct ieee80211_rx_status *status)
1148{
1149 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1150 unsigned int hdrlen;
1151 bool peer_key;
1152 u8 *addr, keyidx;
1153
1154 if (!ieee80211_is_auth(hdr->frame_control) ||
1155 !ieee80211_has_protected(hdr->frame_control))
1156 return;
1157
1158 hdrlen = ieee80211_hdrlen(hdr->frame_control);
1159 if (skb->len < (hdrlen + IEEE80211_WEP_IV_LEN))
1160 return;
1161
1162 keyidx = skb->data[hdrlen + (IEEE80211_WEP_IV_LEN - 1)] >> WEP_KEYID_SHIFT;
1163 addr = ieee80211_get_SA(hdr);
1164
1165 spin_lock_bh(&ar->data_lock);
1166 peer_key = ath10k_mac_is_peer_wep_key_set(ar, addr, keyidx);
1167 spin_unlock_bh(&ar->data_lock);
1168
1169 if (peer_key) {
1170 ath10k_dbg(ar, ATH10K_DBG_MAC,
1171 "mac wep key present for peer %pM\n", addr);
1172 status->flag |= RX_FLAG_DECRYPTED;
1173 }
1174}
1175
32653cf1
MK		 1176static int ath10k_wmi_pull_mgmt_rx_ev(struct sk_buff *skb,
1177 struct wmi_mgmt_rx_ev_arg *arg,
1178 struct ath10k *ar)
5e3dd157 1179{
0d9b0438
MK		 1180 struct wmi_mgmt_rx_event_v1 *ev_v1;
1181 struct wmi_mgmt_rx_event_v2 *ev_v2;
1182 struct wmi_mgmt_rx_hdr_v1 *ev_hdr;
32653cf1
MK		 1183 size_t pull_len;
1184 u32 msdu_len;
1185
1186 if (test_bit(ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX, ar->fw_features)) {
1187 ev_v2 = (struct wmi_mgmt_rx_event_v2 *)skb->data;
1188 ev_hdr = &ev_v2->hdr.v1;
1189 pull_len = sizeof(*ev_v2);
1190 } else {
1191 ev_v1 = (struct wmi_mgmt_rx_event_v1 *)skb->data;
1192 ev_hdr = &ev_v1->hdr;
1193 pull_len = sizeof(*ev_v1);
1194 }
1195
1196 if (skb->len < pull_len)
1197 return -EPROTO;
1198
1199 skb_pull(skb, pull_len);
1200 arg->channel = ev_hdr->channel;
1201 arg->buf_len = ev_hdr->buf_len;
1202 arg->status = ev_hdr->status;
1203 arg->snr = ev_hdr->snr;
1204 arg->phy_mode = ev_hdr->phy_mode;
1205 arg->rate = ev_hdr->rate;
1206
1207 msdu_len = __le32_to_cpu(arg->buf_len);
1208 if (skb->len < msdu_len)
1209 return -EPROTO;
1210
1211 /* the WMI buffer might've ended up being padded to 4 bytes due to HTC
1212 * trailer with credit update. Trim the excess garbage.
1213 */
1214 skb_trim(skb, msdu_len);
1215
1216 return 0;
1217}
1218
1219static int ath10k_wmi_event_mgmt_rx(struct ath10k *ar, struct sk_buff *skb)
1220{
1221 struct wmi_mgmt_rx_ev_arg arg = {};
5e3dd157
KV		 1222 struct ieee80211_rx_status *status = IEEE80211_SKB_RXCB(skb);
1223 struct ieee80211_hdr *hdr;
1224 u32 rx_status;
1225 u32 channel;
1226 u32 phy_mode;
1227 u32 snr;
1228 u32 rate;
1229 u32 buf_len;
1230 u16 fc;
32653cf1 1231 int ret;
0d9b0438 1232
32653cf1
MK		 1233 ret = ath10k_wmi_pull_mgmt_rx_ev(skb, &arg, ar);
1234 if (ret) {
1235 ath10k_warn(ar, "failed to parse mgmt rx event: %d\n", ret);
1236 return ret;
0d9b0438 1237 }
5e3dd157 1238
32653cf1
MK		 1239 channel = __le32_to_cpu(arg.channel);
1240 buf_len = __le32_to_cpu(arg.buf_len);
1241 rx_status = __le32_to_cpu(arg.status);
1242 snr = __le32_to_cpu(arg.snr);
1243 phy_mode = __le32_to_cpu(arg.phy_mode);
1244 rate = __le32_to_cpu(arg.rate);
5e3dd157
KV		 1245
1246 memset(status, 0, sizeof(*status));
1247
7aa7a72a 1248 ath10k_dbg(ar, ATH10K_DBG_MGMT,
5e3dd157
KV		 1249 "event mgmt rx status %08x\n", rx_status);
1250
e8a50f8b
MP		 1251 if (test_bit(ATH10K_CAC_RUNNING, &ar->dev_flags)) {
1252 dev_kfree_skb(skb);
1253 return 0;
1254 }
1255
5e3dd157
KV		 1256 if (rx_status & WMI_RX_STATUS_ERR_DECRYPT) {
1257 dev_kfree_skb(skb);
1258 return 0;
1259 }
1260
1261 if (rx_status & WMI_RX_STATUS_ERR_KEY_CACHE_MISS) {
1262 dev_kfree_skb(skb);
1263 return 0;
1264 }
1265
d67d0a02
MK		 1266 if (rx_status & WMI_RX_STATUS_ERR_CRC) {
1267 dev_kfree_skb(skb);
1268 return 0;
1269 }
1270
5e3dd157
KV		 1271 if (rx_status & WMI_RX_STATUS_ERR_MIC)
1272 status->flag |= RX_FLAG_MMIC_ERROR;
1273
21040bf9 1274 /* Hardware can Rx CCK rates on 5GHz. In that case phy_mode is set to
453cdb61 1275 * MODE_11B. This means phy_mode is not a reliable source for the band
21040bf9
MK		 1276 * of mgmt rx.
1277 */
1278 if (channel >= 1 && channel <= 14) {
1279 status->band = IEEE80211_BAND_2GHZ;
1280 } else if (channel >= 36 && channel <= 165) {
1281 status->band = IEEE80211_BAND_5GHZ;
453cdb61 1282 } else {
21040bf9
MK		 1283 /* Shouldn't happen unless list of advertised channels to
1284 * mac80211 has been changed.
1285 */
1286 WARN_ON_ONCE(1);
1287 dev_kfree_skb(skb);
1288 return 0;
453cdb61
MK		 1289 }
1290
21040bf9
MK		 1291 if (phy_mode == MODE_11B && status->band == IEEE80211_BAND_5GHZ)
1292 ath10k_dbg(ar, ATH10K_DBG_MGMT, "wmi mgmt rx 11b (CCK) on 5GHz\n");
1293
5e3dd157
KV		 1294 status->freq = ieee80211_channel_to_frequency(channel, status->band);
1295 status->signal = snr + ATH10K_DEFAULT_NOISE_FLOOR;
1296 status->rate_idx = get_rate_idx(rate, status->band);
1297
5e3dd157
KV		 1298 hdr = (struct ieee80211_hdr *)skb->data;
1299 fc = le16_to_cpu(hdr->frame_control);
1300
504f6cdf
SM		 1301 ath10k_wmi_handle_wep_reauth(ar, skb, status);
1302
2b6a6a90
MK		 1303 /* FW delivers WEP Shared Auth frame with Protected Bit set and
1304 * encrypted payload. However in case of PMF it delivers decrypted
1305 * frames with Protected Bit set. */
1306 if (ieee80211_has_protected(hdr->frame_control) &&
1307 !ieee80211_is_auth(hdr->frame_control)) {
eeab266c
MK		 1308 status->flag |= RX_FLAG_DECRYPTED;
1309
1310 if (!ieee80211_is_action(hdr->frame_control) &&
1311 !ieee80211_is_deauth(hdr->frame_control) &&
1312 !ieee80211_is_disassoc(hdr->frame_control)) {
1313 status->flag |= RX_FLAG_IV_STRIPPED |
1314 RX_FLAG_MMIC_STRIPPED;
1315 hdr->frame_control = __cpu_to_le16(fc &
5e3dd157 1316 ~IEEE80211_FCTL_PROTECTED);
eeab266c 1317 }
5e3dd157
KV		 1318 }
1319
7aa7a72a 1320 ath10k_dbg(ar, ATH10K_DBG_MGMT,
5e3dd157
KV		 1321 "event mgmt rx skb %p len %d ftype %02x stype %02x\n",
1322 skb, skb->len,
1323 fc & IEEE80211_FCTL_FTYPE, fc & IEEE80211_FCTL_STYPE);
1324
7aa7a72a 1325 ath10k_dbg(ar, ATH10K_DBG_MGMT,
5e3dd157
KV		 1326 "event mgmt rx freq %d band %d snr %d, rate_idx %d\n",
1327 status->freq, status->band, status->signal,
1328 status->rate_idx);
1329
5e3dd157
KV		 1330 ieee80211_rx(ar->hw, skb);
1331 return 0;
1332}
1333
2e1dea40
MK		 1334static int freq_to_idx(struct ath10k *ar, int freq)
1335{
1336 struct ieee80211_supported_band *sband;
1337 int band, ch, idx = 0;
1338
1339 for (band = IEEE80211_BAND_2GHZ; band < IEEE80211_NUM_BANDS; band++) {
1340 sband = ar->hw->wiphy->bands[band];
1341 if (!sband)
1342 continue;
1343
1344 for (ch = 0; ch < sband->n_channels; ch++, idx++)
1345 if (sband->channels[ch].center_freq == freq)
1346 goto exit;
1347 }
1348
1349exit:
1350 return idx;
1351}
1352
32653cf1
MK		 1353static int ath10k_wmi_pull_ch_info_ev(struct sk_buff *skb,
1354 struct wmi_ch_info_ev_arg *arg)
1355{
1356 struct wmi_chan_info_event *ev = (void *)skb->data;
1357
1358 if (skb->len < sizeof(*ev))
1359 return -EPROTO;
1360
1361 skb_pull(skb, sizeof(*ev));
1362 arg->err_code = ev->err_code;
1363 arg->freq = ev->freq;
1364 arg->cmd_flags = ev->cmd_flags;
1365 arg->noise_floor = ev->noise_floor;
1366 arg->rx_clear_count = ev->rx_clear_count;
1367 arg->cycle_count = ev->cycle_count;
1368
1369 return 0;
1370}
1371
5e3dd157
KV		 1372static void ath10k_wmi_event_chan_info(struct ath10k *ar, struct sk_buff *skb)
1373{
32653cf1 1374 struct wmi_ch_info_ev_arg arg = {};
2e1dea40
MK		 1375 struct survey_info *survey;
1376 u32 err_code, freq, cmd_flags, noise_floor, rx_clear_count, cycle_count;
32653cf1 1377 int idx, ret;
2e1dea40 1378
32653cf1
MK		 1379 ret = ath10k_wmi_pull_ch_info_ev(skb, &arg);
1380 if (ret) {
1381 ath10k_warn(ar, "failed to parse chan info event: %d\n", ret);
1382 return;
1383 }
2e1dea40 1384
32653cf1
MK		 1385 err_code = __le32_to_cpu(arg.err_code);
1386 freq = __le32_to_cpu(arg.freq);
1387 cmd_flags = __le32_to_cpu(arg.cmd_flags);
1388 noise_floor = __le32_to_cpu(arg.noise_floor);
1389 rx_clear_count = __le32_to_cpu(arg.rx_clear_count);
1390 cycle_count = __le32_to_cpu(arg.cycle_count);
2e1dea40 1391
7aa7a72a 1392 ath10k_dbg(ar, ATH10K_DBG_WMI,
2e1dea40
MK		 1393 "chan info err_code %d freq %d cmd_flags %d noise_floor %d rx_clear_count %d cycle_count %d\n",
1394 err_code, freq, cmd_flags, noise_floor, rx_clear_count,
1395 cycle_count);
1396
1397 spin_lock_bh(&ar->data_lock);
1398
5c81c7fd
MK		 1399 switch (ar->scan.state) {
1400 case ATH10K_SCAN_IDLE:
1401 case ATH10K_SCAN_STARTING:
7aa7a72a 1402 ath10k_warn(ar, "received chan info event without a scan request, ignoring\n");
2e1dea40 1403 goto exit;
5c81c7fd
MK		 1404 case ATH10K_SCAN_RUNNING:
1405 case ATH10K_SCAN_ABORTING:
1406 break;
2e1dea40
MK		 1407 }
1408
1409 idx = freq_to_idx(ar, freq);
1410 if (idx >= ARRAY_SIZE(ar->survey)) {
7aa7a72a 1411 ath10k_warn(ar, "chan info: invalid frequency %d (idx %d out of bounds)\n",
2e1dea40
MK		 1412 freq, idx);
1413 goto exit;
1414 }
1415
1416 if (cmd_flags & WMI_CHAN_INFO_FLAG_COMPLETE) {
1417 /* During scanning chan info is reported twice for each
1418 * visited channel. The reported cycle count is global
1419 * and per-channel cycle count must be calculated */
1420
1421 cycle_count -= ar->survey_last_cycle_count;
1422 rx_clear_count -= ar->survey_last_rx_clear_count;
1423
1424 survey = &ar->survey[idx];
1425 survey->channel_time = WMI_CHAN_INFO_MSEC(cycle_count);
1426 survey->channel_time_rx = WMI_CHAN_INFO_MSEC(rx_clear_count);
1427 survey->noise = noise_floor;
1428 survey->filled = SURVEY_INFO_CHANNEL_TIME |
1429 SURVEY_INFO_CHANNEL_TIME_RX |
1430 SURVEY_INFO_NOISE_DBM;
1431 }
1432
1433 ar->survey_last_rx_clear_count = rx_clear_count;
1434 ar->survey_last_cycle_count = cycle_count;
1435
1436exit:
1437 spin_unlock_bh(&ar->data_lock);
5e3dd157
KV		 1438}
1439
1440static void ath10k_wmi_event_echo(struct ath10k *ar, struct sk_buff *skb)
1441{
7aa7a72a 1442 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_ECHO_EVENTID\n");
5e3dd157
KV		 1443}
1444
869526b9 1445static int ath10k_wmi_event_debug_mesg(struct ath10k *ar, struct sk_buff *skb)
5e3dd157 1446{
7aa7a72a 1447 ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi event debug mesg len %d\n",
869526b9
KV		 1448 skb->len);
1449
d35a6c18 1450 trace_ath10k_wmi_dbglog(ar, skb->data, skb->len);
869526b9
KV		 1451
1452 return 0;
5e3dd157
KV		 1453}
1454
d15fb520 1455static void ath10k_wmi_pull_pdev_stats(const struct wmi_pdev_stats *src,
5326849a 1456 struct ath10k_fw_stats_pdev *dst)
d15fb520
MK		 1457{
1458 const struct wal_dbg_tx_stats *tx = &src->wal.tx;
1459 const struct wal_dbg_rx_stats *rx = &src->wal.rx;
1460
1461 dst->ch_noise_floor = __le32_to_cpu(src->chan_nf);
1462 dst->tx_frame_count = __le32_to_cpu(src->tx_frame_count);
1463 dst->rx_frame_count = __le32_to_cpu(src->rx_frame_count);
1464 dst->rx_clear_count = __le32_to_cpu(src->rx_clear_count);
1465 dst->cycle_count = __le32_to_cpu(src->cycle_count);
1466 dst->phy_err_count = __le32_to_cpu(src->phy_err_count);
1467 dst->chan_tx_power = __le32_to_cpu(src->chan_tx_pwr);
1468
1469 dst->comp_queued = __le32_to_cpu(tx->comp_queued);
1470 dst->comp_delivered = __le32_to_cpu(tx->comp_delivered);
1471 dst->msdu_enqued = __le32_to_cpu(tx->msdu_enqued);
1472 dst->mpdu_enqued = __le32_to_cpu(tx->mpdu_enqued);
1473 dst->wmm_drop = __le32_to_cpu(tx->wmm_drop);
1474 dst->local_enqued = __le32_to_cpu(tx->local_enqued);
1475 dst->local_freed = __le32_to_cpu(tx->local_freed);
1476 dst->hw_queued = __le32_to_cpu(tx->hw_queued);
1477 dst->hw_reaped = __le32_to_cpu(tx->hw_reaped);
1478 dst->underrun = __le32_to_cpu(tx->underrun);
1479 dst->tx_abort = __le32_to_cpu(tx->tx_abort);
1480 dst->mpdus_requed = __le32_to_cpu(tx->mpdus_requed);
1481 dst->tx_ko = __le32_to_cpu(tx->tx_ko);
1482 dst->data_rc = __le32_to_cpu(tx->data_rc);
1483 dst->self_triggers = __le32_to_cpu(tx->self_triggers);
1484 dst->sw_retry_failure = __le32_to_cpu(tx->sw_retry_failure);
1485 dst->illgl_rate_phy_err = __le32_to_cpu(tx->illgl_rate_phy_err);
1486 dst->pdev_cont_xretry = __le32_to_cpu(tx->pdev_cont_xretry);
1487 dst->pdev_tx_timeout = __le32_to_cpu(tx->pdev_tx_timeout);
1488 dst->pdev_resets = __le32_to_cpu(tx->pdev_resets);
1489 dst->phy_underrun = __le32_to_cpu(tx->phy_underrun);
1490 dst->txop_ovf = __le32_to_cpu(tx->txop_ovf);
1491
1492 dst->mid_ppdu_route_change = __le32_to_cpu(rx->mid_ppdu_route_change);
1493 dst->status_rcvd = __le32_to_cpu(rx->status_rcvd);
1494 dst->r0_frags = __le32_to_cpu(rx->r0_frags);
1495 dst->r1_frags = __le32_to_cpu(rx->r1_frags);
1496 dst->r2_frags = __le32_to_cpu(rx->r2_frags);
1497 dst->r3_frags = __le32_to_cpu(rx->r3_frags);
1498 dst->htt_msdus = __le32_to_cpu(rx->htt_msdus);
1499 dst->htt_mpdus = __le32_to_cpu(rx->htt_mpdus);
1500 dst->loc_msdus = __le32_to_cpu(rx->loc_msdus);
1501 dst->loc_mpdus = __le32_to_cpu(rx->loc_mpdus);
1502 dst->oversize_amsdu = __le32_to_cpu(rx->oversize_amsdu);
1503 dst->phy_errs = __le32_to_cpu(rx->phy_errs);
1504 dst->phy_err_drop = __le32_to_cpu(rx->phy_err_drop);
1505 dst->mpdu_errs = __le32_to_cpu(rx->mpdu_errs);
1506}
1507
1508static void ath10k_wmi_pull_peer_stats(const struct wmi_peer_stats *src,
60ef401a 1509 struct ath10k_fw_stats_peer *dst)
d15fb520
MK		 1510{
1511 ether_addr_copy(dst->peer_macaddr, src->peer_macaddr.addr);
1512 dst->peer_rssi = __le32_to_cpu(src->peer_rssi);
1513 dst->peer_tx_rate = __le32_to_cpu(src->peer_tx_rate);
1514}
1515
1516static int ath10k_wmi_main_pull_fw_stats(struct ath10k *ar,
1517 struct sk_buff *skb,
60ef401a 1518 struct ath10k_fw_stats *stats)
d15fb520
MK		 1519{
1520 const struct wmi_stats_event *ev = (void *)skb->data;
1521 u32 num_pdev_stats, num_vdev_stats, num_peer_stats;
1522 int i;
1523
1524 if (!skb_pull(skb, sizeof(*ev)))
1525 return -EPROTO;
1526
1527 num_pdev_stats = __le32_to_cpu(ev->num_pdev_stats);
1528 num_vdev_stats = __le32_to_cpu(ev->num_vdev_stats);
1529 num_peer_stats = __le32_to_cpu(ev->num_peer_stats);
1530
5326849a 1531 for (i = 0; i < num_pdev_stats; i++) {
d15fb520 1532 const struct wmi_pdev_stats *src;
5326849a 1533 struct ath10k_fw_stats_pdev *dst;
d15fb520
MK		 1534
1535 src = (void *)skb->data;
1536 if (!skb_pull(skb, sizeof(*src)))
1537 return -EPROTO;
1538
5326849a
MK		 1539 dst = kzalloc(sizeof(*dst), GFP_ATOMIC);
1540 if (!dst)
1541 continue;
1542
1543 ath10k_wmi_pull_pdev_stats(src, dst);
1544 list_add_tail(&dst->list, &stats->pdevs);
d15fb520
MK		 1545 }
1546
1547 /* fw doesn't implement vdev stats */
1548
1549 for (i = 0; i < num_peer_stats; i++) {
1550 const struct wmi_peer_stats *src;
5326849a 1551 struct ath10k_fw_stats_peer *dst;
d15fb520
MK		 1552
1553 src = (void *)skb->data;
1554 if (!skb_pull(skb, sizeof(*src)))
1555 return -EPROTO;
1556
5326849a
MK		 1557 dst = kzalloc(sizeof(*dst), GFP_ATOMIC);
1558 if (!dst)
1559 continue;
1560
1561 ath10k_wmi_pull_peer_stats(src, dst);
1562 list_add_tail(&dst->list, &stats->peers);
d15fb520
MK		 1563 }
1564
1565 return 0;
1566}
1567
1568static int ath10k_wmi_10x_pull_fw_stats(struct ath10k *ar,
1569 struct sk_buff *skb,
60ef401a 1570 struct ath10k_fw_stats *stats)
d15fb520
MK		 1571{
1572 const struct wmi_stats_event *ev = (void *)skb->data;
1573 u32 num_pdev_stats, num_vdev_stats, num_peer_stats;
1574 int i;
1575
1576 if (!skb_pull(skb, sizeof(*ev)))
1577 return -EPROTO;
1578
1579 num_pdev_stats = __le32_to_cpu(ev->num_pdev_stats);
1580 num_vdev_stats = __le32_to_cpu(ev->num_vdev_stats);
1581 num_peer_stats = __le32_to_cpu(ev->num_peer_stats);
1582
5326849a 1583 for (i = 0; i < num_pdev_stats; i++) {
d15fb520 1584 const struct wmi_10x_pdev_stats *src;
5326849a 1585 struct ath10k_fw_stats_pdev *dst;
d15fb520
MK		 1586
1587 src = (void *)skb->data;
1588 if (!skb_pull(skb, sizeof(*src)))
1589 return -EPROTO;
1590
5326849a
MK		 1591 dst = kzalloc(sizeof(*dst), GFP_ATOMIC);
1592 if (!dst)
1593 continue;
1594
1595 ath10k_wmi_pull_pdev_stats(&src->old, dst);
1596
1597 dst->ack_rx_bad = __le32_to_cpu(src->ack_rx_bad);
1598 dst->rts_bad = __le32_to_cpu(src->rts_bad);
1599 dst->rts_good = __le32_to_cpu(src->rts_good);
1600 dst->fcs_bad = __le32_to_cpu(src->fcs_bad);
1601 dst->no_beacons = __le32_to_cpu(src->no_beacons);
1602 dst->mib_int_count = __le32_to_cpu(src->mib_int_count);
d15fb520 1603
5326849a 1604 list_add_tail(&dst->list, &stats->pdevs);
d15fb520
MK		 1605 }
1606
1607 /* fw doesn't implement vdev stats */
1608
1609 for (i = 0; i < num_peer_stats; i++) {
1610 const struct wmi_10x_peer_stats *src;
5326849a 1611 struct ath10k_fw_stats_peer *dst;
d15fb520
MK		 1612
1613 src = (void *)skb->data;
1614 if (!skb_pull(skb, sizeof(*src)))
1615 return -EPROTO;
1616
5326849a
MK		 1617 dst = kzalloc(sizeof(*dst), GFP_ATOMIC);
1618 if (!dst)
1619 continue;
1620
1621 ath10k_wmi_pull_peer_stats(&src->old, dst);
1622
1623 dst->peer_rx_rate = __le32_to_cpu(src->peer_rx_rate);
d15fb520 1624
5326849a 1625 list_add_tail(&dst->list, &stats->peers);
d15fb520
MK		 1626 }
1627
1628 return 0;
1629}
1630
1631int ath10k_wmi_pull_fw_stats(struct ath10k *ar, struct sk_buff *skb,
60ef401a 1632 struct ath10k_fw_stats *stats)
d15fb520
MK		 1633{
1634 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features))
1635 return ath10k_wmi_10x_pull_fw_stats(ar, skb, stats);
1636 else
1637 return ath10k_wmi_main_pull_fw_stats(ar, skb, stats);
1638}
1639
5e3dd157
KV		 1640static void ath10k_wmi_event_update_stats(struct ath10k *ar,
1641 struct sk_buff *skb)
1642{
7aa7a72a 1643 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_UPDATE_STATS_EVENTID\n");
60ef401a 1644 ath10k_debug_fw_stats_process(ar, skb);
5e3dd157
KV		 1645}
1646
32653cf1
MK		 1647static int ath10k_wmi_pull_vdev_start_ev(struct sk_buff *skb,
1648 struct wmi_vdev_start_ev_arg *arg)
1649{
1650 struct wmi_vdev_start_response_event *ev = (void *)skb->data;
1651
1652 if (skb->len < sizeof(*ev))
1653 return -EPROTO;
1654
1655 skb_pull(skb, sizeof(*ev));
1656 arg->vdev_id = ev->vdev_id;
1657 arg->req_id = ev->req_id;
1658 arg->resp_type = ev->resp_type;
1659 arg->status = ev->status;
1660
1661 return 0;
1662}
1663
5e3dd157
KV		 1664static void ath10k_wmi_event_vdev_start_resp(struct ath10k *ar,
1665 struct sk_buff *skb)
1666{
32653cf1
MK		 1667 struct wmi_vdev_start_ev_arg arg = {};
1668 int ret;
5e3dd157 1669
7aa7a72a 1670 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_VDEV_START_RESP_EVENTID\n");
5e3dd157 1671
32653cf1
MK		 1672 ret = ath10k_wmi_pull_vdev_start_ev(skb, &arg);
1673 if (ret) {
1674 ath10k_warn(ar, "failed to parse vdev start event: %d\n", ret);
1675 return;
1676 }
5e3dd157 1677
32653cf1 1678 if (WARN_ON(__le32_to_cpu(arg.status)))
5e3dd157
KV		 1679 return;
1680
1681 complete(&ar->vdev_setup_done);
1682}
1683
1684static void ath10k_wmi_event_vdev_stopped(struct ath10k *ar,
1685 struct sk_buff *skb)
1686{
7aa7a72a 1687 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_VDEV_STOPPED_EVENTID\n");
5e3dd157
KV		 1688 complete(&ar->vdev_setup_done);
1689}
1690
32653cf1
MK		 1691static int ath10k_wmi_pull_peer_kick_ev(struct sk_buff *skb,
1692 struct wmi_peer_kick_ev_arg *arg)
1693{
1694 struct wmi_peer_sta_kickout_event *ev = (void *)skb->data;
1695
1696 if (skb->len < sizeof(*ev))
1697 return -EPROTO;
1698
1699 skb_pull(skb, sizeof(*ev));
1700 arg->mac_addr = ev->peer_macaddr.addr;
1701
1702 return 0;
1703}
1704
5e3dd157
KV		 1705static void ath10k_wmi_event_peer_sta_kickout(struct ath10k *ar,
1706 struct sk_buff *skb)
1707{
32653cf1 1708 struct wmi_peer_kick_ev_arg arg = {};
5a13e76e 1709 struct ieee80211_sta *sta;
32653cf1 1710 int ret;
5a13e76e 1711
32653cf1
MK		 1712 ret = ath10k_wmi_pull_peer_kick_ev(skb, &arg);
1713 if (ret) {
1714 ath10k_warn(ar, "failed to parse peer kickout event: %d\n",
1715 ret);
1716 return;
1717 }
5a13e76e 1718
7aa7a72a 1719 ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi event peer sta kickout %pM\n",
32653cf1 1720 arg.mac_addr);
5a13e76e
KV		 1721
1722 rcu_read_lock();
1723
32653cf1 1724 sta = ieee80211_find_sta_by_ifaddr(ar->hw, arg.mac_addr, NULL);
5a13e76e 1725 if (!sta) {
7aa7a72a 1726 ath10k_warn(ar, "Spurious quick kickout for STA %pM\n",
32653cf1 1727 arg.mac_addr);
5a13e76e
KV		 1728 goto exit;
1729 }
1730
1731 ieee80211_report_low_ack(sta, 10);
1732
1733exit:
1734 rcu_read_unlock();
5e3dd157
KV		 1735}
1736
1737/*
1738 * FIXME
1739 *
1740 * We don't report to mac80211 sleep state of connected
1741 * stations. Due to this mac80211 can't fill in TIM IE
1742 * correctly.
1743 *
1744 * I know of no way of getting nullfunc frames that contain
1745 * sleep transition from connected stations - these do not
1746 * seem to be sent from the target to the host. There also
1747 * doesn't seem to be a dedicated event for that. So the
1748 * only way left to do this would be to read tim_bitmap
1749 * during SWBA.
1750 *
1751 * We could probably try using tim_bitmap from SWBA to tell
1752 * mac80211 which stations are asleep and which are not. The
1753 * problem here is calling mac80211 functions so many times
1754 * could take too long and make us miss the time to submit
1755 * the beacon to the target.
1756 *
1757 * So as a workaround we try to extend the TIM IE if there
1758 * is unicast buffered for stations with aid > 7 and fill it
1759 * in ourselves.
1760 */
1761static void ath10k_wmi_update_tim(struct ath10k *ar,
1762 struct ath10k_vif *arvif,
1763 struct sk_buff *bcn,
32653cf1 1764 const struct wmi_tim_info *tim_info)
5e3dd157
KV		 1765{
1766 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)bcn->data;
1767 struct ieee80211_tim_ie *tim;
1768 u8 *ies, *ie;
1769 u8 ie_len, pvm_len;
af762c0b
KV		 1770 __le32 t;
1771 u32 v;
5e3dd157
KV		 1772
1773 /* if next SWBA has no tim_changed the tim_bitmap is garbage.
1774 * we must copy the bitmap upon change and reuse it later */
32653cf1 1775 if (__le32_to_cpu(tim_info->tim_changed)) {
5e3dd157
KV		 1776 int i;
1777
1778 BUILD_BUG_ON(sizeof(arvif->u.ap.tim_bitmap) !=
32653cf1 1779 sizeof(tim_info->tim_bitmap));
5e3dd157
KV		 1780
1781 for (i = 0; i < sizeof(arvif->u.ap.tim_bitmap); i++) {
32653cf1 1782 t = tim_info->tim_bitmap[i / 4];
af762c0b 1783 v = __le32_to_cpu(t);
5e3dd157
KV		 1784 arvif->u.ap.tim_bitmap[i] = (v >> ((i % 4) * 8)) & 0xFF;
1785 }
1786
1787 /* FW reports either length 0 or 16
1788 * so we calculate this on our own */
1789 arvif->u.ap.tim_len = 0;
1790 for (i = 0; i < sizeof(arvif->u.ap.tim_bitmap); i++)
1791 if (arvif->u.ap.tim_bitmap[i])
1792 arvif->u.ap.tim_len = i;
1793
1794 arvif->u.ap.tim_len++;
1795 }
1796
1797 ies = bcn->data;
1798 ies += ieee80211_hdrlen(hdr->frame_control);
1799 ies += 12; /* fixed parameters */
1800
1801 ie = (u8 *)cfg80211_find_ie(WLAN_EID_TIM, ies,
1802 (u8 *)skb_tail_pointer(bcn) - ies);
1803 if (!ie) {
09af8f85 1804 if (arvif->vdev_type != WMI_VDEV_TYPE_IBSS)
7aa7a72a 1805 ath10k_warn(ar, "no tim ie found;\n");
5e3dd157
KV		 1806 return;
1807 }
1808
1809 tim = (void *)ie + 2;
1810 ie_len = ie[1];
1811 pvm_len = ie_len - 3; /* exclude dtim count, dtim period, bmap ctl */
1812
1813 if (pvm_len < arvif->u.ap.tim_len) {
1814 int expand_size = sizeof(arvif->u.ap.tim_bitmap) - pvm_len;
1815 int move_size = skb_tail_pointer(bcn) - (ie + 2 + ie_len);
1816 void *next_ie = ie + 2 + ie_len;
1817
1818 if (skb_put(bcn, expand_size)) {
1819 memmove(next_ie + expand_size, next_ie, move_size);
1820
1821 ie[1] += expand_size;
1822 ie_len += expand_size;
1823 pvm_len += expand_size;
1824 } else {
7aa7a72a 1825 ath10k_warn(ar, "tim expansion failed\n");
5e3dd157
KV		 1826 }
1827 }
1828
1829 if (pvm_len > sizeof(arvif->u.ap.tim_bitmap)) {
7aa7a72a 1830 ath10k_warn(ar, "tim pvm length is too great (%d)\n", pvm_len);
5e3dd157
KV		 1831 return;
1832 }
1833
32653cf1 1834 tim->bitmap_ctrl = !!__le32_to_cpu(tim_info->tim_mcast);
5e3dd157
KV		 1835 memcpy(tim->virtual_map, arvif->u.ap.tim_bitmap, pvm_len);
1836
748afc47
MK		 1837 if (tim->dtim_count == 0) {
1838 ATH10K_SKB_CB(bcn)->bcn.dtim_zero = true;
1839
32653cf1 1840 if (__le32_to_cpu(tim_info->tim_mcast) == 1)
748afc47
MK		 1841 ATH10K_SKB_CB(bcn)->bcn.deliver_cab = true;
1842 }
1843
7aa7a72a 1844 ath10k_dbg(ar, ATH10K_DBG_MGMT, "dtim %d/%d mcast %d pvmlen %d\n",
5e3dd157
KV		 1845 tim->dtim_count, tim->dtim_period,
1846 tim->bitmap_ctrl, pvm_len);
1847}
1848
1849static void ath10k_p2p_fill_noa_ie(u8 *data, u32 len,
32653cf1 1850 const struct wmi_p2p_noa_info *noa)
5e3dd157
KV		 1851{
1852 struct ieee80211_p2p_noa_attr *noa_attr;
1853 u8 ctwindow_oppps = noa->ctwindow_oppps;
1854 u8 ctwindow = ctwindow_oppps >> WMI_P2P_OPPPS_CTWINDOW_OFFSET;
1855 bool oppps = !!(ctwindow_oppps & WMI_P2P_OPPPS_ENABLE_BIT);
1856 __le16 *noa_attr_len;
1857 u16 attr_len;
1858 u8 noa_descriptors = noa->num_descriptors;
1859 int i;
1860
1861 /* P2P IE */
1862 data[0] = WLAN_EID_VENDOR_SPECIFIC;
1863 data[1] = len - 2;
1864 data[2] = (WLAN_OUI_WFA >> 16) & 0xff;
1865 data[3] = (WLAN_OUI_WFA >> 8) & 0xff;
1866 data[4] = (WLAN_OUI_WFA >> 0) & 0xff;
1867 data[5] = WLAN_OUI_TYPE_WFA_P2P;
1868
1869 /* NOA ATTR */
1870 data[6] = IEEE80211_P2P_ATTR_ABSENCE_NOTICE;
1871 noa_attr_len = (__le16 *)&data[7]; /* 2 bytes */
1872 noa_attr = (struct ieee80211_p2p_noa_attr *)&data[9];
1873
1874 noa_attr->index = noa->index;
1875 noa_attr->oppps_ctwindow = ctwindow;
1876 if (oppps)
1877 noa_attr->oppps_ctwindow |= IEEE80211_P2P_OPPPS_ENABLE_BIT;
1878
1879 for (i = 0; i < noa_descriptors; i++) {
1880 noa_attr->desc[i].count =
1881 __le32_to_cpu(noa->descriptors[i].type_count);
1882 noa_attr->desc[i].duration = noa->descriptors[i].duration;
1883 noa_attr->desc[i].interval = noa->descriptors[i].interval;
1884 noa_attr->desc[i].start_time = noa->descriptors[i].start_time;
1885 }
1886
1887 attr_len = 2; /* index + oppps_ctwindow */
1888 attr_len += noa_descriptors * sizeof(struct ieee80211_p2p_noa_desc);
1889 *noa_attr_len = __cpu_to_le16(attr_len);
1890}
1891
32653cf1 1892static u32 ath10k_p2p_calc_noa_ie_len(const struct wmi_p2p_noa_info *noa)
5e3dd157
KV		 1893{
1894 u32 len = 0;
1895 u8 noa_descriptors = noa->num_descriptors;
1896 u8 opp_ps_info = noa->ctwindow_oppps;
1897 bool opps_enabled = !!(opp_ps_info & WMI_P2P_OPPPS_ENABLE_BIT);
1898
5e3dd157
KV		 1899 if (!noa_descriptors && !opps_enabled)
1900 return len;
1901
1902 len += 1 + 1 + 4; /* EID + len + OUI */
1903 len += 1 + 2; /* noa attr + attr len */
1904 len += 1 + 1; /* index + oppps_ctwindow */
1905 len += noa_descriptors * sizeof(struct ieee80211_p2p_noa_desc);
1906
1907 return len;
1908}
1909
1910static void ath10k_wmi_update_noa(struct ath10k *ar, struct ath10k_vif *arvif,
1911 struct sk_buff *bcn,
32653cf1 1912 const struct wmi_p2p_noa_info *noa)
5e3dd157 1913{
5e3dd157
KV		 1914 u8 *new_data, *old_data = arvif->u.ap.noa_data;
1915 u32 new_len;
1916
1917 if (arvif->vdev_subtype != WMI_VDEV_SUBTYPE_P2P_GO)
1918 return;
1919
7aa7a72a 1920 ath10k_dbg(ar, ATH10K_DBG_MGMT, "noa changed: %d\n", noa->changed);
5e3dd157
KV		 1921 if (noa->changed & WMI_P2P_NOA_CHANGED_BIT) {
1922 new_len = ath10k_p2p_calc_noa_ie_len(noa);
1923 if (!new_len)
1924 goto cleanup;
1925
1926 new_data = kmalloc(new_len, GFP_ATOMIC);
1927 if (!new_data)
1928 goto cleanup;
1929
1930 ath10k_p2p_fill_noa_ie(new_data, new_len, noa);
1931
1932 spin_lock_bh(&ar->data_lock);
1933 arvif->u.ap.noa_data = new_data;
1934 arvif->u.ap.noa_len = new_len;
1935 spin_unlock_bh(&ar->data_lock);
1936 kfree(old_data);
1937 }
1938
1939 if (arvif->u.ap.noa_data)
1940 if (!pskb_expand_head(bcn, 0, arvif->u.ap.noa_len, GFP_ATOMIC))
1941 memcpy(skb_put(bcn, arvif->u.ap.noa_len),
1942 arvif->u.ap.noa_data,
1943 arvif->u.ap.noa_len);
1944 return;
1945
1946cleanup:
1947 spin_lock_bh(&ar->data_lock);
1948 arvif->u.ap.noa_data = NULL;
1949 arvif->u.ap.noa_len = 0;
1950 spin_unlock_bh(&ar->data_lock);
1951 kfree(old_data);
1952}
1953
32653cf1
MK		 1954static int ath10k_wmi_pull_swba_ev(struct sk_buff *skb,
1955 struct wmi_swba_ev_arg *arg)
1956{
1957 struct wmi_host_swba_event *ev = (void *)skb->data;
1958 u32 map;
1959 size_t i;
1960
1961 if (skb->len < sizeof(*ev))
1962 return -EPROTO;
1963
1964 skb_pull(skb, sizeof(*ev));
1965 arg->vdev_map = ev->vdev_map;
1966
1967 for (i = 0, map = __le32_to_cpu(ev->vdev_map); map; map >>= 1) {
1968 if (!(map & BIT(0)))
1969 continue;
1970
1971 /* If this happens there were some changes in firmware and
1972 * ath10k should update the max size of tim_info array.
1973 */
1974 if (WARN_ON_ONCE(i == ARRAY_SIZE(arg->tim_info)))
1975 break;
1976
1977 arg->tim_info[i] = &ev->bcn_info[i].tim_info;
1978 arg->noa_info[i] = &ev->bcn_info[i].p2p_noa_info;
1979 i++;
1980 }
1981
1982 return 0;
1983}
1984
5e3dd157
KV		 1985static void ath10k_wmi_event_host_swba(struct ath10k *ar, struct sk_buff *skb)
1986{
32653cf1 1987 struct wmi_swba_ev_arg arg = {};
5e3dd157
KV		 1988 u32 map;
1989 int i = -1;
32653cf1
MK		 1990 const struct wmi_tim_info *tim_info;
1991 const struct wmi_p2p_noa_info *noa_info;
5e3dd157 1992 struct ath10k_vif *arvif;
5e3dd157 1993 struct sk_buff *bcn;
64badcb6 1994 dma_addr_t paddr;
767d34fc 1995 int ret, vdev_id = 0;
5e3dd157 1996
32653cf1
MK		 1997 ret = ath10k_wmi_pull_swba_ev(skb, &arg);
1998 if (ret) {
1999 ath10k_warn(ar, "failed to parse swba event: %d\n", ret);
2000 return;
2001 }
2002
2003 map = __le32_to_cpu(arg.vdev_map);
5e3dd157 2004
7aa7a72a 2005 ath10k_dbg(ar, ATH10K_DBG_MGMT, "mgmt swba vdev_map 0x%x\n",
32653cf1 2006 map);
5e3dd157
KV		 2007
2008 for (; map; map >>= 1, vdev_id++) {
2009 if (!(map & 0x1))
2010 continue;
2011
2012 i++;
2013
2014 if (i >= WMI_MAX_AP_VDEV) {
7aa7a72a 2015 ath10k_warn(ar, "swba has corrupted vdev map\n");
5e3dd157
KV		 2016 break;
2017 }
2018
32653cf1
MK		 2019 tim_info = arg.tim_info[i];
2020 noa_info = arg.noa_info[i];
5e3dd157 2021
7aa7a72a 2022 ath10k_dbg(ar, ATH10K_DBG_MGMT,
7a8a396b 2023 "mgmt event bcn_info %d tim_len %d mcast %d changed %d num_ps_pending %d bitmap 0x%08x%08x%08x%08x\n",
5e3dd157 2024 i,
32653cf1
MK		 2025 __le32_to_cpu(tim_info->tim_len),
2026 __le32_to_cpu(tim_info->tim_mcast),
2027 __le32_to_cpu(tim_info->tim_changed),
2028 __le32_to_cpu(tim_info->tim_num_ps_pending),
2029 __le32_to_cpu(tim_info->tim_bitmap[3]),
2030 __le32_to_cpu(tim_info->tim_bitmap[2]),
2031 __le32_to_cpu(tim_info->tim_bitmap[1]),
2032 __le32_to_cpu(tim_info->tim_bitmap[0]));
5e3dd157
KV		 2033
2034 arvif = ath10k_get_arvif(ar, vdev_id);
2035 if (arvif == NULL) {
7aa7a72a
MK		 2036 ath10k_warn(ar, "no vif for vdev_id %d found\n",
2037 vdev_id);
5e3dd157
KV		 2038 continue;
2039 }
2040
c2df44b3
MK		 2041 /* There are no completions for beacons so wait for next SWBA
2042 * before telling mac80211 to decrement CSA counter
2043 *
2044 * Once CSA counter is completed stop sending beacons until
2045 * actual channel switch is done */
2046 if (arvif->vif->csa_active &&
2047 ieee80211_csa_is_complete(arvif->vif)) {
2048 ieee80211_csa_finish(arvif->vif);
2049 continue;
2050 }
2051
5e3dd157
KV		 2052 bcn = ieee80211_beacon_get(ar->hw, arvif->vif);
2053 if (!bcn) {
7aa7a72a 2054 ath10k_warn(ar, "could not get mac80211 beacon\n");
5e3dd157
KV		 2055 continue;
2056 }
2057
4b604558 2058 ath10k_tx_h_seq_no(arvif->vif, bcn);
32653cf1
MK		 2059 ath10k_wmi_update_tim(ar, arvif, bcn, tim_info);
2060 ath10k_wmi_update_noa(ar, arvif, bcn, noa_info);
5e3dd157 2061
ed54388a 2062 spin_lock_bh(&ar->data_lock);
748afc47 2063
ed54388a 2064 if (arvif->beacon) {
748afc47 2065 if (!arvif->beacon_sent)
7aa7a72a 2066 ath10k_warn(ar, "SWBA overrun on vdev %d\n",
748afc47
MK		 2067 arvif->vdev_id);
2068
64badcb6 2069 ath10k_mac_vif_beacon_free(arvif);
ed54388a 2070 }
5e3dd157 2071
64badcb6
MK		 2072 if (!arvif->beacon_buf) {
2073 paddr = dma_map_single(arvif->ar->dev, bcn->data,
2074 bcn->len, DMA_TO_DEVICE);
2075 ret = dma_mapping_error(arvif->ar->dev, paddr);
2076 if (ret) {
2077 ath10k_warn(ar, "failed to map beacon: %d\n",
2078 ret);
2079 dev_kfree_skb_any(bcn);
2080 goto skip;
2081 }
2082
2083 ATH10K_SKB_CB(bcn)->paddr = paddr;
2084 } else {
2085 if (bcn->len > IEEE80211_MAX_FRAME_LEN) {
2086 ath10k_warn(ar, "trimming beacon %d -> %d bytes!\n",
2087 bcn->len, IEEE80211_MAX_FRAME_LEN);
2088 skb_trim(bcn, IEEE80211_MAX_FRAME_LEN);
2089 }
2090 memcpy(arvif->beacon_buf, bcn->data, bcn->len);
2091 ATH10K_SKB_CB(bcn)->paddr = arvif->beacon_paddr;
767d34fc 2092 }
748afc47 2093
ed54388a 2094 arvif->beacon = bcn;
748afc47 2095 arvif->beacon_sent = false;
5e3dd157 2096
5ce8e7fd
RM		 2097 trace_ath10k_tx_hdr(ar, bcn->data, bcn->len);
2098 trace_ath10k_tx_payload(ar, bcn->data, bcn->len);
2099
ed54388a 2100 ath10k_wmi_tx_beacon_nowait(arvif);
767d34fc 2101skip:
ed54388a 2102 spin_unlock_bh(&ar->data_lock);
5e3dd157
KV		 2103 }
2104}
2105
2106static void ath10k_wmi_event_tbttoffset_update(struct ath10k *ar,
2107 struct sk_buff *skb)
2108{
7aa7a72a 2109 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_TBTTOFFSET_UPDATE_EVENTID\n");
5e3dd157
KV		 2110}
2111
9702c686 2112static void ath10k_dfs_radar_report(struct ath10k *ar,
2332d0ae
MK		 2113 const struct wmi_phyerr *phyerr,
2114 const struct phyerr_radar_report *rr,
9702c686
JD		 2115 u64 tsf)
2116{
2117 u32 reg0, reg1, tsf32l;
2118 struct pulse_event pe;
2119 u64 tsf64;
2120 u8 rssi, width;
2121
2122 reg0 = __le32_to_cpu(rr->reg0);
2123 reg1 = __le32_to_cpu(rr->reg1);
2124
7aa7a72a 2125 ath10k_dbg(ar, ATH10K_DBG_REGULATORY,
9702c686
JD		 2126 "wmi phyerr radar report chirp %d max_width %d agc_total_gain %d pulse_delta_diff %d\n",
2127 MS(reg0, RADAR_REPORT_REG0_PULSE_IS_CHIRP),
2128 MS(reg0, RADAR_REPORT_REG0_PULSE_IS_MAX_WIDTH),
2129 MS(reg0, RADAR_REPORT_REG0_AGC_TOTAL_GAIN),
2130 MS(reg0, RADAR_REPORT_REG0_PULSE_DELTA_DIFF));
7aa7a72a 2131 ath10k_dbg(ar, ATH10K_DBG_REGULATORY,
9702c686
JD		 2132 "wmi phyerr radar report pulse_delta_pean %d pulse_sidx %d fft_valid %d agc_mb_gain %d subchan_mask %d\n",
2133 MS(reg0, RADAR_REPORT_REG0_PULSE_DELTA_PEAK),
2134 MS(reg0, RADAR_REPORT_REG0_PULSE_SIDX),
2135 MS(reg1, RADAR_REPORT_REG1_PULSE_SRCH_FFT_VALID),
2136 MS(reg1, RADAR_REPORT_REG1_PULSE_AGC_MB_GAIN),
2137 MS(reg1, RADAR_REPORT_REG1_PULSE_SUBCHAN_MASK));
7aa7a72a 2138 ath10k_dbg(ar, ATH10K_DBG_REGULATORY,
9702c686
JD		 2139 "wmi phyerr radar report pulse_tsf_offset 0x%X pulse_dur: %d\n",
2140 MS(reg1, RADAR_REPORT_REG1_PULSE_TSF_OFFSET),
2141 MS(reg1, RADAR_REPORT_REG1_PULSE_DUR));
2142
2143 if (!ar->dfs_detector)
2144 return;
2145
2146 /* report event to DFS pattern detector */
2332d0ae 2147 tsf32l = __le32_to_cpu(phyerr->tsf_timestamp);
9702c686
JD		 2148 tsf64 = tsf & (~0xFFFFFFFFULL);
2149 tsf64 |= tsf32l;
2150
2151 width = MS(reg1, RADAR_REPORT_REG1_PULSE_DUR);
2332d0ae 2152 rssi = phyerr->rssi_combined;
9702c686
JD		 2153
2154 /* hardware store this as 8 bit signed value,
2155 * set to zero if negative number
2156 */
2157 if (rssi & 0x80)
2158 rssi = 0;
2159
2160 pe.ts = tsf64;
2161 pe.freq = ar->hw->conf.chandef.chan->center_freq;
2162 pe.width = width;
2163 pe.rssi = rssi;
2164
7aa7a72a 2165 ath10k_dbg(ar, ATH10K_DBG_REGULATORY,
9702c686
JD		 2166 "dfs add pulse freq: %d, width: %d, rssi %d, tsf: %llX\n",
2167 pe.freq, pe.width, pe.rssi, pe.ts);
2168
2169 ATH10K_DFS_STAT_INC(ar, pulses_detected);
2170
2171 if (!ar->dfs_detector->add_pulse(ar->dfs_detector, &pe)) {
7aa7a72a 2172 ath10k_dbg(ar, ATH10K_DBG_REGULATORY,
9702c686
JD		 2173 "dfs no pulse pattern detected, yet\n");
2174 return;
2175 }
2176
7aa7a72a 2177 ath10k_dbg(ar, ATH10K_DBG_REGULATORY, "dfs radar detected\n");
9702c686 2178 ATH10K_DFS_STAT_INC(ar, radar_detected);
7d9b40b4
MP		 2179
2180 /* Control radar events reporting in debugfs file
2181 dfs_block_radar_events */
2182 if (ar->dfs_block_radar_events) {
7aa7a72a 2183 ath10k_info(ar, "DFS Radar detected, but ignored as requested\n");
7d9b40b4
MP		 2184 return;
2185 }
2186
9702c686
JD		 2187 ieee80211_radar_detected(ar->hw);
2188}
2189
2190static int ath10k_dfs_fft_report(struct ath10k *ar,
2332d0ae
MK		 2191 const struct wmi_phyerr *phyerr,
2192 const struct phyerr_fft_report *fftr,
9702c686
JD		 2193 u64 tsf)
2194{
2195 u32 reg0, reg1;
2196 u8 rssi, peak_mag;
2197
2198 reg0 = __le32_to_cpu(fftr->reg0);
2199 reg1 = __le32_to_cpu(fftr->reg1);
2332d0ae 2200 rssi = phyerr->rssi_combined;
9702c686 2201
7aa7a72a 2202 ath10k_dbg(ar, ATH10K_DBG_REGULATORY,
9702c686
JD		 2203 "wmi phyerr fft report total_gain_db %d base_pwr_db %d fft_chn_idx %d peak_sidx %d\n",
2204 MS(reg0, SEARCH_FFT_REPORT_REG0_TOTAL_GAIN_DB),
2205 MS(reg0, SEARCH_FFT_REPORT_REG0_BASE_PWR_DB),
2206 MS(reg0, SEARCH_FFT_REPORT_REG0_FFT_CHN_IDX),
2207 MS(reg0, SEARCH_FFT_REPORT_REG0_PEAK_SIDX));
7aa7a72a 2208 ath10k_dbg(ar, ATH10K_DBG_REGULATORY,
9702c686
JD		 2209 "wmi phyerr fft report rel_pwr_db %d avgpwr_db %d peak_mag %d num_store_bin %d\n",
2210 MS(reg1, SEARCH_FFT_REPORT_REG1_RELPWR_DB),
2211 MS(reg1, SEARCH_FFT_REPORT_REG1_AVGPWR_DB),
2212 MS(reg1, SEARCH_FFT_REPORT_REG1_PEAK_MAG),
2213 MS(reg1, SEARCH_FFT_REPORT_REG1_NUM_STR_BINS_IB));
2214
2215 peak_mag = MS(reg1, SEARCH_FFT_REPORT_REG1_PEAK_MAG);
2216
2217 /* false event detection */
2218 if (rssi == DFS_RSSI_POSSIBLY_FALSE &&
2219 peak_mag < 2 * DFS_PEAK_MAG_THOLD_POSSIBLY_FALSE) {
7aa7a72a 2220 ath10k_dbg(ar, ATH10K_DBG_REGULATORY, "dfs false pulse detected\n");
9702c686
JD		 2221 ATH10K_DFS_STAT_INC(ar, pulses_discarded);
2222 return -EINVAL;
2223 }
2224
2225 return 0;
2226}
2227
2228static void ath10k_wmi_event_dfs(struct ath10k *ar,
2332d0ae 2229 const struct wmi_phyerr *phyerr,
9702c686
JD		 2230 u64 tsf)
2231{
2232 int buf_len, tlv_len, res, i = 0;
2332d0ae
MK		 2233 const struct phyerr_tlv *tlv;
2234 const struct phyerr_radar_report *rr;
2235 const struct phyerr_fft_report *fftr;
2236 const u8 *tlv_buf;
9702c686 2237
2332d0ae 2238 buf_len = __le32_to_cpu(phyerr->buf_len);
7aa7a72a 2239 ath10k_dbg(ar, ATH10K_DBG_REGULATORY,
9702c686 2240 "wmi event dfs err_code %d rssi %d tsfl 0x%X tsf64 0x%llX len %d\n",
2332d0ae
MK		 2241 phyerr->phy_err_code, phyerr->rssi_combined,
2242 __le32_to_cpu(phyerr->tsf_timestamp), tsf, buf_len);
9702c686
JD		 2243
2244 /* Skip event if DFS disabled */
2245 if (!config_enabled(CONFIG_ATH10K_DFS_CERTIFIED))
2246 return;
2247
2248 ATH10K_DFS_STAT_INC(ar, pulses_total);
2249
2250 while (i < buf_len) {
2251 if (i + sizeof(*tlv) > buf_len) {
7aa7a72a
MK		 2252 ath10k_warn(ar, "too short buf for tlv header (%d)\n",
2253 i);
9702c686
JD		 2254 return;
2255 }
2256
2332d0ae 2257 tlv = (struct phyerr_tlv *)&phyerr->buf[i];
9702c686 2258 tlv_len = __le16_to_cpu(tlv->len);
2332d0ae 2259 tlv_buf = &phyerr->buf[i + sizeof(*tlv)];
7aa7a72a 2260 ath10k_dbg(ar, ATH10K_DBG_REGULATORY,
9702c686
JD		 2261 "wmi event dfs tlv_len %d tlv_tag 0x%02X tlv_sig 0x%02X\n",
2262 tlv_len, tlv->tag, tlv->sig);
2263
2264 switch (tlv->tag) {
2265 case PHYERR_TLV_TAG_RADAR_PULSE_SUMMARY:
2266 if (i + sizeof(*tlv) + sizeof(*rr) > buf_len) {
7aa7a72a 2267 ath10k_warn(ar, "too short radar pulse summary (%d)\n",
9702c686
JD		 2268 i);
2269 return;
2270 }
2271
2272 rr = (struct phyerr_radar_report *)tlv_buf;
2332d0ae 2273 ath10k_dfs_radar_report(ar, phyerr, rr, tsf);
9702c686
JD		 2274 break;
2275 case PHYERR_TLV_TAG_SEARCH_FFT_REPORT:
2276 if (i + sizeof(*tlv) + sizeof(*fftr) > buf_len) {
7aa7a72a
MK		 2277 ath10k_warn(ar, "too short fft report (%d)\n",
2278 i);
9702c686
JD		 2279 return;
2280 }
2281
2282 fftr = (struct phyerr_fft_report *)tlv_buf;
2332d0ae 2283 res = ath10k_dfs_fft_report(ar, phyerr, fftr, tsf);
9702c686
JD		 2284 if (res)
2285 return;
2286 break;
2287 }
2288
2289 i += sizeof(*tlv) + tlv_len;
2290 }
2291}
2292
5b07e07f
KV		 2293static void
2294ath10k_wmi_event_spectral_scan(struct ath10k *ar,
2332d0ae 2295 const struct wmi_phyerr *phyerr,
5b07e07f 2296 u64 tsf)
9702c686 2297{
855aed12
SW		 2298 int buf_len, tlv_len, res, i = 0;
2299 struct phyerr_tlv *tlv;
2332d0ae
MK		 2300 const void *tlv_buf;
2301 const struct phyerr_fft_report *fftr;
855aed12
SW		 2302 size_t fftr_len;
2303
2332d0ae 2304 buf_len = __le32_to_cpu(phyerr->buf_len);
855aed12
SW		 2305
2306 while (i < buf_len) {
2307 if (i + sizeof(*tlv) > buf_len) {
7aa7a72a 2308 ath10k_warn(ar, "failed to parse phyerr tlv header at byte %d\n",
855aed12
SW		 2309 i);
2310 return;
2311 }
2312
2332d0ae 2313 tlv = (struct phyerr_tlv *)&phyerr->buf[i];
855aed12 2314 tlv_len = __le16_to_cpu(tlv->len);
2332d0ae 2315 tlv_buf = &phyerr->buf[i + sizeof(*tlv)];
855aed12
SW		 2316
2317 if (i + sizeof(*tlv) + tlv_len > buf_len) {
7aa7a72a 2318 ath10k_warn(ar, "failed to parse phyerr tlv payload at byte %d\n",
855aed12
SW		 2319 i);
2320 return;
2321 }
2322
2323 switch (tlv->tag) {
2324 case PHYERR_TLV_TAG_SEARCH_FFT_REPORT:
2325 if (sizeof(*fftr) > tlv_len) {
7aa7a72a 2326 ath10k_warn(ar, "failed to parse fft report at byte %d\n",
855aed12
SW		 2327 i);
2328 return;
2329 }
2330
2331 fftr_len = tlv_len - sizeof(*fftr);
2332d0ae
MK		 2332 fftr = tlv_buf;
2333 res = ath10k_spectral_process_fft(ar, phyerr,
855aed12
SW		 2334 fftr, fftr_len,
2335 tsf);
2336 if (res < 0) {
7aa7a72a 2337 ath10k_warn(ar, "failed to process fft report: %d\n",
855aed12
SW		 2338 res);
2339 return;
2340 }
2341 break;
2342 }
2343
2344 i += sizeof(*tlv) + tlv_len;
2345 }
9702c686
JD		 2346}
2347
32653cf1
MK		 2348static int ath10k_wmi_pull_phyerr_ev(struct sk_buff *skb,
2349 struct wmi_phyerr_ev_arg *arg)
2350{
2351 struct wmi_phyerr_event *ev = (void *)skb->data;
2352
2353 if (skb->len < sizeof(*ev))
2354 return -EPROTO;
2355
2356 arg->num_phyerrs = ev->num_phyerrs;
2357 arg->tsf_l32 = ev->tsf_l32;
2358 arg->tsf_u32 = ev->tsf_u32;
2359 arg->buf_len = __cpu_to_le32(skb->len - sizeof(*ev));
2360 arg->phyerrs = ev->phyerrs;
2361
2362 return 0;
2363}
2364
5e3dd157
KV		 2365static void ath10k_wmi_event_phyerr(struct ath10k *ar, struct sk_buff *skb)
2366{
32653cf1 2367 struct wmi_phyerr_ev_arg arg = {};
2332d0ae 2368 const struct wmi_phyerr *phyerr;
9702c686
JD		 2369 u32 count, i, buf_len, phy_err_code;
2370 u64 tsf;
32653cf1 2371 int left_len, ret;
9702c686
JD		 2372
2373 ATH10K_DFS_STAT_INC(ar, phy_errors);
2374
32653cf1
MK		 2375 ret = ath10k_wmi_pull_phyerr_ev(skb, &arg);
2376 if (ret) {
2377 ath10k_warn(ar, "failed to parse phyerr event: %d\n", ret);
9702c686
JD		 2378 return;
2379 }
2380
32653cf1 2381 left_len = __le32_to_cpu(arg.buf_len);
9702c686
JD		 2382
2383 /* Check number of included events */
32653cf1 2384 count = __le32_to_cpu(arg.num_phyerrs);
9702c686 2385
32653cf1 2386 tsf = __le32_to_cpu(arg.tsf_u32);
9702c686 2387 tsf <<= 32;
32653cf1 2388 tsf |= __le32_to_cpu(arg.tsf_l32);
9702c686 2389
7aa7a72a 2390 ath10k_dbg(ar, ATH10K_DBG_WMI,
9702c686
JD		 2391 "wmi event phyerr count %d tsf64 0x%llX\n",
2392 count, tsf);
2393
32653cf1 2394 phyerr = arg.phyerrs;
9702c686
JD		 2395 for (i = 0; i < count; i++) {
2396 /* Check if we can read event header */
2332d0ae 2397 if (left_len < sizeof(*phyerr)) {
7aa7a72a
MK		 2398 ath10k_warn(ar, "single event (%d) wrong head len\n",
2399 i);
9702c686
JD		 2400 return;
2401 }
2402
2332d0ae 2403 left_len -= sizeof(*phyerr);
9702c686 2404
2332d0ae
MK		 2405 buf_len = __le32_to_cpu(phyerr->buf_len);
2406 phy_err_code = phyerr->phy_err_code;
9702c686
JD		 2407
2408 if (left_len < buf_len) {
7aa7a72a 2409 ath10k_warn(ar, "single event (%d) wrong buf len\n", i);
9702c686
JD		 2410 return;
2411 }
2412
2413 left_len -= buf_len;
2414
2415 switch (phy_err_code) {
2416 case PHY_ERROR_RADAR:
2332d0ae 2417 ath10k_wmi_event_dfs(ar, phyerr, tsf);
9702c686
JD		 2418 break;
2419 case PHY_ERROR_SPECTRAL_SCAN:
2332d0ae 2420 ath10k_wmi_event_spectral_scan(ar, phyerr, tsf);
9702c686
JD		 2421 break;
2422 case PHY_ERROR_FALSE_RADAR_EXT:
2332d0ae
MK		 2423 ath10k_wmi_event_dfs(ar, phyerr, tsf);
2424 ath10k_wmi_event_spectral_scan(ar, phyerr, tsf);
9702c686
JD		 2425 break;
2426 default:
2427 break;
2428 }
2429
2332d0ae 2430 phyerr = (void *)phyerr + sizeof(*phyerr) + buf_len;
9702c686 2431 }
5e3dd157
KV		 2432}
2433
2434static void ath10k_wmi_event_roam(struct ath10k *ar, struct sk_buff *skb)
2435{
7aa7a72a 2436 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_ROAM_EVENTID\n");
5e3dd157
KV		 2437}
2438
2439static void ath10k_wmi_event_profile_match(struct ath10k *ar,
5b07e07f 2440 struct sk_buff *skb)
5e3dd157 2441{
7aa7a72a 2442 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_PROFILE_MATCH\n");
5e3dd157
KV		 2443}
2444
2445static void ath10k_wmi_event_debug_print(struct ath10k *ar,
2fe5288c 2446 struct sk_buff *skb)
5e3dd157 2447{
2fe5288c
KV		 2448 char buf[101], c;
2449 int i;
2450
2451 for (i = 0; i < sizeof(buf) - 1; i++) {
2452 if (i >= skb->len)
2453 break;
2454
2455 c = skb->data[i];
2456
2457 if (c == '\0')
2458 break;
2459
2460 if (isascii(c) && isprint(c))
2461 buf[i] = c;
2462 else
2463 buf[i] = '.';
2464 }
2465
2466 if (i == sizeof(buf) - 1)
7aa7a72a 2467 ath10k_warn(ar, "wmi debug print truncated: %d\n", skb->len);
2fe5288c
KV		 2468
2469 /* for some reason the debug prints end with \n, remove that */
2470 if (skb->data[i - 1] == '\n')
2471 i--;
2472
2473 /* the last byte is always reserved for the null character */
2474 buf[i] = '\0';
2475
3be004c3 2476 ath10k_dbg(ar, ATH10K_DBG_WMI_PRINT, "wmi print '%s'\n", buf);
5e3dd157
KV		 2477}
2478
2479static void ath10k_wmi_event_pdev_qvit(struct ath10k *ar, struct sk_buff *skb)
2480{
7aa7a72a 2481 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_PDEV_QVIT_EVENTID\n");
5e3dd157
KV		 2482}
2483
2484static void ath10k_wmi_event_wlan_profile_data(struct ath10k *ar,
2485 struct sk_buff *skb)
2486{
7aa7a72a 2487 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_WLAN_PROFILE_DATA_EVENTID\n");
5e3dd157
KV		 2488}
2489
2490static void ath10k_wmi_event_rtt_measurement_report(struct ath10k *ar,
5b07e07f 2491 struct sk_buff *skb)
5e3dd157 2492{
7aa7a72a 2493 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_RTT_MEASUREMENT_REPORT_EVENTID\n");
5e3dd157
KV		 2494}
2495
2496static void ath10k_wmi_event_tsf_measurement_report(struct ath10k *ar,
5b07e07f 2497 struct sk_buff *skb)
5e3dd157 2498{
7aa7a72a 2499 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_TSF_MEASUREMENT_REPORT_EVENTID\n");
5e3dd157
KV		 2500}
2501
2502static void ath10k_wmi_event_rtt_error_report(struct ath10k *ar,
2503 struct sk_buff *skb)
2504{
7aa7a72a 2505 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_RTT_ERROR_REPORT_EVENTID\n");
5e3dd157
KV		 2506}
2507
2508static void ath10k_wmi_event_wow_wakeup_host(struct ath10k *ar,
2509 struct sk_buff *skb)
2510{
7aa7a72a 2511 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_WOW_WAKEUP_HOST_EVENTID\n");
5e3dd157
KV		 2512}
2513
2514static void ath10k_wmi_event_dcs_interference(struct ath10k *ar,
2515 struct sk_buff *skb)
2516{
7aa7a72a 2517 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_DCS_INTERFERENCE_EVENTID\n");
5e3dd157
KV		 2518}
2519
2520static void ath10k_wmi_event_pdev_tpc_config(struct ath10k *ar,
2521 struct sk_buff *skb)
2522{
7aa7a72a 2523 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_PDEV_TPC_CONFIG_EVENTID\n");
5e3dd157
KV		 2524}
2525
2526static void ath10k_wmi_event_pdev_ftm_intg(struct ath10k *ar,
2527 struct sk_buff *skb)
2528{
7aa7a72a 2529 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_PDEV_FTM_INTG_EVENTID\n");
5e3dd157
KV		 2530}
2531
2532static void ath10k_wmi_event_gtk_offload_status(struct ath10k *ar,
5b07e07f 2533 struct sk_buff *skb)
5e3dd157 2534{
7aa7a72a 2535 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_GTK_OFFLOAD_STATUS_EVENTID\n");
5e3dd157
KV		 2536}
2537
2538static void ath10k_wmi_event_gtk_rekey_fail(struct ath10k *ar,
2539 struct sk_buff *skb)
2540{
7aa7a72a 2541 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_GTK_REKEY_FAIL_EVENTID\n");
5e3dd157
KV		 2542}
2543
2544static void ath10k_wmi_event_delba_complete(struct ath10k *ar,
2545 struct sk_buff *skb)
2546{
7aa7a72a 2547 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_TX_DELBA_COMPLETE_EVENTID\n");
5e3dd157
KV		 2548}
2549
2550static void ath10k_wmi_event_addba_complete(struct ath10k *ar,
2551 struct sk_buff *skb)
2552{
7aa7a72a 2553 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_TX_ADDBA_COMPLETE_EVENTID\n");
5e3dd157
KV		 2554}
2555
2556static void ath10k_wmi_event_vdev_install_key_complete(struct ath10k *ar,
5b07e07f 2557 struct sk_buff *skb)
5e3dd157 2558{
7aa7a72a 2559 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID\n");
5e3dd157
KV		 2560}
2561
8a6618b0
BM		 2562static void ath10k_wmi_event_inst_rssi_stats(struct ath10k *ar,
2563 struct sk_buff *skb)
2564{
7aa7a72a 2565 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_INST_RSSI_STATS_EVENTID\n");
8a6618b0
BM		 2566}
2567
2568static void ath10k_wmi_event_vdev_standby_req(struct ath10k *ar,
2569 struct sk_buff *skb)
2570{
7aa7a72a 2571 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_VDEV_STANDBY_REQ_EVENTID\n");
8a6618b0
BM		 2572}
2573
2574static void ath10k_wmi_event_vdev_resume_req(struct ath10k *ar,
2575 struct sk_buff *skb)
2576{
7aa7a72a 2577 ath10k_dbg(ar, ATH10K_DBG_WMI, "WMI_VDEV_RESUME_REQ_EVENTID\n");
8a6618b0
BM		 2578}
2579
b3effe61 2580static int ath10k_wmi_alloc_host_mem(struct ath10k *ar, u32 req_id,
5b07e07f 2581 u32 num_units, u32 unit_len)
b3effe61
BM		 2582{
2583 dma_addr_t paddr;
2584 u32 pool_size;
2585 int idx = ar->wmi.num_mem_chunks;
2586
2587 pool_size = num_units * round_up(unit_len, 4);
2588
2589 if (!pool_size)
2590 return -EINVAL;
2591
2592 ar->wmi.mem_chunks[idx].vaddr = dma_alloc_coherent(ar->dev,
2593 pool_size,
2594 &paddr,
2595 GFP_ATOMIC);
2596 if (!ar->wmi.mem_chunks[idx].vaddr) {
7aa7a72a 2597 ath10k_warn(ar, "failed to allocate memory chunk\n");
b3effe61
BM		 2598 return -ENOMEM;
2599 }
2600
2601 memset(ar->wmi.mem_chunks[idx].vaddr, 0, pool_size);
2602
2603 ar->wmi.mem_chunks[idx].paddr = paddr;
2604 ar->wmi.mem_chunks[idx].len = pool_size;
2605 ar->wmi.mem_chunks[idx].req_id = req_id;
2606 ar->wmi.num_mem_chunks++;
2607
2608 return 0;
2609}
2610
5c01aa3d
MK		 2611static int ath10k_wmi_main_pull_svc_rdy_ev(struct sk_buff *skb,
2612 struct wmi_svc_rdy_ev_arg *arg)
2613{
2614 struct wmi_service_ready_event *ev;
2615 size_t i, n;
2616
2617 if (skb->len < sizeof(*ev))
2618 return -EPROTO;
2619
2620 ev = (void *)skb->data;
2621 skb_pull(skb, sizeof(*ev));
2622 arg->min_tx_power = ev->hw_min_tx_power;
2623 arg->max_tx_power = ev->hw_max_tx_power;
2624 arg->ht_cap = ev->ht_cap_info;
2625 arg->vht_cap = ev->vht_cap_info;
2626 arg->sw_ver0 = ev->sw_version;
2627 arg->sw_ver1 = ev->sw_version_1;
2628 arg->phy_capab = ev->phy_capability;
2629 arg->num_rf_chains = ev->num_rf_chains;
2630 arg->eeprom_rd = ev->hal_reg_capabilities.eeprom_rd;
2631 arg->num_mem_reqs = ev->num_mem_reqs;
2632 arg->service_map = ev->wmi_service_bitmap;
2a3e60d3 2633 arg->service_map_len = sizeof(ev->wmi_service_bitmap);
5c01aa3d
MK		 2634
2635 n = min_t(size_t, __le32_to_cpu(arg->num_mem_reqs),
2636 ARRAY_SIZE(arg->mem_reqs));
2637 for (i = 0; i < n; i++)
2638 arg->mem_reqs[i] = &ev->mem_reqs[i];
2639
2640 if (skb->len <
2641 __le32_to_cpu(arg->num_mem_reqs) * sizeof(arg->mem_reqs[0]))
2642 return -EPROTO;
2643
2644 return 0;
2645}
2646
2647static int ath10k_wmi_10x_pull_svc_rdy_ev(struct sk_buff *skb,
2648 struct wmi_svc_rdy_ev_arg *arg)
2649{
2650 struct wmi_10x_service_ready_event *ev;
2651 int i, n;
2652
2653 if (skb->len < sizeof(*ev))
2654 return -EPROTO;
2655
2656 ev = (void *)skb->data;
2657 skb_pull(skb, sizeof(*ev));
2658 arg->min_tx_power = ev->hw_min_tx_power;
2659 arg->max_tx_power = ev->hw_max_tx_power;
2660 arg->ht_cap = ev->ht_cap_info;
2661 arg->vht_cap = ev->vht_cap_info;
2662 arg->sw_ver0 = ev->sw_version;
2663 arg->phy_capab = ev->phy_capability;
2664 arg->num_rf_chains = ev->num_rf_chains;
2665 arg->eeprom_rd = ev->hal_reg_capabilities.eeprom_rd;
2666 arg->num_mem_reqs = ev->num_mem_reqs;
2667 arg->service_map = ev->wmi_service_bitmap;
2a3e60d3 2668 arg->service_map_len = sizeof(ev->wmi_service_bitmap);
5c01aa3d
MK		 2669
2670 n = min_t(size_t, __le32_to_cpu(arg->num_mem_reqs),
2671 ARRAY_SIZE(arg->mem_reqs));
2672 for (i = 0; i < n; i++)
2673 arg->mem_reqs[i] = &ev->mem_reqs[i];
2674
2675 if (skb->len <
2676 __le32_to_cpu(arg->num_mem_reqs) * sizeof(arg->mem_reqs[0]))
2677 return -EPROTO;
2678
2679 return 0;
2680}
2681
b34d2b3d
MK		 2682static void ath10k_wmi_event_service_ready(struct ath10k *ar,
2683 struct sk_buff *skb)
5e3dd157 2684{
5c01aa3d
MK		 2685 struct wmi_svc_rdy_ev_arg arg = {};
2686 u32 num_units, req_id, unit_size, num_mem_reqs, num_unit_info, i;
5c01aa3d
MK		 2687 int ret;
2688
acfe7ecf
MK		 2689 memset(&ar->wmi.svc_map, 0, sizeof(ar->wmi.svc_map));
2690
5c01aa3d
MK		 2691 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) {
2692 ret = ath10k_wmi_10x_pull_svc_rdy_ev(skb, &arg);
acfe7ecf 2693 wmi_10x_svc_map(arg.service_map, ar->wmi.svc_map,
37b9f933 2694 arg.service_map_len);
5c01aa3d
MK		 2695 } else {
2696 ret = ath10k_wmi_main_pull_svc_rdy_ev(skb, &arg);
acfe7ecf 2697 wmi_main_svc_map(arg.service_map, ar->wmi.svc_map,
37b9f933 2698 arg.service_map_len);
5c01aa3d 2699 }
5e3dd157 2700
5c01aa3d
MK		 2701 if (ret) {
2702 ath10k_warn(ar, "failed to parse service ready: %d\n", ret);
5e3dd157
KV		 2703 return;
2704 }
2705
5c01aa3d
MK		 2706 ar->hw_min_tx_power = __le32_to_cpu(arg.min_tx_power);
2707 ar->hw_max_tx_power = __le32_to_cpu(arg.max_tx_power);
2708 ar->ht_cap_info = __le32_to_cpu(arg.ht_cap);
2709 ar->vht_cap_info = __le32_to_cpu(arg.vht_cap);
5e3dd157 2710 ar->fw_version_major =
5c01aa3d
MK		 2711 (__le32_to_cpu(arg.sw_ver0) & 0xff000000) >> 24;
2712 ar->fw_version_minor = (__le32_to_cpu(arg.sw_ver0) & 0x00ffffff);
5e3dd157 2713 ar->fw_version_release =
5c01aa3d
MK		 2714 (__le32_to_cpu(arg.sw_ver1) & 0xffff0000) >> 16;
2715 ar->fw_version_build = (__le32_to_cpu(arg.sw_ver1) & 0x0000ffff);
2716 ar->phy_capability = __le32_to_cpu(arg.phy_capab);
2717 ar->num_rf_chains = __le32_to_cpu(arg.num_rf_chains);
2718 ar->ath_common.regulatory.current_rd = __le32_to_cpu(arg.eeprom_rd);
2719
5c01aa3d 2720 ath10k_dbg_dump(ar, ATH10K_DBG_WMI, NULL, "wmi svc: ",
2a3e60d3 2721 arg.service_map, arg.service_map_len);
8865bee4 2722
1a222435
KV		 2723 /* only manually set fw features when not using FW IE format */
2724 if (ar->fw_api == 1 && ar->fw_version_build > 636)
0d9b0438
MK		 2725 set_bit(ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX, ar->fw_features);
2726
8865bee4 2727 if (ar->num_rf_chains > WMI_MAX_SPATIAL_STREAM) {
7aa7a72a 2728 ath10k_warn(ar, "hardware advertises support for more spatial streams than it should (%d > %d)\n",
8865bee4
MK		 2729 ar->num_rf_chains, WMI_MAX_SPATIAL_STREAM);
2730 ar->num_rf_chains = WMI_MAX_SPATIAL_STREAM;
2731 }
5e3dd157 2732
fdb959c7
MK		 2733 ar->supp_tx_chainmask = (1 << ar->num_rf_chains) - 1;
2734 ar->supp_rx_chainmask = (1 << ar->num_rf_chains) - 1;
2735
5e3dd157
KV		 2736 if (strlen(ar->hw->wiphy->fw_version) == 0) {
2737 snprintf(ar->hw->wiphy->fw_version,
2738 sizeof(ar->hw->wiphy->fw_version),
2739 "%u.%u.%u.%u",
2740 ar->fw_version_major,
2741 ar->fw_version_minor,
2742 ar->fw_version_release,
2743 ar->fw_version_build);
2744 }
2745
5c01aa3d
MK		 2746 num_mem_reqs = __le32_to_cpu(arg.num_mem_reqs);
2747 if (num_mem_reqs > WMI_MAX_MEM_REQS) {
7aa7a72a 2748 ath10k_warn(ar, "requested memory chunks number (%d) exceeds the limit\n",
b3effe61
BM		 2749 num_mem_reqs);
2750 return;
6f97d256
BM		 2751 }
2752
b3effe61 2753 for (i = 0; i < num_mem_reqs; ++i) {
5c01aa3d
MK		 2754 req_id = __le32_to_cpu(arg.mem_reqs[i]->req_id);
2755 num_units = __le32_to_cpu(arg.mem_reqs[i]->num_units);
2756 unit_size = __le32_to_cpu(arg.mem_reqs[i]->unit_size);
2757 num_unit_info = __le32_to_cpu(arg.mem_reqs[i]->num_unit_info);
b3effe61
BM		 2758
2759 if (num_unit_info & NUM_UNITS_IS_NUM_PEERS)
2760 /* number of units to allocate is number of
2761 * peers, 1 extra for self peer on target */
2762 /* this needs to be tied, host and target
2763 * can get out of sync */
ec6a73f0 2764 num_units = TARGET_10X_NUM_PEERS + 1;
b3effe61 2765 else if (num_unit_info & NUM_UNITS_IS_NUM_VDEVS)
ec6a73f0 2766 num_units = TARGET_10X_NUM_VDEVS + 1;
b3effe61 2767
7aa7a72a 2768 ath10k_dbg(ar, ATH10K_DBG_WMI,
b3effe61
BM		 2769 "wmi mem_req_id %d num_units %d num_unit_info %d unit size %d actual units %d\n",
2770 req_id,
5c01aa3d 2771 __le32_to_cpu(arg.mem_reqs[i]->num_units),
b3effe61
BM		 2772 num_unit_info,
2773 unit_size,
2774 num_units);
2775
2776 ret = ath10k_wmi_alloc_host_mem(ar, req_id, num_units,
2777 unit_size);
2778 if (ret)
2779 return;
2780 }
2781
7aa7a72a 2782 ath10k_dbg(ar, ATH10K_DBG_WMI,
5c01aa3d
MK		 2783 "wmi event service ready min_tx_power 0x%08x max_tx_power 0x%08x ht_cap 0x%08x vht_cap 0x%08x sw_ver0 0x%08x sw_ver1 0x%08x phy_capab 0x%08x num_rf_chains 0x%08x eeprom_rd 0x%08x num_mem_reqs 0x%08x\n",
2784 __le32_to_cpu(arg.min_tx_power),
2785 __le32_to_cpu(arg.max_tx_power),
2786 __le32_to_cpu(arg.ht_cap),
2787 __le32_to_cpu(arg.vht_cap),
2788 __le32_to_cpu(arg.sw_ver0),
2789 __le32_to_cpu(arg.sw_ver1),
2790 __le32_to_cpu(arg.phy_capab),
2791 __le32_to_cpu(arg.num_rf_chains),
2792 __le32_to_cpu(arg.eeprom_rd),
2793 __le32_to_cpu(arg.num_mem_reqs));
6f97d256
BM		 2794
2795 complete(&ar->wmi.service_ready);
2796}
2797
32653cf1
MK		 2798static int ath10k_wmi_pull_rdy_ev(struct sk_buff *skb,
2799 struct wmi_rdy_ev_arg *arg)
5e3dd157 2800{
32653cf1 2801 struct wmi_ready_event *ev = (void *)skb->data;
5e3dd157 2802
32653cf1
MK		 2803 if (skb->len < sizeof(*ev))
2804 return -EPROTO;
2805
2806 skb_pull(skb, sizeof(*ev));
2807 arg->sw_version = ev->sw_version;
2808 arg->abi_version = ev->abi_version;
2809 arg->status = ev->status;
2810 arg->mac_addr = ev->mac_addr.addr;
2811
2812 return 0;
2813}
5e3dd157 2814
32653cf1
MK		 2815static int ath10k_wmi_event_ready(struct ath10k *ar, struct sk_buff *skb)
2816{
2817 struct wmi_rdy_ev_arg arg = {};
2818 int ret;
2819
2820 ret = ath10k_wmi_pull_rdy_ev(skb, &arg);
2821 if (ret) {
2822 ath10k_warn(ar, "failed to parse ready event: %d\n", ret);
2823 return ret;
2824 }
5e3dd157 2825
7aa7a72a 2826 ath10k_dbg(ar, ATH10K_DBG_WMI,
32653cf1
MK		 2827 "wmi event ready sw_version %u abi_version %u mac_addr %pM status %d\n",
2828 __le32_to_cpu(arg.sw_version),
2829 __le32_to_cpu(arg.abi_version),
2830 arg.mac_addr,
2831 __le32_to_cpu(arg.status));
5e3dd157 2832
32653cf1 2833 ether_addr_copy(ar->mac_addr, arg.mac_addr);
5e3dd157
KV		 2834 complete(&ar->wmi.unified_ready);
2835 return 0;
2836}
2837
ce42870e 2838static void ath10k_wmi_main_process_rx(struct ath10k *ar, struct sk_buff *skb)
5e3dd157
KV		 2839{
2840 struct wmi_cmd_hdr *cmd_hdr;
2841 enum wmi_event_id id;
5e3dd157
KV		 2842
2843 cmd_hdr = (struct wmi_cmd_hdr *)skb->data;
2844 id = MS(__le32_to_cpu(cmd_hdr->cmd_id), WMI_CMD_HDR_CMD_ID);
2845
2846 if (skb_pull(skb, sizeof(struct wmi_cmd_hdr)) == NULL)
2847 return;
2848
d35a6c18 2849 trace_ath10k_wmi_event(ar, id, skb->data, skb->len);
5e3dd157
KV		 2850
2851 switch (id) {
2852 case WMI_MGMT_RX_EVENTID:
2853 ath10k_wmi_event_mgmt_rx(ar, skb);
2854 /* mgmt_rx() owns the skb now! */
2855 return;
2856 case WMI_SCAN_EVENTID:
2857 ath10k_wmi_event_scan(ar, skb);
2858 break;
2859 case WMI_CHAN_INFO_EVENTID:
2860 ath10k_wmi_event_chan_info(ar, skb);
2861 break;
2862 case WMI_ECHO_EVENTID:
2863 ath10k_wmi_event_echo(ar, skb);
2864 break;
2865 case WMI_DEBUG_MESG_EVENTID:
2866 ath10k_wmi_event_debug_mesg(ar, skb);
2867 break;
2868 case WMI_UPDATE_STATS_EVENTID:
2869 ath10k_wmi_event_update_stats(ar, skb);
2870 break;
2871 case WMI_VDEV_START_RESP_EVENTID:
2872 ath10k_wmi_event_vdev_start_resp(ar, skb);
2873 break;
2874 case WMI_VDEV_STOPPED_EVENTID:
2875 ath10k_wmi_event_vdev_stopped(ar, skb);
2876 break;
2877 case WMI_PEER_STA_KICKOUT_EVENTID:
2878 ath10k_wmi_event_peer_sta_kickout(ar, skb);
2879 break;
2880 case WMI_HOST_SWBA_EVENTID:
2881 ath10k_wmi_event_host_swba(ar, skb);
2882 break;
2883 case WMI_TBTTOFFSET_UPDATE_EVENTID:
2884 ath10k_wmi_event_tbttoffset_update(ar, skb);
2885 break;
2886 case WMI_PHYERR_EVENTID:
2887 ath10k_wmi_event_phyerr(ar, skb);
2888 break;
2889 case WMI_ROAM_EVENTID:
2890 ath10k_wmi_event_roam(ar, skb);
2891 break;
2892 case WMI_PROFILE_MATCH:
2893 ath10k_wmi_event_profile_match(ar, skb);
2894 break;
2895 case WMI_DEBUG_PRINT_EVENTID:
2896 ath10k_wmi_event_debug_print(ar, skb);
2897 break;
2898 case WMI_PDEV_QVIT_EVENTID:
2899 ath10k_wmi_event_pdev_qvit(ar, skb);
2900 break;
2901 case WMI_WLAN_PROFILE_DATA_EVENTID:
2902 ath10k_wmi_event_wlan_profile_data(ar, skb);
2903 break;
2904 case WMI_RTT_MEASUREMENT_REPORT_EVENTID:
2905 ath10k_wmi_event_rtt_measurement_report(ar, skb);
2906 break;
2907 case WMI_TSF_MEASUREMENT_REPORT_EVENTID:
2908 ath10k_wmi_event_tsf_measurement_report(ar, skb);
2909 break;
2910 case WMI_RTT_ERROR_REPORT_EVENTID:
2911 ath10k_wmi_event_rtt_error_report(ar, skb);
2912 break;
2913 case WMI_WOW_WAKEUP_HOST_EVENTID:
2914 ath10k_wmi_event_wow_wakeup_host(ar, skb);
2915 break;
2916 case WMI_DCS_INTERFERENCE_EVENTID:
2917 ath10k_wmi_event_dcs_interference(ar, skb);
2918 break;
2919 case WMI_PDEV_TPC_CONFIG_EVENTID:
2920 ath10k_wmi_event_pdev_tpc_config(ar, skb);
2921 break;
2922 case WMI_PDEV_FTM_INTG_EVENTID:
2923 ath10k_wmi_event_pdev_ftm_intg(ar, skb);
2924 break;
2925 case WMI_GTK_OFFLOAD_STATUS_EVENTID:
2926 ath10k_wmi_event_gtk_offload_status(ar, skb);
2927 break;
2928 case WMI_GTK_REKEY_FAIL_EVENTID:
2929 ath10k_wmi_event_gtk_rekey_fail(ar, skb);
2930 break;
2931 case WMI_TX_DELBA_COMPLETE_EVENTID:
2932 ath10k_wmi_event_delba_complete(ar, skb);
2933 break;
2934 case WMI_TX_ADDBA_COMPLETE_EVENTID:
2935 ath10k_wmi_event_addba_complete(ar, skb);
2936 break;
2937 case WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID:
2938 ath10k_wmi_event_vdev_install_key_complete(ar, skb);
2939 break;
2940 case WMI_SERVICE_READY_EVENTID:
b34d2b3d 2941 ath10k_wmi_event_service_ready(ar, skb);
5e3dd157
KV		 2942 break;
2943 case WMI_READY_EVENTID:
b34d2b3d 2944 ath10k_wmi_event_ready(ar, skb);
5e3dd157
KV		 2945 break;
2946 default:
7aa7a72a 2947 ath10k_warn(ar, "Unknown eventid: %d\n", id);
5e3dd157
KV		 2948 break;
2949 }
2950
2951 dev_kfree_skb(skb);
2952}
2953
8a6618b0
BM		 2954static void ath10k_wmi_10x_process_rx(struct ath10k *ar, struct sk_buff *skb)
2955{
2956 struct wmi_cmd_hdr *cmd_hdr;
2957 enum wmi_10x_event_id id;
43d2a30f 2958 bool consumed;
8a6618b0
BM		 2959
2960 cmd_hdr = (struct wmi_cmd_hdr *)skb->data;
2961 id = MS(__le32_to_cpu(cmd_hdr->cmd_id), WMI_CMD_HDR_CMD_ID);
2962
2963 if (skb_pull(skb, sizeof(struct wmi_cmd_hdr)) == NULL)
2964 return;
2965
d35a6c18 2966 trace_ath10k_wmi_event(ar, id, skb->data, skb->len);
8a6618b0 2967
43d2a30f
KV		 2968 consumed = ath10k_tm_event_wmi(ar, id, skb);
2969
2970 /* Ready event must be handled normally also in UTF mode so that we
2971 * know the UTF firmware has booted, others we are just bypass WMI
2972 * events to testmode.
2973 */
2974 if (consumed && id != WMI_10X_READY_EVENTID) {
2975 ath10k_dbg(ar, ATH10K_DBG_WMI,
2976 "wmi testmode consumed 0x%x\n", id);
2977 goto out;
2978 }
2979
8a6618b0
BM		 2980 switch (id) {
2981 case WMI_10X_MGMT_RX_EVENTID:
2982 ath10k_wmi_event_mgmt_rx(ar, skb);
2983 /* mgmt_rx() owns the skb now! */
2984 return;
2985 case WMI_10X_SCAN_EVENTID:
2986 ath10k_wmi_event_scan(ar, skb);
2987 break;
2988 case WMI_10X_CHAN_INFO_EVENTID:
2989 ath10k_wmi_event_chan_info(ar, skb);
2990 break;
2991 case WMI_10X_ECHO_EVENTID:
2992 ath10k_wmi_event_echo(ar, skb);
2993 break;
2994 case WMI_10X_DEBUG_MESG_EVENTID:
2995 ath10k_wmi_event_debug_mesg(ar, skb);
2996 break;
2997 case WMI_10X_UPDATE_STATS_EVENTID:
2998 ath10k_wmi_event_update_stats(ar, skb);
2999 break;
3000 case WMI_10X_VDEV_START_RESP_EVENTID:
3001 ath10k_wmi_event_vdev_start_resp(ar, skb);
3002 break;
3003 case WMI_10X_VDEV_STOPPED_EVENTID:
3004 ath10k_wmi_event_vdev_stopped(ar, skb);
3005 break;
3006 case WMI_10X_PEER_STA_KICKOUT_EVENTID:
3007 ath10k_wmi_event_peer_sta_kickout(ar, skb);
3008 break;
3009 case WMI_10X_HOST_SWBA_EVENTID:
3010 ath10k_wmi_event_host_swba(ar, skb);
3011 break;
3012 case WMI_10X_TBTTOFFSET_UPDATE_EVENTID:
3013 ath10k_wmi_event_tbttoffset_update(ar, skb);
3014 break;
3015 case WMI_10X_PHYERR_EVENTID:
3016 ath10k_wmi_event_phyerr(ar, skb);
3017 break;
3018 case WMI_10X_ROAM_EVENTID:
3019 ath10k_wmi_event_roam(ar, skb);
3020 break;
3021 case WMI_10X_PROFILE_MATCH:
3022 ath10k_wmi_event_profile_match(ar, skb);
3023 break;
3024 case WMI_10X_DEBUG_PRINT_EVENTID:
3025 ath10k_wmi_event_debug_print(ar, skb);
3026 break;
3027 case WMI_10X_PDEV_QVIT_EVENTID:
3028 ath10k_wmi_event_pdev_qvit(ar, skb);
3029 break;
3030 case WMI_10X_WLAN_PROFILE_DATA_EVENTID:
3031 ath10k_wmi_event_wlan_profile_data(ar, skb);
3032 break;
3033 case WMI_10X_RTT_MEASUREMENT_REPORT_EVENTID:
3034 ath10k_wmi_event_rtt_measurement_report(ar, skb);
3035 break;
3036 case WMI_10X_TSF_MEASUREMENT_REPORT_EVENTID:
3037 ath10k_wmi_event_tsf_measurement_report(ar, skb);
3038 break;
3039 case WMI_10X_RTT_ERROR_REPORT_EVENTID:
3040 ath10k_wmi_event_rtt_error_report(ar, skb);
3041 break;
3042 case WMI_10X_WOW_WAKEUP_HOST_EVENTID:
3043 ath10k_wmi_event_wow_wakeup_host(ar, skb);
3044 break;
3045 case WMI_10X_DCS_INTERFERENCE_EVENTID:
3046 ath10k_wmi_event_dcs_interference(ar, skb);
3047 break;
3048 case WMI_10X_PDEV_TPC_CONFIG_EVENTID:
3049 ath10k_wmi_event_pdev_tpc_config(ar, skb);
3050 break;
3051 case WMI_10X_INST_RSSI_STATS_EVENTID:
3052 ath10k_wmi_event_inst_rssi_stats(ar, skb);
3053 break;
3054 case WMI_10X_VDEV_STANDBY_REQ_EVENTID:
3055 ath10k_wmi_event_vdev_standby_req(ar, skb);
3056 break;
3057 case WMI_10X_VDEV_RESUME_REQ_EVENTID:
3058 ath10k_wmi_event_vdev_resume_req(ar, skb);
3059 break;
3060 case WMI_10X_SERVICE_READY_EVENTID:
b34d2b3d 3061 ath10k_wmi_event_service_ready(ar, skb);
8a6618b0
BM		 3062 break;
3063 case WMI_10X_READY_EVENTID:
b34d2b3d 3064 ath10k_wmi_event_ready(ar, skb);
8a6618b0 3065 break;
43d2a30f
KV		 3066 case WMI_10X_PDEV_UTF_EVENTID:
3067 /* ignore utf events */
3068 break;
8a6618b0 3069 default:
7aa7a72a 3070 ath10k_warn(ar, "Unknown eventid: %d\n", id);
8a6618b0
BM		 3071 break;
3072 }
3073
43d2a30f 3074out:
8a6618b0
BM		 3075 dev_kfree_skb(skb);
3076}
3077
24c88f78
MK		 3078static void ath10k_wmi_10_2_process_rx(struct ath10k *ar, struct sk_buff *skb)
3079{
3080 struct wmi_cmd_hdr *cmd_hdr;
3081 enum wmi_10_2_event_id id;
3082
3083 cmd_hdr = (struct wmi_cmd_hdr *)skb->data;
3084 id = MS(__le32_to_cpu(cmd_hdr->cmd_id), WMI_CMD_HDR_CMD_ID);
3085
3086 if (skb_pull(skb, sizeof(struct wmi_cmd_hdr)) == NULL)
3087 return;
3088
d35a6c18 3089 trace_ath10k_wmi_event(ar, id, skb->data, skb->len);
24c88f78
MK		 3090
3091 switch (id) {
3092 case WMI_10_2_MGMT_RX_EVENTID:
3093 ath10k_wmi_event_mgmt_rx(ar, skb);
3094 /* mgmt_rx() owns the skb now! */
3095 return;
3096 case WMI_10_2_SCAN_EVENTID:
3097 ath10k_wmi_event_scan(ar, skb);
3098 break;
3099 case WMI_10_2_CHAN_INFO_EVENTID:
3100 ath10k_wmi_event_chan_info(ar, skb);
3101 break;
3102 case WMI_10_2_ECHO_EVENTID:
3103 ath10k_wmi_event_echo(ar, skb);
3104 break;
3105 case WMI_10_2_DEBUG_MESG_EVENTID:
3106 ath10k_wmi_event_debug_mesg(ar, skb);
3107 break;
3108 case WMI_10_2_UPDATE_STATS_EVENTID:
3109 ath10k_wmi_event_update_stats(ar, skb);
3110 break;
3111 case WMI_10_2_VDEV_START_RESP_EVENTID:
3112 ath10k_wmi_event_vdev_start_resp(ar, skb);
3113 break;
3114 case WMI_10_2_VDEV_STOPPED_EVENTID:
3115 ath10k_wmi_event_vdev_stopped(ar, skb);
3116 break;
3117 case WMI_10_2_PEER_STA_KICKOUT_EVENTID:
3118 ath10k_wmi_event_peer_sta_kickout(ar, skb);
3119 break;
3120 case WMI_10_2_HOST_SWBA_EVENTID:
3121 ath10k_wmi_event_host_swba(ar, skb);
3122 break;
3123 case WMI_10_2_TBTTOFFSET_UPDATE_EVENTID:
3124 ath10k_wmi_event_tbttoffset_update(ar, skb);
3125 break;
3126 case WMI_10_2_PHYERR_EVENTID:
3127 ath10k_wmi_event_phyerr(ar, skb);
3128 break;
3129 case WMI_10_2_ROAM_EVENTID:
3130 ath10k_wmi_event_roam(ar, skb);
3131 break;
3132 case WMI_10_2_PROFILE_MATCH:
3133 ath10k_wmi_event_profile_match(ar, skb);
3134 break;
3135 case WMI_10_2_DEBUG_PRINT_EVENTID:
3136 ath10k_wmi_event_debug_print(ar, skb);
3137 break;
3138 case WMI_10_2_PDEV_QVIT_EVENTID:
3139 ath10k_wmi_event_pdev_qvit(ar, skb);
3140 break;
3141 case WMI_10_2_WLAN_PROFILE_DATA_EVENTID:
3142 ath10k_wmi_event_wlan_profile_data(ar, skb);
3143 break;
3144 case WMI_10_2_RTT_MEASUREMENT_REPORT_EVENTID:
3145 ath10k_wmi_event_rtt_measurement_report(ar, skb);
3146 break;
3147 case WMI_10_2_TSF_MEASUREMENT_REPORT_EVENTID:
3148 ath10k_wmi_event_tsf_measurement_report(ar, skb);
3149 break;
3150 case WMI_10_2_RTT_ERROR_REPORT_EVENTID:
3151 ath10k_wmi_event_rtt_error_report(ar, skb);
3152 break;
3153 case WMI_10_2_WOW_WAKEUP_HOST_EVENTID:
3154 ath10k_wmi_event_wow_wakeup_host(ar, skb);
3155 break;
3156 case WMI_10_2_DCS_INTERFERENCE_EVENTID:
3157 ath10k_wmi_event_dcs_interference(ar, skb);
3158 break;
3159 case WMI_10_2_PDEV_TPC_CONFIG_EVENTID:
3160 ath10k_wmi_event_pdev_tpc_config(ar, skb);
3161 break;
3162 case WMI_10_2_INST_RSSI_STATS_EVENTID:
3163 ath10k_wmi_event_inst_rssi_stats(ar, skb);
3164 break;
3165 case WMI_10_2_VDEV_STANDBY_REQ_EVENTID:
3166 ath10k_wmi_event_vdev_standby_req(ar, skb);
3167 break;
3168 case WMI_10_2_VDEV_RESUME_REQ_EVENTID:
3169 ath10k_wmi_event_vdev_resume_req(ar, skb);
3170 break;
3171 case WMI_10_2_SERVICE_READY_EVENTID:
b34d2b3d 3172 ath10k_wmi_event_service_ready(ar, skb);
24c88f78
MK		 3173 break;
3174 case WMI_10_2_READY_EVENTID:
b34d2b3d 3175 ath10k_wmi_event_ready(ar, skb);
24c88f78
MK		 3176 break;
3177 case WMI_10_2_RTT_KEEPALIVE_EVENTID:
3178 case WMI_10_2_GPIO_INPUT_EVENTID:
3179 case WMI_10_2_PEER_RATECODE_LIST_EVENTID:
3180 case WMI_10_2_GENERIC_BUFFER_EVENTID:
3181 case WMI_10_2_MCAST_BUF_RELEASE_EVENTID:
3182 case WMI_10_2_MCAST_LIST_AGEOUT_EVENTID:
3183 case WMI_10_2_WDS_PEER_EVENTID:
7aa7a72a 3184 ath10k_dbg(ar, ATH10K_DBG_WMI,
24c88f78
MK		 3185 "received event id %d not implemented\n", id);
3186 break;
3187 default:
7aa7a72a 3188 ath10k_warn(ar, "Unknown eventid: %d\n", id);
24c88f78
MK		 3189 break;
3190 }
3191
3192 dev_kfree_skb(skb);
3193}
8a6618b0 3194
ce42870e
BM		 3195static void ath10k_wmi_process_rx(struct ath10k *ar, struct sk_buff *skb)
3196{
24c88f78
MK		 3197 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) {
3198 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, ar->fw_features))
3199 ath10k_wmi_10_2_process_rx(ar, skb);
3200 else
3201 ath10k_wmi_10x_process_rx(ar, skb);
3202 } else {
ce42870e 3203 ath10k_wmi_main_process_rx(ar, skb);
24c88f78 3204 }
ce42870e
BM		 3205}
3206
95bf21f9 3207int ath10k_wmi_connect(struct ath10k *ar)
5e3dd157
KV		 3208{
3209 int status;
3210 struct ath10k_htc_svc_conn_req conn_req;
3211 struct ath10k_htc_svc_conn_resp conn_resp;
3212
3213 memset(&conn_req, 0, sizeof(conn_req));
3214 memset(&conn_resp, 0, sizeof(conn_resp));
3215
3216 /* these fields are the same for all service endpoints */
3217 conn_req.ep_ops.ep_tx_complete = ath10k_wmi_htc_tx_complete;
3218 conn_req.ep_ops.ep_rx_complete = ath10k_wmi_process_rx;
be8b3943 3219 conn_req.ep_ops.ep_tx_credits = ath10k_wmi_op_ep_tx_credits;
5e3dd157
KV		 3220
3221 /* connect to control service */
3222 conn_req.service_id = ATH10K_HTC_SVC_ID_WMI_CONTROL;
3223
cd003fad 3224 status = ath10k_htc_connect_service(&ar->htc, &conn_req, &conn_resp);
5e3dd157 3225 if (status) {
7aa7a72a 3226 ath10k_warn(ar, "failed to connect to WMI CONTROL service status: %d\n",
5e3dd157
KV		 3227 status);
3228 return status;
3229 }
3230
3231 ar->wmi.eid = conn_resp.eid;
3232 return 0;
3233}
3234
821af6ae
MP		 3235static int ath10k_wmi_main_pdev_set_regdomain(struct ath10k *ar, u16 rd,
3236 u16 rd2g, u16 rd5g, u16 ctl2g,
3237 u16 ctl5g)
5e3dd157
KV		 3238{
3239 struct wmi_pdev_set_regdomain_cmd *cmd;
3240 struct sk_buff *skb;
3241
7aa7a72a 3242 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 3243 if (!skb)
3244 return -ENOMEM;
3245
3246 cmd = (struct wmi_pdev_set_regdomain_cmd *)skb->data;
3247 cmd->reg_domain = __cpu_to_le32(rd);
3248 cmd->reg_domain_2G = __cpu_to_le32(rd2g);
3249 cmd->reg_domain_5G = __cpu_to_le32(rd5g);
3250 cmd->conformance_test_limit_2G = __cpu_to_le32(ctl2g);
3251 cmd->conformance_test_limit_5G = __cpu_to_le32(ctl5g);
3252
7aa7a72a 3253 ath10k_dbg(ar, ATH10K_DBG_WMI,
5e3dd157
KV		 3254 "wmi pdev regdomain rd %x rd2g %x rd5g %x ctl2g %x ctl5g %x\n",
3255 rd, rd2g, rd5g, ctl2g, ctl5g);
3256
ce42870e
BM		 3257 return ath10k_wmi_cmd_send(ar, skb,
3258 ar->wmi.cmd->pdev_set_regdomain_cmdid);
5e3dd157
KV		 3259}
3260
821af6ae
MP		 3261static int ath10k_wmi_10x_pdev_set_regdomain(struct ath10k *ar, u16 rd,
3262 u16 rd2g, u16 rd5g,
3263 u16 ctl2g, u16 ctl5g,
3264 enum wmi_dfs_region dfs_reg)
3265{
3266 struct wmi_pdev_set_regdomain_cmd_10x *cmd;
3267 struct sk_buff *skb;
3268
7aa7a72a 3269 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
821af6ae
MP		 3270 if (!skb)
3271 return -ENOMEM;
3272
3273 cmd = (struct wmi_pdev_set_regdomain_cmd_10x *)skb->data;
3274 cmd->reg_domain = __cpu_to_le32(rd);
3275 cmd->reg_domain_2G = __cpu_to_le32(rd2g);
3276 cmd->reg_domain_5G = __cpu_to_le32(rd5g);
3277 cmd->conformance_test_limit_2G = __cpu_to_le32(ctl2g);
3278 cmd->conformance_test_limit_5G = __cpu_to_le32(ctl5g);
3279 cmd->dfs_domain = __cpu_to_le32(dfs_reg);
3280
7aa7a72a 3281 ath10k_dbg(ar, ATH10K_DBG_WMI,
821af6ae
MP		 3282 "wmi pdev regdomain rd %x rd2g %x rd5g %x ctl2g %x ctl5g %x dfs_region %x\n",
3283 rd, rd2g, rd5g, ctl2g, ctl5g, dfs_reg);
3284
3285 return ath10k_wmi_cmd_send(ar, skb,
3286 ar->wmi.cmd->pdev_set_regdomain_cmdid);
3287}
3288
3289int ath10k_wmi_pdev_set_regdomain(struct ath10k *ar, u16 rd, u16 rd2g,
3290 u16 rd5g, u16 ctl2g, u16 ctl5g,
3291 enum wmi_dfs_region dfs_reg)
3292{
3293 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features))
3294 return ath10k_wmi_10x_pdev_set_regdomain(ar, rd, rd2g, rd5g,
3295 ctl2g, ctl5g, dfs_reg);
3296 else
3297 return ath10k_wmi_main_pdev_set_regdomain(ar, rd, rd2g, rd5g,
3298 ctl2g, ctl5g);
3299}
3300
00f5482b 3301int ath10k_wmi_pdev_suspend_target(struct ath10k *ar, u32 suspend_opt)
5e3dd157
KV		 3302{
3303 struct wmi_pdev_suspend_cmd *cmd;
3304 struct sk_buff *skb;
3305
7aa7a72a 3306 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 3307 if (!skb)
3308 return -ENOMEM;
3309
3310 cmd = (struct wmi_pdev_suspend_cmd *)skb->data;
00f5482b 3311 cmd->suspend_opt = __cpu_to_le32(suspend_opt);
5e3dd157 3312
ce42870e 3313 return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->pdev_suspend_cmdid);
5e3dd157
KV		 3314}
3315
3316int ath10k_wmi_pdev_resume_target(struct ath10k *ar)
3317{
3318 struct sk_buff *skb;
3319
7aa7a72a 3320 skb = ath10k_wmi_alloc_skb(ar, 0);
5e3dd157
KV		 3321 if (skb == NULL)
3322 return -ENOMEM;
3323
ce42870e 3324 return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->pdev_resume_cmdid);
5e3dd157
KV		 3325}
3326
226a339b 3327int ath10k_wmi_pdev_set_param(struct ath10k *ar, u32 id, u32 value)
5e3dd157
KV		 3328{
3329 struct wmi_pdev_set_param_cmd *cmd;
3330 struct sk_buff *skb;
3331
226a339b 3332 if (id == WMI_PDEV_PARAM_UNSUPPORTED) {
7aa7a72a
MK		 3333 ath10k_warn(ar, "pdev param %d not supported by firmware\n",
3334 id);
d544943a 3335 return -EOPNOTSUPP;
226a339b
BM		 3336 }
3337
7aa7a72a 3338 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 3339 if (!skb)
3340 return -ENOMEM;
3341
3342 cmd = (struct wmi_pdev_set_param_cmd *)skb->data;
3343 cmd->param_id = __cpu_to_le32(id);
3344 cmd->param_value = __cpu_to_le32(value);
3345
7aa7a72a 3346 ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi pdev set param %d value %d\n",
5e3dd157 3347 id, value);
ce42870e 3348 return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->pdev_set_param_cmdid);
5e3dd157
KV		 3349}
3350
cf9fca8f
MK		 3351static void ath10k_wmi_put_host_mem_chunks(struct ath10k *ar,
3352 struct wmi_host_mem_chunks *chunks)
3353{
3354 struct host_memory_chunk *chunk;
3355 int i;
3356
3357 chunks->count = __cpu_to_le32(ar->wmi.num_mem_chunks);
3358
3359 for (i = 0; i < ar->wmi.num_mem_chunks; i++) {
3360 chunk = &chunks->items[i];
3361 chunk->ptr = __cpu_to_le32(ar->wmi.mem_chunks[i].paddr);
3362 chunk->size = __cpu_to_le32(ar->wmi.mem_chunks[i].len);
3363 chunk->req_id = __cpu_to_le32(ar->wmi.mem_chunks[i].req_id);
3364
3365 ath10k_dbg(ar, ATH10K_DBG_WMI,
3366 "wmi chunk %d len %d requested, addr 0x%llx\n",
3367 i,
3368 ar->wmi.mem_chunks[i].len,
3369 (unsigned long long)ar->wmi.mem_chunks[i].paddr);
3370 }
3371}
3372
12b2b9e3 3373static int ath10k_wmi_main_cmd_init(struct ath10k *ar)
5e3dd157
KV		 3374{
3375 struct wmi_init_cmd *cmd;
3376 struct sk_buff *buf;
3377 struct wmi_resource_config config = {};
b3effe61 3378 u32 len, val;
5e3dd157
KV		 3379
3380 config.num_vdevs = __cpu_to_le32(TARGET_NUM_VDEVS);
cfd1061e 3381 config.num_peers = __cpu_to_le32(TARGET_NUM_PEERS);
5e3dd157
KV		 3382 config.num_offload_peers = __cpu_to_le32(TARGET_NUM_OFFLOAD_PEERS);
3383
3384 config.num_offload_reorder_bufs =
3385 __cpu_to_le32(TARGET_NUM_OFFLOAD_REORDER_BUFS);
3386
3387 config.num_peer_keys = __cpu_to_le32(TARGET_NUM_PEER_KEYS);
3388 config.num_tids = __cpu_to_le32(TARGET_NUM_TIDS);
3389 config.ast_skid_limit = __cpu_to_le32(TARGET_AST_SKID_LIMIT);
3390 config.tx_chain_mask = __cpu_to_le32(TARGET_TX_CHAIN_MASK);
3391 config.rx_chain_mask = __cpu_to_le32(TARGET_RX_CHAIN_MASK);
3392 config.rx_timeout_pri_vo = __cpu_to_le32(TARGET_RX_TIMEOUT_LO_PRI);
3393 config.rx_timeout_pri_vi = __cpu_to_le32(TARGET_RX_TIMEOUT_LO_PRI);
3394 config.rx_timeout_pri_be = __cpu_to_le32(TARGET_RX_TIMEOUT_LO_PRI);
3395 config.rx_timeout_pri_bk = __cpu_to_le32(TARGET_RX_TIMEOUT_HI_PRI);
3396 config.rx_decap_mode = __cpu_to_le32(TARGET_RX_DECAP_MODE);
3397
3398 config.scan_max_pending_reqs =
3399 __cpu_to_le32(TARGET_SCAN_MAX_PENDING_REQS);
3400
3401 config.bmiss_offload_max_vdev =
3402 __cpu_to_le32(TARGET_BMISS_OFFLOAD_MAX_VDEV);
3403
3404 config.roam_offload_max_vdev =
3405 __cpu_to_le32(TARGET_ROAM_OFFLOAD_MAX_VDEV);
3406
3407 config.roam_offload_max_ap_profiles =
3408 __cpu_to_le32(TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES);
3409
3410 config.num_mcast_groups = __cpu_to_le32(TARGET_NUM_MCAST_GROUPS);
3411 config.num_mcast_table_elems =
3412 __cpu_to_le32(TARGET_NUM_MCAST_TABLE_ELEMS);
3413
3414 config.mcast2ucast_mode = __cpu_to_le32(TARGET_MCAST2UCAST_MODE);
3415 config.tx_dbg_log_size = __cpu_to_le32(TARGET_TX_DBG_LOG_SIZE);
3416 config.num_wds_entries = __cpu_to_le32(TARGET_NUM_WDS_ENTRIES);
3417 config.dma_burst_size = __cpu_to_le32(TARGET_DMA_BURST_SIZE);
3418 config.mac_aggr_delim = __cpu_to_le32(TARGET_MAC_AGGR_DELIM);
3419
3420 val = TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK;
3421 config.rx_skip_defrag_timeout_dup_detection_check = __cpu_to_le32(val);
3422
3423 config.vow_config = __cpu_to_le32(TARGET_VOW_CONFIG);
3424
3425 config.gtk_offload_max_vdev =
3426 __cpu_to_le32(TARGET_GTK_OFFLOAD_MAX_VDEV);
3427
3428 config.num_msdu_desc = __cpu_to_le32(TARGET_NUM_MSDU_DESC);
3429 config.max_frag_entries = __cpu_to_le32(TARGET_MAX_FRAG_ENTRIES);
3430
b3effe61
BM		 3431 len = sizeof(*cmd) +
3432 (sizeof(struct host_memory_chunk) * ar->wmi.num_mem_chunks);
3433
7aa7a72a 3434 buf = ath10k_wmi_alloc_skb(ar, len);
5e3dd157
KV		 3435 if (!buf)
3436 return -ENOMEM;
3437
3438 cmd = (struct wmi_init_cmd *)buf->data;
b3effe61 3439
5e3dd157 3440 memcpy(&cmd->resource_config, &config, sizeof(config));
cf9fca8f 3441 ath10k_wmi_put_host_mem_chunks(ar, &cmd->mem_chunks);
5e3dd157 3442
7aa7a72a 3443 ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi init\n");
ce42870e 3444 return ath10k_wmi_cmd_send(ar, buf, ar->wmi.cmd->init_cmdid);
5e3dd157
KV		 3445}
3446
12b2b9e3
BM		 3447static int ath10k_wmi_10x_cmd_init(struct ath10k *ar)
3448{
3449 struct wmi_init_cmd_10x *cmd;
3450 struct sk_buff *buf;
3451 struct wmi_resource_config_10x config = {};
3452 u32 len, val;
12b2b9e3 3453
ec6a73f0
BM		 3454 config.num_vdevs = __cpu_to_le32(TARGET_10X_NUM_VDEVS);
3455 config.num_peers = __cpu_to_le32(TARGET_10X_NUM_PEERS);
3456 config.num_peer_keys = __cpu_to_le32(TARGET_10X_NUM_PEER_KEYS);
3457 config.num_tids = __cpu_to_le32(TARGET_10X_NUM_TIDS);
3458 config.ast_skid_limit = __cpu_to_le32(TARGET_10X_AST_SKID_LIMIT);
3459 config.tx_chain_mask = __cpu_to_le32(TARGET_10X_TX_CHAIN_MASK);
3460 config.rx_chain_mask = __cpu_to_le32(TARGET_10X_RX_CHAIN_MASK);
3461 config.rx_timeout_pri_vo = __cpu_to_le32(TARGET_10X_RX_TIMEOUT_LO_PRI);
3462 config.rx_timeout_pri_vi = __cpu_to_le32(TARGET_10X_RX_TIMEOUT_LO_PRI);
3463 config.rx_timeout_pri_be = __cpu_to_le32(TARGET_10X_RX_TIMEOUT_LO_PRI);
3464 config.rx_timeout_pri_bk = __cpu_to_le32(TARGET_10X_RX_TIMEOUT_HI_PRI);
3465 config.rx_decap_mode = __cpu_to_le32(TARGET_10X_RX_DECAP_MODE);
12b2b9e3
BM		 3466
3467 config.scan_max_pending_reqs =
ec6a73f0 3468 __cpu_to_le32(TARGET_10X_SCAN_MAX_PENDING_REQS);
12b2b9e3
BM		 3469
3470 config.bmiss_offload_max_vdev =
ec6a73f0 3471 __cpu_to_le32(TARGET_10X_BMISS_OFFLOAD_MAX_VDEV);
12b2b9e3
BM		 3472
3473 config.roam_offload_max_vdev =
ec6a73f0 3474 __cpu_to_le32(TARGET_10X_ROAM_OFFLOAD_MAX_VDEV);
12b2b9e3
BM		 3475
3476 config.roam_offload_max_ap_profiles =
ec6a73f0 3477 __cpu_to_le32(TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES);
12b2b9e3 3478
ec6a73f0 3479 config.num_mcast_groups = __cpu_to_le32(TARGET_10X_NUM_MCAST_GROUPS);
12b2b9e3 3480 config.num_mcast_table_elems =
ec6a73f0 3481 __cpu_to_le32(TARGET_10X_NUM_MCAST_TABLE_ELEMS);
12b2b9e3 3482
ec6a73f0
BM		 3483 config.mcast2ucast_mode = __cpu_to_le32(TARGET_10X_MCAST2UCAST_MODE);
3484 config.tx_dbg_log_size = __cpu_to_le32(TARGET_10X_TX_DBG_LOG_SIZE);
3485 config.num_wds_entries = __cpu_to_le32(TARGET_10X_NUM_WDS_ENTRIES);
3486 config.dma_burst_size = __cpu_to_le32(TARGET_10X_DMA_BURST_SIZE);
3487 config.mac_aggr_delim = __cpu_to_le32(TARGET_10X_MAC_AGGR_DELIM);
12b2b9e3 3488
ec6a73f0 3489 val = TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK;
12b2b9e3
BM		 3490 config.rx_skip_defrag_timeout_dup_detection_check = __cpu_to_le32(val);
3491
ec6a73f0 3492 config.vow_config = __cpu_to_le32(TARGET_10X_VOW_CONFIG);
12b2b9e3 3493
ec6a73f0
BM		 3494 config.num_msdu_desc = __cpu_to_le32(TARGET_10X_NUM_MSDU_DESC);
3495 config.max_frag_entries = __cpu_to_le32(TARGET_10X_MAX_FRAG_ENTRIES);
12b2b9e3
BM		 3496
3497 len = sizeof(*cmd) +
3498 (sizeof(struct host_memory_chunk) * ar->wmi.num_mem_chunks);
3499
7aa7a72a 3500 buf = ath10k_wmi_alloc_skb(ar, len);
12b2b9e3
BM		 3501 if (!buf)
3502 return -ENOMEM;
3503
3504 cmd = (struct wmi_init_cmd_10x *)buf->data;
3505
12b2b9e3 3506 memcpy(&cmd->resource_config, &config, sizeof(config));
cf9fca8f 3507 ath10k_wmi_put_host_mem_chunks(ar, &cmd->mem_chunks);
12b2b9e3 3508
7aa7a72a 3509 ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi init 10x\n");
12b2b9e3
BM		 3510 return ath10k_wmi_cmd_send(ar, buf, ar->wmi.cmd->init_cmdid);
3511}
3512
24c88f78
MK		 3513static int ath10k_wmi_10_2_cmd_init(struct ath10k *ar)
3514{
3515 struct wmi_init_cmd_10_2 *cmd;
3516 struct sk_buff *buf;
3517 struct wmi_resource_config_10x config = {};
3518 u32 len, val;
24c88f78
MK		 3519
3520 config.num_vdevs = __cpu_to_le32(TARGET_10X_NUM_VDEVS);
3521 config.num_peers = __cpu_to_le32(TARGET_10X_NUM_PEERS);
3522 config.num_peer_keys = __cpu_to_le32(TARGET_10X_NUM_PEER_KEYS);
3523 config.num_tids = __cpu_to_le32(TARGET_10X_NUM_TIDS);
3524 config.ast_skid_limit = __cpu_to_le32(TARGET_10X_AST_SKID_LIMIT);
3525 config.tx_chain_mask = __cpu_to_le32(TARGET_10X_TX_CHAIN_MASK);
3526 config.rx_chain_mask = __cpu_to_le32(TARGET_10X_RX_CHAIN_MASK);
3527 config.rx_timeout_pri_vo = __cpu_to_le32(TARGET_10X_RX_TIMEOUT_LO_PRI);
3528 config.rx_timeout_pri_vi = __cpu_to_le32(TARGET_10X_RX_TIMEOUT_LO_PRI);
3529 config.rx_timeout_pri_be = __cpu_to_le32(TARGET_10X_RX_TIMEOUT_LO_PRI);
3530 config.rx_timeout_pri_bk = __cpu_to_le32(TARGET_10X_RX_TIMEOUT_HI_PRI);
3531 config.rx_decap_mode = __cpu_to_le32(TARGET_10X_RX_DECAP_MODE);
3532
3533 config.scan_max_pending_reqs =
3534 __cpu_to_le32(TARGET_10X_SCAN_MAX_PENDING_REQS);
3535
3536 config.bmiss_offload_max_vdev =
3537 __cpu_to_le32(TARGET_10X_BMISS_OFFLOAD_MAX_VDEV);
3538
3539 config.roam_offload_max_vdev =
3540 __cpu_to_le32(TARGET_10X_ROAM_OFFLOAD_MAX_VDEV);
3541
3542 config.roam_offload_max_ap_profiles =
3543 __cpu_to_le32(TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES);
3544
3545 config.num_mcast_groups = __cpu_to_le32(TARGET_10X_NUM_MCAST_GROUPS);
3546 config.num_mcast_table_elems =
3547 __cpu_to_le32(TARGET_10X_NUM_MCAST_TABLE_ELEMS);
3548
3549 config.mcast2ucast_mode = __cpu_to_le32(TARGET_10X_MCAST2UCAST_MODE);
3550 config.tx_dbg_log_size = __cpu_to_le32(TARGET_10X_TX_DBG_LOG_SIZE);
3551 config.num_wds_entries = __cpu_to_le32(TARGET_10X_NUM_WDS_ENTRIES);
3552 config.dma_burst_size = __cpu_to_le32(TARGET_10X_DMA_BURST_SIZE);
3553 config.mac_aggr_delim = __cpu_to_le32(TARGET_10X_MAC_AGGR_DELIM);
3554
3555 val = TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK;
3556 config.rx_skip_defrag_timeout_dup_detection_check = __cpu_to_le32(val);
3557
3558 config.vow_config = __cpu_to_le32(TARGET_10X_VOW_CONFIG);
3559
3560 config.num_msdu_desc = __cpu_to_le32(TARGET_10X_NUM_MSDU_DESC);
3561 config.max_frag_entries = __cpu_to_le32(TARGET_10X_MAX_FRAG_ENTRIES);
3562
3563 len = sizeof(*cmd) +
3564 (sizeof(struct host_memory_chunk) * ar->wmi.num_mem_chunks);
3565
7aa7a72a 3566 buf = ath10k_wmi_alloc_skb(ar, len);
24c88f78
MK		 3567 if (!buf)
3568 return -ENOMEM;
3569
3570 cmd = (struct wmi_init_cmd_10_2 *)buf->data;
3571
24c88f78 3572 memcpy(&cmd->resource_config.common, &config, sizeof(config));
cf9fca8f 3573 ath10k_wmi_put_host_mem_chunks(ar, &cmd->mem_chunks);
24c88f78 3574
7aa7a72a 3575 ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi init 10.2\n");
24c88f78
MK		 3576 return ath10k_wmi_cmd_send(ar, buf, ar->wmi.cmd->init_cmdid);
3577}
3578
12b2b9e3
BM		 3579int ath10k_wmi_cmd_init(struct ath10k *ar)
3580{
3581 int ret;
3582
24c88f78
MK		 3583 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) {
3584 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, ar->fw_features))
3585 ret = ath10k_wmi_10_2_cmd_init(ar);
3586 else
3587 ret = ath10k_wmi_10x_cmd_init(ar);
3588 } else {
12b2b9e3 3589 ret = ath10k_wmi_main_cmd_init(ar);
24c88f78 3590 }
12b2b9e3
BM		 3591
3592 return ret;
5e3dd157
KV		 3593}
3594
a6aa5da3 3595static int ath10k_wmi_start_scan_verify(const struct wmi_start_scan_arg *arg)
5e3dd157 3596{
a6aa5da3
MK		 3597 if (arg->ie_len && !arg->ie)
3598 return -EINVAL;
3599 if (arg->n_channels && !arg->channels)
3600 return -EINVAL;
3601 if (arg->n_ssids && !arg->ssids)
3602 return -EINVAL;
3603 if (arg->n_bssids && !arg->bssids)
3604 return -EINVAL;
5e3dd157 3605
a6aa5da3
MK		 3606 if (arg->ie_len > WLAN_SCAN_PARAMS_MAX_IE_LEN)
3607 return -EINVAL;
3608 if (arg->n_channels > ARRAY_SIZE(arg->channels))
3609 return -EINVAL;
3610 if (arg->n_ssids > WLAN_SCAN_PARAMS_MAX_SSID)
3611 return -EINVAL;
3612 if (arg->n_bssids > WLAN_SCAN_PARAMS_MAX_BSSID)
3613 return -EINVAL;
5e3dd157 3614
a6aa5da3
MK		 3615 return 0;
3616}
5e3dd157 3617
a6aa5da3
MK		 3618static size_t
3619ath10k_wmi_start_scan_tlvs_len(const struct wmi_start_scan_arg *arg)
3620{
3621 int len = 0;
3622
3623 if (arg->ie_len) {
5e3dd157
KV		 3624 len += sizeof(struct wmi_ie_data);
3625 len += roundup(arg->ie_len, 4);
3626 }
3627
3628 if (arg->n_channels) {
5e3dd157
KV		 3629 len += sizeof(struct wmi_chan_list);
3630 len += sizeof(__le32) * arg->n_channels;
3631 }
3632
3633 if (arg->n_ssids) {
5e3dd157
KV		 3634 len += sizeof(struct wmi_ssid_list);
3635 len += sizeof(struct wmi_ssid) * arg->n_ssids;
3636 }
3637
3638 if (arg->n_bssids) {
5e3dd157
KV		 3639 len += sizeof(struct wmi_bssid_list);
3640 len += sizeof(struct wmi_mac_addr) * arg->n_bssids;
3641 }
3642
3643 return len;
3644}
3645
a6aa5da3
MK		 3646static void
3647ath10k_wmi_put_start_scan_common(struct wmi_start_scan_common *cmn,
3648 const struct wmi_start_scan_arg *arg)
5e3dd157 3649{
5e3dd157
KV		 3650 u32 scan_id;
3651 u32 scan_req_id;
5e3dd157
KV		 3652
3653 scan_id = WMI_HOST_SCAN_REQ_ID_PREFIX;
3654 scan_id |= arg->scan_id;
3655
3656 scan_req_id = WMI_HOST_SCAN_REQUESTOR_ID_PREFIX;
3657 scan_req_id |= arg->scan_req_id;
3658
a6aa5da3
MK		 3659 cmn->scan_id = __cpu_to_le32(scan_id);
3660 cmn->scan_req_id = __cpu_to_le32(scan_req_id);
3661 cmn->vdev_id = __cpu_to_le32(arg->vdev_id);
3662 cmn->scan_priority = __cpu_to_le32(arg->scan_priority);
3663 cmn->notify_scan_events = __cpu_to_le32(arg->notify_scan_events);
3664 cmn->dwell_time_active = __cpu_to_le32(arg->dwell_time_active);
3665 cmn->dwell_time_passive = __cpu_to_le32(arg->dwell_time_passive);
3666 cmn->min_rest_time = __cpu_to_le32(arg->min_rest_time);
3667 cmn->max_rest_time = __cpu_to_le32(arg->max_rest_time);
3668 cmn->repeat_probe_time = __cpu_to_le32(arg->repeat_probe_time);
3669 cmn->probe_spacing_time = __cpu_to_le32(arg->probe_spacing_time);
3670 cmn->idle_time = __cpu_to_le32(arg->idle_time);
3671 cmn->max_scan_time = __cpu_to_le32(arg->max_scan_time);
3672 cmn->probe_delay = __cpu_to_le32(arg->probe_delay);
3673 cmn->scan_ctrl_flags = __cpu_to_le32(arg->scan_ctrl_flags);
3674}
3675
3676static void
3677ath10k_wmi_put_start_scan_tlvs(struct wmi_start_scan_tlvs *tlvs,
3678 const struct wmi_start_scan_arg *arg)
3679{
3680 struct wmi_ie_data *ie;
3681 struct wmi_chan_list *channels;
3682 struct wmi_ssid_list *ssids;
3683 struct wmi_bssid_list *bssids;
3684 void *ptr = tlvs->tlvs;
3685 int i;
5e3dd157
KV		 3686
3687 if (arg->n_channels) {
a6aa5da3 3688 channels = ptr;
5e3dd157
KV		 3689 channels->tag = __cpu_to_le32(WMI_CHAN_LIST_TAG);
3690 channels->num_chan = __cpu_to_le32(arg->n_channels);
3691
3692 for (i = 0; i < arg->n_channels; i++)
24c88f78
MK		 3693 channels->channel_list[i].freq =
3694 __cpu_to_le16(arg->channels[i]);
5e3dd157 3695
a6aa5da3
MK		 3696 ptr += sizeof(*channels);
3697 ptr += sizeof(__le32) * arg->n_channels;
5e3dd157
KV		 3698 }
3699
3700 if (arg->n_ssids) {
a6aa5da3 3701 ssids = ptr;
5e3dd157
KV		 3702 ssids->tag = __cpu_to_le32(WMI_SSID_LIST_TAG);
3703 ssids->num_ssids = __cpu_to_le32(arg->n_ssids);
3704
3705 for (i = 0; i < arg->n_ssids; i++) {
3706 ssids->ssids[i].ssid_len =
3707 __cpu_to_le32(arg->ssids[i].len);
3708 memcpy(&ssids->ssids[i].ssid,
3709 arg->ssids[i].ssid,
3710 arg->ssids[i].len);
3711 }
3712
a6aa5da3
MK		 3713 ptr += sizeof(*ssids);
3714 ptr += sizeof(struct wmi_ssid) * arg->n_ssids;
5e3dd157
KV		 3715 }
3716
3717 if (arg->n_bssids) {
a6aa5da3 3718 bssids = ptr;
5e3dd157
KV		 3719 bssids->tag = __cpu_to_le32(WMI_BSSID_LIST_TAG);
3720 bssids->num_bssid = __cpu_to_le32(arg->n_bssids);
3721
3722 for (i = 0; i < arg->n_bssids; i++)
3723 memcpy(&bssids->bssid_list[i],
3724 arg->bssids[i].bssid,
3725 ETH_ALEN);
3726
a6aa5da3
MK		 3727 ptr += sizeof(*bssids);
3728 ptr += sizeof(struct wmi_mac_addr) * arg->n_bssids;
5e3dd157
KV		 3729 }
3730
3731 if (arg->ie_len) {
a6aa5da3 3732 ie = ptr;
5e3dd157
KV		 3733 ie->tag = __cpu_to_le32(WMI_IE_TAG);
3734 ie->ie_len = __cpu_to_le32(arg->ie_len);
3735 memcpy(ie->ie_data, arg->ie, arg->ie_len);
3736
a6aa5da3
MK		 3737 ptr += sizeof(*ie);
3738 ptr += roundup(arg->ie_len, 4);
5e3dd157 3739 }
a6aa5da3 3740}
5e3dd157 3741
a6aa5da3
MK		 3742int ath10k_wmi_start_scan(struct ath10k *ar,
3743 const struct wmi_start_scan_arg *arg)
3744{
3745 struct sk_buff *skb;
3746 size_t len;
3747 int ret;
3748
3749 ret = ath10k_wmi_start_scan_verify(arg);
3750 if (ret)
3751 return ret;
3752
3753 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features))
6db0885a 3754 len = sizeof(struct wmi_10x_start_scan_cmd) +
a6aa5da3
MK		 3755 ath10k_wmi_start_scan_tlvs_len(arg);
3756 else
6db0885a 3757 len = sizeof(struct wmi_start_scan_cmd) +
a6aa5da3
MK		 3758 ath10k_wmi_start_scan_tlvs_len(arg);
3759
3760 skb = ath10k_wmi_alloc_skb(ar, len);
3761 if (!skb)
3762 return -ENOMEM;
3763
3764 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) {
3765 struct wmi_10x_start_scan_cmd *cmd;
3766
3767 cmd = (struct wmi_10x_start_scan_cmd *)skb->data;
3768 ath10k_wmi_put_start_scan_common(&cmd->common, arg);
3769 ath10k_wmi_put_start_scan_tlvs(&cmd->tlvs, arg);
3770 } else {
3771 struct wmi_start_scan_cmd *cmd;
3772
3773 cmd = (struct wmi_start_scan_cmd *)skb->data;
3774 cmd->burst_duration_ms = __cpu_to_le32(0);
3775
3776 ath10k_wmi_put_start_scan_common(&cmd->common, arg);
3777 ath10k_wmi_put_start_scan_tlvs(&cmd->tlvs, arg);
5e3dd157
KV		 3778 }
3779
7aa7a72a 3780 ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi start scan\n");
ce42870e 3781 return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->start_scan_cmdid);
5e3dd157
KV		 3782}
3783
3784void ath10k_wmi_start_scan_init(struct ath10k *ar,
3785 struct wmi_start_scan_arg *arg)
3786{
3787 /* setup commonly used values */
3788 arg->scan_req_id = 1;
3789 arg->scan_priority = WMI_SCAN_PRIORITY_LOW;
3790 arg->dwell_time_active = 50;
3791 arg->dwell_time_passive = 150;
3792 arg->min_rest_time = 50;
3793 arg->max_rest_time = 500;
3794 arg->repeat_probe_time = 0;
3795 arg->probe_spacing_time = 0;
3796 arg->idle_time = 0;
c322892f 3797 arg->max_scan_time = 20000;
5e3dd157
KV		 3798 arg->probe_delay = 5;
3799 arg->notify_scan_events = WMI_SCAN_EVENT_STARTED
3800 | WMI_SCAN_EVENT_COMPLETED
3801 | WMI_SCAN_EVENT_BSS_CHANNEL
3802 | WMI_SCAN_EVENT_FOREIGN_CHANNEL
3803 | WMI_SCAN_EVENT_DEQUEUED;
3804 arg->scan_ctrl_flags |= WMI_SCAN_ADD_OFDM_RATES;
3805 arg->scan_ctrl_flags |= WMI_SCAN_CHAN_STAT_EVENT;
3806 arg->n_bssids = 1;
3807 arg->bssids[0].bssid = "\xFF\xFF\xFF\xFF\xFF\xFF";
3808}
3809
3810int ath10k_wmi_stop_scan(struct ath10k *ar, const struct wmi_stop_scan_arg *arg)
3811{
3812 struct wmi_stop_scan_cmd *cmd;
3813 struct sk_buff *skb;
3814 u32 scan_id;
3815 u32 req_id;
3816
3817 if (arg->req_id > 0xFFF)
3818 return -EINVAL;
3819 if (arg->req_type == WMI_SCAN_STOP_ONE && arg->u.scan_id > 0xFFF)
3820 return -EINVAL;
3821
7aa7a72a 3822 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 3823 if (!skb)
3824 return -ENOMEM;
3825
3826 scan_id = arg->u.scan_id;
3827 scan_id |= WMI_HOST_SCAN_REQ_ID_PREFIX;
3828
3829 req_id = arg->req_id;
3830 req_id |= WMI_HOST_SCAN_REQUESTOR_ID_PREFIX;
3831
3832 cmd = (struct wmi_stop_scan_cmd *)skb->data;
3833 cmd->req_type = __cpu_to_le32(arg->req_type);
3834 cmd->vdev_id = __cpu_to_le32(arg->u.vdev_id);
3835 cmd->scan_id = __cpu_to_le32(scan_id);
3836 cmd->scan_req_id = __cpu_to_le32(req_id);
3837
7aa7a72a 3838 ath10k_dbg(ar, ATH10K_DBG_WMI,
5e3dd157
KV		 3839 "wmi stop scan reqid %d req_type %d vdev/scan_id %d\n",
3840 arg->req_id, arg->req_type, arg->u.scan_id);
ce42870e 3841 return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->stop_scan_cmdid);
5e3dd157
KV		 3842}
3843
3844int ath10k_wmi_vdev_create(struct ath10k *ar, u32 vdev_id,
3845 enum wmi_vdev_type type,
3846 enum wmi_vdev_subtype subtype,
3847 const u8 macaddr[ETH_ALEN])
3848{
3849 struct wmi_vdev_create_cmd *cmd;
3850 struct sk_buff *skb;
3851
7aa7a72a 3852 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 3853 if (!skb)
3854 return -ENOMEM;
3855
3856 cmd = (struct wmi_vdev_create_cmd *)skb->data;
3857 cmd->vdev_id = __cpu_to_le32(vdev_id);
3858 cmd->vdev_type = __cpu_to_le32(type);
3859 cmd->vdev_subtype = __cpu_to_le32(subtype);
b25f32cb 3860 ether_addr_copy(cmd->vdev_macaddr.addr, macaddr);
5e3dd157 3861
7aa7a72a 3862 ath10k_dbg(ar, ATH10K_DBG_WMI,
5e3dd157
KV		 3863 "WMI vdev create: id %d type %d subtype %d macaddr %pM\n",
3864 vdev_id, type, subtype, macaddr);
3865
ce42870e 3866 return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->vdev_create_cmdid);
5e3dd157
KV		 3867}
3868
3869int ath10k_wmi_vdev_delete(struct ath10k *ar, u32 vdev_id)
3870{
3871 struct wmi_vdev_delete_cmd *cmd;
3872 struct sk_buff *skb;
3873
7aa7a72a 3874 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 3875 if (!skb)
3876 return -ENOMEM;
3877
3878 cmd = (struct wmi_vdev_delete_cmd *)skb->data;
3879 cmd->vdev_id = __cpu_to_le32(vdev_id);
3880
7aa7a72a 3881 ath10k_dbg(ar, ATH10K_DBG_WMI,
5e3dd157
KV		 3882 "WMI vdev delete id %d\n", vdev_id);
3883
ce42870e 3884 return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->vdev_delete_cmdid);
5e3dd157
KV		 3885}
3886
5b07e07f
KV		 3887static int
3888ath10k_wmi_vdev_start_restart(struct ath10k *ar,
3889 const struct wmi_vdev_start_request_arg *arg,
3890 u32 cmd_id)
5e3dd157
KV		 3891{
3892 struct wmi_vdev_start_request_cmd *cmd;
3893 struct sk_buff *skb;
3894 const char *cmdname;
3895 u32 flags = 0;
3896
ce42870e
BM		 3897 if (cmd_id != ar->wmi.cmd->vdev_start_request_cmdid &&
3898 cmd_id != ar->wmi.cmd->vdev_restart_request_cmdid)
5e3dd157
KV		 3899 return -EINVAL;
3900 if (WARN_ON(arg->ssid && arg->ssid_len == 0))
3901 return -EINVAL;
3902 if (WARN_ON(arg->hidden_ssid && !arg->ssid))
3903 return -EINVAL;
3904 if (WARN_ON(arg->ssid_len > sizeof(cmd->ssid.ssid)))
3905 return -EINVAL;
3906
ce42870e 3907 if (cmd_id == ar->wmi.cmd->vdev_start_request_cmdid)
5e3dd157 3908 cmdname = "start";
ce42870e 3909 else if (cmd_id == ar->wmi.cmd->vdev_restart_request_cmdid)
5e3dd157
KV		 3910 cmdname = "restart";
3911 else
3912 return -EINVAL; /* should not happen, we already check cmd_id */
3913
7aa7a72a 3914 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 3915 if (!skb)
3916 return -ENOMEM;
3917
3918 if (arg->hidden_ssid)
3919 flags |= WMI_VDEV_START_HIDDEN_SSID;
3920 if (arg->pmf_enabled)
3921 flags |= WMI_VDEV_START_PMF_ENABLED;
3922
3923 cmd = (struct wmi_vdev_start_request_cmd *)skb->data;
3924 cmd->vdev_id = __cpu_to_le32(arg->vdev_id);
3925 cmd->disable_hw_ack = __cpu_to_le32(arg->disable_hw_ack);
3926 cmd->beacon_interval = __cpu_to_le32(arg->bcn_intval);
3927 cmd->dtim_period = __cpu_to_le32(arg->dtim_period);
3928 cmd->flags = __cpu_to_le32(flags);
3929 cmd->bcn_tx_rate = __cpu_to_le32(arg->bcn_tx_rate);
3930 cmd->bcn_tx_power = __cpu_to_le32(arg->bcn_tx_power);
3931
3932 if (arg->ssid) {
3933 cmd->ssid.ssid_len = __cpu_to_le32(arg->ssid_len);
3934 memcpy(cmd->ssid.ssid, arg->ssid, arg->ssid_len);
3935 }
3936
2d66721c 3937 ath10k_wmi_put_wmi_channel(&cmd->chan, &arg->channel);
5e3dd157 3938
7aa7a72a 3939 ath10k_dbg(ar, ATH10K_DBG_WMI,
8cc7f26c
KV		 3940 "wmi vdev %s id 0x%x flags: 0x%0X, freq %d, mode %d, ch_flags: 0x%0X, max_power: %d\n",
3941 cmdname, arg->vdev_id,
e8a50f8b
MP		 3942 flags, arg->channel.freq, arg->channel.mode,
3943 cmd->chan.flags, arg->channel.max_power);
5e3dd157
KV		 3944
3945 return ath10k_wmi_cmd_send(ar, skb, cmd_id);
3946}
3947
3948int ath10k_wmi_vdev_start(struct ath10k *ar,
3949 const struct wmi_vdev_start_request_arg *arg)
3950{
ce42870e
BM		 3951 u32 cmd_id = ar->wmi.cmd->vdev_start_request_cmdid;
3952
3953 return ath10k_wmi_vdev_start_restart(ar, arg, cmd_id);
5e3dd157
KV		 3954}
3955
3956int ath10k_wmi_vdev_restart(struct ath10k *ar,
5b07e07f 3957 const struct wmi_vdev_start_request_arg *arg)
5e3dd157 3958{
ce42870e
BM		 3959 u32 cmd_id = ar->wmi.cmd->vdev_restart_request_cmdid;
3960
3961 return ath10k_wmi_vdev_start_restart(ar, arg, cmd_id);
5e3dd157
KV		 3962}
3963
3964int ath10k_wmi_vdev_stop(struct ath10k *ar, u32 vdev_id)
3965{
3966 struct wmi_vdev_stop_cmd *cmd;
3967 struct sk_buff *skb;
3968
7aa7a72a 3969 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 3970 if (!skb)
3971 return -ENOMEM;
3972
3973 cmd = (struct wmi_vdev_stop_cmd *)skb->data;
3974 cmd->vdev_id = __cpu_to_le32(vdev_id);
3975
7aa7a72a 3976 ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi vdev stop id 0x%x\n", vdev_id);
5e3dd157 3977
ce42870e 3978 return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->vdev_stop_cmdid);
5e3dd157
KV		 3979}
3980
3981int ath10k_wmi_vdev_up(struct ath10k *ar, u32 vdev_id, u32 aid, const u8 *bssid)
3982{
3983 struct wmi_vdev_up_cmd *cmd;
3984 struct sk_buff *skb;
3985
7aa7a72a 3986 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 3987 if (!skb)
3988 return -ENOMEM;
3989
3990 cmd = (struct wmi_vdev_up_cmd *)skb->data;
3991 cmd->vdev_id = __cpu_to_le32(vdev_id);
3992 cmd->vdev_assoc_id = __cpu_to_le32(aid);
b25f32cb 3993 ether_addr_copy(cmd->vdev_bssid.addr, bssid);
5e3dd157 3994
7aa7a72a 3995 ath10k_dbg(ar, ATH10K_DBG_WMI,
5e3dd157
KV		 3996 "wmi mgmt vdev up id 0x%x assoc id %d bssid %pM\n",
3997 vdev_id, aid, bssid);
3998
ce42870e 3999 return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->vdev_up_cmdid);
5e3dd157
KV		 4000}
4001
4002int ath10k_wmi_vdev_down(struct ath10k *ar, u32 vdev_id)
4003{
4004 struct wmi_vdev_down_cmd *cmd;
4005 struct sk_buff *skb;
4006
7aa7a72a 4007 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 4008 if (!skb)
4009 return -ENOMEM;
4010
4011 cmd = (struct wmi_vdev_down_cmd *)skb->data;
4012 cmd->vdev_id = __cpu_to_le32(vdev_id);
4013
7aa7a72a 4014 ath10k_dbg(ar, ATH10K_DBG_WMI,
5e3dd157
KV		 4015 "wmi mgmt vdev down id 0x%x\n", vdev_id);
4016
ce42870e 4017 return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->vdev_down_cmdid);
5e3dd157
KV		 4018}
4019
4020int ath10k_wmi_vdev_set_param(struct ath10k *ar, u32 vdev_id,
6d1506e7 4021 u32 param_id, u32 param_value)
5e3dd157
KV		 4022{
4023 struct wmi_vdev_set_param_cmd *cmd;
4024 struct sk_buff *skb;
4025
6d1506e7 4026 if (param_id == WMI_VDEV_PARAM_UNSUPPORTED) {
7aa7a72a 4027 ath10k_dbg(ar, ATH10K_DBG_WMI,
6d1506e7
BM		 4028 "vdev param %d not supported by firmware\n",
4029 param_id);
ebc9abdd 4030 return -EOPNOTSUPP;
6d1506e7
BM		 4031 }
4032
7aa7a72a 4033 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 4034 if (!skb)
4035 return -ENOMEM;
4036
4037 cmd = (struct wmi_vdev_set_param_cmd *)skb->data;
4038 cmd->vdev_id = __cpu_to_le32(vdev_id);
4039 cmd->param_id = __cpu_to_le32(param_id);
4040 cmd->param_value = __cpu_to_le32(param_value);
4041
7aa7a72a 4042 ath10k_dbg(ar, ATH10K_DBG_WMI,
5e3dd157
KV		 4043 "wmi vdev id 0x%x set param %d value %d\n",
4044 vdev_id, param_id, param_value);
4045
ce42870e 4046 return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->vdev_set_param_cmdid);
5e3dd157
KV		 4047}
4048
4049int ath10k_wmi_vdev_install_key(struct ath10k *ar,
4050 const struct wmi_vdev_install_key_arg *arg)
4051{
4052 struct wmi_vdev_install_key_cmd *cmd;
4053 struct sk_buff *skb;
4054
4055 if (arg->key_cipher == WMI_CIPHER_NONE && arg->key_data != NULL)
4056 return -EINVAL;
4057 if (arg->key_cipher != WMI_CIPHER_NONE && arg->key_data == NULL)
4058 return -EINVAL;
4059
7aa7a72a 4060 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd) + arg->key_len);
5e3dd157
KV		 4061 if (!skb)
4062 return -ENOMEM;
4063
4064 cmd = (struct wmi_vdev_install_key_cmd *)skb->data;
4065 cmd->vdev_id = __cpu_to_le32(arg->vdev_id);
4066 cmd->key_idx = __cpu_to_le32(arg->key_idx);
4067 cmd->key_flags = __cpu_to_le32(arg->key_flags);
4068 cmd->key_cipher = __cpu_to_le32(arg->key_cipher);
4069 cmd->key_len = __cpu_to_le32(arg->key_len);
4070 cmd->key_txmic_len = __cpu_to_le32(arg->key_txmic_len);
4071 cmd->key_rxmic_len = __cpu_to_le32(arg->key_rxmic_len);
4072
4073 if (arg->macaddr)
b25f32cb 4074 ether_addr_copy(cmd->peer_macaddr.addr, arg->macaddr);
5e3dd157
KV		 4075 if (arg->key_data)
4076 memcpy(cmd->key_data, arg->key_data, arg->key_len);
4077
7aa7a72a 4078 ath10k_dbg(ar, ATH10K_DBG_WMI,
e0c508ab
MK		 4079 "wmi vdev install key idx %d cipher %d len %d\n",
4080 arg->key_idx, arg->key_cipher, arg->key_len);
ce42870e
BM		 4081 return ath10k_wmi_cmd_send(ar, skb,
4082 ar->wmi.cmd->vdev_install_key_cmdid);
5e3dd157
KV		 4083}
4084
855aed12
SW		 4085int ath10k_wmi_vdev_spectral_conf(struct ath10k *ar,
4086 const struct wmi_vdev_spectral_conf_arg *arg)
4087{
4088 struct wmi_vdev_spectral_conf_cmd *cmd;
4089 struct sk_buff *skb;
4090 u32 cmdid;
4091
7aa7a72a 4092 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
855aed12
SW		 4093 if (!skb)
4094 return -ENOMEM;
4095
4096 cmd = (struct wmi_vdev_spectral_conf_cmd *)skb->data;
4097 cmd->vdev_id = __cpu_to_le32(arg->vdev_id);
4098 cmd->scan_count = __cpu_to_le32(arg->scan_count);
4099 cmd->scan_period = __cpu_to_le32(arg->scan_period);
4100 cmd->scan_priority = __cpu_to_le32(arg->scan_priority);
4101 cmd->scan_fft_size = __cpu_to_le32(arg->scan_fft_size);
4102 cmd->scan_gc_ena = __cpu_to_le32(arg->scan_gc_ena);
4103 cmd->scan_restart_ena = __cpu_to_le32(arg->scan_restart_ena);
4104 cmd->scan_noise_floor_ref = __cpu_to_le32(arg->scan_noise_floor_ref);
4105 cmd->scan_init_delay = __cpu_to_le32(arg->scan_init_delay);
4106 cmd->scan_nb_tone_thr = __cpu_to_le32(arg->scan_nb_tone_thr);
4107 cmd->scan_str_bin_thr = __cpu_to_le32(arg->scan_str_bin_thr);
4108 cmd->scan_wb_rpt_mode = __cpu_to_le32(arg->scan_wb_rpt_mode);
4109 cmd->scan_rssi_rpt_mode = __cpu_to_le32(arg->scan_rssi_rpt_mode);
4110 cmd->scan_rssi_thr = __cpu_to_le32(arg->scan_rssi_thr);
4111 cmd->scan_pwr_format = __cpu_to_le32(arg->scan_pwr_format);
4112 cmd->scan_rpt_mode = __cpu_to_le32(arg->scan_rpt_mode);
4113 cmd->scan_bin_scale = __cpu_to_le32(arg->scan_bin_scale);
4114 cmd->scan_dbm_adj = __cpu_to_le32(arg->scan_dbm_adj);
4115 cmd->scan_chn_mask = __cpu_to_le32(arg->scan_chn_mask);
4116
4117 cmdid = ar->wmi.cmd->vdev_spectral_scan_configure_cmdid;
4118 return ath10k_wmi_cmd_send(ar, skb, cmdid);
4119}
4120
4121int ath10k_wmi_vdev_spectral_enable(struct ath10k *ar, u32 vdev_id, u32 trigger,
4122 u32 enable)
4123{
4124 struct wmi_vdev_spectral_enable_cmd *cmd;
4125 struct sk_buff *skb;
4126 u32 cmdid;
4127
7aa7a72a 4128 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
855aed12
SW		 4129 if (!skb)
4130 return -ENOMEM;
4131
4132 cmd = (struct wmi_vdev_spectral_enable_cmd *)skb->data;
4133 cmd->vdev_id = __cpu_to_le32(vdev_id);
4134 cmd->trigger_cmd = __cpu_to_le32(trigger);
4135 cmd->enable_cmd = __cpu_to_le32(enable);
4136
4137 cmdid = ar->wmi.cmd->vdev_spectral_scan_enable_cmdid;
4138 return ath10k_wmi_cmd_send(ar, skb, cmdid);
4139}
4140
5e3dd157
KV		 4141int ath10k_wmi_peer_create(struct ath10k *ar, u32 vdev_id,
4142 const u8 peer_addr[ETH_ALEN])
4143{
4144 struct wmi_peer_create_cmd *cmd;
4145 struct sk_buff *skb;
4146
7aa7a72a 4147 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 4148 if (!skb)
4149 return -ENOMEM;
4150
4151 cmd = (struct wmi_peer_create_cmd *)skb->data;
4152 cmd->vdev_id = __cpu_to_le32(vdev_id);
b25f32cb 4153 ether_addr_copy(cmd->peer_macaddr.addr, peer_addr);
5e3dd157 4154
7aa7a72a 4155 ath10k_dbg(ar, ATH10K_DBG_WMI,
5e3dd157
KV		 4156 "wmi peer create vdev_id %d peer_addr %pM\n",
4157 vdev_id, peer_addr);
ce42870e 4158 return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->peer_create_cmdid);
5e3dd157
KV		 4159}
4160
4161int ath10k_wmi_peer_delete(struct ath10k *ar, u32 vdev_id,
4162 const u8 peer_addr[ETH_ALEN])
4163{
4164 struct wmi_peer_delete_cmd *cmd;
4165 struct sk_buff *skb;
4166
7aa7a72a 4167 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 4168 if (!skb)
4169 return -ENOMEM;
4170
4171 cmd = (struct wmi_peer_delete_cmd *)skb->data;
4172 cmd->vdev_id = __cpu_to_le32(vdev_id);
b25f32cb 4173 ether_addr_copy(cmd->peer_macaddr.addr, peer_addr);
5e3dd157 4174
7aa7a72a 4175 ath10k_dbg(ar, ATH10K_DBG_WMI,
5e3dd157
KV		 4176 "wmi peer delete vdev_id %d peer_addr %pM\n",
4177 vdev_id, peer_addr);
ce42870e 4178 return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->peer_delete_cmdid);
5e3dd157
KV		 4179}
4180
4181int ath10k_wmi_peer_flush(struct ath10k *ar, u32 vdev_id,
4182 const u8 peer_addr[ETH_ALEN], u32 tid_bitmap)
4183{
4184 struct wmi_peer_flush_tids_cmd *cmd;
4185 struct sk_buff *skb;
4186
7aa7a72a 4187 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 4188 if (!skb)
4189 return -ENOMEM;
4190
4191 cmd = (struct wmi_peer_flush_tids_cmd *)skb->data;
4192 cmd->vdev_id = __cpu_to_le32(vdev_id);
4193 cmd->peer_tid_bitmap = __cpu_to_le32(tid_bitmap);
b25f32cb 4194 ether_addr_copy(cmd->peer_macaddr.addr, peer_addr);
5e3dd157 4195
7aa7a72a 4196 ath10k_dbg(ar, ATH10K_DBG_WMI,
5e3dd157
KV		 4197 "wmi peer flush vdev_id %d peer_addr %pM tids %08x\n",
4198 vdev_id, peer_addr, tid_bitmap);
ce42870e 4199 return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->peer_flush_tids_cmdid);
5e3dd157
KV		 4200}
4201
4202int ath10k_wmi_peer_set_param(struct ath10k *ar, u32 vdev_id,
4203 const u8 *peer_addr, enum wmi_peer_param param_id,
4204 u32 param_value)
4205{
4206 struct wmi_peer_set_param_cmd *cmd;
4207 struct sk_buff *skb;
4208
7aa7a72a 4209 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 4210 if (!skb)
4211 return -ENOMEM;
4212
4213 cmd = (struct wmi_peer_set_param_cmd *)skb->data;
4214 cmd->vdev_id = __cpu_to_le32(vdev_id);
4215 cmd->param_id = __cpu_to_le32(param_id);
4216 cmd->param_value = __cpu_to_le32(param_value);
b25f32cb 4217 ether_addr_copy(cmd->peer_macaddr.addr, peer_addr);
5e3dd157 4218
7aa7a72a 4219 ath10k_dbg(ar, ATH10K_DBG_WMI,
5e3dd157
KV		 4220 "wmi vdev %d peer 0x%pM set param %d value %d\n",
4221 vdev_id, peer_addr, param_id, param_value);
4222
ce42870e 4223 return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->peer_set_param_cmdid);
5e3dd157
KV		 4224}
4225
4226int ath10k_wmi_set_psmode(struct ath10k *ar, u32 vdev_id,
4227 enum wmi_sta_ps_mode psmode)
4228{
4229 struct wmi_sta_powersave_mode_cmd *cmd;
4230 struct sk_buff *skb;
4231
7aa7a72a 4232 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 4233 if (!skb)
4234 return -ENOMEM;
4235
4236 cmd = (struct wmi_sta_powersave_mode_cmd *)skb->data;
4237 cmd->vdev_id = __cpu_to_le32(vdev_id);
4238 cmd->sta_ps_mode = __cpu_to_le32(psmode);
4239
7aa7a72a 4240 ath10k_dbg(ar, ATH10K_DBG_WMI,
5e3dd157
KV		 4241 "wmi set powersave id 0x%x mode %d\n",
4242 vdev_id, psmode);
4243
ce42870e
BM		 4244 return ath10k_wmi_cmd_send(ar, skb,
4245 ar->wmi.cmd->sta_powersave_mode_cmdid);
5e3dd157
KV		 4246}
4247
4248int ath10k_wmi_set_sta_ps_param(struct ath10k *ar, u32 vdev_id,
4249 enum wmi_sta_powersave_param param_id,
4250 u32 value)
4251{
4252 struct wmi_sta_powersave_param_cmd *cmd;
4253 struct sk_buff *skb;
4254
7aa7a72a 4255 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 4256 if (!skb)
4257 return -ENOMEM;
4258
4259 cmd = (struct wmi_sta_powersave_param_cmd *)skb->data;
4260 cmd->vdev_id = __cpu_to_le32(vdev_id);
4261 cmd->param_id = __cpu_to_le32(param_id);
4262 cmd->param_value = __cpu_to_le32(value);
4263
7aa7a72a 4264 ath10k_dbg(ar, ATH10K_DBG_WMI,
5e3dd157
KV		 4265 "wmi sta ps param vdev_id 0x%x param %d value %d\n",
4266 vdev_id, param_id, value);
ce42870e
BM		 4267 return ath10k_wmi_cmd_send(ar, skb,
4268 ar->wmi.cmd->sta_powersave_param_cmdid);
5e3dd157
KV		 4269}
4270
4271int ath10k_wmi_set_ap_ps_param(struct ath10k *ar, u32 vdev_id, const u8 *mac,
4272 enum wmi_ap_ps_peer_param param_id, u32 value)
4273{
4274 struct wmi_ap_ps_peer_cmd *cmd;
4275 struct sk_buff *skb;
4276
4277 if (!mac)
4278 return -EINVAL;
4279
7aa7a72a 4280 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 4281 if (!skb)
4282 return -ENOMEM;
4283
4284 cmd = (struct wmi_ap_ps_peer_cmd *)skb->data;
4285 cmd->vdev_id = __cpu_to_le32(vdev_id);
4286 cmd->param_id = __cpu_to_le32(param_id);
4287 cmd->param_value = __cpu_to_le32(value);
b25f32cb 4288 ether_addr_copy(cmd->peer_macaddr.addr, mac);
5e3dd157 4289
7aa7a72a 4290 ath10k_dbg(ar, ATH10K_DBG_WMI,
5e3dd157
KV		 4291 "wmi ap ps param vdev_id 0x%X param %d value %d mac_addr %pM\n",
4292 vdev_id, param_id, value, mac);
4293
ce42870e
BM		 4294 return ath10k_wmi_cmd_send(ar, skb,
4295 ar->wmi.cmd->ap_ps_peer_param_cmdid);
5e3dd157
KV		 4296}
4297
4298int ath10k_wmi_scan_chan_list(struct ath10k *ar,
4299 const struct wmi_scan_chan_list_arg *arg)
4300{
4301 struct wmi_scan_chan_list_cmd *cmd;
4302 struct sk_buff *skb;
4303 struct wmi_channel_arg *ch;
4304 struct wmi_channel *ci;
4305 int len;
4306 int i;
4307
4308 len = sizeof(*cmd) + arg->n_channels * sizeof(struct wmi_channel);
4309
7aa7a72a 4310 skb = ath10k_wmi_alloc_skb(ar, len);
5e3dd157
KV		 4311 if (!skb)
4312 return -EINVAL;
4313
4314 cmd = (struct wmi_scan_chan_list_cmd *)skb->data;
4315 cmd->num_scan_chans = __cpu_to_le32(arg->n_channels);
4316
4317 for (i = 0; i < arg->n_channels; i++) {
5e3dd157
KV		 4318 ch = &arg->channels[i];
4319 ci = &cmd->chan_info[i];
4320
2d66721c 4321 ath10k_wmi_put_wmi_channel(ci, ch);
5e3dd157
KV		 4322 }
4323
ce42870e 4324 return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->scan_chan_list_cmdid);
5e3dd157
KV		 4325}
4326
24c88f78
MK		 4327static void
4328ath10k_wmi_peer_assoc_fill(struct ath10k *ar, void *buf,
4329 const struct wmi_peer_assoc_complete_arg *arg)
5e3dd157 4330{
24c88f78 4331 struct wmi_common_peer_assoc_complete_cmd *cmd = buf;
5e3dd157 4332
5e3dd157
KV		 4333 cmd->vdev_id = __cpu_to_le32(arg->vdev_id);
4334 cmd->peer_new_assoc = __cpu_to_le32(arg->peer_reassoc ? 0 : 1);
4335 cmd->peer_associd = __cpu_to_le32(arg->peer_aid);
4336 cmd->peer_flags = __cpu_to_le32(arg->peer_flags);
4337 cmd->peer_caps = __cpu_to_le32(arg->peer_caps);
4338 cmd->peer_listen_intval = __cpu_to_le32(arg->peer_listen_intval);
4339 cmd->peer_ht_caps = __cpu_to_le32(arg->peer_ht_caps);
4340 cmd->peer_max_mpdu = __cpu_to_le32(arg->peer_max_mpdu);
4341 cmd->peer_mpdu_density = __cpu_to_le32(arg->peer_mpdu_density);
4342 cmd->peer_rate_caps = __cpu_to_le32(arg->peer_rate_caps);
4343 cmd->peer_nss = __cpu_to_le32(arg->peer_num_spatial_streams);
4344 cmd->peer_vht_caps = __cpu_to_le32(arg->peer_vht_caps);
4345 cmd->peer_phymode = __cpu_to_le32(arg->peer_phymode);
4346
b25f32cb 4347 ether_addr_copy(cmd->peer_macaddr.addr, arg->addr);
5e3dd157
KV		 4348
4349 cmd->peer_legacy_rates.num_rates =
4350 __cpu_to_le32(arg->peer_legacy_rates.num_rates);
4351 memcpy(cmd->peer_legacy_rates.rates, arg->peer_legacy_rates.rates,
4352 arg->peer_legacy_rates.num_rates);
4353
4354 cmd->peer_ht_rates.num_rates =
4355 __cpu_to_le32(arg->peer_ht_rates.num_rates);
4356 memcpy(cmd->peer_ht_rates.rates, arg->peer_ht_rates.rates,
4357 arg->peer_ht_rates.num_rates);
4358
4359 cmd->peer_vht_rates.rx_max_rate =
4360 __cpu_to_le32(arg->peer_vht_rates.rx_max_rate);
4361 cmd->peer_vht_rates.rx_mcs_set =
4362 __cpu_to_le32(arg->peer_vht_rates.rx_mcs_set);
4363 cmd->peer_vht_rates.tx_max_rate =
4364 __cpu_to_le32(arg->peer_vht_rates.tx_max_rate);
4365 cmd->peer_vht_rates.tx_mcs_set =
4366 __cpu_to_le32(arg->peer_vht_rates.tx_mcs_set);
24c88f78
MK		 4367}
4368
4369static void
4370ath10k_wmi_peer_assoc_fill_main(struct ath10k *ar, void *buf,
4371 const struct wmi_peer_assoc_complete_arg *arg)
4372{
4373 struct wmi_main_peer_assoc_complete_cmd *cmd = buf;
4374
4375 ath10k_wmi_peer_assoc_fill(ar, buf, arg);
4376 memset(cmd->peer_ht_info, 0, sizeof(cmd->peer_ht_info));
4377}
4378
4379static void
4380ath10k_wmi_peer_assoc_fill_10_1(struct ath10k *ar, void *buf,
4381 const struct wmi_peer_assoc_complete_arg *arg)
4382{
4383 ath10k_wmi_peer_assoc_fill(ar, buf, arg);
4384}
4385
4386static void
4387ath10k_wmi_peer_assoc_fill_10_2(struct ath10k *ar, void *buf,
4388 const struct wmi_peer_assoc_complete_arg *arg)
4389{
4390 struct wmi_10_2_peer_assoc_complete_cmd *cmd = buf;
4391 int max_mcs, max_nss;
4392 u32 info0;
4393
4394 /* TODO: Is using max values okay with firmware? */
4395 max_mcs = 0xf;
4396 max_nss = 0xf;
4397
4398 info0 = SM(max_mcs, WMI_PEER_ASSOC_INFO0_MAX_MCS_IDX) |
4399 SM(max_nss, WMI_PEER_ASSOC_INFO0_MAX_NSS);
4400
4401 ath10k_wmi_peer_assoc_fill(ar, buf, arg);
4402 cmd->info0 = __cpu_to_le32(info0);
4403}
4404
4405int ath10k_wmi_peer_assoc(struct ath10k *ar,
4406 const struct wmi_peer_assoc_complete_arg *arg)
4407{
4408 struct sk_buff *skb;
4409 int len;
4410
4411 if (arg->peer_mpdu_density > 16)
4412 return -EINVAL;
4413 if (arg->peer_legacy_rates.num_rates > MAX_SUPPORTED_RATES)
4414 return -EINVAL;
4415 if (arg->peer_ht_rates.num_rates > MAX_SUPPORTED_RATES)
4416 return -EINVAL;
4417
4418 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) {
4419 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, ar->fw_features))
4420 len = sizeof(struct wmi_10_2_peer_assoc_complete_cmd);
4421 else
4422 len = sizeof(struct wmi_10_1_peer_assoc_complete_cmd);
4423 } else {
4424 len = sizeof(struct wmi_main_peer_assoc_complete_cmd);
4425 }
4426
7aa7a72a 4427 skb = ath10k_wmi_alloc_skb(ar, len);
24c88f78
MK		 4428 if (!skb)
4429 return -ENOMEM;
4430
4431 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) {
4432 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, ar->fw_features))
24c88f78 4433 ath10k_wmi_peer_assoc_fill_10_2(ar, skb->data, arg);
9de8f26f
PO		 4434 else
4435 ath10k_wmi_peer_assoc_fill_10_1(ar, skb->data, arg);
24c88f78
MK		 4436 } else {
4437 ath10k_wmi_peer_assoc_fill_main(ar, skb->data, arg);
4438 }
5e3dd157 4439
7aa7a72a 4440 ath10k_dbg(ar, ATH10K_DBG_WMI,
44d6fa90
CYY		 4441 "wmi peer assoc vdev %d addr %pM (%s)\n",
4442 arg->vdev_id, arg->addr,
4443 arg->peer_reassoc ? "reassociate" : "new");
ce42870e 4444 return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->peer_assoc_cmdid);
5e3dd157
KV		 4445}
4446
748afc47
MK		 4447/* This function assumes the beacon is already DMA mapped */
4448int ath10k_wmi_beacon_send_ref_nowait(struct ath10k_vif *arvif)
5e3dd157 4449{
748afc47 4450 struct wmi_bcn_tx_ref_cmd *cmd;
5e3dd157 4451 struct sk_buff *skb;
748afc47
MK		 4452 struct sk_buff *beacon = arvif->beacon;
4453 struct ath10k *ar = arvif->ar;
4454 struct ieee80211_hdr *hdr;
e2045481 4455 int ret;
748afc47 4456 u16 fc;
5e3dd157 4457
7aa7a72a 4458 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 4459 if (!skb)
4460 return -ENOMEM;
4461
748afc47
MK		 4462 hdr = (struct ieee80211_hdr *)beacon->data;
4463 fc = le16_to_cpu(hdr->frame_control);
4464
4465 cmd = (struct wmi_bcn_tx_ref_cmd *)skb->data;
4466 cmd->vdev_id = __cpu_to_le32(arvif->vdev_id);
4467 cmd->data_len = __cpu_to_le32(beacon->len);
4468 cmd->data_ptr = __cpu_to_le32(ATH10K_SKB_CB(beacon)->paddr);
4469 cmd->msdu_id = 0;
4470 cmd->frame_control = __cpu_to_le32(fc);
4471 cmd->flags = 0;
24c88f78 4472 cmd->antenna_mask = __cpu_to_le32(WMI_BCN_TX_REF_DEF_ANTENNA);
748afc47
MK		 4473
4474 if (ATH10K_SKB_CB(beacon)->bcn.dtim_zero)
4475 cmd->flags |= __cpu_to_le32(WMI_BCN_TX_REF_FLAG_DTIM_ZERO);
4476
4477 if (ATH10K_SKB_CB(beacon)->bcn.deliver_cab)
4478 cmd->flags |= __cpu_to_le32(WMI_BCN_TX_REF_FLAG_DELIVER_CAB);
4479
4480 ret = ath10k_wmi_cmd_send_nowait(ar, skb,
4481 ar->wmi.cmd->pdev_send_bcn_cmdid);
5e3dd157 4482
e2045481
MK		 4483 if (ret)
4484 dev_kfree_skb(skb);
4485
4486 return ret;
5e3dd157
KV		 4487}
4488
4489static void ath10k_wmi_pdev_set_wmm_param(struct wmi_wmm_params *params,
4490 const struct wmi_wmm_params_arg *arg)
4491{
4492 params->cwmin = __cpu_to_le32(arg->cwmin);
4493 params->cwmax = __cpu_to_le32(arg->cwmax);
4494 params->aifs = __cpu_to_le32(arg->aifs);
4495 params->txop = __cpu_to_le32(arg->txop);
4496 params->acm = __cpu_to_le32(arg->acm);
4497 params->no_ack = __cpu_to_le32(arg->no_ack);
4498}
4499
4500int ath10k_wmi_pdev_set_wmm_params(struct ath10k *ar,
5b07e07f 4501 const struct wmi_pdev_set_wmm_params_arg *arg)
5e3dd157
KV		 4502{
4503 struct wmi_pdev_set_wmm_params *cmd;
4504 struct sk_buff *skb;
4505
7aa7a72a 4506 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 4507 if (!skb)
4508 return -ENOMEM;
4509
4510 cmd = (struct wmi_pdev_set_wmm_params *)skb->data;
4511 ath10k_wmi_pdev_set_wmm_param(&cmd->ac_be, &arg->ac_be);
4512 ath10k_wmi_pdev_set_wmm_param(&cmd->ac_bk, &arg->ac_bk);
4513 ath10k_wmi_pdev_set_wmm_param(&cmd->ac_vi, &arg->ac_vi);
4514 ath10k_wmi_pdev_set_wmm_param(&cmd->ac_vo, &arg->ac_vo);
4515
7aa7a72a 4516 ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi pdev set wmm params\n");
ce42870e
BM		 4517 return ath10k_wmi_cmd_send(ar, skb,
4518 ar->wmi.cmd->pdev_set_wmm_params_cmdid);
5e3dd157
KV		 4519}
4520
4521int ath10k_wmi_request_stats(struct ath10k *ar, enum wmi_stats_id stats_id)
4522{
4523 struct wmi_request_stats_cmd *cmd;
4524 struct sk_buff *skb;
4525
7aa7a72a 4526 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
5e3dd157
KV		 4527 if (!skb)
4528 return -ENOMEM;
4529
4530 cmd = (struct wmi_request_stats_cmd *)skb->data;
4531 cmd->stats_id = __cpu_to_le32(stats_id);
4532
7aa7a72a 4533 ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi request stats %d\n", (int)stats_id);
ce42870e 4534 return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->request_stats_cmdid);
5e3dd157 4535}
9cfbce75
MK		 4536
4537int ath10k_wmi_force_fw_hang(struct ath10k *ar,
4538 enum wmi_force_fw_hang_type type, u32 delay_ms)
4539{
4540 struct wmi_force_fw_hang_cmd *cmd;
4541 struct sk_buff *skb;
4542
7aa7a72a 4543 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
9cfbce75
MK		 4544 if (!skb)
4545 return -ENOMEM;
4546
4547 cmd = (struct wmi_force_fw_hang_cmd *)skb->data;
4548 cmd->type = __cpu_to_le32(type);
4549 cmd->delay_ms = __cpu_to_le32(delay_ms);
4550
7aa7a72a 4551 ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi force fw hang %d delay %d\n",
9cfbce75 4552 type, delay_ms);
ce42870e 4553 return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->force_fw_hang_cmdid);
9cfbce75 4554}
f118a3e5
KV		 4555
4556int ath10k_wmi_dbglog_cfg(struct ath10k *ar, u32 module_enable)
4557{
4558 struct wmi_dbglog_cfg_cmd *cmd;
4559 struct sk_buff *skb;
4560 u32 cfg;
4561
7aa7a72a 4562 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
f118a3e5
KV		 4563 if (!skb)
4564 return -ENOMEM;
4565
4566 cmd = (struct wmi_dbglog_cfg_cmd *)skb->data;
4567
4568 if (module_enable) {
4569 cfg = SM(ATH10K_DBGLOG_LEVEL_VERBOSE,
4570 ATH10K_DBGLOG_CFG_LOG_LVL);
4571 } else {
4572 /* set back defaults, all modules with WARN level */
4573 cfg = SM(ATH10K_DBGLOG_LEVEL_WARN,
4574 ATH10K_DBGLOG_CFG_LOG_LVL);
4575 module_enable = ~0;
4576 }
4577
4578 cmd->module_enable = __cpu_to_le32(module_enable);
4579 cmd->module_valid = __cpu_to_le32(~0);
4580 cmd->config_enable = __cpu_to_le32(cfg);
4581 cmd->config_valid = __cpu_to_le32(ATH10K_DBGLOG_CFG_LOG_LVL_MASK);
4582
7aa7a72a 4583 ath10k_dbg(ar, ATH10K_DBG_WMI,
f118a3e5
KV		 4584 "wmi dbglog cfg modules %08x %08x config %08x %08x\n",
4585 __le32_to_cpu(cmd->module_enable),
4586 __le32_to_cpu(cmd->module_valid),
4587 __le32_to_cpu(cmd->config_enable),
4588 __le32_to_cpu(cmd->config_valid));
4589
4590 return ath10k_wmi_cmd_send(ar, skb, ar->wmi.cmd->dbglog_cfg_cmdid);
4591}
b79b9baa 4592
90174455
RM		 4593int ath10k_wmi_pdev_pktlog_enable(struct ath10k *ar, u32 ev_bitmap)
4594{
4595 struct wmi_pdev_pktlog_enable_cmd *cmd;
4596 struct sk_buff *skb;
4597
4598 skb = ath10k_wmi_alloc_skb(ar, sizeof(*cmd));
4599 if (!skb)
4600 return -ENOMEM;
4601
4602 ev_bitmap &= ATH10K_PKTLOG_ANY;
4603 ath10k_dbg(ar, ATH10K_DBG_WMI,
4604 "wmi enable pktlog filter:%x\n", ev_bitmap);
4605
4606 cmd = (struct wmi_pdev_pktlog_enable_cmd *)skb->data;
4607 cmd->ev_bitmap = __cpu_to_le32(ev_bitmap);
4608 return ath10k_wmi_cmd_send(ar, skb,
4609 ar->wmi.cmd->pdev_pktlog_enable_cmdid);
4610}
4611
4612int ath10k_wmi_pdev_pktlog_disable(struct ath10k *ar)
4613{
4614 struct sk_buff *skb;
4615
4616 skb = ath10k_wmi_alloc_skb(ar, 0);
4617 if (!skb)
4618 return -ENOMEM;
4619
4620 ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi disable pktlog\n");
4621
4622 return ath10k_wmi_cmd_send(ar, skb,
4623 ar->wmi.cmd->pdev_pktlog_disable_cmdid);
4624}
4625
b79b9baa
MK		 4626int ath10k_wmi_attach(struct ath10k *ar)
4627{
4628 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) {
4629 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, ar->fw_features))
4630 ar->wmi.cmd = &wmi_10_2_cmd_map;
4631 else
4632 ar->wmi.cmd = &wmi_10x_cmd_map;
4633
4634 ar->wmi.vdev_param = &wmi_10x_vdev_param_map;
4635 ar->wmi.pdev_param = &wmi_10x_pdev_param_map;
4636 } else {
4637 ar->wmi.cmd = &wmi_cmd_map;
4638 ar->wmi.vdev_param = &wmi_vdev_param_map;
4639 ar->wmi.pdev_param = &wmi_pdev_param_map;
4640 }
4641
4642 init_completion(&ar->wmi.service_ready);
4643 init_completion(&ar->wmi.unified_ready);
b79b9baa
MK		 4644
4645 return 0;
4646}
4647
4648void ath10k_wmi_detach(struct ath10k *ar)
4649{
4650 int i;
4651
4652 /* free the host memory chunks requested by firmware */
4653 for (i = 0; i < ar->wmi.num_mem_chunks; i++) {
4654 dma_free_coherent(ar->dev,
4655 ar->wmi.mem_chunks[i].len,
4656 ar->wmi.mem_chunks[i].vaddr,
4657 ar->wmi.mem_chunks[i].paddr);
4658 }
4659
4660 ar->wmi.num_mem_chunks = 0;
4661}
Linux kernel - Deliverables
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