[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / attach.c

/*
 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

/*************************************\
* Attach/Detach Functions and helpers *
\*************************************/

#include <linux/pci.h>
#include <linux/slab.h>
#include "ath5k.h"
#include "reg.h"
#include "debug.h"
#include "base.h"

/**
 * ath5k_hw_post - Power On Self Test helper function
 *
 * @ah: The &struct ath5k_hw
 */
static int ath5k_hw_post(struct ath5k_hw *ah)
{

	static const u32 static_pattern[4] = {
		0x55555555,	0xaaaaaaaa,
		0x66666666,	0x99999999
	};
	static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) };
	int i, c;
	u16 cur_reg;
	u32 var_pattern;
	u32 init_val;
	u32 cur_val;

	for (c = 0; c < 2; c++) {

		cur_reg = regs[c];

		/* Save previous value */
		init_val = ath5k_hw_reg_read(ah, cur_reg);

		for (i = 0; i < 256; i++) {
			var_pattern = i << 16 | i;
			ath5k_hw_reg_write(ah, var_pattern, cur_reg);
			cur_val = ath5k_hw_reg_read(ah, cur_reg);

			if (cur_val != var_pattern) {
				ATH5K_ERR(ah, "POST Failed !!!\n");
				return -EAGAIN;
			}

			/* Found on ndiswrapper dumps */
			var_pattern = 0x0039080f;
			ath5k_hw_reg_write(ah, var_pattern, cur_reg);
		}

		for (i = 0; i < 4; i++) {
			var_pattern = static_pattern[i];
			ath5k_hw_reg_write(ah, var_pattern, cur_reg);
			cur_val = ath5k_hw_reg_read(ah, cur_reg);

			if (cur_val != var_pattern) {
				ATH5K_ERR(ah, "POST Failed !!!\n");
				return -EAGAIN;
			}

			/* Found on ndiswrapper dumps */
			var_pattern = 0x003b080f;
			ath5k_hw_reg_write(ah, var_pattern, cur_reg);
		}

		/* Restore previous value */
		ath5k_hw_reg_write(ah, init_val, cur_reg);

	}

	return 0;

}

/**
 * ath5k_hw_init - Check if hw is supported and init the needed structs
 *
 * @ah: The &struct ath5k_hw we got from the driver's init_softc function
 *
 * Check if the device is supported, perform a POST and initialize the needed
 * structs. Returns -ENOMEM if we don't have memory for the needed structs,
 * -ENODEV if the device is not supported or prints an error msg if something
 * else went wrong.
 */
int ath5k_hw_init(struct ath5k_hw *ah)
{
	static const u8 zero_mac[ETH_ALEN] = { };
	struct ath_common *common = ath5k_hw_common(ah);
	struct pci_dev *pdev = ah->pdev;
	struct ath5k_eeprom_info *ee;
	int ret;
	u32 srev;

	/*
	 * HW information
	 */
	ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
	ah->ah_bwmode = AR5K_BWMODE_DEFAULT;
	ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
	ah->ah_imr = 0;
	ah->ah_retry_short = AR5K_INIT_RETRY_SHORT;
	ah->ah_retry_long = AR5K_INIT_RETRY_LONG;
	ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT;
	ah->ah_noise_floor = -95;	/* until first NF calibration is run */
	ah->ani_state.ani_mode = ATH5K_ANI_MODE_AUTO;
	ah->ah_current_channel = &ah->channels[0];

	/*
	 * Find the mac version
	 */
	ath5k_hw_read_srev(ah);
	srev = ah->ah_mac_srev;
	if (srev < AR5K_SREV_AR5311)
		ah->ah_version = AR5K_AR5210;
	else if (srev < AR5K_SREV_AR5212)
		ah->ah_version = AR5K_AR5211;
	else
		ah->ah_version = AR5K_AR5212;

	/* Get the MAC revision */
	ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
	ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);

	/* Fill the ath5k_hw struct with the needed functions */
	ret = ath5k_hw_init_desc_functions(ah);
	if (ret)
		goto err;

	/* Bring device out of sleep and reset its units */
	ret = ath5k_hw_nic_wakeup(ah, 0, true);
	if (ret)
		goto err;

	/* Get PHY and RADIO revisions */
	ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
			0xffffffff;
	ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
			CHANNEL_5GHZ);
	ah->ah_phy = AR5K_PHY(0);

	/* Try to identify radio chip based on its srev */
	switch (ah->ah_radio_5ghz_revision & 0xf0) {
	case AR5K_SREV_RAD_5111:
		ah->ah_radio = AR5K_RF5111;
		ah->ah_single_chip = false;
		ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
							CHANNEL_2GHZ);
		break;
	case AR5K_SREV_RAD_5112:
	case AR5K_SREV_RAD_2112:
		ah->ah_radio = AR5K_RF5112;
		ah->ah_single_chip = false;
		ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
							CHANNEL_2GHZ);
		break;
	case AR5K_SREV_RAD_2413:
		ah->ah_radio = AR5K_RF2413;
		ah->ah_single_chip = true;
		break;
	case AR5K_SREV_RAD_5413:
		ah->ah_radio = AR5K_RF5413;
		ah->ah_single_chip = true;
		break;
	case AR5K_SREV_RAD_2316:
		ah->ah_radio = AR5K_RF2316;
		ah->ah_single_chip = true;
		break;
	case AR5K_SREV_RAD_2317:
		ah->ah_radio = AR5K_RF2317;
		ah->ah_single_chip = true;
		break;
	case AR5K_SREV_RAD_5424:
		if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
		    ah->ah_mac_version == AR5K_SREV_AR2417) {
			ah->ah_radio = AR5K_RF2425;
			ah->ah_single_chip = true;
		} else {
			ah->ah_radio = AR5K_RF5413;
			ah->ah_single_chip = true;
		}
		break;
	default:
		/* Identify radio based on mac/phy srev */
		if (ah->ah_version == AR5K_AR5210) {
			ah->ah_radio = AR5K_RF5110;
			ah->ah_single_chip = false;
		} else if (ah->ah_version == AR5K_AR5211) {
			ah->ah_radio = AR5K_RF5111;
			ah->ah_single_chip = false;
			ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
								CHANNEL_2GHZ);
		} else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
			   ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
			   ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
			ah->ah_radio = AR5K_RF2425;
			ah->ah_single_chip = true;
			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
		} else if (srev == AR5K_SREV_AR5213A &&
			   ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
			ah->ah_radio = AR5K_RF5112;
			ah->ah_single_chip = false;
			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
		} else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4) ||
			   ah->ah_mac_version == (AR5K_SREV_AR2315_R6 >> 4)) {
			ah->ah_radio = AR5K_RF2316;
			ah->ah_single_chip = true;
			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
		} else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
			   ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
			ah->ah_radio = AR5K_RF5413;
			ah->ah_single_chip = true;
			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
		} else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
			   ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
			ah->ah_radio = AR5K_RF2413;
			ah->ah_single_chip = true;
			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
		} else {
			ATH5K_ERR(ah, "Couldn't identify radio revision.\n");
			ret = -ENODEV;
			goto err;
		}
	}


	/* Return on unsupported chips (unsupported eeprom etc) */
	if ((srev >= AR5K_SREV_AR5416) && (srev < AR5K_SREV_AR2425)) {
		ATH5K_ERR(ah, "Device not yet supported.\n");
		ret = -ENODEV;
		goto err;
	}

	/*
	 * POST
	 */
	ret = ath5k_hw_post(ah);
	if (ret)
		goto err;

	/* Enable pci core retry fix on Hainan (5213A) and later chips */
	if (srev >= AR5K_SREV_AR5213A)
		AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX);

	/*
	 * Get card capabilities, calibration values etc
	 * TODO: EEPROM work
	 */
	ret = ath5k_eeprom_init(ah);
	if (ret) {
		ATH5K_ERR(ah, "unable to init EEPROM\n");
		goto err;
	}

	ee = &ah->ah_capabilities.cap_eeprom;

	/*
	 * Write PCI-E power save settings
	 */
	if ((ah->ah_version == AR5K_AR5212) && pdev && (pci_is_pcie(pdev))) {
		ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
		ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);

		/* Shut off RX when elecidle is asserted */
		ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
		ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);

		/* If serdes programming is enabled, increase PCI-E
		 * tx power for systems with long trace from host
		 * to minicard connector. */
		if (ee->ee_serdes)
			ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
		else
			ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES);

		/* Shut off PLL and CLKREQ active in L1 */
		ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);

		/* Preserve other settings */
		ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
		ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
		ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);

		/* Reset SERDES to load new settings */
		ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
		mdelay(1);
	}

	/* Get misc capabilities */
	ret = ath5k_hw_set_capabilities(ah);
	if (ret) {
		ATH5K_ERR(ah, "unable to get device capabilities\n");
		goto err;
	}

	if (test_bit(ATH_STAT_2G_DISABLED, ah->status)) {
		__clear_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode);
		__clear_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode);
	}

	/* Crypto settings */
	common->keymax = (ah->ah_version == AR5K_AR5210 ?
			  AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211);

	if (srev >= AR5K_SREV_AR5212_V4 &&
	    (ee->ee_version < AR5K_EEPROM_VERSION_5_0 ||
	    !AR5K_EEPROM_AES_DIS(ee->ee_misc5)))
		common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;

	if (srev >= AR5K_SREV_AR2414) {
		common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
		AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
			AR5K_MISC_MODE_COMBINED_MIC);
	}

	/* MAC address is cleared until add_interface */
	ath5k_hw_set_lladdr(ah, zero_mac);

	/* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
	memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN);
	ath5k_hw_set_bssid(ah);
	ath5k_hw_set_opmode(ah, ah->opmode);

	ath5k_hw_rfgain_opt_init(ah);

	ath5k_hw_init_nfcal_hist(ah);

	/* turn on HW LEDs */
	ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);

	return 0;
err:
	return ret;
}

/**
 * ath5k_hw_deinit - Free the ath5k_hw struct
 *
 * @ah: The &struct ath5k_hw
 */
void ath5k_hw_deinit(struct ath5k_hw *ah)
{
	__set_bit(ATH_STAT_INVALID, ah->status);

	if (ah->ah_rf_banks != NULL)
		kfree(ah->ah_rf_banks);

	ath5k_eeprom_detach(ah);

	/* assume interrupts are down */
}
Commit	Line	Data
c6e387a2 NK	1	/*
	2	* Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
	3	* Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
	4	*
	5	* Permission to use, copy, modify, and distribute this software for any
	6	* purpose with or without fee is hereby granted, provided that the above
	7	* copyright notice and this permission notice appear in all copies.
	8	*
	9	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	10	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	11	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	12	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	13	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	14	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	15	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	16	*
	17	*/
	18
	19	/*************************************\
	20	* Attach/Detach Functions and helpers *
	21	\*************************************/
	22
	23	#include <linux/pci.h>
5a0e3ad6	24	#include <linux/slab.h>
c6e387a2 NK	25	#include "ath5k.h"
	26	#include "reg.h"
	27	#include "debug.h"
	28	#include "base.h"
	29
	30	/**
	31	* ath5k_hw_post - Power On Self Test helper function
	32	*
	33	* @ah: The &struct ath5k_hw
	34	*/
	35	static int ath5k_hw_post(struct ath5k_hw *ah)
	36	{
	37
2c91108c	38	static const u32 static_pattern[4] = {
c6e387a2 NK	39	0x55555555, 0xaaaaaaaa,
	40	0x66666666, 0x99999999
	41	};
2c91108c JS	42	static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) };
	43	int i, c;
	44	u16 cur_reg;
	45	u32 var_pattern;
c6e387a2 NK	46	u32 init_val;
	47	u32 cur_val;
	48
	49	for (c = 0; c < 2; c++) {
	50
	51	cur_reg = regs[c];
	52
	53	/* Save previous value */
	54	init_val = ath5k_hw_reg_read(ah, cur_reg);
	55
	56	for (i = 0; i < 256; i++) {
	57	var_pattern = i << 16 \| i;
	58	ath5k_hw_reg_write(ah, var_pattern, cur_reg);
	59	cur_val = ath5k_hw_reg_read(ah, cur_reg);
	60
	61	if (cur_val != var_pattern) {
e0d687bd	62	ATH5K_ERR(ah, "POST Failed !!!\n");
c6e387a2 NK	63	return -EAGAIN;
	64	}
	65
	66	/* Found on ndiswrapper dumps */
	67	var_pattern = 0x0039080f;
	68	ath5k_hw_reg_write(ah, var_pattern, cur_reg);
	69	}
	70
	71	for (i = 0; i < 4; i++) {
	72	var_pattern = static_pattern[i];
	73	ath5k_hw_reg_write(ah, var_pattern, cur_reg);
	74	cur_val = ath5k_hw_reg_read(ah, cur_reg);
	75
	76	if (cur_val != var_pattern) {
e0d687bd	77	ATH5K_ERR(ah, "POST Failed !!!\n");
c6e387a2 NK	78	return -EAGAIN;
	79	}
	80
	81	/* Found on ndiswrapper dumps */
	82	var_pattern = 0x003b080f;
	83	ath5k_hw_reg_write(ah, var_pattern, cur_reg);
	84	}
	85
	86	/* Restore previous value */
	87	ath5k_hw_reg_write(ah, init_val, cur_reg);
	88
	89	}
	90
	91	return 0;
	92
	93	}
	94
	95	/**
132b1c3e	96	* ath5k_hw_init - Check if hw is supported and init the needed structs
c6e387a2	97	*
e0d687bd	98	* @ah: The &struct ath5k_hw we got from the driver's init_softc function
c6e387a2 NK	99	*
	100	* Check if the device is supported, perform a POST and initialize the needed
	101	* structs. Returns -ENOMEM if we don't have memory for the needed structs,
	102	* -ENODEV if the device is not supported or prints an error msg if something
	103	* else went wrong.
	104	*/
e0d687bd	105	int ath5k_hw_init(struct ath5k_hw *ah)
c6e387a2	106	{
2724a74a	107	static const u8 zero_mac[ETH_ALEN] = { };
13b81559	108	struct ath_common *common = ath5k_hw_common(ah);
e0d687bd	109	struct pci_dev *pdev = ah->pdev;
1c818740	110	struct ath5k_eeprom_info *ee;
c6e387a2 NK	111	int ret;
	112	u32 srev;
	113
c6e387a2 NK	114	/*
	115	* HW information
	116	*/
c6e387a2	117	ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
fa3d2fee	118	ah->ah_bwmode = AR5K_BWMODE_DEFAULT;
c6e387a2 NK	119	ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
c6e387a2 NK	120	ah->ah_imr = 0;
76a9f6fd BR	121	ah->ah_retry_short = AR5K_INIT_RETRY_SHORT;
76a9f6fd BR	122	ah->ah_retry_long = AR5K_INIT_RETRY_LONG;
caec9112	123	ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT;
9d332c82	124	ah->ah_noise_floor = -95; /* until first NF calibration is run */
e0d687bd PR	125	ah->ani_state.ani_mode = ATH5K_ANI_MODE_AUTO;
e0d687bd PR	126	ah->ah_current_channel = &ah->channels[0];
c6e387a2 NK	127
c6e387a2 NK	128	/*
97a81f5c	129	* Find the mac version
c6e387a2	130	*/
e7aecd32 FF	131	ath5k_hw_read_srev(ah);
e7aecd32 FF	132	srev = ah->ah_mac_srev;
97a81f5c PR	133	if (srev < AR5K_SREV_AR5311)
	134	ah->ah_version = AR5K_AR5210;
	135	else if (srev < AR5K_SREV_AR5212)
	136	ah->ah_version = AR5K_AR5211;
	137	else
	138	ah->ah_version = AR5K_AR5212;
c6e387a2	139
e7aecd32 FF	140	/* Get the MAC revision */
	141	ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
	142	ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
	143
a180a130	144	/* Fill the ath5k_hw struct with the needed functions */
c6e387a2 NK	145	ret = ath5k_hw_init_desc_functions(ah);
c6e387a2 NK	146	if (ret)
3d435ad7	147	goto err;
c6e387a2	148
a180a130	149	/* Bring device out of sleep and reset its units */
edd7fc70	150	ret = ath5k_hw_nic_wakeup(ah, 0, true);
c6e387a2	151	if (ret)
3d435ad7	152	goto err;
c6e387a2	153
e7aecd32	154	/* Get PHY and RADIO revisions */
c6e387a2 NK	155	ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
	156	0xffffffff;
	157	ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
	158	CHANNEL_5GHZ);
ee81c554	159	ah->ah_phy = AR5K_PHY(0);
c6e387a2	160
a180a130	161	/* Try to identify radio chip based on its srev */
ee81c554 NK	162	switch (ah->ah_radio_5ghz_revision & 0xf0) {
ee81c554 NK	163	case AR5K_SREV_RAD_5111:
c6e387a2	164	ah->ah_radio = AR5K_RF5111;
ee81c554 NK	165	ah->ah_single_chip = false;
	166	ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
	167	CHANNEL_2GHZ);
ee81c554 NK	168	break;
	169	case AR5K_SREV_RAD_5112:
	170	case AR5K_SREV_RAD_2112:
c6e387a2	171	ah->ah_radio = AR5K_RF5112;
ee81c554 NK	172	ah->ah_single_chip = false;
	173	ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
	174	CHANNEL_2GHZ);
ee81c554 NK	175	break;
ee81c554 NK	176	case AR5K_SREV_RAD_2413:
c6e387a2	177	ah->ah_radio = AR5K_RF2413;
ee81c554	178	ah->ah_single_chip = true;
ee81c554 NK	179	break;
ee81c554 NK	180	case AR5K_SREV_RAD_5413:
c6e387a2	181	ah->ah_radio = AR5K_RF5413;
ee81c554	182	ah->ah_single_chip = true;
ee81c554 NK	183	break;
	184	case AR5K_SREV_RAD_2316:
	185	ah->ah_radio = AR5K_RF2316;
	186	ah->ah_single_chip = true;
ee81c554 NK	187	break;
	188	case AR5K_SREV_RAD_2317:
	189	ah->ah_radio = AR5K_RF2317;
	190	ah->ah_single_chip = true;
ee81c554 NK	191	break;
	192	case AR5K_SREV_RAD_5424:
	193	if (ah->ah_mac_version == AR5K_SREV_AR2425 \|\|
e4bbf2f5	194	ah->ah_mac_version == AR5K_SREV_AR2417) {
ee81c554 NK	195	ah->ah_radio = AR5K_RF2425;
ee81c554 NK	196	ah->ah_single_chip = true;
ee81c554	197	} else {
c6e387a2	198	ah->ah_radio = AR5K_RF5413;
ee81c554	199	ah->ah_single_chip = true;
ee81c554 NK	200	}
	201	break;
	202	default:
	203	/* Identify radio based on mac/phy srev */
	204	if (ah->ah_version == AR5K_AR5210) {
	205	ah->ah_radio = AR5K_RF5110;
	206	ah->ah_single_chip = false;
	207	} else if (ah->ah_version == AR5K_AR5211) {
	208	ah->ah_radio = AR5K_RF5111;
	209	ah->ah_single_chip = false;
	210	ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
	211	CHANNEL_2GHZ);
	212	} else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) \|\|
e4bbf2f5 PR	213	ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) \|\|
e4bbf2f5 PR	214	ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
ee81c554 NK	215	ah->ah_radio = AR5K_RF2425;
	216	ah->ah_single_chip = true;
	217	ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
ee81c554	218	} else if (srev == AR5K_SREV_AR5213A &&
e4bbf2f5	219	ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
ee81c554 NK	220	ah->ah_radio = AR5K_RF5112;
ee81c554 NK	221	ah->ah_single_chip = false;
e8f055f0	222	ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
d985255e	223	} else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4) \|\|
e4bbf2f5	224	ah->ah_mac_version == (AR5K_SREV_AR2315_R6 >> 4)) {
ee81c554 NK	225	ah->ah_radio = AR5K_RF2316;
	226	ah->ah_single_chip = true;
	227	ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
ee81c554	228	} else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) \|\|
e4bbf2f5	229	ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
ee81c554 NK	230	ah->ah_radio = AR5K_RF5413;
	231	ah->ah_single_chip = true;
	232	ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
ee81c554	233	} else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) \|\|
e4bbf2f5	234	ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
ee81c554 NK	235	ah->ah_radio = AR5K_RF2413;
	236	ah->ah_single_chip = true;
	237	ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
ee81c554	238	} else {
e0d687bd	239	ATH5K_ERR(ah, "Couldn't identify radio revision.\n");
ee81c554	240	ret = -ENODEV;
3d435ad7	241	goto err;
c6e387a2 NK	242	}
c6e387a2 NK	243	}
ee81c554 NK	244
ee81c554 NK	245
6a2a0e73	246	/* Return on unsupported chips (unsupported eeprom etc) */
e4bbf2f5	247	if ((srev >= AR5K_SREV_AR5416) && (srev < AR5K_SREV_AR2425)) {
e0d687bd	248	ATH5K_ERR(ah, "Device not yet supported.\n");
ee81c554	249	ret = -ENODEV;
3d435ad7	250	goto err;
ee81c554	251	}
c6e387a2	252
c6e387a2 NK	253	/*
	254	* POST
	255	*/
	256	ret = ath5k_hw_post(ah);
	257	if (ret)
3d435ad7	258	goto err;
c6e387a2	259
ee81c554 NK	260	/* Enable pci core retry fix on Hainan (5213A) and later chips */
ee81c554 NK	261	if (srev >= AR5K_SREV_AR5213A)
b55a5de1	262	AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX);
c6e387a2 NK	263
c6e387a2 NK	264	/*
ee81c554 NK	265	* Get card capabilities, calibration values etc
ee81c554 NK	266	* TODO: EEPROM work
c6e387a2 NK	267	*/
	268	ret = ath5k_eeprom_init(ah);
	269	if (ret) {
e0d687bd	270	ATH5K_ERR(ah, "unable to init EEPROM\n");
3d435ad7	271	goto err;
c6e387a2 NK	272	}
c6e387a2 NK	273
394317fc LR	274	ee = &ah->ah_capabilities.cap_eeprom;
394317fc LR	275
c38e7a93 NK	276	/*
	277	* Write PCI-E power save settings
	278	*/
e98b06b0	279	if ((ah->ah_version == AR5K_AR5212) && pdev && (pci_is_pcie(pdev))) {
c38e7a93 NK	280	ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
	281	ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
	282
	283	/* Shut off RX when elecidle is asserted */
	284	ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
	285	ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
	286
6a2a0e73	287	/* If serdes programming is enabled, increase PCI-E
c38e7a93 NK	288	* tx power for systems with long trace from host
	289	* to minicard connector. */
	290	if (ee->ee_serdes)
	291	ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
	292	else
	293	ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES);
	294
	295	/* Shut off PLL and CLKREQ active in L1 */
	296	ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
	297
	298	/* Preserve other settings */
	299	ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
	300	ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
	301	ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
	302
	303	/* Reset SERDES to load new settings */
	304	ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
	305	mdelay(1);
	306	}
	307
c6e387a2 NK	308	/* Get misc capabilities */
	309	ret = ath5k_hw_set_capabilities(ah);
	310	if (ret) {
e0d687bd	311	ATH5K_ERR(ah, "unable to get device capabilities\n");
3d435ad7	312	goto err;
c6e387a2 NK	313	}
c6e387a2 NK	314
e0d687bd	315	if (test_bit(ATH_STAT_2G_DISABLED, ah->status)) {
3a9dddea FF	316	__clear_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode);
	317	__clear_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode);
	318	}
	319
1c818740	320	/* Crypto settings */
e0d687bd	321	common->keymax = (ah->ah_version == AR5K_AR5210 ?
e0f8c2a9 BR	322	AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211);
e0f8c2a9 BR	323
781f3136	324	if (srev >= AR5K_SREV_AR5212_V4 &&
32377b6c	325	(ee->ee_version < AR5K_EEPROM_VERSION_5_0 \|\|
781f3136	326	!AR5K_EEPROM_AES_DIS(ee->ee_misc5)))
ce2220d1	327	common->crypt_caps \|= ATH_CRYPT_CAP_CIPHER_AESCCM;
1c818740	328
f650470a	329	if (srev >= AR5K_SREV_AR2414) {
781f3136	330	common->crypt_caps \|= ATH_CRYPT_CAP_MIC_COMBINED;
f650470a BC	331	AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
	332	AR5K_MISC_MODE_COMBINED_MIC);
	333	}
	334
0e149cf5	335	/* MAC address is cleared until add_interface */
2724a74a	336	ath5k_hw_set_lladdr(ah, zero_mac);
0e149cf5	337
c6e387a2	338	/* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
954fecea	339	memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN);
418de6d9	340	ath5k_hw_set_bssid(ah);
e0d687bd	341	ath5k_hw_set_opmode(ah, ah->opmode);
c6e387a2	342
6f3b414a	343	ath5k_hw_rfgain_opt_init(ah);
c6e387a2	344
e5e2647f BC	345	ath5k_hw_init_nfcal_hist(ah);
e5e2647f BC	346
f0f3d388 BC	347	/* turn on HW LEDs */
	348	ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);
	349
9adca126	350	return 0;
3d435ad7	351	err:
9adca126	352	return ret;
c6e387a2 NK	353	}
	354
	355	/**
132b1c3e	356	* ath5k_hw_deinit - Free the ath5k_hw struct
c6e387a2 NK	357	*
	358	* @ah: The &struct ath5k_hw
	359	*/
132b1c3e	360	void ath5k_hw_deinit(struct ath5k_hw *ah)
c6e387a2	361	{
e0d687bd	362	__set_bit(ATH_STAT_INVALID, ah->status);
c6e387a2 NK	363
	364	if (ah->ah_rf_banks != NULL)
	365	kfree(ah->ah_rf_banks);
	366
8f655dde NK	367	ath5k_eeprom_detach(ah);
8f655dde NK	368
c6e387a2	369	/* assume interrupts are down */
c6e387a2	370	}