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Merge tag 'platform-drivers-x86-v3.18-1' of git://git.infradead.org/users/dvhart...
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
516304b0
JP		 43#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
fa1c114f
JS		 45#include <linux/module.h>
46#include <linux/delay.h>
b7f080cf 47#include <linux/dma-mapping.h>
274c7c36 48#include <linux/hardirq.h>
fa1c114f 49#include <linux/if.h>
274c7c36 50#include <linux/io.h>
fa1c114f
JS		 51#include <linux/netdevice.h>
52#include <linux/cache.h>
fa1c114f
JS		 53#include <linux/ethtool.h>
54#include <linux/uaccess.h>
5a0e3ad6 55#include <linux/slab.h>
b1ae1edf 56#include <linux/etherdevice.h>
931be260 57#include <linux/nl80211.h>
fa1c114f 58
4d70f2fb 59#include <net/cfg80211.h>
fa1c114f
JS		 60#include <net/ieee80211_radiotap.h>
61
62#include <asm/unaligned.h>
63
0967e01e 64#include <net/mac80211.h>
fa1c114f
JS		 65#include "base.h"
66#include "reg.h"
67#include "debug.h"
2111ac0d 68#include "ani.h"
931be260
PR		 69#include "ath5k.h"
70#include "../regd.h"
fa1c114f 71
0e472252
BC		 72#define CREATE_TRACE_POINTS
73#include "trace.h"
74
eb939922 75bool ath5k_modparam_nohwcrypt;
18cb6e32 76module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 77MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 78
eb939922 79static bool modparam_fastchanswitch;
a99168ee
NK		 80module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO);
81MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
82
11deb533 83static bool ath5k_modparam_no_hw_rfkill_switch;
84e1e737
NK		 84module_param_named(no_hw_rfkill_switch, ath5k_modparam_no_hw_rfkill_switch,
85 bool, S_IRUGO);
86MODULE_PARM_DESC(no_hw_rfkill_switch, "Ignore the GPIO RFKill switch state");
87
a99168ee 88
fa1c114f
JS		 89/* Module info */
90MODULE_AUTHOR("Jiri Slaby");
91MODULE_AUTHOR("Nick Kossifidis");
92MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
93MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
94MODULE_LICENSE("Dual BSD/GPL");
fa1c114f 95
132b1c3e 96static int ath5k_init(struct ieee80211_hw *hw);
e0d687bd 97static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
8aec7af9 98 bool skip_pcu);
fa1c114f 99
fa1c114f 100/* Known SREVs */
2c91108c 101static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 102 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
103 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
104 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
105 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
106 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
107 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
108 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
109 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
110 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
111 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
112 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
113 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
114 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
115 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
116 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
117 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
118 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
119 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
120 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 121 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
122 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 123 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 124 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
125 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
126 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 127 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 128 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
129 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 130 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
131 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
132 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
1bef016a 133 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 134 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
135 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
136};
137
2c91108c 138static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 139 { .bitrate = 10,
140 .hw_value = ATH5K_RATE_CODE_1M, },
141 { .bitrate = 20,
142 .hw_value = ATH5K_RATE_CODE_2M,
143 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
144 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
145 { .bitrate = 55,
146 .hw_value = ATH5K_RATE_CODE_5_5M,
147 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
148 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
149 { .bitrate = 110,
150 .hw_value = ATH5K_RATE_CODE_11M,
151 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
152 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
153 { .bitrate = 60,
154 .hw_value = ATH5K_RATE_CODE_6M,
6a09ae95
SW		 155 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
156 IEEE80211_RATE_SUPPORTS_10MHZ },
63266a65
BR		 157 { .bitrate = 90,
158 .hw_value = ATH5K_RATE_CODE_9M,
6a09ae95
SW		 159 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
160 IEEE80211_RATE_SUPPORTS_10MHZ },
63266a65
BR		 161 { .bitrate = 120,
162 .hw_value = ATH5K_RATE_CODE_12M,
6a09ae95
SW		 163 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
164 IEEE80211_RATE_SUPPORTS_10MHZ },
63266a65
BR		 165 { .bitrate = 180,
166 .hw_value = ATH5K_RATE_CODE_18M,
6a09ae95
SW		 167 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
168 IEEE80211_RATE_SUPPORTS_10MHZ },
63266a65
BR		 169 { .bitrate = 240,
170 .hw_value = ATH5K_RATE_CODE_24M,
6a09ae95
SW		 171 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
172 IEEE80211_RATE_SUPPORTS_10MHZ },
63266a65
BR		 173 { .bitrate = 360,
174 .hw_value = ATH5K_RATE_CODE_36M,
6a09ae95
SW		 175 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
176 IEEE80211_RATE_SUPPORTS_10MHZ },
63266a65
BR		 177 { .bitrate = 480,
178 .hw_value = ATH5K_RATE_CODE_48M,
6a09ae95
SW		 179 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
180 IEEE80211_RATE_SUPPORTS_10MHZ },
63266a65
BR		 181 { .bitrate = 540,
182 .hw_value = ATH5K_RATE_CODE_54M,
6a09ae95
SW		 183 .flags = IEEE80211_RATE_SUPPORTS_5MHZ |
184 IEEE80211_RATE_SUPPORTS_10MHZ },
63266a65
BR		 185};
186
fa1c114f
JS		 187static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
188{
189 u64 tsf = ath5k_hw_get_tsf64(ah);
190
191 if ((tsf & 0x7fff) < rstamp)
192 tsf -= 0x8000;
193
194 return (tsf & ~0x7fff) | rstamp;
195}
196
e5b046d8 197const char *
fa1c114f
JS		 198ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
199{
200 const char *name = "xxxxx";
201 unsigned int i;
202
203 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
204 if (srev_names[i].sr_type != type)
205 continue;
75d0edb8
NK		 206
207 if ((val & 0xf0) == srev_names[i].sr_val)
208 name = srev_names[i].sr_name;
209
210 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 211 name = srev_names[i].sr_name;
212 break;
213 }
214 }
215
216 return name;
217}
e5aa8474
LR		 218static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
219{
220 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
221 return ath5k_hw_reg_read(ah, reg_offset);
222}
223
224static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
225{
226 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
227 ath5k_hw_reg_write(ah, val, reg_offset);
228}
229
230static const struct ath_ops ath5k_common_ops = {
231 .read = ath5k_ioread32,
232 .write = ath5k_iowrite32,
233};
fa1c114f 234
8a63facc
BC		 235/***********************\
236* Driver Initialization *
237\***********************/
238
0c0280bd
LR		 239static void ath5k_reg_notifier(struct wiphy *wiphy,
240 struct regulatory_request *request)
fa1c114f 241{
8a63facc 242 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
e0d687bd
PR		 243 struct ath5k_hw *ah = hw->priv;
244 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
fa1c114f 245
0c0280bd 246 ath_reg_notifier_apply(wiphy, request, regulatory);
8a63facc 247}
6ccf15a1 248
8a63facc
BC		 249/********************\
250* Channel/mode setup *
251\********************/
fa1c114f 252
8a63facc 253/*
2f8684ce 254 * Returns true for the channel numbers used.
8a63facc 255 */
2f8684ce
LR		 256#ifdef CONFIG_ATH5K_TEST_CHANNELS
257static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
258{
259 return true;
260}
261
262#else
410e6120 263static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
8a63facc 264{
410e6120
BR		 265 if (band == IEEE80211_BAND_2GHZ && chan <= 14)
266 return true;
267
268 return /* UNII 1,2 */
269 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
8a63facc
BC		 270 /* midband */
271 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
272 /* UNII-3 */
410e6120
BR		 273 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
274 /* 802.11j 5.030-5.080 GHz (20MHz) */
275 (chan == 8 || chan == 12 || chan == 16) ||
276 /* 802.11j 4.9GHz (20MHz) */
277 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
8a63facc 278}
2f8684ce 279#endif
fa1c114f 280
8a63facc 281static unsigned int
97d9c3a3
BR		 282ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
283 unsigned int mode, unsigned int max)
8a63facc 284{
32c25464 285 unsigned int count, size, freq, ch;
90c02d72 286 enum ieee80211_band band;
fa1c114f 287
8a63facc
BC		 288 switch (mode) {
289 case AR5K_MODE_11A:
8a63facc 290 /* 1..220, but 2GHz frequencies are filtered by check_channel */
97d9c3a3 291 size = 220;
90c02d72 292 band = IEEE80211_BAND_5GHZ;
8a63facc
BC		 293 break;
294 case AR5K_MODE_11B:
295 case AR5K_MODE_11G:
8a63facc 296 size = 26;
90c02d72 297 band = IEEE80211_BAND_2GHZ;
8a63facc
BC		 298 break;
299 default:
e0d687bd 300 ATH5K_WARN(ah, "bad mode, not copying channels\n");
8a63facc 301 return 0;
fa1c114f
JS		 302 }
303
2b1351a3
BR		 304 count = 0;
305 for (ch = 1; ch <= size && count < max; ch++) {
90c02d72
BR		 306 freq = ieee80211_channel_to_frequency(ch, band);
307
308 if (freq == 0) /* mapping failed - not a standard channel */
309 continue;
fa1c114f 310
32c25464
PR		 311 /* Write channel info, needed for ath5k_channel_ok() */
312 channels[count].center_freq = freq;
313 channels[count].band = band;
314 channels[count].hw_value = mode;
315
8a63facc 316 /* Check if channel is supported by the chipset */
32c25464 317 if (!ath5k_channel_ok(ah, &channels[count]))
8a63facc 318 continue;
f59ac048 319
2f8684ce 320 if (!ath5k_is_standard_channel(ch, band))
8a63facc 321 continue;
f59ac048 322
8a63facc 323 count++;
8a63facc 324 }
fa1c114f 325
8a63facc
BC		 326 return count;
327}
fa1c114f 328
8a63facc 329static void
e0d687bd 330ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b)
8a63facc
BC		 331{
332 u8 i;
fa1c114f 333
8a63facc 334 for (i = 0; i < AR5K_MAX_RATES; i++)
e0d687bd 335 ah->rate_idx[b->band][i] = -1;
fa1c114f 336
8a63facc 337 for (i = 0; i < b->n_bitrates; i++) {
e0d687bd 338 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i;
8a63facc 339 if (b->bitrates[i].hw_value_short)
e0d687bd 340 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
fa1c114f 341 }
8a63facc 342}
fa1c114f 343
8a63facc
BC		 344static int
345ath5k_setup_bands(struct ieee80211_hw *hw)
346{
e0d687bd 347 struct ath5k_hw *ah = hw->priv;
8a63facc
BC		 348 struct ieee80211_supported_band *sband;
349 int max_c, count_c = 0;
350 int i;
fa1c114f 351
e0d687bd
PR		 352 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS);
353 max_c = ARRAY_SIZE(ah->channels);
db719718 354
8a63facc 355 /* 2GHz band */
e0d687bd 356 sband = &ah->sbands[IEEE80211_BAND_2GHZ];
8a63facc 357 sband->band = IEEE80211_BAND_2GHZ;
e0d687bd 358 sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0];
9adca126 359
e0d687bd 360 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) {
8a63facc
BC		 361 /* G mode */
362 memcpy(sband->bitrates, &ath5k_rates[0],
363 sizeof(struct ieee80211_rate) * 12);
364 sband->n_bitrates = 12;
2f7fe870 365
e0d687bd 366 sband->channels = ah->channels;
08105690 367 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 368 AR5K_MODE_11G, max_c);
fa1c114f 369
8a63facc
BC		 370 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
371 count_c = sband->n_channels;
372 max_c -= count_c;
e0d687bd 373 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) {
8a63facc
BC		 374 /* B mode */
375 memcpy(sband->bitrates, &ath5k_rates[0],
376 sizeof(struct ieee80211_rate) * 4);
377 sband->n_bitrates = 4;
fa1c114f 378
8a63facc
BC		 379 /* 5211 only supports B rates and uses 4bit rate codes
380 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
381 * fix them up here:
382 */
383 if (ah->ah_version == AR5K_AR5211) {
384 for (i = 0; i < 4; i++) {
385 sband->bitrates[i].hw_value =
386 sband->bitrates[i].hw_value & 0xF;
387 sband->bitrates[i].hw_value_short =
388 sband->bitrates[i].hw_value_short & 0xF;
fa1c114f
JS		 389 }
390 }
fa1c114f 391
e0d687bd 392 sband->channels = ah->channels;
08105690 393 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 394 AR5K_MODE_11B, max_c);
fa1c114f 395
8a63facc
BC		 396 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
397 count_c = sband->n_channels;
398 max_c -= count_c;
399 }
e0d687bd 400 ath5k_setup_rate_idx(ah, sband);
fa1c114f 401
8a63facc 402 /* 5GHz band, A mode */
e0d687bd
PR		 403 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
404 sband = &ah->sbands[IEEE80211_BAND_5GHZ];
8a63facc 405 sband->band = IEEE80211_BAND_5GHZ;
e0d687bd 406 sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 407
8a63facc
BC		 408 memcpy(sband->bitrates, &ath5k_rates[4],
409 sizeof(struct ieee80211_rate) * 8);
410 sband->n_bitrates = 8;
fa1c114f 411
e0d687bd 412 sband->channels = &ah->channels[count_c];
08105690 413 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 414 AR5K_MODE_11A, max_c);
fa1c114f 415
8a63facc
BC		 416 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
417 }
e0d687bd 418 ath5k_setup_rate_idx(ah, sband);
8a63facc 419
e0d687bd 420 ath5k_debug_dump_bands(ah);
fa1c114f 421
fa1c114f
JS		 422 return 0;
423}
424
8a63facc
BC		 425/*
426 * Set/change channels. We always reset the chip.
427 * To accomplish this we must first cleanup any pending DMA,
428 * then restart stuff after a la ath5k_init.
429 *
e0d687bd 430 * Called with ah->lock.
8a63facc 431 */
cd2c5486 432int
4d70f2fb 433ath5k_chan_set(struct ath5k_hw *ah, struct cfg80211_chan_def *chandef)
8a63facc 434{
e0d687bd 435 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
8a63facc 436 "channel set, resetting (%u -> %u MHz)\n",
4d70f2fb
SW		 437 ah->curchan->center_freq, chandef->chan->center_freq);
438
439 switch (chandef->width) {
440 case NL80211_CHAN_WIDTH_20:
441 case NL80211_CHAN_WIDTH_20_NOHT:
442 ah->ah_bwmode = AR5K_BWMODE_DEFAULT;
443 break;
444 case NL80211_CHAN_WIDTH_5:
445 ah->ah_bwmode = AR5K_BWMODE_5MHZ;
446 break;
447 case NL80211_CHAN_WIDTH_10:
448 ah->ah_bwmode = AR5K_BWMODE_10MHZ;
449 break;
450 default:
451 WARN_ON(1);
452 return -EINVAL;
453 }
8a63facc 454
8451d22d 455 /*
8a63facc
BC		 456 * To switch channels clear any pending DMA operations;
457 * wait long enough for the RX fifo to drain, reset the
458 * hardware at the new frequency, and then re-enable
459 * the relevant bits of the h/w.
8451d22d 460 */
4d70f2fb 461 return ath5k_reset(ah, chandef->chan, true);
fa1c114f 462}
fa1c114f 463
e4b0b32a 464void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
b1ae1edf 465{
e4b0b32a 466 struct ath5k_vif_iter_data *iter_data = data;
b1ae1edf 467 int i;
62c58fb4 468 struct ath5k_vif *avf = (void *)vif->drv_priv;
b1ae1edf
BG		 469
470 if (iter_data->hw_macaddr)
471 for (i = 0; i < ETH_ALEN; i++)
472 iter_data->mask[i] &=
473 ~(iter_data->hw_macaddr[i] ^ mac[i]);
474
475 if (!iter_data->found_active) {
476 iter_data->found_active = true;
477 memcpy(iter_data->active_mac, mac, ETH_ALEN);
478 }
479
480 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
2e42e474 481 if (ether_addr_equal(iter_data->hw_macaddr, mac))
b1ae1edf
BG		 482 iter_data->need_set_hw_addr = false;
483
484 if (!iter_data->any_assoc) {
b1ae1edf
BG		 485 if (avf->assoc)
486 iter_data->any_assoc = true;
487 }
62c58fb4
BG		 488
489 /* Calculate combined mode - when APs are active, operate in AP mode.
490 * Otherwise use the mode of the new interface. This can currently
491 * only deal with combinations of APs and STAs. Only one ad-hoc
7afbb2f0 492 * interfaces is allowed.
62c58fb4
BG		 493 */
494 if (avf->opmode == NL80211_IFTYPE_AP)
495 iter_data->opmode = NL80211_IFTYPE_AP;
e4b0b32a
BG		 496 else {
497 if (avf->opmode == NL80211_IFTYPE_STATION)
498 iter_data->n_stas++;
62c58fb4
BG		 499 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
500 iter_data->opmode = avf->opmode;
e4b0b32a 501 }
b1ae1edf
BG		 502}
503
cd2c5486 504void
e0d687bd 505ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
cd2c5486 506 struct ieee80211_vif *vif)
b1ae1edf 507{
e0d687bd 508 struct ath_common *common = ath5k_hw_common(ah);
e4b0b32a
BG		 509 struct ath5k_vif_iter_data iter_data;
510 u32 rfilt;
b1ae1edf
BG		 511
512 /*
513 * Use the hardware MAC address as reference, the hardware uses it
514 * together with the BSSID mask when matching addresses.
515 */
516 iter_data.hw_macaddr = common->macaddr;
517 memset(&iter_data.mask, 0xff, ETH_ALEN);
518 iter_data.found_active = false;
519 iter_data.need_set_hw_addr = true;
62c58fb4 520 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
e4b0b32a 521 iter_data.n_stas = 0;
b1ae1edf
BG		 522
523 if (vif)
e4b0b32a 524 ath5k_vif_iter(&iter_data, vif->addr, vif);
b1ae1edf
BG		 525
526 /* Get list of all active MAC addresses */
8b2c9824
JB		 527 ieee80211_iterate_active_interfaces_atomic(
528 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
529 ath5k_vif_iter, &iter_data);
e0d687bd 530 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN);
b1ae1edf 531
e0d687bd
PR		 532 ah->opmode = iter_data.opmode;
533 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED)
62c58fb4 534 /* Nothing active, default to station mode */
e0d687bd 535 ah->opmode = NL80211_IFTYPE_STATION;
62c58fb4 536
e0d687bd
PR		 537 ath5k_hw_set_opmode(ah, ah->opmode);
538 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
539 ah->opmode, ath_opmode_to_string(ah->opmode));
62c58fb4 540
b1ae1edf 541 if (iter_data.need_set_hw_addr && iter_data.found_active)
e0d687bd 542 ath5k_hw_set_lladdr(ah, iter_data.active_mac);
b1ae1edf 543
e0d687bd
PR		 544 if (ath5k_hw_hasbssidmask(ah))
545 ath5k_hw_set_bssid_mask(ah, ah->bssidmask);
b1ae1edf 546
e4b0b32a
BG		 547 /* Set up RX Filter */
548 if (iter_data.n_stas > 1) {
549 /* If you have multiple STA interfaces connected to
550 * different APs, ARPs are not received (most of the time?)
6a2a0e73 551 * Enabling PROMISC appears to fix that problem.
e4b0b32a 552 */
e0d687bd 553 ah->filter_flags |= AR5K_RX_FILTER_PROM;
e4b0b32a 554 }
fa1c114f 555
e0d687bd
PR		 556 rfilt = ah->filter_flags;
557 ath5k_hw_set_rx_filter(ah, rfilt);
558 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
8a63facc 559}
fa1c114f 560
8a63facc 561static inline int
e0d687bd 562ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix)
8a63facc
BC		 563{
564 int rix;
fa1c114f 565
8a63facc
BC		 566 /* return base rate on errors */
567 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
568 "hw_rix out of bounds: %x\n", hw_rix))
569 return 0;
570
e0d687bd 571 rix = ah->rate_idx[ah->curchan->band][hw_rix];
8a63facc
BC		 572 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
573 rix = 0;
574
575 return rix;
576}
577
578/***************\
579* Buffers setup *
580\***************/
581
582static
e0d687bd 583struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr)
8a63facc 584{
e0d687bd 585 struct ath_common *common = ath5k_hw_common(ah);
8a63facc 586 struct sk_buff *skb;
fa1c114f
JS		 587
588 /*
8a63facc
BC		 589 * Allocate buffer with headroom_needed space for the
590 * fake physical layer header at the start.
fa1c114f 591 */
8a63facc
BC		 592 skb = ath_rxbuf_alloc(common,
593 common->rx_bufsize,
594 GFP_ATOMIC);
fa1c114f 595
8a63facc 596 if (!skb) {
e0d687bd 597 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n",
8a63facc
BC		 598 common->rx_bufsize);
599 return NULL;
fa1c114f
JS		 600 }
601
e0d687bd 602 *skb_addr = dma_map_single(ah->dev,
8a63facc 603 skb->data, common->rx_bufsize,
aeae4ac9
FF		 604 DMA_FROM_DEVICE);
605
e0d687bd
PR		 606 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) {
607 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__);
8a63facc
BC		 608 dev_kfree_skb(skb);
609 return NULL;
0e149cf5 610 }
8a63facc
BC		 611 return skb;
612}
0e149cf5 613
8a63facc 614static int
e0d687bd 615ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
8a63facc 616{
8a63facc
BC		 617 struct sk_buff *skb = bf->skb;
618 struct ath5k_desc *ds;
619 int ret;
fa1c114f 620
8a63facc 621 if (!skb) {
e0d687bd 622 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr);
8a63facc
BC		 623 if (!skb)
624 return -ENOMEM;
625 bf->skb = skb;
f769c36b
BC		 626 }
627
8a63facc
BC		 628 /*
629 * Setup descriptors. For receive we always terminate
630 * the descriptor list with a self-linked entry so we'll
631 * not get overrun under high load (as can happen with a
632 * 5212 when ANI processing enables PHY error frames).
633 *
634 * To ensure the last descriptor is self-linked we create
635 * each descriptor as self-linked and add it to the end. As
636 * each additional descriptor is added the previous self-linked
637 * entry is "fixed" naturally. This should be safe even
638 * if DMA is happening. When processing RX interrupts we
639 * never remove/process the last, self-linked, entry on the
640 * descriptor list. This ensures the hardware always has
641 * someplace to write a new frame.
642 */
643 ds = bf->desc;
644 ds->ds_link = bf->daddr; /* link to self */
645 ds->ds_data = bf->skbaddr;
646 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
fa1c114f 647 if (ret) {
e0d687bd 648 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__);
8a63facc 649 return ret;
fa1c114f
JS		 650 }
651
e0d687bd
PR		 652 if (ah->rxlink != NULL)
653 *ah->rxlink = bf->daddr;
654 ah->rxlink = &ds->ds_link;
fa1c114f 655 return 0;
fa1c114f
JS		 656}
657
8a63facc 658static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
fa1c114f 659{
8a63facc
BC		 660 struct ieee80211_hdr *hdr;
661 enum ath5k_pkt_type htype;
662 __le16 fc;
fa1c114f 663
8a63facc
BC		 664 hdr = (struct ieee80211_hdr *)skb->data;
665 fc = hdr->frame_control;
fa1c114f 666
8a63facc
BC		 667 if (ieee80211_is_beacon(fc))
668 htype = AR5K_PKT_TYPE_BEACON;
669 else if (ieee80211_is_probe_resp(fc))
670 htype = AR5K_PKT_TYPE_PROBE_RESP;
671 else if (ieee80211_is_atim(fc))
672 htype = AR5K_PKT_TYPE_ATIM;
673 else if (ieee80211_is_pspoll(fc))
674 htype = AR5K_PKT_TYPE_PSPOLL;
fa1c114f 675 else
8a63facc 676 htype = AR5K_PKT_TYPE_NORMAL;
fa1c114f 677
8a63facc 678 return htype;
42639fcd
BC		 679}
680
0967e01e
TH		 681static struct ieee80211_rate *
682ath5k_get_rate(const struct ieee80211_hw *hw,
683 const struct ieee80211_tx_info *info,
684 struct ath5k_buf *bf, int idx)
685{
686 /*
687 * convert a ieee80211_tx_rate RC-table entry to
688 * the respective ieee80211_rate struct
689 */
690 if (bf->rates[idx].idx < 0) {
691 return NULL;
692 }
693
694 return &hw->wiphy->bands[info->band]->bitrates[ bf->rates[idx].idx ];
695}
696
697static u16
698ath5k_get_rate_hw_value(const struct ieee80211_hw *hw,
699 const struct ieee80211_tx_info *info,
700 struct ath5k_buf *bf, int idx)
701{
702 struct ieee80211_rate *rate;
703 u16 hw_rate;
704 u8 rc_flags;
705
706 rate = ath5k_get_rate(hw, info, bf, idx);
707 if (!rate)
708 return 0;
709
710 rc_flags = bf->rates[idx].flags;
711 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
712 rate->hw_value_short : rate->hw_value;
713
714 return hw_rate;
715}
716
8a63facc 717static int
e0d687bd 718ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf,
0967e01e
TH		 719 struct ath5k_txq *txq, int padsize,
720 struct ieee80211_tx_control *control)
fa1c114f 721{
8a63facc
BC		 722 struct ath5k_desc *ds = bf->desc;
723 struct sk_buff *skb = bf->skb;
724 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
725 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
726 struct ieee80211_rate *rate;
727 unsigned int mrr_rate[3], mrr_tries[3];
728 int i, ret;
729 u16 hw_rate;
730 u16 cts_rate = 0;
731 u16 duration = 0;
732 u8 rc_flags;
fa1c114f 733
8a63facc 734 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
fa1c114f 735
8a63facc 736 /* XXX endianness */
e0d687bd 737 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
aeae4ac9 738 DMA_TO_DEVICE);
fa1c114f 739
b499abdc
JG		 740 if (dma_mapping_error(ah->dev, bf->skbaddr))
741 return -ENOSPC;
742
0967e01e
TH		 743 ieee80211_get_tx_rates(info->control.vif, (control) ? control->sta : NULL, skb, bf->rates,
744 ARRAY_SIZE(bf->rates));
745
746 rate = ath5k_get_rate(ah->hw, info, bf, 0);
747
29ad2fac
JL		 748 if (!rate) {
749 ret = -EINVAL;
750 goto err_unmap;
751 }
fa1c114f 752
8a63facc
BC		 753 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
754 flags |= AR5K_TXDESC_NOACK;
fa1c114f 755
8a63facc 756 rc_flags = info->control.rates[0].flags;
0967e01e
TH		 757
758 hw_rate = ath5k_get_rate_hw_value(ah->hw, info, bf, 0);
42639fcd 759
8a63facc
BC		 760 pktlen = skb->len;
761
762 /* FIXME: If we are in g mode and rate is a CCK rate
763 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
764 * from tx power (value is in dB units already) */
765 if (info->control.hw_key) {
766 keyidx = info->control.hw_key->hw_key_idx;
767 pktlen += info->control.hw_key->icv_len;
768 }
769 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
770 flags |= AR5K_TXDESC_RTSENA;
e0d687bd
PR		 771 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
772 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw,
b1ae1edf 773 info->control.vif, pktlen, info));
8a63facc
BC		 774 }
775 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
776 flags |= AR5K_TXDESC_CTSENA;
e0d687bd
PR		 777 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
778 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw,
b1ae1edf 779 info->control.vif, pktlen, info));
8a63facc 780 }
0967e01e 781
8a63facc
BC		 782 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
783 ieee80211_get_hdrlen_from_skb(skb), padsize,
784 get_hw_packet_type(skb),
987af54f 785 (ah->ah_txpower.txp_requested * 2),
8a63facc 786 hw_rate,
0967e01e 787 bf->rates[0].count, keyidx, ah->ah_tx_ant, flags,
8a63facc
BC		 788 cts_rate, duration);
789 if (ret)
790 goto err_unmap;
791
86f62d9b
NK		 792 /* Set up MRR descriptor */
793 if (ah->ah_capabilities.cap_has_mrr_support) {
794 memset(mrr_rate, 0, sizeof(mrr_rate));
795 memset(mrr_tries, 0, sizeof(mrr_tries));
0967e01e 796
86f62d9b 797 for (i = 0; i < 3; i++) {
0967e01e
TH		 798
799 rate = ath5k_get_rate(ah->hw, info, bf, i);
86f62d9b
NK		 800 if (!rate)
801 break;
fa1c114f 802
0967e01e
TH		 803 mrr_rate[i] = ath5k_get_rate_hw_value(ah->hw, info, bf, i);
804 mrr_tries[i] = bf->rates[i].count;
86f62d9b 805 }
fa1c114f 806
86f62d9b
NK		 807 ath5k_hw_setup_mrr_tx_desc(ah, ds,
808 mrr_rate[0], mrr_tries[0],
809 mrr_rate[1], mrr_tries[1],
810 mrr_rate[2], mrr_tries[2]);
811 }
fa1c114f 812
8a63facc
BC		 813 ds->ds_link = 0;
814 ds->ds_data = bf->skbaddr;
63266a65 815
8a63facc
BC		 816 spin_lock_bh(&txq->lock);
817 list_add_tail(&bf->list, &txq->q);
925e0b06 818 txq->txq_len++;
8a63facc
BC		 819 if (txq->link == NULL) /* is this first packet? */
820 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
821 else /* no, so only link it */
822 *txq->link = bf->daddr;
63266a65 823
8a63facc
BC		 824 txq->link = &ds->ds_link;
825 ath5k_hw_start_tx_dma(ah, txq->qnum);
826 mmiowb();
827 spin_unlock_bh(&txq->lock);
828
829 return 0;
830err_unmap:
e0d687bd 831 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
8a63facc 832 return ret;
63266a65
BR		 833}
834
8a63facc
BC		 835/*******************\
836* Descriptors setup *
837\*******************/
838
d8ee398d 839static int
e0d687bd 840ath5k_desc_alloc(struct ath5k_hw *ah)
fa1c114f 841{
8a63facc
BC		 842 struct ath5k_desc *ds;
843 struct ath5k_buf *bf;
844 dma_addr_t da;
845 unsigned int i;
846 int ret;
d8ee398d 847
8a63facc 848 /* allocate descriptors */
e0d687bd 849 ah->desc_len = sizeof(struct ath5k_desc) *
8a63facc 850 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
aeae4ac9 851
e0d687bd
PR		 852 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len,
853 &ah->desc_daddr, GFP_KERNEL);
854 if (ah->desc == NULL) {
855 ATH5K_ERR(ah, "can't allocate descriptors\n");
8a63facc
BC		 856 ret = -ENOMEM;
857 goto err;
858 }
e0d687bd
PR		 859 ds = ah->desc;
860 da = ah->desc_daddr;
861 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
862 ds, ah->desc_len, (unsigned long long)ah->desc_daddr);
fa1c114f 863
8a63facc
BC		 864 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
865 sizeof(struct ath5k_buf), GFP_KERNEL);
866 if (bf == NULL) {
e0d687bd 867 ATH5K_ERR(ah, "can't allocate bufptr\n");
8a63facc
BC		 868 ret = -ENOMEM;
869 goto err_free;
870 }
e0d687bd 871 ah->bufptr = bf;
fa1c114f 872
e0d687bd 873 INIT_LIST_HEAD(&ah->rxbuf);
8a63facc
BC		 874 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
875 bf->desc = ds;
876 bf->daddr = da;
e0d687bd 877 list_add_tail(&bf->list, &ah->rxbuf);
8a63facc 878 }
d8ee398d 879
e0d687bd
PR		 880 INIT_LIST_HEAD(&ah->txbuf);
881 ah->txbuf_len = ATH_TXBUF;
e4bbf2f5 882 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
8a63facc
BC		 883 bf->desc = ds;
884 bf->daddr = da;
e0d687bd 885 list_add_tail(&bf->list, &ah->txbuf);
fa1c114f
JS		 886 }
887
b1ae1edf 888 /* beacon buffers */
e0d687bd 889 INIT_LIST_HEAD(&ah->bcbuf);
b1ae1edf
BG		 890 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
891 bf->desc = ds;
892 bf->daddr = da;
e0d687bd 893 list_add_tail(&bf->list, &ah->bcbuf);
b1ae1edf 894 }
fa1c114f 895
8a63facc
BC		 896 return 0;
897err_free:
e0d687bd 898 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
8a63facc 899err:
e0d687bd 900 ah->desc = NULL;
8a63facc
BC		 901 return ret;
902}
fa1c114f 903
cd2c5486 904void
e0d687bd 905ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
cd2c5486
BR		 906{
907 BUG_ON(!bf);
908 if (!bf->skb)
909 return;
e0d687bd 910 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len,
cd2c5486 911 DMA_TO_DEVICE);
596ab5ec 912 ieee80211_free_txskb(ah->hw, bf->skb);
cd2c5486
BR		 913 bf->skb = NULL;
914 bf->skbaddr = 0;
915 bf->desc->ds_data = 0;
916}
917
918void
e0d687bd 919ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
cd2c5486 920{
cd2c5486
BR		 921 struct ath_common *common = ath5k_hw_common(ah);
922
923 BUG_ON(!bf);
924 if (!bf->skb)
925 return;
e0d687bd 926 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize,
cd2c5486
BR		 927 DMA_FROM_DEVICE);
928 dev_kfree_skb_any(bf->skb);
929 bf->skb = NULL;
930 bf->skbaddr = 0;
931 bf->desc->ds_data = 0;
932}
933
8a63facc 934static void
e0d687bd 935ath5k_desc_free(struct ath5k_hw *ah)
8a63facc
BC		 936{
937 struct ath5k_buf *bf;
d8ee398d 938
e0d687bd
PR		 939 list_for_each_entry(bf, &ah->txbuf, list)
940 ath5k_txbuf_free_skb(ah, bf);
941 list_for_each_entry(bf, &ah->rxbuf, list)
942 ath5k_rxbuf_free_skb(ah, bf);
943 list_for_each_entry(bf, &ah->bcbuf, list)
944 ath5k_txbuf_free_skb(ah, bf);
d8ee398d 945
8a63facc 946 /* Free memory associated with all descriptors */
e0d687bd
PR		 947 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
948 ah->desc = NULL;
949 ah->desc_daddr = 0;
d8ee398d 950
e0d687bd
PR		 951 kfree(ah->bufptr);
952 ah->bufptr = NULL;
fa1c114f
JS		 953}
954
8a63facc
BC		 955
956/**************\
957* Queues setup *
958\**************/
959
960static struct ath5k_txq *
e0d687bd 961ath5k_txq_setup(struct ath5k_hw *ah,
8a63facc 962 int qtype, int subtype)
fa1c114f 963{
8a63facc
BC		 964 struct ath5k_txq *txq;
965 struct ath5k_txq_info qi = {
966 .tqi_subtype = subtype,
de8af455
BR		 967 /* XXX: default values not correct for B and XR channels,
968 * but who cares? */
969 .tqi_aifs = AR5K_TUNE_AIFS,
970 .tqi_cw_min = AR5K_TUNE_CWMIN,
971 .tqi_cw_max = AR5K_TUNE_CWMAX
8a63facc
BC		 972 };
973 int qnum;
d8ee398d 974
e30eb4ab 975 /*
8a63facc
BC		 976 * Enable interrupts only for EOL and DESC conditions.
977 * We mark tx descriptors to receive a DESC interrupt
978 * when a tx queue gets deep; otherwise we wait for the
979 * EOL to reap descriptors. Note that this is done to
980 * reduce interrupt load and this only defers reaping
981 * descriptors, never transmitting frames. Aside from
982 * reducing interrupts this also permits more concurrency.
983 * The only potential downside is if the tx queue backs
984 * up in which case the top half of the kernel may backup
985 * due to a lack of tx descriptors.
e30eb4ab 986 */
8a63facc
BC		 987 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
988 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
989 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
990 if (qnum < 0) {
991 /*
992 * NB: don't print a message, this happens
993 * normally on parts with too few tx queues
994 */
995 return ERR_PTR(qnum);
996 }
e0d687bd 997 txq = &ah->txqs[qnum];
8a63facc
BC		 998 if (!txq->setup) {
999 txq->qnum = qnum;
1000 txq->link = NULL;
1001 INIT_LIST_HEAD(&txq->q);
1002 spin_lock_init(&txq->lock);
1003 txq->setup = true;
925e0b06 1004 txq->txq_len = 0;
81266baf 1005 txq->txq_max = ATH5K_TXQ_LEN_MAX;
4edd761f 1006 txq->txq_poll_mark = false;
923e5b3d 1007 txq->txq_stuck = 0;
8a63facc 1008 }
e0d687bd 1009 return &ah->txqs[qnum];
fa1c114f
JS		 1010}
1011
8a63facc
BC		 1012static int
1013ath5k_beaconq_setup(struct ath5k_hw *ah)
fa1c114f 1014{
8a63facc 1015 struct ath5k_txq_info qi = {
de8af455
BR		 1016 /* XXX: default values not correct for B and XR channels,
1017 * but who cares? */
1018 .tqi_aifs = AR5K_TUNE_AIFS,
1019 .tqi_cw_min = AR5K_TUNE_CWMIN,
1020 .tqi_cw_max = AR5K_TUNE_CWMAX,
8a63facc
BC		 1021 /* NB: for dynamic turbo, don't enable any other interrupts */
1022 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1023 };
d8ee398d 1024
8a63facc 1025 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
fa1c114f
JS		 1026}
1027
8a63facc 1028static int
e0d687bd 1029ath5k_beaconq_config(struct ath5k_hw *ah)
fa1c114f 1030{
8a63facc
BC		 1031 struct ath5k_txq_info qi;
1032 int ret;
fa1c114f 1033
e0d687bd 1034 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi);
8a63facc
BC		 1035 if (ret)
1036 goto err;
fa1c114f 1037
e0d687bd
PR		 1038 if (ah->opmode == NL80211_IFTYPE_AP ||
1039 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
8a63facc
BC		 1040 /*
1041 * Always burst out beacon and CAB traffic
1042 * (aifs = cwmin = cwmax = 0)
1043 */
1044 qi.tqi_aifs = 0;
1045 qi.tqi_cw_min = 0;
1046 qi.tqi_cw_max = 0;
e0d687bd 1047 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) {
8a63facc
BC		 1048 /*
1049 * Adhoc mode; backoff between 0 and (2 * cw_min).
1050 */
1051 qi.tqi_aifs = 0;
1052 qi.tqi_cw_min = 0;
de8af455 1053 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
8a63facc 1054 }
fa1c114f 1055
e0d687bd 1056 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
8a63facc
BC		 1057 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1058 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
fa1c114f 1059
e0d687bd 1060 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi);
8a63facc 1061 if (ret) {
e0d687bd 1062 ATH5K_ERR(ah, "%s: unable to update parameters for beacon "
8a63facc
BC		 1063 "hardware queue!\n", __func__);
1064 goto err;
1065 }
e0d687bd 1066 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */
8a63facc
BC		 1067 if (ret)
1068 goto err;
b7266047 1069
8a63facc
BC		 1070 /* reconfigure cabq with ready time to 80% of beacon_interval */
1071 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1072 if (ret)
1073 goto err;
b7266047 1074
e0d687bd 1075 qi.tqi_ready_time = (ah->bintval * 80) / 100;
8a63facc
BC		 1076 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1077 if (ret)
1078 goto err;
b7266047 1079
8a63facc
BC		 1080 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1081err:
1082 return ret;
d8ee398d
LR		 1083}
1084
80dac9ee
NK		 1085/**
1086 * ath5k_drain_tx_buffs - Empty tx buffers
1087 *
e0d687bd 1088 * @ah The &struct ath5k_hw
80dac9ee
NK		 1089 *
1090 * Empty tx buffers from all queues in preparation
1091 * of a reset or during shutdown.
1092 *
1093 * NB: this assumes output has been stopped and
1094 * we do not need to block ath5k_tx_tasklet
1095 */
8a63facc 1096static void
e0d687bd 1097ath5k_drain_tx_buffs(struct ath5k_hw *ah)
8a63facc 1098{
80dac9ee 1099 struct ath5k_txq *txq;
8a63facc 1100 struct ath5k_buf *bf, *bf0;
80dac9ee 1101 int i;
b6ea0356 1102
e0d687bd
PR		 1103 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
1104 if (ah->txqs[i].setup) {
1105 txq = &ah->txqs[i];
80dac9ee
NK		 1106 spin_lock_bh(&txq->lock);
1107 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
e0d687bd 1108 ath5k_debug_printtxbuf(ah, bf);
b6ea0356 1109
e0d687bd 1110 ath5k_txbuf_free_skb(ah, bf);
fa1c114f 1111
6617942e 1112 spin_lock(&ah->txbuflock);
e0d687bd
PR		 1113 list_move_tail(&bf->list, &ah->txbuf);
1114 ah->txbuf_len++;
80dac9ee 1115 txq->txq_len--;
6617942e 1116 spin_unlock(&ah->txbuflock);
8a63facc 1117 }
80dac9ee
NK		 1118 txq->link = NULL;
1119 txq->txq_poll_mark = false;
1120 spin_unlock_bh(&txq->lock);
1121 }
0452d4a5 1122 }
fa1c114f
JS		 1123}
1124
8a63facc 1125static void
e0d687bd 1126ath5k_txq_release(struct ath5k_hw *ah)
2ac2927a 1127{
e0d687bd 1128 struct ath5k_txq *txq = ah->txqs;
8a63facc 1129 unsigned int i;
2ac2927a 1130
e0d687bd 1131 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++)
8a63facc 1132 if (txq->setup) {
e0d687bd 1133 ath5k_hw_release_tx_queue(ah, txq->qnum);
8a63facc
BC		 1134 txq->setup = false;
1135 }
1136}
2ac2927a 1137
2ac2927a 1138
8a63facc
BC		 1139/*************\
1140* RX Handling *
1141\*************/
2ac2927a 1142
8a63facc
BC		 1143/*
1144 * Enable the receive h/w following a reset.
1145 */
fa1c114f 1146static int
e0d687bd 1147ath5k_rx_start(struct ath5k_hw *ah)
fa1c114f 1148{
8a63facc
BC		 1149 struct ath_common *common = ath5k_hw_common(ah);
1150 struct ath5k_buf *bf;
1151 int ret;
fa1c114f 1152
8a63facc 1153 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
fa1c114f 1154
e0d687bd 1155 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
8a63facc 1156 common->cachelsz, common->rx_bufsize);
2f7fe870 1157
e0d687bd
PR		 1158 spin_lock_bh(&ah->rxbuflock);
1159 ah->rxlink = NULL;
1160 list_for_each_entry(bf, &ah->rxbuf, list) {
1161 ret = ath5k_rxbuf_setup(ah, bf);
8a63facc 1162 if (ret != 0) {
e0d687bd 1163 spin_unlock_bh(&ah->rxbuflock);
8a63facc
BC		 1164 goto err;
1165 }
2f7fe870 1166 }
e0d687bd 1167 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
8a63facc 1168 ath5k_hw_set_rxdp(ah, bf->daddr);
e0d687bd 1169 spin_unlock_bh(&ah->rxbuflock);
2f7fe870 1170
8a63facc 1171 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
e0d687bd 1172 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */
8a63facc 1173 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
fa1c114f
JS		 1174
1175 return 0;
8a63facc 1176err:
fa1c114f
JS		 1177 return ret;
1178}
1179
8a63facc 1180/*
80dac9ee
NK		 1181 * Disable the receive logic on PCU (DRU)
1182 * In preparation for a shutdown.
1183 *
1184 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1185 * does.
8a63facc
BC		 1186 */
1187static void
e0d687bd 1188ath5k_rx_stop(struct ath5k_hw *ah)
fa1c114f 1189{
fa1c114f 1190
8a63facc 1191 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
80dac9ee 1192 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f 1193
e0d687bd 1194 ath5k_debug_printrxbuffs(ah);
8a63facc 1195}
fa1c114f 1196
8a63facc 1197static unsigned int
e0d687bd 1198ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb,
8a63facc
BC		 1199 struct ath5k_rx_status *rs)
1200{
8a63facc
BC		 1201 struct ath_common *common = ath5k_hw_common(ah);
1202 struct ieee80211_hdr *hdr = (void *)skb->data;
1203 unsigned int keyix, hlen;
fa1c114f 1204
8a63facc
BC		 1205 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1206 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1207 return RX_FLAG_DECRYPTED;
fa1c114f 1208
8a63facc
BC		 1209 /* Apparently when a default key is used to decrypt the packet
1210 the hw does not set the index used to decrypt. In such cases
1211 get the index from the packet. */
1212 hlen = ieee80211_hdrlen(hdr->frame_control);
1213 if (ieee80211_has_protected(hdr->frame_control) &&
1214 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1215 skb->len >= hlen + 4) {
1216 keyix = skb->data[hlen + 3] >> 6;
1217
1218 if (test_bit(keyix, common->keymap))
1219 return RX_FLAG_DECRYPTED;
1220 }
fa1c114f
JS		 1221
1222 return 0;
fa1c114f
JS		 1223}
1224
8a63facc 1225
fa1c114f 1226static void
e0d687bd 1227ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb,
8a63facc 1228 struct ieee80211_rx_status *rxs)
fa1c114f 1229{
8a63facc
BC		 1230 u64 tsf, bc_tstamp;
1231 u32 hw_tu;
1232 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
fa1c114f 1233
d44efe21 1234 if (le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS) {
8a63facc
BC		 1235 /*
1236 * Received an IBSS beacon with the same BSSID. Hardware *must*
1237 * have updated the local TSF. We have to work around various
1238 * hardware bugs, though...
1239 */
e0d687bd 1240 tsf = ath5k_hw_get_tsf64(ah);
8a63facc
BC		 1241 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1242 hw_tu = TSF_TO_TU(tsf);
fa1c114f 1243
e0d687bd 1244 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
8a63facc
BC		 1245 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1246 (unsigned long long)bc_tstamp,
1247 (unsigned long long)rxs->mactime,
1248 (unsigned long long)(rxs->mactime - bc_tstamp),
1249 (unsigned long long)tsf);
fa1c114f 1250
8a63facc
BC		 1251 /*
1252 * Sometimes the HW will give us a wrong tstamp in the rx
1253 * status, causing the timestamp extension to go wrong.
1254 * (This seems to happen especially with beacon frames bigger
1255 * than 78 byte (incl. FCS))
1256 * But we know that the receive timestamp must be later than the
1257 * timestamp of the beacon since HW must have synced to that.
1258 *
1259 * NOTE: here we assume mactime to be after the frame was
1260 * received, not like mac80211 which defines it at the start.
1261 */
1262 if (bc_tstamp > rxs->mactime) {
e0d687bd 1263 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
8a63facc
BC		 1264 "fixing mactime from %llx to %llx\n",
1265 (unsigned long long)rxs->mactime,
1266 (unsigned long long)tsf);
1267 rxs->mactime = tsf;
1268 }
fa1c114f 1269
8a63facc
BC		 1270 /*
1271 * Local TSF might have moved higher than our beacon timers,
1272 * in that case we have to update them to continue sending
1273 * beacons. This also takes care of synchronizing beacon sending
1274 * times with other stations.
1275 */
e0d687bd
PR		 1276 if (hw_tu >= ah->nexttbtt)
1277 ath5k_beacon_update_timers(ah, bc_tstamp);
7f896126
BR		 1278
1279 /* Check if the beacon timers are still correct, because a TSF
1280 * update might have created a window between them - for a
1281 * longer description see the comment of this function: */
e0d687bd
PR		 1282 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) {
1283 ath5k_beacon_update_timers(ah, bc_tstamp);
1284 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
7f896126
BR		 1285 "fixed beacon timers after beacon receive\n");
1286 }
8a63facc
BC		 1287 }
1288}
fa1c114f 1289
8a63facc
BC		 1290/*
1291 * Compute padding position. skb must contain an IEEE 802.11 frame
1292 */
1293static int ath5k_common_padpos(struct sk_buff *skb)
fa1c114f 1294{
e4bbf2f5 1295 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
8a63facc
BC		 1296 __le16 frame_control = hdr->frame_control;
1297 int padpos = 24;
fa1c114f 1298
d2c7f773 1299 if (ieee80211_has_a4(frame_control))
8a63facc 1300 padpos += ETH_ALEN;
d2c7f773
PR		 1301
1302 if (ieee80211_is_data_qos(frame_control))
8a63facc 1303 padpos += IEEE80211_QOS_CTL_LEN;
8a63facc
BC		 1304
1305 return padpos;
fa1c114f
JS		 1306}
1307
8a63facc
BC		 1308/*
1309 * This function expects an 802.11 frame and returns the number of
1310 * bytes added, or -1 if we don't have enough header room.
1311 */
1312static int ath5k_add_padding(struct sk_buff *skb)
fa1c114f 1313{
8a63facc
BC		 1314 int padpos = ath5k_common_padpos(skb);
1315 int padsize = padpos & 3;
fa1c114f 1316
e4bbf2f5 1317 if (padsize && skb->len > padpos) {
fa1c114f 1318
8a63facc
BC		 1319 if (skb_headroom(skb) < padsize)
1320 return -1;
fa1c114f 1321
8a63facc 1322 skb_push(skb, padsize);
e4bbf2f5 1323 memmove(skb->data, skb->data + padsize, padpos);
8a63facc
BC		 1324 return padsize;
1325 }
a951ae21 1326
8a63facc
BC		 1327 return 0;
1328}
fa1c114f 1329
8a63facc
BC		 1330/*
1331 * The MAC header is padded to have 32-bit boundary if the
1332 * packet payload is non-zero. The general calculation for
1333 * padsize would take into account odd header lengths:
1334 * padsize = 4 - (hdrlen & 3); however, since only
1335 * even-length headers are used, padding can only be 0 or 2
1336 * bytes and we can optimize this a bit. We must not try to
1337 * remove padding from short control frames that do not have a
1338 * payload.
1339 *
1340 * This function expects an 802.11 frame and returns the number of
1341 * bytes removed.
1342 */
1343static int ath5k_remove_padding(struct sk_buff *skb)
1344{
1345 int padpos = ath5k_common_padpos(skb);
1346 int padsize = padpos & 3;
6d91e1d8 1347
e4bbf2f5 1348 if (padsize && skb->len >= padpos + padsize) {
8a63facc
BC		 1349 memmove(skb->data + padsize, skb->data, padpos);
1350 skb_pull(skb, padsize);
1351 return padsize;
fa1c114f 1352 }
a951ae21 1353
8a63facc 1354 return 0;
fa1c114f
JS		 1355}
1356
1357static void
e0d687bd 1358ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb,
8a63facc 1359 struct ath5k_rx_status *rs)
fa1c114f 1360{
8a63facc 1361 struct ieee80211_rx_status *rxs;
d44efe21 1362 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1363
1364 ath5k_remove_padding(skb);
1365
1366 rxs = IEEE80211_SKB_RXCB(skb);
1367
1368 rxs->flag = 0;
1369 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1370 rxs->flag |= RX_FLAG_MMIC_ERROR;
41881354
MV		 1371 if (unlikely(rs->rs_status & AR5K_RXERR_CRC))
1372 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
1373
fa1c114f
JS		 1374
1375 /*
8a63facc
BC		 1376 * always extend the mac timestamp, since this information is
1377 * also needed for proper IBSS merging.
1378 *
1379 * XXX: it might be too late to do it here, since rs_tstamp is
1380 * 15bit only. that means TSF extension has to be done within
1381 * 32768usec (about 32ms). it might be necessary to move this to
1382 * the interrupt handler, like it is done in madwifi.
fa1c114f 1383 */
e0d687bd 1384 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp);
e576defd 1385 rxs->flag |= RX_FLAG_MACTIME_END;
fa1c114f 1386
e0d687bd
PR		 1387 rxs->freq = ah->curchan->center_freq;
1388 rxs->band = ah->curchan->band;
fa1c114f 1389
e0d687bd 1390 rxs->signal = ah->ah_noise_floor + rs->rs_rssi;
fa1c114f 1391
8a63facc 1392 rxs->antenna = rs->rs_antenna;
fa1c114f 1393
8a63facc 1394 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
e0d687bd 1395 ah->stats.antenna_rx[rs->rs_antenna]++;
8a63facc 1396 else
e0d687bd 1397 ah->stats.antenna_rx[0]++; /* invalid */
fa1c114f 1398
e0d687bd
PR		 1399 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate);
1400 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs);
312a6443
SW		 1401 switch (ah->ah_bwmode) {
1402 case AR5K_BWMODE_5MHZ:
1403 rxs->flag |= RX_FLAG_5MHZ;
1404 break;
1405 case AR5K_BWMODE_10MHZ:
1406 rxs->flag |= RX_FLAG_10MHZ;
1407 break;
1408 default:
1409 break;
1410 }
fa1c114f 1411
e6938ea4 1412 if (rs->rs_rate ==
e0d687bd 1413 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
8a63facc 1414 rxs->flag |= RX_FLAG_SHORTPRE;
fa1c114f 1415
e0d687bd 1416 trace_ath5k_rx(ah, skb);
fa1c114f 1417
d44efe21
OR		 1418 if (ath_is_mybeacon(common, (struct ieee80211_hdr *)skb->data)) {
1419 ewma_add(&ah->ah_beacon_rssi_avg, rs->rs_rssi);
fa1c114f 1420
d44efe21
OR		 1421 /* check beacons in IBSS mode */
1422 if (ah->opmode == NL80211_IFTYPE_ADHOC)
1423 ath5k_check_ibss_tsf(ah, skb, rxs);
1424 }
fa1c114f 1425
e0d687bd 1426 ieee80211_rx(ah->hw, skb);
8a63facc 1427}
fa1c114f 1428
8a63facc
BC		 1429/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1430 *
1431 * Check if we want to further process this frame or not. Also update
1432 * statistics. Return true if we want this frame, false if not.
fa1c114f 1433 */
8a63facc 1434static bool
e0d687bd 1435ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs)
fa1c114f 1436{
e0d687bd
PR		 1437 ah->stats.rx_all_count++;
1438 ah->stats.rx_bytes_count += rs->rs_datalen;
fa1c114f 1439
8a63facc 1440 if (unlikely(rs->rs_status)) {
41881354
MV		 1441 unsigned int filters;
1442
8a63facc 1443 if (rs->rs_status & AR5K_RXERR_CRC)
e0d687bd 1444 ah->stats.rxerr_crc++;
8a63facc 1445 if (rs->rs_status & AR5K_RXERR_FIFO)
e0d687bd 1446 ah->stats.rxerr_fifo++;
8a63facc 1447 if (rs->rs_status & AR5K_RXERR_PHY) {
e0d687bd 1448 ah->stats.rxerr_phy++;
8a63facc 1449 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
e0d687bd 1450 ah->stats.rxerr_phy_code[rs->rs_phyerr]++;
b76ff0d2
MV		 1451
1452 /*
1453 * Treat packets that underwent a CCK or OFDM reset as having a bad CRC.
1454 * These restarts happen when the radio resynchronizes to a stronger frame
1455 * while receiving a weaker frame. Here we receive the prefix of the weak
1456 * frame. Since these are incomplete packets, mark their CRC as invalid.
1457 */
1458 if (rs->rs_phyerr == AR5K_RX_PHY_ERROR_OFDM_RESTART ||
1459 rs->rs_phyerr == AR5K_RX_PHY_ERROR_CCK_RESTART) {
1460 rs->rs_status |= AR5K_RXERR_CRC;
1461 rs->rs_status &= ~AR5K_RXERR_PHY;
1462 } else {
1463 return false;
1464 }
8a63facc
BC		 1465 }
1466 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1467 /*
1468 * Decrypt error. If the error occurred
1469 * because there was no hardware key, then
1470 * let the frame through so the upper layers
1471 * can process it. This is necessary for 5210
1472 * parts which have no way to setup a ``clear''
1473 * key cache entry.
1474 *
1475 * XXX do key cache faulting
1476 */
e0d687bd 1477 ah->stats.rxerr_decrypt++;
8a63facc
BC		 1478 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1479 !(rs->rs_status & AR5K_RXERR_CRC))
1480 return true;
1481 }
1482 if (rs->rs_status & AR5K_RXERR_MIC) {
e0d687bd 1483 ah->stats.rxerr_mic++;
8a63facc 1484 return true;
fa1c114f 1485 }
fa1c114f 1486
41881354
MV		 1487 /*
1488 * Reject any frames with non-crypto errors, and take into account the
1489 * current FIF_* filters.
1490 */
1491 filters = AR5K_RXERR_DECRYPT;
1492 if (ah->fif_filter_flags & FIF_FCSFAIL)
1493 filters |= AR5K_RXERR_CRC;
1494
1495 if (rs->rs_status & ~filters)
8a63facc
BC		 1496 return false;
1497 }
fa1c114f 1498
8a63facc 1499 if (unlikely(rs->rs_more)) {
e0d687bd 1500 ah->stats.rxerr_jumbo++;
8a63facc
BC		 1501 return false;
1502 }
1503 return true;
fa1c114f
JS		 1504}
1505
c266c71a 1506static void
e0d687bd 1507ath5k_set_current_imask(struct ath5k_hw *ah)
c266c71a 1508{
4fc5401c 1509 enum ath5k_int imask;
c266c71a
FF		 1510 unsigned long flags;
1511
e0d687bd
PR		 1512 spin_lock_irqsave(&ah->irqlock, flags);
1513 imask = ah->imask;
1514 if (ah->rx_pending)
c266c71a 1515 imask &= ~AR5K_INT_RX_ALL;
e0d687bd 1516 if (ah->tx_pending)
c266c71a 1517 imask &= ~AR5K_INT_TX_ALL;
e0d687bd
PR		 1518 ath5k_hw_set_imr(ah, imask);
1519 spin_unlock_irqrestore(&ah->irqlock, flags);
c266c71a
FF		 1520}
1521
fa1c114f 1522static void
8a63facc 1523ath5k_tasklet_rx(unsigned long data)
fa1c114f 1524{
8a63facc
BC		 1525 struct ath5k_rx_status rs = {};
1526 struct sk_buff *skb, *next_skb;
1527 dma_addr_t next_skb_addr;
e0d687bd 1528 struct ath5k_hw *ah = (void *)data;
dc1e001b 1529 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1530 struct ath5k_buf *bf;
1531 struct ath5k_desc *ds;
1532 int ret;
fa1c114f 1533
e0d687bd
PR		 1534 spin_lock(&ah->rxbuflock);
1535 if (list_empty(&ah->rxbuf)) {
1536 ATH5K_WARN(ah, "empty rx buf pool\n");
8a63facc
BC		 1537 goto unlock;
1538 }
1539 do {
e0d687bd 1540 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
8a63facc
BC		 1541 BUG_ON(bf->skb == NULL);
1542 skb = bf->skb;
1543 ds = bf->desc;
fa1c114f 1544
8a63facc 1545 /* bail if HW is still using self-linked descriptor */
e0d687bd 1546 if (ath5k_hw_get_rxdp(ah) == bf->daddr)
8a63facc 1547 break;
fa1c114f 1548
e0d687bd 1549 ret = ah->ah_proc_rx_desc(ah, ds, &rs);
8a63facc
BC		 1550 if (unlikely(ret == -EINPROGRESS))
1551 break;
1552 else if (unlikely(ret)) {
e0d687bd
PR		 1553 ATH5K_ERR(ah, "error in processing rx descriptor\n");
1554 ah->stats.rxerr_proc++;
8a63facc
BC		 1555 break;
1556 }
fa1c114f 1557
e0d687bd
PR		 1558 if (ath5k_receive_frame_ok(ah, &rs)) {
1559 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr);
fa1c114f 1560
8a63facc
BC		 1561 /*
1562 * If we can't replace bf->skb with a new skb under
1563 * memory pressure, just skip this packet
1564 */
1565 if (!next_skb)
1566 goto next;
036cd1ec 1567
e0d687bd 1568 dma_unmap_single(ah->dev, bf->skbaddr,
8a63facc 1569 common->rx_bufsize,
aeae4ac9 1570 DMA_FROM_DEVICE);
036cd1ec 1571
8a63facc 1572 skb_put(skb, rs.rs_datalen);
6ba81c2c 1573
e0d687bd 1574 ath5k_receive_frame(ah, skb, &rs);
6ba81c2c 1575
8a63facc
BC		 1576 bf->skb = next_skb;
1577 bf->skbaddr = next_skb_addr;
036cd1ec 1578 }
8a63facc 1579next:
e0d687bd
PR		 1580 list_move_tail(&bf->list, &ah->rxbuf);
1581 } while (ath5k_rxbuf_setup(ah, bf) == 0);
8a63facc 1582unlock:
e0d687bd
PR		 1583 spin_unlock(&ah->rxbuflock);
1584 ah->rx_pending = false;
1585 ath5k_set_current_imask(ah);
036cd1ec
BR		 1586}
1587
b4ea449d 1588
8a63facc
BC		 1589/*************\
1590* TX Handling *
1591\*************/
b4ea449d 1592
7bb45683 1593void
cd2c5486 1594ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
0967e01e 1595 struct ath5k_txq *txq, struct ieee80211_tx_control *control)
8a63facc 1596{
e0d687bd 1597 struct ath5k_hw *ah = hw->priv;
8a63facc
BC		 1598 struct ath5k_buf *bf;
1599 unsigned long flags;
1600 int padsize;
b4ea449d 1601
e0d687bd 1602 trace_ath5k_tx(ah, skb, txq);
b4ea449d 1603
8a63facc
BC		 1604 /*
1605 * The hardware expects the header padded to 4 byte boundaries.
1606 * If this is not the case, we add the padding after the header.
1607 */
1608 padsize = ath5k_add_padding(skb);
1609 if (padsize < 0) {
e0d687bd 1610 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough"
8a63facc
BC		 1611 " headroom to pad");
1612 goto drop_packet;
1613 }
8127fbdc 1614
4e868796
FF		 1615 if (txq->txq_len >= txq->txq_max &&
1616 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX)
925e0b06
BR		 1617 ieee80211_stop_queue(hw, txq->qnum);
1618
e0d687bd
PR		 1619 spin_lock_irqsave(&ah->txbuflock, flags);
1620 if (list_empty(&ah->txbuf)) {
1621 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n");
1622 spin_unlock_irqrestore(&ah->txbuflock, flags);
651d9375 1623 ieee80211_stop_queues(hw);
8a63facc 1624 goto drop_packet;
8127fbdc 1625 }
e0d687bd 1626 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list);
8a63facc 1627 list_del(&bf->list);
e0d687bd
PR		 1628 ah->txbuf_len--;
1629 if (list_empty(&ah->txbuf))
8a63facc 1630 ieee80211_stop_queues(hw);
e0d687bd 1631 spin_unlock_irqrestore(&ah->txbuflock, flags);
8a63facc
BC		 1632
1633 bf->skb = skb;
1634
0967e01e 1635 if (ath5k_txbuf_setup(ah, bf, txq, padsize, control)) {
8a63facc 1636 bf->skb = NULL;
e0d687bd
PR		 1637 spin_lock_irqsave(&ah->txbuflock, flags);
1638 list_add_tail(&bf->list, &ah->txbuf);
1639 ah->txbuf_len++;
1640 spin_unlock_irqrestore(&ah->txbuflock, flags);
8a63facc 1641 goto drop_packet;
8127fbdc 1642 }
7bb45683 1643 return;
8127fbdc 1644
8a63facc 1645drop_packet:
596ab5ec 1646 ieee80211_free_txskb(hw, skb);
8127fbdc
BP		 1647}
1648
1440401e 1649static void
e0d687bd 1650ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb,
0967e01e
TH		 1651 struct ath5k_txq *txq, struct ath5k_tx_status *ts,
1652 struct ath5k_buf *bf)
1440401e
BR		 1653{
1654 struct ieee80211_tx_info *info;
ed895085 1655 u8 tries[3];
1440401e 1656 int i;
0967e01e 1657 int size = 0;
1440401e 1658
e0d687bd
PR		 1659 ah->stats.tx_all_count++;
1660 ah->stats.tx_bytes_count += skb->len;
1440401e
BR		 1661 info = IEEE80211_SKB_CB(skb);
1662
7ede612f
FF		 1663 size = min_t(int, sizeof(info->status.rates), sizeof(bf->rates));
1664 memcpy(info->status.rates, bf->rates, size);
1665
ed895085
FF		 1666 tries[0] = info->status.rates[0].count;
1667 tries[1] = info->status.rates[1].count;
1668 tries[2] = info->status.rates[2].count;
1669
1440401e 1670 ieee80211_tx_info_clear_status(info);
ed895085
FF		 1671
1672 for (i = 0; i < ts->ts_final_idx; i++) {
1440401e
BR		 1673 struct ieee80211_tx_rate *r =
1674 &info->status.rates[i];
1675
ed895085 1676 r->count = tries[i];
1440401e
BR		 1677 }
1678
ed895085 1679 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry;
6d7b97b2 1680 info->status.rates[ts->ts_final_idx + 1].idx = -1;
1440401e
BR		 1681
1682 if (unlikely(ts->ts_status)) {
e0d687bd 1683 ah->stats.ack_fail++;
1440401e
BR		 1684 if (ts->ts_status & AR5K_TXERR_FILT) {
1685 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
e0d687bd 1686 ah->stats.txerr_filt++;
1440401e
BR		 1687 }
1688 if (ts->ts_status & AR5K_TXERR_XRETRY)
e0d687bd 1689 ah->stats.txerr_retry++;
1440401e 1690 if (ts->ts_status & AR5K_TXERR_FIFO)
e0d687bd 1691 ah->stats.txerr_fifo++;
1440401e
BR		 1692 } else {
1693 info->flags |= IEEE80211_TX_STAT_ACK;
1694 info->status.ack_signal = ts->ts_rssi;
6d7b97b2
FF		 1695
1696 /* count the successful attempt as well */
1697 info->status.rates[ts->ts_final_idx].count++;
1440401e
BR		 1698 }
1699
1700 /*
1701 * Remove MAC header padding before giving the frame
1702 * back to mac80211.
1703 */
1704 ath5k_remove_padding(skb);
1705
1706 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
e0d687bd 1707 ah->stats.antenna_tx[ts->ts_antenna]++;
1440401e 1708 else
e0d687bd 1709 ah->stats.antenna_tx[0]++; /* invalid */
1440401e 1710
e0d687bd
PR		 1711 trace_ath5k_tx_complete(ah, skb, txq, ts);
1712 ieee80211_tx_status(ah->hw, skb);
1440401e 1713}
8a63facc
BC		 1714
1715static void
e0d687bd 1716ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq)
8127fbdc 1717{
8a63facc
BC		 1718 struct ath5k_tx_status ts = {};
1719 struct ath5k_buf *bf, *bf0;
1720 struct ath5k_desc *ds;
1721 struct sk_buff *skb;
1440401e 1722 int ret;
8127fbdc 1723
8a63facc
BC		 1724 spin_lock(&txq->lock);
1725 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
23413296
BR		 1726
1727 txq->txq_poll_mark = false;
1728
1729 /* skb might already have been processed last time. */
1730 if (bf->skb != NULL) {
1731 ds = bf->desc;
1732
e0d687bd 1733 ret = ah->ah_proc_tx_desc(ah, ds, &ts);
23413296
BR		 1734 if (unlikely(ret == -EINPROGRESS))
1735 break;
1736 else if (unlikely(ret)) {
e0d687bd 1737 ATH5K_ERR(ah,
23413296
BR		 1738 "error %d while processing "
1739 "queue %u\n", ret, txq->qnum);
1740 break;
1741 }
1742
1743 skb = bf->skb;
1744 bf->skb = NULL;
aeae4ac9 1745
e0d687bd 1746 dma_unmap_single(ah->dev, bf->skbaddr, skb->len,
aeae4ac9 1747 DMA_TO_DEVICE);
0967e01e 1748 ath5k_tx_frame_completed(ah, skb, txq, &ts, bf);
23413296 1749 }
8127fbdc 1750
8a63facc
BC		 1751 /*
1752 * It's possible that the hardware can say the buffer is
1753 * completed when it hasn't yet loaded the ds_link from
23413296
BR		 1754 * host memory and moved on.
1755 * Always keep the last descriptor to avoid HW races...
8a63facc 1756 */
e0d687bd
PR		 1757 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) {
1758 spin_lock(&ah->txbuflock);
1759 list_move_tail(&bf->list, &ah->txbuf);
1760 ah->txbuf_len++;
23413296 1761 txq->txq_len--;
e0d687bd 1762 spin_unlock(&ah->txbuflock);
8a63facc 1763 }
fa1c114f 1764 }
fa1c114f 1765 spin_unlock(&txq->lock);
4198a8d0 1766 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
e0d687bd 1767 ieee80211_wake_queue(ah->hw, txq->qnum);
fa1c114f
JS		 1768}
1769
1770static void
1771ath5k_tasklet_tx(unsigned long data)
1772{
8784d2ee 1773 int i;
e0d687bd 1774 struct ath5k_hw *ah = (void *)data;
fa1c114f 1775
e4bbf2f5 1776 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
7ff7c82e 1777 if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i)))
e0d687bd 1778 ath5k_tx_processq(ah, &ah->txqs[i]);
c266c71a 1779
e0d687bd
PR		 1780 ah->tx_pending = false;
1781 ath5k_set_current_imask(ah);
fa1c114f
JS		 1782}
1783
1784
fa1c114f
JS		 1785/*****************\
1786* Beacon handling *
1787\*****************/
1788
1789/*
1790 * Setup the beacon frame for transmit.
1791 */
1792static int
e0d687bd 1793ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
fa1c114f
JS		 1794{
1795 struct sk_buff *skb = bf->skb;
a888d52d 1796 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1797 struct ath5k_desc *ds;
2bed03eb
NK		 1798 int ret = 0;
1799 u8 antenna;
fa1c114f 1800 u32 flags;
8127fbdc 1801 const int padsize = 0;
fa1c114f 1802
e0d687bd 1803 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
aeae4ac9 1804 DMA_TO_DEVICE);
e0d687bd 1805 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
fa1c114f
JS		 1806 "skbaddr %llx\n", skb, skb->data, skb->len,
1807 (unsigned long long)bf->skbaddr);
aeae4ac9 1808
e0d687bd
PR		 1809 if (dma_mapping_error(ah->dev, bf->skbaddr)) {
1810 ATH5K_ERR(ah, "beacon DMA mapping failed\n");
bdc71bc5
BC		 1811 dev_kfree_skb_any(skb);
1812 bf->skb = NULL;
fa1c114f
JS		 1813 return -EIO;
1814 }
1815
1816 ds = bf->desc;
2bed03eb 1817 antenna = ah->ah_tx_ant;
fa1c114f
JS		 1818
1819 flags = AR5K_TXDESC_NOACK;
e0d687bd 1820 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1821 ds->ds_link = bf->daddr; /* self-linked */
1822 flags |= AR5K_TXDESC_VEOL;
2bed03eb 1823 } else
fa1c114f 1824 ds->ds_link = 0;
2bed03eb
NK		 1825
1826 /*
1827 * If we use multiple antennas on AP and use
1828 * the Sectored AP scenario, switch antenna every
1829 * 4 beacons to make sure everybody hears our AP.
1830 * When a client tries to associate, hw will keep
1831 * track of the tx antenna to be used for this client
6a2a0e73 1832 * automatically, based on ACKed packets.
2bed03eb
NK		 1833 *
1834 * Note: AP still listens and transmits RTS on the
1835 * default antenna which is supposed to be an omni.
1836 *
1837 * Note2: On sectored scenarios it's possible to have
a180a130
BC		 1838 * multiple antennas (1 omni -- the default -- and 14
1839 * sectors), so if we choose to actually support this
1840 * mode, we need to allow the user to set how many antennas
1841 * we have and tweak the code below to send beacons
1842 * on all of them.
2bed03eb
NK		 1843 */
1844 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
e0d687bd 1845 antenna = ah->bsent & 4 ? 2 : 1;
2bed03eb 1846
fa1c114f 1847
8f655dde
NK		 1848 /* FIXME: If we are in g mode and rate is a CCK rate
1849 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1850 * from tx power (value is in dB units already) */
fa1c114f 1851 ds->ds_data = bf->skbaddr;
281c56dd 1852 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 1853 ieee80211_get_hdrlen_from_skb(skb), padsize,
987af54f
NK		 1854 AR5K_PKT_TYPE_BEACON,
1855 (ah->ah_txpower.txp_requested * 2),
e0d687bd 1856 ieee80211_get_tx_rate(ah->hw, info)->hw_value,
2e92e6f2 1857 1, AR5K_TXKEYIX_INVALID,
400ec45a 1858 antenna, flags, 0, 0);
fa1c114f
JS		 1859 if (ret)
1860 goto err_unmap;
1861
1862 return 0;
1863err_unmap:
e0d687bd 1864 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
fa1c114f
JS		 1865 return ret;
1866}
1867
8a63facc
BC		 1868/*
1869 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1870 * this is called only once at config_bss time, for AP we do it every
1871 * SWBA interrupt so that the TIM will reflect buffered frames.
1872 *
1873 * Called with the beacon lock.
1874 */
cd2c5486 1875int
8a63facc
BC		 1876ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1877{
1878 int ret;
e0d687bd 1879 struct ath5k_hw *ah = hw->priv;
9c371f99 1880 struct ath5k_vif *avf;
8a63facc
BC		 1881 struct sk_buff *skb;
1882
1883 if (WARN_ON(!vif)) {
1884 ret = -EINVAL;
1885 goto out;
1886 }
1887
1888 skb = ieee80211_beacon_get(hw, vif);
1889
1890 if (!skb) {
1891 ret = -ENOMEM;
1892 goto out;
1893 }
1894
9c371f99 1895 avf = (void *)vif->drv_priv;
e0d687bd 1896 ath5k_txbuf_free_skb(ah, avf->bbuf);
b1ae1edf 1897 avf->bbuf->skb = skb;
e0d687bd 1898 ret = ath5k_beacon_setup(ah, avf->bbuf);
8a63facc
BC		 1899out:
1900 return ret;
1901}
1902
fa1c114f
JS		 1903/*
1904 * Transmit a beacon frame at SWBA. Dynamic updates to the
1905 * frame contents are done as needed and the slot time is
1906 * also adjusted based on current state.
1907 *
5faaff74
BC		 1908 * This is called from software irq context (beacontq tasklets)
1909 * or user context from ath5k_beacon_config.
fa1c114f
JS		 1910 */
1911static void
e0d687bd 1912ath5k_beacon_send(struct ath5k_hw *ah)
fa1c114f 1913{
b1ae1edf
BG		 1914 struct ieee80211_vif *vif;
1915 struct ath5k_vif *avf;
1916 struct ath5k_buf *bf;
cec8db23 1917 struct sk_buff *skb;
bdc71bc5 1918 int err;
fa1c114f 1919
e0d687bd 1920 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1921
fa1c114f
JS		 1922 /*
1923 * Check if the previous beacon has gone out. If
a180a130 1924 * not, don't don't try to post another: skip this
fa1c114f
JS		 1925 * period and wait for the next. Missed beacons
1926 * indicate a problem and should not occur. If we
1927 * miss too many consecutive beacons reset the device.
1928 */
e0d687bd
PR		 1929 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) {
1930 ah->bmisscount++;
1931 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1932 "missed %u consecutive beacons\n", ah->bmisscount);
1933 if (ah->bmisscount > 10) { /* NB: 10 is a guess */
1934 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
fa1c114f 1935 "stuck beacon time (%u missed)\n",
e0d687bd
PR		 1936 ah->bmisscount);
1937 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
8d67a031 1938 "stuck beacon, resetting\n");
e0d687bd 1939 ieee80211_queue_work(ah->hw, &ah->reset_work);
fa1c114f
JS		 1940 }
1941 return;
1942 }
e0d687bd
PR		 1943 if (unlikely(ah->bmisscount != 0)) {
1944 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
fa1c114f 1945 "resume beacon xmit after %u misses\n",
e0d687bd
PR		 1946 ah->bmisscount);
1947 ah->bmisscount = 0;
fa1c114f
JS		 1948 }
1949
da473b61
CYY		 1950 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs +
1951 ah->num_mesh_vifs > 1) ||
e0d687bd 1952 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
b1ae1edf
BG		 1953 u64 tsf = ath5k_hw_get_tsf64(ah);
1954 u32 tsftu = TSF_TO_TU(tsf);
e0d687bd
PR		 1955 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval;
1956 vif = ah->bslot[(slot + 1) % ATH_BCBUF];
1957 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
b1ae1edf 1958 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
e0d687bd 1959 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif);
b1ae1edf 1960 } else /* only one interface */
e0d687bd 1961 vif = ah->bslot[0];
b1ae1edf
BG		 1962
1963 if (!vif)
1964 return;
1965
1966 avf = (void *)vif->drv_priv;
1967 bf = avf->bbuf;
b1ae1edf 1968
fa1c114f
JS		 1969 /*
1970 * Stop any current dma and put the new frame on the queue.
1971 * This should never fail since we check above that no frames
1972 * are still pending on the queue.
1973 */
e0d687bd
PR		 1974 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) {
1975 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq);
fa1c114f
JS		 1976 /* NB: hw still stops DMA, so proceed */
1977 }
fa1c114f 1978
d82b577b 1979 /* refresh the beacon for AP or MESH mode */
e0d687bd 1980 if (ah->opmode == NL80211_IFTYPE_AP ||
bdc71bc5
BC		 1981 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1982 err = ath5k_beacon_update(ah->hw, vif);
1983 if (err)
1984 return;
1985 }
1986
1987 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION ||
1988 ah->opmode == NL80211_IFTYPE_MONITOR)) {
1989 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb);
1990 return;
1991 }
1071db86 1992
e0d687bd 1993 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]);
0e472252 1994
e0d687bd
PR		 1995 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr);
1996 ath5k_hw_start_tx_dma(ah, ah->bhalq);
1997 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1998 ah->bhalq, (unsigned long long)bf->daddr, bf->desc);
fa1c114f 1999
e0d687bd 2000 skb = ieee80211_get_buffered_bc(ah->hw, vif);
cec8db23 2001 while (skb) {
0967e01e 2002 ath5k_tx_queue(ah->hw, skb, ah->cabq, NULL);
4e868796 2003
e0d687bd 2004 if (ah->cabq->txq_len >= ah->cabq->txq_max)
4e868796
FF		 2005 break;
2006
e0d687bd 2007 skb = ieee80211_get_buffered_bc(ah->hw, vif);
cec8db23
BC		 2008 }
2009
e0d687bd 2010 ah->bsent++;
fa1c114f
JS		 2011}
2012
9804b98d
BR		 2013/**
2014 * ath5k_beacon_update_timers - update beacon timers
2015 *
e0d687bd 2016 * @ah: struct ath5k_hw pointer we are operating on
9804b98d
BR		 2017 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2018 * beacon timer update based on the current HW TSF.
2019 *
2020 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2021 * of a received beacon or the current local hardware TSF and write it to the
2022 * beacon timer registers.
2023 *
2024 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2025 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2026 * when we otherwise know we have to update the timers, but we keep it in this
2027 * function to have it all together in one place.
2028 */
cd2c5486 2029void
e0d687bd 2030ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
fa1c114f 2031{
9804b98d
BR		 2032 u32 nexttbtt, intval, hw_tu, bc_tu;
2033 u64 hw_tsf;
fa1c114f 2034
e0d687bd 2035 intval = ah->bintval & AR5K_BEACON_PERIOD;
da473b61
CYY		 2036 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs
2037 + ah->num_mesh_vifs > 1) {
b1ae1edf
BG		 2038 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
2039 if (intval < 15)
e0d687bd 2040 ATH5K_WARN(ah, "intval %u is too low, min 15\n",
b1ae1edf
BG		 2041 intval);
2042 }
fa1c114f
JS		 2043 if (WARN_ON(!intval))
2044 return;
2045
9804b98d
BR		 2046 /* beacon TSF converted to TU */
2047 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2048
9804b98d
BR		 2049 /* current TSF converted to TU */
2050 hw_tsf = ath5k_hw_get_tsf64(ah);
2051 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2052
633d006e 2053#define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
11f21df3 2054 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
25985edc 2055 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
11f21df3
BR		 2056 * configuration we need to make sure it is bigger than that. */
2057
9804b98d
BR		 2058 if (bc_tsf == -1) {
2059 /*
2060 * no beacons received, called internally.
2061 * just need to refresh timers based on HW TSF.
2062 */
2063 nexttbtt = roundup(hw_tu + FUDGE, intval);
2064 } else if (bc_tsf == 0) {
2065 /*
2066 * no beacon received, probably called by ath5k_reset_tsf().
2067 * reset TSF to start with 0.
2068 */
2069 nexttbtt = intval;
2070 intval |= AR5K_BEACON_RESET_TSF;
2071 } else if (bc_tsf > hw_tsf) {
2072 /*
25985edc 2073 * beacon received, SW merge happened but HW TSF not yet updated.
9804b98d
BR		 2074 * not possible to reconfigure timers yet, but next time we
2075 * receive a beacon with the same BSSID, the hardware will
2076 * automatically update the TSF and then we need to reconfigure
2077 * the timers.
2078 */
e0d687bd 2079 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
9804b98d
BR		 2080 "need to wait for HW TSF sync\n");
2081 return;
2082 } else {
2083 /*
2084 * most important case for beacon synchronization between STA.
2085 *
2086 * beacon received and HW TSF has been already updated by HW.
2087 * update next TBTT based on the TSF of the beacon, but make
2088 * sure it is ahead of our local TSF timer.
2089 */
2090 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2091 }
2092#undef FUDGE
fa1c114f 2093
e0d687bd 2094 ah->nexttbtt = nexttbtt;
036cd1ec 2095
fa1c114f 2096 intval |= AR5K_BEACON_ENA;
c47faa36 2097 ath5k_hw_init_beacon_timers(ah, nexttbtt, intval);
9804b98d
BR		 2098
2099 /*
2100 * debugging output last in order to preserve the time critical aspect
2101 * of this function
2102 */
2103 if (bc_tsf == -1)
e0d687bd 2104 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
9804b98d
BR		 2105 "reconfigured timers based on HW TSF\n");
2106 else if (bc_tsf == 0)
e0d687bd 2107 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
9804b98d
BR		 2108 "reset HW TSF and timers\n");
2109 else
e0d687bd 2110 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
9804b98d
BR		 2111 "updated timers based on beacon TSF\n");
2112
e0d687bd 2113 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2114 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2115 (unsigned long long) bc_tsf,
2116 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
e0d687bd 2117 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
9804b98d
BR		 2118 intval & AR5K_BEACON_PERIOD,
2119 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2120 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2121}
2122
036cd1ec
BR		 2123/**
2124 * ath5k_beacon_config - Configure the beacon queues and interrupts
2125 *
e0d687bd 2126 * @ah: struct ath5k_hw pointer we are operating on
fa1c114f 2127 *
036cd1ec 2128 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2129 * interrupts to detect TSF updates only.
fa1c114f 2130 */
cd2c5486 2131void
e0d687bd 2132ath5k_beacon_config(struct ath5k_hw *ah)
fa1c114f 2133{
7dd6753f 2134 spin_lock_bh(&ah->block);
e0d687bd
PR		 2135 ah->bmisscount = 0;
2136 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2137
e0d687bd 2138 if (ah->enable_beacon) {
fa1c114f 2139 /*
036cd1ec
BR		 2140 * In IBSS mode we use a self-linked tx descriptor and let the
2141 * hardware send the beacons automatically. We have to load it
fa1c114f 2142 * only once here.
036cd1ec 2143 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2144 * timers in order to detect automatic TSF updates.
fa1c114f 2145 */
e0d687bd 2146 ath5k_beaconq_config(ah);
fa1c114f 2147
e0d687bd 2148 ah->imask |= AR5K_INT_SWBA;
036cd1ec 2149
e0d687bd 2150 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2151 if (ath5k_hw_hasveol(ah))
e0d687bd 2152 ath5k_beacon_send(ah);
da966bca 2153 } else
e0d687bd 2154 ath5k_beacon_update_timers(ah, -1);
21800491 2155 } else {
e0d687bd 2156 ath5k_hw_stop_beacon_queue(ah, ah->bhalq);
fa1c114f 2157 }
fa1c114f 2158
e0d687bd 2159 ath5k_hw_set_imr(ah, ah->imask);
21800491 2160 mmiowb();
7dd6753f 2161 spin_unlock_bh(&ah->block);
fa1c114f
JS		 2162}
2163
428cbd4f
NK		 2164static void ath5k_tasklet_beacon(unsigned long data)
2165{
e0d687bd 2166 struct ath5k_hw *ah = (struct ath5k_hw *) data;
428cbd4f
NK		 2167
2168 /*
2169 * Software beacon alert--time to send a beacon.
2170 *
2171 * In IBSS mode we use this interrupt just to
2172 * keep track of the next TBTT (target beacon
6a2a0e73 2173 * transmission time) in order to detect whether
428cbd4f
NK		 2174 * automatic TSF updates happened.
2175 */
e0d687bd 2176 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
6a2a0e73 2177 /* XXX: only if VEOL supported */
e0d687bd
PR		 2178 u64 tsf = ath5k_hw_get_tsf64(ah);
2179 ah->nexttbtt += ah->bintval;
2180 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
428cbd4f
NK		 2181 "SWBA nexttbtt: %x hw_tu: %x "
2182 "TSF: %llx\n",
e0d687bd 2183 ah->nexttbtt,
428cbd4f
NK		 2184 TSF_TO_TU(tsf),
2185 (unsigned long long) tsf);
2186 } else {
e0d687bd
PR		 2187 spin_lock(&ah->block);
2188 ath5k_beacon_send(ah);
2189 spin_unlock(&ah->block);
428cbd4f
NK		 2190 }
2191}
2192
fa1c114f
JS		 2193
2194/********************\
2195* Interrupt handling *
2196\********************/
2197
6a8a3f6b
BR		 2198static void
2199ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2200{
2111ac0d 2201 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
ce169aca
NK		 2202 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2203 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2204
2205 /* Run ANI only when calibration is not active */
2206
2111ac0d
BR		 2207 ah->ah_cal_next_ani = jiffies +
2208 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
e0d687bd 2209 tasklet_schedule(&ah->ani_tasklet);
2111ac0d 2210
ce169aca
NK		 2211 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) &&
2212 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2213 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2214
2215 /* Run calibration only when another calibration
2216 * is not running.
2217 *
2218 * Note: This is for both full/short calibration,
2219 * if it's time for a full one, ath5k_calibrate_work will deal
2220 * with it. */
2221
2222 ah->ah_cal_next_short = jiffies +
2223 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2224 ieee80211_queue_work(ah->hw, &ah->calib_work);
6a8a3f6b
BR		 2225 }
2226 /* we could use SWI to generate enough interrupts to meet our
2227 * calibration interval requirements, if necessary:
2228 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2229}
2230
c266c71a 2231static void
e0d687bd 2232ath5k_schedule_rx(struct ath5k_hw *ah)
c266c71a 2233{
e0d687bd
PR		 2234 ah->rx_pending = true;
2235 tasklet_schedule(&ah->rxtq);
c266c71a
FF		 2236}
2237
2238static void
e0d687bd 2239ath5k_schedule_tx(struct ath5k_hw *ah)
c266c71a 2240{
e0d687bd
PR		 2241 ah->tx_pending = true;
2242 tasklet_schedule(&ah->txtq);
c266c71a
FF		 2243}
2244
f5cbc8ba 2245static irqreturn_t
fa1c114f
JS		 2246ath5k_intr(int irq, void *dev_id)
2247{
e0d687bd 2248 struct ath5k_hw *ah = dev_id;
fa1c114f
JS		 2249 enum ath5k_int status;
2250 unsigned int counter = 1000;
2251
34ce644a
NK		 2252
2253 /*
2254 * If hw is not ready (or detached) and we get an
2255 * interrupt, or if we have no interrupts pending
2256 * (that means it's not for us) skip it.
2257 *
2258 * NOTE: Group 0/1 PCI interface registers are not
2259 * supported on WiSOCs, so we can't check for pending
2260 * interrupts (ISR belongs to another register group
2261 * so we are ok).
2262 */
e0d687bd 2263 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
34ce644a
NK		 2264 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2265 !ath5k_hw_is_intr_pending(ah))))
fa1c114f
JS		 2266 return IRQ_NONE;
2267
34ce644a 2268 /** Main loop **/
fa1c114f 2269 do {
34ce644a
NK		 2270 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2271
e0d687bd
PR		 2272 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2273 status, ah->imask);
34ce644a
NK		 2274
2275 /*
2276 * Fatal hw error -> Log and reset
2277 *
2278 * Fatal errors are unrecoverable so we have to
2279 * reset the card. These errors include bus and
2280 * dma errors.
2281 */
fa1c114f 2282 if (unlikely(status & AR5K_INT_FATAL)) {
34ce644a 2283
e0d687bd 2284 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
8d67a031 2285 "fatal int, resetting\n");
e0d687bd 2286 ieee80211_queue_work(ah->hw, &ah->reset_work);
34ce644a
NK		 2287
2288 /*
2289 * RX Overrun -> Count and reset if needed
2290 *
2291 * Receive buffers are full. Either the bus is busy or
2292 * the CPU is not fast enough to process all received
2293 * frames.
2294 */
fa1c114f 2295 } else if (unlikely(status & AR5K_INT_RXORN)) {
34ce644a 2296
87d77c4e 2297 /*
87d77c4e
BR		 2298 * Older chipsets need a reset to come out of this
2299 * condition, but we treat it as RX for newer chips.
34ce644a 2300 * We don't know exactly which versions need a reset
87d77c4e
BR		 2301 * this guess is copied from the HAL.
2302 */
e0d687bd 2303 ah->stats.rxorn_intr++;
34ce644a 2304
8d67a031 2305 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
e0d687bd 2306 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
8d67a031 2307 "rx overrun, resetting\n");
e0d687bd 2308 ieee80211_queue_work(ah->hw, &ah->reset_work);
d2c7f773 2309 } else
e0d687bd 2310 ath5k_schedule_rx(ah);
34ce644a 2311
fa1c114f 2312 } else {
34ce644a
NK		 2313
2314 /* Software Beacon Alert -> Schedule beacon tasklet */
d2c7f773 2315 if (status & AR5K_INT_SWBA)
e0d687bd 2316 tasklet_hi_schedule(&ah->beacontq);
d2c7f773 2317
34ce644a
NK		 2318 /*
2319 * No more RX descriptors -> Just count
2320 *
2321 * NB: the hardware should re-read the link when
2322 * RXE bit is written, but it doesn't work at
2323 * least on older hardware revs.
2324 */
2325 if (status & AR5K_INT_RXEOL)
e0d687bd 2326 ah->stats.rxeol_intr++;
34ce644a
NK		 2327
2328
2329 /* TX Underrun -> Bump tx trigger level */
2330 if (status & AR5K_INT_TXURN)
fa1c114f 2331 ath5k_hw_update_tx_triglevel(ah, true);
34ce644a
NK		 2332
2333 /* RX -> Schedule rx tasklet */
4c674c60 2334 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
e0d687bd 2335 ath5k_schedule_rx(ah);
34ce644a
NK		 2336
2337 /* TX -> Schedule tx tasklet */
2338 if (status & (AR5K_INT_TXOK
2339 | AR5K_INT_TXDESC
2340 | AR5K_INT_TXERR
2341 | AR5K_INT_TXEOL))
e0d687bd 2342 ath5k_schedule_tx(ah);
34ce644a
NK		 2343
2344 /* Missed beacon -> TODO
2345 if (status & AR5K_INT_BMISS)
2346 */
2347
2348 /* MIB event -> Update counters and notify ANI */
fa1c114f 2349 if (status & AR5K_INT_MIB) {
e0d687bd 2350 ah->stats.mib_intr++;
495391d7 2351 ath5k_hw_update_mib_counters(ah);
2111ac0d 2352 ath5k_ani_mib_intr(ah);
fa1c114f 2353 }
34ce644a
NK		 2354
2355 /* GPIO -> Notify RFKill layer */
e6a3b616 2356 if (status & AR5K_INT_GPIO)
e0d687bd 2357 tasklet_schedule(&ah->rf_kill.toggleq);
a6ae0716 2358
fa1c114f 2359 }
4cebb34c
FF		 2360
2361 if (ath5k_get_bus_type(ah) == ATH_AHB)
2362 break;
2363
2516baa6 2364 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f 2365
34ce644a
NK		 2366 /*
2367 * Until we handle rx/tx interrupts mask them on IMR
2368 *
2369 * NOTE: ah->(rx/tx)_pending are set when scheduling the tasklets
2370 * and unset after we 've handled the interrupts.
2371 */
e0d687bd
PR		 2372 if (ah->rx_pending || ah->tx_pending)
2373 ath5k_set_current_imask(ah);
c266c71a 2374
fa1c114f 2375 if (unlikely(!counter))
e0d687bd 2376 ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
fa1c114f 2377
34ce644a 2378 /* Fire up calibration poll */
6a8a3f6b 2379 ath5k_intr_calibration_poll(ah);
6e220662 2380
fa1c114f
JS		 2381 return IRQ_HANDLED;
2382}
2383
fa1c114f
JS		 2384/*
2385 * Periodically recalibrate the PHY to account
2386 * for temperature/environment changes.
2387 */
2388static void
ce169aca 2389ath5k_calibrate_work(struct work_struct *work)
fa1c114f 2390{
ce169aca
NK		 2391 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2392 calib_work);
2393
2394 /* Should we run a full calibration ? */
2395 if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2396
2397 ah->ah_cal_next_full = jiffies +
2398 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2399 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2400
2401 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
2402 "running full calibration\n");
2403
2404 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2405 /*
2406 * Rfgain is out of bounds, reset the chip
2407 * to load new gain values.
2408 */
2409 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2410 "got new rfgain, resetting\n");
2411 ieee80211_queue_work(ah->hw, &ah->reset_work);
2412 }
ce169aca
NK		 2413 } else
2414 ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT;
fa1c114f 2415
6e220662 2416
e0d687bd
PR		 2417 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2418 ieee80211_frequency_to_channel(ah->curchan->center_freq),
2419 ah->curchan->hw_value);
fa1c114f 2420
e0d687bd
PR		 2421 if (ath5k_hw_phy_calibrate(ah, ah->curchan))
2422 ATH5K_ERR(ah, "calibration of channel %u failed\n",
400ec45a 2423 ieee80211_frequency_to_channel(
e0d687bd 2424 ah->curchan->center_freq));
fa1c114f 2425
ce169aca 2426 /* Clear calibration flags */
62e2c102 2427 if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL)
ce169aca 2428 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
62e2c102 2429 else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)
ce169aca 2430 ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT;
fa1c114f
JS		 2431}
2432
2433
2111ac0d
BR		 2434static void
2435ath5k_tasklet_ani(unsigned long data)
2436{
e0d687bd 2437 struct ath5k_hw *ah = (void *)data;
2111ac0d
BR		 2438
2439 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2440 ath5k_ani_calibration(ah);
2441 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2442}
2443
2444
4edd761f
BR		 2445static void
2446ath5k_tx_complete_poll_work(struct work_struct *work)
2447{
e0d687bd 2448 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
4edd761f
BR		 2449 tx_complete_work.work);
2450 struct ath5k_txq *txq;
2451 int i;
2452 bool needreset = false;
2453
db178340
SG		 2454 if (!test_bit(ATH_STAT_STARTED, ah->status))
2455 return;
2456
e0d687bd 2457 mutex_lock(&ah->lock);
599b13ad 2458
e0d687bd
PR		 2459 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
2460 if (ah->txqs[i].setup) {
2461 txq = &ah->txqs[i];
4edd761f 2462 spin_lock_bh(&txq->lock);
23413296 2463 if (txq->txq_len > 1) {
4edd761f 2464 if (txq->txq_poll_mark) {
e0d687bd 2465 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT,
4edd761f
BR		 2466 "TX queue stuck %d\n",
2467 txq->qnum);
2468 needreset = true;
923e5b3d 2469 txq->txq_stuck++;
4edd761f
BR		 2470 spin_unlock_bh(&txq->lock);
2471 break;
2472 } else {
2473 txq->txq_poll_mark = true;
2474 }
2475 }
2476 spin_unlock_bh(&txq->lock);
2477 }
2478 }
2479
2480 if (needreset) {
e0d687bd 2481 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
4edd761f 2482 "TX queues stuck, resetting\n");
e0d687bd 2483 ath5k_reset(ah, NULL, true);
4edd761f
BR		 2484 }
2485
e0d687bd 2486 mutex_unlock(&ah->lock);
599b13ad 2487
e0d687bd 2488 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
4edd761f
BR		 2489 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2490}
2491
2492
8a63facc
BC		 2493/*************************\
2494* Initialization routines *
2495\*************************/
fa1c114f 2496
9b4760e3
FF		 2497static const struct ieee80211_iface_limit if_limits[] = {
2498 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) },
2499 { .max = 4, .types =
2500#ifdef CONFIG_MAC80211_MESH
2501 BIT(NL80211_IFTYPE_MESH_POINT) |
2502#endif
2503 BIT(NL80211_IFTYPE_AP) },
2504};
2505
2506static const struct ieee80211_iface_combination if_comb = {
2507 .limits = if_limits,
2508 .n_limits = ARRAY_SIZE(if_limits),
2509 .max_interfaces = 2048,
2510 .num_different_channels = 1,
2511};
2512
e829cf96 2513int
bb1f3ad9 2514ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
132b1c3e 2515{
e0d687bd 2516 struct ieee80211_hw *hw = ah->hw;
132b1c3e
FF		 2517 struct ath_common *common;
2518 int ret;
2519 int csz;
2520
2521 /* Initialize driver private data */
e0d687bd 2522 SET_IEEE80211_DEV(hw, ah->dev);
132b1c3e 2523 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
b9e61f11
NK		 2524 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2525 IEEE80211_HW_SIGNAL_DBM |
90e6274d 2526 IEEE80211_HW_MFP_CAPABLE |
0967e01e
TH		 2527 IEEE80211_HW_REPORTS_TX_ACK_STATUS |
2528 IEEE80211_HW_SUPPORTS_RC_TABLE;
132b1c3e
FF		 2529
2530 hw->wiphy->interface_modes =
2531 BIT(NL80211_IFTYPE_AP) |
2532 BIT(NL80211_IFTYPE_STATION) |
2533 BIT(NL80211_IFTYPE_ADHOC) |
2534 BIT(NL80211_IFTYPE_MESH_POINT);
2535
9b4760e3
FF		 2536 hw->wiphy->iface_combinations = &if_comb;
2537 hw->wiphy->n_iface_combinations = 1;
2538
f9972577
AQ		 2539 /* SW support for IBSS_RSN is provided by mac80211 */
2540 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
2541
4d70f2fb
SW		 2542 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
2543
3de135db
BR		 2544 /* both antennas can be configured as RX or TX */
2545 hw->wiphy->available_antennas_tx = 0x3;
2546 hw->wiphy->available_antennas_rx = 0x3;
2547
132b1c3e 2548 hw->extra_tx_headroom = 2;
132b1c3e
FF		 2549
2550 /*
2551 * Mark the device as detached to avoid processing
2552 * interrupts until setup is complete.
2553 */
e0d687bd 2554 __set_bit(ATH_STAT_INVALID, ah->status);
132b1c3e 2555
e0d687bd
PR		 2556 ah->opmode = NL80211_IFTYPE_STATION;
2557 ah->bintval = 1000;
2558 mutex_init(&ah->lock);
2559 spin_lock_init(&ah->rxbuflock);
2560 spin_lock_init(&ah->txbuflock);
2561 spin_lock_init(&ah->block);
2562 spin_lock_init(&ah->irqlock);
132b1c3e
FF		 2563
2564 /* Setup interrupt handler */
e0d687bd 2565 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah);
132b1c3e 2566 if (ret) {
e0d687bd 2567 ATH5K_ERR(ah, "request_irq failed\n");
132b1c3e
FF		 2568 goto err;
2569 }
2570
e0d687bd 2571 common = ath5k_hw_common(ah);
132b1c3e
FF		 2572 common->ops = &ath5k_common_ops;
2573 common->bus_ops = bus_ops;
e0d687bd 2574 common->ah = ah;
132b1c3e 2575 common->hw = hw;
e0d687bd 2576 common->priv = ah;
26d16d23 2577 common->clockrate = 40;
132b1c3e
FF		 2578
2579 /*
2580 * Cache line size is used to size and align various
2581 * structures used to communicate with the hardware.
2582 */
2583 ath5k_read_cachesize(common, &csz);
2584 common->cachelsz = csz << 2; /* convert to bytes */
2585
2586 spin_lock_init(&common->cc_lock);
2587
2588 /* Initialize device */
e0d687bd 2589 ret = ath5k_hw_init(ah);
132b1c3e 2590 if (ret)
e0d687bd 2591 goto err_irq;
132b1c3e 2592
86f62d9b
NK		 2593 /* Set up multi-rate retry capabilities */
2594 if (ah->ah_capabilities.cap_has_mrr_support) {
132b1c3e 2595 hw->max_rates = 4;
76a9f6fd
BR		 2596 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2597 AR5K_INIT_RETRY_LONG);
132b1c3e
FF		 2598 }
2599
2600 hw->vif_data_size = sizeof(struct ath5k_vif);
2601
2602 /* Finish private driver data initialization */
2603 ret = ath5k_init(hw);
2604 if (ret)
2605 goto err_ah;
2606
e0d687bd
PR		 2607 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2608 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev),
2609 ah->ah_mac_srev,
2610 ah->ah_phy_revision);
132b1c3e 2611
e0d687bd 2612 if (!ah->ah_single_chip) {
132b1c3e 2613 /* Single chip radio (!RF5111) */
e0d687bd
PR		 2614 if (ah->ah_radio_5ghz_revision &&
2615 !ah->ah_radio_2ghz_revision) {
132b1c3e
FF		 2616 /* No 5GHz support -> report 2GHz radio */
2617 if (!test_bit(AR5K_MODE_11A,
e0d687bd
PR		 2618 ah->ah_capabilities.cap_mode)) {
2619 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
132b1c3e 2620 ath5k_chip_name(AR5K_VERSION_RAD,
e0d687bd
PR		 2621 ah->ah_radio_5ghz_revision),
2622 ah->ah_radio_5ghz_revision);
132b1c3e 2623 /* No 2GHz support (5110 and some
6a2a0e73 2624 * 5GHz only cards) -> report 5GHz radio */
132b1c3e 2625 } else if (!test_bit(AR5K_MODE_11B,
e0d687bd
PR		 2626 ah->ah_capabilities.cap_mode)) {
2627 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
132b1c3e 2628 ath5k_chip_name(AR5K_VERSION_RAD,
e0d687bd
PR		 2629 ah->ah_radio_5ghz_revision),
2630 ah->ah_radio_5ghz_revision);
132b1c3e
FF		 2631 /* Multiband radio */
2632 } else {
e0d687bd 2633 ATH5K_INFO(ah, "RF%s multiband radio found"
132b1c3e
FF		 2634 " (0x%x)\n",
2635 ath5k_chip_name(AR5K_VERSION_RAD,
e0d687bd
PR		 2636 ah->ah_radio_5ghz_revision),
2637 ah->ah_radio_5ghz_revision);
132b1c3e
FF		 2638 }
2639 }
2640 /* Multi chip radio (RF5111 - RF2111) ->
2641 * report both 2GHz/5GHz radios */
e0d687bd
PR		 2642 else if (ah->ah_radio_5ghz_revision &&
2643 ah->ah_radio_2ghz_revision) {
2644 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
132b1c3e 2645 ath5k_chip_name(AR5K_VERSION_RAD,
e0d687bd
PR		 2646 ah->ah_radio_5ghz_revision),
2647 ah->ah_radio_5ghz_revision);
2648 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
132b1c3e 2649 ath5k_chip_name(AR5K_VERSION_RAD,
e0d687bd
PR		 2650 ah->ah_radio_2ghz_revision),
2651 ah->ah_radio_2ghz_revision);
132b1c3e
FF		 2652 }
2653 }
2654
e0d687bd 2655 ath5k_debug_init_device(ah);
132b1c3e
FF		 2656
2657 /* ready to process interrupts */
e0d687bd 2658 __clear_bit(ATH_STAT_INVALID, ah->status);
132b1c3e
FF		 2659
2660 return 0;
2661err_ah:
e0d687bd 2662 ath5k_hw_deinit(ah);
132b1c3e 2663err_irq:
e0d687bd 2664 free_irq(ah->irq, ah);
132b1c3e
FF		 2665err:
2666 return ret;
2667}
2668
fa1c114f 2669static int
e0d687bd 2670ath5k_stop_locked(struct ath5k_hw *ah)
cec8db23 2671{
cec8db23 2672
e0d687bd
PR		 2673 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n",
2674 test_bit(ATH_STAT_INVALID, ah->status));
8a63facc
BC		 2675
2676 /*
2677 * Shutdown the hardware and driver:
2678 * stop output from above
2679 * disable interrupts
2680 * turn off timers
2681 * turn off the radio
2682 * clear transmit machinery
2683 * clear receive machinery
2684 * drain and release tx queues
2685 * reclaim beacon resources
2686 * power down hardware
2687 *
2688 * Note that some of this work is not possible if the
2689 * hardware is gone (invalid).
2690 */
e0d687bd 2691 ieee80211_stop_queues(ah->hw);
8a63facc 2692
e0d687bd
PR		 2693 if (!test_bit(ATH_STAT_INVALID, ah->status)) {
2694 ath5k_led_off(ah);
8a63facc 2695 ath5k_hw_set_imr(ah, 0);
e0d687bd
PR		 2696 synchronize_irq(ah->irq);
2697 ath5k_rx_stop(ah);
80dac9ee 2698 ath5k_hw_dma_stop(ah);
e0d687bd 2699 ath5k_drain_tx_buffs(ah);
8a63facc
BC		 2700 ath5k_hw_phy_disable(ah);
2701 }
2702
2703 return 0;
cec8db23
BC		 2704}
2705
fabba048 2706int ath5k_start(struct ieee80211_hw *hw)
fa1c114f 2707{
fabba048 2708 struct ath5k_hw *ah = hw->priv;
8a63facc
BC		 2709 struct ath_common *common = ath5k_hw_common(ah);
2710 int ret, i;
fa1c114f 2711
e0d687bd 2712 mutex_lock(&ah->lock);
8a63facc 2713
e0d687bd 2714 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode);
fa1c114f 2715
fa1c114f 2716 /*
8a63facc
BC		 2717 * Stop anything previously setup. This is safe
2718 * no matter this is the first time through or not.
fa1c114f 2719 */
e0d687bd 2720 ath5k_stop_locked(ah);
fa1c114f 2721
8a63facc
BC		 2722 /*
2723 * The basic interface to setting the hardware in a good
2724 * state is ``reset''. On return the hardware is known to
2725 * be powered up and with interrupts disabled. This must
2726 * be followed by initialization of the appropriate bits
2727 * and then setup of the interrupt mask.
2728 */
675a0b04 2729 ah->curchan = ah->hw->conf.chandef.chan;
34ce644a
NK		 2730 ah->imask = AR5K_INT_RXOK
2731 | AR5K_INT_RXERR
2732 | AR5K_INT_RXEOL
2733 | AR5K_INT_RXORN
2734 | AR5K_INT_TXDESC
2735 | AR5K_INT_TXEOL
2736 | AR5K_INT_FATAL
2737 | AR5K_INT_GLOBAL
2738 | AR5K_INT_MIB;
fa1c114f 2739
e0d687bd 2740 ret = ath5k_reset(ah, NULL, false);
8a63facc
BC		 2741 if (ret)
2742 goto done;
fa1c114f 2743
84e1e737
NK		 2744 if (!ath5k_modparam_no_hw_rfkill_switch)
2745 ath5k_rfkill_hw_start(ah);
8a63facc
BC		 2746
2747 /*
2748 * Reset the key cache since some parts do not reset the
2749 * contents on initial power up or resume from suspend.
2750 */
2751 for (i = 0; i < common->keymax; i++)
2752 ath_hw_keyreset(common, (u16) i);
2753
61cde037
NK		 2754 /* Use higher rates for acks instead of base
2755 * rate */
2756 ah->ah_ack_bitrate_high = true;
b1ae1edf 2757
e0d687bd
PR		 2758 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++)
2759 ah->bslot[i] = NULL;
b1ae1edf 2760
8a63facc
BC		 2761 ret = 0;
2762done:
2763 mmiowb();
e0d687bd 2764 mutex_unlock(&ah->lock);
4edd761f 2765
db178340 2766 set_bit(ATH_STAT_STARTED, ah->status);
e0d687bd 2767 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
4edd761f
BR		 2768 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2769
8a63facc
BC		 2770 return ret;
2771}
2772
e0d687bd 2773static void ath5k_stop_tasklets(struct ath5k_hw *ah)
8a63facc 2774{
e0d687bd
PR		 2775 ah->rx_pending = false;
2776 ah->tx_pending = false;
2777 tasklet_kill(&ah->rxtq);
2778 tasklet_kill(&ah->txtq);
e0d687bd
PR		 2779 tasklet_kill(&ah->beacontq);
2780 tasklet_kill(&ah->ani_tasklet);
8a63facc
BC		 2781}
2782
2783/*
2784 * Stop the device, grabbing the top-level lock to protect
2785 * against concurrent entry through ath5k_init (which can happen
2786 * if another thread does a system call and the thread doing the
2787 * stop is preempted).
2788 */
fabba048 2789void ath5k_stop(struct ieee80211_hw *hw)
8a63facc 2790{
fabba048 2791 struct ath5k_hw *ah = hw->priv;
8a63facc
BC		 2792 int ret;
2793
e0d687bd
PR		 2794 mutex_lock(&ah->lock);
2795 ret = ath5k_stop_locked(ah);
2796 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) {
8a63facc
BC		 2797 /*
2798 * Don't set the card in full sleep mode!
2799 *
2800 * a) When the device is in this state it must be carefully
2801 * woken up or references to registers in the PCI clock
2802 * domain may freeze the bus (and system). This varies
2803 * by chip and is mostly an issue with newer parts
2804 * (madwifi sources mentioned srev >= 0x78) that go to
2805 * sleep more quickly.
2806 *
2807 * b) On older chips full sleep results a weird behaviour
2808 * during wakeup. I tested various cards with srev < 0x78
2809 * and they don't wake up after module reload, a second
2810 * module reload is needed to bring the card up again.
2811 *
2812 * Until we figure out what's going on don't enable
2813 * full chip reset on any chip (this is what Legacy HAL
2814 * and Sam's HAL do anyway). Instead Perform a full reset
2815 * on the device (same as initial state after attach) and
2816 * leave it idle (keep MAC/BB on warm reset) */
e0d687bd 2817 ret = ath5k_hw_on_hold(ah);
8a63facc 2818
e0d687bd 2819 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
8a63facc 2820 "putting device to sleep\n");
fa1c114f
JS		 2821 }
2822
8a63facc 2823 mmiowb();
e0d687bd 2824 mutex_unlock(&ah->lock);
8a63facc 2825
e0d687bd 2826 ath5k_stop_tasklets(ah);
4edd761f 2827
db178340 2828 clear_bit(ATH_STAT_STARTED, ah->status);
e0d687bd 2829 cancel_delayed_work_sync(&ah->tx_complete_work);
8a63facc 2830
84e1e737
NK		 2831 if (!ath5k_modparam_no_hw_rfkill_switch)
2832 ath5k_rfkill_hw_stop(ah);
fa1c114f
JS		 2833}
2834
209d889b
BC		 2835/*
2836 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2837 * and change to the given channel.
5faaff74 2838 *
e0d687bd 2839 * This should be called with ah->lock.
209d889b 2840 */
fa1c114f 2841static int
e0d687bd 2842ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
8aec7af9 2843 bool skip_pcu)
fa1c114f 2844{
f15a4bb2 2845 struct ath_common *common = ath5k_hw_common(ah);
344b54b9 2846 int ret, ani_mode;
a99168ee 2847 bool fast;
fa1c114f 2848
e0d687bd 2849 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2850
450464de 2851 ath5k_hw_set_imr(ah, 0);
e0d687bd
PR		 2852 synchronize_irq(ah->irq);
2853 ath5k_stop_tasklets(ah);
450464de 2854
25985edc 2855 /* Save ani mode and disable ANI during
344b54b9
NK		 2856 * reset. If we don't we might get false
2857 * PHY error interrupts. */
e0d687bd 2858 ani_mode = ah->ani_state.ani_mode;
344b54b9
NK		 2859 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2860
19252ecb
NK		 2861 /* We are going to empty hw queues
2862 * so we should also free any remaining
2863 * tx buffers */
e0d687bd 2864 ath5k_drain_tx_buffs(ah);
930a7622 2865 if (chan)
e0d687bd 2866 ah->curchan = chan;
a99168ee
NK		 2867
2868 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
2869
e0d687bd 2870 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu);
d7dc1003 2871 if (ret) {
e0d687bd 2872 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret);
fa1c114f
JS		 2873 goto err;
2874 }
d7dc1003 2875
e0d687bd 2876 ret = ath5k_rx_start(ah);
d7dc1003 2877 if (ret) {
e0d687bd 2878 ATH5K_ERR(ah, "can't start recv logic\n");
fa1c114f
JS		 2879 goto err;
2880 }
d7dc1003 2881
344b54b9 2882 ath5k_ani_init(ah, ani_mode);
2111ac0d 2883
ce169aca
NK		 2884 /*
2885 * Set calibration intervals
2886 *
2887 * Note: We don't need to run calibration imediately
2888 * since some initial calibration is done on reset
2889 * even for fast channel switching. Also on scanning
2890 * this will get set again and again and it won't get
2891 * executed unless we connect somewhere and spend some
2892 * time on the channel (that's what calibration needs
2893 * anyway to be accurate).
2894 */
2895 ah->ah_cal_next_full = jiffies +
2896 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2897 ah->ah_cal_next_ani = jiffies +
2898 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2899 ah->ah_cal_next_short = jiffies +
2900 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2901
5dcc03fe 2902 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
afe86286 2903
f15a4bb2 2904 /* clear survey data and cycle counters */
e0d687bd 2905 memset(&ah->survey, 0, sizeof(ah->survey));
bb007554 2906 spin_lock_bh(&common->cc_lock);
f15a4bb2
BR		 2907 ath_hw_cycle_counters_update(common);
2908 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2909 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
bb007554 2910 spin_unlock_bh(&common->cc_lock);
f15a4bb2 2911
fa1c114f 2912 /*
d7dc1003
JS		 2913 * Change channels and update the h/w rate map if we're switching;
2914 * e.g. 11a to 11b/g.
2915 *
2916 * We may be doing a reset in response to an ioctl that changes the
2917 * channel so update any state that might change as a result.
fa1c114f
JS		 2918 *
2919 * XXX needed?
2920 */
e0d687bd 2921/* ath5k_chan_change(ah, c); */
fa1c114f 2922
e0d687bd 2923 ath5k_beacon_config(ah);
d7dc1003 2924 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 2925
e0d687bd 2926 ieee80211_wake_queues(ah->hw);
397f385b 2927
fa1c114f
JS		 2928 return 0;
2929err:
2930 return ret;
2931}
2932
5faaff74
BC		 2933static void ath5k_reset_work(struct work_struct *work)
2934{
e0d687bd 2935 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
5faaff74
BC		 2936 reset_work);
2937
e0d687bd
PR		 2938 mutex_lock(&ah->lock);
2939 ath5k_reset(ah, NULL, true);
2940 mutex_unlock(&ah->lock);
5faaff74
BC		 2941}
2942
e829cf96 2943static int
132b1c3e 2944ath5k_init(struct ieee80211_hw *hw)
fa1c114f 2945{
132b1c3e 2946
e0d687bd 2947 struct ath5k_hw *ah = hw->priv;
8a63facc 2948 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
925e0b06 2949 struct ath5k_txq *txq;
8a63facc 2950 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2951 int ret;
2952
fa1c114f 2953
8a63facc
BC		 2954 /*
2955 * Collect the channel list. The 802.11 layer
6a2a0e73 2956 * is responsible for filtering this list based
8a63facc
BC		 2957 * on settings like the phy mode and regulatory
2958 * domain restrictions.
2959 */
2960 ret = ath5k_setup_bands(hw);
2961 if (ret) {
e0d687bd 2962 ATH5K_ERR(ah, "can't get channels\n");
8a63facc
BC		 2963 goto err;
2964 }
67d2e2df 2965
8a63facc
BC		 2966 /*
2967 * Allocate tx+rx descriptors and populate the lists.
2968 */
e0d687bd 2969 ret = ath5k_desc_alloc(ah);
8a63facc 2970 if (ret) {
e0d687bd 2971 ATH5K_ERR(ah, "can't allocate descriptors\n");
8a63facc
BC		 2972 goto err;
2973 }
fa1c114f 2974
8a63facc
BC		 2975 /*
2976 * Allocate hardware transmit queues: one queue for
2977 * beacon frames and one data queue for each QoS
2978 * priority. Note that hw functions handle resetting
2979 * these queues at the needed time.
2980 */
2981 ret = ath5k_beaconq_setup(ah);
2982 if (ret < 0) {
e0d687bd 2983 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n");
8a63facc
BC		 2984 goto err_desc;
2985 }
e0d687bd
PR		 2986 ah->bhalq = ret;
2987 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0);
2988 if (IS_ERR(ah->cabq)) {
2989 ATH5K_ERR(ah, "can't setup cab queue\n");
2990 ret = PTR_ERR(ah->cabq);
8a63facc
BC		 2991 goto err_bhal;
2992 }
fa1c114f 2993
22d8d9f8
BR		 2994 /* 5211 and 5212 usually support 10 queues but we better rely on the
2995 * capability information */
2996 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2997 /* This order matches mac80211's queue priority, so we can
2998 * directly use the mac80211 queue number without any mapping */
e0d687bd 2999 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
22d8d9f8 3000 if (IS_ERR(txq)) {
e0d687bd 3001 ATH5K_ERR(ah, "can't setup xmit queue\n");
22d8d9f8
BR		 3002 ret = PTR_ERR(txq);
3003 goto err_queues;
3004 }
e0d687bd 3005 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
22d8d9f8 3006 if (IS_ERR(txq)) {
e0d687bd 3007 ATH5K_ERR(ah, "can't setup xmit queue\n");
22d8d9f8
BR		 3008 ret = PTR_ERR(txq);
3009 goto err_queues;
3010 }
e0d687bd 3011 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
22d8d9f8 3012 if (IS_ERR(txq)) {
e0d687bd 3013 ATH5K_ERR(ah, "can't setup xmit queue\n");
22d8d9f8
BR		 3014 ret = PTR_ERR(txq);
3015 goto err_queues;
3016 }
e0d687bd 3017 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
22d8d9f8 3018 if (IS_ERR(txq)) {
e0d687bd 3019 ATH5K_ERR(ah, "can't setup xmit queue\n");
22d8d9f8
BR		 3020 ret = PTR_ERR(txq);
3021 goto err_queues;
3022 }
3023 hw->queues = 4;
3024 } else {
3025 /* older hardware (5210) can only support one data queue */
e0d687bd 3026 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
22d8d9f8 3027 if (IS_ERR(txq)) {
e0d687bd 3028 ATH5K_ERR(ah, "can't setup xmit queue\n");
22d8d9f8
BR		 3029 ret = PTR_ERR(txq);
3030 goto err_queues;
3031 }
3032 hw->queues = 1;
3033 }
fa1c114f 3034
e0d687bd
PR		 3035 tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah);
3036 tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah);
e0d687bd
PR		 3037 tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah);
3038 tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah);
be009370 3039
e0d687bd 3040 INIT_WORK(&ah->reset_work, ath5k_reset_work);
ce169aca 3041 INIT_WORK(&ah->calib_work, ath5k_calibrate_work);
e0d687bd 3042 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work);
fa1c114f 3043
fa9bfd61 3044 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
8a63facc 3045 if (ret) {
e0d687bd 3046 ATH5K_ERR(ah, "unable to read address from EEPROM\n");
8a63facc 3047 goto err_queues;
e30eb4ab 3048 }
2bed03eb 3049
8a63facc
BC		 3050 SET_IEEE80211_PERM_ADDR(hw, mac);
3051 /* All MAC address bits matter for ACKs */
e0d687bd 3052 ath5k_update_bssid_mask_and_opmode(ah, NULL);
8a63facc
BC		 3053
3054 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
3055 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
3056 if (ret) {
e0d687bd 3057 ATH5K_ERR(ah, "can't initialize regulatory system\n");
8a63facc
BC		 3058 goto err_queues;
3059 }
3060
3061 ret = ieee80211_register_hw(hw);
3062 if (ret) {
e0d687bd 3063 ATH5K_ERR(ah, "can't register ieee80211 hw\n");
8a63facc
BC		 3064 goto err_queues;
3065 }
3066
3067 if (!ath_is_world_regd(regulatory))
3068 regulatory_hint(hw->wiphy, regulatory->alpha2);
3069
e0d687bd 3070 ath5k_init_leds(ah);
8a63facc 3071
e0d687bd 3072 ath5k_sysfs_register(ah);
8a63facc
BC		 3073
3074 return 0;
3075err_queues:
e0d687bd 3076 ath5k_txq_release(ah);
8a63facc 3077err_bhal:
e0d687bd 3078 ath5k_hw_release_tx_queue(ah, ah->bhalq);
8a63facc 3079err_desc:
e0d687bd 3080 ath5k_desc_free(ah);
8a63facc
BC		 3081err:
3082 return ret;
3083}
3084
132b1c3e 3085void
bb1f3ad9 3086ath5k_deinit_ah(struct ath5k_hw *ah)
8a63facc 3087{
e0d687bd 3088 struct ieee80211_hw *hw = ah->hw;
8a63facc
BC		 3089
3090 /*
3091 * NB: the order of these is important:
3092 * o call the 802.11 layer before detaching ath5k_hw to
3093 * ensure callbacks into the driver to delete global
3094 * key cache entries can be handled
3095 * o reclaim the tx queue data structures after calling
3096 * the 802.11 layer as we'll get called back to reclaim
3097 * node state and potentially want to use them
3098 * o to cleanup the tx queues the hal is called, so detach
3099 * it last
3100 * XXX: ??? detach ath5k_hw ???
3101 * Other than that, it's straightforward...
3102 */
3103 ieee80211_unregister_hw(hw);
e0d687bd
PR		 3104 ath5k_desc_free(ah);
3105 ath5k_txq_release(ah);
3106 ath5k_hw_release_tx_queue(ah, ah->bhalq);
3107 ath5k_unregister_leds(ah);
8a63facc 3108
e0d687bd 3109 ath5k_sysfs_unregister(ah);
8a63facc
BC		 3110 /*
3111 * NB: can't reclaim these until after ieee80211_ifdetach
3112 * returns because we'll get called back to reclaim node
3113 * state and potentially want to use them.
3114 */
e0d687bd
PR		 3115 ath5k_hw_deinit(ah);
3116 free_irq(ah->irq, ah);
8a63facc
BC		 3117}
3118
cd2c5486 3119bool
e0d687bd 3120ath5k_any_vif_assoc(struct ath5k_hw *ah)
b1ae1edf 3121{
e4b0b32a 3122 struct ath5k_vif_iter_data iter_data;
b1ae1edf
BG		 3123 iter_data.hw_macaddr = NULL;
3124 iter_data.any_assoc = false;
3125 iter_data.need_set_hw_addr = false;
3126 iter_data.found_active = true;
3127
8b2c9824
JB		 3128 ieee80211_iterate_active_interfaces_atomic(
3129 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
3130 ath5k_vif_iter, &iter_data);
b1ae1edf
BG		 3131 return iter_data.any_assoc;
3132}
3133
cd2c5486 3134void
f5cbc8ba 3135ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
8a63facc 3136{
e0d687bd 3137 struct ath5k_hw *ah = hw->priv;
8a63facc
BC		 3138 u32 rfilt;
3139 rfilt = ath5k_hw_get_rx_filter(ah);
3140 if (enable)
3141 rfilt |= AR5K_RX_FILTER_BEACON;
3142 else
3143 rfilt &= ~AR5K_RX_FILTER_BEACON;
3144 ath5k_hw_set_rx_filter(ah, rfilt);
e0d687bd 3145 ah->filter_flags = rfilt;
8a63facc 3146}
227842d1
JP		 3147
3148void _ath5k_printk(const struct ath5k_hw *ah, const char *level,
3149 const char *fmt, ...)
3150{
3151 struct va_format vaf;
3152 va_list args;
3153
3154 va_start(args, fmt);
3155
3156 vaf.fmt = fmt;
3157 vaf.va = &args;
3158
3159 if (ah && ah->hw)
3160 printk("%s" pr_fmt("%s: %pV"),
3161 level, wiphy_name(ah->hw->wiphy), &vaf);
3162 else
3163 printk("%s" pr_fmt("%pV"), level, &vaf);
3164
3165 va_end(args);
3166}
Linux kernel - Deliverables
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