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fa1c114f JS |
1 | /*- |
2 | * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting | |
3 | * Copyright (c) 2004-2005 Atheros Communications, Inc. | |
4 | * Copyright (c) 2006 Devicescape Software, Inc. | |
5 | * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> | |
6 | * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu> | |
7 | * | |
8 | * All rights reserved. | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or without | |
11 | * modification, are permitted provided that the following conditions | |
12 | * are met: | |
13 | * 1. Redistributions of source code must retain the above copyright | |
14 | * notice, this list of conditions and the following disclaimer, | |
15 | * without modification. | |
16 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer | |
17 | * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any | |
18 | * redistribution must be conditioned upon including a substantially | |
19 | * similar Disclaimer requirement for further binary redistribution. | |
20 | * 3. Neither the names of the above-listed copyright holders nor the names | |
21 | * of any contributors may be used to endorse or promote products derived | |
22 | * from this software without specific prior written permission. | |
23 | * | |
24 | * Alternatively, this software may be distributed under the terms of the | |
25 | * GNU General Public License ("GPL") version 2 as published by the Free | |
26 | * Software Foundation. | |
27 | * | |
28 | * NO WARRANTY | |
29 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
30 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
31 | * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY | |
32 | * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL | |
33 | * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, | |
34 | * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
35 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
36 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER | |
37 | * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
38 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
39 | * THE POSSIBILITY OF SUCH DAMAGES. | |
40 | * | |
41 | */ | |
42 | ||
516304b0 JP |
43 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
44 | ||
fa1c114f JS |
45 | #include <linux/module.h> |
46 | #include <linux/delay.h> | |
b7f080cf | 47 | #include <linux/dma-mapping.h> |
274c7c36 | 48 | #include <linux/hardirq.h> |
fa1c114f | 49 | #include <linux/if.h> |
274c7c36 | 50 | #include <linux/io.h> |
fa1c114f JS |
51 | #include <linux/netdevice.h> |
52 | #include <linux/cache.h> | |
fa1c114f JS |
53 | #include <linux/ethtool.h> |
54 | #include <linux/uaccess.h> | |
5a0e3ad6 | 55 | #include <linux/slab.h> |
b1ae1edf | 56 | #include <linux/etherdevice.h> |
931be260 | 57 | #include <linux/nl80211.h> |
fa1c114f JS |
58 | |
59 | #include <net/ieee80211_radiotap.h> | |
60 | ||
61 | #include <asm/unaligned.h> | |
62 | ||
63 | #include "base.h" | |
64 | #include "reg.h" | |
65 | #include "debug.h" | |
2111ac0d | 66 | #include "ani.h" |
931be260 PR |
67 | #include "ath5k.h" |
68 | #include "../regd.h" | |
fa1c114f | 69 | |
0e472252 BC |
70 | #define CREATE_TRACE_POINTS |
71 | #include "trace.h" | |
72 | ||
eb939922 | 73 | bool ath5k_modparam_nohwcrypt; |
18cb6e32 | 74 | module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO); |
9ad9a26e | 75 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); |
fa1c114f | 76 | |
eb939922 | 77 | static bool modparam_fastchanswitch; |
a99168ee NK |
78 | module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO); |
79 | MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios."); | |
80 | ||
11deb533 | 81 | static bool ath5k_modparam_no_hw_rfkill_switch; |
84e1e737 NK |
82 | module_param_named(no_hw_rfkill_switch, ath5k_modparam_no_hw_rfkill_switch, |
83 | bool, S_IRUGO); | |
84 | MODULE_PARM_DESC(no_hw_rfkill_switch, "Ignore the GPIO RFKill switch state"); | |
85 | ||
a99168ee | 86 | |
fa1c114f JS |
87 | /* Module info */ |
88 | MODULE_AUTHOR("Jiri Slaby"); | |
89 | MODULE_AUTHOR("Nick Kossifidis"); | |
90 | MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); | |
91 | MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards"); | |
92 | MODULE_LICENSE("Dual BSD/GPL"); | |
fa1c114f | 93 | |
132b1c3e | 94 | static int ath5k_init(struct ieee80211_hw *hw); |
e0d687bd | 95 | static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan, |
8aec7af9 | 96 | bool skip_pcu); |
fa1c114f | 97 | |
fa1c114f | 98 | /* Known SREVs */ |
2c91108c | 99 | static const struct ath5k_srev_name srev_names[] = { |
a0b907ee FF |
100 | #ifdef CONFIG_ATHEROS_AR231X |
101 | { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 }, | |
102 | { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 }, | |
103 | { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 }, | |
104 | { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 }, | |
105 | { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 }, | |
106 | { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 }, | |
107 | { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 }, | |
108 | #else | |
1bef016a NK |
109 | { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 }, |
110 | { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 }, | |
111 | { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A }, | |
112 | { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B }, | |
113 | { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 }, | |
114 | { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 }, | |
115 | { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 }, | |
116 | { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A }, | |
117 | { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 }, | |
118 | { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 }, | |
119 | { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 }, | |
120 | { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 }, | |
121 | { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 }, | |
122 | { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 }, | |
123 | { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 }, | |
124 | { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 }, | |
125 | { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 }, | |
126 | { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 }, | |
a0b907ee | 127 | #endif |
1bef016a | 128 | { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN }, |
fa1c114f JS |
129 | { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, |
130 | { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, | |
1bef016a | 131 | { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A }, |
fa1c114f JS |
132 | { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, |
133 | { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, | |
134 | { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, | |
1bef016a | 135 | { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B }, |
fa1c114f JS |
136 | { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, |
137 | { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, | |
1bef016a NK |
138 | { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B }, |
139 | { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 }, | |
140 | { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 }, | |
1bef016a | 141 | { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 }, |
fa1c114f | 142 | { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, |
a0b907ee FF |
143 | #ifdef CONFIG_ATHEROS_AR231X |
144 | { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 }, | |
145 | { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 }, | |
146 | #endif | |
fa1c114f JS |
147 | { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, |
148 | }; | |
149 | ||
2c91108c | 150 | static const struct ieee80211_rate ath5k_rates[] = { |
63266a65 BR |
151 | { .bitrate = 10, |
152 | .hw_value = ATH5K_RATE_CODE_1M, }, | |
153 | { .bitrate = 20, | |
154 | .hw_value = ATH5K_RATE_CODE_2M, | |
155 | .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE, | |
156 | .flags = IEEE80211_RATE_SHORT_PREAMBLE }, | |
157 | { .bitrate = 55, | |
158 | .hw_value = ATH5K_RATE_CODE_5_5M, | |
159 | .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE, | |
160 | .flags = IEEE80211_RATE_SHORT_PREAMBLE }, | |
161 | { .bitrate = 110, | |
162 | .hw_value = ATH5K_RATE_CODE_11M, | |
163 | .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE, | |
164 | .flags = IEEE80211_RATE_SHORT_PREAMBLE }, | |
165 | { .bitrate = 60, | |
166 | .hw_value = ATH5K_RATE_CODE_6M, | |
167 | .flags = 0 }, | |
168 | { .bitrate = 90, | |
169 | .hw_value = ATH5K_RATE_CODE_9M, | |
170 | .flags = 0 }, | |
171 | { .bitrate = 120, | |
172 | .hw_value = ATH5K_RATE_CODE_12M, | |
173 | .flags = 0 }, | |
174 | { .bitrate = 180, | |
175 | .hw_value = ATH5K_RATE_CODE_18M, | |
176 | .flags = 0 }, | |
177 | { .bitrate = 240, | |
178 | .hw_value = ATH5K_RATE_CODE_24M, | |
179 | .flags = 0 }, | |
180 | { .bitrate = 360, | |
181 | .hw_value = ATH5K_RATE_CODE_36M, | |
182 | .flags = 0 }, | |
183 | { .bitrate = 480, | |
184 | .hw_value = ATH5K_RATE_CODE_48M, | |
185 | .flags = 0 }, | |
186 | { .bitrate = 540, | |
187 | .hw_value = ATH5K_RATE_CODE_54M, | |
188 | .flags = 0 }, | |
63266a65 BR |
189 | }; |
190 | ||
fa1c114f JS |
191 | static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) |
192 | { | |
193 | u64 tsf = ath5k_hw_get_tsf64(ah); | |
194 | ||
195 | if ((tsf & 0x7fff) < rstamp) | |
196 | tsf -= 0x8000; | |
197 | ||
198 | return (tsf & ~0x7fff) | rstamp; | |
199 | } | |
200 | ||
e5b046d8 | 201 | const char * |
fa1c114f JS |
202 | ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val) |
203 | { | |
204 | const char *name = "xxxxx"; | |
205 | unsigned int i; | |
206 | ||
207 | for (i = 0; i < ARRAY_SIZE(srev_names); i++) { | |
208 | if (srev_names[i].sr_type != type) | |
209 | continue; | |
75d0edb8 NK |
210 | |
211 | if ((val & 0xf0) == srev_names[i].sr_val) | |
212 | name = srev_names[i].sr_name; | |
213 | ||
214 | if ((val & 0xff) == srev_names[i].sr_val) { | |
fa1c114f JS |
215 | name = srev_names[i].sr_name; |
216 | break; | |
217 | } | |
218 | } | |
219 | ||
220 | return name; | |
221 | } | |
e5aa8474 LR |
222 | static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset) |
223 | { | |
224 | struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; | |
225 | return ath5k_hw_reg_read(ah, reg_offset); | |
226 | } | |
227 | ||
228 | static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) | |
229 | { | |
230 | struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; | |
231 | ath5k_hw_reg_write(ah, val, reg_offset); | |
232 | } | |
233 | ||
234 | static const struct ath_ops ath5k_common_ops = { | |
235 | .read = ath5k_ioread32, | |
236 | .write = ath5k_iowrite32, | |
237 | }; | |
fa1c114f | 238 | |
8a63facc BC |
239 | /***********************\ |
240 | * Driver Initialization * | |
241 | \***********************/ | |
242 | ||
0c0280bd LR |
243 | static void ath5k_reg_notifier(struct wiphy *wiphy, |
244 | struct regulatory_request *request) | |
fa1c114f | 245 | { |
8a63facc | 246 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); |
e0d687bd PR |
247 | struct ath5k_hw *ah = hw->priv; |
248 | struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); | |
fa1c114f | 249 | |
0c0280bd | 250 | ath_reg_notifier_apply(wiphy, request, regulatory); |
8a63facc | 251 | } |
6ccf15a1 | 252 | |
8a63facc BC |
253 | /********************\ |
254 | * Channel/mode setup * | |
255 | \********************/ | |
fa1c114f | 256 | |
8a63facc | 257 | /* |
2f8684ce | 258 | * Returns true for the channel numbers used. |
8a63facc | 259 | */ |
2f8684ce LR |
260 | #ifdef CONFIG_ATH5K_TEST_CHANNELS |
261 | static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band) | |
262 | { | |
263 | return true; | |
264 | } | |
265 | ||
266 | #else | |
410e6120 | 267 | static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band) |
8a63facc | 268 | { |
410e6120 BR |
269 | if (band == IEEE80211_BAND_2GHZ && chan <= 14) |
270 | return true; | |
271 | ||
272 | return /* UNII 1,2 */ | |
273 | (((chan & 3) == 0 && chan >= 36 && chan <= 64) || | |
8a63facc BC |
274 | /* midband */ |
275 | ((chan & 3) == 0 && chan >= 100 && chan <= 140) || | |
276 | /* UNII-3 */ | |
410e6120 BR |
277 | ((chan & 3) == 1 && chan >= 149 && chan <= 165) || |
278 | /* 802.11j 5.030-5.080 GHz (20MHz) */ | |
279 | (chan == 8 || chan == 12 || chan == 16) || | |
280 | /* 802.11j 4.9GHz (20MHz) */ | |
281 | (chan == 184 || chan == 188 || chan == 192 || chan == 196)); | |
8a63facc | 282 | } |
2f8684ce | 283 | #endif |
fa1c114f | 284 | |
8a63facc | 285 | static unsigned int |
97d9c3a3 BR |
286 | ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels, |
287 | unsigned int mode, unsigned int max) | |
8a63facc | 288 | { |
32c25464 | 289 | unsigned int count, size, freq, ch; |
90c02d72 | 290 | enum ieee80211_band band; |
fa1c114f | 291 | |
8a63facc BC |
292 | switch (mode) { |
293 | case AR5K_MODE_11A: | |
8a63facc | 294 | /* 1..220, but 2GHz frequencies are filtered by check_channel */ |
97d9c3a3 | 295 | size = 220; |
90c02d72 | 296 | band = IEEE80211_BAND_5GHZ; |
8a63facc BC |
297 | break; |
298 | case AR5K_MODE_11B: | |
299 | case AR5K_MODE_11G: | |
8a63facc | 300 | size = 26; |
90c02d72 | 301 | band = IEEE80211_BAND_2GHZ; |
8a63facc BC |
302 | break; |
303 | default: | |
e0d687bd | 304 | ATH5K_WARN(ah, "bad mode, not copying channels\n"); |
8a63facc | 305 | return 0; |
fa1c114f JS |
306 | } |
307 | ||
2b1351a3 BR |
308 | count = 0; |
309 | for (ch = 1; ch <= size && count < max; ch++) { | |
90c02d72 BR |
310 | freq = ieee80211_channel_to_frequency(ch, band); |
311 | ||
312 | if (freq == 0) /* mapping failed - not a standard channel */ | |
313 | continue; | |
fa1c114f | 314 | |
32c25464 PR |
315 | /* Write channel info, needed for ath5k_channel_ok() */ |
316 | channels[count].center_freq = freq; | |
317 | channels[count].band = band; | |
318 | channels[count].hw_value = mode; | |
319 | ||
8a63facc | 320 | /* Check if channel is supported by the chipset */ |
32c25464 | 321 | if (!ath5k_channel_ok(ah, &channels[count])) |
8a63facc | 322 | continue; |
f59ac048 | 323 | |
2f8684ce | 324 | if (!ath5k_is_standard_channel(ch, band)) |
8a63facc | 325 | continue; |
f59ac048 | 326 | |
8a63facc | 327 | count++; |
8a63facc | 328 | } |
fa1c114f | 329 | |
8a63facc BC |
330 | return count; |
331 | } | |
fa1c114f | 332 | |
8a63facc | 333 | static void |
e0d687bd | 334 | ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b) |
8a63facc BC |
335 | { |
336 | u8 i; | |
fa1c114f | 337 | |
8a63facc | 338 | for (i = 0; i < AR5K_MAX_RATES; i++) |
e0d687bd | 339 | ah->rate_idx[b->band][i] = -1; |
fa1c114f | 340 | |
8a63facc | 341 | for (i = 0; i < b->n_bitrates; i++) { |
e0d687bd | 342 | ah->rate_idx[b->band][b->bitrates[i].hw_value] = i; |
8a63facc | 343 | if (b->bitrates[i].hw_value_short) |
e0d687bd | 344 | ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; |
fa1c114f | 345 | } |
8a63facc | 346 | } |
fa1c114f | 347 | |
8a63facc BC |
348 | static int |
349 | ath5k_setup_bands(struct ieee80211_hw *hw) | |
350 | { | |
e0d687bd | 351 | struct ath5k_hw *ah = hw->priv; |
8a63facc BC |
352 | struct ieee80211_supported_band *sband; |
353 | int max_c, count_c = 0; | |
354 | int i; | |
fa1c114f | 355 | |
e0d687bd PR |
356 | BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS); |
357 | max_c = ARRAY_SIZE(ah->channels); | |
db719718 | 358 | |
8a63facc | 359 | /* 2GHz band */ |
e0d687bd | 360 | sband = &ah->sbands[IEEE80211_BAND_2GHZ]; |
8a63facc | 361 | sband->band = IEEE80211_BAND_2GHZ; |
e0d687bd | 362 | sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0]; |
9adca126 | 363 | |
e0d687bd | 364 | if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) { |
8a63facc BC |
365 | /* G mode */ |
366 | memcpy(sband->bitrates, &ath5k_rates[0], | |
367 | sizeof(struct ieee80211_rate) * 12); | |
368 | sband->n_bitrates = 12; | |
2f7fe870 | 369 | |
e0d687bd | 370 | sband->channels = ah->channels; |
08105690 | 371 | sband->n_channels = ath5k_setup_channels(ah, sband->channels, |
8a63facc | 372 | AR5K_MODE_11G, max_c); |
fa1c114f | 373 | |
8a63facc BC |
374 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; |
375 | count_c = sband->n_channels; | |
376 | max_c -= count_c; | |
e0d687bd | 377 | } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) { |
8a63facc BC |
378 | /* B mode */ |
379 | memcpy(sband->bitrates, &ath5k_rates[0], | |
380 | sizeof(struct ieee80211_rate) * 4); | |
381 | sband->n_bitrates = 4; | |
fa1c114f | 382 | |
8a63facc BC |
383 | /* 5211 only supports B rates and uses 4bit rate codes |
384 | * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B) | |
385 | * fix them up here: | |
386 | */ | |
387 | if (ah->ah_version == AR5K_AR5211) { | |
388 | for (i = 0; i < 4; i++) { | |
389 | sband->bitrates[i].hw_value = | |
390 | sband->bitrates[i].hw_value & 0xF; | |
391 | sband->bitrates[i].hw_value_short = | |
392 | sband->bitrates[i].hw_value_short & 0xF; | |
fa1c114f JS |
393 | } |
394 | } | |
fa1c114f | 395 | |
e0d687bd | 396 | sband->channels = ah->channels; |
08105690 | 397 | sband->n_channels = ath5k_setup_channels(ah, sband->channels, |
8a63facc | 398 | AR5K_MODE_11B, max_c); |
fa1c114f | 399 | |
8a63facc BC |
400 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; |
401 | count_c = sband->n_channels; | |
402 | max_c -= count_c; | |
403 | } | |
e0d687bd | 404 | ath5k_setup_rate_idx(ah, sband); |
fa1c114f | 405 | |
8a63facc | 406 | /* 5GHz band, A mode */ |
e0d687bd PR |
407 | if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) { |
408 | sband = &ah->sbands[IEEE80211_BAND_5GHZ]; | |
8a63facc | 409 | sband->band = IEEE80211_BAND_5GHZ; |
e0d687bd | 410 | sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0]; |
fa1c114f | 411 | |
8a63facc BC |
412 | memcpy(sband->bitrates, &ath5k_rates[4], |
413 | sizeof(struct ieee80211_rate) * 8); | |
414 | sband->n_bitrates = 8; | |
fa1c114f | 415 | |
e0d687bd | 416 | sband->channels = &ah->channels[count_c]; |
08105690 | 417 | sband->n_channels = ath5k_setup_channels(ah, sband->channels, |
8a63facc | 418 | AR5K_MODE_11A, max_c); |
fa1c114f | 419 | |
8a63facc BC |
420 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband; |
421 | } | |
e0d687bd | 422 | ath5k_setup_rate_idx(ah, sband); |
8a63facc | 423 | |
e0d687bd | 424 | ath5k_debug_dump_bands(ah); |
fa1c114f | 425 | |
fa1c114f JS |
426 | return 0; |
427 | } | |
428 | ||
8a63facc BC |
429 | /* |
430 | * Set/change channels. We always reset the chip. | |
431 | * To accomplish this we must first cleanup any pending DMA, | |
432 | * then restart stuff after a la ath5k_init. | |
433 | * | |
e0d687bd | 434 | * Called with ah->lock. |
8a63facc | 435 | */ |
cd2c5486 | 436 | int |
e0d687bd | 437 | ath5k_chan_set(struct ath5k_hw *ah, struct ieee80211_channel *chan) |
8a63facc | 438 | { |
e0d687bd | 439 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, |
8a63facc | 440 | "channel set, resetting (%u -> %u MHz)\n", |
e0d687bd | 441 | ah->curchan->center_freq, chan->center_freq); |
8a63facc | 442 | |
8451d22d | 443 | /* |
8a63facc BC |
444 | * To switch channels clear any pending DMA operations; |
445 | * wait long enough for the RX fifo to drain, reset the | |
446 | * hardware at the new frequency, and then re-enable | |
447 | * the relevant bits of the h/w. | |
8451d22d | 448 | */ |
e0d687bd | 449 | return ath5k_reset(ah, chan, true); |
fa1c114f | 450 | } |
fa1c114f | 451 | |
e4b0b32a | 452 | void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
b1ae1edf | 453 | { |
e4b0b32a | 454 | struct ath5k_vif_iter_data *iter_data = data; |
b1ae1edf | 455 | int i; |
62c58fb4 | 456 | struct ath5k_vif *avf = (void *)vif->drv_priv; |
b1ae1edf BG |
457 | |
458 | if (iter_data->hw_macaddr) | |
459 | for (i = 0; i < ETH_ALEN; i++) | |
460 | iter_data->mask[i] &= | |
461 | ~(iter_data->hw_macaddr[i] ^ mac[i]); | |
462 | ||
463 | if (!iter_data->found_active) { | |
464 | iter_data->found_active = true; | |
465 | memcpy(iter_data->active_mac, mac, ETH_ALEN); | |
466 | } | |
467 | ||
468 | if (iter_data->need_set_hw_addr && iter_data->hw_macaddr) | |
2e42e474 | 469 | if (ether_addr_equal(iter_data->hw_macaddr, mac)) |
b1ae1edf BG |
470 | iter_data->need_set_hw_addr = false; |
471 | ||
472 | if (!iter_data->any_assoc) { | |
b1ae1edf BG |
473 | if (avf->assoc) |
474 | iter_data->any_assoc = true; | |
475 | } | |
62c58fb4 BG |
476 | |
477 | /* Calculate combined mode - when APs are active, operate in AP mode. | |
478 | * Otherwise use the mode of the new interface. This can currently | |
479 | * only deal with combinations of APs and STAs. Only one ad-hoc | |
7afbb2f0 | 480 | * interfaces is allowed. |
62c58fb4 BG |
481 | */ |
482 | if (avf->opmode == NL80211_IFTYPE_AP) | |
483 | iter_data->opmode = NL80211_IFTYPE_AP; | |
e4b0b32a BG |
484 | else { |
485 | if (avf->opmode == NL80211_IFTYPE_STATION) | |
486 | iter_data->n_stas++; | |
62c58fb4 BG |
487 | if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED) |
488 | iter_data->opmode = avf->opmode; | |
e4b0b32a | 489 | } |
b1ae1edf BG |
490 | } |
491 | ||
cd2c5486 | 492 | void |
e0d687bd | 493 | ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah, |
cd2c5486 | 494 | struct ieee80211_vif *vif) |
b1ae1edf | 495 | { |
e0d687bd | 496 | struct ath_common *common = ath5k_hw_common(ah); |
e4b0b32a BG |
497 | struct ath5k_vif_iter_data iter_data; |
498 | u32 rfilt; | |
b1ae1edf BG |
499 | |
500 | /* | |
501 | * Use the hardware MAC address as reference, the hardware uses it | |
502 | * together with the BSSID mask when matching addresses. | |
503 | */ | |
504 | iter_data.hw_macaddr = common->macaddr; | |
505 | memset(&iter_data.mask, 0xff, ETH_ALEN); | |
506 | iter_data.found_active = false; | |
507 | iter_data.need_set_hw_addr = true; | |
62c58fb4 | 508 | iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED; |
e4b0b32a | 509 | iter_data.n_stas = 0; |
b1ae1edf BG |
510 | |
511 | if (vif) | |
e4b0b32a | 512 | ath5k_vif_iter(&iter_data, vif->addr, vif); |
b1ae1edf BG |
513 | |
514 | /* Get list of all active MAC addresses */ | |
8b2c9824 JB |
515 | ieee80211_iterate_active_interfaces_atomic( |
516 | ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL, | |
517 | ath5k_vif_iter, &iter_data); | |
e0d687bd | 518 | memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN); |
b1ae1edf | 519 | |
e0d687bd PR |
520 | ah->opmode = iter_data.opmode; |
521 | if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED) | |
62c58fb4 | 522 | /* Nothing active, default to station mode */ |
e0d687bd | 523 | ah->opmode = NL80211_IFTYPE_STATION; |
62c58fb4 | 524 | |
e0d687bd PR |
525 | ath5k_hw_set_opmode(ah, ah->opmode); |
526 | ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n", | |
527 | ah->opmode, ath_opmode_to_string(ah->opmode)); | |
62c58fb4 | 528 | |
b1ae1edf | 529 | if (iter_data.need_set_hw_addr && iter_data.found_active) |
e0d687bd | 530 | ath5k_hw_set_lladdr(ah, iter_data.active_mac); |
b1ae1edf | 531 | |
e0d687bd PR |
532 | if (ath5k_hw_hasbssidmask(ah)) |
533 | ath5k_hw_set_bssid_mask(ah, ah->bssidmask); | |
b1ae1edf | 534 | |
e4b0b32a BG |
535 | /* Set up RX Filter */ |
536 | if (iter_data.n_stas > 1) { | |
537 | /* If you have multiple STA interfaces connected to | |
538 | * different APs, ARPs are not received (most of the time?) | |
6a2a0e73 | 539 | * Enabling PROMISC appears to fix that problem. |
e4b0b32a | 540 | */ |
e0d687bd | 541 | ah->filter_flags |= AR5K_RX_FILTER_PROM; |
e4b0b32a | 542 | } |
fa1c114f | 543 | |
e0d687bd PR |
544 | rfilt = ah->filter_flags; |
545 | ath5k_hw_set_rx_filter(ah, rfilt); | |
546 | ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); | |
8a63facc | 547 | } |
fa1c114f | 548 | |
8a63facc | 549 | static inline int |
e0d687bd | 550 | ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix) |
8a63facc BC |
551 | { |
552 | int rix; | |
fa1c114f | 553 | |
8a63facc BC |
554 | /* return base rate on errors */ |
555 | if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES, | |
556 | "hw_rix out of bounds: %x\n", hw_rix)) | |
557 | return 0; | |
558 | ||
e0d687bd | 559 | rix = ah->rate_idx[ah->curchan->band][hw_rix]; |
8a63facc BC |
560 | if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix)) |
561 | rix = 0; | |
562 | ||
563 | return rix; | |
564 | } | |
565 | ||
566 | /***************\ | |
567 | * Buffers setup * | |
568 | \***************/ | |
569 | ||
570 | static | |
e0d687bd | 571 | struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr) |
8a63facc | 572 | { |
e0d687bd | 573 | struct ath_common *common = ath5k_hw_common(ah); |
8a63facc | 574 | struct sk_buff *skb; |
fa1c114f JS |
575 | |
576 | /* | |
8a63facc BC |
577 | * Allocate buffer with headroom_needed space for the |
578 | * fake physical layer header at the start. | |
fa1c114f | 579 | */ |
8a63facc BC |
580 | skb = ath_rxbuf_alloc(common, |
581 | common->rx_bufsize, | |
582 | GFP_ATOMIC); | |
fa1c114f | 583 | |
8a63facc | 584 | if (!skb) { |
e0d687bd | 585 | ATH5K_ERR(ah, "can't alloc skbuff of size %u\n", |
8a63facc BC |
586 | common->rx_bufsize); |
587 | return NULL; | |
fa1c114f JS |
588 | } |
589 | ||
e0d687bd | 590 | *skb_addr = dma_map_single(ah->dev, |
8a63facc | 591 | skb->data, common->rx_bufsize, |
aeae4ac9 FF |
592 | DMA_FROM_DEVICE); |
593 | ||
e0d687bd PR |
594 | if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) { |
595 | ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__); | |
8a63facc BC |
596 | dev_kfree_skb(skb); |
597 | return NULL; | |
0e149cf5 | 598 | } |
8a63facc BC |
599 | return skb; |
600 | } | |
0e149cf5 | 601 | |
8a63facc | 602 | static int |
e0d687bd | 603 | ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) |
8a63facc | 604 | { |
8a63facc BC |
605 | struct sk_buff *skb = bf->skb; |
606 | struct ath5k_desc *ds; | |
607 | int ret; | |
fa1c114f | 608 | |
8a63facc | 609 | if (!skb) { |
e0d687bd | 610 | skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr); |
8a63facc BC |
611 | if (!skb) |
612 | return -ENOMEM; | |
613 | bf->skb = skb; | |
f769c36b BC |
614 | } |
615 | ||
8a63facc BC |
616 | /* |
617 | * Setup descriptors. For receive we always terminate | |
618 | * the descriptor list with a self-linked entry so we'll | |
619 | * not get overrun under high load (as can happen with a | |
620 | * 5212 when ANI processing enables PHY error frames). | |
621 | * | |
622 | * To ensure the last descriptor is self-linked we create | |
623 | * each descriptor as self-linked and add it to the end. As | |
624 | * each additional descriptor is added the previous self-linked | |
625 | * entry is "fixed" naturally. This should be safe even | |
626 | * if DMA is happening. When processing RX interrupts we | |
627 | * never remove/process the last, self-linked, entry on the | |
628 | * descriptor list. This ensures the hardware always has | |
629 | * someplace to write a new frame. | |
630 | */ | |
631 | ds = bf->desc; | |
632 | ds->ds_link = bf->daddr; /* link to self */ | |
633 | ds->ds_data = bf->skbaddr; | |
634 | ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0); | |
fa1c114f | 635 | if (ret) { |
e0d687bd | 636 | ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__); |
8a63facc | 637 | return ret; |
fa1c114f JS |
638 | } |
639 | ||
e0d687bd PR |
640 | if (ah->rxlink != NULL) |
641 | *ah->rxlink = bf->daddr; | |
642 | ah->rxlink = &ds->ds_link; | |
fa1c114f | 643 | return 0; |
fa1c114f JS |
644 | } |
645 | ||
8a63facc | 646 | static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb) |
fa1c114f | 647 | { |
8a63facc BC |
648 | struct ieee80211_hdr *hdr; |
649 | enum ath5k_pkt_type htype; | |
650 | __le16 fc; | |
fa1c114f | 651 | |
8a63facc BC |
652 | hdr = (struct ieee80211_hdr *)skb->data; |
653 | fc = hdr->frame_control; | |
fa1c114f | 654 | |
8a63facc BC |
655 | if (ieee80211_is_beacon(fc)) |
656 | htype = AR5K_PKT_TYPE_BEACON; | |
657 | else if (ieee80211_is_probe_resp(fc)) | |
658 | htype = AR5K_PKT_TYPE_PROBE_RESP; | |
659 | else if (ieee80211_is_atim(fc)) | |
660 | htype = AR5K_PKT_TYPE_ATIM; | |
661 | else if (ieee80211_is_pspoll(fc)) | |
662 | htype = AR5K_PKT_TYPE_PSPOLL; | |
fa1c114f | 663 | else |
8a63facc | 664 | htype = AR5K_PKT_TYPE_NORMAL; |
fa1c114f | 665 | |
8a63facc | 666 | return htype; |
42639fcd BC |
667 | } |
668 | ||
8a63facc | 669 | static int |
e0d687bd | 670 | ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf, |
8a63facc | 671 | struct ath5k_txq *txq, int padsize) |
fa1c114f | 672 | { |
8a63facc BC |
673 | struct ath5k_desc *ds = bf->desc; |
674 | struct sk_buff *skb = bf->skb; | |
675 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
676 | unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; | |
677 | struct ieee80211_rate *rate; | |
678 | unsigned int mrr_rate[3], mrr_tries[3]; | |
679 | int i, ret; | |
680 | u16 hw_rate; | |
681 | u16 cts_rate = 0; | |
682 | u16 duration = 0; | |
683 | u8 rc_flags; | |
fa1c114f | 684 | |
8a63facc | 685 | flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; |
fa1c114f | 686 | |
8a63facc | 687 | /* XXX endianness */ |
e0d687bd | 688 | bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, |
aeae4ac9 | 689 | DMA_TO_DEVICE); |
fa1c114f | 690 | |
e0d687bd | 691 | rate = ieee80211_get_tx_rate(ah->hw, info); |
29ad2fac JL |
692 | if (!rate) { |
693 | ret = -EINVAL; | |
694 | goto err_unmap; | |
695 | } | |
fa1c114f | 696 | |
8a63facc BC |
697 | if (info->flags & IEEE80211_TX_CTL_NO_ACK) |
698 | flags |= AR5K_TXDESC_NOACK; | |
fa1c114f | 699 | |
8a63facc BC |
700 | rc_flags = info->control.rates[0].flags; |
701 | hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? | |
702 | rate->hw_value_short : rate->hw_value; | |
42639fcd | 703 | |
8a63facc BC |
704 | pktlen = skb->len; |
705 | ||
706 | /* FIXME: If we are in g mode and rate is a CCK rate | |
707 | * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta | |
708 | * from tx power (value is in dB units already) */ | |
709 | if (info->control.hw_key) { | |
710 | keyidx = info->control.hw_key->hw_key_idx; | |
711 | pktlen += info->control.hw_key->icv_len; | |
712 | } | |
713 | if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { | |
714 | flags |= AR5K_TXDESC_RTSENA; | |
e0d687bd PR |
715 | cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; |
716 | duration = le16_to_cpu(ieee80211_rts_duration(ah->hw, | |
b1ae1edf | 717 | info->control.vif, pktlen, info)); |
8a63facc BC |
718 | } |
719 | if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { | |
720 | flags |= AR5K_TXDESC_CTSENA; | |
e0d687bd PR |
721 | cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; |
722 | duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw, | |
b1ae1edf | 723 | info->control.vif, pktlen, info)); |
8a63facc BC |
724 | } |
725 | ret = ah->ah_setup_tx_desc(ah, ds, pktlen, | |
726 | ieee80211_get_hdrlen_from_skb(skb), padsize, | |
727 | get_hw_packet_type(skb), | |
987af54f | 728 | (ah->ah_txpower.txp_requested * 2), |
8a63facc BC |
729 | hw_rate, |
730 | info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags, | |
731 | cts_rate, duration); | |
732 | if (ret) | |
733 | goto err_unmap; | |
734 | ||
86f62d9b NK |
735 | /* Set up MRR descriptor */ |
736 | if (ah->ah_capabilities.cap_has_mrr_support) { | |
737 | memset(mrr_rate, 0, sizeof(mrr_rate)); | |
738 | memset(mrr_tries, 0, sizeof(mrr_tries)); | |
739 | for (i = 0; i < 3; i++) { | |
740 | rate = ieee80211_get_alt_retry_rate(ah->hw, info, i); | |
741 | if (!rate) | |
742 | break; | |
fa1c114f | 743 | |
86f62d9b NK |
744 | mrr_rate[i] = rate->hw_value; |
745 | mrr_tries[i] = info->control.rates[i + 1].count; | |
746 | } | |
fa1c114f | 747 | |
86f62d9b NK |
748 | ath5k_hw_setup_mrr_tx_desc(ah, ds, |
749 | mrr_rate[0], mrr_tries[0], | |
750 | mrr_rate[1], mrr_tries[1], | |
751 | mrr_rate[2], mrr_tries[2]); | |
752 | } | |
fa1c114f | 753 | |
8a63facc BC |
754 | ds->ds_link = 0; |
755 | ds->ds_data = bf->skbaddr; | |
63266a65 | 756 | |
8a63facc BC |
757 | spin_lock_bh(&txq->lock); |
758 | list_add_tail(&bf->list, &txq->q); | |
925e0b06 | 759 | txq->txq_len++; |
8a63facc BC |
760 | if (txq->link == NULL) /* is this first packet? */ |
761 | ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); | |
762 | else /* no, so only link it */ | |
763 | *txq->link = bf->daddr; | |
63266a65 | 764 | |
8a63facc BC |
765 | txq->link = &ds->ds_link; |
766 | ath5k_hw_start_tx_dma(ah, txq->qnum); | |
767 | mmiowb(); | |
768 | spin_unlock_bh(&txq->lock); | |
769 | ||
770 | return 0; | |
771 | err_unmap: | |
e0d687bd | 772 | dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); |
8a63facc | 773 | return ret; |
63266a65 BR |
774 | } |
775 | ||
8a63facc BC |
776 | /*******************\ |
777 | * Descriptors setup * | |
778 | \*******************/ | |
779 | ||
d8ee398d | 780 | static int |
e0d687bd | 781 | ath5k_desc_alloc(struct ath5k_hw *ah) |
fa1c114f | 782 | { |
8a63facc BC |
783 | struct ath5k_desc *ds; |
784 | struct ath5k_buf *bf; | |
785 | dma_addr_t da; | |
786 | unsigned int i; | |
787 | int ret; | |
d8ee398d | 788 | |
8a63facc | 789 | /* allocate descriptors */ |
e0d687bd | 790 | ah->desc_len = sizeof(struct ath5k_desc) * |
8a63facc | 791 | (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); |
aeae4ac9 | 792 | |
e0d687bd PR |
793 | ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len, |
794 | &ah->desc_daddr, GFP_KERNEL); | |
795 | if (ah->desc == NULL) { | |
796 | ATH5K_ERR(ah, "can't allocate descriptors\n"); | |
8a63facc BC |
797 | ret = -ENOMEM; |
798 | goto err; | |
799 | } | |
e0d687bd PR |
800 | ds = ah->desc; |
801 | da = ah->desc_daddr; | |
802 | ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", | |
803 | ds, ah->desc_len, (unsigned long long)ah->desc_daddr); | |
fa1c114f | 804 | |
8a63facc BC |
805 | bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, |
806 | sizeof(struct ath5k_buf), GFP_KERNEL); | |
807 | if (bf == NULL) { | |
e0d687bd | 808 | ATH5K_ERR(ah, "can't allocate bufptr\n"); |
8a63facc BC |
809 | ret = -ENOMEM; |
810 | goto err_free; | |
811 | } | |
e0d687bd | 812 | ah->bufptr = bf; |
fa1c114f | 813 | |
e0d687bd | 814 | INIT_LIST_HEAD(&ah->rxbuf); |
8a63facc BC |
815 | for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { |
816 | bf->desc = ds; | |
817 | bf->daddr = da; | |
e0d687bd | 818 | list_add_tail(&bf->list, &ah->rxbuf); |
8a63facc | 819 | } |
d8ee398d | 820 | |
e0d687bd PR |
821 | INIT_LIST_HEAD(&ah->txbuf); |
822 | ah->txbuf_len = ATH_TXBUF; | |
e4bbf2f5 | 823 | for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) { |
8a63facc BC |
824 | bf->desc = ds; |
825 | bf->daddr = da; | |
e0d687bd | 826 | list_add_tail(&bf->list, &ah->txbuf); |
fa1c114f JS |
827 | } |
828 | ||
b1ae1edf | 829 | /* beacon buffers */ |
e0d687bd | 830 | INIT_LIST_HEAD(&ah->bcbuf); |
b1ae1edf BG |
831 | for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { |
832 | bf->desc = ds; | |
833 | bf->daddr = da; | |
e0d687bd | 834 | list_add_tail(&bf->list, &ah->bcbuf); |
b1ae1edf | 835 | } |
fa1c114f | 836 | |
8a63facc BC |
837 | return 0; |
838 | err_free: | |
e0d687bd | 839 | dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); |
8a63facc | 840 | err: |
e0d687bd | 841 | ah->desc = NULL; |
8a63facc BC |
842 | return ret; |
843 | } | |
fa1c114f | 844 | |
cd2c5486 | 845 | void |
e0d687bd | 846 | ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) |
cd2c5486 BR |
847 | { |
848 | BUG_ON(!bf); | |
849 | if (!bf->skb) | |
850 | return; | |
e0d687bd | 851 | dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len, |
cd2c5486 | 852 | DMA_TO_DEVICE); |
596ab5ec | 853 | ieee80211_free_txskb(ah->hw, bf->skb); |
cd2c5486 BR |
854 | bf->skb = NULL; |
855 | bf->skbaddr = 0; | |
856 | bf->desc->ds_data = 0; | |
857 | } | |
858 | ||
859 | void | |
e0d687bd | 860 | ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) |
cd2c5486 | 861 | { |
cd2c5486 BR |
862 | struct ath_common *common = ath5k_hw_common(ah); |
863 | ||
864 | BUG_ON(!bf); | |
865 | if (!bf->skb) | |
866 | return; | |
e0d687bd | 867 | dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize, |
cd2c5486 BR |
868 | DMA_FROM_DEVICE); |
869 | dev_kfree_skb_any(bf->skb); | |
870 | bf->skb = NULL; | |
871 | bf->skbaddr = 0; | |
872 | bf->desc->ds_data = 0; | |
873 | } | |
874 | ||
8a63facc | 875 | static void |
e0d687bd | 876 | ath5k_desc_free(struct ath5k_hw *ah) |
8a63facc BC |
877 | { |
878 | struct ath5k_buf *bf; | |
d8ee398d | 879 | |
e0d687bd PR |
880 | list_for_each_entry(bf, &ah->txbuf, list) |
881 | ath5k_txbuf_free_skb(ah, bf); | |
882 | list_for_each_entry(bf, &ah->rxbuf, list) | |
883 | ath5k_rxbuf_free_skb(ah, bf); | |
884 | list_for_each_entry(bf, &ah->bcbuf, list) | |
885 | ath5k_txbuf_free_skb(ah, bf); | |
d8ee398d | 886 | |
8a63facc | 887 | /* Free memory associated with all descriptors */ |
e0d687bd PR |
888 | dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); |
889 | ah->desc = NULL; | |
890 | ah->desc_daddr = 0; | |
d8ee398d | 891 | |
e0d687bd PR |
892 | kfree(ah->bufptr); |
893 | ah->bufptr = NULL; | |
fa1c114f JS |
894 | } |
895 | ||
8a63facc BC |
896 | |
897 | /**************\ | |
898 | * Queues setup * | |
899 | \**************/ | |
900 | ||
901 | static struct ath5k_txq * | |
e0d687bd | 902 | ath5k_txq_setup(struct ath5k_hw *ah, |
8a63facc | 903 | int qtype, int subtype) |
fa1c114f | 904 | { |
8a63facc BC |
905 | struct ath5k_txq *txq; |
906 | struct ath5k_txq_info qi = { | |
907 | .tqi_subtype = subtype, | |
de8af455 BR |
908 | /* XXX: default values not correct for B and XR channels, |
909 | * but who cares? */ | |
910 | .tqi_aifs = AR5K_TUNE_AIFS, | |
911 | .tqi_cw_min = AR5K_TUNE_CWMIN, | |
912 | .tqi_cw_max = AR5K_TUNE_CWMAX | |
8a63facc BC |
913 | }; |
914 | int qnum; | |
d8ee398d | 915 | |
e30eb4ab | 916 | /* |
8a63facc BC |
917 | * Enable interrupts only for EOL and DESC conditions. |
918 | * We mark tx descriptors to receive a DESC interrupt | |
919 | * when a tx queue gets deep; otherwise we wait for the | |
920 | * EOL to reap descriptors. Note that this is done to | |
921 | * reduce interrupt load and this only defers reaping | |
922 | * descriptors, never transmitting frames. Aside from | |
923 | * reducing interrupts this also permits more concurrency. | |
924 | * The only potential downside is if the tx queue backs | |
925 | * up in which case the top half of the kernel may backup | |
926 | * due to a lack of tx descriptors. | |
e30eb4ab | 927 | */ |
8a63facc BC |
928 | qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | |
929 | AR5K_TXQ_FLAG_TXDESCINT_ENABLE; | |
930 | qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); | |
931 | if (qnum < 0) { | |
932 | /* | |
933 | * NB: don't print a message, this happens | |
934 | * normally on parts with too few tx queues | |
935 | */ | |
936 | return ERR_PTR(qnum); | |
937 | } | |
e0d687bd | 938 | txq = &ah->txqs[qnum]; |
8a63facc BC |
939 | if (!txq->setup) { |
940 | txq->qnum = qnum; | |
941 | txq->link = NULL; | |
942 | INIT_LIST_HEAD(&txq->q); | |
943 | spin_lock_init(&txq->lock); | |
944 | txq->setup = true; | |
925e0b06 | 945 | txq->txq_len = 0; |
81266baf | 946 | txq->txq_max = ATH5K_TXQ_LEN_MAX; |
4edd761f | 947 | txq->txq_poll_mark = false; |
923e5b3d | 948 | txq->txq_stuck = 0; |
8a63facc | 949 | } |
e0d687bd | 950 | return &ah->txqs[qnum]; |
fa1c114f JS |
951 | } |
952 | ||
8a63facc BC |
953 | static int |
954 | ath5k_beaconq_setup(struct ath5k_hw *ah) | |
fa1c114f | 955 | { |
8a63facc | 956 | struct ath5k_txq_info qi = { |
de8af455 BR |
957 | /* XXX: default values not correct for B and XR channels, |
958 | * but who cares? */ | |
959 | .tqi_aifs = AR5K_TUNE_AIFS, | |
960 | .tqi_cw_min = AR5K_TUNE_CWMIN, | |
961 | .tqi_cw_max = AR5K_TUNE_CWMAX, | |
8a63facc BC |
962 | /* NB: for dynamic turbo, don't enable any other interrupts */ |
963 | .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE | |
964 | }; | |
d8ee398d | 965 | |
8a63facc | 966 | return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); |
fa1c114f JS |
967 | } |
968 | ||
8a63facc | 969 | static int |
e0d687bd | 970 | ath5k_beaconq_config(struct ath5k_hw *ah) |
fa1c114f | 971 | { |
8a63facc BC |
972 | struct ath5k_txq_info qi; |
973 | int ret; | |
fa1c114f | 974 | |
e0d687bd | 975 | ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi); |
8a63facc BC |
976 | if (ret) |
977 | goto err; | |
fa1c114f | 978 | |
e0d687bd PR |
979 | if (ah->opmode == NL80211_IFTYPE_AP || |
980 | ah->opmode == NL80211_IFTYPE_MESH_POINT) { | |
8a63facc BC |
981 | /* |
982 | * Always burst out beacon and CAB traffic | |
983 | * (aifs = cwmin = cwmax = 0) | |
984 | */ | |
985 | qi.tqi_aifs = 0; | |
986 | qi.tqi_cw_min = 0; | |
987 | qi.tqi_cw_max = 0; | |
e0d687bd | 988 | } else if (ah->opmode == NL80211_IFTYPE_ADHOC) { |
8a63facc BC |
989 | /* |
990 | * Adhoc mode; backoff between 0 and (2 * cw_min). | |
991 | */ | |
992 | qi.tqi_aifs = 0; | |
993 | qi.tqi_cw_min = 0; | |
de8af455 | 994 | qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN; |
8a63facc | 995 | } |
fa1c114f | 996 | |
e0d687bd | 997 | ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, |
8a63facc BC |
998 | "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", |
999 | qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); | |
fa1c114f | 1000 | |
e0d687bd | 1001 | ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi); |
8a63facc | 1002 | if (ret) { |
e0d687bd | 1003 | ATH5K_ERR(ah, "%s: unable to update parameters for beacon " |
8a63facc BC |
1004 | "hardware queue!\n", __func__); |
1005 | goto err; | |
1006 | } | |
e0d687bd | 1007 | ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */ |
8a63facc BC |
1008 | if (ret) |
1009 | goto err; | |
b7266047 | 1010 | |
8a63facc BC |
1011 | /* reconfigure cabq with ready time to 80% of beacon_interval */ |
1012 | ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); | |
1013 | if (ret) | |
1014 | goto err; | |
b7266047 | 1015 | |
e0d687bd | 1016 | qi.tqi_ready_time = (ah->bintval * 80) / 100; |
8a63facc BC |
1017 | ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); |
1018 | if (ret) | |
1019 | goto err; | |
b7266047 | 1020 | |
8a63facc BC |
1021 | ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB); |
1022 | err: | |
1023 | return ret; | |
d8ee398d LR |
1024 | } |
1025 | ||
80dac9ee NK |
1026 | /** |
1027 | * ath5k_drain_tx_buffs - Empty tx buffers | |
1028 | * | |
e0d687bd | 1029 | * @ah The &struct ath5k_hw |
80dac9ee NK |
1030 | * |
1031 | * Empty tx buffers from all queues in preparation | |
1032 | * of a reset or during shutdown. | |
1033 | * | |
1034 | * NB: this assumes output has been stopped and | |
1035 | * we do not need to block ath5k_tx_tasklet | |
1036 | */ | |
8a63facc | 1037 | static void |
e0d687bd | 1038 | ath5k_drain_tx_buffs(struct ath5k_hw *ah) |
8a63facc | 1039 | { |
80dac9ee | 1040 | struct ath5k_txq *txq; |
8a63facc | 1041 | struct ath5k_buf *bf, *bf0; |
80dac9ee | 1042 | int i; |
b6ea0356 | 1043 | |
e0d687bd PR |
1044 | for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { |
1045 | if (ah->txqs[i].setup) { | |
1046 | txq = &ah->txqs[i]; | |
80dac9ee NK |
1047 | spin_lock_bh(&txq->lock); |
1048 | list_for_each_entry_safe(bf, bf0, &txq->q, list) { | |
e0d687bd | 1049 | ath5k_debug_printtxbuf(ah, bf); |
b6ea0356 | 1050 | |
e0d687bd | 1051 | ath5k_txbuf_free_skb(ah, bf); |
fa1c114f | 1052 | |
6617942e | 1053 | spin_lock(&ah->txbuflock); |
e0d687bd PR |
1054 | list_move_tail(&bf->list, &ah->txbuf); |
1055 | ah->txbuf_len++; | |
80dac9ee | 1056 | txq->txq_len--; |
6617942e | 1057 | spin_unlock(&ah->txbuflock); |
8a63facc | 1058 | } |
80dac9ee NK |
1059 | txq->link = NULL; |
1060 | txq->txq_poll_mark = false; | |
1061 | spin_unlock_bh(&txq->lock); | |
1062 | } | |
0452d4a5 | 1063 | } |
fa1c114f JS |
1064 | } |
1065 | ||
8a63facc | 1066 | static void |
e0d687bd | 1067 | ath5k_txq_release(struct ath5k_hw *ah) |
2ac2927a | 1068 | { |
e0d687bd | 1069 | struct ath5k_txq *txq = ah->txqs; |
8a63facc | 1070 | unsigned int i; |
2ac2927a | 1071 | |
e0d687bd | 1072 | for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++) |
8a63facc | 1073 | if (txq->setup) { |
e0d687bd | 1074 | ath5k_hw_release_tx_queue(ah, txq->qnum); |
8a63facc BC |
1075 | txq->setup = false; |
1076 | } | |
1077 | } | |
2ac2927a | 1078 | |
2ac2927a | 1079 | |
8a63facc BC |
1080 | /*************\ |
1081 | * RX Handling * | |
1082 | \*************/ | |
2ac2927a | 1083 | |
8a63facc BC |
1084 | /* |
1085 | * Enable the receive h/w following a reset. | |
1086 | */ | |
fa1c114f | 1087 | static int |
e0d687bd | 1088 | ath5k_rx_start(struct ath5k_hw *ah) |
fa1c114f | 1089 | { |
8a63facc BC |
1090 | struct ath_common *common = ath5k_hw_common(ah); |
1091 | struct ath5k_buf *bf; | |
1092 | int ret; | |
fa1c114f | 1093 | |
8a63facc | 1094 | common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz); |
fa1c114f | 1095 | |
e0d687bd | 1096 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", |
8a63facc | 1097 | common->cachelsz, common->rx_bufsize); |
2f7fe870 | 1098 | |
e0d687bd PR |
1099 | spin_lock_bh(&ah->rxbuflock); |
1100 | ah->rxlink = NULL; | |
1101 | list_for_each_entry(bf, &ah->rxbuf, list) { | |
1102 | ret = ath5k_rxbuf_setup(ah, bf); | |
8a63facc | 1103 | if (ret != 0) { |
e0d687bd | 1104 | spin_unlock_bh(&ah->rxbuflock); |
8a63facc BC |
1105 | goto err; |
1106 | } | |
2f7fe870 | 1107 | } |
e0d687bd | 1108 | bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); |
8a63facc | 1109 | ath5k_hw_set_rxdp(ah, bf->daddr); |
e0d687bd | 1110 | spin_unlock_bh(&ah->rxbuflock); |
2f7fe870 | 1111 | |
8a63facc | 1112 | ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ |
e0d687bd | 1113 | ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */ |
8a63facc | 1114 | ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ |
fa1c114f JS |
1115 | |
1116 | return 0; | |
8a63facc | 1117 | err: |
fa1c114f JS |
1118 | return ret; |
1119 | } | |
1120 | ||
8a63facc | 1121 | /* |
80dac9ee NK |
1122 | * Disable the receive logic on PCU (DRU) |
1123 | * In preparation for a shutdown. | |
1124 | * | |
1125 | * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop | |
1126 | * does. | |
8a63facc BC |
1127 | */ |
1128 | static void | |
e0d687bd | 1129 | ath5k_rx_stop(struct ath5k_hw *ah) |
fa1c114f | 1130 | { |
fa1c114f | 1131 | |
8a63facc | 1132 | ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ |
80dac9ee | 1133 | ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ |
fa1c114f | 1134 | |
e0d687bd | 1135 | ath5k_debug_printrxbuffs(ah); |
8a63facc | 1136 | } |
fa1c114f | 1137 | |
8a63facc | 1138 | static unsigned int |
e0d687bd | 1139 | ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb, |
8a63facc BC |
1140 | struct ath5k_rx_status *rs) |
1141 | { | |
8a63facc BC |
1142 | struct ath_common *common = ath5k_hw_common(ah); |
1143 | struct ieee80211_hdr *hdr = (void *)skb->data; | |
1144 | unsigned int keyix, hlen; | |
fa1c114f | 1145 | |
8a63facc BC |
1146 | if (!(rs->rs_status & AR5K_RXERR_DECRYPT) && |
1147 | rs->rs_keyix != AR5K_RXKEYIX_INVALID) | |
1148 | return RX_FLAG_DECRYPTED; | |
fa1c114f | 1149 | |
8a63facc BC |
1150 | /* Apparently when a default key is used to decrypt the packet |
1151 | the hw does not set the index used to decrypt. In such cases | |
1152 | get the index from the packet. */ | |
1153 | hlen = ieee80211_hdrlen(hdr->frame_control); | |
1154 | if (ieee80211_has_protected(hdr->frame_control) && | |
1155 | !(rs->rs_status & AR5K_RXERR_DECRYPT) && | |
1156 | skb->len >= hlen + 4) { | |
1157 | keyix = skb->data[hlen + 3] >> 6; | |
1158 | ||
1159 | if (test_bit(keyix, common->keymap)) | |
1160 | return RX_FLAG_DECRYPTED; | |
1161 | } | |
fa1c114f JS |
1162 | |
1163 | return 0; | |
fa1c114f JS |
1164 | } |
1165 | ||
8a63facc | 1166 | |
fa1c114f | 1167 | static void |
e0d687bd | 1168 | ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb, |
8a63facc | 1169 | struct ieee80211_rx_status *rxs) |
fa1c114f | 1170 | { |
e0d687bd | 1171 | struct ath_common *common = ath5k_hw_common(ah); |
8a63facc BC |
1172 | u64 tsf, bc_tstamp; |
1173 | u32 hw_tu; | |
1174 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; | |
fa1c114f | 1175 | |
8a63facc BC |
1176 | if (ieee80211_is_beacon(mgmt->frame_control) && |
1177 | le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS && | |
2e42e474 | 1178 | ether_addr_equal(mgmt->bssid, common->curbssid)) { |
8a63facc BC |
1179 | /* |
1180 | * Received an IBSS beacon with the same BSSID. Hardware *must* | |
1181 | * have updated the local TSF. We have to work around various | |
1182 | * hardware bugs, though... | |
1183 | */ | |
e0d687bd | 1184 | tsf = ath5k_hw_get_tsf64(ah); |
8a63facc BC |
1185 | bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); |
1186 | hw_tu = TSF_TO_TU(tsf); | |
fa1c114f | 1187 | |
e0d687bd | 1188 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, |
8a63facc BC |
1189 | "beacon %llx mactime %llx (diff %lld) tsf now %llx\n", |
1190 | (unsigned long long)bc_tstamp, | |
1191 | (unsigned long long)rxs->mactime, | |
1192 | (unsigned long long)(rxs->mactime - bc_tstamp), | |
1193 | (unsigned long long)tsf); | |
fa1c114f | 1194 | |
8a63facc BC |
1195 | /* |
1196 | * Sometimes the HW will give us a wrong tstamp in the rx | |
1197 | * status, causing the timestamp extension to go wrong. | |
1198 | * (This seems to happen especially with beacon frames bigger | |
1199 | * than 78 byte (incl. FCS)) | |
1200 | * But we know that the receive timestamp must be later than the | |
1201 | * timestamp of the beacon since HW must have synced to that. | |
1202 | * | |
1203 | * NOTE: here we assume mactime to be after the frame was | |
1204 | * received, not like mac80211 which defines it at the start. | |
1205 | */ | |
1206 | if (bc_tstamp > rxs->mactime) { | |
e0d687bd | 1207 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, |
8a63facc BC |
1208 | "fixing mactime from %llx to %llx\n", |
1209 | (unsigned long long)rxs->mactime, | |
1210 | (unsigned long long)tsf); | |
1211 | rxs->mactime = tsf; | |
1212 | } | |
fa1c114f | 1213 | |
8a63facc BC |
1214 | /* |
1215 | * Local TSF might have moved higher than our beacon timers, | |
1216 | * in that case we have to update them to continue sending | |
1217 | * beacons. This also takes care of synchronizing beacon sending | |
1218 | * times with other stations. | |
1219 | */ | |
e0d687bd PR |
1220 | if (hw_tu >= ah->nexttbtt) |
1221 | ath5k_beacon_update_timers(ah, bc_tstamp); | |
7f896126 BR |
1222 | |
1223 | /* Check if the beacon timers are still correct, because a TSF | |
1224 | * update might have created a window between them - for a | |
1225 | * longer description see the comment of this function: */ | |
e0d687bd PR |
1226 | if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) { |
1227 | ath5k_beacon_update_timers(ah, bc_tstamp); | |
1228 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, | |
7f896126 BR |
1229 | "fixed beacon timers after beacon receive\n"); |
1230 | } | |
8a63facc BC |
1231 | } |
1232 | } | |
fa1c114f | 1233 | |
8a63facc | 1234 | static void |
e0d687bd | 1235 | ath5k_update_beacon_rssi(struct ath5k_hw *ah, struct sk_buff *skb, int rssi) |
8a63facc BC |
1236 | { |
1237 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; | |
8a63facc | 1238 | struct ath_common *common = ath5k_hw_common(ah); |
fa1c114f | 1239 | |
8a63facc BC |
1240 | /* only beacons from our BSSID */ |
1241 | if (!ieee80211_is_beacon(mgmt->frame_control) || | |
2e42e474 | 1242 | !ether_addr_equal(mgmt->bssid, common->curbssid)) |
8a63facc | 1243 | return; |
fa1c114f | 1244 | |
eef39bef | 1245 | ewma_add(&ah->ah_beacon_rssi_avg, rssi); |
fa1c114f | 1246 | |
8a63facc BC |
1247 | /* in IBSS mode we should keep RSSI statistics per neighbour */ |
1248 | /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */ | |
1249 | } | |
fa1c114f | 1250 | |
8a63facc BC |
1251 | /* |
1252 | * Compute padding position. skb must contain an IEEE 802.11 frame | |
1253 | */ | |
1254 | static int ath5k_common_padpos(struct sk_buff *skb) | |
fa1c114f | 1255 | { |
e4bbf2f5 | 1256 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
8a63facc BC |
1257 | __le16 frame_control = hdr->frame_control; |
1258 | int padpos = 24; | |
fa1c114f | 1259 | |
d2c7f773 | 1260 | if (ieee80211_has_a4(frame_control)) |
8a63facc | 1261 | padpos += ETH_ALEN; |
d2c7f773 PR |
1262 | |
1263 | if (ieee80211_is_data_qos(frame_control)) | |
8a63facc | 1264 | padpos += IEEE80211_QOS_CTL_LEN; |
8a63facc BC |
1265 | |
1266 | return padpos; | |
fa1c114f JS |
1267 | } |
1268 | ||
8a63facc BC |
1269 | /* |
1270 | * This function expects an 802.11 frame and returns the number of | |
1271 | * bytes added, or -1 if we don't have enough header room. | |
1272 | */ | |
1273 | static int ath5k_add_padding(struct sk_buff *skb) | |
fa1c114f | 1274 | { |
8a63facc BC |
1275 | int padpos = ath5k_common_padpos(skb); |
1276 | int padsize = padpos & 3; | |
fa1c114f | 1277 | |
e4bbf2f5 | 1278 | if (padsize && skb->len > padpos) { |
fa1c114f | 1279 | |
8a63facc BC |
1280 | if (skb_headroom(skb) < padsize) |
1281 | return -1; | |
fa1c114f | 1282 | |
8a63facc | 1283 | skb_push(skb, padsize); |
e4bbf2f5 | 1284 | memmove(skb->data, skb->data + padsize, padpos); |
8a63facc BC |
1285 | return padsize; |
1286 | } | |
a951ae21 | 1287 | |
8a63facc BC |
1288 | return 0; |
1289 | } | |
fa1c114f | 1290 | |
8a63facc BC |
1291 | /* |
1292 | * The MAC header is padded to have 32-bit boundary if the | |
1293 | * packet payload is non-zero. The general calculation for | |
1294 | * padsize would take into account odd header lengths: | |
1295 | * padsize = 4 - (hdrlen & 3); however, since only | |
1296 | * even-length headers are used, padding can only be 0 or 2 | |
1297 | * bytes and we can optimize this a bit. We must not try to | |
1298 | * remove padding from short control frames that do not have a | |
1299 | * payload. | |
1300 | * | |
1301 | * This function expects an 802.11 frame and returns the number of | |
1302 | * bytes removed. | |
1303 | */ | |
1304 | static int ath5k_remove_padding(struct sk_buff *skb) | |
1305 | { | |
1306 | int padpos = ath5k_common_padpos(skb); | |
1307 | int padsize = padpos & 3; | |
6d91e1d8 | 1308 | |
e4bbf2f5 | 1309 | if (padsize && skb->len >= padpos + padsize) { |
8a63facc BC |
1310 | memmove(skb->data + padsize, skb->data, padpos); |
1311 | skb_pull(skb, padsize); | |
1312 | return padsize; | |
fa1c114f | 1313 | } |
a951ae21 | 1314 | |
8a63facc | 1315 | return 0; |
fa1c114f JS |
1316 | } |
1317 | ||
1318 | static void | |
e0d687bd | 1319 | ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb, |
8a63facc | 1320 | struct ath5k_rx_status *rs) |
fa1c114f | 1321 | { |
8a63facc BC |
1322 | struct ieee80211_rx_status *rxs; |
1323 | ||
1324 | ath5k_remove_padding(skb); | |
1325 | ||
1326 | rxs = IEEE80211_SKB_RXCB(skb); | |
1327 | ||
1328 | rxs->flag = 0; | |
1329 | if (unlikely(rs->rs_status & AR5K_RXERR_MIC)) | |
1330 | rxs->flag |= RX_FLAG_MMIC_ERROR; | |
fa1c114f JS |
1331 | |
1332 | /* | |
8a63facc BC |
1333 | * always extend the mac timestamp, since this information is |
1334 | * also needed for proper IBSS merging. | |
1335 | * | |
1336 | * XXX: it might be too late to do it here, since rs_tstamp is | |
1337 | * 15bit only. that means TSF extension has to be done within | |
1338 | * 32768usec (about 32ms). it might be necessary to move this to | |
1339 | * the interrupt handler, like it is done in madwifi. | |
fa1c114f | 1340 | */ |
e0d687bd | 1341 | rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp); |
e576defd | 1342 | rxs->flag |= RX_FLAG_MACTIME_END; |
fa1c114f | 1343 | |
e0d687bd PR |
1344 | rxs->freq = ah->curchan->center_freq; |
1345 | rxs->band = ah->curchan->band; | |
fa1c114f | 1346 | |
e0d687bd | 1347 | rxs->signal = ah->ah_noise_floor + rs->rs_rssi; |
fa1c114f | 1348 | |
8a63facc | 1349 | rxs->antenna = rs->rs_antenna; |
fa1c114f | 1350 | |
8a63facc | 1351 | if (rs->rs_antenna > 0 && rs->rs_antenna < 5) |
e0d687bd | 1352 | ah->stats.antenna_rx[rs->rs_antenna]++; |
8a63facc | 1353 | else |
e0d687bd | 1354 | ah->stats.antenna_rx[0]++; /* invalid */ |
fa1c114f | 1355 | |
e0d687bd PR |
1356 | rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate); |
1357 | rxs->flag |= ath5k_rx_decrypted(ah, skb, rs); | |
fa1c114f | 1358 | |
8a63facc | 1359 | if (rxs->rate_idx >= 0 && rs->rs_rate == |
e0d687bd | 1360 | ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short) |
8a63facc | 1361 | rxs->flag |= RX_FLAG_SHORTPRE; |
fa1c114f | 1362 | |
e0d687bd | 1363 | trace_ath5k_rx(ah, skb); |
fa1c114f | 1364 | |
e0d687bd | 1365 | ath5k_update_beacon_rssi(ah, skb, rs->rs_rssi); |
fa1c114f | 1366 | |
8a63facc | 1367 | /* check beacons in IBSS mode */ |
e0d687bd PR |
1368 | if (ah->opmode == NL80211_IFTYPE_ADHOC) |
1369 | ath5k_check_ibss_tsf(ah, skb, rxs); | |
fa1c114f | 1370 | |
e0d687bd | 1371 | ieee80211_rx(ah->hw, skb); |
8a63facc | 1372 | } |
fa1c114f | 1373 | |
8a63facc BC |
1374 | /** ath5k_frame_receive_ok() - Do we want to receive this frame or not? |
1375 | * | |
1376 | * Check if we want to further process this frame or not. Also update | |
1377 | * statistics. Return true if we want this frame, false if not. | |
fa1c114f | 1378 | */ |
8a63facc | 1379 | static bool |
e0d687bd | 1380 | ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs) |
fa1c114f | 1381 | { |
e0d687bd PR |
1382 | ah->stats.rx_all_count++; |
1383 | ah->stats.rx_bytes_count += rs->rs_datalen; | |
fa1c114f | 1384 | |
8a63facc BC |
1385 | if (unlikely(rs->rs_status)) { |
1386 | if (rs->rs_status & AR5K_RXERR_CRC) | |
e0d687bd | 1387 | ah->stats.rxerr_crc++; |
8a63facc | 1388 | if (rs->rs_status & AR5K_RXERR_FIFO) |
e0d687bd | 1389 | ah->stats.rxerr_fifo++; |
8a63facc | 1390 | if (rs->rs_status & AR5K_RXERR_PHY) { |
e0d687bd | 1391 | ah->stats.rxerr_phy++; |
8a63facc | 1392 | if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32) |
e0d687bd | 1393 | ah->stats.rxerr_phy_code[rs->rs_phyerr]++; |
8a63facc BC |
1394 | return false; |
1395 | } | |
1396 | if (rs->rs_status & AR5K_RXERR_DECRYPT) { | |
1397 | /* | |
1398 | * Decrypt error. If the error occurred | |
1399 | * because there was no hardware key, then | |
1400 | * let the frame through so the upper layers | |
1401 | * can process it. This is necessary for 5210 | |
1402 | * parts which have no way to setup a ``clear'' | |
1403 | * key cache entry. | |
1404 | * | |
1405 | * XXX do key cache faulting | |
1406 | */ | |
e0d687bd | 1407 | ah->stats.rxerr_decrypt++; |
8a63facc BC |
1408 | if (rs->rs_keyix == AR5K_RXKEYIX_INVALID && |
1409 | !(rs->rs_status & AR5K_RXERR_CRC)) | |
1410 | return true; | |
1411 | } | |
1412 | if (rs->rs_status & AR5K_RXERR_MIC) { | |
e0d687bd | 1413 | ah->stats.rxerr_mic++; |
8a63facc | 1414 | return true; |
fa1c114f | 1415 | } |
fa1c114f | 1416 | |
8a63facc BC |
1417 | /* reject any frames with non-crypto errors */ |
1418 | if (rs->rs_status & ~(AR5K_RXERR_DECRYPT)) | |
1419 | return false; | |
1420 | } | |
fa1c114f | 1421 | |
8a63facc | 1422 | if (unlikely(rs->rs_more)) { |
e0d687bd | 1423 | ah->stats.rxerr_jumbo++; |
8a63facc BC |
1424 | return false; |
1425 | } | |
1426 | return true; | |
fa1c114f JS |
1427 | } |
1428 | ||
c266c71a | 1429 | static void |
e0d687bd | 1430 | ath5k_set_current_imask(struct ath5k_hw *ah) |
c266c71a | 1431 | { |
4fc5401c | 1432 | enum ath5k_int imask; |
c266c71a FF |
1433 | unsigned long flags; |
1434 | ||
e0d687bd PR |
1435 | spin_lock_irqsave(&ah->irqlock, flags); |
1436 | imask = ah->imask; | |
1437 | if (ah->rx_pending) | |
c266c71a | 1438 | imask &= ~AR5K_INT_RX_ALL; |
e0d687bd | 1439 | if (ah->tx_pending) |
c266c71a | 1440 | imask &= ~AR5K_INT_TX_ALL; |
e0d687bd PR |
1441 | ath5k_hw_set_imr(ah, imask); |
1442 | spin_unlock_irqrestore(&ah->irqlock, flags); | |
c266c71a FF |
1443 | } |
1444 | ||
fa1c114f | 1445 | static void |
8a63facc | 1446 | ath5k_tasklet_rx(unsigned long data) |
fa1c114f | 1447 | { |
8a63facc BC |
1448 | struct ath5k_rx_status rs = {}; |
1449 | struct sk_buff *skb, *next_skb; | |
1450 | dma_addr_t next_skb_addr; | |
e0d687bd | 1451 | struct ath5k_hw *ah = (void *)data; |
dc1e001b | 1452 | struct ath_common *common = ath5k_hw_common(ah); |
8a63facc BC |
1453 | struct ath5k_buf *bf; |
1454 | struct ath5k_desc *ds; | |
1455 | int ret; | |
fa1c114f | 1456 | |
e0d687bd PR |
1457 | spin_lock(&ah->rxbuflock); |
1458 | if (list_empty(&ah->rxbuf)) { | |
1459 | ATH5K_WARN(ah, "empty rx buf pool\n"); | |
8a63facc BC |
1460 | goto unlock; |
1461 | } | |
1462 | do { | |
e0d687bd | 1463 | bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); |
8a63facc BC |
1464 | BUG_ON(bf->skb == NULL); |
1465 | skb = bf->skb; | |
1466 | ds = bf->desc; | |
fa1c114f | 1467 | |
8a63facc | 1468 | /* bail if HW is still using self-linked descriptor */ |
e0d687bd | 1469 | if (ath5k_hw_get_rxdp(ah) == bf->daddr) |
8a63facc | 1470 | break; |
fa1c114f | 1471 | |
e0d687bd | 1472 | ret = ah->ah_proc_rx_desc(ah, ds, &rs); |
8a63facc BC |
1473 | if (unlikely(ret == -EINPROGRESS)) |
1474 | break; | |
1475 | else if (unlikely(ret)) { | |
e0d687bd PR |
1476 | ATH5K_ERR(ah, "error in processing rx descriptor\n"); |
1477 | ah->stats.rxerr_proc++; | |
8a63facc BC |
1478 | break; |
1479 | } | |
fa1c114f | 1480 | |
e0d687bd PR |
1481 | if (ath5k_receive_frame_ok(ah, &rs)) { |
1482 | next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr); | |
fa1c114f | 1483 | |
8a63facc BC |
1484 | /* |
1485 | * If we can't replace bf->skb with a new skb under | |
1486 | * memory pressure, just skip this packet | |
1487 | */ | |
1488 | if (!next_skb) | |
1489 | goto next; | |
036cd1ec | 1490 | |
e0d687bd | 1491 | dma_unmap_single(ah->dev, bf->skbaddr, |
8a63facc | 1492 | common->rx_bufsize, |
aeae4ac9 | 1493 | DMA_FROM_DEVICE); |
036cd1ec | 1494 | |
8a63facc | 1495 | skb_put(skb, rs.rs_datalen); |
6ba81c2c | 1496 | |
e0d687bd | 1497 | ath5k_receive_frame(ah, skb, &rs); |
6ba81c2c | 1498 | |
8a63facc BC |
1499 | bf->skb = next_skb; |
1500 | bf->skbaddr = next_skb_addr; | |
036cd1ec | 1501 | } |
8a63facc | 1502 | next: |
e0d687bd PR |
1503 | list_move_tail(&bf->list, &ah->rxbuf); |
1504 | } while (ath5k_rxbuf_setup(ah, bf) == 0); | |
8a63facc | 1505 | unlock: |
e0d687bd PR |
1506 | spin_unlock(&ah->rxbuflock); |
1507 | ah->rx_pending = false; | |
1508 | ath5k_set_current_imask(ah); | |
036cd1ec BR |
1509 | } |
1510 | ||
b4ea449d | 1511 | |
8a63facc BC |
1512 | /*************\ |
1513 | * TX Handling * | |
1514 | \*************/ | |
b4ea449d | 1515 | |
7bb45683 | 1516 | void |
cd2c5486 BR |
1517 | ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, |
1518 | struct ath5k_txq *txq) | |
8a63facc | 1519 | { |
e0d687bd | 1520 | struct ath5k_hw *ah = hw->priv; |
8a63facc BC |
1521 | struct ath5k_buf *bf; |
1522 | unsigned long flags; | |
1523 | int padsize; | |
b4ea449d | 1524 | |
e0d687bd | 1525 | trace_ath5k_tx(ah, skb, txq); |
b4ea449d | 1526 | |
8a63facc BC |
1527 | /* |
1528 | * The hardware expects the header padded to 4 byte boundaries. | |
1529 | * If this is not the case, we add the padding after the header. | |
1530 | */ | |
1531 | padsize = ath5k_add_padding(skb); | |
1532 | if (padsize < 0) { | |
e0d687bd | 1533 | ATH5K_ERR(ah, "tx hdrlen not %%4: not enough" |
8a63facc BC |
1534 | " headroom to pad"); |
1535 | goto drop_packet; | |
1536 | } | |
8127fbdc | 1537 | |
4e868796 FF |
1538 | if (txq->txq_len >= txq->txq_max && |
1539 | txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX) | |
925e0b06 BR |
1540 | ieee80211_stop_queue(hw, txq->qnum); |
1541 | ||
e0d687bd PR |
1542 | spin_lock_irqsave(&ah->txbuflock, flags); |
1543 | if (list_empty(&ah->txbuf)) { | |
1544 | ATH5K_ERR(ah, "no further txbuf available, dropping packet\n"); | |
1545 | spin_unlock_irqrestore(&ah->txbuflock, flags); | |
651d9375 | 1546 | ieee80211_stop_queues(hw); |
8a63facc | 1547 | goto drop_packet; |
8127fbdc | 1548 | } |
e0d687bd | 1549 | bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list); |
8a63facc | 1550 | list_del(&bf->list); |
e0d687bd PR |
1551 | ah->txbuf_len--; |
1552 | if (list_empty(&ah->txbuf)) | |
8a63facc | 1553 | ieee80211_stop_queues(hw); |
e0d687bd | 1554 | spin_unlock_irqrestore(&ah->txbuflock, flags); |
8a63facc BC |
1555 | |
1556 | bf->skb = skb; | |
1557 | ||
e0d687bd | 1558 | if (ath5k_txbuf_setup(ah, bf, txq, padsize)) { |
8a63facc | 1559 | bf->skb = NULL; |
e0d687bd PR |
1560 | spin_lock_irqsave(&ah->txbuflock, flags); |
1561 | list_add_tail(&bf->list, &ah->txbuf); | |
1562 | ah->txbuf_len++; | |
1563 | spin_unlock_irqrestore(&ah->txbuflock, flags); | |
8a63facc | 1564 | goto drop_packet; |
8127fbdc | 1565 | } |
7bb45683 | 1566 | return; |
8127fbdc | 1567 | |
8a63facc | 1568 | drop_packet: |
596ab5ec | 1569 | ieee80211_free_txskb(hw, skb); |
8127fbdc BP |
1570 | } |
1571 | ||
1440401e | 1572 | static void |
e0d687bd | 1573 | ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb, |
0e472252 | 1574 | struct ath5k_txq *txq, struct ath5k_tx_status *ts) |
1440401e BR |
1575 | { |
1576 | struct ieee80211_tx_info *info; | |
ed895085 | 1577 | u8 tries[3]; |
1440401e BR |
1578 | int i; |
1579 | ||
e0d687bd PR |
1580 | ah->stats.tx_all_count++; |
1581 | ah->stats.tx_bytes_count += skb->len; | |
1440401e BR |
1582 | info = IEEE80211_SKB_CB(skb); |
1583 | ||
ed895085 FF |
1584 | tries[0] = info->status.rates[0].count; |
1585 | tries[1] = info->status.rates[1].count; | |
1586 | tries[2] = info->status.rates[2].count; | |
1587 | ||
1440401e | 1588 | ieee80211_tx_info_clear_status(info); |
ed895085 FF |
1589 | |
1590 | for (i = 0; i < ts->ts_final_idx; i++) { | |
1440401e BR |
1591 | struct ieee80211_tx_rate *r = |
1592 | &info->status.rates[i]; | |
1593 | ||
ed895085 | 1594 | r->count = tries[i]; |
1440401e BR |
1595 | } |
1596 | ||
ed895085 | 1597 | info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry; |
6d7b97b2 | 1598 | info->status.rates[ts->ts_final_idx + 1].idx = -1; |
1440401e BR |
1599 | |
1600 | if (unlikely(ts->ts_status)) { | |
e0d687bd | 1601 | ah->stats.ack_fail++; |
1440401e BR |
1602 | if (ts->ts_status & AR5K_TXERR_FILT) { |
1603 | info->flags |= IEEE80211_TX_STAT_TX_FILTERED; | |
e0d687bd | 1604 | ah->stats.txerr_filt++; |
1440401e BR |
1605 | } |
1606 | if (ts->ts_status & AR5K_TXERR_XRETRY) | |
e0d687bd | 1607 | ah->stats.txerr_retry++; |
1440401e | 1608 | if (ts->ts_status & AR5K_TXERR_FIFO) |
e0d687bd | 1609 | ah->stats.txerr_fifo++; |
1440401e BR |
1610 | } else { |
1611 | info->flags |= IEEE80211_TX_STAT_ACK; | |
1612 | info->status.ack_signal = ts->ts_rssi; | |
6d7b97b2 FF |
1613 | |
1614 | /* count the successful attempt as well */ | |
1615 | info->status.rates[ts->ts_final_idx].count++; | |
1440401e BR |
1616 | } |
1617 | ||
1618 | /* | |
1619 | * Remove MAC header padding before giving the frame | |
1620 | * back to mac80211. | |
1621 | */ | |
1622 | ath5k_remove_padding(skb); | |
1623 | ||
1624 | if (ts->ts_antenna > 0 && ts->ts_antenna < 5) | |
e0d687bd | 1625 | ah->stats.antenna_tx[ts->ts_antenna]++; |
1440401e | 1626 | else |
e0d687bd | 1627 | ah->stats.antenna_tx[0]++; /* invalid */ |
1440401e | 1628 | |
e0d687bd PR |
1629 | trace_ath5k_tx_complete(ah, skb, txq, ts); |
1630 | ieee80211_tx_status(ah->hw, skb); | |
1440401e | 1631 | } |
8a63facc BC |
1632 | |
1633 | static void | |
e0d687bd | 1634 | ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq) |
8127fbdc | 1635 | { |
8a63facc BC |
1636 | struct ath5k_tx_status ts = {}; |
1637 | struct ath5k_buf *bf, *bf0; | |
1638 | struct ath5k_desc *ds; | |
1639 | struct sk_buff *skb; | |
1440401e | 1640 | int ret; |
8127fbdc | 1641 | |
8a63facc BC |
1642 | spin_lock(&txq->lock); |
1643 | list_for_each_entry_safe(bf, bf0, &txq->q, list) { | |
23413296 BR |
1644 | |
1645 | txq->txq_poll_mark = false; | |
1646 | ||
1647 | /* skb might already have been processed last time. */ | |
1648 | if (bf->skb != NULL) { | |
1649 | ds = bf->desc; | |
1650 | ||
e0d687bd | 1651 | ret = ah->ah_proc_tx_desc(ah, ds, &ts); |
23413296 BR |
1652 | if (unlikely(ret == -EINPROGRESS)) |
1653 | break; | |
1654 | else if (unlikely(ret)) { | |
e0d687bd | 1655 | ATH5K_ERR(ah, |
23413296 BR |
1656 | "error %d while processing " |
1657 | "queue %u\n", ret, txq->qnum); | |
1658 | break; | |
1659 | } | |
1660 | ||
1661 | skb = bf->skb; | |
1662 | bf->skb = NULL; | |
aeae4ac9 | 1663 | |
e0d687bd | 1664 | dma_unmap_single(ah->dev, bf->skbaddr, skb->len, |
aeae4ac9 | 1665 | DMA_TO_DEVICE); |
e0d687bd | 1666 | ath5k_tx_frame_completed(ah, skb, txq, &ts); |
23413296 | 1667 | } |
8127fbdc | 1668 | |
8a63facc BC |
1669 | /* |
1670 | * It's possible that the hardware can say the buffer is | |
1671 | * completed when it hasn't yet loaded the ds_link from | |
23413296 BR |
1672 | * host memory and moved on. |
1673 | * Always keep the last descriptor to avoid HW races... | |
8a63facc | 1674 | */ |
e0d687bd PR |
1675 | if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) { |
1676 | spin_lock(&ah->txbuflock); | |
1677 | list_move_tail(&bf->list, &ah->txbuf); | |
1678 | ah->txbuf_len++; | |
23413296 | 1679 | txq->txq_len--; |
e0d687bd | 1680 | spin_unlock(&ah->txbuflock); |
8a63facc | 1681 | } |
fa1c114f | 1682 | } |
fa1c114f | 1683 | spin_unlock(&txq->lock); |
4198a8d0 | 1684 | if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4) |
e0d687bd | 1685 | ieee80211_wake_queue(ah->hw, txq->qnum); |
fa1c114f JS |
1686 | } |
1687 | ||
1688 | static void | |
1689 | ath5k_tasklet_tx(unsigned long data) | |
1690 | { | |
8784d2ee | 1691 | int i; |
e0d687bd | 1692 | struct ath5k_hw *ah = (void *)data; |
fa1c114f | 1693 | |
e4bbf2f5 | 1694 | for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) |
7ff7c82e | 1695 | if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i))) |
e0d687bd | 1696 | ath5k_tx_processq(ah, &ah->txqs[i]); |
c266c71a | 1697 | |
e0d687bd PR |
1698 | ah->tx_pending = false; |
1699 | ath5k_set_current_imask(ah); | |
fa1c114f JS |
1700 | } |
1701 | ||
1702 | ||
fa1c114f JS |
1703 | /*****************\ |
1704 | * Beacon handling * | |
1705 | \*****************/ | |
1706 | ||
1707 | /* | |
1708 | * Setup the beacon frame for transmit. | |
1709 | */ | |
1710 | static int | |
e0d687bd | 1711 | ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) |
fa1c114f JS |
1712 | { |
1713 | struct sk_buff *skb = bf->skb; | |
a888d52d | 1714 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
fa1c114f | 1715 | struct ath5k_desc *ds; |
2bed03eb NK |
1716 | int ret = 0; |
1717 | u8 antenna; | |
fa1c114f | 1718 | u32 flags; |
8127fbdc | 1719 | const int padsize = 0; |
fa1c114f | 1720 | |
e0d687bd | 1721 | bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, |
aeae4ac9 | 1722 | DMA_TO_DEVICE); |
e0d687bd | 1723 | ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " |
fa1c114f JS |
1724 | "skbaddr %llx\n", skb, skb->data, skb->len, |
1725 | (unsigned long long)bf->skbaddr); | |
aeae4ac9 | 1726 | |
e0d687bd PR |
1727 | if (dma_mapping_error(ah->dev, bf->skbaddr)) { |
1728 | ATH5K_ERR(ah, "beacon DMA mapping failed\n"); | |
bdc71bc5 BC |
1729 | dev_kfree_skb_any(skb); |
1730 | bf->skb = NULL; | |
fa1c114f JS |
1731 | return -EIO; |
1732 | } | |
1733 | ||
1734 | ds = bf->desc; | |
2bed03eb | 1735 | antenna = ah->ah_tx_ant; |
fa1c114f JS |
1736 | |
1737 | flags = AR5K_TXDESC_NOACK; | |
e0d687bd | 1738 | if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { |
fa1c114f JS |
1739 | ds->ds_link = bf->daddr; /* self-linked */ |
1740 | flags |= AR5K_TXDESC_VEOL; | |
2bed03eb | 1741 | } else |
fa1c114f | 1742 | ds->ds_link = 0; |
2bed03eb NK |
1743 | |
1744 | /* | |
1745 | * If we use multiple antennas on AP and use | |
1746 | * the Sectored AP scenario, switch antenna every | |
1747 | * 4 beacons to make sure everybody hears our AP. | |
1748 | * When a client tries to associate, hw will keep | |
1749 | * track of the tx antenna to be used for this client | |
6a2a0e73 | 1750 | * automatically, based on ACKed packets. |
2bed03eb NK |
1751 | * |
1752 | * Note: AP still listens and transmits RTS on the | |
1753 | * default antenna which is supposed to be an omni. | |
1754 | * | |
1755 | * Note2: On sectored scenarios it's possible to have | |
a180a130 BC |
1756 | * multiple antennas (1 omni -- the default -- and 14 |
1757 | * sectors), so if we choose to actually support this | |
1758 | * mode, we need to allow the user to set how many antennas | |
1759 | * we have and tweak the code below to send beacons | |
1760 | * on all of them. | |
2bed03eb NK |
1761 | */ |
1762 | if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) | |
e0d687bd | 1763 | antenna = ah->bsent & 4 ? 2 : 1; |
2bed03eb | 1764 | |
fa1c114f | 1765 | |
8f655dde NK |
1766 | /* FIXME: If we are in g mode and rate is a CCK rate |
1767 | * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta | |
1768 | * from tx power (value is in dB units already) */ | |
fa1c114f | 1769 | ds->ds_data = bf->skbaddr; |
281c56dd | 1770 | ret = ah->ah_setup_tx_desc(ah, ds, skb->len, |
8127fbdc | 1771 | ieee80211_get_hdrlen_from_skb(skb), padsize, |
987af54f NK |
1772 | AR5K_PKT_TYPE_BEACON, |
1773 | (ah->ah_txpower.txp_requested * 2), | |
e0d687bd | 1774 | ieee80211_get_tx_rate(ah->hw, info)->hw_value, |
2e92e6f2 | 1775 | 1, AR5K_TXKEYIX_INVALID, |
400ec45a | 1776 | antenna, flags, 0, 0); |
fa1c114f JS |
1777 | if (ret) |
1778 | goto err_unmap; | |
1779 | ||
1780 | return 0; | |
1781 | err_unmap: | |
e0d687bd | 1782 | dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); |
fa1c114f JS |
1783 | return ret; |
1784 | } | |
1785 | ||
8a63facc BC |
1786 | /* |
1787 | * Updates the beacon that is sent by ath5k_beacon_send. For adhoc, | |
1788 | * this is called only once at config_bss time, for AP we do it every | |
1789 | * SWBA interrupt so that the TIM will reflect buffered frames. | |
1790 | * | |
1791 | * Called with the beacon lock. | |
1792 | */ | |
cd2c5486 | 1793 | int |
8a63facc BC |
1794 | ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
1795 | { | |
1796 | int ret; | |
e0d687bd | 1797 | struct ath5k_hw *ah = hw->priv; |
9c371f99 | 1798 | struct ath5k_vif *avf; |
8a63facc BC |
1799 | struct sk_buff *skb; |
1800 | ||
1801 | if (WARN_ON(!vif)) { | |
1802 | ret = -EINVAL; | |
1803 | goto out; | |
1804 | } | |
1805 | ||
1806 | skb = ieee80211_beacon_get(hw, vif); | |
1807 | ||
1808 | if (!skb) { | |
1809 | ret = -ENOMEM; | |
1810 | goto out; | |
1811 | } | |
1812 | ||
9c371f99 | 1813 | avf = (void *)vif->drv_priv; |
e0d687bd | 1814 | ath5k_txbuf_free_skb(ah, avf->bbuf); |
b1ae1edf | 1815 | avf->bbuf->skb = skb; |
e0d687bd | 1816 | ret = ath5k_beacon_setup(ah, avf->bbuf); |
8a63facc BC |
1817 | out: |
1818 | return ret; | |
1819 | } | |
1820 | ||
fa1c114f JS |
1821 | /* |
1822 | * Transmit a beacon frame at SWBA. Dynamic updates to the | |
1823 | * frame contents are done as needed and the slot time is | |
1824 | * also adjusted based on current state. | |
1825 | * | |
5faaff74 BC |
1826 | * This is called from software irq context (beacontq tasklets) |
1827 | * or user context from ath5k_beacon_config. | |
fa1c114f JS |
1828 | */ |
1829 | static void | |
e0d687bd | 1830 | ath5k_beacon_send(struct ath5k_hw *ah) |
fa1c114f | 1831 | { |
b1ae1edf BG |
1832 | struct ieee80211_vif *vif; |
1833 | struct ath5k_vif *avf; | |
1834 | struct ath5k_buf *bf; | |
cec8db23 | 1835 | struct sk_buff *skb; |
bdc71bc5 | 1836 | int err; |
fa1c114f | 1837 | |
e0d687bd | 1838 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n"); |
fa1c114f | 1839 | |
fa1c114f JS |
1840 | /* |
1841 | * Check if the previous beacon has gone out. If | |
a180a130 | 1842 | * not, don't don't try to post another: skip this |
fa1c114f JS |
1843 | * period and wait for the next. Missed beacons |
1844 | * indicate a problem and should not occur. If we | |
1845 | * miss too many consecutive beacons reset the device. | |
1846 | */ | |
e0d687bd PR |
1847 | if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) { |
1848 | ah->bmisscount++; | |
1849 | ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, | |
1850 | "missed %u consecutive beacons\n", ah->bmisscount); | |
1851 | if (ah->bmisscount > 10) { /* NB: 10 is a guess */ | |
1852 | ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, | |
fa1c114f | 1853 | "stuck beacon time (%u missed)\n", |
e0d687bd PR |
1854 | ah->bmisscount); |
1855 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, | |
8d67a031 | 1856 | "stuck beacon, resetting\n"); |
e0d687bd | 1857 | ieee80211_queue_work(ah->hw, &ah->reset_work); |
fa1c114f JS |
1858 | } |
1859 | return; | |
1860 | } | |
e0d687bd PR |
1861 | if (unlikely(ah->bmisscount != 0)) { |
1862 | ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, | |
fa1c114f | 1863 | "resume beacon xmit after %u misses\n", |
e0d687bd PR |
1864 | ah->bmisscount); |
1865 | ah->bmisscount = 0; | |
fa1c114f JS |
1866 | } |
1867 | ||
da473b61 CYY |
1868 | if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs + |
1869 | ah->num_mesh_vifs > 1) || | |
e0d687bd | 1870 | ah->opmode == NL80211_IFTYPE_MESH_POINT) { |
b1ae1edf BG |
1871 | u64 tsf = ath5k_hw_get_tsf64(ah); |
1872 | u32 tsftu = TSF_TO_TU(tsf); | |
e0d687bd PR |
1873 | int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval; |
1874 | vif = ah->bslot[(slot + 1) % ATH_BCBUF]; | |
1875 | ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, | |
b1ae1edf | 1876 | "tsf %llx tsftu %x intval %u slot %u vif %p\n", |
e0d687bd | 1877 | (unsigned long long)tsf, tsftu, ah->bintval, slot, vif); |
b1ae1edf | 1878 | } else /* only one interface */ |
e0d687bd | 1879 | vif = ah->bslot[0]; |
b1ae1edf BG |
1880 | |
1881 | if (!vif) | |
1882 | return; | |
1883 | ||
1884 | avf = (void *)vif->drv_priv; | |
1885 | bf = avf->bbuf; | |
b1ae1edf | 1886 | |
fa1c114f JS |
1887 | /* |
1888 | * Stop any current dma and put the new frame on the queue. | |
1889 | * This should never fail since we check above that no frames | |
1890 | * are still pending on the queue. | |
1891 | */ | |
e0d687bd PR |
1892 | if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) { |
1893 | ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq); | |
fa1c114f JS |
1894 | /* NB: hw still stops DMA, so proceed */ |
1895 | } | |
fa1c114f | 1896 | |
d82b577b | 1897 | /* refresh the beacon for AP or MESH mode */ |
e0d687bd | 1898 | if (ah->opmode == NL80211_IFTYPE_AP || |
bdc71bc5 BC |
1899 | ah->opmode == NL80211_IFTYPE_MESH_POINT) { |
1900 | err = ath5k_beacon_update(ah->hw, vif); | |
1901 | if (err) | |
1902 | return; | |
1903 | } | |
1904 | ||
1905 | if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION || | |
1906 | ah->opmode == NL80211_IFTYPE_MONITOR)) { | |
1907 | ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb); | |
1908 | return; | |
1909 | } | |
1071db86 | 1910 | |
e0d687bd | 1911 | trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]); |
0e472252 | 1912 | |
e0d687bd PR |
1913 | ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr); |
1914 | ath5k_hw_start_tx_dma(ah, ah->bhalq); | |
1915 | ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", | |
1916 | ah->bhalq, (unsigned long long)bf->daddr, bf->desc); | |
fa1c114f | 1917 | |
e0d687bd | 1918 | skb = ieee80211_get_buffered_bc(ah->hw, vif); |
cec8db23 | 1919 | while (skb) { |
e0d687bd | 1920 | ath5k_tx_queue(ah->hw, skb, ah->cabq); |
4e868796 | 1921 | |
e0d687bd | 1922 | if (ah->cabq->txq_len >= ah->cabq->txq_max) |
4e868796 FF |
1923 | break; |
1924 | ||
e0d687bd | 1925 | skb = ieee80211_get_buffered_bc(ah->hw, vif); |
cec8db23 BC |
1926 | } |
1927 | ||
e0d687bd | 1928 | ah->bsent++; |
fa1c114f JS |
1929 | } |
1930 | ||
9804b98d BR |
1931 | /** |
1932 | * ath5k_beacon_update_timers - update beacon timers | |
1933 | * | |
e0d687bd | 1934 | * @ah: struct ath5k_hw pointer we are operating on |
9804b98d BR |
1935 | * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a |
1936 | * beacon timer update based on the current HW TSF. | |
1937 | * | |
1938 | * Calculate the next target beacon transmit time (TBTT) based on the timestamp | |
1939 | * of a received beacon or the current local hardware TSF and write it to the | |
1940 | * beacon timer registers. | |
1941 | * | |
1942 | * This is called in a variety of situations, e.g. when a beacon is received, | |
6ba81c2c | 1943 | * when a TSF update has been detected, but also when an new IBSS is created or |
9804b98d BR |
1944 | * when we otherwise know we have to update the timers, but we keep it in this |
1945 | * function to have it all together in one place. | |
1946 | */ | |
cd2c5486 | 1947 | void |
e0d687bd | 1948 | ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf) |
fa1c114f | 1949 | { |
9804b98d BR |
1950 | u32 nexttbtt, intval, hw_tu, bc_tu; |
1951 | u64 hw_tsf; | |
fa1c114f | 1952 | |
e0d687bd | 1953 | intval = ah->bintval & AR5K_BEACON_PERIOD; |
da473b61 CYY |
1954 | if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs |
1955 | + ah->num_mesh_vifs > 1) { | |
b1ae1edf BG |
1956 | intval /= ATH_BCBUF; /* staggered multi-bss beacons */ |
1957 | if (intval < 15) | |
e0d687bd | 1958 | ATH5K_WARN(ah, "intval %u is too low, min 15\n", |
b1ae1edf BG |
1959 | intval); |
1960 | } | |
fa1c114f JS |
1961 | if (WARN_ON(!intval)) |
1962 | return; | |
1963 | ||
9804b98d BR |
1964 | /* beacon TSF converted to TU */ |
1965 | bc_tu = TSF_TO_TU(bc_tsf); | |
fa1c114f | 1966 | |
9804b98d BR |
1967 | /* current TSF converted to TU */ |
1968 | hw_tsf = ath5k_hw_get_tsf64(ah); | |
1969 | hw_tu = TSF_TO_TU(hw_tsf); | |
fa1c114f | 1970 | |
633d006e | 1971 | #define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3) |
11f21df3 | 1972 | /* We use FUDGE to make sure the next TBTT is ahead of the current TU. |
25985edc | 1973 | * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer |
11f21df3 BR |
1974 | * configuration we need to make sure it is bigger than that. */ |
1975 | ||
9804b98d BR |
1976 | if (bc_tsf == -1) { |
1977 | /* | |
1978 | * no beacons received, called internally. | |
1979 | * just need to refresh timers based on HW TSF. | |
1980 | */ | |
1981 | nexttbtt = roundup(hw_tu + FUDGE, intval); | |
1982 | } else if (bc_tsf == 0) { | |
1983 | /* | |
1984 | * no beacon received, probably called by ath5k_reset_tsf(). | |
1985 | * reset TSF to start with 0. | |
1986 | */ | |
1987 | nexttbtt = intval; | |
1988 | intval |= AR5K_BEACON_RESET_TSF; | |
1989 | } else if (bc_tsf > hw_tsf) { | |
1990 | /* | |
25985edc | 1991 | * beacon received, SW merge happened but HW TSF not yet updated. |
9804b98d BR |
1992 | * not possible to reconfigure timers yet, but next time we |
1993 | * receive a beacon with the same BSSID, the hardware will | |
1994 | * automatically update the TSF and then we need to reconfigure | |
1995 | * the timers. | |
1996 | */ | |
e0d687bd | 1997 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, |
9804b98d BR |
1998 | "need to wait for HW TSF sync\n"); |
1999 | return; | |
2000 | } else { | |
2001 | /* | |
2002 | * most important case for beacon synchronization between STA. | |
2003 | * | |
2004 | * beacon received and HW TSF has been already updated by HW. | |
2005 | * update next TBTT based on the TSF of the beacon, but make | |
2006 | * sure it is ahead of our local TSF timer. | |
2007 | */ | |
2008 | nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval); | |
2009 | } | |
2010 | #undef FUDGE | |
fa1c114f | 2011 | |
e0d687bd | 2012 | ah->nexttbtt = nexttbtt; |
036cd1ec | 2013 | |
fa1c114f | 2014 | intval |= AR5K_BEACON_ENA; |
c47faa36 | 2015 | ath5k_hw_init_beacon_timers(ah, nexttbtt, intval); |
9804b98d BR |
2016 | |
2017 | /* | |
2018 | * debugging output last in order to preserve the time critical aspect | |
2019 | * of this function | |
2020 | */ | |
2021 | if (bc_tsf == -1) | |
e0d687bd | 2022 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, |
9804b98d BR |
2023 | "reconfigured timers based on HW TSF\n"); |
2024 | else if (bc_tsf == 0) | |
e0d687bd | 2025 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, |
9804b98d BR |
2026 | "reset HW TSF and timers\n"); |
2027 | else | |
e0d687bd | 2028 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, |
9804b98d BR |
2029 | "updated timers based on beacon TSF\n"); |
2030 | ||
e0d687bd | 2031 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, |
04f93a87 DM |
2032 | "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", |
2033 | (unsigned long long) bc_tsf, | |
2034 | (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); | |
e0d687bd | 2035 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", |
9804b98d BR |
2036 | intval & AR5K_BEACON_PERIOD, |
2037 | intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", | |
2038 | intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); | |
fa1c114f JS |
2039 | } |
2040 | ||
036cd1ec BR |
2041 | /** |
2042 | * ath5k_beacon_config - Configure the beacon queues and interrupts | |
2043 | * | |
e0d687bd | 2044 | * @ah: struct ath5k_hw pointer we are operating on |
fa1c114f | 2045 | * |
036cd1ec | 2046 | * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA |
6ba81c2c | 2047 | * interrupts to detect TSF updates only. |
fa1c114f | 2048 | */ |
cd2c5486 | 2049 | void |
e0d687bd | 2050 | ath5k_beacon_config(struct ath5k_hw *ah) |
fa1c114f | 2051 | { |
7dd6753f | 2052 | spin_lock_bh(&ah->block); |
e0d687bd PR |
2053 | ah->bmisscount = 0; |
2054 | ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); | |
fa1c114f | 2055 | |
e0d687bd | 2056 | if (ah->enable_beacon) { |
fa1c114f | 2057 | /* |
036cd1ec BR |
2058 | * In IBSS mode we use a self-linked tx descriptor and let the |
2059 | * hardware send the beacons automatically. We have to load it | |
fa1c114f | 2060 | * only once here. |
036cd1ec | 2061 | * We use the SWBA interrupt only to keep track of the beacon |
6ba81c2c | 2062 | * timers in order to detect automatic TSF updates. |
fa1c114f | 2063 | */ |
e0d687bd | 2064 | ath5k_beaconq_config(ah); |
fa1c114f | 2065 | |
e0d687bd | 2066 | ah->imask |= AR5K_INT_SWBA; |
036cd1ec | 2067 | |
e0d687bd | 2068 | if (ah->opmode == NL80211_IFTYPE_ADHOC) { |
21800491 | 2069 | if (ath5k_hw_hasveol(ah)) |
e0d687bd | 2070 | ath5k_beacon_send(ah); |
da966bca | 2071 | } else |
e0d687bd | 2072 | ath5k_beacon_update_timers(ah, -1); |
21800491 | 2073 | } else { |
e0d687bd | 2074 | ath5k_hw_stop_beacon_queue(ah, ah->bhalq); |
fa1c114f | 2075 | } |
fa1c114f | 2076 | |
e0d687bd | 2077 | ath5k_hw_set_imr(ah, ah->imask); |
21800491 | 2078 | mmiowb(); |
7dd6753f | 2079 | spin_unlock_bh(&ah->block); |
fa1c114f JS |
2080 | } |
2081 | ||
428cbd4f NK |
2082 | static void ath5k_tasklet_beacon(unsigned long data) |
2083 | { | |
e0d687bd | 2084 | struct ath5k_hw *ah = (struct ath5k_hw *) data; |
428cbd4f NK |
2085 | |
2086 | /* | |
2087 | * Software beacon alert--time to send a beacon. | |
2088 | * | |
2089 | * In IBSS mode we use this interrupt just to | |
2090 | * keep track of the next TBTT (target beacon | |
6a2a0e73 | 2091 | * transmission time) in order to detect whether |
428cbd4f NK |
2092 | * automatic TSF updates happened. |
2093 | */ | |
e0d687bd | 2094 | if (ah->opmode == NL80211_IFTYPE_ADHOC) { |
6a2a0e73 | 2095 | /* XXX: only if VEOL supported */ |
e0d687bd PR |
2096 | u64 tsf = ath5k_hw_get_tsf64(ah); |
2097 | ah->nexttbtt += ah->bintval; | |
2098 | ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, | |
428cbd4f NK |
2099 | "SWBA nexttbtt: %x hw_tu: %x " |
2100 | "TSF: %llx\n", | |
e0d687bd | 2101 | ah->nexttbtt, |
428cbd4f NK |
2102 | TSF_TO_TU(tsf), |
2103 | (unsigned long long) tsf); | |
2104 | } else { | |
e0d687bd PR |
2105 | spin_lock(&ah->block); |
2106 | ath5k_beacon_send(ah); | |
2107 | spin_unlock(&ah->block); | |
428cbd4f NK |
2108 | } |
2109 | } | |
2110 | ||
fa1c114f JS |
2111 | |
2112 | /********************\ | |
2113 | * Interrupt handling * | |
2114 | \********************/ | |
2115 | ||
6a8a3f6b BR |
2116 | static void |
2117 | ath5k_intr_calibration_poll(struct ath5k_hw *ah) | |
2118 | { | |
2111ac0d | 2119 | if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) && |
ce169aca NK |
2120 | !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && |
2121 | !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) { | |
2122 | ||
2123 | /* Run ANI only when calibration is not active */ | |
2124 | ||
2111ac0d BR |
2125 | ah->ah_cal_next_ani = jiffies + |
2126 | msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); | |
e0d687bd | 2127 | tasklet_schedule(&ah->ani_tasklet); |
2111ac0d | 2128 | |
ce169aca NK |
2129 | } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) && |
2130 | !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && | |
2131 | !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) { | |
2132 | ||
2133 | /* Run calibration only when another calibration | |
2134 | * is not running. | |
2135 | * | |
2136 | * Note: This is for both full/short calibration, | |
2137 | * if it's time for a full one, ath5k_calibrate_work will deal | |
2138 | * with it. */ | |
2139 | ||
2140 | ah->ah_cal_next_short = jiffies + | |
2141 | msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT); | |
2142 | ieee80211_queue_work(ah->hw, &ah->calib_work); | |
6a8a3f6b BR |
2143 | } |
2144 | /* we could use SWI to generate enough interrupts to meet our | |
2145 | * calibration interval requirements, if necessary: | |
2146 | * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */ | |
2147 | } | |
2148 | ||
c266c71a | 2149 | static void |
e0d687bd | 2150 | ath5k_schedule_rx(struct ath5k_hw *ah) |
c266c71a | 2151 | { |
e0d687bd PR |
2152 | ah->rx_pending = true; |
2153 | tasklet_schedule(&ah->rxtq); | |
c266c71a FF |
2154 | } |
2155 | ||
2156 | static void | |
e0d687bd | 2157 | ath5k_schedule_tx(struct ath5k_hw *ah) |
c266c71a | 2158 | { |
e0d687bd PR |
2159 | ah->tx_pending = true; |
2160 | tasklet_schedule(&ah->txtq); | |
c266c71a FF |
2161 | } |
2162 | ||
f5cbc8ba | 2163 | static irqreturn_t |
fa1c114f JS |
2164 | ath5k_intr(int irq, void *dev_id) |
2165 | { | |
e0d687bd | 2166 | struct ath5k_hw *ah = dev_id; |
fa1c114f JS |
2167 | enum ath5k_int status; |
2168 | unsigned int counter = 1000; | |
2169 | ||
34ce644a NK |
2170 | |
2171 | /* | |
2172 | * If hw is not ready (or detached) and we get an | |
2173 | * interrupt, or if we have no interrupts pending | |
2174 | * (that means it's not for us) skip it. | |
2175 | * | |
2176 | * NOTE: Group 0/1 PCI interface registers are not | |
2177 | * supported on WiSOCs, so we can't check for pending | |
2178 | * interrupts (ISR belongs to another register group | |
2179 | * so we are ok). | |
2180 | */ | |
e0d687bd | 2181 | if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) || |
34ce644a NK |
2182 | ((ath5k_get_bus_type(ah) != ATH_AHB) && |
2183 | !ath5k_hw_is_intr_pending(ah)))) | |
fa1c114f JS |
2184 | return IRQ_NONE; |
2185 | ||
34ce644a | 2186 | /** Main loop **/ |
fa1c114f | 2187 | do { |
34ce644a NK |
2188 | ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ |
2189 | ||
e0d687bd PR |
2190 | ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", |
2191 | status, ah->imask); | |
34ce644a NK |
2192 | |
2193 | /* | |
2194 | * Fatal hw error -> Log and reset | |
2195 | * | |
2196 | * Fatal errors are unrecoverable so we have to | |
2197 | * reset the card. These errors include bus and | |
2198 | * dma errors. | |
2199 | */ | |
fa1c114f | 2200 | if (unlikely(status & AR5K_INT_FATAL)) { |
34ce644a | 2201 | |
e0d687bd | 2202 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, |
8d67a031 | 2203 | "fatal int, resetting\n"); |
e0d687bd | 2204 | ieee80211_queue_work(ah->hw, &ah->reset_work); |
34ce644a NK |
2205 | |
2206 | /* | |
2207 | * RX Overrun -> Count and reset if needed | |
2208 | * | |
2209 | * Receive buffers are full. Either the bus is busy or | |
2210 | * the CPU is not fast enough to process all received | |
2211 | * frames. | |
2212 | */ | |
fa1c114f | 2213 | } else if (unlikely(status & AR5K_INT_RXORN)) { |
34ce644a | 2214 | |
87d77c4e | 2215 | /* |
87d77c4e BR |
2216 | * Older chipsets need a reset to come out of this |
2217 | * condition, but we treat it as RX for newer chips. | |
34ce644a | 2218 | * We don't know exactly which versions need a reset |
87d77c4e BR |
2219 | * this guess is copied from the HAL. |
2220 | */ | |
e0d687bd | 2221 | ah->stats.rxorn_intr++; |
34ce644a | 2222 | |
8d67a031 | 2223 | if (ah->ah_mac_srev < AR5K_SREV_AR5212) { |
e0d687bd | 2224 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, |
8d67a031 | 2225 | "rx overrun, resetting\n"); |
e0d687bd | 2226 | ieee80211_queue_work(ah->hw, &ah->reset_work); |
d2c7f773 | 2227 | } else |
e0d687bd | 2228 | ath5k_schedule_rx(ah); |
34ce644a | 2229 | |
fa1c114f | 2230 | } else { |
34ce644a NK |
2231 | |
2232 | /* Software Beacon Alert -> Schedule beacon tasklet */ | |
d2c7f773 | 2233 | if (status & AR5K_INT_SWBA) |
e0d687bd | 2234 | tasklet_hi_schedule(&ah->beacontq); |
d2c7f773 | 2235 | |
34ce644a NK |
2236 | /* |
2237 | * No more RX descriptors -> Just count | |
2238 | * | |
2239 | * NB: the hardware should re-read the link when | |
2240 | * RXE bit is written, but it doesn't work at | |
2241 | * least on older hardware revs. | |
2242 | */ | |
2243 | if (status & AR5K_INT_RXEOL) | |
e0d687bd | 2244 | ah->stats.rxeol_intr++; |
34ce644a NK |
2245 | |
2246 | ||
2247 | /* TX Underrun -> Bump tx trigger level */ | |
2248 | if (status & AR5K_INT_TXURN) | |
fa1c114f | 2249 | ath5k_hw_update_tx_triglevel(ah, true); |
34ce644a NK |
2250 | |
2251 | /* RX -> Schedule rx tasklet */ | |
4c674c60 | 2252 | if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) |
e0d687bd | 2253 | ath5k_schedule_rx(ah); |
34ce644a NK |
2254 | |
2255 | /* TX -> Schedule tx tasklet */ | |
2256 | if (status & (AR5K_INT_TXOK | |
2257 | | AR5K_INT_TXDESC | |
2258 | | AR5K_INT_TXERR | |
2259 | | AR5K_INT_TXEOL)) | |
e0d687bd | 2260 | ath5k_schedule_tx(ah); |
34ce644a NK |
2261 | |
2262 | /* Missed beacon -> TODO | |
2263 | if (status & AR5K_INT_BMISS) | |
2264 | */ | |
2265 | ||
2266 | /* MIB event -> Update counters and notify ANI */ | |
fa1c114f | 2267 | if (status & AR5K_INT_MIB) { |
e0d687bd | 2268 | ah->stats.mib_intr++; |
495391d7 | 2269 | ath5k_hw_update_mib_counters(ah); |
2111ac0d | 2270 | ath5k_ani_mib_intr(ah); |
fa1c114f | 2271 | } |
34ce644a NK |
2272 | |
2273 | /* GPIO -> Notify RFKill layer */ | |
e6a3b616 | 2274 | if (status & AR5K_INT_GPIO) |
e0d687bd | 2275 | tasklet_schedule(&ah->rf_kill.toggleq); |
a6ae0716 | 2276 | |
fa1c114f | 2277 | } |
4cebb34c FF |
2278 | |
2279 | if (ath5k_get_bus_type(ah) == ATH_AHB) | |
2280 | break; | |
2281 | ||
2516baa6 | 2282 | } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); |
fa1c114f | 2283 | |
34ce644a NK |
2284 | /* |
2285 | * Until we handle rx/tx interrupts mask them on IMR | |
2286 | * | |
2287 | * NOTE: ah->(rx/tx)_pending are set when scheduling the tasklets | |
2288 | * and unset after we 've handled the interrupts. | |
2289 | */ | |
e0d687bd PR |
2290 | if (ah->rx_pending || ah->tx_pending) |
2291 | ath5k_set_current_imask(ah); | |
c266c71a | 2292 | |
fa1c114f | 2293 | if (unlikely(!counter)) |
e0d687bd | 2294 | ATH5K_WARN(ah, "too many interrupts, giving up for now\n"); |
fa1c114f | 2295 | |
34ce644a | 2296 | /* Fire up calibration poll */ |
6a8a3f6b | 2297 | ath5k_intr_calibration_poll(ah); |
6e220662 | 2298 | |
fa1c114f JS |
2299 | return IRQ_HANDLED; |
2300 | } | |
2301 | ||
fa1c114f JS |
2302 | /* |
2303 | * Periodically recalibrate the PHY to account | |
2304 | * for temperature/environment changes. | |
2305 | */ | |
2306 | static void | |
ce169aca | 2307 | ath5k_calibrate_work(struct work_struct *work) |
fa1c114f | 2308 | { |
ce169aca NK |
2309 | struct ath5k_hw *ah = container_of(work, struct ath5k_hw, |
2310 | calib_work); | |
2311 | ||
2312 | /* Should we run a full calibration ? */ | |
2313 | if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) { | |
2314 | ||
2315 | ah->ah_cal_next_full = jiffies + | |
2316 | msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); | |
2317 | ah->ah_cal_mask |= AR5K_CALIBRATION_FULL; | |
2318 | ||
2319 | ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, | |
2320 | "running full calibration\n"); | |
2321 | ||
2322 | if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { | |
2323 | /* | |
2324 | * Rfgain is out of bounds, reset the chip | |
2325 | * to load new gain values. | |
2326 | */ | |
2327 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, | |
2328 | "got new rfgain, resetting\n"); | |
2329 | ieee80211_queue_work(ah->hw, &ah->reset_work); | |
2330 | } | |
ce169aca NK |
2331 | } else |
2332 | ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT; | |
fa1c114f | 2333 | |
6e220662 | 2334 | |
e0d687bd PR |
2335 | ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", |
2336 | ieee80211_frequency_to_channel(ah->curchan->center_freq), | |
2337 | ah->curchan->hw_value); | |
fa1c114f | 2338 | |
e0d687bd PR |
2339 | if (ath5k_hw_phy_calibrate(ah, ah->curchan)) |
2340 | ATH5K_ERR(ah, "calibration of channel %u failed\n", | |
400ec45a | 2341 | ieee80211_frequency_to_channel( |
e0d687bd | 2342 | ah->curchan->center_freq)); |
fa1c114f | 2343 | |
ce169aca | 2344 | /* Clear calibration flags */ |
62e2c102 | 2345 | if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL) |
ce169aca | 2346 | ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL; |
62e2c102 | 2347 | else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT) |
ce169aca | 2348 | ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT; |
fa1c114f JS |
2349 | } |
2350 | ||
2351 | ||
2111ac0d BR |
2352 | static void |
2353 | ath5k_tasklet_ani(unsigned long data) | |
2354 | { | |
e0d687bd | 2355 | struct ath5k_hw *ah = (void *)data; |
2111ac0d BR |
2356 | |
2357 | ah->ah_cal_mask |= AR5K_CALIBRATION_ANI; | |
2358 | ath5k_ani_calibration(ah); | |
2359 | ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI; | |
fa1c114f JS |
2360 | } |
2361 | ||
2362 | ||
4edd761f BR |
2363 | static void |
2364 | ath5k_tx_complete_poll_work(struct work_struct *work) | |
2365 | { | |
e0d687bd | 2366 | struct ath5k_hw *ah = container_of(work, struct ath5k_hw, |
4edd761f BR |
2367 | tx_complete_work.work); |
2368 | struct ath5k_txq *txq; | |
2369 | int i; | |
2370 | bool needreset = false; | |
2371 | ||
e0d687bd | 2372 | mutex_lock(&ah->lock); |
599b13ad | 2373 | |
e0d687bd PR |
2374 | for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { |
2375 | if (ah->txqs[i].setup) { | |
2376 | txq = &ah->txqs[i]; | |
4edd761f | 2377 | spin_lock_bh(&txq->lock); |
23413296 | 2378 | if (txq->txq_len > 1) { |
4edd761f | 2379 | if (txq->txq_poll_mark) { |
e0d687bd | 2380 | ATH5K_DBG(ah, ATH5K_DEBUG_XMIT, |
4edd761f BR |
2381 | "TX queue stuck %d\n", |
2382 | txq->qnum); | |
2383 | needreset = true; | |
923e5b3d | 2384 | txq->txq_stuck++; |
4edd761f BR |
2385 | spin_unlock_bh(&txq->lock); |
2386 | break; | |
2387 | } else { | |
2388 | txq->txq_poll_mark = true; | |
2389 | } | |
2390 | } | |
2391 | spin_unlock_bh(&txq->lock); | |
2392 | } | |
2393 | } | |
2394 | ||
2395 | if (needreset) { | |
e0d687bd | 2396 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, |
4edd761f | 2397 | "TX queues stuck, resetting\n"); |
e0d687bd | 2398 | ath5k_reset(ah, NULL, true); |
4edd761f BR |
2399 | } |
2400 | ||
e0d687bd | 2401 | mutex_unlock(&ah->lock); |
599b13ad | 2402 | |
e0d687bd | 2403 | ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, |
4edd761f BR |
2404 | msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); |
2405 | } | |
2406 | ||
2407 | ||
8a63facc BC |
2408 | /*************************\ |
2409 | * Initialization routines * | |
2410 | \*************************/ | |
fa1c114f | 2411 | |
9b4760e3 FF |
2412 | static const struct ieee80211_iface_limit if_limits[] = { |
2413 | { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) }, | |
2414 | { .max = 4, .types = | |
2415 | #ifdef CONFIG_MAC80211_MESH | |
2416 | BIT(NL80211_IFTYPE_MESH_POINT) | | |
2417 | #endif | |
2418 | BIT(NL80211_IFTYPE_AP) }, | |
2419 | }; | |
2420 | ||
2421 | static const struct ieee80211_iface_combination if_comb = { | |
2422 | .limits = if_limits, | |
2423 | .n_limits = ARRAY_SIZE(if_limits), | |
2424 | .max_interfaces = 2048, | |
2425 | .num_different_channels = 1, | |
2426 | }; | |
2427 | ||
e829cf96 | 2428 | int |
bb1f3ad9 | 2429 | ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops) |
132b1c3e | 2430 | { |
e0d687bd | 2431 | struct ieee80211_hw *hw = ah->hw; |
132b1c3e FF |
2432 | struct ath_common *common; |
2433 | int ret; | |
2434 | int csz; | |
2435 | ||
2436 | /* Initialize driver private data */ | |
e0d687bd | 2437 | SET_IEEE80211_DEV(hw, ah->dev); |
132b1c3e | 2438 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | |
b9e61f11 NK |
2439 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | |
2440 | IEEE80211_HW_SIGNAL_DBM | | |
90e6274d | 2441 | IEEE80211_HW_MFP_CAPABLE | |
b9e61f11 | 2442 | IEEE80211_HW_REPORTS_TX_ACK_STATUS; |
132b1c3e FF |
2443 | |
2444 | hw->wiphy->interface_modes = | |
2445 | BIT(NL80211_IFTYPE_AP) | | |
2446 | BIT(NL80211_IFTYPE_STATION) | | |
2447 | BIT(NL80211_IFTYPE_ADHOC) | | |
2448 | BIT(NL80211_IFTYPE_MESH_POINT); | |
2449 | ||
9b4760e3 FF |
2450 | hw->wiphy->iface_combinations = &if_comb; |
2451 | hw->wiphy->n_iface_combinations = 1; | |
2452 | ||
f9972577 AQ |
2453 | /* SW support for IBSS_RSN is provided by mac80211 */ |
2454 | hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; | |
2455 | ||
3de135db BR |
2456 | /* both antennas can be configured as RX or TX */ |
2457 | hw->wiphy->available_antennas_tx = 0x3; | |
2458 | hw->wiphy->available_antennas_rx = 0x3; | |
2459 | ||
132b1c3e FF |
2460 | hw->extra_tx_headroom = 2; |
2461 | hw->channel_change_time = 5000; | |
2462 | ||
2463 | /* | |
2464 | * Mark the device as detached to avoid processing | |
2465 | * interrupts until setup is complete. | |
2466 | */ | |
e0d687bd | 2467 | __set_bit(ATH_STAT_INVALID, ah->status); |
132b1c3e | 2468 | |
e0d687bd PR |
2469 | ah->opmode = NL80211_IFTYPE_STATION; |
2470 | ah->bintval = 1000; | |
2471 | mutex_init(&ah->lock); | |
2472 | spin_lock_init(&ah->rxbuflock); | |
2473 | spin_lock_init(&ah->txbuflock); | |
2474 | spin_lock_init(&ah->block); | |
2475 | spin_lock_init(&ah->irqlock); | |
132b1c3e FF |
2476 | |
2477 | /* Setup interrupt handler */ | |
e0d687bd | 2478 | ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah); |
132b1c3e | 2479 | if (ret) { |
e0d687bd | 2480 | ATH5K_ERR(ah, "request_irq failed\n"); |
132b1c3e FF |
2481 | goto err; |
2482 | } | |
2483 | ||
e0d687bd | 2484 | common = ath5k_hw_common(ah); |
132b1c3e FF |
2485 | common->ops = &ath5k_common_ops; |
2486 | common->bus_ops = bus_ops; | |
e0d687bd | 2487 | common->ah = ah; |
132b1c3e | 2488 | common->hw = hw; |
e0d687bd | 2489 | common->priv = ah; |
26d16d23 | 2490 | common->clockrate = 40; |
132b1c3e FF |
2491 | |
2492 | /* | |
2493 | * Cache line size is used to size and align various | |
2494 | * structures used to communicate with the hardware. | |
2495 | */ | |
2496 | ath5k_read_cachesize(common, &csz); | |
2497 | common->cachelsz = csz << 2; /* convert to bytes */ | |
2498 | ||
2499 | spin_lock_init(&common->cc_lock); | |
2500 | ||
2501 | /* Initialize device */ | |
e0d687bd | 2502 | ret = ath5k_hw_init(ah); |
132b1c3e | 2503 | if (ret) |
e0d687bd | 2504 | goto err_irq; |
132b1c3e | 2505 | |
86f62d9b NK |
2506 | /* Set up multi-rate retry capabilities */ |
2507 | if (ah->ah_capabilities.cap_has_mrr_support) { | |
132b1c3e | 2508 | hw->max_rates = 4; |
76a9f6fd BR |
2509 | hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT, |
2510 | AR5K_INIT_RETRY_LONG); | |
132b1c3e FF |
2511 | } |
2512 | ||
2513 | hw->vif_data_size = sizeof(struct ath5k_vif); | |
2514 | ||
2515 | /* Finish private driver data initialization */ | |
2516 | ret = ath5k_init(hw); | |
2517 | if (ret) | |
2518 | goto err_ah; | |
2519 | ||
e0d687bd PR |
2520 | ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", |
2521 | ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev), | |
2522 | ah->ah_mac_srev, | |
2523 | ah->ah_phy_revision); | |
132b1c3e | 2524 | |
e0d687bd | 2525 | if (!ah->ah_single_chip) { |
132b1c3e | 2526 | /* Single chip radio (!RF5111) */ |
e0d687bd PR |
2527 | if (ah->ah_radio_5ghz_revision && |
2528 | !ah->ah_radio_2ghz_revision) { | |
132b1c3e FF |
2529 | /* No 5GHz support -> report 2GHz radio */ |
2530 | if (!test_bit(AR5K_MODE_11A, | |
e0d687bd PR |
2531 | ah->ah_capabilities.cap_mode)) { |
2532 | ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", | |
132b1c3e | 2533 | ath5k_chip_name(AR5K_VERSION_RAD, |
e0d687bd PR |
2534 | ah->ah_radio_5ghz_revision), |
2535 | ah->ah_radio_5ghz_revision); | |
132b1c3e | 2536 | /* No 2GHz support (5110 and some |
6a2a0e73 | 2537 | * 5GHz only cards) -> report 5GHz radio */ |
132b1c3e | 2538 | } else if (!test_bit(AR5K_MODE_11B, |
e0d687bd PR |
2539 | ah->ah_capabilities.cap_mode)) { |
2540 | ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", | |
132b1c3e | 2541 | ath5k_chip_name(AR5K_VERSION_RAD, |
e0d687bd PR |
2542 | ah->ah_radio_5ghz_revision), |
2543 | ah->ah_radio_5ghz_revision); | |
132b1c3e FF |
2544 | /* Multiband radio */ |
2545 | } else { | |
e0d687bd | 2546 | ATH5K_INFO(ah, "RF%s multiband radio found" |
132b1c3e FF |
2547 | " (0x%x)\n", |
2548 | ath5k_chip_name(AR5K_VERSION_RAD, | |
e0d687bd PR |
2549 | ah->ah_radio_5ghz_revision), |
2550 | ah->ah_radio_5ghz_revision); | |
132b1c3e FF |
2551 | } |
2552 | } | |
2553 | /* Multi chip radio (RF5111 - RF2111) -> | |
2554 | * report both 2GHz/5GHz radios */ | |
e0d687bd PR |
2555 | else if (ah->ah_radio_5ghz_revision && |
2556 | ah->ah_radio_2ghz_revision) { | |
2557 | ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", | |
132b1c3e | 2558 | ath5k_chip_name(AR5K_VERSION_RAD, |
e0d687bd PR |
2559 | ah->ah_radio_5ghz_revision), |
2560 | ah->ah_radio_5ghz_revision); | |
2561 | ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", | |
132b1c3e | 2562 | ath5k_chip_name(AR5K_VERSION_RAD, |
e0d687bd PR |
2563 | ah->ah_radio_2ghz_revision), |
2564 | ah->ah_radio_2ghz_revision); | |
132b1c3e FF |
2565 | } |
2566 | } | |
2567 | ||
e0d687bd | 2568 | ath5k_debug_init_device(ah); |
132b1c3e FF |
2569 | |
2570 | /* ready to process interrupts */ | |
e0d687bd | 2571 | __clear_bit(ATH_STAT_INVALID, ah->status); |
132b1c3e FF |
2572 | |
2573 | return 0; | |
2574 | err_ah: | |
e0d687bd | 2575 | ath5k_hw_deinit(ah); |
132b1c3e | 2576 | err_irq: |
e0d687bd | 2577 | free_irq(ah->irq, ah); |
132b1c3e FF |
2578 | err: |
2579 | return ret; | |
2580 | } | |
2581 | ||
fa1c114f | 2582 | static int |
e0d687bd | 2583 | ath5k_stop_locked(struct ath5k_hw *ah) |
cec8db23 | 2584 | { |
cec8db23 | 2585 | |
e0d687bd PR |
2586 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n", |
2587 | test_bit(ATH_STAT_INVALID, ah->status)); | |
8a63facc BC |
2588 | |
2589 | /* | |
2590 | * Shutdown the hardware and driver: | |
2591 | * stop output from above | |
2592 | * disable interrupts | |
2593 | * turn off timers | |
2594 | * turn off the radio | |
2595 | * clear transmit machinery | |
2596 | * clear receive machinery | |
2597 | * drain and release tx queues | |
2598 | * reclaim beacon resources | |
2599 | * power down hardware | |
2600 | * | |
2601 | * Note that some of this work is not possible if the | |
2602 | * hardware is gone (invalid). | |
2603 | */ | |
e0d687bd | 2604 | ieee80211_stop_queues(ah->hw); |
8a63facc | 2605 | |
e0d687bd PR |
2606 | if (!test_bit(ATH_STAT_INVALID, ah->status)) { |
2607 | ath5k_led_off(ah); | |
8a63facc | 2608 | ath5k_hw_set_imr(ah, 0); |
e0d687bd PR |
2609 | synchronize_irq(ah->irq); |
2610 | ath5k_rx_stop(ah); | |
80dac9ee | 2611 | ath5k_hw_dma_stop(ah); |
e0d687bd | 2612 | ath5k_drain_tx_buffs(ah); |
8a63facc BC |
2613 | ath5k_hw_phy_disable(ah); |
2614 | } | |
2615 | ||
2616 | return 0; | |
cec8db23 BC |
2617 | } |
2618 | ||
fabba048 | 2619 | int ath5k_start(struct ieee80211_hw *hw) |
fa1c114f | 2620 | { |
fabba048 | 2621 | struct ath5k_hw *ah = hw->priv; |
8a63facc BC |
2622 | struct ath_common *common = ath5k_hw_common(ah); |
2623 | int ret, i; | |
fa1c114f | 2624 | |
e0d687bd | 2625 | mutex_lock(&ah->lock); |
8a63facc | 2626 | |
e0d687bd | 2627 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode); |
fa1c114f | 2628 | |
fa1c114f | 2629 | /* |
8a63facc BC |
2630 | * Stop anything previously setup. This is safe |
2631 | * no matter this is the first time through or not. | |
fa1c114f | 2632 | */ |
e0d687bd | 2633 | ath5k_stop_locked(ah); |
fa1c114f | 2634 | |
8a63facc BC |
2635 | /* |
2636 | * The basic interface to setting the hardware in a good | |
2637 | * state is ``reset''. On return the hardware is known to | |
2638 | * be powered up and with interrupts disabled. This must | |
2639 | * be followed by initialization of the appropriate bits | |
2640 | * and then setup of the interrupt mask. | |
2641 | */ | |
675a0b04 | 2642 | ah->curchan = ah->hw->conf.chandef.chan; |
34ce644a NK |
2643 | ah->imask = AR5K_INT_RXOK |
2644 | | AR5K_INT_RXERR | |
2645 | | AR5K_INT_RXEOL | |
2646 | | AR5K_INT_RXORN | |
2647 | | AR5K_INT_TXDESC | |
2648 | | AR5K_INT_TXEOL | |
2649 | | AR5K_INT_FATAL | |
2650 | | AR5K_INT_GLOBAL | |
2651 | | AR5K_INT_MIB; | |
fa1c114f | 2652 | |
e0d687bd | 2653 | ret = ath5k_reset(ah, NULL, false); |
8a63facc BC |
2654 | if (ret) |
2655 | goto done; | |
fa1c114f | 2656 | |
84e1e737 NK |
2657 | if (!ath5k_modparam_no_hw_rfkill_switch) |
2658 | ath5k_rfkill_hw_start(ah); | |
8a63facc BC |
2659 | |
2660 | /* | |
2661 | * Reset the key cache since some parts do not reset the | |
2662 | * contents on initial power up or resume from suspend. | |
2663 | */ | |
2664 | for (i = 0; i < common->keymax; i++) | |
2665 | ath_hw_keyreset(common, (u16) i); | |
2666 | ||
61cde037 NK |
2667 | /* Use higher rates for acks instead of base |
2668 | * rate */ | |
2669 | ah->ah_ack_bitrate_high = true; | |
b1ae1edf | 2670 | |
e0d687bd PR |
2671 | for (i = 0; i < ARRAY_SIZE(ah->bslot); i++) |
2672 | ah->bslot[i] = NULL; | |
b1ae1edf | 2673 | |
8a63facc BC |
2674 | ret = 0; |
2675 | done: | |
2676 | mmiowb(); | |
e0d687bd | 2677 | mutex_unlock(&ah->lock); |
4edd761f | 2678 | |
e0d687bd | 2679 | ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, |
4edd761f BR |
2680 | msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); |
2681 | ||
8a63facc BC |
2682 | return ret; |
2683 | } | |
2684 | ||
e0d687bd | 2685 | static void ath5k_stop_tasklets(struct ath5k_hw *ah) |
8a63facc | 2686 | { |
e0d687bd PR |
2687 | ah->rx_pending = false; |
2688 | ah->tx_pending = false; | |
2689 | tasklet_kill(&ah->rxtq); | |
2690 | tasklet_kill(&ah->txtq); | |
e0d687bd PR |
2691 | tasklet_kill(&ah->beacontq); |
2692 | tasklet_kill(&ah->ani_tasklet); | |
8a63facc BC |
2693 | } |
2694 | ||
2695 | /* | |
2696 | * Stop the device, grabbing the top-level lock to protect | |
2697 | * against concurrent entry through ath5k_init (which can happen | |
2698 | * if another thread does a system call and the thread doing the | |
2699 | * stop is preempted). | |
2700 | */ | |
fabba048 | 2701 | void ath5k_stop(struct ieee80211_hw *hw) |
8a63facc | 2702 | { |
fabba048 | 2703 | struct ath5k_hw *ah = hw->priv; |
8a63facc BC |
2704 | int ret; |
2705 | ||
e0d687bd PR |
2706 | mutex_lock(&ah->lock); |
2707 | ret = ath5k_stop_locked(ah); | |
2708 | if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) { | |
8a63facc BC |
2709 | /* |
2710 | * Don't set the card in full sleep mode! | |
2711 | * | |
2712 | * a) When the device is in this state it must be carefully | |
2713 | * woken up or references to registers in the PCI clock | |
2714 | * domain may freeze the bus (and system). This varies | |
2715 | * by chip and is mostly an issue with newer parts | |
2716 | * (madwifi sources mentioned srev >= 0x78) that go to | |
2717 | * sleep more quickly. | |
2718 | * | |
2719 | * b) On older chips full sleep results a weird behaviour | |
2720 | * during wakeup. I tested various cards with srev < 0x78 | |
2721 | * and they don't wake up after module reload, a second | |
2722 | * module reload is needed to bring the card up again. | |
2723 | * | |
2724 | * Until we figure out what's going on don't enable | |
2725 | * full chip reset on any chip (this is what Legacy HAL | |
2726 | * and Sam's HAL do anyway). Instead Perform a full reset | |
2727 | * on the device (same as initial state after attach) and | |
2728 | * leave it idle (keep MAC/BB on warm reset) */ | |
e0d687bd | 2729 | ret = ath5k_hw_on_hold(ah); |
8a63facc | 2730 | |
e0d687bd | 2731 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, |
8a63facc | 2732 | "putting device to sleep\n"); |
fa1c114f JS |
2733 | } |
2734 | ||
8a63facc | 2735 | mmiowb(); |
e0d687bd | 2736 | mutex_unlock(&ah->lock); |
8a63facc | 2737 | |
e0d687bd | 2738 | ath5k_stop_tasklets(ah); |
4edd761f | 2739 | |
e0d687bd | 2740 | cancel_delayed_work_sync(&ah->tx_complete_work); |
8a63facc | 2741 | |
84e1e737 NK |
2742 | if (!ath5k_modparam_no_hw_rfkill_switch) |
2743 | ath5k_rfkill_hw_stop(ah); | |
fa1c114f JS |
2744 | } |
2745 | ||
209d889b BC |
2746 | /* |
2747 | * Reset the hardware. If chan is not NULL, then also pause rx/tx | |
2748 | * and change to the given channel. | |
5faaff74 | 2749 | * |
e0d687bd | 2750 | * This should be called with ah->lock. |
209d889b | 2751 | */ |
fa1c114f | 2752 | static int |
e0d687bd | 2753 | ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan, |
8aec7af9 | 2754 | bool skip_pcu) |
fa1c114f | 2755 | { |
f15a4bb2 | 2756 | struct ath_common *common = ath5k_hw_common(ah); |
344b54b9 | 2757 | int ret, ani_mode; |
a99168ee | 2758 | bool fast; |
fa1c114f | 2759 | |
e0d687bd | 2760 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n"); |
fa1c114f | 2761 | |
450464de | 2762 | ath5k_hw_set_imr(ah, 0); |
e0d687bd PR |
2763 | synchronize_irq(ah->irq); |
2764 | ath5k_stop_tasklets(ah); | |
450464de | 2765 | |
25985edc | 2766 | /* Save ani mode and disable ANI during |
344b54b9 NK |
2767 | * reset. If we don't we might get false |
2768 | * PHY error interrupts. */ | |
e0d687bd | 2769 | ani_mode = ah->ani_state.ani_mode; |
344b54b9 NK |
2770 | ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF); |
2771 | ||
19252ecb NK |
2772 | /* We are going to empty hw queues |
2773 | * so we should also free any remaining | |
2774 | * tx buffers */ | |
e0d687bd | 2775 | ath5k_drain_tx_buffs(ah); |
930a7622 | 2776 | if (chan) |
e0d687bd | 2777 | ah->curchan = chan; |
a99168ee NK |
2778 | |
2779 | fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0; | |
2780 | ||
e0d687bd | 2781 | ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu); |
d7dc1003 | 2782 | if (ret) { |
e0d687bd | 2783 | ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret); |
fa1c114f JS |
2784 | goto err; |
2785 | } | |
d7dc1003 | 2786 | |
e0d687bd | 2787 | ret = ath5k_rx_start(ah); |
d7dc1003 | 2788 | if (ret) { |
e0d687bd | 2789 | ATH5K_ERR(ah, "can't start recv logic\n"); |
fa1c114f JS |
2790 | goto err; |
2791 | } | |
d7dc1003 | 2792 | |
344b54b9 | 2793 | ath5k_ani_init(ah, ani_mode); |
2111ac0d | 2794 | |
ce169aca NK |
2795 | /* |
2796 | * Set calibration intervals | |
2797 | * | |
2798 | * Note: We don't need to run calibration imediately | |
2799 | * since some initial calibration is done on reset | |
2800 | * even for fast channel switching. Also on scanning | |
2801 | * this will get set again and again and it won't get | |
2802 | * executed unless we connect somewhere and spend some | |
2803 | * time on the channel (that's what calibration needs | |
2804 | * anyway to be accurate). | |
2805 | */ | |
2806 | ah->ah_cal_next_full = jiffies + | |
2807 | msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); | |
2808 | ah->ah_cal_next_ani = jiffies + | |
2809 | msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); | |
2810 | ah->ah_cal_next_short = jiffies + | |
2811 | msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT); | |
2812 | ||
5dcc03fe | 2813 | ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8); |
afe86286 | 2814 | |
f15a4bb2 | 2815 | /* clear survey data and cycle counters */ |
e0d687bd | 2816 | memset(&ah->survey, 0, sizeof(ah->survey)); |
bb007554 | 2817 | spin_lock_bh(&common->cc_lock); |
f15a4bb2 BR |
2818 | ath_hw_cycle_counters_update(common); |
2819 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
2820 | memset(&common->cc_ani, 0, sizeof(common->cc_ani)); | |
bb007554 | 2821 | spin_unlock_bh(&common->cc_lock); |
f15a4bb2 | 2822 | |
fa1c114f | 2823 | /* |
d7dc1003 JS |
2824 | * Change channels and update the h/w rate map if we're switching; |
2825 | * e.g. 11a to 11b/g. | |
2826 | * | |
2827 | * We may be doing a reset in response to an ioctl that changes the | |
2828 | * channel so update any state that might change as a result. | |
fa1c114f JS |
2829 | * |
2830 | * XXX needed? | |
2831 | */ | |
e0d687bd | 2832 | /* ath5k_chan_change(ah, c); */ |
fa1c114f | 2833 | |
e0d687bd | 2834 | ath5k_beacon_config(ah); |
d7dc1003 | 2835 | /* intrs are enabled by ath5k_beacon_config */ |
fa1c114f | 2836 | |
e0d687bd | 2837 | ieee80211_wake_queues(ah->hw); |
397f385b | 2838 | |
fa1c114f JS |
2839 | return 0; |
2840 | err: | |
2841 | return ret; | |
2842 | } | |
2843 | ||
5faaff74 BC |
2844 | static void ath5k_reset_work(struct work_struct *work) |
2845 | { | |
e0d687bd | 2846 | struct ath5k_hw *ah = container_of(work, struct ath5k_hw, |
5faaff74 BC |
2847 | reset_work); |
2848 | ||
e0d687bd PR |
2849 | mutex_lock(&ah->lock); |
2850 | ath5k_reset(ah, NULL, true); | |
2851 | mutex_unlock(&ah->lock); | |
5faaff74 BC |
2852 | } |
2853 | ||
e829cf96 | 2854 | static int |
132b1c3e | 2855 | ath5k_init(struct ieee80211_hw *hw) |
fa1c114f | 2856 | { |
132b1c3e | 2857 | |
e0d687bd | 2858 | struct ath5k_hw *ah = hw->priv; |
8a63facc | 2859 | struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); |
925e0b06 | 2860 | struct ath5k_txq *txq; |
8a63facc | 2861 | u8 mac[ETH_ALEN] = {}; |
fa1c114f JS |
2862 | int ret; |
2863 | ||
fa1c114f | 2864 | |
8a63facc BC |
2865 | /* |
2866 | * Collect the channel list. The 802.11 layer | |
6a2a0e73 | 2867 | * is responsible for filtering this list based |
8a63facc BC |
2868 | * on settings like the phy mode and regulatory |
2869 | * domain restrictions. | |
2870 | */ | |
2871 | ret = ath5k_setup_bands(hw); | |
2872 | if (ret) { | |
e0d687bd | 2873 | ATH5K_ERR(ah, "can't get channels\n"); |
8a63facc BC |
2874 | goto err; |
2875 | } | |
67d2e2df | 2876 | |
8a63facc BC |
2877 | /* |
2878 | * Allocate tx+rx descriptors and populate the lists. | |
2879 | */ | |
e0d687bd | 2880 | ret = ath5k_desc_alloc(ah); |
8a63facc | 2881 | if (ret) { |
e0d687bd | 2882 | ATH5K_ERR(ah, "can't allocate descriptors\n"); |
8a63facc BC |
2883 | goto err; |
2884 | } | |
fa1c114f | 2885 | |
8a63facc BC |
2886 | /* |
2887 | * Allocate hardware transmit queues: one queue for | |
2888 | * beacon frames and one data queue for each QoS | |
2889 | * priority. Note that hw functions handle resetting | |
2890 | * these queues at the needed time. | |
2891 | */ | |
2892 | ret = ath5k_beaconq_setup(ah); | |
2893 | if (ret < 0) { | |
e0d687bd | 2894 | ATH5K_ERR(ah, "can't setup a beacon xmit queue\n"); |
8a63facc BC |
2895 | goto err_desc; |
2896 | } | |
e0d687bd PR |
2897 | ah->bhalq = ret; |
2898 | ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0); | |
2899 | if (IS_ERR(ah->cabq)) { | |
2900 | ATH5K_ERR(ah, "can't setup cab queue\n"); | |
2901 | ret = PTR_ERR(ah->cabq); | |
8a63facc BC |
2902 | goto err_bhal; |
2903 | } | |
fa1c114f | 2904 | |
22d8d9f8 BR |
2905 | /* 5211 and 5212 usually support 10 queues but we better rely on the |
2906 | * capability information */ | |
2907 | if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) { | |
2908 | /* This order matches mac80211's queue priority, so we can | |
2909 | * directly use the mac80211 queue number without any mapping */ | |
e0d687bd | 2910 | txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO); |
22d8d9f8 | 2911 | if (IS_ERR(txq)) { |
e0d687bd | 2912 | ATH5K_ERR(ah, "can't setup xmit queue\n"); |
22d8d9f8 BR |
2913 | ret = PTR_ERR(txq); |
2914 | goto err_queues; | |
2915 | } | |
e0d687bd | 2916 | txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI); |
22d8d9f8 | 2917 | if (IS_ERR(txq)) { |
e0d687bd | 2918 | ATH5K_ERR(ah, "can't setup xmit queue\n"); |
22d8d9f8 BR |
2919 | ret = PTR_ERR(txq); |
2920 | goto err_queues; | |
2921 | } | |
e0d687bd | 2922 | txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); |
22d8d9f8 | 2923 | if (IS_ERR(txq)) { |
e0d687bd | 2924 | ATH5K_ERR(ah, "can't setup xmit queue\n"); |
22d8d9f8 BR |
2925 | ret = PTR_ERR(txq); |
2926 | goto err_queues; | |
2927 | } | |
e0d687bd | 2928 | txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); |
22d8d9f8 | 2929 | if (IS_ERR(txq)) { |
e0d687bd | 2930 | ATH5K_ERR(ah, "can't setup xmit queue\n"); |
22d8d9f8 BR |
2931 | ret = PTR_ERR(txq); |
2932 | goto err_queues; | |
2933 | } | |
2934 | hw->queues = 4; | |
2935 | } else { | |
2936 | /* older hardware (5210) can only support one data queue */ | |
e0d687bd | 2937 | txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); |
22d8d9f8 | 2938 | if (IS_ERR(txq)) { |
e0d687bd | 2939 | ATH5K_ERR(ah, "can't setup xmit queue\n"); |
22d8d9f8 BR |
2940 | ret = PTR_ERR(txq); |
2941 | goto err_queues; | |
2942 | } | |
2943 | hw->queues = 1; | |
2944 | } | |
fa1c114f | 2945 | |
e0d687bd PR |
2946 | tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah); |
2947 | tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah); | |
e0d687bd PR |
2948 | tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah); |
2949 | tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah); | |
be009370 | 2950 | |
e0d687bd | 2951 | INIT_WORK(&ah->reset_work, ath5k_reset_work); |
ce169aca | 2952 | INIT_WORK(&ah->calib_work, ath5k_calibrate_work); |
e0d687bd | 2953 | INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work); |
fa1c114f | 2954 | |
fa9bfd61 | 2955 | ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac); |
8a63facc | 2956 | if (ret) { |
e0d687bd | 2957 | ATH5K_ERR(ah, "unable to read address from EEPROM\n"); |
8a63facc | 2958 | goto err_queues; |
e30eb4ab | 2959 | } |
2bed03eb | 2960 | |
8a63facc BC |
2961 | SET_IEEE80211_PERM_ADDR(hw, mac); |
2962 | /* All MAC address bits matter for ACKs */ | |
e0d687bd | 2963 | ath5k_update_bssid_mask_and_opmode(ah, NULL); |
8a63facc BC |
2964 | |
2965 | regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; | |
2966 | ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); | |
2967 | if (ret) { | |
e0d687bd | 2968 | ATH5K_ERR(ah, "can't initialize regulatory system\n"); |
8a63facc BC |
2969 | goto err_queues; |
2970 | } | |
2971 | ||
2972 | ret = ieee80211_register_hw(hw); | |
2973 | if (ret) { | |
e0d687bd | 2974 | ATH5K_ERR(ah, "can't register ieee80211 hw\n"); |
8a63facc BC |
2975 | goto err_queues; |
2976 | } | |
2977 | ||
2978 | if (!ath_is_world_regd(regulatory)) | |
2979 | regulatory_hint(hw->wiphy, regulatory->alpha2); | |
2980 | ||
e0d687bd | 2981 | ath5k_init_leds(ah); |
8a63facc | 2982 | |
e0d687bd | 2983 | ath5k_sysfs_register(ah); |
8a63facc BC |
2984 | |
2985 | return 0; | |
2986 | err_queues: | |
e0d687bd | 2987 | ath5k_txq_release(ah); |
8a63facc | 2988 | err_bhal: |
e0d687bd | 2989 | ath5k_hw_release_tx_queue(ah, ah->bhalq); |
8a63facc | 2990 | err_desc: |
e0d687bd | 2991 | ath5k_desc_free(ah); |
8a63facc BC |
2992 | err: |
2993 | return ret; | |
2994 | } | |
2995 | ||
132b1c3e | 2996 | void |
bb1f3ad9 | 2997 | ath5k_deinit_ah(struct ath5k_hw *ah) |
8a63facc | 2998 | { |
e0d687bd | 2999 | struct ieee80211_hw *hw = ah->hw; |
8a63facc BC |
3000 | |
3001 | /* | |
3002 | * NB: the order of these is important: | |
3003 | * o call the 802.11 layer before detaching ath5k_hw to | |
3004 | * ensure callbacks into the driver to delete global | |
3005 | * key cache entries can be handled | |
3006 | * o reclaim the tx queue data structures after calling | |
3007 | * the 802.11 layer as we'll get called back to reclaim | |
3008 | * node state and potentially want to use them | |
3009 | * o to cleanup the tx queues the hal is called, so detach | |
3010 | * it last | |
3011 | * XXX: ??? detach ath5k_hw ??? | |
3012 | * Other than that, it's straightforward... | |
3013 | */ | |
3014 | ieee80211_unregister_hw(hw); | |
e0d687bd PR |
3015 | ath5k_desc_free(ah); |
3016 | ath5k_txq_release(ah); | |
3017 | ath5k_hw_release_tx_queue(ah, ah->bhalq); | |
3018 | ath5k_unregister_leds(ah); | |
8a63facc | 3019 | |
e0d687bd | 3020 | ath5k_sysfs_unregister(ah); |
8a63facc BC |
3021 | /* |
3022 | * NB: can't reclaim these until after ieee80211_ifdetach | |
3023 | * returns because we'll get called back to reclaim node | |
3024 | * state and potentially want to use them. | |
3025 | */ | |
e0d687bd PR |
3026 | ath5k_hw_deinit(ah); |
3027 | free_irq(ah->irq, ah); | |
8a63facc BC |
3028 | } |
3029 | ||
cd2c5486 | 3030 | bool |
e0d687bd | 3031 | ath5k_any_vif_assoc(struct ath5k_hw *ah) |
b1ae1edf | 3032 | { |
e4b0b32a | 3033 | struct ath5k_vif_iter_data iter_data; |
b1ae1edf BG |
3034 | iter_data.hw_macaddr = NULL; |
3035 | iter_data.any_assoc = false; | |
3036 | iter_data.need_set_hw_addr = false; | |
3037 | iter_data.found_active = true; | |
3038 | ||
8b2c9824 JB |
3039 | ieee80211_iterate_active_interfaces_atomic( |
3040 | ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL, | |
3041 | ath5k_vif_iter, &iter_data); | |
b1ae1edf BG |
3042 | return iter_data.any_assoc; |
3043 | } | |
3044 | ||
cd2c5486 | 3045 | void |
f5cbc8ba | 3046 | ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable) |
8a63facc | 3047 | { |
e0d687bd | 3048 | struct ath5k_hw *ah = hw->priv; |
8a63facc BC |
3049 | u32 rfilt; |
3050 | rfilt = ath5k_hw_get_rx_filter(ah); | |
3051 | if (enable) | |
3052 | rfilt |= AR5K_RX_FILTER_BEACON; | |
3053 | else | |
3054 | rfilt &= ~AR5K_RX_FILTER_BEACON; | |
3055 | ath5k_hw_set_rx_filter(ah, rfilt); | |
e0d687bd | 3056 | ah->filter_flags = rfilt; |
8a63facc | 3057 | } |
227842d1 JP |
3058 | |
3059 | void _ath5k_printk(const struct ath5k_hw *ah, const char *level, | |
3060 | const char *fmt, ...) | |
3061 | { | |
3062 | struct va_format vaf; | |
3063 | va_list args; | |
3064 | ||
3065 | va_start(args, fmt); | |
3066 | ||
3067 | vaf.fmt = fmt; | |
3068 | vaf.va = &args; | |
3069 | ||
3070 | if (ah && ah->hw) | |
3071 | printk("%s" pr_fmt("%s: %pV"), | |
3072 | level, wiphy_name(ah->hw->wiphy), &vaf); | |
3073 | else | |
3074 | printk("%s" pr_fmt("%pV"), level, &vaf); | |
3075 | ||
3076 | va_end(args); | |
3077 | } |