Commit | Line | Data |
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fa1c114f JS |
1 | /*- |
2 | * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting | |
3 | * Copyright (c) 2004-2005 Atheros Communications, Inc. | |
4 | * Copyright (c) 2006 Devicescape Software, Inc. | |
5 | * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> | |
6 | * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu> | |
7 | * | |
8 | * All rights reserved. | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or without | |
11 | * modification, are permitted provided that the following conditions | |
12 | * are met: | |
13 | * 1. Redistributions of source code must retain the above copyright | |
14 | * notice, this list of conditions and the following disclaimer, | |
15 | * without modification. | |
16 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer | |
17 | * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any | |
18 | * redistribution must be conditioned upon including a substantially | |
19 | * similar Disclaimer requirement for further binary redistribution. | |
20 | * 3. Neither the names of the above-listed copyright holders nor the names | |
21 | * of any contributors may be used to endorse or promote products derived | |
22 | * from this software without specific prior written permission. | |
23 | * | |
24 | * Alternatively, this software may be distributed under the terms of the | |
25 | * GNU General Public License ("GPL") version 2 as published by the Free | |
26 | * Software Foundation. | |
27 | * | |
28 | * NO WARRANTY | |
29 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
30 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
31 | * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY | |
32 | * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL | |
33 | * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, | |
34 | * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
35 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
36 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER | |
37 | * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
38 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
39 | * THE POSSIBILITY OF SUCH DAMAGES. | |
40 | * | |
41 | */ | |
42 | ||
fa1c114f JS |
43 | #include <linux/module.h> |
44 | #include <linux/delay.h> | |
274c7c36 | 45 | #include <linux/hardirq.h> |
fa1c114f | 46 | #include <linux/if.h> |
274c7c36 | 47 | #include <linux/io.h> |
fa1c114f JS |
48 | #include <linux/netdevice.h> |
49 | #include <linux/cache.h> | |
fa1c114f JS |
50 | #include <linux/ethtool.h> |
51 | #include <linux/uaccess.h> | |
5a0e3ad6 | 52 | #include <linux/slab.h> |
b1ae1edf | 53 | #include <linux/etherdevice.h> |
fa1c114f JS |
54 | |
55 | #include <net/ieee80211_radiotap.h> | |
56 | ||
57 | #include <asm/unaligned.h> | |
58 | ||
59 | #include "base.h" | |
60 | #include "reg.h" | |
61 | #include "debug.h" | |
2111ac0d | 62 | #include "ani.h" |
62c58fb4 | 63 | #include "../debug.h" |
fa1c114f | 64 | |
9ad9a26e | 65 | static int modparam_nohwcrypt; |
46802a4f | 66 | module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO); |
9ad9a26e | 67 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); |
fa1c114f | 68 | |
42639fcd | 69 | static int modparam_all_channels; |
46802a4f | 70 | module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO); |
42639fcd BC |
71 | MODULE_PARM_DESC(all_channels, "Expose all channels the device can use."); |
72 | ||
fa1c114f JS |
73 | /* Module info */ |
74 | MODULE_AUTHOR("Jiri Slaby"); | |
75 | MODULE_AUTHOR("Nick Kossifidis"); | |
76 | MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); | |
77 | MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards"); | |
78 | MODULE_LICENSE("Dual BSD/GPL"); | |
0d5f0316 | 79 | MODULE_VERSION("0.6.0 (EXPERIMENTAL)"); |
fa1c114f | 80 | |
132b1c3e | 81 | static int ath5k_init(struct ieee80211_hw *hw); |
8aec7af9 NK |
82 | static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan, |
83 | bool skip_pcu); | |
8a63facc BC |
84 | static int ath5k_beacon_update(struct ieee80211_hw *hw, |
85 | struct ieee80211_vif *vif); | |
86 | static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf); | |
fa1c114f | 87 | |
fa1c114f | 88 | /* Known SREVs */ |
2c91108c | 89 | static const struct ath5k_srev_name srev_names[] = { |
a0b907ee FF |
90 | #ifdef CONFIG_ATHEROS_AR231X |
91 | { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 }, | |
92 | { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 }, | |
93 | { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 }, | |
94 | { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 }, | |
95 | { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 }, | |
96 | { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 }, | |
97 | { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 }, | |
98 | #else | |
1bef016a NK |
99 | { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 }, |
100 | { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 }, | |
101 | { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A }, | |
102 | { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B }, | |
103 | { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 }, | |
104 | { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 }, | |
105 | { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 }, | |
106 | { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A }, | |
107 | { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 }, | |
108 | { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 }, | |
109 | { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 }, | |
110 | { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 }, | |
111 | { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 }, | |
112 | { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 }, | |
113 | { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 }, | |
114 | { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 }, | |
115 | { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 }, | |
116 | { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 }, | |
a0b907ee | 117 | #endif |
1bef016a | 118 | { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN }, |
fa1c114f JS |
119 | { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, |
120 | { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, | |
1bef016a | 121 | { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A }, |
fa1c114f JS |
122 | { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, |
123 | { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, | |
124 | { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, | |
1bef016a | 125 | { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B }, |
fa1c114f JS |
126 | { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, |
127 | { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, | |
1bef016a NK |
128 | { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B }, |
129 | { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 }, | |
130 | { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 }, | |
1bef016a | 131 | { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 }, |
fa1c114f | 132 | { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, |
a0b907ee FF |
133 | #ifdef CONFIG_ATHEROS_AR231X |
134 | { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 }, | |
135 | { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 }, | |
136 | #endif | |
fa1c114f JS |
137 | { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, |
138 | }; | |
139 | ||
2c91108c | 140 | static const struct ieee80211_rate ath5k_rates[] = { |
63266a65 BR |
141 | { .bitrate = 10, |
142 | .hw_value = ATH5K_RATE_CODE_1M, }, | |
143 | { .bitrate = 20, | |
144 | .hw_value = ATH5K_RATE_CODE_2M, | |
145 | .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE, | |
146 | .flags = IEEE80211_RATE_SHORT_PREAMBLE }, | |
147 | { .bitrate = 55, | |
148 | .hw_value = ATH5K_RATE_CODE_5_5M, | |
149 | .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE, | |
150 | .flags = IEEE80211_RATE_SHORT_PREAMBLE }, | |
151 | { .bitrate = 110, | |
152 | .hw_value = ATH5K_RATE_CODE_11M, | |
153 | .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE, | |
154 | .flags = IEEE80211_RATE_SHORT_PREAMBLE }, | |
155 | { .bitrate = 60, | |
156 | .hw_value = ATH5K_RATE_CODE_6M, | |
157 | .flags = 0 }, | |
158 | { .bitrate = 90, | |
159 | .hw_value = ATH5K_RATE_CODE_9M, | |
160 | .flags = 0 }, | |
161 | { .bitrate = 120, | |
162 | .hw_value = ATH5K_RATE_CODE_12M, | |
163 | .flags = 0 }, | |
164 | { .bitrate = 180, | |
165 | .hw_value = ATH5K_RATE_CODE_18M, | |
166 | .flags = 0 }, | |
167 | { .bitrate = 240, | |
168 | .hw_value = ATH5K_RATE_CODE_24M, | |
169 | .flags = 0 }, | |
170 | { .bitrate = 360, | |
171 | .hw_value = ATH5K_RATE_CODE_36M, | |
172 | .flags = 0 }, | |
173 | { .bitrate = 480, | |
174 | .hw_value = ATH5K_RATE_CODE_48M, | |
175 | .flags = 0 }, | |
176 | { .bitrate = 540, | |
177 | .hw_value = ATH5K_RATE_CODE_54M, | |
178 | .flags = 0 }, | |
179 | /* XR missing */ | |
180 | }; | |
181 | ||
9e4e43f2 | 182 | static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc, |
fa1c114f JS |
183 | struct ath5k_buf *bf) |
184 | { | |
185 | BUG_ON(!bf); | |
186 | if (!bf->skb) | |
187 | return; | |
aeae4ac9 FF |
188 | dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len, |
189 | DMA_TO_DEVICE); | |
00482973 | 190 | dev_kfree_skb_any(bf->skb); |
fa1c114f | 191 | bf->skb = NULL; |
39d63f2a BR |
192 | bf->skbaddr = 0; |
193 | bf->desc->ds_data = 0; | |
fa1c114f JS |
194 | } |
195 | ||
9e4e43f2 | 196 | static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc, |
a6c8d375 FF |
197 | struct ath5k_buf *bf) |
198 | { | |
cc861f74 LR |
199 | struct ath5k_hw *ah = sc->ah; |
200 | struct ath_common *common = ath5k_hw_common(ah); | |
201 | ||
a6c8d375 FF |
202 | BUG_ON(!bf); |
203 | if (!bf->skb) | |
204 | return; | |
aeae4ac9 FF |
205 | dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize, |
206 | DMA_FROM_DEVICE); | |
a6c8d375 FF |
207 | dev_kfree_skb_any(bf->skb); |
208 | bf->skb = NULL; | |
39d63f2a BR |
209 | bf->skbaddr = 0; |
210 | bf->desc->ds_data = 0; | |
a6c8d375 FF |
211 | } |
212 | ||
213 | ||
fa1c114f JS |
214 | static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) |
215 | { | |
216 | u64 tsf = ath5k_hw_get_tsf64(ah); | |
217 | ||
218 | if ((tsf & 0x7fff) < rstamp) | |
219 | tsf -= 0x8000; | |
220 | ||
221 | return (tsf & ~0x7fff) | rstamp; | |
222 | } | |
223 | ||
e5b046d8 | 224 | const char * |
fa1c114f JS |
225 | ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val) |
226 | { | |
227 | const char *name = "xxxxx"; | |
228 | unsigned int i; | |
229 | ||
230 | for (i = 0; i < ARRAY_SIZE(srev_names); i++) { | |
231 | if (srev_names[i].sr_type != type) | |
232 | continue; | |
75d0edb8 NK |
233 | |
234 | if ((val & 0xf0) == srev_names[i].sr_val) | |
235 | name = srev_names[i].sr_name; | |
236 | ||
237 | if ((val & 0xff) == srev_names[i].sr_val) { | |
fa1c114f JS |
238 | name = srev_names[i].sr_name; |
239 | break; | |
240 | } | |
241 | } | |
242 | ||
243 | return name; | |
244 | } | |
e5aa8474 LR |
245 | static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset) |
246 | { | |
247 | struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; | |
248 | return ath5k_hw_reg_read(ah, reg_offset); | |
249 | } | |
250 | ||
251 | static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) | |
252 | { | |
253 | struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; | |
254 | ath5k_hw_reg_write(ah, val, reg_offset); | |
255 | } | |
256 | ||
257 | static const struct ath_ops ath5k_common_ops = { | |
258 | .read = ath5k_ioread32, | |
259 | .write = ath5k_iowrite32, | |
260 | }; | |
fa1c114f | 261 | |
8a63facc BC |
262 | /***********************\ |
263 | * Driver Initialization * | |
264 | \***********************/ | |
265 | ||
266 | static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) | |
fa1c114f | 267 | { |
8a63facc BC |
268 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); |
269 | struct ath5k_softc *sc = hw->priv; | |
270 | struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah); | |
fa1c114f | 271 | |
8a63facc BC |
272 | return ath_reg_notifier_apply(wiphy, request, regulatory); |
273 | } | |
6ccf15a1 | 274 | |
8a63facc BC |
275 | /********************\ |
276 | * Channel/mode setup * | |
277 | \********************/ | |
fa1c114f | 278 | |
8a63facc BC |
279 | /* |
280 | * Convert IEEE channel number to MHz frequency. | |
281 | */ | |
282 | static inline short | |
283 | ath5k_ieee2mhz(short chan) | |
284 | { | |
285 | if (chan <= 14 || chan >= 27) | |
286 | return ieee80211chan2mhz(chan); | |
287 | else | |
288 | return 2212 + chan * 20; | |
289 | } | |
fa1c114f | 290 | |
8a63facc BC |
291 | /* |
292 | * Returns true for the channel numbers used without all_channels modparam. | |
293 | */ | |
294 | static bool ath5k_is_standard_channel(short chan) | |
295 | { | |
296 | return ((chan <= 14) || | |
297 | /* UNII 1,2 */ | |
298 | ((chan & 3) == 0 && chan >= 36 && chan <= 64) || | |
299 | /* midband */ | |
300 | ((chan & 3) == 0 && chan >= 100 && chan <= 140) || | |
301 | /* UNII-3 */ | |
302 | ((chan & 3) == 1 && chan >= 149 && chan <= 165)); | |
303 | } | |
fa1c114f | 304 | |
8a63facc BC |
305 | static unsigned int |
306 | ath5k_copy_channels(struct ath5k_hw *ah, | |
307 | struct ieee80211_channel *channels, | |
308 | unsigned int mode, | |
309 | unsigned int max) | |
310 | { | |
311 | unsigned int i, count, size, chfreq, freq, ch; | |
fa1c114f | 312 | |
8a63facc BC |
313 | if (!test_bit(mode, ah->ah_modes)) |
314 | return 0; | |
fa1c114f | 315 | |
8a63facc BC |
316 | switch (mode) { |
317 | case AR5K_MODE_11A: | |
8a63facc BC |
318 | /* 1..220, but 2GHz frequencies are filtered by check_channel */ |
319 | size = 220 ; | |
320 | chfreq = CHANNEL_5GHZ; | |
321 | break; | |
322 | case AR5K_MODE_11B: | |
323 | case AR5K_MODE_11G: | |
8a63facc BC |
324 | size = 26; |
325 | chfreq = CHANNEL_2GHZ; | |
326 | break; | |
327 | default: | |
328 | ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n"); | |
329 | return 0; | |
fa1c114f JS |
330 | } |
331 | ||
8a63facc BC |
332 | for (i = 0, count = 0; i < size && max > 0; i++) { |
333 | ch = i + 1 ; | |
334 | freq = ath5k_ieee2mhz(ch); | |
fa1c114f | 335 | |
8a63facc BC |
336 | /* Check if channel is supported by the chipset */ |
337 | if (!ath5k_channel_ok(ah, freq, chfreq)) | |
338 | continue; | |
f59ac048 | 339 | |
8a63facc BC |
340 | if (!modparam_all_channels && !ath5k_is_standard_channel(ch)) |
341 | continue; | |
f59ac048 | 342 | |
8a63facc BC |
343 | /* Write channel info and increment counter */ |
344 | channels[count].center_freq = freq; | |
345 | channels[count].band = (chfreq == CHANNEL_2GHZ) ? | |
346 | IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; | |
347 | switch (mode) { | |
348 | case AR5K_MODE_11A: | |
349 | case AR5K_MODE_11G: | |
350 | channels[count].hw_value = chfreq | CHANNEL_OFDM; | |
351 | break; | |
8a63facc BC |
352 | case AR5K_MODE_11B: |
353 | channels[count].hw_value = CHANNEL_B; | |
354 | } | |
fa1c114f | 355 | |
8a63facc BC |
356 | count++; |
357 | max--; | |
358 | } | |
fa1c114f | 359 | |
8a63facc BC |
360 | return count; |
361 | } | |
fa1c114f | 362 | |
8a63facc BC |
363 | static void |
364 | ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b) | |
365 | { | |
366 | u8 i; | |
fa1c114f | 367 | |
8a63facc BC |
368 | for (i = 0; i < AR5K_MAX_RATES; i++) |
369 | sc->rate_idx[b->band][i] = -1; | |
fa1c114f | 370 | |
8a63facc BC |
371 | for (i = 0; i < b->n_bitrates; i++) { |
372 | sc->rate_idx[b->band][b->bitrates[i].hw_value] = i; | |
373 | if (b->bitrates[i].hw_value_short) | |
374 | sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; | |
fa1c114f | 375 | } |
8a63facc | 376 | } |
fa1c114f | 377 | |
8a63facc BC |
378 | static int |
379 | ath5k_setup_bands(struct ieee80211_hw *hw) | |
380 | { | |
381 | struct ath5k_softc *sc = hw->priv; | |
382 | struct ath5k_hw *ah = sc->ah; | |
383 | struct ieee80211_supported_band *sband; | |
384 | int max_c, count_c = 0; | |
385 | int i; | |
fa1c114f | 386 | |
8a63facc BC |
387 | BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS); |
388 | max_c = ARRAY_SIZE(sc->channels); | |
db719718 | 389 | |
8a63facc BC |
390 | /* 2GHz band */ |
391 | sband = &sc->sbands[IEEE80211_BAND_2GHZ]; | |
392 | sband->band = IEEE80211_BAND_2GHZ; | |
393 | sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0]; | |
9adca126 | 394 | |
8a63facc BC |
395 | if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) { |
396 | /* G mode */ | |
397 | memcpy(sband->bitrates, &ath5k_rates[0], | |
398 | sizeof(struct ieee80211_rate) * 12); | |
399 | sband->n_bitrates = 12; | |
2f7fe870 | 400 | |
8a63facc BC |
401 | sband->channels = sc->channels; |
402 | sband->n_channels = ath5k_copy_channels(ah, sband->channels, | |
403 | AR5K_MODE_11G, max_c); | |
fa1c114f | 404 | |
8a63facc BC |
405 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; |
406 | count_c = sband->n_channels; | |
407 | max_c -= count_c; | |
408 | } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) { | |
409 | /* B mode */ | |
410 | memcpy(sband->bitrates, &ath5k_rates[0], | |
411 | sizeof(struct ieee80211_rate) * 4); | |
412 | sband->n_bitrates = 4; | |
fa1c114f | 413 | |
8a63facc BC |
414 | /* 5211 only supports B rates and uses 4bit rate codes |
415 | * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B) | |
416 | * fix them up here: | |
417 | */ | |
418 | if (ah->ah_version == AR5K_AR5211) { | |
419 | for (i = 0; i < 4; i++) { | |
420 | sband->bitrates[i].hw_value = | |
421 | sband->bitrates[i].hw_value & 0xF; | |
422 | sband->bitrates[i].hw_value_short = | |
423 | sband->bitrates[i].hw_value_short & 0xF; | |
fa1c114f JS |
424 | } |
425 | } | |
fa1c114f | 426 | |
8a63facc BC |
427 | sband->channels = sc->channels; |
428 | sband->n_channels = ath5k_copy_channels(ah, sband->channels, | |
429 | AR5K_MODE_11B, max_c); | |
fa1c114f | 430 | |
8a63facc BC |
431 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; |
432 | count_c = sband->n_channels; | |
433 | max_c -= count_c; | |
434 | } | |
435 | ath5k_setup_rate_idx(sc, sband); | |
fa1c114f | 436 | |
8a63facc BC |
437 | /* 5GHz band, A mode */ |
438 | if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) { | |
439 | sband = &sc->sbands[IEEE80211_BAND_5GHZ]; | |
440 | sband->band = IEEE80211_BAND_5GHZ; | |
441 | sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0]; | |
fa1c114f | 442 | |
8a63facc BC |
443 | memcpy(sband->bitrates, &ath5k_rates[4], |
444 | sizeof(struct ieee80211_rate) * 8); | |
445 | sband->n_bitrates = 8; | |
fa1c114f | 446 | |
8a63facc BC |
447 | sband->channels = &sc->channels[count_c]; |
448 | sband->n_channels = ath5k_copy_channels(ah, sband->channels, | |
449 | AR5K_MODE_11A, max_c); | |
fa1c114f | 450 | |
8a63facc BC |
451 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband; |
452 | } | |
453 | ath5k_setup_rate_idx(sc, sband); | |
454 | ||
455 | ath5k_debug_dump_bands(sc); | |
fa1c114f | 456 | |
fa1c114f JS |
457 | return 0; |
458 | } | |
459 | ||
8a63facc BC |
460 | /* |
461 | * Set/change channels. We always reset the chip. | |
462 | * To accomplish this we must first cleanup any pending DMA, | |
463 | * then restart stuff after a la ath5k_init. | |
464 | * | |
465 | * Called with sc->lock. | |
466 | */ | |
467 | static int | |
468 | ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan) | |
469 | { | |
470 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, | |
471 | "channel set, resetting (%u -> %u MHz)\n", | |
472 | sc->curchan->center_freq, chan->center_freq); | |
473 | ||
8451d22d | 474 | /* |
8a63facc BC |
475 | * To switch channels clear any pending DMA operations; |
476 | * wait long enough for the RX fifo to drain, reset the | |
477 | * hardware at the new frequency, and then re-enable | |
478 | * the relevant bits of the h/w. | |
8451d22d | 479 | */ |
8aec7af9 | 480 | return ath5k_reset(sc, chan, true); |
fa1c114f | 481 | } |
fa1c114f | 482 | |
8a63facc BC |
483 | static void |
484 | ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode) | |
f769c36b | 485 | { |
8a63facc | 486 | sc->curmode = mode; |
f769c36b | 487 | |
8a63facc BC |
488 | if (mode == AR5K_MODE_11A) { |
489 | sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ]; | |
490 | } else { | |
491 | sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ]; | |
492 | } | |
f769c36b BC |
493 | } |
494 | ||
b1ae1edf BG |
495 | struct ath_vif_iter_data { |
496 | const u8 *hw_macaddr; | |
497 | u8 mask[ETH_ALEN]; | |
498 | u8 active_mac[ETH_ALEN]; /* first active MAC */ | |
499 | bool need_set_hw_addr; | |
500 | bool found_active; | |
501 | bool any_assoc; | |
62c58fb4 | 502 | enum nl80211_iftype opmode; |
b1ae1edf BG |
503 | }; |
504 | ||
505 | static void ath_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) | |
506 | { | |
507 | struct ath_vif_iter_data *iter_data = data; | |
508 | int i; | |
62c58fb4 | 509 | struct ath5k_vif *avf = (void *)vif->drv_priv; |
b1ae1edf BG |
510 | |
511 | if (iter_data->hw_macaddr) | |
512 | for (i = 0; i < ETH_ALEN; i++) | |
513 | iter_data->mask[i] &= | |
514 | ~(iter_data->hw_macaddr[i] ^ mac[i]); | |
515 | ||
516 | if (!iter_data->found_active) { | |
517 | iter_data->found_active = true; | |
518 | memcpy(iter_data->active_mac, mac, ETH_ALEN); | |
519 | } | |
520 | ||
521 | if (iter_data->need_set_hw_addr && iter_data->hw_macaddr) | |
522 | if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0) | |
523 | iter_data->need_set_hw_addr = false; | |
524 | ||
525 | if (!iter_data->any_assoc) { | |
b1ae1edf BG |
526 | if (avf->assoc) |
527 | iter_data->any_assoc = true; | |
528 | } | |
62c58fb4 BG |
529 | |
530 | /* Calculate combined mode - when APs are active, operate in AP mode. | |
531 | * Otherwise use the mode of the new interface. This can currently | |
532 | * only deal with combinations of APs and STAs. Only one ad-hoc | |
7afbb2f0 | 533 | * interfaces is allowed. |
62c58fb4 BG |
534 | */ |
535 | if (avf->opmode == NL80211_IFTYPE_AP) | |
536 | iter_data->opmode = NL80211_IFTYPE_AP; | |
537 | else | |
538 | if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED) | |
539 | iter_data->opmode = avf->opmode; | |
b1ae1edf BG |
540 | } |
541 | ||
14fb7c17 LR |
542 | static void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc, |
543 | struct ieee80211_vif *vif) | |
b1ae1edf BG |
544 | { |
545 | struct ath_common *common = ath5k_hw_common(sc->ah); | |
546 | struct ath_vif_iter_data iter_data; | |
547 | ||
548 | /* | |
549 | * Use the hardware MAC address as reference, the hardware uses it | |
550 | * together with the BSSID mask when matching addresses. | |
551 | */ | |
552 | iter_data.hw_macaddr = common->macaddr; | |
553 | memset(&iter_data.mask, 0xff, ETH_ALEN); | |
554 | iter_data.found_active = false; | |
555 | iter_data.need_set_hw_addr = true; | |
62c58fb4 | 556 | iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED; |
b1ae1edf BG |
557 | |
558 | if (vif) | |
559 | ath_vif_iter(&iter_data, vif->addr, vif); | |
560 | ||
561 | /* Get list of all active MAC addresses */ | |
562 | ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter, | |
563 | &iter_data); | |
564 | memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN); | |
565 | ||
62c58fb4 BG |
566 | sc->opmode = iter_data.opmode; |
567 | if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED) | |
568 | /* Nothing active, default to station mode */ | |
569 | sc->opmode = NL80211_IFTYPE_STATION; | |
570 | ||
7afbb2f0 BG |
571 | ath5k_hw_set_opmode(sc->ah, sc->opmode); |
572 | ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n", | |
573 | sc->opmode, ath_opmode_to_string(sc->opmode)); | |
62c58fb4 | 574 | |
b1ae1edf BG |
575 | if (iter_data.need_set_hw_addr && iter_data.found_active) |
576 | ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac); | |
577 | ||
62c58fb4 BG |
578 | if (ath5k_hw_hasbssidmask(sc->ah)) |
579 | ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask); | |
b1ae1edf BG |
580 | } |
581 | ||
8a63facc | 582 | static void |
b1ae1edf | 583 | ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif) |
fa1c114f | 584 | { |
fa1c114f | 585 | struct ath5k_hw *ah = sc->ah; |
8a63facc | 586 | u32 rfilt; |
fa1c114f | 587 | |
8a63facc BC |
588 | /* configure rx filter */ |
589 | rfilt = sc->filter_flags; | |
590 | ath5k_hw_set_rx_filter(ah, rfilt); | |
8a63facc | 591 | ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); |
62c58fb4 BG |
592 | |
593 | ath5k_update_bssid_mask_and_opmode(sc, vif); | |
8a63facc | 594 | } |
fa1c114f | 595 | |
8a63facc BC |
596 | static inline int |
597 | ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) | |
598 | { | |
599 | int rix; | |
fa1c114f | 600 | |
8a63facc BC |
601 | /* return base rate on errors */ |
602 | if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES, | |
603 | "hw_rix out of bounds: %x\n", hw_rix)) | |
604 | return 0; | |
605 | ||
606 | rix = sc->rate_idx[sc->curband->band][hw_rix]; | |
607 | if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix)) | |
608 | rix = 0; | |
609 | ||
610 | return rix; | |
611 | } | |
612 | ||
613 | /***************\ | |
614 | * Buffers setup * | |
615 | \***************/ | |
616 | ||
617 | static | |
618 | struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr) | |
619 | { | |
620 | struct ath_common *common = ath5k_hw_common(sc->ah); | |
621 | struct sk_buff *skb; | |
fa1c114f JS |
622 | |
623 | /* | |
8a63facc BC |
624 | * Allocate buffer with headroom_needed space for the |
625 | * fake physical layer header at the start. | |
fa1c114f | 626 | */ |
8a63facc BC |
627 | skb = ath_rxbuf_alloc(common, |
628 | common->rx_bufsize, | |
629 | GFP_ATOMIC); | |
fa1c114f | 630 | |
8a63facc BC |
631 | if (!skb) { |
632 | ATH5K_ERR(sc, "can't alloc skbuff of size %u\n", | |
633 | common->rx_bufsize); | |
634 | return NULL; | |
fa1c114f JS |
635 | } |
636 | ||
aeae4ac9 | 637 | *skb_addr = dma_map_single(sc->dev, |
8a63facc | 638 | skb->data, common->rx_bufsize, |
aeae4ac9 FF |
639 | DMA_FROM_DEVICE); |
640 | ||
641 | if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) { | |
8a63facc BC |
642 | ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__); |
643 | dev_kfree_skb(skb); | |
644 | return NULL; | |
0e149cf5 | 645 | } |
8a63facc BC |
646 | return skb; |
647 | } | |
0e149cf5 | 648 | |
8a63facc BC |
649 | static int |
650 | ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) | |
651 | { | |
652 | struct ath5k_hw *ah = sc->ah; | |
653 | struct sk_buff *skb = bf->skb; | |
654 | struct ath5k_desc *ds; | |
655 | int ret; | |
fa1c114f | 656 | |
8a63facc BC |
657 | if (!skb) { |
658 | skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr); | |
659 | if (!skb) | |
660 | return -ENOMEM; | |
661 | bf->skb = skb; | |
f769c36b BC |
662 | } |
663 | ||
8a63facc BC |
664 | /* |
665 | * Setup descriptors. For receive we always terminate | |
666 | * the descriptor list with a self-linked entry so we'll | |
667 | * not get overrun under high load (as can happen with a | |
668 | * 5212 when ANI processing enables PHY error frames). | |
669 | * | |
670 | * To ensure the last descriptor is self-linked we create | |
671 | * each descriptor as self-linked and add it to the end. As | |
672 | * each additional descriptor is added the previous self-linked | |
673 | * entry is "fixed" naturally. This should be safe even | |
674 | * if DMA is happening. When processing RX interrupts we | |
675 | * never remove/process the last, self-linked, entry on the | |
676 | * descriptor list. This ensures the hardware always has | |
677 | * someplace to write a new frame. | |
678 | */ | |
679 | ds = bf->desc; | |
680 | ds->ds_link = bf->daddr; /* link to self */ | |
681 | ds->ds_data = bf->skbaddr; | |
682 | ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0); | |
fa1c114f | 683 | if (ret) { |
8a63facc BC |
684 | ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__); |
685 | return ret; | |
fa1c114f JS |
686 | } |
687 | ||
8a63facc BC |
688 | if (sc->rxlink != NULL) |
689 | *sc->rxlink = bf->daddr; | |
690 | sc->rxlink = &ds->ds_link; | |
fa1c114f | 691 | return 0; |
fa1c114f JS |
692 | } |
693 | ||
8a63facc | 694 | static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb) |
fa1c114f | 695 | { |
8a63facc BC |
696 | struct ieee80211_hdr *hdr; |
697 | enum ath5k_pkt_type htype; | |
698 | __le16 fc; | |
fa1c114f | 699 | |
8a63facc BC |
700 | hdr = (struct ieee80211_hdr *)skb->data; |
701 | fc = hdr->frame_control; | |
fa1c114f | 702 | |
8a63facc BC |
703 | if (ieee80211_is_beacon(fc)) |
704 | htype = AR5K_PKT_TYPE_BEACON; | |
705 | else if (ieee80211_is_probe_resp(fc)) | |
706 | htype = AR5K_PKT_TYPE_PROBE_RESP; | |
707 | else if (ieee80211_is_atim(fc)) | |
708 | htype = AR5K_PKT_TYPE_ATIM; | |
709 | else if (ieee80211_is_pspoll(fc)) | |
710 | htype = AR5K_PKT_TYPE_PSPOLL; | |
fa1c114f | 711 | else |
8a63facc | 712 | htype = AR5K_PKT_TYPE_NORMAL; |
fa1c114f | 713 | |
8a63facc | 714 | return htype; |
42639fcd BC |
715 | } |
716 | ||
8a63facc BC |
717 | static int |
718 | ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, | |
719 | struct ath5k_txq *txq, int padsize) | |
fa1c114f | 720 | { |
8a63facc BC |
721 | struct ath5k_hw *ah = sc->ah; |
722 | struct ath5k_desc *ds = bf->desc; | |
723 | struct sk_buff *skb = bf->skb; | |
724 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
725 | unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; | |
726 | struct ieee80211_rate *rate; | |
727 | unsigned int mrr_rate[3], mrr_tries[3]; | |
728 | int i, ret; | |
729 | u16 hw_rate; | |
730 | u16 cts_rate = 0; | |
731 | u16 duration = 0; | |
732 | u8 rc_flags; | |
fa1c114f | 733 | |
8a63facc | 734 | flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; |
fa1c114f | 735 | |
8a63facc | 736 | /* XXX endianness */ |
aeae4ac9 FF |
737 | bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len, |
738 | DMA_TO_DEVICE); | |
fa1c114f | 739 | |
8a63facc | 740 | rate = ieee80211_get_tx_rate(sc->hw, info); |
29ad2fac JL |
741 | if (!rate) { |
742 | ret = -EINVAL; | |
743 | goto err_unmap; | |
744 | } | |
fa1c114f | 745 | |
8a63facc BC |
746 | if (info->flags & IEEE80211_TX_CTL_NO_ACK) |
747 | flags |= AR5K_TXDESC_NOACK; | |
fa1c114f | 748 | |
8a63facc BC |
749 | rc_flags = info->control.rates[0].flags; |
750 | hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? | |
751 | rate->hw_value_short : rate->hw_value; | |
42639fcd | 752 | |
8a63facc BC |
753 | pktlen = skb->len; |
754 | ||
755 | /* FIXME: If we are in g mode and rate is a CCK rate | |
756 | * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta | |
757 | * from tx power (value is in dB units already) */ | |
758 | if (info->control.hw_key) { | |
759 | keyidx = info->control.hw_key->hw_key_idx; | |
760 | pktlen += info->control.hw_key->icv_len; | |
761 | } | |
762 | if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { | |
763 | flags |= AR5K_TXDESC_RTSENA; | |
764 | cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; | |
765 | duration = le16_to_cpu(ieee80211_rts_duration(sc->hw, | |
b1ae1edf | 766 | info->control.vif, pktlen, info)); |
8a63facc BC |
767 | } |
768 | if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { | |
769 | flags |= AR5K_TXDESC_CTSENA; | |
770 | cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; | |
771 | duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw, | |
b1ae1edf | 772 | info->control.vif, pktlen, info)); |
8a63facc BC |
773 | } |
774 | ret = ah->ah_setup_tx_desc(ah, ds, pktlen, | |
775 | ieee80211_get_hdrlen_from_skb(skb), padsize, | |
776 | get_hw_packet_type(skb), | |
777 | (sc->power_level * 2), | |
778 | hw_rate, | |
779 | info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags, | |
780 | cts_rate, duration); | |
781 | if (ret) | |
782 | goto err_unmap; | |
783 | ||
784 | memset(mrr_rate, 0, sizeof(mrr_rate)); | |
785 | memset(mrr_tries, 0, sizeof(mrr_tries)); | |
786 | for (i = 0; i < 3; i++) { | |
787 | rate = ieee80211_get_alt_retry_rate(sc->hw, info, i); | |
788 | if (!rate) | |
400ec45a | 789 | break; |
fa1c114f | 790 | |
8a63facc BC |
791 | mrr_rate[i] = rate->hw_value; |
792 | mrr_tries[i] = info->control.rates[i + 1].count; | |
fa1c114f JS |
793 | } |
794 | ||
8a63facc BC |
795 | ath5k_hw_setup_mrr_tx_desc(ah, ds, |
796 | mrr_rate[0], mrr_tries[0], | |
797 | mrr_rate[1], mrr_tries[1], | |
798 | mrr_rate[2], mrr_tries[2]); | |
fa1c114f | 799 | |
8a63facc BC |
800 | ds->ds_link = 0; |
801 | ds->ds_data = bf->skbaddr; | |
63266a65 | 802 | |
8a63facc BC |
803 | spin_lock_bh(&txq->lock); |
804 | list_add_tail(&bf->list, &txq->q); | |
925e0b06 | 805 | txq->txq_len++; |
8a63facc BC |
806 | if (txq->link == NULL) /* is this first packet? */ |
807 | ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); | |
808 | else /* no, so only link it */ | |
809 | *txq->link = bf->daddr; | |
63266a65 | 810 | |
8a63facc BC |
811 | txq->link = &ds->ds_link; |
812 | ath5k_hw_start_tx_dma(ah, txq->qnum); | |
813 | mmiowb(); | |
814 | spin_unlock_bh(&txq->lock); | |
815 | ||
816 | return 0; | |
817 | err_unmap: | |
aeae4ac9 | 818 | dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); |
8a63facc | 819 | return ret; |
63266a65 BR |
820 | } |
821 | ||
8a63facc BC |
822 | /*******************\ |
823 | * Descriptors setup * | |
824 | \*******************/ | |
825 | ||
d8ee398d | 826 | static int |
aeae4ac9 | 827 | ath5k_desc_alloc(struct ath5k_softc *sc) |
fa1c114f | 828 | { |
8a63facc BC |
829 | struct ath5k_desc *ds; |
830 | struct ath5k_buf *bf; | |
831 | dma_addr_t da; | |
832 | unsigned int i; | |
833 | int ret; | |
d8ee398d | 834 | |
8a63facc BC |
835 | /* allocate descriptors */ |
836 | sc->desc_len = sizeof(struct ath5k_desc) * | |
837 | (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); | |
aeae4ac9 FF |
838 | |
839 | sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len, | |
840 | &sc->desc_daddr, GFP_KERNEL); | |
8a63facc BC |
841 | if (sc->desc == NULL) { |
842 | ATH5K_ERR(sc, "can't allocate descriptors\n"); | |
843 | ret = -ENOMEM; | |
844 | goto err; | |
845 | } | |
846 | ds = sc->desc; | |
847 | da = sc->desc_daddr; | |
848 | ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", | |
849 | ds, sc->desc_len, (unsigned long long)sc->desc_daddr); | |
fa1c114f | 850 | |
8a63facc BC |
851 | bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, |
852 | sizeof(struct ath5k_buf), GFP_KERNEL); | |
853 | if (bf == NULL) { | |
854 | ATH5K_ERR(sc, "can't allocate bufptr\n"); | |
855 | ret = -ENOMEM; | |
856 | goto err_free; | |
857 | } | |
858 | sc->bufptr = bf; | |
fa1c114f | 859 | |
8a63facc BC |
860 | INIT_LIST_HEAD(&sc->rxbuf); |
861 | for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { | |
862 | bf->desc = ds; | |
863 | bf->daddr = da; | |
864 | list_add_tail(&bf->list, &sc->rxbuf); | |
865 | } | |
d8ee398d | 866 | |
8a63facc BC |
867 | INIT_LIST_HEAD(&sc->txbuf); |
868 | sc->txbuf_len = ATH_TXBUF; | |
869 | for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, | |
870 | da += sizeof(*ds)) { | |
871 | bf->desc = ds; | |
872 | bf->daddr = da; | |
873 | list_add_tail(&bf->list, &sc->txbuf); | |
fa1c114f JS |
874 | } |
875 | ||
b1ae1edf BG |
876 | /* beacon buffers */ |
877 | INIT_LIST_HEAD(&sc->bcbuf); | |
878 | for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { | |
879 | bf->desc = ds; | |
880 | bf->daddr = da; | |
881 | list_add_tail(&bf->list, &sc->bcbuf); | |
882 | } | |
fa1c114f | 883 | |
8a63facc BC |
884 | return 0; |
885 | err_free: | |
aeae4ac9 | 886 | dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr); |
8a63facc BC |
887 | err: |
888 | sc->desc = NULL; | |
889 | return ret; | |
890 | } | |
fa1c114f | 891 | |
8a63facc | 892 | static void |
aeae4ac9 | 893 | ath5k_desc_free(struct ath5k_softc *sc) |
8a63facc BC |
894 | { |
895 | struct ath5k_buf *bf; | |
d8ee398d | 896 | |
8a63facc BC |
897 | list_for_each_entry(bf, &sc->txbuf, list) |
898 | ath5k_txbuf_free_skb(sc, bf); | |
899 | list_for_each_entry(bf, &sc->rxbuf, list) | |
900 | ath5k_rxbuf_free_skb(sc, bf); | |
b1ae1edf BG |
901 | list_for_each_entry(bf, &sc->bcbuf, list) |
902 | ath5k_txbuf_free_skb(sc, bf); | |
d8ee398d | 903 | |
8a63facc | 904 | /* Free memory associated with all descriptors */ |
aeae4ac9 | 905 | dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr); |
8a63facc BC |
906 | sc->desc = NULL; |
907 | sc->desc_daddr = 0; | |
d8ee398d | 908 | |
8a63facc BC |
909 | kfree(sc->bufptr); |
910 | sc->bufptr = NULL; | |
fa1c114f JS |
911 | } |
912 | ||
8a63facc BC |
913 | |
914 | /**************\ | |
915 | * Queues setup * | |
916 | \**************/ | |
917 | ||
918 | static struct ath5k_txq * | |
919 | ath5k_txq_setup(struct ath5k_softc *sc, | |
920 | int qtype, int subtype) | |
fa1c114f | 921 | { |
8a63facc BC |
922 | struct ath5k_hw *ah = sc->ah; |
923 | struct ath5k_txq *txq; | |
924 | struct ath5k_txq_info qi = { | |
925 | .tqi_subtype = subtype, | |
de8af455 BR |
926 | /* XXX: default values not correct for B and XR channels, |
927 | * but who cares? */ | |
928 | .tqi_aifs = AR5K_TUNE_AIFS, | |
929 | .tqi_cw_min = AR5K_TUNE_CWMIN, | |
930 | .tqi_cw_max = AR5K_TUNE_CWMAX | |
8a63facc BC |
931 | }; |
932 | int qnum; | |
d8ee398d | 933 | |
e30eb4ab | 934 | /* |
8a63facc BC |
935 | * Enable interrupts only for EOL and DESC conditions. |
936 | * We mark tx descriptors to receive a DESC interrupt | |
937 | * when a tx queue gets deep; otherwise we wait for the | |
938 | * EOL to reap descriptors. Note that this is done to | |
939 | * reduce interrupt load and this only defers reaping | |
940 | * descriptors, never transmitting frames. Aside from | |
941 | * reducing interrupts this also permits more concurrency. | |
942 | * The only potential downside is if the tx queue backs | |
943 | * up in which case the top half of the kernel may backup | |
944 | * due to a lack of tx descriptors. | |
e30eb4ab | 945 | */ |
8a63facc BC |
946 | qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | |
947 | AR5K_TXQ_FLAG_TXDESCINT_ENABLE; | |
948 | qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); | |
949 | if (qnum < 0) { | |
950 | /* | |
951 | * NB: don't print a message, this happens | |
952 | * normally on parts with too few tx queues | |
953 | */ | |
954 | return ERR_PTR(qnum); | |
955 | } | |
956 | if (qnum >= ARRAY_SIZE(sc->txqs)) { | |
957 | ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n", | |
958 | qnum, ARRAY_SIZE(sc->txqs)); | |
959 | ath5k_hw_release_tx_queue(ah, qnum); | |
960 | return ERR_PTR(-EINVAL); | |
961 | } | |
962 | txq = &sc->txqs[qnum]; | |
963 | if (!txq->setup) { | |
964 | txq->qnum = qnum; | |
965 | txq->link = NULL; | |
966 | INIT_LIST_HEAD(&txq->q); | |
967 | spin_lock_init(&txq->lock); | |
968 | txq->setup = true; | |
925e0b06 | 969 | txq->txq_len = 0; |
4edd761f | 970 | txq->txq_poll_mark = false; |
923e5b3d | 971 | txq->txq_stuck = 0; |
8a63facc BC |
972 | } |
973 | return &sc->txqs[qnum]; | |
fa1c114f JS |
974 | } |
975 | ||
8a63facc BC |
976 | static int |
977 | ath5k_beaconq_setup(struct ath5k_hw *ah) | |
fa1c114f | 978 | { |
8a63facc | 979 | struct ath5k_txq_info qi = { |
de8af455 BR |
980 | /* XXX: default values not correct for B and XR channels, |
981 | * but who cares? */ | |
982 | .tqi_aifs = AR5K_TUNE_AIFS, | |
983 | .tqi_cw_min = AR5K_TUNE_CWMIN, | |
984 | .tqi_cw_max = AR5K_TUNE_CWMAX, | |
8a63facc BC |
985 | /* NB: for dynamic turbo, don't enable any other interrupts */ |
986 | .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE | |
987 | }; | |
d8ee398d | 988 | |
8a63facc | 989 | return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); |
fa1c114f JS |
990 | } |
991 | ||
8a63facc BC |
992 | static int |
993 | ath5k_beaconq_config(struct ath5k_softc *sc) | |
fa1c114f JS |
994 | { |
995 | struct ath5k_hw *ah = sc->ah; | |
8a63facc BC |
996 | struct ath5k_txq_info qi; |
997 | int ret; | |
fa1c114f | 998 | |
8a63facc BC |
999 | ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi); |
1000 | if (ret) | |
1001 | goto err; | |
fa1c114f | 1002 | |
8a63facc BC |
1003 | if (sc->opmode == NL80211_IFTYPE_AP || |
1004 | sc->opmode == NL80211_IFTYPE_MESH_POINT) { | |
1005 | /* | |
1006 | * Always burst out beacon and CAB traffic | |
1007 | * (aifs = cwmin = cwmax = 0) | |
1008 | */ | |
1009 | qi.tqi_aifs = 0; | |
1010 | qi.tqi_cw_min = 0; | |
1011 | qi.tqi_cw_max = 0; | |
1012 | } else if (sc->opmode == NL80211_IFTYPE_ADHOC) { | |
1013 | /* | |
1014 | * Adhoc mode; backoff between 0 and (2 * cw_min). | |
1015 | */ | |
1016 | qi.tqi_aifs = 0; | |
1017 | qi.tqi_cw_min = 0; | |
de8af455 | 1018 | qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN; |
8a63facc | 1019 | } |
fa1c114f | 1020 | |
8a63facc BC |
1021 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, |
1022 | "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", | |
1023 | qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); | |
fa1c114f | 1024 | |
8a63facc BC |
1025 | ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi); |
1026 | if (ret) { | |
1027 | ATH5K_ERR(sc, "%s: unable to update parameters for beacon " | |
1028 | "hardware queue!\n", __func__); | |
1029 | goto err; | |
1030 | } | |
1031 | ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */ | |
1032 | if (ret) | |
1033 | goto err; | |
b7266047 | 1034 | |
8a63facc BC |
1035 | /* reconfigure cabq with ready time to 80% of beacon_interval */ |
1036 | ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); | |
1037 | if (ret) | |
1038 | goto err; | |
b7266047 | 1039 | |
8a63facc BC |
1040 | qi.tqi_ready_time = (sc->bintval * 80) / 100; |
1041 | ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); | |
1042 | if (ret) | |
1043 | goto err; | |
b7266047 | 1044 | |
8a63facc BC |
1045 | ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB); |
1046 | err: | |
1047 | return ret; | |
d8ee398d LR |
1048 | } |
1049 | ||
80dac9ee NK |
1050 | /** |
1051 | * ath5k_drain_tx_buffs - Empty tx buffers | |
1052 | * | |
1053 | * @sc The &struct ath5k_softc | |
1054 | * | |
1055 | * Empty tx buffers from all queues in preparation | |
1056 | * of a reset or during shutdown. | |
1057 | * | |
1058 | * NB: this assumes output has been stopped and | |
1059 | * we do not need to block ath5k_tx_tasklet | |
1060 | */ | |
8a63facc | 1061 | static void |
80dac9ee | 1062 | ath5k_drain_tx_buffs(struct ath5k_softc *sc) |
8a63facc | 1063 | { |
80dac9ee | 1064 | struct ath5k_txq *txq; |
8a63facc | 1065 | struct ath5k_buf *bf, *bf0; |
80dac9ee | 1066 | int i; |
b6ea0356 | 1067 | |
80dac9ee NK |
1068 | for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) { |
1069 | if (sc->txqs[i].setup) { | |
1070 | txq = &sc->txqs[i]; | |
1071 | spin_lock_bh(&txq->lock); | |
1072 | list_for_each_entry_safe(bf, bf0, &txq->q, list) { | |
1073 | ath5k_debug_printtxbuf(sc, bf); | |
b6ea0356 | 1074 | |
80dac9ee | 1075 | ath5k_txbuf_free_skb(sc, bf); |
fa1c114f | 1076 | |
80dac9ee NK |
1077 | spin_lock_bh(&sc->txbuflock); |
1078 | list_move_tail(&bf->list, &sc->txbuf); | |
1079 | sc->txbuf_len++; | |
1080 | txq->txq_len--; | |
1081 | spin_unlock_bh(&sc->txbuflock); | |
8a63facc | 1082 | } |
80dac9ee NK |
1083 | txq->link = NULL; |
1084 | txq->txq_poll_mark = false; | |
1085 | spin_unlock_bh(&txq->lock); | |
1086 | } | |
0452d4a5 | 1087 | } |
fa1c114f JS |
1088 | } |
1089 | ||
8a63facc BC |
1090 | static void |
1091 | ath5k_txq_release(struct ath5k_softc *sc) | |
2ac2927a | 1092 | { |
8a63facc BC |
1093 | struct ath5k_txq *txq = sc->txqs; |
1094 | unsigned int i; | |
2ac2927a | 1095 | |
8a63facc BC |
1096 | for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++) |
1097 | if (txq->setup) { | |
1098 | ath5k_hw_release_tx_queue(sc->ah, txq->qnum); | |
1099 | txq->setup = false; | |
1100 | } | |
1101 | } | |
2ac2927a | 1102 | |
2ac2927a | 1103 | |
8a63facc BC |
1104 | /*************\ |
1105 | * RX Handling * | |
1106 | \*************/ | |
2ac2927a | 1107 | |
8a63facc BC |
1108 | /* |
1109 | * Enable the receive h/w following a reset. | |
1110 | */ | |
fa1c114f | 1111 | static int |
8a63facc | 1112 | ath5k_rx_start(struct ath5k_softc *sc) |
fa1c114f JS |
1113 | { |
1114 | struct ath5k_hw *ah = sc->ah; | |
8a63facc BC |
1115 | struct ath_common *common = ath5k_hw_common(ah); |
1116 | struct ath5k_buf *bf; | |
1117 | int ret; | |
fa1c114f | 1118 | |
8a63facc | 1119 | common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz); |
fa1c114f | 1120 | |
8a63facc BC |
1121 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", |
1122 | common->cachelsz, common->rx_bufsize); | |
2f7fe870 | 1123 | |
8a63facc BC |
1124 | spin_lock_bh(&sc->rxbuflock); |
1125 | sc->rxlink = NULL; | |
1126 | list_for_each_entry(bf, &sc->rxbuf, list) { | |
1127 | ret = ath5k_rxbuf_setup(sc, bf); | |
1128 | if (ret != 0) { | |
1129 | spin_unlock_bh(&sc->rxbuflock); | |
1130 | goto err; | |
1131 | } | |
2f7fe870 | 1132 | } |
8a63facc BC |
1133 | bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); |
1134 | ath5k_hw_set_rxdp(ah, bf->daddr); | |
1135 | spin_unlock_bh(&sc->rxbuflock); | |
2f7fe870 | 1136 | |
8a63facc | 1137 | ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ |
b1ae1edf | 1138 | ath5k_mode_setup(sc, NULL); /* set filters, etc. */ |
8a63facc | 1139 | ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ |
fa1c114f JS |
1140 | |
1141 | return 0; | |
8a63facc | 1142 | err: |
fa1c114f JS |
1143 | return ret; |
1144 | } | |
1145 | ||
8a63facc | 1146 | /* |
80dac9ee NK |
1147 | * Disable the receive logic on PCU (DRU) |
1148 | * In preparation for a shutdown. | |
1149 | * | |
1150 | * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop | |
1151 | * does. | |
8a63facc BC |
1152 | */ |
1153 | static void | |
1154 | ath5k_rx_stop(struct ath5k_softc *sc) | |
fa1c114f | 1155 | { |
8a63facc | 1156 | struct ath5k_hw *ah = sc->ah; |
fa1c114f | 1157 | |
8a63facc | 1158 | ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ |
80dac9ee | 1159 | ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ |
fa1c114f | 1160 | |
8a63facc BC |
1161 | ath5k_debug_printrxbuffs(sc, ah); |
1162 | } | |
fa1c114f | 1163 | |
8a63facc BC |
1164 | static unsigned int |
1165 | ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb, | |
1166 | struct ath5k_rx_status *rs) | |
1167 | { | |
1168 | struct ath5k_hw *ah = sc->ah; | |
1169 | struct ath_common *common = ath5k_hw_common(ah); | |
1170 | struct ieee80211_hdr *hdr = (void *)skb->data; | |
1171 | unsigned int keyix, hlen; | |
fa1c114f | 1172 | |
8a63facc BC |
1173 | if (!(rs->rs_status & AR5K_RXERR_DECRYPT) && |
1174 | rs->rs_keyix != AR5K_RXKEYIX_INVALID) | |
1175 | return RX_FLAG_DECRYPTED; | |
fa1c114f | 1176 | |
8a63facc BC |
1177 | /* Apparently when a default key is used to decrypt the packet |
1178 | the hw does not set the index used to decrypt. In such cases | |
1179 | get the index from the packet. */ | |
1180 | hlen = ieee80211_hdrlen(hdr->frame_control); | |
1181 | if (ieee80211_has_protected(hdr->frame_control) && | |
1182 | !(rs->rs_status & AR5K_RXERR_DECRYPT) && | |
1183 | skb->len >= hlen + 4) { | |
1184 | keyix = skb->data[hlen + 3] >> 6; | |
1185 | ||
1186 | if (test_bit(keyix, common->keymap)) | |
1187 | return RX_FLAG_DECRYPTED; | |
1188 | } | |
fa1c114f JS |
1189 | |
1190 | return 0; | |
fa1c114f JS |
1191 | } |
1192 | ||
8a63facc | 1193 | |
fa1c114f | 1194 | static void |
8a63facc BC |
1195 | ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb, |
1196 | struct ieee80211_rx_status *rxs) | |
fa1c114f | 1197 | { |
8a63facc BC |
1198 | struct ath_common *common = ath5k_hw_common(sc->ah); |
1199 | u64 tsf, bc_tstamp; | |
1200 | u32 hw_tu; | |
1201 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; | |
fa1c114f | 1202 | |
8a63facc BC |
1203 | if (ieee80211_is_beacon(mgmt->frame_control) && |
1204 | le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS && | |
1205 | memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) { | |
1206 | /* | |
1207 | * Received an IBSS beacon with the same BSSID. Hardware *must* | |
1208 | * have updated the local TSF. We have to work around various | |
1209 | * hardware bugs, though... | |
1210 | */ | |
1211 | tsf = ath5k_hw_get_tsf64(sc->ah); | |
1212 | bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); | |
1213 | hw_tu = TSF_TO_TU(tsf); | |
fa1c114f | 1214 | |
8a63facc BC |
1215 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, |
1216 | "beacon %llx mactime %llx (diff %lld) tsf now %llx\n", | |
1217 | (unsigned long long)bc_tstamp, | |
1218 | (unsigned long long)rxs->mactime, | |
1219 | (unsigned long long)(rxs->mactime - bc_tstamp), | |
1220 | (unsigned long long)tsf); | |
fa1c114f | 1221 | |
8a63facc BC |
1222 | /* |
1223 | * Sometimes the HW will give us a wrong tstamp in the rx | |
1224 | * status, causing the timestamp extension to go wrong. | |
1225 | * (This seems to happen especially with beacon frames bigger | |
1226 | * than 78 byte (incl. FCS)) | |
1227 | * But we know that the receive timestamp must be later than the | |
1228 | * timestamp of the beacon since HW must have synced to that. | |
1229 | * | |
1230 | * NOTE: here we assume mactime to be after the frame was | |
1231 | * received, not like mac80211 which defines it at the start. | |
1232 | */ | |
1233 | if (bc_tstamp > rxs->mactime) { | |
1234 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, | |
1235 | "fixing mactime from %llx to %llx\n", | |
1236 | (unsigned long long)rxs->mactime, | |
1237 | (unsigned long long)tsf); | |
1238 | rxs->mactime = tsf; | |
1239 | } | |
fa1c114f | 1240 | |
8a63facc BC |
1241 | /* |
1242 | * Local TSF might have moved higher than our beacon timers, | |
1243 | * in that case we have to update them to continue sending | |
1244 | * beacons. This also takes care of synchronizing beacon sending | |
1245 | * times with other stations. | |
1246 | */ | |
1247 | if (hw_tu >= sc->nexttbtt) | |
1248 | ath5k_beacon_update_timers(sc, bc_tstamp); | |
7f896126 BR |
1249 | |
1250 | /* Check if the beacon timers are still correct, because a TSF | |
1251 | * update might have created a window between them - for a | |
1252 | * longer description see the comment of this function: */ | |
1253 | if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) { | |
1254 | ath5k_beacon_update_timers(sc, bc_tstamp); | |
1255 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, | |
1256 | "fixed beacon timers after beacon receive\n"); | |
1257 | } | |
8a63facc BC |
1258 | } |
1259 | } | |
fa1c114f | 1260 | |
8a63facc BC |
1261 | static void |
1262 | ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi) | |
1263 | { | |
1264 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; | |
1265 | struct ath5k_hw *ah = sc->ah; | |
1266 | struct ath_common *common = ath5k_hw_common(ah); | |
fa1c114f | 1267 | |
8a63facc BC |
1268 | /* only beacons from our BSSID */ |
1269 | if (!ieee80211_is_beacon(mgmt->frame_control) || | |
1270 | memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0) | |
1271 | return; | |
fa1c114f | 1272 | |
eef39bef | 1273 | ewma_add(&ah->ah_beacon_rssi_avg, rssi); |
fa1c114f | 1274 | |
8a63facc BC |
1275 | /* in IBSS mode we should keep RSSI statistics per neighbour */ |
1276 | /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */ | |
1277 | } | |
fa1c114f | 1278 | |
8a63facc BC |
1279 | /* |
1280 | * Compute padding position. skb must contain an IEEE 802.11 frame | |
1281 | */ | |
1282 | static int ath5k_common_padpos(struct sk_buff *skb) | |
fa1c114f | 1283 | { |
8a63facc BC |
1284 | struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; |
1285 | __le16 frame_control = hdr->frame_control; | |
1286 | int padpos = 24; | |
fa1c114f | 1287 | |
8a63facc BC |
1288 | if (ieee80211_has_a4(frame_control)) { |
1289 | padpos += ETH_ALEN; | |
fa1c114f | 1290 | } |
8a63facc BC |
1291 | if (ieee80211_is_data_qos(frame_control)) { |
1292 | padpos += IEEE80211_QOS_CTL_LEN; | |
fa1c114f | 1293 | } |
8a63facc BC |
1294 | |
1295 | return padpos; | |
fa1c114f JS |
1296 | } |
1297 | ||
8a63facc BC |
1298 | /* |
1299 | * This function expects an 802.11 frame and returns the number of | |
1300 | * bytes added, or -1 if we don't have enough header room. | |
1301 | */ | |
1302 | static int ath5k_add_padding(struct sk_buff *skb) | |
fa1c114f | 1303 | { |
8a63facc BC |
1304 | int padpos = ath5k_common_padpos(skb); |
1305 | int padsize = padpos & 3; | |
fa1c114f | 1306 | |
8a63facc | 1307 | if (padsize && skb->len>padpos) { |
fa1c114f | 1308 | |
8a63facc BC |
1309 | if (skb_headroom(skb) < padsize) |
1310 | return -1; | |
fa1c114f | 1311 | |
8a63facc BC |
1312 | skb_push(skb, padsize); |
1313 | memmove(skb->data, skb->data+padsize, padpos); | |
1314 | return padsize; | |
1315 | } | |
a951ae21 | 1316 | |
8a63facc BC |
1317 | return 0; |
1318 | } | |
fa1c114f | 1319 | |
8a63facc BC |
1320 | /* |
1321 | * The MAC header is padded to have 32-bit boundary if the | |
1322 | * packet payload is non-zero. The general calculation for | |
1323 | * padsize would take into account odd header lengths: | |
1324 | * padsize = 4 - (hdrlen & 3); however, since only | |
1325 | * even-length headers are used, padding can only be 0 or 2 | |
1326 | * bytes and we can optimize this a bit. We must not try to | |
1327 | * remove padding from short control frames that do not have a | |
1328 | * payload. | |
1329 | * | |
1330 | * This function expects an 802.11 frame and returns the number of | |
1331 | * bytes removed. | |
1332 | */ | |
1333 | static int ath5k_remove_padding(struct sk_buff *skb) | |
1334 | { | |
1335 | int padpos = ath5k_common_padpos(skb); | |
1336 | int padsize = padpos & 3; | |
6d91e1d8 | 1337 | |
8a63facc BC |
1338 | if (padsize && skb->len>=padpos+padsize) { |
1339 | memmove(skb->data + padsize, skb->data, padpos); | |
1340 | skb_pull(skb, padsize); | |
1341 | return padsize; | |
fa1c114f | 1342 | } |
a951ae21 | 1343 | |
8a63facc | 1344 | return 0; |
fa1c114f JS |
1345 | } |
1346 | ||
1347 | static void | |
8a63facc BC |
1348 | ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb, |
1349 | struct ath5k_rx_status *rs) | |
fa1c114f | 1350 | { |
8a63facc BC |
1351 | struct ieee80211_rx_status *rxs; |
1352 | ||
1353 | ath5k_remove_padding(skb); | |
1354 | ||
1355 | rxs = IEEE80211_SKB_RXCB(skb); | |
1356 | ||
1357 | rxs->flag = 0; | |
1358 | if (unlikely(rs->rs_status & AR5K_RXERR_MIC)) | |
1359 | rxs->flag |= RX_FLAG_MMIC_ERROR; | |
fa1c114f JS |
1360 | |
1361 | /* | |
8a63facc BC |
1362 | * always extend the mac timestamp, since this information is |
1363 | * also needed for proper IBSS merging. | |
1364 | * | |
1365 | * XXX: it might be too late to do it here, since rs_tstamp is | |
1366 | * 15bit only. that means TSF extension has to be done within | |
1367 | * 32768usec (about 32ms). it might be necessary to move this to | |
1368 | * the interrupt handler, like it is done in madwifi. | |
1369 | * | |
1370 | * Unfortunately we don't know when the hardware takes the rx | |
1371 | * timestamp (beginning of phy frame, data frame, end of rx?). | |
1372 | * The only thing we know is that it is hardware specific... | |
1373 | * On AR5213 it seems the rx timestamp is at the end of the | |
1374 | * frame, but i'm not sure. | |
1375 | * | |
1376 | * NOTE: mac80211 defines mactime at the beginning of the first | |
1377 | * data symbol. Since we don't have any time references it's | |
1378 | * impossible to comply to that. This affects IBSS merge only | |
1379 | * right now, so it's not too bad... | |
fa1c114f | 1380 | */ |
8a63facc BC |
1381 | rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp); |
1382 | rxs->flag |= RX_FLAG_TSFT; | |
fa1c114f | 1383 | |
8a63facc BC |
1384 | rxs->freq = sc->curchan->center_freq; |
1385 | rxs->band = sc->curband->band; | |
fa1c114f | 1386 | |
8a63facc | 1387 | rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi; |
fa1c114f | 1388 | |
8a63facc | 1389 | rxs->antenna = rs->rs_antenna; |
fa1c114f | 1390 | |
8a63facc BC |
1391 | if (rs->rs_antenna > 0 && rs->rs_antenna < 5) |
1392 | sc->stats.antenna_rx[rs->rs_antenna]++; | |
1393 | else | |
1394 | sc->stats.antenna_rx[0]++; /* invalid */ | |
fa1c114f | 1395 | |
8a63facc BC |
1396 | rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate); |
1397 | rxs->flag |= ath5k_rx_decrypted(sc, skb, rs); | |
fa1c114f | 1398 | |
8a63facc BC |
1399 | if (rxs->rate_idx >= 0 && rs->rs_rate == |
1400 | sc->curband->bitrates[rxs->rate_idx].hw_value_short) | |
1401 | rxs->flag |= RX_FLAG_SHORTPRE; | |
fa1c114f | 1402 | |
8a63facc | 1403 | ath5k_debug_dump_skb(sc, skb, "RX ", 0); |
fa1c114f | 1404 | |
8a63facc | 1405 | ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi); |
fa1c114f | 1406 | |
8a63facc BC |
1407 | /* check beacons in IBSS mode */ |
1408 | if (sc->opmode == NL80211_IFTYPE_ADHOC) | |
1409 | ath5k_check_ibss_tsf(sc, skb, rxs); | |
fa1c114f | 1410 | |
8a63facc BC |
1411 | ieee80211_rx(sc->hw, skb); |
1412 | } | |
fa1c114f | 1413 | |
8a63facc BC |
1414 | /** ath5k_frame_receive_ok() - Do we want to receive this frame or not? |
1415 | * | |
1416 | * Check if we want to further process this frame or not. Also update | |
1417 | * statistics. Return true if we want this frame, false if not. | |
fa1c114f | 1418 | */ |
8a63facc BC |
1419 | static bool |
1420 | ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs) | |
fa1c114f | 1421 | { |
8a63facc | 1422 | sc->stats.rx_all_count++; |
b72acddb | 1423 | sc->stats.rx_bytes_count += rs->rs_datalen; |
fa1c114f | 1424 | |
8a63facc BC |
1425 | if (unlikely(rs->rs_status)) { |
1426 | if (rs->rs_status & AR5K_RXERR_CRC) | |
1427 | sc->stats.rxerr_crc++; | |
1428 | if (rs->rs_status & AR5K_RXERR_FIFO) | |
1429 | sc->stats.rxerr_fifo++; | |
1430 | if (rs->rs_status & AR5K_RXERR_PHY) { | |
1431 | sc->stats.rxerr_phy++; | |
1432 | if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32) | |
1433 | sc->stats.rxerr_phy_code[rs->rs_phyerr]++; | |
1434 | return false; | |
1435 | } | |
1436 | if (rs->rs_status & AR5K_RXERR_DECRYPT) { | |
1437 | /* | |
1438 | * Decrypt error. If the error occurred | |
1439 | * because there was no hardware key, then | |
1440 | * let the frame through so the upper layers | |
1441 | * can process it. This is necessary for 5210 | |
1442 | * parts which have no way to setup a ``clear'' | |
1443 | * key cache entry. | |
1444 | * | |
1445 | * XXX do key cache faulting | |
1446 | */ | |
1447 | sc->stats.rxerr_decrypt++; | |
1448 | if (rs->rs_keyix == AR5K_RXKEYIX_INVALID && | |
1449 | !(rs->rs_status & AR5K_RXERR_CRC)) | |
1450 | return true; | |
1451 | } | |
1452 | if (rs->rs_status & AR5K_RXERR_MIC) { | |
1453 | sc->stats.rxerr_mic++; | |
1454 | return true; | |
fa1c114f | 1455 | } |
fa1c114f | 1456 | |
8a63facc BC |
1457 | /* reject any frames with non-crypto errors */ |
1458 | if (rs->rs_status & ~(AR5K_RXERR_DECRYPT)) | |
1459 | return false; | |
1460 | } | |
fa1c114f | 1461 | |
8a63facc BC |
1462 | if (unlikely(rs->rs_more)) { |
1463 | sc->stats.rxerr_jumbo++; | |
1464 | return false; | |
1465 | } | |
1466 | return true; | |
fa1c114f JS |
1467 | } |
1468 | ||
fa1c114f | 1469 | static void |
8a63facc | 1470 | ath5k_tasklet_rx(unsigned long data) |
fa1c114f | 1471 | { |
8a63facc BC |
1472 | struct ath5k_rx_status rs = {}; |
1473 | struct sk_buff *skb, *next_skb; | |
1474 | dma_addr_t next_skb_addr; | |
1475 | struct ath5k_softc *sc = (void *)data; | |
dc1e001b LR |
1476 | struct ath5k_hw *ah = sc->ah; |
1477 | struct ath_common *common = ath5k_hw_common(ah); | |
8a63facc BC |
1478 | struct ath5k_buf *bf; |
1479 | struct ath5k_desc *ds; | |
1480 | int ret; | |
fa1c114f | 1481 | |
8a63facc BC |
1482 | spin_lock(&sc->rxbuflock); |
1483 | if (list_empty(&sc->rxbuf)) { | |
1484 | ATH5K_WARN(sc, "empty rx buf pool\n"); | |
1485 | goto unlock; | |
1486 | } | |
1487 | do { | |
1488 | bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); | |
1489 | BUG_ON(bf->skb == NULL); | |
1490 | skb = bf->skb; | |
1491 | ds = bf->desc; | |
fa1c114f | 1492 | |
8a63facc BC |
1493 | /* bail if HW is still using self-linked descriptor */ |
1494 | if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr) | |
1495 | break; | |
fa1c114f | 1496 | |
8a63facc BC |
1497 | ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs); |
1498 | if (unlikely(ret == -EINPROGRESS)) | |
1499 | break; | |
1500 | else if (unlikely(ret)) { | |
1501 | ATH5K_ERR(sc, "error in processing rx descriptor\n"); | |
1502 | sc->stats.rxerr_proc++; | |
1503 | break; | |
1504 | } | |
fa1c114f | 1505 | |
8a63facc BC |
1506 | if (ath5k_receive_frame_ok(sc, &rs)) { |
1507 | next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr); | |
fa1c114f | 1508 | |
8a63facc BC |
1509 | /* |
1510 | * If we can't replace bf->skb with a new skb under | |
1511 | * memory pressure, just skip this packet | |
1512 | */ | |
1513 | if (!next_skb) | |
1514 | goto next; | |
036cd1ec | 1515 | |
aeae4ac9 | 1516 | dma_unmap_single(sc->dev, bf->skbaddr, |
8a63facc | 1517 | common->rx_bufsize, |
aeae4ac9 | 1518 | DMA_FROM_DEVICE); |
036cd1ec | 1519 | |
8a63facc | 1520 | skb_put(skb, rs.rs_datalen); |
6ba81c2c | 1521 | |
8a63facc | 1522 | ath5k_receive_frame(sc, skb, &rs); |
6ba81c2c | 1523 | |
8a63facc BC |
1524 | bf->skb = next_skb; |
1525 | bf->skbaddr = next_skb_addr; | |
036cd1ec | 1526 | } |
8a63facc BC |
1527 | next: |
1528 | list_move_tail(&bf->list, &sc->rxbuf); | |
1529 | } while (ath5k_rxbuf_setup(sc, bf) == 0); | |
1530 | unlock: | |
1531 | spin_unlock(&sc->rxbuflock); | |
036cd1ec BR |
1532 | } |
1533 | ||
b4ea449d | 1534 | |
8a63facc BC |
1535 | /*************\ |
1536 | * TX Handling * | |
1537 | \*************/ | |
b4ea449d | 1538 | |
8a63facc BC |
1539 | static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, |
1540 | struct ath5k_txq *txq) | |
1541 | { | |
1542 | struct ath5k_softc *sc = hw->priv; | |
1543 | struct ath5k_buf *bf; | |
1544 | unsigned long flags; | |
1545 | int padsize; | |
b4ea449d | 1546 | |
8a63facc | 1547 | ath5k_debug_dump_skb(sc, skb, "TX ", 1); |
b4ea449d | 1548 | |
8a63facc BC |
1549 | /* |
1550 | * The hardware expects the header padded to 4 byte boundaries. | |
1551 | * If this is not the case, we add the padding after the header. | |
1552 | */ | |
1553 | padsize = ath5k_add_padding(skb); | |
1554 | if (padsize < 0) { | |
1555 | ATH5K_ERR(sc, "tx hdrlen not %%4: not enough" | |
1556 | " headroom to pad"); | |
1557 | goto drop_packet; | |
1558 | } | |
8127fbdc | 1559 | |
925e0b06 BR |
1560 | if (txq->txq_len >= ATH5K_TXQ_LEN_MAX) |
1561 | ieee80211_stop_queue(hw, txq->qnum); | |
1562 | ||
8a63facc BC |
1563 | spin_lock_irqsave(&sc->txbuflock, flags); |
1564 | if (list_empty(&sc->txbuf)) { | |
1565 | ATH5K_ERR(sc, "no further txbuf available, dropping packet\n"); | |
1566 | spin_unlock_irqrestore(&sc->txbuflock, flags); | |
651d9375 | 1567 | ieee80211_stop_queues(hw); |
8a63facc | 1568 | goto drop_packet; |
8127fbdc | 1569 | } |
8a63facc BC |
1570 | bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list); |
1571 | list_del(&bf->list); | |
1572 | sc->txbuf_len--; | |
1573 | if (list_empty(&sc->txbuf)) | |
1574 | ieee80211_stop_queues(hw); | |
1575 | spin_unlock_irqrestore(&sc->txbuflock, flags); | |
1576 | ||
1577 | bf->skb = skb; | |
1578 | ||
1579 | if (ath5k_txbuf_setup(sc, bf, txq, padsize)) { | |
1580 | bf->skb = NULL; | |
1581 | spin_lock_irqsave(&sc->txbuflock, flags); | |
1582 | list_add_tail(&bf->list, &sc->txbuf); | |
1583 | sc->txbuf_len++; | |
1584 | spin_unlock_irqrestore(&sc->txbuflock, flags); | |
1585 | goto drop_packet; | |
8127fbdc | 1586 | } |
8a63facc | 1587 | return NETDEV_TX_OK; |
8127fbdc | 1588 | |
8a63facc BC |
1589 | drop_packet: |
1590 | dev_kfree_skb_any(skb); | |
1591 | return NETDEV_TX_OK; | |
8127fbdc BP |
1592 | } |
1593 | ||
1440401e BR |
1594 | static void |
1595 | ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb, | |
1596 | struct ath5k_tx_status *ts) | |
1597 | { | |
1598 | struct ieee80211_tx_info *info; | |
1599 | int i; | |
1600 | ||
1601 | sc->stats.tx_all_count++; | |
b72acddb | 1602 | sc->stats.tx_bytes_count += skb->len; |
1440401e BR |
1603 | info = IEEE80211_SKB_CB(skb); |
1604 | ||
1605 | ieee80211_tx_info_clear_status(info); | |
1606 | for (i = 0; i < 4; i++) { | |
1607 | struct ieee80211_tx_rate *r = | |
1608 | &info->status.rates[i]; | |
1609 | ||
1610 | if (ts->ts_rate[i]) { | |
1611 | r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]); | |
1612 | r->count = ts->ts_retry[i]; | |
1613 | } else { | |
1614 | r->idx = -1; | |
1615 | r->count = 0; | |
1616 | } | |
1617 | } | |
1618 | ||
1619 | /* count the successful attempt as well */ | |
1620 | info->status.rates[ts->ts_final_idx].count++; | |
1621 | ||
1622 | if (unlikely(ts->ts_status)) { | |
1623 | sc->stats.ack_fail++; | |
1624 | if (ts->ts_status & AR5K_TXERR_FILT) { | |
1625 | info->flags |= IEEE80211_TX_STAT_TX_FILTERED; | |
1626 | sc->stats.txerr_filt++; | |
1627 | } | |
1628 | if (ts->ts_status & AR5K_TXERR_XRETRY) | |
1629 | sc->stats.txerr_retry++; | |
1630 | if (ts->ts_status & AR5K_TXERR_FIFO) | |
1631 | sc->stats.txerr_fifo++; | |
1632 | } else { | |
1633 | info->flags |= IEEE80211_TX_STAT_ACK; | |
1634 | info->status.ack_signal = ts->ts_rssi; | |
1635 | } | |
1636 | ||
1637 | /* | |
1638 | * Remove MAC header padding before giving the frame | |
1639 | * back to mac80211. | |
1640 | */ | |
1641 | ath5k_remove_padding(skb); | |
1642 | ||
1643 | if (ts->ts_antenna > 0 && ts->ts_antenna < 5) | |
1644 | sc->stats.antenna_tx[ts->ts_antenna]++; | |
1645 | else | |
1646 | sc->stats.antenna_tx[0]++; /* invalid */ | |
1647 | ||
1648 | ieee80211_tx_status(sc->hw, skb); | |
1649 | } | |
8a63facc BC |
1650 | |
1651 | static void | |
1652 | ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq) | |
8127fbdc | 1653 | { |
8a63facc BC |
1654 | struct ath5k_tx_status ts = {}; |
1655 | struct ath5k_buf *bf, *bf0; | |
1656 | struct ath5k_desc *ds; | |
1657 | struct sk_buff *skb; | |
1440401e | 1658 | int ret; |
8127fbdc | 1659 | |
8a63facc BC |
1660 | spin_lock(&txq->lock); |
1661 | list_for_each_entry_safe(bf, bf0, &txq->q, list) { | |
23413296 BR |
1662 | |
1663 | txq->txq_poll_mark = false; | |
1664 | ||
1665 | /* skb might already have been processed last time. */ | |
1666 | if (bf->skb != NULL) { | |
1667 | ds = bf->desc; | |
1668 | ||
1669 | ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts); | |
1670 | if (unlikely(ret == -EINPROGRESS)) | |
1671 | break; | |
1672 | else if (unlikely(ret)) { | |
1673 | ATH5K_ERR(sc, | |
1674 | "error %d while processing " | |
1675 | "queue %u\n", ret, txq->qnum); | |
1676 | break; | |
1677 | } | |
1678 | ||
1679 | skb = bf->skb; | |
1680 | bf->skb = NULL; | |
aeae4ac9 FF |
1681 | |
1682 | dma_unmap_single(sc->dev, bf->skbaddr, skb->len, | |
1683 | DMA_TO_DEVICE); | |
23413296 BR |
1684 | ath5k_tx_frame_completed(sc, skb, &ts); |
1685 | } | |
8127fbdc | 1686 | |
8a63facc BC |
1687 | /* |
1688 | * It's possible that the hardware can say the buffer is | |
1689 | * completed when it hasn't yet loaded the ds_link from | |
23413296 BR |
1690 | * host memory and moved on. |
1691 | * Always keep the last descriptor to avoid HW races... | |
8a63facc | 1692 | */ |
23413296 BR |
1693 | if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) { |
1694 | spin_lock(&sc->txbuflock); | |
1695 | list_move_tail(&bf->list, &sc->txbuf); | |
1696 | sc->txbuf_len++; | |
1697 | txq->txq_len--; | |
1698 | spin_unlock(&sc->txbuflock); | |
8a63facc | 1699 | } |
fa1c114f | 1700 | } |
fa1c114f | 1701 | spin_unlock(&txq->lock); |
4198a8d0 | 1702 | if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4) |
925e0b06 | 1703 | ieee80211_wake_queue(sc->hw, txq->qnum); |
fa1c114f JS |
1704 | } |
1705 | ||
1706 | static void | |
1707 | ath5k_tasklet_tx(unsigned long data) | |
1708 | { | |
8784d2ee | 1709 | int i; |
fa1c114f JS |
1710 | struct ath5k_softc *sc = (void *)data; |
1711 | ||
8784d2ee BC |
1712 | for (i=0; i < AR5K_NUM_TX_QUEUES; i++) |
1713 | if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i))) | |
1714 | ath5k_tx_processq(sc, &sc->txqs[i]); | |
fa1c114f JS |
1715 | } |
1716 | ||
1717 | ||
fa1c114f JS |
1718 | /*****************\ |
1719 | * Beacon handling * | |
1720 | \*****************/ | |
1721 | ||
1722 | /* | |
1723 | * Setup the beacon frame for transmit. | |
1724 | */ | |
1725 | static int | |
e039fa4a | 1726 | ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) |
fa1c114f JS |
1727 | { |
1728 | struct sk_buff *skb = bf->skb; | |
a888d52d | 1729 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
fa1c114f JS |
1730 | struct ath5k_hw *ah = sc->ah; |
1731 | struct ath5k_desc *ds; | |
2bed03eb NK |
1732 | int ret = 0; |
1733 | u8 antenna; | |
fa1c114f | 1734 | u32 flags; |
8127fbdc | 1735 | const int padsize = 0; |
fa1c114f | 1736 | |
aeae4ac9 FF |
1737 | bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len, |
1738 | DMA_TO_DEVICE); | |
fa1c114f JS |
1739 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " |
1740 | "skbaddr %llx\n", skb, skb->data, skb->len, | |
1741 | (unsigned long long)bf->skbaddr); | |
aeae4ac9 FF |
1742 | |
1743 | if (dma_mapping_error(sc->dev, bf->skbaddr)) { | |
fa1c114f JS |
1744 | ATH5K_ERR(sc, "beacon DMA mapping failed\n"); |
1745 | return -EIO; | |
1746 | } | |
1747 | ||
1748 | ds = bf->desc; | |
2bed03eb | 1749 | antenna = ah->ah_tx_ant; |
fa1c114f JS |
1750 | |
1751 | flags = AR5K_TXDESC_NOACK; | |
05c914fe | 1752 | if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { |
fa1c114f JS |
1753 | ds->ds_link = bf->daddr; /* self-linked */ |
1754 | flags |= AR5K_TXDESC_VEOL; | |
2bed03eb | 1755 | } else |
fa1c114f | 1756 | ds->ds_link = 0; |
2bed03eb NK |
1757 | |
1758 | /* | |
1759 | * If we use multiple antennas on AP and use | |
1760 | * the Sectored AP scenario, switch antenna every | |
1761 | * 4 beacons to make sure everybody hears our AP. | |
1762 | * When a client tries to associate, hw will keep | |
1763 | * track of the tx antenna to be used for this client | |
1764 | * automaticaly, based on ACKed packets. | |
1765 | * | |
1766 | * Note: AP still listens and transmits RTS on the | |
1767 | * default antenna which is supposed to be an omni. | |
1768 | * | |
1769 | * Note2: On sectored scenarios it's possible to have | |
a180a130 BC |
1770 | * multiple antennas (1 omni -- the default -- and 14 |
1771 | * sectors), so if we choose to actually support this | |
1772 | * mode, we need to allow the user to set how many antennas | |
1773 | * we have and tweak the code below to send beacons | |
1774 | * on all of them. | |
2bed03eb NK |
1775 | */ |
1776 | if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) | |
1777 | antenna = sc->bsent & 4 ? 2 : 1; | |
1778 | ||
fa1c114f | 1779 | |
8f655dde NK |
1780 | /* FIXME: If we are in g mode and rate is a CCK rate |
1781 | * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta | |
1782 | * from tx power (value is in dB units already) */ | |
fa1c114f | 1783 | ds->ds_data = bf->skbaddr; |
281c56dd | 1784 | ret = ah->ah_setup_tx_desc(ah, ds, skb->len, |
8127fbdc | 1785 | ieee80211_get_hdrlen_from_skb(skb), padsize, |
400ec45a | 1786 | AR5K_PKT_TYPE_BEACON, (sc->power_level * 2), |
e039fa4a | 1787 | ieee80211_get_tx_rate(sc->hw, info)->hw_value, |
2e92e6f2 | 1788 | 1, AR5K_TXKEYIX_INVALID, |
400ec45a | 1789 | antenna, flags, 0, 0); |
fa1c114f JS |
1790 | if (ret) |
1791 | goto err_unmap; | |
1792 | ||
1793 | return 0; | |
1794 | err_unmap: | |
aeae4ac9 | 1795 | dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); |
fa1c114f JS |
1796 | return ret; |
1797 | } | |
1798 | ||
8a63facc BC |
1799 | /* |
1800 | * Updates the beacon that is sent by ath5k_beacon_send. For adhoc, | |
1801 | * this is called only once at config_bss time, for AP we do it every | |
1802 | * SWBA interrupt so that the TIM will reflect buffered frames. | |
1803 | * | |
1804 | * Called with the beacon lock. | |
1805 | */ | |
1806 | static int | |
1807 | ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) | |
1808 | { | |
1809 | int ret; | |
1810 | struct ath5k_softc *sc = hw->priv; | |
b1ae1edf | 1811 | struct ath5k_vif *avf = (void *)vif->drv_priv; |
8a63facc BC |
1812 | struct sk_buff *skb; |
1813 | ||
1814 | if (WARN_ON(!vif)) { | |
1815 | ret = -EINVAL; | |
1816 | goto out; | |
1817 | } | |
1818 | ||
1819 | skb = ieee80211_beacon_get(hw, vif); | |
1820 | ||
1821 | if (!skb) { | |
1822 | ret = -ENOMEM; | |
1823 | goto out; | |
1824 | } | |
1825 | ||
1826 | ath5k_debug_dump_skb(sc, skb, "BC ", 1); | |
1827 | ||
b1ae1edf BG |
1828 | ath5k_txbuf_free_skb(sc, avf->bbuf); |
1829 | avf->bbuf->skb = skb; | |
1830 | ret = ath5k_beacon_setup(sc, avf->bbuf); | |
8a63facc | 1831 | if (ret) |
b1ae1edf | 1832 | avf->bbuf->skb = NULL; |
8a63facc BC |
1833 | out: |
1834 | return ret; | |
1835 | } | |
1836 | ||
fa1c114f JS |
1837 | /* |
1838 | * Transmit a beacon frame at SWBA. Dynamic updates to the | |
1839 | * frame contents are done as needed and the slot time is | |
1840 | * also adjusted based on current state. | |
1841 | * | |
5faaff74 BC |
1842 | * This is called from software irq context (beacontq tasklets) |
1843 | * or user context from ath5k_beacon_config. | |
fa1c114f JS |
1844 | */ |
1845 | static void | |
1846 | ath5k_beacon_send(struct ath5k_softc *sc) | |
1847 | { | |
fa1c114f | 1848 | struct ath5k_hw *ah = sc->ah; |
b1ae1edf BG |
1849 | struct ieee80211_vif *vif; |
1850 | struct ath5k_vif *avf; | |
1851 | struct ath5k_buf *bf; | |
cec8db23 | 1852 | struct sk_buff *skb; |
fa1c114f | 1853 | |
be9b7259 | 1854 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n"); |
fa1c114f | 1855 | |
fa1c114f JS |
1856 | /* |
1857 | * Check if the previous beacon has gone out. If | |
a180a130 | 1858 | * not, don't don't try to post another: skip this |
fa1c114f JS |
1859 | * period and wait for the next. Missed beacons |
1860 | * indicate a problem and should not occur. If we | |
1861 | * miss too many consecutive beacons reset the device. | |
1862 | */ | |
1863 | if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) { | |
1864 | sc->bmisscount++; | |
be9b7259 | 1865 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, |
fa1c114f | 1866 | "missed %u consecutive beacons\n", sc->bmisscount); |
428cbd4f | 1867 | if (sc->bmisscount > 10) { /* NB: 10 is a guess */ |
be9b7259 | 1868 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, |
fa1c114f JS |
1869 | "stuck beacon time (%u missed)\n", |
1870 | sc->bmisscount); | |
8d67a031 BR |
1871 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, |
1872 | "stuck beacon, resetting\n"); | |
5faaff74 | 1873 | ieee80211_queue_work(sc->hw, &sc->reset_work); |
fa1c114f JS |
1874 | } |
1875 | return; | |
1876 | } | |
1877 | if (unlikely(sc->bmisscount != 0)) { | |
be9b7259 | 1878 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, |
fa1c114f JS |
1879 | "resume beacon xmit after %u misses\n", |
1880 | sc->bmisscount); | |
1881 | sc->bmisscount = 0; | |
1882 | } | |
1883 | ||
b1ae1edf BG |
1884 | if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) { |
1885 | u64 tsf = ath5k_hw_get_tsf64(ah); | |
1886 | u32 tsftu = TSF_TO_TU(tsf); | |
1887 | int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval; | |
1888 | vif = sc->bslot[(slot + 1) % ATH_BCBUF]; | |
1889 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, | |
1890 | "tsf %llx tsftu %x intval %u slot %u vif %p\n", | |
1891 | (unsigned long long)tsf, tsftu, sc->bintval, slot, vif); | |
1892 | } else /* only one interface */ | |
1893 | vif = sc->bslot[0]; | |
1894 | ||
1895 | if (!vif) | |
1896 | return; | |
1897 | ||
1898 | avf = (void *)vif->drv_priv; | |
1899 | bf = avf->bbuf; | |
1900 | if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION || | |
1901 | sc->opmode == NL80211_IFTYPE_MONITOR)) { | |
1902 | ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL); | |
1903 | return; | |
1904 | } | |
1905 | ||
fa1c114f JS |
1906 | /* |
1907 | * Stop any current dma and put the new frame on the queue. | |
1908 | * This should never fail since we check above that no frames | |
1909 | * are still pending on the queue. | |
1910 | */ | |
14fae2d4 | 1911 | if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) { |
428cbd4f | 1912 | ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq); |
fa1c114f JS |
1913 | /* NB: hw still stops DMA, so proceed */ |
1914 | } | |
fa1c114f | 1915 | |
1071db86 BC |
1916 | /* refresh the beacon for AP mode */ |
1917 | if (sc->opmode == NL80211_IFTYPE_AP) | |
b1ae1edf | 1918 | ath5k_beacon_update(sc->hw, vif); |
1071db86 | 1919 | |
c6e387a2 NK |
1920 | ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr); |
1921 | ath5k_hw_start_tx_dma(ah, sc->bhalq); | |
be9b7259 | 1922 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", |
fa1c114f JS |
1923 | sc->bhalq, (unsigned long long)bf->daddr, bf->desc); |
1924 | ||
b1ae1edf | 1925 | skb = ieee80211_get_buffered_bc(sc->hw, vif); |
cec8db23 BC |
1926 | while (skb) { |
1927 | ath5k_tx_queue(sc->hw, skb, sc->cabq); | |
b1ae1edf | 1928 | skb = ieee80211_get_buffered_bc(sc->hw, vif); |
cec8db23 BC |
1929 | } |
1930 | ||
fa1c114f JS |
1931 | sc->bsent++; |
1932 | } | |
1933 | ||
9804b98d BR |
1934 | /** |
1935 | * ath5k_beacon_update_timers - update beacon timers | |
1936 | * | |
1937 | * @sc: struct ath5k_softc pointer we are operating on | |
1938 | * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a | |
1939 | * beacon timer update based on the current HW TSF. | |
1940 | * | |
1941 | * Calculate the next target beacon transmit time (TBTT) based on the timestamp | |
1942 | * of a received beacon or the current local hardware TSF and write it to the | |
1943 | * beacon timer registers. | |
1944 | * | |
1945 | * This is called in a variety of situations, e.g. when a beacon is received, | |
6ba81c2c | 1946 | * when a TSF update has been detected, but also when an new IBSS is created or |
9804b98d BR |
1947 | * when we otherwise know we have to update the timers, but we keep it in this |
1948 | * function to have it all together in one place. | |
1949 | */ | |
fa1c114f | 1950 | static void |
9804b98d | 1951 | ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf) |
fa1c114f JS |
1952 | { |
1953 | struct ath5k_hw *ah = sc->ah; | |
9804b98d BR |
1954 | u32 nexttbtt, intval, hw_tu, bc_tu; |
1955 | u64 hw_tsf; | |
fa1c114f JS |
1956 | |
1957 | intval = sc->bintval & AR5K_BEACON_PERIOD; | |
b1ae1edf BG |
1958 | if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) { |
1959 | intval /= ATH_BCBUF; /* staggered multi-bss beacons */ | |
1960 | if (intval < 15) | |
1961 | ATH5K_WARN(sc, "intval %u is too low, min 15\n", | |
1962 | intval); | |
1963 | } | |
fa1c114f JS |
1964 | if (WARN_ON(!intval)) |
1965 | return; | |
1966 | ||
9804b98d BR |
1967 | /* beacon TSF converted to TU */ |
1968 | bc_tu = TSF_TO_TU(bc_tsf); | |
fa1c114f | 1969 | |
9804b98d BR |
1970 | /* current TSF converted to TU */ |
1971 | hw_tsf = ath5k_hw_get_tsf64(ah); | |
1972 | hw_tu = TSF_TO_TU(hw_tsf); | |
fa1c114f | 1973 | |
11f21df3 BR |
1974 | #define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3 |
1975 | /* We use FUDGE to make sure the next TBTT is ahead of the current TU. | |
1976 | * Since we later substract AR5K_TUNE_SW_BEACON_RESP (10) in the timer | |
1977 | * configuration we need to make sure it is bigger than that. */ | |
1978 | ||
9804b98d BR |
1979 | if (bc_tsf == -1) { |
1980 | /* | |
1981 | * no beacons received, called internally. | |
1982 | * just need to refresh timers based on HW TSF. | |
1983 | */ | |
1984 | nexttbtt = roundup(hw_tu + FUDGE, intval); | |
1985 | } else if (bc_tsf == 0) { | |
1986 | /* | |
1987 | * no beacon received, probably called by ath5k_reset_tsf(). | |
1988 | * reset TSF to start with 0. | |
1989 | */ | |
1990 | nexttbtt = intval; | |
1991 | intval |= AR5K_BEACON_RESET_TSF; | |
1992 | } else if (bc_tsf > hw_tsf) { | |
1993 | /* | |
1994 | * beacon received, SW merge happend but HW TSF not yet updated. | |
1995 | * not possible to reconfigure timers yet, but next time we | |
1996 | * receive a beacon with the same BSSID, the hardware will | |
1997 | * automatically update the TSF and then we need to reconfigure | |
1998 | * the timers. | |
1999 | */ | |
2000 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, | |
2001 | "need to wait for HW TSF sync\n"); | |
2002 | return; | |
2003 | } else { | |
2004 | /* | |
2005 | * most important case for beacon synchronization between STA. | |
2006 | * | |
2007 | * beacon received and HW TSF has been already updated by HW. | |
2008 | * update next TBTT based on the TSF of the beacon, but make | |
2009 | * sure it is ahead of our local TSF timer. | |
2010 | */ | |
2011 | nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval); | |
2012 | } | |
2013 | #undef FUDGE | |
fa1c114f | 2014 | |
036cd1ec BR |
2015 | sc->nexttbtt = nexttbtt; |
2016 | ||
fa1c114f | 2017 | intval |= AR5K_BEACON_ENA; |
fa1c114f | 2018 | ath5k_hw_init_beacon(ah, nexttbtt, intval); |
9804b98d BR |
2019 | |
2020 | /* | |
2021 | * debugging output last in order to preserve the time critical aspect | |
2022 | * of this function | |
2023 | */ | |
2024 | if (bc_tsf == -1) | |
2025 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, | |
2026 | "reconfigured timers based on HW TSF\n"); | |
2027 | else if (bc_tsf == 0) | |
2028 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, | |
2029 | "reset HW TSF and timers\n"); | |
2030 | else | |
2031 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, | |
2032 | "updated timers based on beacon TSF\n"); | |
2033 | ||
2034 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, | |
04f93a87 DM |
2035 | "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", |
2036 | (unsigned long long) bc_tsf, | |
2037 | (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); | |
9804b98d BR |
2038 | ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", |
2039 | intval & AR5K_BEACON_PERIOD, | |
2040 | intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", | |
2041 | intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); | |
fa1c114f JS |
2042 | } |
2043 | ||
036cd1ec BR |
2044 | /** |
2045 | * ath5k_beacon_config - Configure the beacon queues and interrupts | |
2046 | * | |
2047 | * @sc: struct ath5k_softc pointer we are operating on | |
fa1c114f | 2048 | * |
036cd1ec | 2049 | * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA |
6ba81c2c | 2050 | * interrupts to detect TSF updates only. |
fa1c114f JS |
2051 | */ |
2052 | static void | |
2053 | ath5k_beacon_config(struct ath5k_softc *sc) | |
2054 | { | |
2055 | struct ath5k_hw *ah = sc->ah; | |
b5f03956 | 2056 | unsigned long flags; |
fa1c114f | 2057 | |
21800491 | 2058 | spin_lock_irqsave(&sc->block, flags); |
fa1c114f | 2059 | sc->bmisscount = 0; |
dc1968e7 | 2060 | sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); |
fa1c114f | 2061 | |
21800491 | 2062 | if (sc->enable_beacon) { |
fa1c114f | 2063 | /* |
036cd1ec BR |
2064 | * In IBSS mode we use a self-linked tx descriptor and let the |
2065 | * hardware send the beacons automatically. We have to load it | |
fa1c114f | 2066 | * only once here. |
036cd1ec | 2067 | * We use the SWBA interrupt only to keep track of the beacon |
6ba81c2c | 2068 | * timers in order to detect automatic TSF updates. |
fa1c114f JS |
2069 | */ |
2070 | ath5k_beaconq_config(sc); | |
fa1c114f | 2071 | |
036cd1ec BR |
2072 | sc->imask |= AR5K_INT_SWBA; |
2073 | ||
da966bca | 2074 | if (sc->opmode == NL80211_IFTYPE_ADHOC) { |
21800491 | 2075 | if (ath5k_hw_hasveol(ah)) |
da966bca | 2076 | ath5k_beacon_send(sc); |
da966bca JS |
2077 | } else |
2078 | ath5k_beacon_update_timers(sc, -1); | |
21800491 | 2079 | } else { |
14fae2d4 | 2080 | ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq); |
fa1c114f | 2081 | } |
fa1c114f | 2082 | |
c6e387a2 | 2083 | ath5k_hw_set_imr(ah, sc->imask); |
21800491 BC |
2084 | mmiowb(); |
2085 | spin_unlock_irqrestore(&sc->block, flags); | |
fa1c114f JS |
2086 | } |
2087 | ||
428cbd4f NK |
2088 | static void ath5k_tasklet_beacon(unsigned long data) |
2089 | { | |
2090 | struct ath5k_softc *sc = (struct ath5k_softc *) data; | |
2091 | ||
2092 | /* | |
2093 | * Software beacon alert--time to send a beacon. | |
2094 | * | |
2095 | * In IBSS mode we use this interrupt just to | |
2096 | * keep track of the next TBTT (target beacon | |
2097 | * transmission time) in order to detect wether | |
2098 | * automatic TSF updates happened. | |
2099 | */ | |
2100 | if (sc->opmode == NL80211_IFTYPE_ADHOC) { | |
2101 | /* XXX: only if VEOL suppported */ | |
2102 | u64 tsf = ath5k_hw_get_tsf64(sc->ah); | |
2103 | sc->nexttbtt += sc->bintval; | |
2104 | ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, | |
2105 | "SWBA nexttbtt: %x hw_tu: %x " | |
2106 | "TSF: %llx\n", | |
2107 | sc->nexttbtt, | |
2108 | TSF_TO_TU(tsf), | |
2109 | (unsigned long long) tsf); | |
2110 | } else { | |
2111 | spin_lock(&sc->block); | |
2112 | ath5k_beacon_send(sc); | |
2113 | spin_unlock(&sc->block); | |
2114 | } | |
2115 | } | |
2116 | ||
fa1c114f JS |
2117 | |
2118 | /********************\ | |
2119 | * Interrupt handling * | |
2120 | \********************/ | |
2121 | ||
6a8a3f6b BR |
2122 | static void |
2123 | ath5k_intr_calibration_poll(struct ath5k_hw *ah) | |
2124 | { | |
2111ac0d BR |
2125 | if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) && |
2126 | !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) { | |
2127 | /* run ANI only when full calibration is not active */ | |
2128 | ah->ah_cal_next_ani = jiffies + | |
2129 | msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); | |
2130 | tasklet_schedule(&ah->ah_sc->ani_tasklet); | |
2131 | ||
2132 | } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) { | |
6a8a3f6b BR |
2133 | ah->ah_cal_next_full = jiffies + |
2134 | msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); | |
2135 | tasklet_schedule(&ah->ah_sc->calib); | |
2136 | } | |
2137 | /* we could use SWI to generate enough interrupts to meet our | |
2138 | * calibration interval requirements, if necessary: | |
2139 | * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */ | |
2140 | } | |
2141 | ||
132b1c3e | 2142 | irqreturn_t |
fa1c114f JS |
2143 | ath5k_intr(int irq, void *dev_id) |
2144 | { | |
2145 | struct ath5k_softc *sc = dev_id; | |
2146 | struct ath5k_hw *ah = sc->ah; | |
2147 | enum ath5k_int status; | |
2148 | unsigned int counter = 1000; | |
2149 | ||
2150 | if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) || | |
2151 | !ath5k_hw_is_intr_pending(ah))) | |
2152 | return IRQ_NONE; | |
2153 | ||
2154 | do { | |
fa1c114f JS |
2155 | ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ |
2156 | ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", | |
2157 | status, sc->imask); | |
fa1c114f JS |
2158 | if (unlikely(status & AR5K_INT_FATAL)) { |
2159 | /* | |
2160 | * Fatal errors are unrecoverable. | |
2161 | * Typically these are caused by DMA errors. | |
2162 | */ | |
8d67a031 BR |
2163 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, |
2164 | "fatal int, resetting\n"); | |
5faaff74 | 2165 | ieee80211_queue_work(sc->hw, &sc->reset_work); |
fa1c114f | 2166 | } else if (unlikely(status & AR5K_INT_RXORN)) { |
87d77c4e BR |
2167 | /* |
2168 | * Receive buffers are full. Either the bus is busy or | |
2169 | * the CPU is not fast enough to process all received | |
2170 | * frames. | |
2171 | * Older chipsets need a reset to come out of this | |
2172 | * condition, but we treat it as RX for newer chips. | |
2173 | * We don't know exactly which versions need a reset - | |
2174 | * this guess is copied from the HAL. | |
2175 | */ | |
2176 | sc->stats.rxorn_intr++; | |
8d67a031 BR |
2177 | if (ah->ah_mac_srev < AR5K_SREV_AR5212) { |
2178 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, | |
2179 | "rx overrun, resetting\n"); | |
5faaff74 | 2180 | ieee80211_queue_work(sc->hw, &sc->reset_work); |
8d67a031 | 2181 | } |
87d77c4e BR |
2182 | else |
2183 | tasklet_schedule(&sc->rxtq); | |
fa1c114f JS |
2184 | } else { |
2185 | if (status & AR5K_INT_SWBA) { | |
56d2ac76 | 2186 | tasklet_hi_schedule(&sc->beacontq); |
fa1c114f JS |
2187 | } |
2188 | if (status & AR5K_INT_RXEOL) { | |
2189 | /* | |
2190 | * NB: the hardware should re-read the link when | |
2191 | * RXE bit is written, but it doesn't work at | |
2192 | * least on older hardware revs. | |
2193 | */ | |
b3f194e5 | 2194 | sc->stats.rxeol_intr++; |
fa1c114f JS |
2195 | } |
2196 | if (status & AR5K_INT_TXURN) { | |
2197 | /* bump tx trigger level */ | |
2198 | ath5k_hw_update_tx_triglevel(ah, true); | |
2199 | } | |
4c674c60 | 2200 | if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) |
fa1c114f | 2201 | tasklet_schedule(&sc->rxtq); |
4c674c60 NK |
2202 | if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC |
2203 | | AR5K_INT_TXERR | AR5K_INT_TXEOL)) | |
fa1c114f JS |
2204 | tasklet_schedule(&sc->txtq); |
2205 | if (status & AR5K_INT_BMISS) { | |
1e3e6e8f | 2206 | /* TODO */ |
fa1c114f JS |
2207 | } |
2208 | if (status & AR5K_INT_MIB) { | |
2111ac0d | 2209 | sc->stats.mib_intr++; |
495391d7 | 2210 | ath5k_hw_update_mib_counters(ah); |
2111ac0d | 2211 | ath5k_ani_mib_intr(ah); |
fa1c114f | 2212 | } |
e6a3b616 | 2213 | if (status & AR5K_INT_GPIO) |
e6a3b616 | 2214 | tasklet_schedule(&sc->rf_kill.toggleq); |
a6ae0716 | 2215 | |
fa1c114f | 2216 | } |
2516baa6 | 2217 | } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); |
fa1c114f JS |
2218 | |
2219 | if (unlikely(!counter)) | |
2220 | ATH5K_WARN(sc, "too many interrupts, giving up for now\n"); | |
2221 | ||
6a8a3f6b | 2222 | ath5k_intr_calibration_poll(ah); |
6e220662 | 2223 | |
fa1c114f JS |
2224 | return IRQ_HANDLED; |
2225 | } | |
2226 | ||
fa1c114f JS |
2227 | /* |
2228 | * Periodically recalibrate the PHY to account | |
2229 | * for temperature/environment changes. | |
2230 | */ | |
2231 | static void | |
6e220662 | 2232 | ath5k_tasklet_calibrate(unsigned long data) |
fa1c114f JS |
2233 | { |
2234 | struct ath5k_softc *sc = (void *)data; | |
2235 | struct ath5k_hw *ah = sc->ah; | |
2236 | ||
6e220662 | 2237 | /* Only full calibration for now */ |
e65e1d77 | 2238 | ah->ah_cal_mask |= AR5K_CALIBRATION_FULL; |
6e220662 | 2239 | |
fa1c114f | 2240 | ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", |
400ec45a LR |
2241 | ieee80211_frequency_to_channel(sc->curchan->center_freq), |
2242 | sc->curchan->hw_value); | |
fa1c114f | 2243 | |
6f3b414a | 2244 | if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { |
fa1c114f JS |
2245 | /* |
2246 | * Rfgain is out of bounds, reset the chip | |
2247 | * to load new gain values. | |
2248 | */ | |
2249 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n"); | |
5faaff74 | 2250 | ieee80211_queue_work(sc->hw, &sc->reset_work); |
fa1c114f JS |
2251 | } |
2252 | if (ath5k_hw_phy_calibrate(ah, sc->curchan)) | |
2253 | ATH5K_ERR(sc, "calibration of channel %u failed\n", | |
400ec45a LR |
2254 | ieee80211_frequency_to_channel( |
2255 | sc->curchan->center_freq)); | |
fa1c114f | 2256 | |
0e8e02dd | 2257 | /* Noise floor calibration interrupts rx/tx path while I/Q calibration |
651d9375 BR |
2258 | * doesn't. |
2259 | * TODO: We should stop TX here, so that it doesn't interfere. | |
2260 | * Note that stopping the queues is not enough to stop TX! */ | |
afe86286 BR |
2261 | if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) { |
2262 | ah->ah_cal_next_nf = jiffies + | |
2263 | msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF); | |
afe86286 | 2264 | ath5k_hw_update_noise_floor(ah); |
afe86286 | 2265 | } |
6e220662 | 2266 | |
e65e1d77 | 2267 | ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL; |
fa1c114f JS |
2268 | } |
2269 | ||
2270 | ||
2111ac0d BR |
2271 | static void |
2272 | ath5k_tasklet_ani(unsigned long data) | |
2273 | { | |
2274 | struct ath5k_softc *sc = (void *)data; | |
2275 | struct ath5k_hw *ah = sc->ah; | |
2276 | ||
2277 | ah->ah_cal_mask |= AR5K_CALIBRATION_ANI; | |
2278 | ath5k_ani_calibration(ah); | |
2279 | ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI; | |
fa1c114f JS |
2280 | } |
2281 | ||
2282 | ||
4edd761f BR |
2283 | static void |
2284 | ath5k_tx_complete_poll_work(struct work_struct *work) | |
2285 | { | |
2286 | struct ath5k_softc *sc = container_of(work, struct ath5k_softc, | |
2287 | tx_complete_work.work); | |
2288 | struct ath5k_txq *txq; | |
2289 | int i; | |
2290 | bool needreset = false; | |
2291 | ||
2292 | for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) { | |
2293 | if (sc->txqs[i].setup) { | |
2294 | txq = &sc->txqs[i]; | |
2295 | spin_lock_bh(&txq->lock); | |
23413296 | 2296 | if (txq->txq_len > 1) { |
4edd761f BR |
2297 | if (txq->txq_poll_mark) { |
2298 | ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, | |
2299 | "TX queue stuck %d\n", | |
2300 | txq->qnum); | |
2301 | needreset = true; | |
923e5b3d | 2302 | txq->txq_stuck++; |
4edd761f BR |
2303 | spin_unlock_bh(&txq->lock); |
2304 | break; | |
2305 | } else { | |
2306 | txq->txq_poll_mark = true; | |
2307 | } | |
2308 | } | |
2309 | spin_unlock_bh(&txq->lock); | |
2310 | } | |
2311 | } | |
2312 | ||
2313 | if (needreset) { | |
2314 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, | |
2315 | "TX queues stuck, resetting\n"); | |
8aec7af9 | 2316 | ath5k_reset(sc, NULL, true); |
4edd761f BR |
2317 | } |
2318 | ||
2319 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, | |
2320 | msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); | |
2321 | } | |
2322 | ||
2323 | ||
8a63facc BC |
2324 | /*************************\ |
2325 | * Initialization routines * | |
2326 | \*************************/ | |
fa1c114f | 2327 | |
132b1c3e FF |
2328 | int |
2329 | ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops) | |
2330 | { | |
2331 | struct ieee80211_hw *hw = sc->hw; | |
2332 | struct ath_common *common; | |
2333 | int ret; | |
2334 | int csz; | |
2335 | ||
2336 | /* Initialize driver private data */ | |
2337 | SET_IEEE80211_DEV(hw, sc->dev); | |
2338 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | | |
2339 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | | |
2340 | IEEE80211_HW_SIGNAL_DBM; | |
2341 | ||
2342 | hw->wiphy->interface_modes = | |
2343 | BIT(NL80211_IFTYPE_AP) | | |
2344 | BIT(NL80211_IFTYPE_STATION) | | |
2345 | BIT(NL80211_IFTYPE_ADHOC) | | |
2346 | BIT(NL80211_IFTYPE_MESH_POINT); | |
2347 | ||
2348 | hw->extra_tx_headroom = 2; | |
2349 | hw->channel_change_time = 5000; | |
2350 | ||
2351 | /* | |
2352 | * Mark the device as detached to avoid processing | |
2353 | * interrupts until setup is complete. | |
2354 | */ | |
2355 | __set_bit(ATH_STAT_INVALID, sc->status); | |
2356 | ||
2357 | sc->opmode = NL80211_IFTYPE_STATION; | |
2358 | sc->bintval = 1000; | |
2359 | mutex_init(&sc->lock); | |
2360 | spin_lock_init(&sc->rxbuflock); | |
2361 | spin_lock_init(&sc->txbuflock); | |
2362 | spin_lock_init(&sc->block); | |
2363 | ||
2364 | ||
2365 | /* Setup interrupt handler */ | |
2366 | ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc); | |
2367 | if (ret) { | |
2368 | ATH5K_ERR(sc, "request_irq failed\n"); | |
2369 | goto err; | |
2370 | } | |
2371 | ||
2372 | /* If we passed the test, malloc an ath5k_hw struct */ | |
2373 | sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL); | |
2374 | if (!sc->ah) { | |
2375 | ret = -ENOMEM; | |
2376 | ATH5K_ERR(sc, "out of memory\n"); | |
2377 | goto err_irq; | |
2378 | } | |
2379 | ||
2380 | sc->ah->ah_sc = sc; | |
2381 | sc->ah->ah_iobase = sc->iobase; | |
2382 | common = ath5k_hw_common(sc->ah); | |
2383 | common->ops = &ath5k_common_ops; | |
2384 | common->bus_ops = bus_ops; | |
2385 | common->ah = sc->ah; | |
2386 | common->hw = hw; | |
2387 | common->priv = sc; | |
2388 | ||
2389 | /* | |
2390 | * Cache line size is used to size and align various | |
2391 | * structures used to communicate with the hardware. | |
2392 | */ | |
2393 | ath5k_read_cachesize(common, &csz); | |
2394 | common->cachelsz = csz << 2; /* convert to bytes */ | |
2395 | ||
2396 | spin_lock_init(&common->cc_lock); | |
2397 | ||
2398 | /* Initialize device */ | |
2399 | ret = ath5k_hw_init(sc); | |
2400 | if (ret) | |
2401 | goto err_free_ah; | |
2402 | ||
2403 | /* set up multi-rate retry capabilities */ | |
2404 | if (sc->ah->ah_version == AR5K_AR5212) { | |
2405 | hw->max_rates = 4; | |
2406 | hw->max_rate_tries = 11; | |
2407 | } | |
2408 | ||
2409 | hw->vif_data_size = sizeof(struct ath5k_vif); | |
2410 | ||
2411 | /* Finish private driver data initialization */ | |
2412 | ret = ath5k_init(hw); | |
2413 | if (ret) | |
2414 | goto err_ah; | |
2415 | ||
2416 | ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", | |
2417 | ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev), | |
2418 | sc->ah->ah_mac_srev, | |
2419 | sc->ah->ah_phy_revision); | |
2420 | ||
2421 | if (!sc->ah->ah_single_chip) { | |
2422 | /* Single chip radio (!RF5111) */ | |
2423 | if (sc->ah->ah_radio_5ghz_revision && | |
2424 | !sc->ah->ah_radio_2ghz_revision) { | |
2425 | /* No 5GHz support -> report 2GHz radio */ | |
2426 | if (!test_bit(AR5K_MODE_11A, | |
2427 | sc->ah->ah_capabilities.cap_mode)) { | |
2428 | ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", | |
2429 | ath5k_chip_name(AR5K_VERSION_RAD, | |
2430 | sc->ah->ah_radio_5ghz_revision), | |
2431 | sc->ah->ah_radio_5ghz_revision); | |
2432 | /* No 2GHz support (5110 and some | |
2433 | * 5Ghz only cards) -> report 5Ghz radio */ | |
2434 | } else if (!test_bit(AR5K_MODE_11B, | |
2435 | sc->ah->ah_capabilities.cap_mode)) { | |
2436 | ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", | |
2437 | ath5k_chip_name(AR5K_VERSION_RAD, | |
2438 | sc->ah->ah_radio_5ghz_revision), | |
2439 | sc->ah->ah_radio_5ghz_revision); | |
2440 | /* Multiband radio */ | |
2441 | } else { | |
2442 | ATH5K_INFO(sc, "RF%s multiband radio found" | |
2443 | " (0x%x)\n", | |
2444 | ath5k_chip_name(AR5K_VERSION_RAD, | |
2445 | sc->ah->ah_radio_5ghz_revision), | |
2446 | sc->ah->ah_radio_5ghz_revision); | |
2447 | } | |
2448 | } | |
2449 | /* Multi chip radio (RF5111 - RF2111) -> | |
2450 | * report both 2GHz/5GHz radios */ | |
2451 | else if (sc->ah->ah_radio_5ghz_revision && | |
2452 | sc->ah->ah_radio_2ghz_revision){ | |
2453 | ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", | |
2454 | ath5k_chip_name(AR5K_VERSION_RAD, | |
2455 | sc->ah->ah_radio_5ghz_revision), | |
2456 | sc->ah->ah_radio_5ghz_revision); | |
2457 | ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", | |
2458 | ath5k_chip_name(AR5K_VERSION_RAD, | |
2459 | sc->ah->ah_radio_2ghz_revision), | |
2460 | sc->ah->ah_radio_2ghz_revision); | |
2461 | } | |
2462 | } | |
2463 | ||
2464 | ath5k_debug_init_device(sc); | |
2465 | ||
2466 | /* ready to process interrupts */ | |
2467 | __clear_bit(ATH_STAT_INVALID, sc->status); | |
2468 | ||
2469 | return 0; | |
2470 | err_ah: | |
2471 | ath5k_hw_deinit(sc->ah); | |
2472 | err_free_ah: | |
2473 | kfree(sc->ah); | |
2474 | err_irq: | |
2475 | free_irq(sc->irq, sc); | |
2476 | err: | |
2477 | return ret; | |
2478 | } | |
2479 | ||
fa1c114f | 2480 | static int |
8a63facc | 2481 | ath5k_stop_locked(struct ath5k_softc *sc) |
cec8db23 | 2482 | { |
8a63facc | 2483 | struct ath5k_hw *ah = sc->ah; |
cec8db23 | 2484 | |
8a63facc BC |
2485 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n", |
2486 | test_bit(ATH_STAT_INVALID, sc->status)); | |
2487 | ||
2488 | /* | |
2489 | * Shutdown the hardware and driver: | |
2490 | * stop output from above | |
2491 | * disable interrupts | |
2492 | * turn off timers | |
2493 | * turn off the radio | |
2494 | * clear transmit machinery | |
2495 | * clear receive machinery | |
2496 | * drain and release tx queues | |
2497 | * reclaim beacon resources | |
2498 | * power down hardware | |
2499 | * | |
2500 | * Note that some of this work is not possible if the | |
2501 | * hardware is gone (invalid). | |
2502 | */ | |
2503 | ieee80211_stop_queues(sc->hw); | |
2504 | ||
2505 | if (!test_bit(ATH_STAT_INVALID, sc->status)) { | |
2506 | ath5k_led_off(sc); | |
2507 | ath5k_hw_set_imr(ah, 0); | |
aeae4ac9 | 2508 | synchronize_irq(sc->irq); |
8a63facc | 2509 | ath5k_rx_stop(sc); |
80dac9ee NK |
2510 | ath5k_hw_dma_stop(ah); |
2511 | ath5k_drain_tx_buffs(sc); | |
8a63facc BC |
2512 | ath5k_hw_phy_disable(ah); |
2513 | } | |
2514 | ||
2515 | return 0; | |
cec8db23 BC |
2516 | } |
2517 | ||
8a63facc | 2518 | static int |
132b1c3e | 2519 | ath5k_init_hw(struct ath5k_softc *sc) |
fa1c114f | 2520 | { |
8a63facc BC |
2521 | struct ath5k_hw *ah = sc->ah; |
2522 | struct ath_common *common = ath5k_hw_common(ah); | |
2523 | int ret, i; | |
fa1c114f | 2524 | |
8a63facc BC |
2525 | mutex_lock(&sc->lock); |
2526 | ||
2527 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode); | |
fa1c114f | 2528 | |
fa1c114f | 2529 | /* |
8a63facc BC |
2530 | * Stop anything previously setup. This is safe |
2531 | * no matter this is the first time through or not. | |
fa1c114f | 2532 | */ |
8a63facc | 2533 | ath5k_stop_locked(sc); |
fa1c114f | 2534 | |
8a63facc BC |
2535 | /* |
2536 | * The basic interface to setting the hardware in a good | |
2537 | * state is ``reset''. On return the hardware is known to | |
2538 | * be powered up and with interrupts disabled. This must | |
2539 | * be followed by initialization of the appropriate bits | |
2540 | * and then setup of the interrupt mask. | |
2541 | */ | |
2542 | sc->curchan = sc->hw->conf.channel; | |
2543 | sc->curband = &sc->sbands[sc->curchan->band]; | |
2544 | sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL | | |
2545 | AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL | | |
2546 | AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB; | |
fa1c114f | 2547 | |
8aec7af9 | 2548 | ret = ath5k_reset(sc, NULL, false); |
8a63facc BC |
2549 | if (ret) |
2550 | goto done; | |
fa1c114f | 2551 | |
8a63facc BC |
2552 | ath5k_rfkill_hw_start(ah); |
2553 | ||
2554 | /* | |
2555 | * Reset the key cache since some parts do not reset the | |
2556 | * contents on initial power up or resume from suspend. | |
2557 | */ | |
2558 | for (i = 0; i < common->keymax; i++) | |
2559 | ath_hw_keyreset(common, (u16) i); | |
2560 | ||
61cde037 NK |
2561 | /* Use higher rates for acks instead of base |
2562 | * rate */ | |
2563 | ah->ah_ack_bitrate_high = true; | |
b1ae1edf BG |
2564 | |
2565 | for (i = 0; i < ARRAY_SIZE(sc->bslot); i++) | |
2566 | sc->bslot[i] = NULL; | |
2567 | ||
8a63facc BC |
2568 | ret = 0; |
2569 | done: | |
2570 | mmiowb(); | |
2571 | mutex_unlock(&sc->lock); | |
4edd761f BR |
2572 | |
2573 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, | |
2574 | msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); | |
2575 | ||
8a63facc BC |
2576 | return ret; |
2577 | } | |
2578 | ||
2579 | static void stop_tasklets(struct ath5k_softc *sc) | |
2580 | { | |
2581 | tasklet_kill(&sc->rxtq); | |
2582 | tasklet_kill(&sc->txtq); | |
2583 | tasklet_kill(&sc->calib); | |
2584 | tasklet_kill(&sc->beacontq); | |
2585 | tasklet_kill(&sc->ani_tasklet); | |
2586 | } | |
2587 | ||
2588 | /* | |
2589 | * Stop the device, grabbing the top-level lock to protect | |
2590 | * against concurrent entry through ath5k_init (which can happen | |
2591 | * if another thread does a system call and the thread doing the | |
2592 | * stop is preempted). | |
2593 | */ | |
2594 | static int | |
2595 | ath5k_stop_hw(struct ath5k_softc *sc) | |
2596 | { | |
2597 | int ret; | |
2598 | ||
2599 | mutex_lock(&sc->lock); | |
2600 | ret = ath5k_stop_locked(sc); | |
2601 | if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) { | |
2602 | /* | |
2603 | * Don't set the card in full sleep mode! | |
2604 | * | |
2605 | * a) When the device is in this state it must be carefully | |
2606 | * woken up or references to registers in the PCI clock | |
2607 | * domain may freeze the bus (and system). This varies | |
2608 | * by chip and is mostly an issue with newer parts | |
2609 | * (madwifi sources mentioned srev >= 0x78) that go to | |
2610 | * sleep more quickly. | |
2611 | * | |
2612 | * b) On older chips full sleep results a weird behaviour | |
2613 | * during wakeup. I tested various cards with srev < 0x78 | |
2614 | * and they don't wake up after module reload, a second | |
2615 | * module reload is needed to bring the card up again. | |
2616 | * | |
2617 | * Until we figure out what's going on don't enable | |
2618 | * full chip reset on any chip (this is what Legacy HAL | |
2619 | * and Sam's HAL do anyway). Instead Perform a full reset | |
2620 | * on the device (same as initial state after attach) and | |
2621 | * leave it idle (keep MAC/BB on warm reset) */ | |
2622 | ret = ath5k_hw_on_hold(sc->ah); | |
2623 | ||
2624 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, | |
2625 | "putting device to sleep\n"); | |
fa1c114f JS |
2626 | } |
2627 | ||
8a63facc BC |
2628 | mmiowb(); |
2629 | mutex_unlock(&sc->lock); | |
2630 | ||
2631 | stop_tasklets(sc); | |
2632 | ||
4edd761f BR |
2633 | cancel_delayed_work_sync(&sc->tx_complete_work); |
2634 | ||
8a63facc BC |
2635 | ath5k_rfkill_hw_stop(sc->ah); |
2636 | ||
2637 | return ret; | |
fa1c114f JS |
2638 | } |
2639 | ||
209d889b BC |
2640 | /* |
2641 | * Reset the hardware. If chan is not NULL, then also pause rx/tx | |
2642 | * and change to the given channel. | |
5faaff74 BC |
2643 | * |
2644 | * This should be called with sc->lock. | |
209d889b | 2645 | */ |
fa1c114f | 2646 | static int |
8aec7af9 NK |
2647 | ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan, |
2648 | bool skip_pcu) | |
fa1c114f | 2649 | { |
fa1c114f JS |
2650 | struct ath5k_hw *ah = sc->ah; |
2651 | int ret; | |
2652 | ||
2653 | ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n"); | |
fa1c114f | 2654 | |
450464de | 2655 | ath5k_hw_set_imr(ah, 0); |
aeae4ac9 | 2656 | synchronize_irq(sc->irq); |
450464de BC |
2657 | stop_tasklets(sc); |
2658 | ||
209d889b | 2659 | if (chan) { |
80dac9ee | 2660 | ath5k_drain_tx_buffs(sc); |
209d889b BC |
2661 | |
2662 | sc->curchan = chan; | |
2663 | sc->curband = &sc->sbands[chan->band]; | |
d7dc1003 | 2664 | } |
8aec7af9 NK |
2665 | ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL, |
2666 | skip_pcu); | |
d7dc1003 | 2667 | if (ret) { |
fa1c114f JS |
2668 | ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret); |
2669 | goto err; | |
2670 | } | |
d7dc1003 | 2671 | |
fa1c114f | 2672 | ret = ath5k_rx_start(sc); |
d7dc1003 | 2673 | if (ret) { |
fa1c114f JS |
2674 | ATH5K_ERR(sc, "can't start recv logic\n"); |
2675 | goto err; | |
2676 | } | |
d7dc1003 | 2677 | |
2111ac0d BR |
2678 | ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode); |
2679 | ||
ac559526 BR |
2680 | ah->ah_cal_next_full = jiffies; |
2681 | ah->ah_cal_next_ani = jiffies; | |
afe86286 | 2682 | ah->ah_cal_next_nf = jiffies; |
eef39bef | 2683 | ewma_init(&ah->ah_beacon_rssi_avg, 1000, 8); |
afe86286 | 2684 | |
fa1c114f | 2685 | /* |
d7dc1003 JS |
2686 | * Change channels and update the h/w rate map if we're switching; |
2687 | * e.g. 11a to 11b/g. | |
2688 | * | |
2689 | * We may be doing a reset in response to an ioctl that changes the | |
2690 | * channel so update any state that might change as a result. | |
fa1c114f JS |
2691 | * |
2692 | * XXX needed? | |
2693 | */ | |
2694 | /* ath5k_chan_change(sc, c); */ | |
fa1c114f | 2695 | |
d7dc1003 JS |
2696 | ath5k_beacon_config(sc); |
2697 | /* intrs are enabled by ath5k_beacon_config */ | |
fa1c114f | 2698 | |
397f385b BR |
2699 | ieee80211_wake_queues(sc->hw); |
2700 | ||
fa1c114f JS |
2701 | return 0; |
2702 | err: | |
2703 | return ret; | |
2704 | } | |
2705 | ||
5faaff74 BC |
2706 | static void ath5k_reset_work(struct work_struct *work) |
2707 | { | |
2708 | struct ath5k_softc *sc = container_of(work, struct ath5k_softc, | |
2709 | reset_work); | |
2710 | ||
2711 | mutex_lock(&sc->lock); | |
8aec7af9 | 2712 | ath5k_reset(sc, NULL, true); |
5faaff74 BC |
2713 | mutex_unlock(&sc->lock); |
2714 | } | |
2715 | ||
8a63facc | 2716 | static int |
132b1c3e | 2717 | ath5k_init(struct ieee80211_hw *hw) |
fa1c114f | 2718 | { |
132b1c3e | 2719 | |
fa1c114f | 2720 | struct ath5k_softc *sc = hw->priv; |
8a63facc BC |
2721 | struct ath5k_hw *ah = sc->ah; |
2722 | struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); | |
925e0b06 | 2723 | struct ath5k_txq *txq; |
8a63facc | 2724 | u8 mac[ETH_ALEN] = {}; |
fa1c114f JS |
2725 | int ret; |
2726 | ||
fa1c114f | 2727 | |
8a63facc BC |
2728 | /* |
2729 | * Check if the MAC has multi-rate retry support. | |
2730 | * We do this by trying to setup a fake extended | |
2731 | * descriptor. MACs that don't have support will | |
2732 | * return false w/o doing anything. MACs that do | |
2733 | * support it will return true w/o doing anything. | |
2734 | */ | |
2735 | ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); | |
67d2e2df | 2736 | |
8a63facc BC |
2737 | if (ret < 0) |
2738 | goto err; | |
2739 | if (ret > 0) | |
2740 | __set_bit(ATH_STAT_MRRETRY, sc->status); | |
ccfe5552 | 2741 | |
8a63facc BC |
2742 | /* |
2743 | * Collect the channel list. The 802.11 layer | |
2744 | * is resposible for filtering this list based | |
2745 | * on settings like the phy mode and regulatory | |
2746 | * domain restrictions. | |
2747 | */ | |
2748 | ret = ath5k_setup_bands(hw); | |
2749 | if (ret) { | |
2750 | ATH5K_ERR(sc, "can't get channels\n"); | |
2751 | goto err; | |
2752 | } | |
67d2e2df | 2753 | |
8a63facc BC |
2754 | /* NB: setup here so ath5k_rate_update is happy */ |
2755 | if (test_bit(AR5K_MODE_11A, ah->ah_modes)) | |
2756 | ath5k_setcurmode(sc, AR5K_MODE_11A); | |
2757 | else | |
2758 | ath5k_setcurmode(sc, AR5K_MODE_11B); | |
fa1c114f | 2759 | |
8a63facc BC |
2760 | /* |
2761 | * Allocate tx+rx descriptors and populate the lists. | |
2762 | */ | |
aeae4ac9 | 2763 | ret = ath5k_desc_alloc(sc); |
8a63facc BC |
2764 | if (ret) { |
2765 | ATH5K_ERR(sc, "can't allocate descriptors\n"); | |
2766 | goto err; | |
2767 | } | |
fa1c114f | 2768 | |
8a63facc BC |
2769 | /* |
2770 | * Allocate hardware transmit queues: one queue for | |
2771 | * beacon frames and one data queue for each QoS | |
2772 | * priority. Note that hw functions handle resetting | |
2773 | * these queues at the needed time. | |
2774 | */ | |
2775 | ret = ath5k_beaconq_setup(ah); | |
2776 | if (ret < 0) { | |
2777 | ATH5K_ERR(sc, "can't setup a beacon xmit queue\n"); | |
2778 | goto err_desc; | |
2779 | } | |
2780 | sc->bhalq = ret; | |
2781 | sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0); | |
2782 | if (IS_ERR(sc->cabq)) { | |
2783 | ATH5K_ERR(sc, "can't setup cab queue\n"); | |
2784 | ret = PTR_ERR(sc->cabq); | |
2785 | goto err_bhal; | |
2786 | } | |
fa1c114f | 2787 | |
925e0b06 BR |
2788 | /* This order matches mac80211's queue priority, so we can |
2789 | * directly use the mac80211 queue number without any mapping */ | |
2790 | txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO); | |
2791 | if (IS_ERR(txq)) { | |
2792 | ATH5K_ERR(sc, "can't setup xmit queue\n"); | |
2793 | ret = PTR_ERR(txq); | |
2794 | goto err_queues; | |
2795 | } | |
2796 | txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI); | |
2797 | if (IS_ERR(txq)) { | |
8a63facc | 2798 | ATH5K_ERR(sc, "can't setup xmit queue\n"); |
925e0b06 | 2799 | ret = PTR_ERR(txq); |
8a63facc BC |
2800 | goto err_queues; |
2801 | } | |
925e0b06 BR |
2802 | txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); |
2803 | if (IS_ERR(txq)) { | |
2804 | ATH5K_ERR(sc, "can't setup xmit queue\n"); | |
2805 | ret = PTR_ERR(txq); | |
2806 | goto err_queues; | |
2807 | } | |
2808 | txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); | |
2809 | if (IS_ERR(txq)) { | |
2810 | ATH5K_ERR(sc, "can't setup xmit queue\n"); | |
2811 | ret = PTR_ERR(txq); | |
2812 | goto err_queues; | |
2813 | } | |
2814 | hw->queues = 4; | |
fa1c114f | 2815 | |
8a63facc BC |
2816 | tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc); |
2817 | tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc); | |
2818 | tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc); | |
2819 | tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc); | |
2820 | tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc); | |
be009370 | 2821 | |
8a63facc | 2822 | INIT_WORK(&sc->reset_work, ath5k_reset_work); |
4edd761f | 2823 | INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work); |
fa1c114f | 2824 | |
8a63facc BC |
2825 | ret = ath5k_eeprom_read_mac(ah, mac); |
2826 | if (ret) { | |
aeae4ac9 | 2827 | ATH5K_ERR(sc, "unable to read address from EEPROM\n"); |
8a63facc | 2828 | goto err_queues; |
e30eb4ab | 2829 | } |
2bed03eb | 2830 | |
8a63facc | 2831 | SET_IEEE80211_PERM_ADDR(hw, mac); |
b1ae1edf | 2832 | memcpy(&sc->lladdr, mac, ETH_ALEN); |
8a63facc | 2833 | /* All MAC address bits matter for ACKs */ |
62c58fb4 | 2834 | ath5k_update_bssid_mask_and_opmode(sc, NULL); |
8a63facc BC |
2835 | |
2836 | regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; | |
2837 | ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); | |
2838 | if (ret) { | |
2839 | ATH5K_ERR(sc, "can't initialize regulatory system\n"); | |
2840 | goto err_queues; | |
2841 | } | |
2842 | ||
2843 | ret = ieee80211_register_hw(hw); | |
2844 | if (ret) { | |
2845 | ATH5K_ERR(sc, "can't register ieee80211 hw\n"); | |
2846 | goto err_queues; | |
2847 | } | |
2848 | ||
2849 | if (!ath_is_world_regd(regulatory)) | |
2850 | regulatory_hint(hw->wiphy, regulatory->alpha2); | |
2851 | ||
2852 | ath5k_init_leds(sc); | |
2853 | ||
2854 | ath5k_sysfs_register(sc); | |
2855 | ||
2856 | return 0; | |
2857 | err_queues: | |
2858 | ath5k_txq_release(sc); | |
2859 | err_bhal: | |
2860 | ath5k_hw_release_tx_queue(ah, sc->bhalq); | |
2861 | err_desc: | |
aeae4ac9 | 2862 | ath5k_desc_free(sc); |
8a63facc BC |
2863 | err: |
2864 | return ret; | |
2865 | } | |
2866 | ||
132b1c3e FF |
2867 | void |
2868 | ath5k_deinit_softc(struct ath5k_softc *sc) | |
8a63facc | 2869 | { |
132b1c3e | 2870 | struct ieee80211_hw *hw = sc->hw; |
8a63facc BC |
2871 | |
2872 | /* | |
2873 | * NB: the order of these is important: | |
2874 | * o call the 802.11 layer before detaching ath5k_hw to | |
2875 | * ensure callbacks into the driver to delete global | |
2876 | * key cache entries can be handled | |
2877 | * o reclaim the tx queue data structures after calling | |
2878 | * the 802.11 layer as we'll get called back to reclaim | |
2879 | * node state and potentially want to use them | |
2880 | * o to cleanup the tx queues the hal is called, so detach | |
2881 | * it last | |
2882 | * XXX: ??? detach ath5k_hw ??? | |
2883 | * Other than that, it's straightforward... | |
2884 | */ | |
132b1c3e | 2885 | ath5k_debug_finish_device(sc); |
8a63facc | 2886 | ieee80211_unregister_hw(hw); |
aeae4ac9 | 2887 | ath5k_desc_free(sc); |
8a63facc BC |
2888 | ath5k_txq_release(sc); |
2889 | ath5k_hw_release_tx_queue(sc->ah, sc->bhalq); | |
2890 | ath5k_unregister_leds(sc); | |
2891 | ||
2892 | ath5k_sysfs_unregister(sc); | |
2893 | /* | |
2894 | * NB: can't reclaim these until after ieee80211_ifdetach | |
2895 | * returns because we'll get called back to reclaim node | |
2896 | * state and potentially want to use them. | |
2897 | */ | |
132b1c3e FF |
2898 | ath5k_hw_deinit(sc->ah); |
2899 | free_irq(sc->irq, sc); | |
8a63facc BC |
2900 | } |
2901 | ||
2902 | /********************\ | |
2903 | * Mac80211 functions * | |
2904 | \********************/ | |
2905 | ||
2906 | static int | |
2907 | ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |
2908 | { | |
2909 | struct ath5k_softc *sc = hw->priv; | |
925e0b06 BR |
2910 | u16 qnum = skb_get_queue_mapping(skb); |
2911 | ||
2912 | if (WARN_ON(qnum >= sc->ah->ah_capabilities.cap_queues.q_tx_num)) { | |
2913 | dev_kfree_skb_any(skb); | |
2914 | return 0; | |
2915 | } | |
8a63facc | 2916 | |
925e0b06 | 2917 | return ath5k_tx_queue(hw, skb, &sc->txqs[qnum]); |
8a63facc BC |
2918 | } |
2919 | ||
2920 | static int ath5k_start(struct ieee80211_hw *hw) | |
2921 | { | |
132b1c3e | 2922 | return ath5k_init_hw(hw->priv); |
8a63facc BC |
2923 | } |
2924 | ||
2925 | static void ath5k_stop(struct ieee80211_hw *hw) | |
2926 | { | |
2927 | ath5k_stop_hw(hw->priv); | |
2928 | } | |
2929 | ||
2930 | static int ath5k_add_interface(struct ieee80211_hw *hw, | |
2931 | struct ieee80211_vif *vif) | |
2932 | { | |
2933 | struct ath5k_softc *sc = hw->priv; | |
2934 | int ret; | |
b1ae1edf | 2935 | struct ath5k_vif *avf = (void *)vif->drv_priv; |
8a63facc BC |
2936 | |
2937 | mutex_lock(&sc->lock); | |
b1ae1edf BG |
2938 | |
2939 | if ((vif->type == NL80211_IFTYPE_AP || | |
2940 | vif->type == NL80211_IFTYPE_ADHOC) | |
2941 | && (sc->num_ap_vifs + sc->num_adhoc_vifs) >= ATH_BCBUF) { | |
2942 | ret = -ELNRNG; | |
8a63facc BC |
2943 | goto end; |
2944 | } | |
2945 | ||
b1ae1edf BG |
2946 | /* Don't allow other interfaces if one ad-hoc is configured. |
2947 | * TODO: Fix the problems with ad-hoc and multiple other interfaces. | |
2948 | * We would need to operate the HW in ad-hoc mode to allow TSF updates | |
2949 | * for the IBSS, but this breaks with additional AP or STA interfaces | |
2950 | * at the moment. */ | |
2951 | if (sc->num_adhoc_vifs || | |
2952 | (sc->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) { | |
2953 | ATH5K_ERR(sc, "Only one single ad-hoc interface is allowed.\n"); | |
2954 | ret = -ELNRNG; | |
2955 | goto end; | |
2956 | } | |
8a63facc BC |
2957 | |
2958 | switch (vif->type) { | |
2959 | case NL80211_IFTYPE_AP: | |
2960 | case NL80211_IFTYPE_STATION: | |
2961 | case NL80211_IFTYPE_ADHOC: | |
2962 | case NL80211_IFTYPE_MESH_POINT: | |
b1ae1edf | 2963 | avf->opmode = vif->type; |
8a63facc BC |
2964 | break; |
2965 | default: | |
2966 | ret = -EOPNOTSUPP; | |
2967 | goto end; | |
2968 | } | |
2969 | ||
b1ae1edf BG |
2970 | sc->nvifs++; |
2971 | ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", avf->opmode); | |
8a63facc | 2972 | |
b1ae1edf BG |
2973 | /* Assign the vap/adhoc to a beacon xmit slot. */ |
2974 | if ((avf->opmode == NL80211_IFTYPE_AP) || | |
2975 | (avf->opmode == NL80211_IFTYPE_ADHOC)) { | |
2976 | int slot; | |
2977 | ||
2978 | WARN_ON(list_empty(&sc->bcbuf)); | |
2979 | avf->bbuf = list_first_entry(&sc->bcbuf, struct ath5k_buf, | |
2980 | list); | |
2981 | list_del(&avf->bbuf->list); | |
2982 | ||
2983 | avf->bslot = 0; | |
2984 | for (slot = 0; slot < ATH_BCBUF; slot++) { | |
2985 | if (!sc->bslot[slot]) { | |
2986 | avf->bslot = slot; | |
2987 | break; | |
2988 | } | |
2989 | } | |
2990 | BUG_ON(sc->bslot[avf->bslot] != NULL); | |
2991 | sc->bslot[avf->bslot] = vif; | |
2992 | if (avf->opmode == NL80211_IFTYPE_AP) | |
2993 | sc->num_ap_vifs++; | |
2994 | else | |
2995 | sc->num_adhoc_vifs++; | |
2996 | } | |
2997 | ||
b1ae1edf BG |
2998 | /* Any MAC address is fine, all others are included through the |
2999 | * filter. | |
3000 | */ | |
3001 | memcpy(&sc->lladdr, vif->addr, ETH_ALEN); | |
8a63facc | 3002 | ath5k_hw_set_lladdr(sc->ah, vif->addr); |
b1ae1edf BG |
3003 | |
3004 | memcpy(&avf->lladdr, vif->addr, ETH_ALEN); | |
3005 | ||
3006 | ath5k_mode_setup(sc, vif); | |
8a63facc BC |
3007 | |
3008 | ret = 0; | |
3009 | end: | |
3010 | mutex_unlock(&sc->lock); | |
3011 | return ret; | |
3012 | } | |
3013 | ||
3014 | static void | |
3015 | ath5k_remove_interface(struct ieee80211_hw *hw, | |
3016 | struct ieee80211_vif *vif) | |
3017 | { | |
3018 | struct ath5k_softc *sc = hw->priv; | |
b1ae1edf BG |
3019 | struct ath5k_vif *avf = (void *)vif->drv_priv; |
3020 | unsigned int i; | |
8a63facc BC |
3021 | |
3022 | mutex_lock(&sc->lock); | |
b1ae1edf BG |
3023 | sc->nvifs--; |
3024 | ||
3025 | if (avf->bbuf) { | |
3026 | ath5k_txbuf_free_skb(sc, avf->bbuf); | |
3027 | list_add_tail(&avf->bbuf->list, &sc->bcbuf); | |
3028 | for (i = 0; i < ATH_BCBUF; i++) { | |
3029 | if (sc->bslot[i] == vif) { | |
3030 | sc->bslot[i] = NULL; | |
3031 | break; | |
3032 | } | |
3033 | } | |
3034 | avf->bbuf = NULL; | |
3035 | } | |
3036 | if (avf->opmode == NL80211_IFTYPE_AP) | |
3037 | sc->num_ap_vifs--; | |
3038 | else if (avf->opmode == NL80211_IFTYPE_ADHOC) | |
3039 | sc->num_adhoc_vifs--; | |
8a63facc | 3040 | |
62c58fb4 | 3041 | ath5k_update_bssid_mask_and_opmode(sc, NULL); |
8a63facc BC |
3042 | mutex_unlock(&sc->lock); |
3043 | } | |
3044 | ||
3045 | /* | |
3046 | * TODO: Phy disable/diversity etc | |
3047 | */ | |
3048 | static int | |
3049 | ath5k_config(struct ieee80211_hw *hw, u32 changed) | |
3050 | { | |
3051 | struct ath5k_softc *sc = hw->priv; | |
3052 | struct ath5k_hw *ah = sc->ah; | |
3053 | struct ieee80211_conf *conf = &hw->conf; | |
3054 | int ret = 0; | |
3055 | ||
3056 | mutex_lock(&sc->lock); | |
3057 | ||
3058 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { | |
3059 | ret = ath5k_chan_set(sc, conf->channel); | |
3060 | if (ret < 0) | |
3061 | goto unlock; | |
3062 | } | |
3063 | ||
3064 | if ((changed & IEEE80211_CONF_CHANGE_POWER) && | |
3065 | (sc->power_level != conf->power_level)) { | |
a0823810 NK |
3066 | sc->power_level = conf->power_level; |
3067 | ||
3068 | /* Half dB steps */ | |
3069 | ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2)); | |
3070 | } | |
fa1c114f | 3071 | |
2bed03eb NK |
3072 | /* TODO: |
3073 | * 1) Move this on config_interface and handle each case | |
3074 | * separately eg. when we have only one STA vif, use | |
3075 | * AR5K_ANTMODE_SINGLE_AP | |
3076 | * | |
3077 | * 2) Allow the user to change antenna mode eg. when only | |
3078 | * one antenna is present | |
3079 | * | |
3080 | * 3) Allow the user to set default/tx antenna when possible | |
3081 | * | |
3082 | * 4) Default mode should handle 90% of the cases, together | |
3083 | * with fixed a/b and single AP modes we should be able to | |
3084 | * handle 99%. Sectored modes are extreme cases and i still | |
3085 | * haven't found a usage for them. If we decide to support them, | |
3086 | * then we must allow the user to set how many tx antennas we | |
3087 | * have available | |
3088 | */ | |
caec9112 | 3089 | ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode); |
be009370 | 3090 | |
55aa4e0f | 3091 | unlock: |
be009370 | 3092 | mutex_unlock(&sc->lock); |
55aa4e0f | 3093 | return ret; |
fa1c114f JS |
3094 | } |
3095 | ||
3ac64bee | 3096 | static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw, |
22bedad3 | 3097 | struct netdev_hw_addr_list *mc_list) |
3ac64bee JB |
3098 | { |
3099 | u32 mfilt[2], val; | |
3ac64bee | 3100 | u8 pos; |
22bedad3 | 3101 | struct netdev_hw_addr *ha; |
3ac64bee JB |
3102 | |
3103 | mfilt[0] = 0; | |
3104 | mfilt[1] = 1; | |
3105 | ||
22bedad3 | 3106 | netdev_hw_addr_list_for_each(ha, mc_list) { |
3ac64bee | 3107 | /* calculate XOR of eight 6-bit values */ |
22bedad3 | 3108 | val = get_unaligned_le32(ha->addr + 0); |
3ac64bee | 3109 | pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; |
22bedad3 | 3110 | val = get_unaligned_le32(ha->addr + 3); |
3ac64bee JB |
3111 | pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; |
3112 | pos &= 0x3f; | |
3113 | mfilt[pos / 32] |= (1 << (pos % 32)); | |
3114 | /* XXX: we might be able to just do this instead, | |
3115 | * but not sure, needs testing, if we do use this we'd | |
3116 | * neet to inform below to not reset the mcast */ | |
3117 | /* ath5k_hw_set_mcast_filterindex(ah, | |
22bedad3 | 3118 | * ha->addr[5]); */ |
3ac64bee JB |
3119 | } |
3120 | ||
3121 | return ((u64)(mfilt[1]) << 32) | mfilt[0]; | |
3122 | } | |
3123 | ||
b1ae1edf BG |
3124 | static bool ath_any_vif_assoc(struct ath5k_softc *sc) |
3125 | { | |
3126 | struct ath_vif_iter_data iter_data; | |
3127 | iter_data.hw_macaddr = NULL; | |
3128 | iter_data.any_assoc = false; | |
3129 | iter_data.need_set_hw_addr = false; | |
3130 | iter_data.found_active = true; | |
3131 | ||
3132 | ieee80211_iterate_active_interfaces_atomic(sc->hw, ath_vif_iter, | |
3133 | &iter_data); | |
3134 | return iter_data.any_assoc; | |
3135 | } | |
3136 | ||
fa1c114f JS |
3137 | #define SUPPORTED_FIF_FLAGS \ |
3138 | FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \ | |
3139 | FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \ | |
3140 | FIF_BCN_PRBRESP_PROMISC | |
3141 | /* | |
3142 | * o always accept unicast, broadcast, and multicast traffic | |
3143 | * o multicast traffic for all BSSIDs will be enabled if mac80211 | |
3144 | * says it should be | |
3145 | * o maintain current state of phy ofdm or phy cck error reception. | |
3146 | * If the hardware detects any of these type of errors then | |
3147 | * ath5k_hw_get_rx_filter() will pass to us the respective | |
3148 | * hardware filters to be able to receive these type of frames. | |
3149 | * o probe request frames are accepted only when operating in | |
3150 | * hostap, adhoc, or monitor modes | |
3151 | * o enable promiscuous mode according to the interface state | |
3152 | * o accept beacons: | |
3153 | * - when operating in adhoc mode so the 802.11 layer creates | |
3154 | * node table entries for peers, | |
3155 | * - when operating in station mode for collecting rssi data when | |
3156 | * the station is otherwise quiet, or | |
3157 | * - when scanning | |
3158 | */ | |
3159 | static void ath5k_configure_filter(struct ieee80211_hw *hw, | |
3160 | unsigned int changed_flags, | |
3161 | unsigned int *new_flags, | |
3ac64bee | 3162 | u64 multicast) |
fa1c114f JS |
3163 | { |
3164 | struct ath5k_softc *sc = hw->priv; | |
3165 | struct ath5k_hw *ah = sc->ah; | |
3ac64bee | 3166 | u32 mfilt[2], rfilt; |
fa1c114f | 3167 | |
56d1de0a BC |
3168 | mutex_lock(&sc->lock); |
3169 | ||
3ac64bee JB |
3170 | mfilt[0] = multicast; |
3171 | mfilt[1] = multicast >> 32; | |
fa1c114f JS |
3172 | |
3173 | /* Only deal with supported flags */ | |
3174 | changed_flags &= SUPPORTED_FIF_FLAGS; | |
3175 | *new_flags &= SUPPORTED_FIF_FLAGS; | |
3176 | ||
3177 | /* If HW detects any phy or radar errors, leave those filters on. | |
3178 | * Also, always enable Unicast, Broadcasts and Multicast | |
3179 | * XXX: move unicast, bssid broadcasts and multicast to mac80211 */ | |
3180 | rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) | | |
3181 | (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST | | |
3182 | AR5K_RX_FILTER_MCAST); | |
3183 | ||
3184 | if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) { | |
3185 | if (*new_flags & FIF_PROMISC_IN_BSS) { | |
fa1c114f | 3186 | __set_bit(ATH_STAT_PROMISC, sc->status); |
0bbac08f | 3187 | } else { |
fa1c114f | 3188 | __clear_bit(ATH_STAT_PROMISC, sc->status); |
0bbac08f | 3189 | } |
fa1c114f JS |
3190 | } |
3191 | ||
6b5dcccb BC |
3192 | if (test_bit(ATH_STAT_PROMISC, sc->status)) |
3193 | rfilt |= AR5K_RX_FILTER_PROM; | |
3194 | ||
fa1c114f JS |
3195 | /* Note, AR5K_RX_FILTER_MCAST is already enabled */ |
3196 | if (*new_flags & FIF_ALLMULTI) { | |
3197 | mfilt[0] = ~0; | |
3198 | mfilt[1] = ~0; | |
fa1c114f JS |
3199 | } |
3200 | ||
3201 | /* This is the best we can do */ | |
3202 | if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL)) | |
3203 | rfilt |= AR5K_RX_FILTER_PHYERR; | |
3204 | ||
3205 | /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons | |
30bf4169 | 3206 | * and probes for any BSSID */ |
b1ae1edf | 3207 | if ((*new_flags & FIF_BCN_PRBRESP_PROMISC) || (sc->nvifs > 1)) |
30bf4169 | 3208 | rfilt |= AR5K_RX_FILTER_BEACON; |
fa1c114f JS |
3209 | |
3210 | /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not | |
3211 | * set we should only pass on control frames for this | |
3212 | * station. This needs testing. I believe right now this | |
3213 | * enables *all* control frames, which is OK.. but | |
3214 | * but we should see if we can improve on granularity */ | |
3215 | if (*new_flags & FIF_CONTROL) | |
3216 | rfilt |= AR5K_RX_FILTER_CONTROL; | |
3217 | ||
3218 | /* Additional settings per mode -- this is per ath5k */ | |
3219 | ||
3220 | /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */ | |
3221 | ||
56d1de0a BC |
3222 | switch (sc->opmode) { |
3223 | case NL80211_IFTYPE_MESH_POINT: | |
56d1de0a BC |
3224 | rfilt |= AR5K_RX_FILTER_CONTROL | |
3225 | AR5K_RX_FILTER_BEACON | | |
3226 | AR5K_RX_FILTER_PROBEREQ | | |
3227 | AR5K_RX_FILTER_PROM; | |
3228 | break; | |
3229 | case NL80211_IFTYPE_AP: | |
3230 | case NL80211_IFTYPE_ADHOC: | |
3231 | rfilt |= AR5K_RX_FILTER_PROBEREQ | | |
3232 | AR5K_RX_FILTER_BEACON; | |
3233 | break; | |
3234 | case NL80211_IFTYPE_STATION: | |
3235 | if (sc->assoc) | |
3236 | rfilt |= AR5K_RX_FILTER_BEACON; | |
3237 | default: | |
3238 | break; | |
3239 | } | |
fa1c114f JS |
3240 | |
3241 | /* Set filters */ | |
0bbac08f | 3242 | ath5k_hw_set_rx_filter(ah, rfilt); |
fa1c114f JS |
3243 | |
3244 | /* Set multicast bits */ | |
3245 | ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]); | |
a180a130 | 3246 | /* Set the cached hw filter flags, this will later actually |
fa1c114f JS |
3247 | * be set in HW */ |
3248 | sc->filter_flags = rfilt; | |
56d1de0a BC |
3249 | |
3250 | mutex_unlock(&sc->lock); | |
fa1c114f JS |
3251 | } |
3252 | ||
3253 | static int | |
3254 | ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, | |
dc822b5d JB |
3255 | struct ieee80211_vif *vif, struct ieee80211_sta *sta, |
3256 | struct ieee80211_key_conf *key) | |
fa1c114f JS |
3257 | { |
3258 | struct ath5k_softc *sc = hw->priv; | |
dc1e001b LR |
3259 | struct ath5k_hw *ah = sc->ah; |
3260 | struct ath_common *common = ath5k_hw_common(ah); | |
fa1c114f JS |
3261 | int ret = 0; |
3262 | ||
9ad9a26e BC |
3263 | if (modparam_nohwcrypt) |
3264 | return -EOPNOTSUPP; | |
3265 | ||
97359d12 JB |
3266 | switch (key->cipher) { |
3267 | case WLAN_CIPHER_SUITE_WEP40: | |
3268 | case WLAN_CIPHER_SUITE_WEP104: | |
3269 | case WLAN_CIPHER_SUITE_TKIP: | |
3f64b435 | 3270 | break; |
97359d12 | 3271 | case WLAN_CIPHER_SUITE_CCMP: |
781f3136 | 3272 | if (common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM) |
1c818740 | 3273 | break; |
fa1c114f JS |
3274 | return -EOPNOTSUPP; |
3275 | default: | |
3276 | WARN_ON(1); | |
3277 | return -EINVAL; | |
3278 | } | |
3279 | ||
3280 | mutex_lock(&sc->lock); | |
3281 | ||
3282 | switch (cmd) { | |
3283 | case SET_KEY: | |
e0f8c2a9 BR |
3284 | ret = ath_key_config(common, vif, sta, key); |
3285 | if (ret >= 0) { | |
3286 | key->hw_key_idx = ret; | |
3287 | /* push IV and Michael MIC generation to stack */ | |
3288 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
3289 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) | |
3290 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; | |
3291 | if (key->cipher == WLAN_CIPHER_SUITE_CCMP) | |
3292 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; | |
3293 | ret = 0; | |
fa1c114f | 3294 | } |
fa1c114f JS |
3295 | break; |
3296 | case DISABLE_KEY: | |
e0f8c2a9 | 3297 | ath_key_delete(common, key); |
fa1c114f JS |
3298 | break; |
3299 | default: | |
3300 | ret = -EINVAL; | |
fa1c114f JS |
3301 | } |
3302 | ||
8a63facc BC |
3303 | mmiowb(); |
3304 | mutex_unlock(&sc->lock); | |
3305 | return ret; | |
3306 | } | |
3307 | ||
3308 | static int | |
3309 | ath5k_get_stats(struct ieee80211_hw *hw, | |
3310 | struct ieee80211_low_level_stats *stats) | |
3311 | { | |
3312 | struct ath5k_softc *sc = hw->priv; | |
3313 | ||
3314 | /* Force update */ | |
3315 | ath5k_hw_update_mib_counters(sc->ah); | |
3316 | ||
3317 | stats->dot11ACKFailureCount = sc->stats.ack_fail; | |
3318 | stats->dot11RTSFailureCount = sc->stats.rts_fail; | |
3319 | stats->dot11RTSSuccessCount = sc->stats.rts_ok; | |
3320 | stats->dot11FCSErrorCount = sc->stats.fcs_error; | |
3321 | ||
3322 | return 0; | |
3323 | } | |
3324 | ||
3325 | static int ath5k_get_survey(struct ieee80211_hw *hw, int idx, | |
3326 | struct survey_info *survey) | |
3327 | { | |
3328 | struct ath5k_softc *sc = hw->priv; | |
3329 | struct ieee80211_conf *conf = &hw->conf; | |
edb40a23 BR |
3330 | struct ath_common *common = ath5k_hw_common(sc->ah); |
3331 | struct ath_cycle_counters *cc = &common->cc_survey; | |
3332 | unsigned int div = common->clockrate * 1000; | |
8a63facc | 3333 | |
edb40a23 | 3334 | if (idx != 0) |
8a63facc BC |
3335 | return -ENOENT; |
3336 | ||
3337 | survey->channel = conf->channel; | |
3338 | survey->filled = SURVEY_INFO_NOISE_DBM; | |
3339 | survey->noise = sc->ah->ah_noise_floor; | |
3340 | ||
edb40a23 BR |
3341 | spin_lock_bh(&common->cc_lock); |
3342 | ath_hw_cycle_counters_update(common); | |
3343 | if (cc->cycles > 0) { | |
3344 | survey->filled |= SURVEY_INFO_CHANNEL_TIME | | |
3345 | SURVEY_INFO_CHANNEL_TIME_BUSY | | |
3346 | SURVEY_INFO_CHANNEL_TIME_RX | | |
3347 | SURVEY_INFO_CHANNEL_TIME_TX; | |
3348 | survey->channel_time += cc->cycles / div; | |
3349 | survey->channel_time_busy += cc->rx_busy / div; | |
3350 | survey->channel_time_rx += cc->rx_frame / div; | |
3351 | survey->channel_time_tx += cc->tx_frame / div; | |
3352 | } | |
3353 | memset(cc, 0, sizeof(*cc)); | |
3354 | spin_unlock_bh(&common->cc_lock); | |
3355 | ||
8a63facc BC |
3356 | return 0; |
3357 | } | |
3358 | ||
3359 | static u64 | |
3360 | ath5k_get_tsf(struct ieee80211_hw *hw) | |
3361 | { | |
3362 | struct ath5k_softc *sc = hw->priv; | |
3363 | ||
3364 | return ath5k_hw_get_tsf64(sc->ah); | |
3365 | } | |
3366 | ||
3367 | static void | |
3368 | ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf) | |
3369 | { | |
3370 | struct ath5k_softc *sc = hw->priv; | |
3371 | ||
3372 | ath5k_hw_set_tsf64(sc->ah, tsf); | |
3373 | } | |
3374 | ||
3375 | static void | |
3376 | ath5k_reset_tsf(struct ieee80211_hw *hw) | |
3377 | { | |
3378 | struct ath5k_softc *sc = hw->priv; | |
3379 | ||
3380 | /* | |
3381 | * in IBSS mode we need to update the beacon timers too. | |
3382 | * this will also reset the TSF if we call it with 0 | |
3383 | */ | |
3384 | if (sc->opmode == NL80211_IFTYPE_ADHOC) | |
3385 | ath5k_beacon_update_timers(sc, 0); | |
3386 | else | |
3387 | ath5k_hw_reset_tsf(sc->ah); | |
3388 | } | |
3389 | ||
3390 | static void | |
3391 | set_beacon_filter(struct ieee80211_hw *hw, bool enable) | |
3392 | { | |
3393 | struct ath5k_softc *sc = hw->priv; | |
3394 | struct ath5k_hw *ah = sc->ah; | |
3395 | u32 rfilt; | |
3396 | rfilt = ath5k_hw_get_rx_filter(ah); | |
3397 | if (enable) | |
3398 | rfilt |= AR5K_RX_FILTER_BEACON; | |
3399 | else | |
3400 | rfilt &= ~AR5K_RX_FILTER_BEACON; | |
3401 | ath5k_hw_set_rx_filter(ah, rfilt); | |
3402 | sc->filter_flags = rfilt; | |
3403 | } | |
3404 | ||
3405 | static void ath5k_bss_info_changed(struct ieee80211_hw *hw, | |
3406 | struct ieee80211_vif *vif, | |
3407 | struct ieee80211_bss_conf *bss_conf, | |
3408 | u32 changes) | |
3409 | { | |
b1ae1edf | 3410 | struct ath5k_vif *avf = (void *)vif->drv_priv; |
8a63facc BC |
3411 | struct ath5k_softc *sc = hw->priv; |
3412 | struct ath5k_hw *ah = sc->ah; | |
3413 | struct ath_common *common = ath5k_hw_common(ah); | |
3414 | unsigned long flags; | |
3415 | ||
3416 | mutex_lock(&sc->lock); | |
8a63facc BC |
3417 | |
3418 | if (changes & BSS_CHANGED_BSSID) { | |
3419 | /* Cache for later use during resets */ | |
3420 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | |
3421 | common->curaid = 0; | |
3422 | ath5k_hw_set_bssid(ah); | |
3423 | mmiowb(); | |
3424 | } | |
3425 | ||
3426 | if (changes & BSS_CHANGED_BEACON_INT) | |
3427 | sc->bintval = bss_conf->beacon_int; | |
3428 | ||
3429 | if (changes & BSS_CHANGED_ASSOC) { | |
b1ae1edf BG |
3430 | avf->assoc = bss_conf->assoc; |
3431 | if (bss_conf->assoc) | |
3432 | sc->assoc = bss_conf->assoc; | |
3433 | else | |
3434 | sc->assoc = ath_any_vif_assoc(sc); | |
3435 | ||
8a63facc BC |
3436 | if (sc->opmode == NL80211_IFTYPE_STATION) |
3437 | set_beacon_filter(hw, sc->assoc); | |
3438 | ath5k_hw_set_ledstate(sc->ah, sc->assoc ? | |
3439 | AR5K_LED_ASSOC : AR5K_LED_INIT); | |
3440 | if (bss_conf->assoc) { | |
3441 | ATH5K_DBG(sc, ATH5K_DEBUG_ANY, | |
3442 | "Bss Info ASSOC %d, bssid: %pM\n", | |
3443 | bss_conf->aid, common->curbssid); | |
3444 | common->curaid = bss_conf->aid; | |
3445 | ath5k_hw_set_bssid(ah); | |
3446 | /* Once ANI is available you would start it here */ | |
3447 | } | |
3448 | } | |
3449 | ||
3450 | if (changes & BSS_CHANGED_BEACON) { | |
3451 | spin_lock_irqsave(&sc->block, flags); | |
3452 | ath5k_beacon_update(hw, vif); | |
3453 | spin_unlock_irqrestore(&sc->block, flags); | |
3454 | } | |
3455 | ||
3456 | if (changes & BSS_CHANGED_BEACON_ENABLED) | |
3457 | sc->enable_beacon = bss_conf->enable_beacon; | |
3458 | ||
3459 | if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED | | |
3460 | BSS_CHANGED_BEACON_INT)) | |
3461 | ath5k_beacon_config(sc); | |
3462 | ||
8a63facc BC |
3463 | mutex_unlock(&sc->lock); |
3464 | } | |
3465 | ||
3466 | static void ath5k_sw_scan_start(struct ieee80211_hw *hw) | |
3467 | { | |
3468 | struct ath5k_softc *sc = hw->priv; | |
3469 | if (!sc->assoc) | |
3470 | ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN); | |
3471 | } | |
3472 | ||
3473 | static void ath5k_sw_scan_complete(struct ieee80211_hw *hw) | |
3474 | { | |
3475 | struct ath5k_softc *sc = hw->priv; | |
3476 | ath5k_hw_set_ledstate(sc->ah, sc->assoc ? | |
3477 | AR5K_LED_ASSOC : AR5K_LED_INIT); | |
3478 | } | |
3479 | ||
3480 | /** | |
3481 | * ath5k_set_coverage_class - Set IEEE 802.11 coverage class | |
3482 | * | |
3483 | * @hw: struct ieee80211_hw pointer | |
3484 | * @coverage_class: IEEE 802.11 coverage class number | |
3485 | * | |
3486 | * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given | |
3487 | * coverage class. The values are persistent, they are restored after device | |
3488 | * reset. | |
3489 | */ | |
3490 | static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) | |
3491 | { | |
3492 | struct ath5k_softc *sc = hw->priv; | |
3493 | ||
3494 | mutex_lock(&sc->lock); | |
3495 | ath5k_hw_set_coverage_class(sc->ah, coverage_class); | |
3496 | mutex_unlock(&sc->lock); | |
3497 | } | |
3498 | ||
e0b1cc52 BR |
3499 | static int ath5k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
3500 | const struct ieee80211_tx_queue_params *params) | |
3501 | { | |
3502 | struct ath5k_softc *sc = hw->priv; | |
3503 | struct ath5k_hw *ah = sc->ah; | |
3504 | struct ath5k_txq_info qi; | |
3505 | int ret = 0; | |
3506 | ||
3507 | if (queue >= ah->ah_capabilities.cap_queues.q_tx_num) | |
3508 | return 0; | |
3509 | ||
3510 | mutex_lock(&sc->lock); | |
3511 | ||
3512 | ath5k_hw_get_tx_queueprops(ah, queue, &qi); | |
3513 | ||
3514 | qi.tqi_aifs = params->aifs; | |
3515 | qi.tqi_cw_min = params->cw_min; | |
3516 | qi.tqi_cw_max = params->cw_max; | |
3517 | qi.tqi_burst_time = params->txop; | |
3518 | ||
3519 | ATH5K_DBG(sc, ATH5K_DEBUG_ANY, | |
3520 | "Configure tx [queue %d], " | |
3521 | "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | |
3522 | queue, params->aifs, params->cw_min, | |
3523 | params->cw_max, params->txop); | |
3524 | ||
3525 | if (ath5k_hw_set_tx_queueprops(ah, queue, &qi)) { | |
3526 | ATH5K_ERR(sc, | |
3527 | "Unable to update hardware queue %u!\n", queue); | |
3528 | ret = -EIO; | |
3529 | } else | |
3530 | ath5k_hw_reset_tx_queue(ah, queue); | |
3531 | ||
3532 | mutex_unlock(&sc->lock); | |
3533 | ||
3534 | return ret; | |
3535 | } | |
3536 | ||
72a80110 BR |
3537 | static int ath5k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) |
3538 | { | |
3539 | struct ath5k_softc *sc = hw->priv; | |
3540 | ||
3541 | if (tx_ant == 1 && rx_ant == 1) | |
3542 | ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_A); | |
3543 | else if (tx_ant == 2 && rx_ant == 2) | |
3544 | ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_B); | |
3545 | else if ((tx_ant & 3) == 3 && (rx_ant & 3) == 3) | |
3546 | ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_DEFAULT); | |
3547 | else | |
3548 | return -EINVAL; | |
3549 | return 0; | |
3550 | } | |
3551 | ||
3552 | static int ath5k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) | |
3553 | { | |
3554 | struct ath5k_softc *sc = hw->priv; | |
3555 | ||
3556 | switch (sc->ah->ah_ant_mode) { | |
3557 | case AR5K_ANTMODE_FIXED_A: | |
3558 | *tx_ant = 1; *rx_ant = 1; break; | |
3559 | case AR5K_ANTMODE_FIXED_B: | |
3560 | *tx_ant = 2; *rx_ant = 2; break; | |
3561 | case AR5K_ANTMODE_DEFAULT: | |
3562 | *tx_ant = 3; *rx_ant = 3; break; | |
3563 | } | |
3564 | return 0; | |
3565 | } | |
3566 | ||
132b1c3e | 3567 | const struct ieee80211_ops ath5k_hw_ops = { |
8a63facc BC |
3568 | .tx = ath5k_tx, |
3569 | .start = ath5k_start, | |
3570 | .stop = ath5k_stop, | |
3571 | .add_interface = ath5k_add_interface, | |
3572 | .remove_interface = ath5k_remove_interface, | |
3573 | .config = ath5k_config, | |
3574 | .prepare_multicast = ath5k_prepare_multicast, | |
3575 | .configure_filter = ath5k_configure_filter, | |
3576 | .set_key = ath5k_set_key, | |
3577 | .get_stats = ath5k_get_stats, | |
3578 | .get_survey = ath5k_get_survey, | |
e0b1cc52 | 3579 | .conf_tx = ath5k_conf_tx, |
8a63facc BC |
3580 | .get_tsf = ath5k_get_tsf, |
3581 | .set_tsf = ath5k_set_tsf, | |
3582 | .reset_tsf = ath5k_reset_tsf, | |
3583 | .bss_info_changed = ath5k_bss_info_changed, | |
3584 | .sw_scan_start = ath5k_sw_scan_start, | |
3585 | .sw_scan_complete = ath5k_sw_scan_complete, | |
3586 | .set_coverage_class = ath5k_set_coverage_class, | |
72a80110 BR |
3587 | .set_antenna = ath5k_set_antenna, |
3588 | .get_antenna = ath5k_get_antenna, | |
8a63facc | 3589 | }; |