projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ath5k: merge ath5k_{init, deinit}_hw() with their thin wrappers
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
fa1c114f
JS		 50#include <linux/ethtool.h>
51#include <linux/uaccess.h>
5a0e3ad6 52#include <linux/slab.h>
b1ae1edf 53#include <linux/etherdevice.h>
fa1c114f
JS		 54
55#include <net/ieee80211_radiotap.h>
56
57#include <asm/unaligned.h>
58
59#include "base.h"
60#include "reg.h"
61#include "debug.h"
2111ac0d 62#include "ani.h"
fa1c114f 63
0e472252
BC		 64#define CREATE_TRACE_POINTS
65#include "trace.h"
66
18cb6e32
JL		 67int ath5k_modparam_nohwcrypt;
68module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 69MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 70
42639fcd 71static int modparam_all_channels;
46802a4f 72module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 73MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
74
a99168ee
NK		 75static int modparam_fastchanswitch;
76module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO);
77MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
78
79
fa1c114f
JS		 80/* Module info */
81MODULE_AUTHOR("Jiri Slaby");
82MODULE_AUTHOR("Nick Kossifidis");
83MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
84MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
85MODULE_LICENSE("Dual BSD/GPL");
fa1c114f 86
132b1c3e 87static int ath5k_init(struct ieee80211_hw *hw);
e0d687bd 88static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
8aec7af9 89 bool skip_pcu);
fa1c114f 90
fa1c114f 91/* Known SREVs */
2c91108c 92static const struct ath5k_srev_name srev_names[] = {
a0b907ee
FF		 93#ifdef CONFIG_ATHEROS_AR231X
94 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
95 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
96 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
97 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
98 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
99 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
100 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
101#else
1bef016a
NK		 102 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
103 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
104 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
105 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
106 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
107 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
108 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
109 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
110 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
111 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
112 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
113 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
114 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
115 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
116 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
117 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
118 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
119 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
a0b907ee 120#endif
1bef016a 121 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 122 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
123 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 124 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 125 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
126 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
127 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 128 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 129 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
130 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 131 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
132 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
133 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
1bef016a 134 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f 135 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
a0b907ee
FF		 136#ifdef CONFIG_ATHEROS_AR231X
137 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
138 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
139#endif
fa1c114f
JS		 140 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
141};
142
2c91108c 143static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 144 { .bitrate = 10,
145 .hw_value = ATH5K_RATE_CODE_1M, },
146 { .bitrate = 20,
147 .hw_value = ATH5K_RATE_CODE_2M,
148 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
149 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
150 { .bitrate = 55,
151 .hw_value = ATH5K_RATE_CODE_5_5M,
152 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
153 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
154 { .bitrate = 110,
155 .hw_value = ATH5K_RATE_CODE_11M,
156 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
157 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
158 { .bitrate = 60,
159 .hw_value = ATH5K_RATE_CODE_6M,
160 .flags = 0 },
161 { .bitrate = 90,
162 .hw_value = ATH5K_RATE_CODE_9M,
163 .flags = 0 },
164 { .bitrate = 120,
165 .hw_value = ATH5K_RATE_CODE_12M,
166 .flags = 0 },
167 { .bitrate = 180,
168 .hw_value = ATH5K_RATE_CODE_18M,
169 .flags = 0 },
170 { .bitrate = 240,
171 .hw_value = ATH5K_RATE_CODE_24M,
172 .flags = 0 },
173 { .bitrate = 360,
174 .hw_value = ATH5K_RATE_CODE_36M,
175 .flags = 0 },
176 { .bitrate = 480,
177 .hw_value = ATH5K_RATE_CODE_48M,
178 .flags = 0 },
179 { .bitrate = 540,
180 .hw_value = ATH5K_RATE_CODE_54M,
181 .flags = 0 },
182 /* XR missing */
183};
184
fa1c114f
JS		 185static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
186{
187 u64 tsf = ath5k_hw_get_tsf64(ah);
188
189 if ((tsf & 0x7fff) < rstamp)
190 tsf -= 0x8000;
191
192 return (tsf & ~0x7fff) | rstamp;
193}
194
e5b046d8 195const char *
fa1c114f
JS		 196ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
197{
198 const char *name = "xxxxx";
199 unsigned int i;
200
201 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
202 if (srev_names[i].sr_type != type)
203 continue;
75d0edb8
NK		 204
205 if ((val & 0xf0) == srev_names[i].sr_val)
206 name = srev_names[i].sr_name;
207
208 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 209 name = srev_names[i].sr_name;
210 break;
211 }
212 }
213
214 return name;
215}
e5aa8474
LR		 216static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
217{
218 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
219 return ath5k_hw_reg_read(ah, reg_offset);
220}
221
222static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
223{
224 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
225 ath5k_hw_reg_write(ah, val, reg_offset);
226}
227
228static const struct ath_ops ath5k_common_ops = {
229 .read = ath5k_ioread32,
230 .write = ath5k_iowrite32,
231};
fa1c114f 232
8a63facc
BC		 233/***********************\
234* Driver Initialization *
235\***********************/
236
237static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
fa1c114f 238{
8a63facc 239 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
e0d687bd
PR		 240 struct ath5k_hw *ah = hw->priv;
241 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
fa1c114f 242
8a63facc
BC		 243 return ath_reg_notifier_apply(wiphy, request, regulatory);
244}
6ccf15a1 245
8a63facc
BC		 246/********************\
247* Channel/mode setup *
248\********************/
fa1c114f 249
8a63facc
BC		 250/*
251 * Returns true for the channel numbers used without all_channels modparam.
252 */
410e6120 253static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
8a63facc 254{
410e6120
BR		 255 if (band == IEEE80211_BAND_2GHZ && chan <= 14)
256 return true;
257
258 return /* UNII 1,2 */
259 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
8a63facc
BC		 260 /* midband */
261 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
262 /* UNII-3 */
410e6120
BR		 263 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
264 /* 802.11j 5.030-5.080 GHz (20MHz) */
265 (chan == 8 || chan == 12 || chan == 16) ||
266 /* 802.11j 4.9GHz (20MHz) */
267 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
8a63facc 268}
fa1c114f 269
8a63facc 270static unsigned int
97d9c3a3
BR		 271ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
272 unsigned int mode, unsigned int max)
8a63facc 273{
2b1351a3 274 unsigned int count, size, chfreq, freq, ch;
90c02d72 275 enum ieee80211_band band;
fa1c114f 276
8a63facc
BC		 277 switch (mode) {
278 case AR5K_MODE_11A:
8a63facc 279 /* 1..220, but 2GHz frequencies are filtered by check_channel */
97d9c3a3 280 size = 220;
8a63facc 281 chfreq = CHANNEL_5GHZ;
90c02d72 282 band = IEEE80211_BAND_5GHZ;
8a63facc
BC		 283 break;
284 case AR5K_MODE_11B:
285 case AR5K_MODE_11G:
8a63facc
BC		 286 size = 26;
287 chfreq = CHANNEL_2GHZ;
90c02d72 288 band = IEEE80211_BAND_2GHZ;
8a63facc
BC		 289 break;
290 default:
e0d687bd 291 ATH5K_WARN(ah, "bad mode, not copying channels\n");
8a63facc 292 return 0;
fa1c114f
JS		 293 }
294
2b1351a3
BR		 295 count = 0;
296 for (ch = 1; ch <= size && count < max; ch++) {
90c02d72
BR		 297 freq = ieee80211_channel_to_frequency(ch, band);
298
299 if (freq == 0) /* mapping failed - not a standard channel */
300 continue;
fa1c114f 301
8a63facc
BC		 302 /* Check if channel is supported by the chipset */
303 if (!ath5k_channel_ok(ah, freq, chfreq))
304 continue;
f59ac048 305
410e6120
BR		 306 if (!modparam_all_channels &&
307 !ath5k_is_standard_channel(ch, band))
8a63facc 308 continue;
f59ac048 309
8a63facc
BC		 310 /* Write channel info and increment counter */
311 channels[count].center_freq = freq;
90c02d72 312 channels[count].band = band;
8a63facc
BC		 313 switch (mode) {
314 case AR5K_MODE_11A:
315 case AR5K_MODE_11G:
316 channels[count].hw_value = chfreq | CHANNEL_OFDM;
317 break;
8a63facc
BC		 318 case AR5K_MODE_11B:
319 channels[count].hw_value = CHANNEL_B;
320 }
fa1c114f 321
8a63facc 322 count++;
8a63facc 323 }
fa1c114f 324
8a63facc
BC		 325 return count;
326}
fa1c114f 327
8a63facc 328static void
e0d687bd 329ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b)
8a63facc
BC		 330{
331 u8 i;
fa1c114f 332
8a63facc 333 for (i = 0; i < AR5K_MAX_RATES; i++)
e0d687bd 334 ah->rate_idx[b->band][i] = -1;
fa1c114f 335
8a63facc 336 for (i = 0; i < b->n_bitrates; i++) {
e0d687bd 337 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i;
8a63facc 338 if (b->bitrates[i].hw_value_short)
e0d687bd 339 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
fa1c114f 340 }
8a63facc 341}
fa1c114f 342
8a63facc
BC		 343static int
344ath5k_setup_bands(struct ieee80211_hw *hw)
345{
e0d687bd 346 struct ath5k_hw *ah = hw->priv;
8a63facc
BC		 347 struct ieee80211_supported_band *sband;
348 int max_c, count_c = 0;
349 int i;
fa1c114f 350
e0d687bd
PR		 351 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS);
352 max_c = ARRAY_SIZE(ah->channels);
db719718 353
8a63facc 354 /* 2GHz band */
e0d687bd 355 sband = &ah->sbands[IEEE80211_BAND_2GHZ];
8a63facc 356 sband->band = IEEE80211_BAND_2GHZ;
e0d687bd 357 sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0];
9adca126 358
e0d687bd 359 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) {
8a63facc
BC		 360 /* G mode */
361 memcpy(sband->bitrates, &ath5k_rates[0],
362 sizeof(struct ieee80211_rate) * 12);
363 sband->n_bitrates = 12;
2f7fe870 364
e0d687bd 365 sband->channels = ah->channels;
08105690 366 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 367 AR5K_MODE_11G, max_c);
fa1c114f 368
8a63facc
BC		 369 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
370 count_c = sband->n_channels;
371 max_c -= count_c;
e0d687bd 372 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) {
8a63facc
BC		 373 /* B mode */
374 memcpy(sband->bitrates, &ath5k_rates[0],
375 sizeof(struct ieee80211_rate) * 4);
376 sband->n_bitrates = 4;
fa1c114f 377
8a63facc
BC		 378 /* 5211 only supports B rates and uses 4bit rate codes
379 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
380 * fix them up here:
381 */
382 if (ah->ah_version == AR5K_AR5211) {
383 for (i = 0; i < 4; i++) {
384 sband->bitrates[i].hw_value =
385 sband->bitrates[i].hw_value & 0xF;
386 sband->bitrates[i].hw_value_short =
387 sband->bitrates[i].hw_value_short & 0xF;
fa1c114f
JS		 388 }
389 }
fa1c114f 390
e0d687bd 391 sband->channels = ah->channels;
08105690 392 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 393 AR5K_MODE_11B, max_c);
fa1c114f 394
8a63facc
BC		 395 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
396 count_c = sband->n_channels;
397 max_c -= count_c;
398 }
e0d687bd 399 ath5k_setup_rate_idx(ah, sband);
fa1c114f 400
8a63facc 401 /* 5GHz band, A mode */
e0d687bd
PR		 402 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
403 sband = &ah->sbands[IEEE80211_BAND_5GHZ];
8a63facc 404 sband->band = IEEE80211_BAND_5GHZ;
e0d687bd 405 sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 406
8a63facc
BC		 407 memcpy(sband->bitrates, &ath5k_rates[4],
408 sizeof(struct ieee80211_rate) * 8);
409 sband->n_bitrates = 8;
fa1c114f 410
e0d687bd 411 sband->channels = &ah->channels[count_c];
08105690 412 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 413 AR5K_MODE_11A, max_c);
fa1c114f 414
8a63facc
BC		 415 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
416 }
e0d687bd 417 ath5k_setup_rate_idx(ah, sband);
8a63facc 418
e0d687bd 419 ath5k_debug_dump_bands(ah);
fa1c114f 420
fa1c114f
JS		 421 return 0;
422}
423
8a63facc
BC		 424/*
425 * Set/change channels. We always reset the chip.
426 * To accomplish this we must first cleanup any pending DMA,
427 * then restart stuff after a la ath5k_init.
428 *
e0d687bd 429 * Called with ah->lock.
8a63facc 430 */
cd2c5486 431int
e0d687bd 432ath5k_chan_set(struct ath5k_hw *ah, struct ieee80211_channel *chan)
8a63facc 433{
e0d687bd 434 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
8a63facc 435 "channel set, resetting (%u -> %u MHz)\n",
e0d687bd 436 ah->curchan->center_freq, chan->center_freq);
8a63facc 437
8451d22d 438 /*
8a63facc
BC		 439 * To switch channels clear any pending DMA operations;
440 * wait long enough for the RX fifo to drain, reset the
441 * hardware at the new frequency, and then re-enable
442 * the relevant bits of the h/w.
8451d22d 443 */
e0d687bd 444 return ath5k_reset(ah, chan, true);
fa1c114f 445}
fa1c114f 446
e4b0b32a 447void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
b1ae1edf 448{
e4b0b32a 449 struct ath5k_vif_iter_data *iter_data = data;
b1ae1edf 450 int i;
62c58fb4 451 struct ath5k_vif *avf = (void *)vif->drv_priv;
b1ae1edf
BG		 452
453 if (iter_data->hw_macaddr)
454 for (i = 0; i < ETH_ALEN; i++)
455 iter_data->mask[i] &=
456 ~(iter_data->hw_macaddr[i] ^ mac[i]);
457
458 if (!iter_data->found_active) {
459 iter_data->found_active = true;
460 memcpy(iter_data->active_mac, mac, ETH_ALEN);
461 }
462
463 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
464 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
465 iter_data->need_set_hw_addr = false;
466
467 if (!iter_data->any_assoc) {
b1ae1edf
BG		 468 if (avf->assoc)
469 iter_data->any_assoc = true;
470 }
62c58fb4
BG		 471
472 /* Calculate combined mode - when APs are active, operate in AP mode.
473 * Otherwise use the mode of the new interface. This can currently
474 * only deal with combinations of APs and STAs. Only one ad-hoc
7afbb2f0 475 * interfaces is allowed.
62c58fb4
BG		 476 */
477 if (avf->opmode == NL80211_IFTYPE_AP)
478 iter_data->opmode = NL80211_IFTYPE_AP;
e4b0b32a
BG		 479 else {
480 if (avf->opmode == NL80211_IFTYPE_STATION)
481 iter_data->n_stas++;
62c58fb4
BG		 482 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
483 iter_data->opmode = avf->opmode;
e4b0b32a 484 }
b1ae1edf
BG		 485}
486
cd2c5486 487void
e0d687bd 488ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
cd2c5486 489 struct ieee80211_vif *vif)
b1ae1edf 490{
e0d687bd 491 struct ath_common *common = ath5k_hw_common(ah);
e4b0b32a
BG		 492 struct ath5k_vif_iter_data iter_data;
493 u32 rfilt;
b1ae1edf
BG		 494
495 /*
496 * Use the hardware MAC address as reference, the hardware uses it
497 * together with the BSSID mask when matching addresses.
498 */
499 iter_data.hw_macaddr = common->macaddr;
500 memset(&iter_data.mask, 0xff, ETH_ALEN);
501 iter_data.found_active = false;
502 iter_data.need_set_hw_addr = true;
62c58fb4 503 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
e4b0b32a 504 iter_data.n_stas = 0;
b1ae1edf
BG		 505
506 if (vif)
e4b0b32a 507 ath5k_vif_iter(&iter_data, vif->addr, vif);
b1ae1edf
BG		 508
509 /* Get list of all active MAC addresses */
e0d687bd 510 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
b1ae1edf 511 &iter_data);
e0d687bd 512 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN);
b1ae1edf 513
e0d687bd
PR		 514 ah->opmode = iter_data.opmode;
515 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED)
62c58fb4 516 /* Nothing active, default to station mode */
e0d687bd 517 ah->opmode = NL80211_IFTYPE_STATION;
62c58fb4 518
e0d687bd
PR		 519 ath5k_hw_set_opmode(ah, ah->opmode);
520 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
521 ah->opmode, ath_opmode_to_string(ah->opmode));
62c58fb4 522
b1ae1edf 523 if (iter_data.need_set_hw_addr && iter_data.found_active)
e0d687bd 524 ath5k_hw_set_lladdr(ah, iter_data.active_mac);
b1ae1edf 525
e0d687bd
PR		 526 if (ath5k_hw_hasbssidmask(ah))
527 ath5k_hw_set_bssid_mask(ah, ah->bssidmask);
b1ae1edf 528
e4b0b32a
BG		 529 /* Set up RX Filter */
530 if (iter_data.n_stas > 1) {
531 /* If you have multiple STA interfaces connected to
532 * different APs, ARPs are not received (most of the time?)
6a2a0e73 533 * Enabling PROMISC appears to fix that problem.
e4b0b32a 534 */
e0d687bd 535 ah->filter_flags |= AR5K_RX_FILTER_PROM;
e4b0b32a 536 }
fa1c114f 537
e0d687bd
PR		 538 rfilt = ah->filter_flags;
539 ath5k_hw_set_rx_filter(ah, rfilt);
540 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
8a63facc 541}
fa1c114f 542
8a63facc 543static inline int
e0d687bd 544ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix)
8a63facc
BC		 545{
546 int rix;
fa1c114f 547
8a63facc
BC		 548 /* return base rate on errors */
549 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
550 "hw_rix out of bounds: %x\n", hw_rix))
551 return 0;
552
e0d687bd 553 rix = ah->rate_idx[ah->curchan->band][hw_rix];
8a63facc
BC		 554 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
555 rix = 0;
556
557 return rix;
558}
559
560/***************\
561* Buffers setup *
562\***************/
563
564static
e0d687bd 565struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr)
8a63facc 566{
e0d687bd 567 struct ath_common *common = ath5k_hw_common(ah);
8a63facc 568 struct sk_buff *skb;
fa1c114f
JS		 569
570 /*
8a63facc
BC		 571 * Allocate buffer with headroom_needed space for the
572 * fake physical layer header at the start.
fa1c114f 573 */
8a63facc
BC		 574 skb = ath_rxbuf_alloc(common,
575 common->rx_bufsize,
576 GFP_ATOMIC);
fa1c114f 577
8a63facc 578 if (!skb) {
e0d687bd 579 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n",
8a63facc
BC		 580 common->rx_bufsize);
581 return NULL;
fa1c114f
JS		 582 }
583
e0d687bd 584 *skb_addr = dma_map_single(ah->dev,
8a63facc 585 skb->data, common->rx_bufsize,
aeae4ac9
FF		 586 DMA_FROM_DEVICE);
587
e0d687bd
PR		 588 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) {
589 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__);
8a63facc
BC		 590 dev_kfree_skb(skb);
591 return NULL;
0e149cf5 592 }
8a63facc
BC		 593 return skb;
594}
0e149cf5 595
8a63facc 596static int
e0d687bd 597ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
8a63facc 598{
8a63facc
BC		 599 struct sk_buff *skb = bf->skb;
600 struct ath5k_desc *ds;
601 int ret;
fa1c114f 602
8a63facc 603 if (!skb) {
e0d687bd 604 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr);
8a63facc
BC		 605 if (!skb)
606 return -ENOMEM;
607 bf->skb = skb;
f769c36b
BC		 608 }
609
8a63facc
BC		 610 /*
611 * Setup descriptors. For receive we always terminate
612 * the descriptor list with a self-linked entry so we'll
613 * not get overrun under high load (as can happen with a
614 * 5212 when ANI processing enables PHY error frames).
615 *
616 * To ensure the last descriptor is self-linked we create
617 * each descriptor as self-linked and add it to the end. As
618 * each additional descriptor is added the previous self-linked
619 * entry is "fixed" naturally. This should be safe even
620 * if DMA is happening. When processing RX interrupts we
621 * never remove/process the last, self-linked, entry on the
622 * descriptor list. This ensures the hardware always has
623 * someplace to write a new frame.
624 */
625 ds = bf->desc;
626 ds->ds_link = bf->daddr; /* link to self */
627 ds->ds_data = bf->skbaddr;
628 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
fa1c114f 629 if (ret) {
e0d687bd 630 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__);
8a63facc 631 return ret;
fa1c114f
JS		 632 }
633
e0d687bd
PR		 634 if (ah->rxlink != NULL)
635 *ah->rxlink = bf->daddr;
636 ah->rxlink = &ds->ds_link;
fa1c114f 637 return 0;
fa1c114f
JS		 638}
639
8a63facc 640static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
fa1c114f 641{
8a63facc
BC		 642 struct ieee80211_hdr *hdr;
643 enum ath5k_pkt_type htype;
644 __le16 fc;
fa1c114f 645
8a63facc
BC		 646 hdr = (struct ieee80211_hdr *)skb->data;
647 fc = hdr->frame_control;
fa1c114f 648
8a63facc
BC		 649 if (ieee80211_is_beacon(fc))
650 htype = AR5K_PKT_TYPE_BEACON;
651 else if (ieee80211_is_probe_resp(fc))
652 htype = AR5K_PKT_TYPE_PROBE_RESP;
653 else if (ieee80211_is_atim(fc))
654 htype = AR5K_PKT_TYPE_ATIM;
655 else if (ieee80211_is_pspoll(fc))
656 htype = AR5K_PKT_TYPE_PSPOLL;
fa1c114f 657 else
8a63facc 658 htype = AR5K_PKT_TYPE_NORMAL;
fa1c114f 659
8a63facc 660 return htype;
42639fcd
BC		 661}
662
8a63facc 663static int
e0d687bd 664ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf,
8a63facc 665 struct ath5k_txq *txq, int padsize)
fa1c114f 666{
8a63facc
BC		 667 struct ath5k_desc *ds = bf->desc;
668 struct sk_buff *skb = bf->skb;
669 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
670 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
671 struct ieee80211_rate *rate;
672 unsigned int mrr_rate[3], mrr_tries[3];
673 int i, ret;
674 u16 hw_rate;
675 u16 cts_rate = 0;
676 u16 duration = 0;
677 u8 rc_flags;
fa1c114f 678
8a63facc 679 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
fa1c114f 680
8a63facc 681 /* XXX endianness */
e0d687bd 682 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
aeae4ac9 683 DMA_TO_DEVICE);
fa1c114f 684
e0d687bd 685 rate = ieee80211_get_tx_rate(ah->hw, info);
29ad2fac
JL		 686 if (!rate) {
687 ret = -EINVAL;
688 goto err_unmap;
689 }
fa1c114f 690
8a63facc
BC		 691 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
692 flags |= AR5K_TXDESC_NOACK;
fa1c114f 693
8a63facc
BC		 694 rc_flags = info->control.rates[0].flags;
695 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
696 rate->hw_value_short : rate->hw_value;
42639fcd 697
8a63facc
BC		 698 pktlen = skb->len;
699
700 /* FIXME: If we are in g mode and rate is a CCK rate
701 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
702 * from tx power (value is in dB units already) */
703 if (info->control.hw_key) {
704 keyidx = info->control.hw_key->hw_key_idx;
705 pktlen += info->control.hw_key->icv_len;
706 }
707 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
708 flags |= AR5K_TXDESC_RTSENA;
e0d687bd
PR		 709 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
710 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw,
b1ae1edf 711 info->control.vif, pktlen, info));
8a63facc
BC		 712 }
713 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
714 flags |= AR5K_TXDESC_CTSENA;
e0d687bd
PR		 715 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
716 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw,
b1ae1edf 717 info->control.vif, pktlen, info));
8a63facc
BC		 718 }
719 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
720 ieee80211_get_hdrlen_from_skb(skb), padsize,
721 get_hw_packet_type(skb),
e0d687bd 722 (ah->power_level * 2),
8a63facc
BC		 723 hw_rate,
724 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
725 cts_rate, duration);
726 if (ret)
727 goto err_unmap;
728
729 memset(mrr_rate, 0, sizeof(mrr_rate));
730 memset(mrr_tries, 0, sizeof(mrr_tries));
731 for (i = 0; i < 3; i++) {
e0d687bd 732 rate = ieee80211_get_alt_retry_rate(ah->hw, info, i);
8a63facc 733 if (!rate)
400ec45a 734 break;
fa1c114f 735
8a63facc
BC		 736 mrr_rate[i] = rate->hw_value;
737 mrr_tries[i] = info->control.rates[i + 1].count;
fa1c114f
JS		 738 }
739
8a63facc
BC		 740 ath5k_hw_setup_mrr_tx_desc(ah, ds,
741 mrr_rate[0], mrr_tries[0],
742 mrr_rate[1], mrr_tries[1],
743 mrr_rate[2], mrr_tries[2]);
fa1c114f 744
8a63facc
BC		 745 ds->ds_link = 0;
746 ds->ds_data = bf->skbaddr;
63266a65 747
8a63facc
BC		 748 spin_lock_bh(&txq->lock);
749 list_add_tail(&bf->list, &txq->q);
925e0b06 750 txq->txq_len++;
8a63facc
BC		 751 if (txq->link == NULL) /* is this first packet? */
752 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
753 else /* no, so only link it */
754 *txq->link = bf->daddr;
63266a65 755
8a63facc
BC		 756 txq->link = &ds->ds_link;
757 ath5k_hw_start_tx_dma(ah, txq->qnum);
758 mmiowb();
759 spin_unlock_bh(&txq->lock);
760
761 return 0;
762err_unmap:
e0d687bd 763 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
8a63facc 764 return ret;
63266a65
BR		 765}
766
8a63facc
BC		 767/*******************\
768* Descriptors setup *
769\*******************/
770
d8ee398d 771static int
e0d687bd 772ath5k_desc_alloc(struct ath5k_hw *ah)
fa1c114f 773{
8a63facc
BC		 774 struct ath5k_desc *ds;
775 struct ath5k_buf *bf;
776 dma_addr_t da;
777 unsigned int i;
778 int ret;
d8ee398d 779
8a63facc 780 /* allocate descriptors */
e0d687bd 781 ah->desc_len = sizeof(struct ath5k_desc) *
8a63facc 782 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
aeae4ac9 783
e0d687bd
PR		 784 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len,
785 &ah->desc_daddr, GFP_KERNEL);
786 if (ah->desc == NULL) {
787 ATH5K_ERR(ah, "can't allocate descriptors\n");
8a63facc
BC		 788 ret = -ENOMEM;
789 goto err;
790 }
e0d687bd
PR		 791 ds = ah->desc;
792 da = ah->desc_daddr;
793 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
794 ds, ah->desc_len, (unsigned long long)ah->desc_daddr);
fa1c114f 795
8a63facc
BC		 796 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
797 sizeof(struct ath5k_buf), GFP_KERNEL);
798 if (bf == NULL) {
e0d687bd 799 ATH5K_ERR(ah, "can't allocate bufptr\n");
8a63facc
BC		 800 ret = -ENOMEM;
801 goto err_free;
802 }
e0d687bd 803 ah->bufptr = bf;
fa1c114f 804
e0d687bd 805 INIT_LIST_HEAD(&ah->rxbuf);
8a63facc
BC		 806 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
807 bf->desc = ds;
808 bf->daddr = da;
e0d687bd 809 list_add_tail(&bf->list, &ah->rxbuf);
8a63facc 810 }
d8ee398d 811
e0d687bd
PR		 812 INIT_LIST_HEAD(&ah->txbuf);
813 ah->txbuf_len = ATH_TXBUF;
e4bbf2f5 814 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
8a63facc
BC		 815 bf->desc = ds;
816 bf->daddr = da;
e0d687bd 817 list_add_tail(&bf->list, &ah->txbuf);
fa1c114f
JS		 818 }
819
b1ae1edf 820 /* beacon buffers */
e0d687bd 821 INIT_LIST_HEAD(&ah->bcbuf);
b1ae1edf
BG		 822 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
823 bf->desc = ds;
824 bf->daddr = da;
e0d687bd 825 list_add_tail(&bf->list, &ah->bcbuf);
b1ae1edf 826 }
fa1c114f 827
8a63facc
BC		 828 return 0;
829err_free:
e0d687bd 830 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
8a63facc 831err:
e0d687bd 832 ah->desc = NULL;
8a63facc
BC		 833 return ret;
834}
fa1c114f 835
cd2c5486 836void
e0d687bd 837ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
cd2c5486
BR		 838{
839 BUG_ON(!bf);
840 if (!bf->skb)
841 return;
e0d687bd 842 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len,
cd2c5486
BR		 843 DMA_TO_DEVICE);
844 dev_kfree_skb_any(bf->skb);
845 bf->skb = NULL;
846 bf->skbaddr = 0;
847 bf->desc->ds_data = 0;
848}
849
850void
e0d687bd 851ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
cd2c5486 852{
cd2c5486
BR		 853 struct ath_common *common = ath5k_hw_common(ah);
854
855 BUG_ON(!bf);
856 if (!bf->skb)
857 return;
e0d687bd 858 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize,
cd2c5486
BR		 859 DMA_FROM_DEVICE);
860 dev_kfree_skb_any(bf->skb);
861 bf->skb = NULL;
862 bf->skbaddr = 0;
863 bf->desc->ds_data = 0;
864}
865
8a63facc 866static void
e0d687bd 867ath5k_desc_free(struct ath5k_hw *ah)
8a63facc
BC		 868{
869 struct ath5k_buf *bf;
d8ee398d 870
e0d687bd
PR		 871 list_for_each_entry(bf, &ah->txbuf, list)
872 ath5k_txbuf_free_skb(ah, bf);
873 list_for_each_entry(bf, &ah->rxbuf, list)
874 ath5k_rxbuf_free_skb(ah, bf);
875 list_for_each_entry(bf, &ah->bcbuf, list)
876 ath5k_txbuf_free_skb(ah, bf);
d8ee398d 877
8a63facc 878 /* Free memory associated with all descriptors */
e0d687bd
PR		 879 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
880 ah->desc = NULL;
881 ah->desc_daddr = 0;
d8ee398d 882
e0d687bd
PR		 883 kfree(ah->bufptr);
884 ah->bufptr = NULL;
fa1c114f
JS		 885}
886
8a63facc
BC		 887
888/**************\
889* Queues setup *
890\**************/
891
892static struct ath5k_txq *
e0d687bd 893ath5k_txq_setup(struct ath5k_hw *ah,
8a63facc 894 int qtype, int subtype)
fa1c114f 895{
8a63facc
BC		 896 struct ath5k_txq *txq;
897 struct ath5k_txq_info qi = {
898 .tqi_subtype = subtype,
de8af455
BR		 899 /* XXX: default values not correct for B and XR channels,
900 * but who cares? */
901 .tqi_aifs = AR5K_TUNE_AIFS,
902 .tqi_cw_min = AR5K_TUNE_CWMIN,
903 .tqi_cw_max = AR5K_TUNE_CWMAX
8a63facc
BC		 904 };
905 int qnum;
d8ee398d 906
e30eb4ab 907 /*
8a63facc
BC		 908 * Enable interrupts only for EOL and DESC conditions.
909 * We mark tx descriptors to receive a DESC interrupt
910 * when a tx queue gets deep; otherwise we wait for the
911 * EOL to reap descriptors. Note that this is done to
912 * reduce interrupt load and this only defers reaping
913 * descriptors, never transmitting frames. Aside from
914 * reducing interrupts this also permits more concurrency.
915 * The only potential downside is if the tx queue backs
916 * up in which case the top half of the kernel may backup
917 * due to a lack of tx descriptors.
e30eb4ab 918 */
8a63facc
BC		 919 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
920 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
921 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
922 if (qnum < 0) {
923 /*
924 * NB: don't print a message, this happens
925 * normally on parts with too few tx queues
926 */
927 return ERR_PTR(qnum);
928 }
e0d687bd
PR		 929 if (qnum >= ARRAY_SIZE(ah->txqs)) {
930 ATH5K_ERR(ah, "hw qnum %u out of range, max %tu!\n",
931 qnum, ARRAY_SIZE(ah->txqs));
8a63facc
BC		 932 ath5k_hw_release_tx_queue(ah, qnum);
933 return ERR_PTR(-EINVAL);
934 }
e0d687bd 935 txq = &ah->txqs[qnum];
8a63facc
BC		 936 if (!txq->setup) {
937 txq->qnum = qnum;
938 txq->link = NULL;
939 INIT_LIST_HEAD(&txq->q);
940 spin_lock_init(&txq->lock);
941 txq->setup = true;
925e0b06 942 txq->txq_len = 0;
81266baf 943 txq->txq_max = ATH5K_TXQ_LEN_MAX;
4edd761f 944 txq->txq_poll_mark = false;
923e5b3d 945 txq->txq_stuck = 0;
8a63facc 946 }
e0d687bd 947 return &ah->txqs[qnum];
fa1c114f
JS		 948}
949
8a63facc
BC		 950static int
951ath5k_beaconq_setup(struct ath5k_hw *ah)
fa1c114f 952{
8a63facc 953 struct ath5k_txq_info qi = {
de8af455
BR		 954 /* XXX: default values not correct for B and XR channels,
955 * but who cares? */
956 .tqi_aifs = AR5K_TUNE_AIFS,
957 .tqi_cw_min = AR5K_TUNE_CWMIN,
958 .tqi_cw_max = AR5K_TUNE_CWMAX,
8a63facc
BC		 959 /* NB: for dynamic turbo, don't enable any other interrupts */
960 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
961 };
d8ee398d 962
8a63facc 963 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
fa1c114f
JS		 964}
965
8a63facc 966static int
e0d687bd 967ath5k_beaconq_config(struct ath5k_hw *ah)
fa1c114f 968{
8a63facc
BC		 969 struct ath5k_txq_info qi;
970 int ret;
fa1c114f 971
e0d687bd 972 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi);
8a63facc
BC		 973 if (ret)
974 goto err;
fa1c114f 975
e0d687bd
PR		 976 if (ah->opmode == NL80211_IFTYPE_AP ||
977 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
8a63facc
BC		 978 /*
979 * Always burst out beacon and CAB traffic
980 * (aifs = cwmin = cwmax = 0)
981 */
982 qi.tqi_aifs = 0;
983 qi.tqi_cw_min = 0;
984 qi.tqi_cw_max = 0;
e0d687bd 985 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) {
8a63facc
BC		 986 /*
987 * Adhoc mode; backoff between 0 and (2 * cw_min).
988 */
989 qi.tqi_aifs = 0;
990 qi.tqi_cw_min = 0;
de8af455 991 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
8a63facc 992 }
fa1c114f 993
e0d687bd 994 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
8a63facc
BC		 995 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
996 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
fa1c114f 997
e0d687bd 998 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi);
8a63facc 999 if (ret) {
e0d687bd 1000 ATH5K_ERR(ah, "%s: unable to update parameters for beacon "
8a63facc
BC		 1001 "hardware queue!\n", __func__);
1002 goto err;
1003 }
e0d687bd 1004 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */
8a63facc
BC		 1005 if (ret)
1006 goto err;
b7266047 1007
8a63facc
BC		 1008 /* reconfigure cabq with ready time to 80% of beacon_interval */
1009 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1010 if (ret)
1011 goto err;
b7266047 1012
e0d687bd 1013 qi.tqi_ready_time = (ah->bintval * 80) / 100;
8a63facc
BC		 1014 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1015 if (ret)
1016 goto err;
b7266047 1017
8a63facc
BC		 1018 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1019err:
1020 return ret;
d8ee398d
LR		 1021}
1022
80dac9ee
NK		 1023/**
1024 * ath5k_drain_tx_buffs - Empty tx buffers
1025 *
e0d687bd 1026 * @ah The &struct ath5k_hw
80dac9ee
NK		 1027 *
1028 * Empty tx buffers from all queues in preparation
1029 * of a reset or during shutdown.
1030 *
1031 * NB: this assumes output has been stopped and
1032 * we do not need to block ath5k_tx_tasklet
1033 */
8a63facc 1034static void
e0d687bd 1035ath5k_drain_tx_buffs(struct ath5k_hw *ah)
8a63facc 1036{
80dac9ee 1037 struct ath5k_txq *txq;
8a63facc 1038 struct ath5k_buf *bf, *bf0;
80dac9ee 1039 int i;
b6ea0356 1040
e0d687bd
PR		 1041 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
1042 if (ah->txqs[i].setup) {
1043 txq = &ah->txqs[i];
80dac9ee
NK		 1044 spin_lock_bh(&txq->lock);
1045 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
e0d687bd 1046 ath5k_debug_printtxbuf(ah, bf);
b6ea0356 1047
e0d687bd 1048 ath5k_txbuf_free_skb(ah, bf);
fa1c114f 1049
e0d687bd
PR		 1050 spin_lock_bh(&ah->txbuflock);
1051 list_move_tail(&bf->list, &ah->txbuf);
1052 ah->txbuf_len++;
80dac9ee 1053 txq->txq_len--;
e0d687bd 1054 spin_unlock_bh(&ah->txbuflock);
8a63facc 1055 }
80dac9ee
NK		 1056 txq->link = NULL;
1057 txq->txq_poll_mark = false;
1058 spin_unlock_bh(&txq->lock);
1059 }
0452d4a5 1060 }
fa1c114f
JS		 1061}
1062
8a63facc 1063static void
e0d687bd 1064ath5k_txq_release(struct ath5k_hw *ah)
2ac2927a 1065{
e0d687bd 1066 struct ath5k_txq *txq = ah->txqs;
8a63facc 1067 unsigned int i;
2ac2927a 1068
e0d687bd 1069 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++)
8a63facc 1070 if (txq->setup) {
e0d687bd 1071 ath5k_hw_release_tx_queue(ah, txq->qnum);
8a63facc
BC		 1072 txq->setup = false;
1073 }
1074}
2ac2927a 1075
2ac2927a 1076
8a63facc
BC		 1077/*************\
1078* RX Handling *
1079\*************/
2ac2927a 1080
8a63facc
BC		 1081/*
1082 * Enable the receive h/w following a reset.
1083 */
fa1c114f 1084static int
e0d687bd 1085ath5k_rx_start(struct ath5k_hw *ah)
fa1c114f 1086{
8a63facc
BC		 1087 struct ath_common *common = ath5k_hw_common(ah);
1088 struct ath5k_buf *bf;
1089 int ret;
fa1c114f 1090
8a63facc 1091 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
fa1c114f 1092
e0d687bd 1093 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
8a63facc 1094 common->cachelsz, common->rx_bufsize);
2f7fe870 1095
e0d687bd
PR		 1096 spin_lock_bh(&ah->rxbuflock);
1097 ah->rxlink = NULL;
1098 list_for_each_entry(bf, &ah->rxbuf, list) {
1099 ret = ath5k_rxbuf_setup(ah, bf);
8a63facc 1100 if (ret != 0) {
e0d687bd 1101 spin_unlock_bh(&ah->rxbuflock);
8a63facc
BC		 1102 goto err;
1103 }
2f7fe870 1104 }
e0d687bd 1105 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
8a63facc 1106 ath5k_hw_set_rxdp(ah, bf->daddr);
e0d687bd 1107 spin_unlock_bh(&ah->rxbuflock);
2f7fe870 1108
8a63facc 1109 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
e0d687bd 1110 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */
8a63facc 1111 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
fa1c114f
JS		 1112
1113 return 0;
8a63facc 1114err:
fa1c114f
JS		 1115 return ret;
1116}
1117
8a63facc 1118/*
80dac9ee
NK		 1119 * Disable the receive logic on PCU (DRU)
1120 * In preparation for a shutdown.
1121 *
1122 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1123 * does.
8a63facc
BC		 1124 */
1125static void
e0d687bd 1126ath5k_rx_stop(struct ath5k_hw *ah)
fa1c114f 1127{
fa1c114f 1128
8a63facc 1129 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
80dac9ee 1130 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f 1131
e0d687bd 1132 ath5k_debug_printrxbuffs(ah);
8a63facc 1133}
fa1c114f 1134
8a63facc 1135static unsigned int
e0d687bd 1136ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb,
8a63facc
BC		 1137 struct ath5k_rx_status *rs)
1138{
8a63facc
BC		 1139 struct ath_common *common = ath5k_hw_common(ah);
1140 struct ieee80211_hdr *hdr = (void *)skb->data;
1141 unsigned int keyix, hlen;
fa1c114f 1142
8a63facc
BC		 1143 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1144 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1145 return RX_FLAG_DECRYPTED;
fa1c114f 1146
8a63facc
BC		 1147 /* Apparently when a default key is used to decrypt the packet
1148 the hw does not set the index used to decrypt. In such cases
1149 get the index from the packet. */
1150 hlen = ieee80211_hdrlen(hdr->frame_control);
1151 if (ieee80211_has_protected(hdr->frame_control) &&
1152 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1153 skb->len >= hlen + 4) {
1154 keyix = skb->data[hlen + 3] >> 6;
1155
1156 if (test_bit(keyix, common->keymap))
1157 return RX_FLAG_DECRYPTED;
1158 }
fa1c114f
JS		 1159
1160 return 0;
fa1c114f
JS		 1161}
1162
8a63facc 1163
fa1c114f 1164static void
e0d687bd 1165ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb,
8a63facc 1166 struct ieee80211_rx_status *rxs)
fa1c114f 1167{
e0d687bd 1168 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1169 u64 tsf, bc_tstamp;
1170 u32 hw_tu;
1171 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
fa1c114f 1172
8a63facc
BC		 1173 if (ieee80211_is_beacon(mgmt->frame_control) &&
1174 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1175 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1176 /*
1177 * Received an IBSS beacon with the same BSSID. Hardware *must*
1178 * have updated the local TSF. We have to work around various
1179 * hardware bugs, though...
1180 */
e0d687bd 1181 tsf = ath5k_hw_get_tsf64(ah);
8a63facc
BC		 1182 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1183 hw_tu = TSF_TO_TU(tsf);
fa1c114f 1184
e0d687bd 1185 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
8a63facc
BC		 1186 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1187 (unsigned long long)bc_tstamp,
1188 (unsigned long long)rxs->mactime,
1189 (unsigned long long)(rxs->mactime - bc_tstamp),
1190 (unsigned long long)tsf);
fa1c114f 1191
8a63facc
BC		 1192 /*
1193 * Sometimes the HW will give us a wrong tstamp in the rx
1194 * status, causing the timestamp extension to go wrong.
1195 * (This seems to happen especially with beacon frames bigger
1196 * than 78 byte (incl. FCS))
1197 * But we know that the receive timestamp must be later than the
1198 * timestamp of the beacon since HW must have synced to that.
1199 *
1200 * NOTE: here we assume mactime to be after the frame was
1201 * received, not like mac80211 which defines it at the start.
1202 */
1203 if (bc_tstamp > rxs->mactime) {
e0d687bd 1204 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
8a63facc
BC		 1205 "fixing mactime from %llx to %llx\n",
1206 (unsigned long long)rxs->mactime,
1207 (unsigned long long)tsf);
1208 rxs->mactime = tsf;
1209 }
fa1c114f 1210
8a63facc
BC		 1211 /*
1212 * Local TSF might have moved higher than our beacon timers,
1213 * in that case we have to update them to continue sending
1214 * beacons. This also takes care of synchronizing beacon sending
1215 * times with other stations.
1216 */
e0d687bd
PR		 1217 if (hw_tu >= ah->nexttbtt)
1218 ath5k_beacon_update_timers(ah, bc_tstamp);
7f896126
BR		 1219
1220 /* Check if the beacon timers are still correct, because a TSF
1221 * update might have created a window between them - for a
1222 * longer description see the comment of this function: */
e0d687bd
PR		 1223 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) {
1224 ath5k_beacon_update_timers(ah, bc_tstamp);
1225 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
7f896126
BR		 1226 "fixed beacon timers after beacon receive\n");
1227 }
8a63facc
BC		 1228 }
1229}
fa1c114f 1230
8a63facc 1231static void
e0d687bd 1232ath5k_update_beacon_rssi(struct ath5k_hw *ah, struct sk_buff *skb, int rssi)
8a63facc
BC		 1233{
1234 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
8a63facc 1235 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1236
8a63facc
BC		 1237 /* only beacons from our BSSID */
1238 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1239 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1240 return;
fa1c114f 1241
eef39bef 1242 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
fa1c114f 1243
8a63facc
BC		 1244 /* in IBSS mode we should keep RSSI statistics per neighbour */
1245 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1246}
fa1c114f 1247
8a63facc
BC		 1248/*
1249 * Compute padding position. skb must contain an IEEE 802.11 frame
1250 */
1251static int ath5k_common_padpos(struct sk_buff *skb)
fa1c114f 1252{
e4bbf2f5 1253 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
8a63facc
BC		 1254 __le16 frame_control = hdr->frame_control;
1255 int padpos = 24;
fa1c114f 1256
d2c7f773 1257 if (ieee80211_has_a4(frame_control))
8a63facc 1258 padpos += ETH_ALEN;
d2c7f773
PR		 1259
1260 if (ieee80211_is_data_qos(frame_control))
8a63facc 1261 padpos += IEEE80211_QOS_CTL_LEN;
8a63facc
BC		 1262
1263 return padpos;
fa1c114f
JS		 1264}
1265
8a63facc
BC		 1266/*
1267 * This function expects an 802.11 frame and returns the number of
1268 * bytes added, or -1 if we don't have enough header room.
1269 */
1270static int ath5k_add_padding(struct sk_buff *skb)
fa1c114f 1271{
8a63facc
BC		 1272 int padpos = ath5k_common_padpos(skb);
1273 int padsize = padpos & 3;
fa1c114f 1274
e4bbf2f5 1275 if (padsize && skb->len > padpos) {
fa1c114f 1276
8a63facc
BC		 1277 if (skb_headroom(skb) < padsize)
1278 return -1;
fa1c114f 1279
8a63facc 1280 skb_push(skb, padsize);
e4bbf2f5 1281 memmove(skb->data, skb->data + padsize, padpos);
8a63facc
BC		 1282 return padsize;
1283 }
a951ae21 1284
8a63facc
BC		 1285 return 0;
1286}
fa1c114f 1287
8a63facc
BC		 1288/*
1289 * The MAC header is padded to have 32-bit boundary if the
1290 * packet payload is non-zero. The general calculation for
1291 * padsize would take into account odd header lengths:
1292 * padsize = 4 - (hdrlen & 3); however, since only
1293 * even-length headers are used, padding can only be 0 or 2
1294 * bytes and we can optimize this a bit. We must not try to
1295 * remove padding from short control frames that do not have a
1296 * payload.
1297 *
1298 * This function expects an 802.11 frame and returns the number of
1299 * bytes removed.
1300 */
1301static int ath5k_remove_padding(struct sk_buff *skb)
1302{
1303 int padpos = ath5k_common_padpos(skb);
1304 int padsize = padpos & 3;
6d91e1d8 1305
e4bbf2f5 1306 if (padsize && skb->len >= padpos + padsize) {
8a63facc
BC		 1307 memmove(skb->data + padsize, skb->data, padpos);
1308 skb_pull(skb, padsize);
1309 return padsize;
fa1c114f 1310 }
a951ae21 1311
8a63facc 1312 return 0;
fa1c114f
JS		 1313}
1314
1315static void
e0d687bd 1316ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb,
8a63facc 1317 struct ath5k_rx_status *rs)
fa1c114f 1318{
8a63facc
BC		 1319 struct ieee80211_rx_status *rxs;
1320
1321 ath5k_remove_padding(skb);
1322
1323 rxs = IEEE80211_SKB_RXCB(skb);
1324
1325 rxs->flag = 0;
1326 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1327 rxs->flag |= RX_FLAG_MMIC_ERROR;
fa1c114f
JS		 1328
1329 /*
8a63facc
BC		 1330 * always extend the mac timestamp, since this information is
1331 * also needed for proper IBSS merging.
1332 *
1333 * XXX: it might be too late to do it here, since rs_tstamp is
1334 * 15bit only. that means TSF extension has to be done within
1335 * 32768usec (about 32ms). it might be necessary to move this to
1336 * the interrupt handler, like it is done in madwifi.
1337 *
1338 * Unfortunately we don't know when the hardware takes the rx
1339 * timestamp (beginning of phy frame, data frame, end of rx?).
1340 * The only thing we know is that it is hardware specific...
1341 * On AR5213 it seems the rx timestamp is at the end of the
6a2a0e73 1342 * frame, but I'm not sure.
8a63facc
BC		 1343 *
1344 * NOTE: mac80211 defines mactime at the beginning of the first
1345 * data symbol. Since we don't have any time references it's
1346 * impossible to comply to that. This affects IBSS merge only
1347 * right now, so it's not too bad...
fa1c114f 1348 */
e0d687bd 1349 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp);
6ebacbb7 1350 rxs->flag |= RX_FLAG_MACTIME_MPDU;
fa1c114f 1351
e0d687bd
PR		 1352 rxs->freq = ah->curchan->center_freq;
1353 rxs->band = ah->curchan->band;
fa1c114f 1354
e0d687bd 1355 rxs->signal = ah->ah_noise_floor + rs->rs_rssi;
fa1c114f 1356
8a63facc 1357 rxs->antenna = rs->rs_antenna;
fa1c114f 1358
8a63facc 1359 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
e0d687bd 1360 ah->stats.antenna_rx[rs->rs_antenna]++;
8a63facc 1361 else
e0d687bd 1362 ah->stats.antenna_rx[0]++; /* invalid */
fa1c114f 1363
e0d687bd
PR		 1364 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate);
1365 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs);
fa1c114f 1366
8a63facc 1367 if (rxs->rate_idx >= 0 && rs->rs_rate ==
e0d687bd 1368 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
8a63facc 1369 rxs->flag |= RX_FLAG_SHORTPRE;
fa1c114f 1370
e0d687bd 1371 trace_ath5k_rx(ah, skb);
fa1c114f 1372
e0d687bd 1373 ath5k_update_beacon_rssi(ah, skb, rs->rs_rssi);
fa1c114f 1374
8a63facc 1375 /* check beacons in IBSS mode */
e0d687bd
PR		 1376 if (ah->opmode == NL80211_IFTYPE_ADHOC)
1377 ath5k_check_ibss_tsf(ah, skb, rxs);
fa1c114f 1378
e0d687bd 1379 ieee80211_rx(ah->hw, skb);
8a63facc 1380}
fa1c114f 1381
8a63facc
BC		 1382/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1383 *
1384 * Check if we want to further process this frame or not. Also update
1385 * statistics. Return true if we want this frame, false if not.
fa1c114f 1386 */
8a63facc 1387static bool
e0d687bd 1388ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs)
fa1c114f 1389{
e0d687bd
PR		 1390 ah->stats.rx_all_count++;
1391 ah->stats.rx_bytes_count += rs->rs_datalen;
fa1c114f 1392
8a63facc
BC		 1393 if (unlikely(rs->rs_status)) {
1394 if (rs->rs_status & AR5K_RXERR_CRC)
e0d687bd 1395 ah->stats.rxerr_crc++;
8a63facc 1396 if (rs->rs_status & AR5K_RXERR_FIFO)
e0d687bd 1397 ah->stats.rxerr_fifo++;
8a63facc 1398 if (rs->rs_status & AR5K_RXERR_PHY) {
e0d687bd 1399 ah->stats.rxerr_phy++;
8a63facc 1400 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
e0d687bd 1401 ah->stats.rxerr_phy_code[rs->rs_phyerr]++;
8a63facc
BC		 1402 return false;
1403 }
1404 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1405 /*
1406 * Decrypt error. If the error occurred
1407 * because there was no hardware key, then
1408 * let the frame through so the upper layers
1409 * can process it. This is necessary for 5210
1410 * parts which have no way to setup a ``clear''
1411 * key cache entry.
1412 *
1413 * XXX do key cache faulting
1414 */
e0d687bd 1415 ah->stats.rxerr_decrypt++;
8a63facc
BC		 1416 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1417 !(rs->rs_status & AR5K_RXERR_CRC))
1418 return true;
1419 }
1420 if (rs->rs_status & AR5K_RXERR_MIC) {
e0d687bd 1421 ah->stats.rxerr_mic++;
8a63facc 1422 return true;
fa1c114f 1423 }
fa1c114f 1424
8a63facc
BC		 1425 /* reject any frames with non-crypto errors */
1426 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1427 return false;
1428 }
fa1c114f 1429
8a63facc 1430 if (unlikely(rs->rs_more)) {
e0d687bd 1431 ah->stats.rxerr_jumbo++;
8a63facc
BC		 1432 return false;
1433 }
1434 return true;
fa1c114f
JS		 1435}
1436
c266c71a 1437static void
e0d687bd 1438ath5k_set_current_imask(struct ath5k_hw *ah)
c266c71a 1439{
4fc5401c 1440 enum ath5k_int imask;
c266c71a
FF		 1441 unsigned long flags;
1442
e0d687bd
PR		 1443 spin_lock_irqsave(&ah->irqlock, flags);
1444 imask = ah->imask;
1445 if (ah->rx_pending)
c266c71a 1446 imask &= ~AR5K_INT_RX_ALL;
e0d687bd 1447 if (ah->tx_pending)
c266c71a 1448 imask &= ~AR5K_INT_TX_ALL;
e0d687bd
PR		 1449 ath5k_hw_set_imr(ah, imask);
1450 spin_unlock_irqrestore(&ah->irqlock, flags);
c266c71a
FF		 1451}
1452
fa1c114f 1453static void
8a63facc 1454ath5k_tasklet_rx(unsigned long data)
fa1c114f 1455{
8a63facc
BC		 1456 struct ath5k_rx_status rs = {};
1457 struct sk_buff *skb, *next_skb;
1458 dma_addr_t next_skb_addr;
e0d687bd 1459 struct ath5k_hw *ah = (void *)data;
dc1e001b 1460 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1461 struct ath5k_buf *bf;
1462 struct ath5k_desc *ds;
1463 int ret;
fa1c114f 1464
e0d687bd
PR		 1465 spin_lock(&ah->rxbuflock);
1466 if (list_empty(&ah->rxbuf)) {
1467 ATH5K_WARN(ah, "empty rx buf pool\n");
8a63facc
BC		 1468 goto unlock;
1469 }
1470 do {
e0d687bd 1471 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
8a63facc
BC		 1472 BUG_ON(bf->skb == NULL);
1473 skb = bf->skb;
1474 ds = bf->desc;
fa1c114f 1475
8a63facc 1476 /* bail if HW is still using self-linked descriptor */
e0d687bd 1477 if (ath5k_hw_get_rxdp(ah) == bf->daddr)
8a63facc 1478 break;
fa1c114f 1479
e0d687bd 1480 ret = ah->ah_proc_rx_desc(ah, ds, &rs);
8a63facc
BC		 1481 if (unlikely(ret == -EINPROGRESS))
1482 break;
1483 else if (unlikely(ret)) {
e0d687bd
PR		 1484 ATH5K_ERR(ah, "error in processing rx descriptor\n");
1485 ah->stats.rxerr_proc++;
8a63facc
BC		 1486 break;
1487 }
fa1c114f 1488
e0d687bd
PR		 1489 if (ath5k_receive_frame_ok(ah, &rs)) {
1490 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr);
fa1c114f 1491
8a63facc
BC		 1492 /*
1493 * If we can't replace bf->skb with a new skb under
1494 * memory pressure, just skip this packet
1495 */
1496 if (!next_skb)
1497 goto next;
036cd1ec 1498
e0d687bd 1499 dma_unmap_single(ah->dev, bf->skbaddr,
8a63facc 1500 common->rx_bufsize,
aeae4ac9 1501 DMA_FROM_DEVICE);
036cd1ec 1502
8a63facc 1503 skb_put(skb, rs.rs_datalen);
6ba81c2c 1504
e0d687bd 1505 ath5k_receive_frame(ah, skb, &rs);
6ba81c2c 1506
8a63facc
BC		 1507 bf->skb = next_skb;
1508 bf->skbaddr = next_skb_addr;
036cd1ec 1509 }
8a63facc 1510next:
e0d687bd
PR		 1511 list_move_tail(&bf->list, &ah->rxbuf);
1512 } while (ath5k_rxbuf_setup(ah, bf) == 0);
8a63facc 1513unlock:
e0d687bd
PR		 1514 spin_unlock(&ah->rxbuflock);
1515 ah->rx_pending = false;
1516 ath5k_set_current_imask(ah);
036cd1ec
BR		 1517}
1518
b4ea449d 1519
8a63facc
BC		 1520/*************\
1521* TX Handling *
1522\*************/
b4ea449d 1523
7bb45683 1524void
cd2c5486
BR		 1525ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1526 struct ath5k_txq *txq)
8a63facc 1527{
e0d687bd 1528 struct ath5k_hw *ah = hw->priv;
8a63facc
BC		 1529 struct ath5k_buf *bf;
1530 unsigned long flags;
1531 int padsize;
b4ea449d 1532
e0d687bd 1533 trace_ath5k_tx(ah, skb, txq);
b4ea449d 1534
8a63facc
BC		 1535 /*
1536 * The hardware expects the header padded to 4 byte boundaries.
1537 * If this is not the case, we add the padding after the header.
1538 */
1539 padsize = ath5k_add_padding(skb);
1540 if (padsize < 0) {
e0d687bd 1541 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough"
8a63facc
BC		 1542 " headroom to pad");
1543 goto drop_packet;
1544 }
8127fbdc 1545
4e868796
FF		 1546 if (txq->txq_len >= txq->txq_max &&
1547 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX)
925e0b06
BR		 1548 ieee80211_stop_queue(hw, txq->qnum);
1549
e0d687bd
PR		 1550 spin_lock_irqsave(&ah->txbuflock, flags);
1551 if (list_empty(&ah->txbuf)) {
1552 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n");
1553 spin_unlock_irqrestore(&ah->txbuflock, flags);
651d9375 1554 ieee80211_stop_queues(hw);
8a63facc 1555 goto drop_packet;
8127fbdc 1556 }
e0d687bd 1557 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list);
8a63facc 1558 list_del(&bf->list);
e0d687bd
PR		 1559 ah->txbuf_len--;
1560 if (list_empty(&ah->txbuf))
8a63facc 1561 ieee80211_stop_queues(hw);
e0d687bd 1562 spin_unlock_irqrestore(&ah->txbuflock, flags);
8a63facc
BC		 1563
1564 bf->skb = skb;
1565
e0d687bd 1566 if (ath5k_txbuf_setup(ah, bf, txq, padsize)) {
8a63facc 1567 bf->skb = NULL;
e0d687bd
PR		 1568 spin_lock_irqsave(&ah->txbuflock, flags);
1569 list_add_tail(&bf->list, &ah->txbuf);
1570 ah->txbuf_len++;
1571 spin_unlock_irqrestore(&ah->txbuflock, flags);
8a63facc 1572 goto drop_packet;
8127fbdc 1573 }
7bb45683 1574 return;
8127fbdc 1575
8a63facc
BC		 1576drop_packet:
1577 dev_kfree_skb_any(skb);
8127fbdc
BP		 1578}
1579
1440401e 1580static void
e0d687bd 1581ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb,
0e472252 1582 struct ath5k_txq *txq, struct ath5k_tx_status *ts)
1440401e
BR		 1583{
1584 struct ieee80211_tx_info *info;
ed895085 1585 u8 tries[3];
1440401e
BR		 1586 int i;
1587
e0d687bd
PR		 1588 ah->stats.tx_all_count++;
1589 ah->stats.tx_bytes_count += skb->len;
1440401e
BR		 1590 info = IEEE80211_SKB_CB(skb);
1591
ed895085
FF		 1592 tries[0] = info->status.rates[0].count;
1593 tries[1] = info->status.rates[1].count;
1594 tries[2] = info->status.rates[2].count;
1595
1440401e 1596 ieee80211_tx_info_clear_status(info);
ed895085
FF		 1597
1598 for (i = 0; i < ts->ts_final_idx; i++) {
1440401e
BR		 1599 struct ieee80211_tx_rate *r =
1600 &info->status.rates[i];
1601
ed895085 1602 r->count = tries[i];
1440401e
BR		 1603 }
1604
ed895085 1605 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry;
6d7b97b2 1606 info->status.rates[ts->ts_final_idx + 1].idx = -1;
1440401e
BR		 1607
1608 if (unlikely(ts->ts_status)) {
e0d687bd 1609 ah->stats.ack_fail++;
1440401e
BR		 1610 if (ts->ts_status & AR5K_TXERR_FILT) {
1611 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
e0d687bd 1612 ah->stats.txerr_filt++;
1440401e
BR		 1613 }
1614 if (ts->ts_status & AR5K_TXERR_XRETRY)
e0d687bd 1615 ah->stats.txerr_retry++;
1440401e 1616 if (ts->ts_status & AR5K_TXERR_FIFO)
e0d687bd 1617 ah->stats.txerr_fifo++;
1440401e
BR		 1618 } else {
1619 info->flags |= IEEE80211_TX_STAT_ACK;
1620 info->status.ack_signal = ts->ts_rssi;
6d7b97b2
FF		 1621
1622 /* count the successful attempt as well */
1623 info->status.rates[ts->ts_final_idx].count++;
1440401e
BR		 1624 }
1625
1626 /*
1627 * Remove MAC header padding before giving the frame
1628 * back to mac80211.
1629 */
1630 ath5k_remove_padding(skb);
1631
1632 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
e0d687bd 1633 ah->stats.antenna_tx[ts->ts_antenna]++;
1440401e 1634 else
e0d687bd 1635 ah->stats.antenna_tx[0]++; /* invalid */
1440401e 1636
e0d687bd
PR		 1637 trace_ath5k_tx_complete(ah, skb, txq, ts);
1638 ieee80211_tx_status(ah->hw, skb);
1440401e 1639}
8a63facc
BC		 1640
1641static void
e0d687bd 1642ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq)
8127fbdc 1643{
8a63facc
BC		 1644 struct ath5k_tx_status ts = {};
1645 struct ath5k_buf *bf, *bf0;
1646 struct ath5k_desc *ds;
1647 struct sk_buff *skb;
1440401e 1648 int ret;
8127fbdc 1649
8a63facc
BC		 1650 spin_lock(&txq->lock);
1651 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
23413296
BR		 1652
1653 txq->txq_poll_mark = false;
1654
1655 /* skb might already have been processed last time. */
1656 if (bf->skb != NULL) {
1657 ds = bf->desc;
1658
e0d687bd 1659 ret = ah->ah_proc_tx_desc(ah, ds, &ts);
23413296
BR		 1660 if (unlikely(ret == -EINPROGRESS))
1661 break;
1662 else if (unlikely(ret)) {
e0d687bd 1663 ATH5K_ERR(ah,
23413296
BR		 1664 "error %d while processing "
1665 "queue %u\n", ret, txq->qnum);
1666 break;
1667 }
1668
1669 skb = bf->skb;
1670 bf->skb = NULL;
aeae4ac9 1671
e0d687bd 1672 dma_unmap_single(ah->dev, bf->skbaddr, skb->len,
aeae4ac9 1673 DMA_TO_DEVICE);
e0d687bd 1674 ath5k_tx_frame_completed(ah, skb, txq, &ts);
23413296 1675 }
8127fbdc 1676
8a63facc
BC		 1677 /*
1678 * It's possible that the hardware can say the buffer is
1679 * completed when it hasn't yet loaded the ds_link from
23413296
BR		 1680 * host memory and moved on.
1681 * Always keep the last descriptor to avoid HW races...
8a63facc 1682 */
e0d687bd
PR		 1683 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) {
1684 spin_lock(&ah->txbuflock);
1685 list_move_tail(&bf->list, &ah->txbuf);
1686 ah->txbuf_len++;
23413296 1687 txq->txq_len--;
e0d687bd 1688 spin_unlock(&ah->txbuflock);
8a63facc 1689 }
fa1c114f 1690 }
fa1c114f 1691 spin_unlock(&txq->lock);
4198a8d0 1692 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
e0d687bd 1693 ieee80211_wake_queue(ah->hw, txq->qnum);
fa1c114f
JS		 1694}
1695
1696static void
1697ath5k_tasklet_tx(unsigned long data)
1698{
8784d2ee 1699 int i;
e0d687bd 1700 struct ath5k_hw *ah = (void *)data;
fa1c114f 1701
e4bbf2f5 1702 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
e0d687bd
PR		 1703 if (ah->txqs[i].setup && (ah->ah_txq_isr & BIT(i)))
1704 ath5k_tx_processq(ah, &ah->txqs[i]);
c266c71a 1705
e0d687bd
PR		 1706 ah->tx_pending = false;
1707 ath5k_set_current_imask(ah);
fa1c114f
JS		 1708}
1709
1710
fa1c114f
JS		 1711/*****************\
1712* Beacon handling *
1713\*****************/
1714
1715/*
1716 * Setup the beacon frame for transmit.
1717 */
1718static int
e0d687bd 1719ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
fa1c114f
JS		 1720{
1721 struct sk_buff *skb = bf->skb;
a888d52d 1722 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1723 struct ath5k_desc *ds;
2bed03eb
NK		 1724 int ret = 0;
1725 u8 antenna;
fa1c114f 1726 u32 flags;
8127fbdc 1727 const int padsize = 0;
fa1c114f 1728
e0d687bd 1729 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
aeae4ac9 1730 DMA_TO_DEVICE);
e0d687bd 1731 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
fa1c114f
JS		 1732 "skbaddr %llx\n", skb, skb->data, skb->len,
1733 (unsigned long long)bf->skbaddr);
aeae4ac9 1734
e0d687bd
PR		 1735 if (dma_mapping_error(ah->dev, bf->skbaddr)) {
1736 ATH5K_ERR(ah, "beacon DMA mapping failed\n");
fa1c114f
JS		 1737 return -EIO;
1738 }
1739
1740 ds = bf->desc;
2bed03eb 1741 antenna = ah->ah_tx_ant;
fa1c114f
JS		 1742
1743 flags = AR5K_TXDESC_NOACK;
e0d687bd 1744 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1745 ds->ds_link = bf->daddr; /* self-linked */
1746 flags |= AR5K_TXDESC_VEOL;
2bed03eb 1747 } else
fa1c114f 1748 ds->ds_link = 0;
2bed03eb
NK		 1749
1750 /*
1751 * If we use multiple antennas on AP and use
1752 * the Sectored AP scenario, switch antenna every
1753 * 4 beacons to make sure everybody hears our AP.
1754 * When a client tries to associate, hw will keep
1755 * track of the tx antenna to be used for this client
6a2a0e73 1756 * automatically, based on ACKed packets.
2bed03eb
NK		 1757 *
1758 * Note: AP still listens and transmits RTS on the
1759 * default antenna which is supposed to be an omni.
1760 *
1761 * Note2: On sectored scenarios it's possible to have
a180a130
BC		 1762 * multiple antennas (1 omni -- the default -- and 14
1763 * sectors), so if we choose to actually support this
1764 * mode, we need to allow the user to set how many antennas
1765 * we have and tweak the code below to send beacons
1766 * on all of them.
2bed03eb
NK		 1767 */
1768 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
e0d687bd 1769 antenna = ah->bsent & 4 ? 2 : 1;
2bed03eb 1770
fa1c114f 1771
8f655dde
NK		 1772 /* FIXME: If we are in g mode and rate is a CCK rate
1773 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1774 * from tx power (value is in dB units already) */
fa1c114f 1775 ds->ds_data = bf->skbaddr;
281c56dd 1776 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 1777 ieee80211_get_hdrlen_from_skb(skb), padsize,
e0d687bd
PR		 1778 AR5K_PKT_TYPE_BEACON, (ah->power_level * 2),
1779 ieee80211_get_tx_rate(ah->hw, info)->hw_value,
2e92e6f2 1780 1, AR5K_TXKEYIX_INVALID,
400ec45a 1781 antenna, flags, 0, 0);
fa1c114f
JS		 1782 if (ret)
1783 goto err_unmap;
1784
1785 return 0;
1786err_unmap:
e0d687bd 1787 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
fa1c114f
JS		 1788 return ret;
1789}
1790
8a63facc
BC		 1791/*
1792 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1793 * this is called only once at config_bss time, for AP we do it every
1794 * SWBA interrupt so that the TIM will reflect buffered frames.
1795 *
1796 * Called with the beacon lock.
1797 */
cd2c5486 1798int
8a63facc
BC		 1799ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1800{
1801 int ret;
e0d687bd 1802 struct ath5k_hw *ah = hw->priv;
b1ae1edf 1803 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 1804 struct sk_buff *skb;
1805
1806 if (WARN_ON(!vif)) {
1807 ret = -EINVAL;
1808 goto out;
1809 }
1810
1811 skb = ieee80211_beacon_get(hw, vif);
1812
1813 if (!skb) {
1814 ret = -ENOMEM;
1815 goto out;
1816 }
1817
e0d687bd 1818 ath5k_txbuf_free_skb(ah, avf->bbuf);
b1ae1edf 1819 avf->bbuf->skb = skb;
e0d687bd 1820 ret = ath5k_beacon_setup(ah, avf->bbuf);
8a63facc 1821 if (ret)
b1ae1edf 1822 avf->bbuf->skb = NULL;
8a63facc
BC		 1823out:
1824 return ret;
1825}
1826
fa1c114f
JS		 1827/*
1828 * Transmit a beacon frame at SWBA. Dynamic updates to the
1829 * frame contents are done as needed and the slot time is
1830 * also adjusted based on current state.
1831 *
5faaff74
BC		 1832 * This is called from software irq context (beacontq tasklets)
1833 * or user context from ath5k_beacon_config.
fa1c114f
JS		 1834 */
1835static void
e0d687bd 1836ath5k_beacon_send(struct ath5k_hw *ah)
fa1c114f 1837{
b1ae1edf
BG		 1838 struct ieee80211_vif *vif;
1839 struct ath5k_vif *avf;
1840 struct ath5k_buf *bf;
cec8db23 1841 struct sk_buff *skb;
fa1c114f 1842
e0d687bd 1843 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1844
fa1c114f
JS		 1845 /*
1846 * Check if the previous beacon has gone out. If
a180a130 1847 * not, don't don't try to post another: skip this
fa1c114f
JS		 1848 * period and wait for the next. Missed beacons
1849 * indicate a problem and should not occur. If we
1850 * miss too many consecutive beacons reset the device.
1851 */
e0d687bd
PR		 1852 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) {
1853 ah->bmisscount++;
1854 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1855 "missed %u consecutive beacons\n", ah->bmisscount);
1856 if (ah->bmisscount > 10) { /* NB: 10 is a guess */
1857 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
fa1c114f 1858 "stuck beacon time (%u missed)\n",
e0d687bd
PR		 1859 ah->bmisscount);
1860 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
8d67a031 1861 "stuck beacon, resetting\n");
e0d687bd 1862 ieee80211_queue_work(ah->hw, &ah->reset_work);
fa1c114f
JS		 1863 }
1864 return;
1865 }
e0d687bd
PR		 1866 if (unlikely(ah->bmisscount != 0)) {
1867 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
fa1c114f 1868 "resume beacon xmit after %u misses\n",
e0d687bd
PR		 1869 ah->bmisscount);
1870 ah->bmisscount = 0;
fa1c114f
JS		 1871 }
1872
e0d687bd
PR		 1873 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs > 1) ||
1874 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
b1ae1edf
BG		 1875 u64 tsf = ath5k_hw_get_tsf64(ah);
1876 u32 tsftu = TSF_TO_TU(tsf);
e0d687bd
PR		 1877 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval;
1878 vif = ah->bslot[(slot + 1) % ATH_BCBUF];
1879 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
b1ae1edf 1880 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
e0d687bd 1881 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif);
b1ae1edf 1882 } else /* only one interface */
e0d687bd 1883 vif = ah->bslot[0];
b1ae1edf
BG		 1884
1885 if (!vif)
1886 return;
1887
1888 avf = (void *)vif->drv_priv;
1889 bf = avf->bbuf;
e0d687bd
PR		 1890 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION ||
1891 ah->opmode == NL80211_IFTYPE_MONITOR)) {
1892 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
b1ae1edf
BG		 1893 return;
1894 }
1895
fa1c114f
JS		 1896 /*
1897 * Stop any current dma and put the new frame on the queue.
1898 * This should never fail since we check above that no frames
1899 * are still pending on the queue.
1900 */
e0d687bd
PR		 1901 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) {
1902 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq);
fa1c114f
JS		 1903 /* NB: hw still stops DMA, so proceed */
1904 }
fa1c114f 1905
d82b577b 1906 /* refresh the beacon for AP or MESH mode */
e0d687bd
PR		 1907 if (ah->opmode == NL80211_IFTYPE_AP ||
1908 ah->opmode == NL80211_IFTYPE_MESH_POINT)
1909 ath5k_beacon_update(ah->hw, vif);
1071db86 1910
e0d687bd 1911 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]);
0e472252 1912
e0d687bd
PR		 1913 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr);
1914 ath5k_hw_start_tx_dma(ah, ah->bhalq);
1915 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1916 ah->bhalq, (unsigned long long)bf->daddr, bf->desc);
fa1c114f 1917
e0d687bd 1918 skb = ieee80211_get_buffered_bc(ah->hw, vif);
cec8db23 1919 while (skb) {
e0d687bd 1920 ath5k_tx_queue(ah->hw, skb, ah->cabq);
4e868796 1921
e0d687bd 1922 if (ah->cabq->txq_len >= ah->cabq->txq_max)
4e868796
FF		 1923 break;
1924
e0d687bd 1925 skb = ieee80211_get_buffered_bc(ah->hw, vif);
cec8db23
BC		 1926 }
1927
e0d687bd 1928 ah->bsent++;
fa1c114f
JS		 1929}
1930
9804b98d
BR		 1931/**
1932 * ath5k_beacon_update_timers - update beacon timers
1933 *
e0d687bd 1934 * @ah: struct ath5k_hw pointer we are operating on
9804b98d
BR		 1935 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1936 * beacon timer update based on the current HW TSF.
1937 *
1938 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1939 * of a received beacon or the current local hardware TSF and write it to the
1940 * beacon timer registers.
1941 *
1942 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 1943 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 1944 * when we otherwise know we have to update the timers, but we keep it in this
1945 * function to have it all together in one place.
1946 */
cd2c5486 1947void
e0d687bd 1948ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
fa1c114f 1949{
9804b98d
BR		 1950 u32 nexttbtt, intval, hw_tu, bc_tu;
1951 u64 hw_tsf;
fa1c114f 1952
e0d687bd
PR		 1953 intval = ah->bintval & AR5K_BEACON_PERIOD;
1954 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs > 1) {
b1ae1edf
BG		 1955 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1956 if (intval < 15)
e0d687bd 1957 ATH5K_WARN(ah, "intval %u is too low, min 15\n",
b1ae1edf
BG		 1958 intval);
1959 }
fa1c114f
JS		 1960 if (WARN_ON(!intval))
1961 return;
1962
9804b98d
BR		 1963 /* beacon TSF converted to TU */
1964 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 1965
9804b98d
BR		 1966 /* current TSF converted to TU */
1967 hw_tsf = ath5k_hw_get_tsf64(ah);
1968 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 1969
633d006e 1970#define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
11f21df3 1971 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
25985edc 1972 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
11f21df3
BR		 1973 * configuration we need to make sure it is bigger than that. */
1974
9804b98d
BR		 1975 if (bc_tsf == -1) {
1976 /*
1977 * no beacons received, called internally.
1978 * just need to refresh timers based on HW TSF.
1979 */
1980 nexttbtt = roundup(hw_tu + FUDGE, intval);
1981 } else if (bc_tsf == 0) {
1982 /*
1983 * no beacon received, probably called by ath5k_reset_tsf().
1984 * reset TSF to start with 0.
1985 */
1986 nexttbtt = intval;
1987 intval |= AR5K_BEACON_RESET_TSF;
1988 } else if (bc_tsf > hw_tsf) {
1989 /*
25985edc 1990 * beacon received, SW merge happened but HW TSF not yet updated.
9804b98d
BR		 1991 * not possible to reconfigure timers yet, but next time we
1992 * receive a beacon with the same BSSID, the hardware will
1993 * automatically update the TSF and then we need to reconfigure
1994 * the timers.
1995 */
e0d687bd 1996 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
9804b98d
BR		 1997 "need to wait for HW TSF sync\n");
1998 return;
1999 } else {
2000 /*
2001 * most important case for beacon synchronization between STA.
2002 *
2003 * beacon received and HW TSF has been already updated by HW.
2004 * update next TBTT based on the TSF of the beacon, but make
2005 * sure it is ahead of our local TSF timer.
2006 */
2007 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2008 }
2009#undef FUDGE
fa1c114f 2010
e0d687bd 2011 ah->nexttbtt = nexttbtt;
036cd1ec 2012
fa1c114f 2013 intval |= AR5K_BEACON_ENA;
fa1c114f 2014 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2015
2016 /*
2017 * debugging output last in order to preserve the time critical aspect
2018 * of this function
2019 */
2020 if (bc_tsf == -1)
e0d687bd 2021 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
9804b98d
BR		 2022 "reconfigured timers based on HW TSF\n");
2023 else if (bc_tsf == 0)
e0d687bd 2024 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
9804b98d
BR		 2025 "reset HW TSF and timers\n");
2026 else
e0d687bd 2027 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
9804b98d
BR		 2028 "updated timers based on beacon TSF\n");
2029
e0d687bd 2030 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2031 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2032 (unsigned long long) bc_tsf,
2033 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
e0d687bd 2034 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
9804b98d
BR		 2035 intval & AR5K_BEACON_PERIOD,
2036 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2037 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2038}
2039
036cd1ec
BR		 2040/**
2041 * ath5k_beacon_config - Configure the beacon queues and interrupts
2042 *
e0d687bd 2043 * @ah: struct ath5k_hw pointer we are operating on
fa1c114f 2044 *
036cd1ec 2045 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2046 * interrupts to detect TSF updates only.
fa1c114f 2047 */
cd2c5486 2048void
e0d687bd 2049ath5k_beacon_config(struct ath5k_hw *ah)
fa1c114f 2050{
b5f03956 2051 unsigned long flags;
fa1c114f 2052
e0d687bd
PR		 2053 spin_lock_irqsave(&ah->block, flags);
2054 ah->bmisscount = 0;
2055 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2056
e0d687bd 2057 if (ah->enable_beacon) {
fa1c114f 2058 /*
036cd1ec
BR		 2059 * In IBSS mode we use a self-linked tx descriptor and let the
2060 * hardware send the beacons automatically. We have to load it
fa1c114f 2061 * only once here.
036cd1ec 2062 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2063 * timers in order to detect automatic TSF updates.
fa1c114f 2064 */
e0d687bd 2065 ath5k_beaconq_config(ah);
fa1c114f 2066
e0d687bd 2067 ah->imask |= AR5K_INT_SWBA;
036cd1ec 2068
e0d687bd 2069 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2070 if (ath5k_hw_hasveol(ah))
e0d687bd 2071 ath5k_beacon_send(ah);
da966bca 2072 } else
e0d687bd 2073 ath5k_beacon_update_timers(ah, -1);
21800491 2074 } else {
e0d687bd 2075 ath5k_hw_stop_beacon_queue(ah, ah->bhalq);
fa1c114f 2076 }
fa1c114f 2077
e0d687bd 2078 ath5k_hw_set_imr(ah, ah->imask);
21800491 2079 mmiowb();
e0d687bd 2080 spin_unlock_irqrestore(&ah->block, flags);
fa1c114f
JS		 2081}
2082
428cbd4f
NK		 2083static void ath5k_tasklet_beacon(unsigned long data)
2084{
e0d687bd 2085 struct ath5k_hw *ah = (struct ath5k_hw *) data;
428cbd4f
NK		 2086
2087 /*
2088 * Software beacon alert--time to send a beacon.
2089 *
2090 * In IBSS mode we use this interrupt just to
2091 * keep track of the next TBTT (target beacon
6a2a0e73 2092 * transmission time) in order to detect whether
428cbd4f
NK		 2093 * automatic TSF updates happened.
2094 */
e0d687bd 2095 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
6a2a0e73 2096 /* XXX: only if VEOL supported */
e0d687bd
PR		 2097 u64 tsf = ath5k_hw_get_tsf64(ah);
2098 ah->nexttbtt += ah->bintval;
2099 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
428cbd4f
NK		 2100 "SWBA nexttbtt: %x hw_tu: %x "
2101 "TSF: %llx\n",
e0d687bd 2102 ah->nexttbtt,
428cbd4f
NK		 2103 TSF_TO_TU(tsf),
2104 (unsigned long long) tsf);
2105 } else {
e0d687bd
PR		 2106 spin_lock(&ah->block);
2107 ath5k_beacon_send(ah);
2108 spin_unlock(&ah->block);
428cbd4f
NK		 2109 }
2110}
2111
fa1c114f
JS		 2112
2113/********************\
2114* Interrupt handling *
2115\********************/
2116
6a8a3f6b
BR		 2117static void
2118ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2119{
2111ac0d
BR		 2120 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2121 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2122 /* run ANI only when full calibration is not active */
2123 ah->ah_cal_next_ani = jiffies +
2124 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
e0d687bd 2125 tasklet_schedule(&ah->ani_tasklet);
2111ac0d
BR		 2126
2127 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
6a8a3f6b
BR		 2128 ah->ah_cal_next_full = jiffies +
2129 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
e0d687bd 2130 tasklet_schedule(&ah->calib);
6a8a3f6b
BR		 2131 }
2132 /* we could use SWI to generate enough interrupts to meet our
2133 * calibration interval requirements, if necessary:
2134 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2135}
2136
c266c71a 2137static void
e0d687bd 2138ath5k_schedule_rx(struct ath5k_hw *ah)
c266c71a 2139{
e0d687bd
PR		 2140 ah->rx_pending = true;
2141 tasklet_schedule(&ah->rxtq);
c266c71a
FF		 2142}
2143
2144static void
e0d687bd 2145ath5k_schedule_tx(struct ath5k_hw *ah)
c266c71a 2146{
e0d687bd
PR		 2147 ah->tx_pending = true;
2148 tasklet_schedule(&ah->txtq);
c266c71a
FF		 2149}
2150
f5cbc8ba 2151static irqreturn_t
fa1c114f
JS		 2152ath5k_intr(int irq, void *dev_id)
2153{
e0d687bd 2154 struct ath5k_hw *ah = dev_id;
fa1c114f
JS		 2155 enum ath5k_int status;
2156 unsigned int counter = 1000;
2157
e0d687bd 2158 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
4cebb34c
FF		 2159 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2160 !ath5k_hw_is_intr_pending(ah))))
fa1c114f
JS		 2161 return IRQ_NONE;
2162
2163 do {
fa1c114f 2164 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
e0d687bd
PR		 2165 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2166 status, ah->imask);
fa1c114f
JS		 2167 if (unlikely(status & AR5K_INT_FATAL)) {
2168 /*
2169 * Fatal errors are unrecoverable.
2170 * Typically these are caused by DMA errors.
2171 */
e0d687bd 2172 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
8d67a031 2173 "fatal int, resetting\n");
e0d687bd 2174 ieee80211_queue_work(ah->hw, &ah->reset_work);
fa1c114f 2175 } else if (unlikely(status & AR5K_INT_RXORN)) {
87d77c4e
BR		 2176 /*
2177 * Receive buffers are full. Either the bus is busy or
2178 * the CPU is not fast enough to process all received
2179 * frames.
2180 * Older chipsets need a reset to come out of this
2181 * condition, but we treat it as RX for newer chips.
2182 * We don't know exactly which versions need a reset -
2183 * this guess is copied from the HAL.
2184 */
e0d687bd 2185 ah->stats.rxorn_intr++;
8d67a031 2186 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
e0d687bd 2187 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
8d67a031 2188 "rx overrun, resetting\n");
e0d687bd 2189 ieee80211_queue_work(ah->hw, &ah->reset_work);
d2c7f773 2190 } else
e0d687bd 2191 ath5k_schedule_rx(ah);
fa1c114f 2192 } else {
d2c7f773 2193 if (status & AR5K_INT_SWBA)
e0d687bd 2194 tasklet_hi_schedule(&ah->beacontq);
d2c7f773 2195
fa1c114f
JS		 2196 if (status & AR5K_INT_RXEOL) {
2197 /*
2198 * NB: the hardware should re-read the link when
2199 * RXE bit is written, but it doesn't work at
2200 * least on older hardware revs.
2201 */
e0d687bd 2202 ah->stats.rxeol_intr++;
fa1c114f
JS		 2203 }
2204 if (status & AR5K_INT_TXURN) {
2205 /* bump tx trigger level */
2206 ath5k_hw_update_tx_triglevel(ah, true);
2207 }
4c674c60 2208 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
e0d687bd 2209 ath5k_schedule_rx(ah);
4c674c60
NK		 2210 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2211 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
e0d687bd 2212 ath5k_schedule_tx(ah);
fa1c114f 2213 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2214 /* TODO */
fa1c114f
JS		 2215 }
2216 if (status & AR5K_INT_MIB) {
e0d687bd 2217 ah->stats.mib_intr++;
495391d7 2218 ath5k_hw_update_mib_counters(ah);
2111ac0d 2219 ath5k_ani_mib_intr(ah);
fa1c114f 2220 }
e6a3b616 2221 if (status & AR5K_INT_GPIO)
e0d687bd 2222 tasklet_schedule(&ah->rf_kill.toggleq);
a6ae0716 2223
fa1c114f 2224 }
4cebb34c
FF		 2225
2226 if (ath5k_get_bus_type(ah) == ATH_AHB)
2227 break;
2228
2516baa6 2229 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f 2230
e0d687bd
PR		 2231 if (ah->rx_pending || ah->tx_pending)
2232 ath5k_set_current_imask(ah);
c266c71a 2233
fa1c114f 2234 if (unlikely(!counter))
e0d687bd 2235 ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
fa1c114f 2236
6a8a3f6b 2237 ath5k_intr_calibration_poll(ah);
6e220662 2238
fa1c114f
JS		 2239 return IRQ_HANDLED;
2240}
2241
fa1c114f
JS		 2242/*
2243 * Periodically recalibrate the PHY to account
2244 * for temperature/environment changes.
2245 */
2246static void
6e220662 2247ath5k_tasklet_calibrate(unsigned long data)
fa1c114f 2248{
e0d687bd 2249 struct ath5k_hw *ah = (void *)data;
fa1c114f 2250
6e220662 2251 /* Only full calibration for now */
e65e1d77 2252 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
6e220662 2253
e0d687bd
PR		 2254 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2255 ieee80211_frequency_to_channel(ah->curchan->center_freq),
2256 ah->curchan->hw_value);
fa1c114f 2257
6f3b414a 2258 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2259 /*
2260 * Rfgain is out of bounds, reset the chip
2261 * to load new gain values.
2262 */
e0d687bd
PR		 2263 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2264 ieee80211_queue_work(ah->hw, &ah->reset_work);
fa1c114f 2265 }
e0d687bd
PR		 2266 if (ath5k_hw_phy_calibrate(ah, ah->curchan))
2267 ATH5K_ERR(ah, "calibration of channel %u failed\n",
400ec45a 2268 ieee80211_frequency_to_channel(
e0d687bd 2269 ah->curchan->center_freq));
fa1c114f 2270
0e8e02dd 2271 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
651d9375
BR		 2272 * doesn't.
2273 * TODO: We should stop TX here, so that it doesn't interfere.
2274 * Note that stopping the queues is not enough to stop TX! */
afe86286
BR		 2275 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2276 ah->ah_cal_next_nf = jiffies +
2277 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
afe86286 2278 ath5k_hw_update_noise_floor(ah);
afe86286 2279 }
6e220662 2280
e65e1d77 2281 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
fa1c114f
JS		 2282}
2283
2284
2111ac0d
BR		 2285static void
2286ath5k_tasklet_ani(unsigned long data)
2287{
e0d687bd 2288 struct ath5k_hw *ah = (void *)data;
2111ac0d
BR		 2289
2290 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2291 ath5k_ani_calibration(ah);
2292 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2293}
2294
2295
4edd761f
BR		 2296static void
2297ath5k_tx_complete_poll_work(struct work_struct *work)
2298{
e0d687bd 2299 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
4edd761f
BR		 2300 tx_complete_work.work);
2301 struct ath5k_txq *txq;
2302 int i;
2303 bool needreset = false;
2304
e0d687bd 2305 mutex_lock(&ah->lock);
599b13ad 2306
e0d687bd
PR		 2307 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
2308 if (ah->txqs[i].setup) {
2309 txq = &ah->txqs[i];
4edd761f 2310 spin_lock_bh(&txq->lock);
23413296 2311 if (txq->txq_len > 1) {
4edd761f 2312 if (txq->txq_poll_mark) {
e0d687bd 2313 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT,
4edd761f
BR		 2314 "TX queue stuck %d\n",
2315 txq->qnum);
2316 needreset = true;
923e5b3d 2317 txq->txq_stuck++;
4edd761f
BR		 2318 spin_unlock_bh(&txq->lock);
2319 break;
2320 } else {
2321 txq->txq_poll_mark = true;
2322 }
2323 }
2324 spin_unlock_bh(&txq->lock);
2325 }
2326 }
2327
2328 if (needreset) {
e0d687bd 2329 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
4edd761f 2330 "TX queues stuck, resetting\n");
e0d687bd 2331 ath5k_reset(ah, NULL, true);
4edd761f
BR		 2332 }
2333
e0d687bd 2334 mutex_unlock(&ah->lock);
599b13ad 2335
e0d687bd 2336 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
4edd761f
BR		 2337 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2338}
2339
2340
8a63facc
BC		 2341/*************************\
2342* Initialization routines *
2343\*************************/
fa1c114f 2344
25380d80 2345int __devinit
e0d687bd 2346ath5k_init_softc(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
132b1c3e 2347{
e0d687bd 2348 struct ieee80211_hw *hw = ah->hw;
132b1c3e
FF		 2349 struct ath_common *common;
2350 int ret;
2351 int csz;
2352
2353 /* Initialize driver private data */
e0d687bd 2354 SET_IEEE80211_DEV(hw, ah->dev);
132b1c3e 2355 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
b9e61f11
NK		 2356 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2357 IEEE80211_HW_SIGNAL_DBM |
2358 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
132b1c3e
FF		 2359
2360 hw->wiphy->interface_modes =
2361 BIT(NL80211_IFTYPE_AP) |
2362 BIT(NL80211_IFTYPE_STATION) |
2363 BIT(NL80211_IFTYPE_ADHOC) |
2364 BIT(NL80211_IFTYPE_MESH_POINT);
2365
3de135db
BR		 2366 /* both antennas can be configured as RX or TX */
2367 hw->wiphy->available_antennas_tx = 0x3;
2368 hw->wiphy->available_antennas_rx = 0x3;
2369
132b1c3e
FF		 2370 hw->extra_tx_headroom = 2;
2371 hw->channel_change_time = 5000;
2372
2373 /*
2374 * Mark the device as detached to avoid processing
2375 * interrupts until setup is complete.
2376 */
e0d687bd 2377 __set_bit(ATH_STAT_INVALID, ah->status);
132b1c3e 2378
e0d687bd
PR		 2379 ah->opmode = NL80211_IFTYPE_STATION;
2380 ah->bintval = 1000;
2381 mutex_init(&ah->lock);
2382 spin_lock_init(&ah->rxbuflock);
2383 spin_lock_init(&ah->txbuflock);
2384 spin_lock_init(&ah->block);
2385 spin_lock_init(&ah->irqlock);
132b1c3e
FF		 2386
2387 /* Setup interrupt handler */
e0d687bd 2388 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah);
132b1c3e 2389 if (ret) {
e0d687bd 2390 ATH5K_ERR(ah, "request_irq failed\n");
132b1c3e
FF		 2391 goto err;
2392 }
2393
e0d687bd 2394 common = ath5k_hw_common(ah);
132b1c3e
FF		 2395 common->ops = &ath5k_common_ops;
2396 common->bus_ops = bus_ops;
e0d687bd 2397 common->ah = ah;
132b1c3e 2398 common->hw = hw;
e0d687bd 2399 common->priv = ah;
26d16d23 2400 common->clockrate = 40;
132b1c3e
FF		 2401
2402 /*
2403 * Cache line size is used to size and align various
2404 * structures used to communicate with the hardware.
2405 */
2406 ath5k_read_cachesize(common, &csz);
2407 common->cachelsz = csz << 2; /* convert to bytes */
2408
2409 spin_lock_init(&common->cc_lock);
2410
2411 /* Initialize device */
e0d687bd 2412 ret = ath5k_hw_init(ah);
132b1c3e 2413 if (ret)
e0d687bd 2414 goto err_irq;
132b1c3e
FF		 2415
2416 /* set up multi-rate retry capabilities */
e0d687bd 2417 if (ah->ah_version == AR5K_AR5212) {
132b1c3e 2418 hw->max_rates = 4;
76a9f6fd
BR		 2419 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2420 AR5K_INIT_RETRY_LONG);
132b1c3e
FF		 2421 }
2422
2423 hw->vif_data_size = sizeof(struct ath5k_vif);
2424
2425 /* Finish private driver data initialization */
2426 ret = ath5k_init(hw);
2427 if (ret)
2428 goto err_ah;
2429
e0d687bd
PR		 2430 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2431 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev),
2432 ah->ah_mac_srev,
2433 ah->ah_phy_revision);
132b1c3e 2434
e0d687bd 2435 if (!ah->ah_single_chip) {
132b1c3e 2436 /* Single chip radio (!RF5111) */
e0d687bd
PR		 2437 if (ah->ah_radio_5ghz_revision &&
2438 !ah->ah_radio_2ghz_revision) {
132b1c3e
FF		 2439 /* No 5GHz support -> report 2GHz radio */
2440 if (!test_bit(AR5K_MODE_11A,
e0d687bd
PR		 2441 ah->ah_capabilities.cap_mode)) {
2442 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
132b1c3e 2443 ath5k_chip_name(AR5K_VERSION_RAD,
e0d687bd
PR		 2444 ah->ah_radio_5ghz_revision),
2445 ah->ah_radio_5ghz_revision);
132b1c3e 2446 /* No 2GHz support (5110 and some
6a2a0e73 2447 * 5GHz only cards) -> report 5GHz radio */
132b1c3e 2448 } else if (!test_bit(AR5K_MODE_11B,
e0d687bd
PR		 2449 ah->ah_capabilities.cap_mode)) {
2450 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
132b1c3e 2451 ath5k_chip_name(AR5K_VERSION_RAD,
e0d687bd
PR		 2452 ah->ah_radio_5ghz_revision),
2453 ah->ah_radio_5ghz_revision);
132b1c3e
FF		 2454 /* Multiband radio */
2455 } else {
e0d687bd 2456 ATH5K_INFO(ah, "RF%s multiband radio found"
132b1c3e
FF		 2457 " (0x%x)\n",
2458 ath5k_chip_name(AR5K_VERSION_RAD,
e0d687bd
PR		 2459 ah->ah_radio_5ghz_revision),
2460 ah->ah_radio_5ghz_revision);
132b1c3e
FF		 2461 }
2462 }
2463 /* Multi chip radio (RF5111 - RF2111) ->
2464 * report both 2GHz/5GHz radios */
e0d687bd
PR		 2465 else if (ah->ah_radio_5ghz_revision &&
2466 ah->ah_radio_2ghz_revision) {
2467 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
132b1c3e 2468 ath5k_chip_name(AR5K_VERSION_RAD,
e0d687bd
PR		 2469 ah->ah_radio_5ghz_revision),
2470 ah->ah_radio_5ghz_revision);
2471 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
132b1c3e 2472 ath5k_chip_name(AR5K_VERSION_RAD,
e0d687bd
PR		 2473 ah->ah_radio_2ghz_revision),
2474 ah->ah_radio_2ghz_revision);
132b1c3e
FF		 2475 }
2476 }
2477
e0d687bd 2478 ath5k_debug_init_device(ah);
132b1c3e
FF		 2479
2480 /* ready to process interrupts */
e0d687bd 2481 __clear_bit(ATH_STAT_INVALID, ah->status);
132b1c3e
FF		 2482
2483 return 0;
2484err_ah:
e0d687bd 2485 ath5k_hw_deinit(ah);
132b1c3e 2486err_irq:
e0d687bd 2487 free_irq(ah->irq, ah);
132b1c3e
FF		 2488err:
2489 return ret;
2490}
2491
fa1c114f 2492static int
e0d687bd 2493ath5k_stop_locked(struct ath5k_hw *ah)
cec8db23 2494{
cec8db23 2495
e0d687bd
PR		 2496 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n",
2497 test_bit(ATH_STAT_INVALID, ah->status));
8a63facc
BC		 2498
2499 /*
2500 * Shutdown the hardware and driver:
2501 * stop output from above
2502 * disable interrupts
2503 * turn off timers
2504 * turn off the radio
2505 * clear transmit machinery
2506 * clear receive machinery
2507 * drain and release tx queues
2508 * reclaim beacon resources
2509 * power down hardware
2510 *
2511 * Note that some of this work is not possible if the
2512 * hardware is gone (invalid).
2513 */
e0d687bd 2514 ieee80211_stop_queues(ah->hw);
8a63facc 2515
e0d687bd
PR		 2516 if (!test_bit(ATH_STAT_INVALID, ah->status)) {
2517 ath5k_led_off(ah);
8a63facc 2518 ath5k_hw_set_imr(ah, 0);
e0d687bd
PR		 2519 synchronize_irq(ah->irq);
2520 ath5k_rx_stop(ah);
80dac9ee 2521 ath5k_hw_dma_stop(ah);
e0d687bd 2522 ath5k_drain_tx_buffs(ah);
8a63facc
BC		 2523 ath5k_hw_phy_disable(ah);
2524 }
2525
2526 return 0;
cec8db23
BC		 2527}
2528
fabba048 2529int ath5k_start(struct ieee80211_hw *hw)
fa1c114f 2530{
fabba048 2531 struct ath5k_hw *ah = hw->priv;
8a63facc
BC		 2532 struct ath_common *common = ath5k_hw_common(ah);
2533 int ret, i;
fa1c114f 2534
e0d687bd 2535 mutex_lock(&ah->lock);
8a63facc 2536
e0d687bd 2537 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode);
fa1c114f 2538
fa1c114f 2539 /*
8a63facc
BC		 2540 * Stop anything previously setup. This is safe
2541 * no matter this is the first time through or not.
fa1c114f 2542 */
e0d687bd 2543 ath5k_stop_locked(ah);
fa1c114f 2544
8a63facc
BC		 2545 /*
2546 * The basic interface to setting the hardware in a good
2547 * state is ``reset''. On return the hardware is known to
2548 * be powered up and with interrupts disabled. This must
2549 * be followed by initialization of the appropriate bits
2550 * and then setup of the interrupt mask.
2551 */
e0d687bd
PR		 2552 ah->curchan = ah->hw->conf.channel;
2553 ah->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
8a63facc
BC		 2554 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2555 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
fa1c114f 2556
e0d687bd 2557 ret = ath5k_reset(ah, NULL, false);
8a63facc
BC		 2558 if (ret)
2559 goto done;
fa1c114f 2560
8a63facc
BC		 2561 ath5k_rfkill_hw_start(ah);
2562
2563 /*
2564 * Reset the key cache since some parts do not reset the
2565 * contents on initial power up or resume from suspend.
2566 */
2567 for (i = 0; i < common->keymax; i++)
2568 ath_hw_keyreset(common, (u16) i);
2569
61cde037
NK		 2570 /* Use higher rates for acks instead of base
2571 * rate */
2572 ah->ah_ack_bitrate_high = true;
b1ae1edf 2573
e0d687bd
PR		 2574 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++)
2575 ah->bslot[i] = NULL;
b1ae1edf 2576
8a63facc
BC		 2577 ret = 0;
2578done:
2579 mmiowb();
e0d687bd 2580 mutex_unlock(&ah->lock);
4edd761f 2581
e0d687bd 2582 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
4edd761f
BR		 2583 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2584
8a63facc
BC		 2585 return ret;
2586}
2587
e0d687bd 2588static void ath5k_stop_tasklets(struct ath5k_hw *ah)
8a63facc 2589{
e0d687bd
PR		 2590 ah->rx_pending = false;
2591 ah->tx_pending = false;
2592 tasklet_kill(&ah->rxtq);
2593 tasklet_kill(&ah->txtq);
2594 tasklet_kill(&ah->calib);
2595 tasklet_kill(&ah->beacontq);
2596 tasklet_kill(&ah->ani_tasklet);
8a63facc
BC		 2597}
2598
2599/*
2600 * Stop the device, grabbing the top-level lock to protect
2601 * against concurrent entry through ath5k_init (which can happen
2602 * if another thread does a system call and the thread doing the
2603 * stop is preempted).
2604 */
fabba048 2605void ath5k_stop(struct ieee80211_hw *hw)
8a63facc 2606{
fabba048 2607 struct ath5k_hw *ah = hw->priv;
8a63facc
BC		 2608 int ret;
2609
e0d687bd
PR		 2610 mutex_lock(&ah->lock);
2611 ret = ath5k_stop_locked(ah);
2612 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) {
8a63facc
BC		 2613 /*
2614 * Don't set the card in full sleep mode!
2615 *
2616 * a) When the device is in this state it must be carefully
2617 * woken up or references to registers in the PCI clock
2618 * domain may freeze the bus (and system). This varies
2619 * by chip and is mostly an issue with newer parts
2620 * (madwifi sources mentioned srev >= 0x78) that go to
2621 * sleep more quickly.
2622 *
2623 * b) On older chips full sleep results a weird behaviour
2624 * during wakeup. I tested various cards with srev < 0x78
2625 * and they don't wake up after module reload, a second
2626 * module reload is needed to bring the card up again.
2627 *
2628 * Until we figure out what's going on don't enable
2629 * full chip reset on any chip (this is what Legacy HAL
2630 * and Sam's HAL do anyway). Instead Perform a full reset
2631 * on the device (same as initial state after attach) and
2632 * leave it idle (keep MAC/BB on warm reset) */
e0d687bd 2633 ret = ath5k_hw_on_hold(ah);
8a63facc 2634
e0d687bd 2635 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
8a63facc 2636 "putting device to sleep\n");
fa1c114f
JS		 2637 }
2638
8a63facc 2639 mmiowb();
e0d687bd 2640 mutex_unlock(&ah->lock);
8a63facc 2641
e0d687bd 2642 ath5k_stop_tasklets(ah);
8a63facc 2643
e0d687bd 2644 cancel_delayed_work_sync(&ah->tx_complete_work);
4edd761f 2645
e0d687bd 2646 ath5k_rfkill_hw_stop(ah);
fa1c114f
JS		 2647}
2648
209d889b
BC		 2649/*
2650 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2651 * and change to the given channel.
5faaff74 2652 *
e0d687bd 2653 * This should be called with ah->lock.
209d889b 2654 */
fa1c114f 2655static int
e0d687bd 2656ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
8aec7af9 2657 bool skip_pcu)
fa1c114f 2658{
f15a4bb2 2659 struct ath_common *common = ath5k_hw_common(ah);
344b54b9 2660 int ret, ani_mode;
a99168ee 2661 bool fast;
fa1c114f 2662
e0d687bd 2663 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2664
450464de 2665 ath5k_hw_set_imr(ah, 0);
e0d687bd
PR		 2666 synchronize_irq(ah->irq);
2667 ath5k_stop_tasklets(ah);
450464de 2668
25985edc 2669 /* Save ani mode and disable ANI during
344b54b9
NK		 2670 * reset. If we don't we might get false
2671 * PHY error interrupts. */
e0d687bd 2672 ani_mode = ah->ani_state.ani_mode;
344b54b9
NK		 2673 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2674
19252ecb
NK		 2675 /* We are going to empty hw queues
2676 * so we should also free any remaining
2677 * tx buffers */
e0d687bd 2678 ath5k_drain_tx_buffs(ah);
930a7622 2679 if (chan)
e0d687bd 2680 ah->curchan = chan;
a99168ee
NK		 2681
2682 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
2683
e0d687bd 2684 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu);
d7dc1003 2685 if (ret) {
e0d687bd 2686 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret);
fa1c114f
JS		 2687 goto err;
2688 }
d7dc1003 2689
e0d687bd 2690 ret = ath5k_rx_start(ah);
d7dc1003 2691 if (ret) {
e0d687bd 2692 ATH5K_ERR(ah, "can't start recv logic\n");
fa1c114f
JS		 2693 goto err;
2694 }
d7dc1003 2695
344b54b9 2696 ath5k_ani_init(ah, ani_mode);
2111ac0d 2697
fe00deb3 2698 ah->ah_cal_next_full = jiffies + msecs_to_jiffies(100);
ac559526 2699 ah->ah_cal_next_ani = jiffies;
afe86286 2700 ah->ah_cal_next_nf = jiffies;
5dcc03fe 2701 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
afe86286 2702
f15a4bb2 2703 /* clear survey data and cycle counters */
e0d687bd 2704 memset(&ah->survey, 0, sizeof(ah->survey));
bb007554 2705 spin_lock_bh(&common->cc_lock);
f15a4bb2
BR		 2706 ath_hw_cycle_counters_update(common);
2707 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2708 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
bb007554 2709 spin_unlock_bh(&common->cc_lock);
f15a4bb2 2710
fa1c114f 2711 /*
d7dc1003
JS		 2712 * Change channels and update the h/w rate map if we're switching;
2713 * e.g. 11a to 11b/g.
2714 *
2715 * We may be doing a reset in response to an ioctl that changes the
2716 * channel so update any state that might change as a result.
fa1c114f
JS		 2717 *
2718 * XXX needed?
2719 */
e0d687bd 2720/* ath5k_chan_change(ah, c); */
fa1c114f 2721
e0d687bd 2722 ath5k_beacon_config(ah);
d7dc1003 2723 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 2724
e0d687bd 2725 ieee80211_wake_queues(ah->hw);
397f385b 2726
fa1c114f
JS		 2727 return 0;
2728err:
2729 return ret;
2730}
2731
5faaff74
BC		 2732static void ath5k_reset_work(struct work_struct *work)
2733{
e0d687bd 2734 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
5faaff74
BC		 2735 reset_work);
2736
e0d687bd
PR		 2737 mutex_lock(&ah->lock);
2738 ath5k_reset(ah, NULL, true);
2739 mutex_unlock(&ah->lock);
5faaff74
BC		 2740}
2741
25380d80 2742static int __devinit
132b1c3e 2743ath5k_init(struct ieee80211_hw *hw)
fa1c114f 2744{
132b1c3e 2745
e0d687bd 2746 struct ath5k_hw *ah = hw->priv;
8a63facc 2747 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
925e0b06 2748 struct ath5k_txq *txq;
8a63facc 2749 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2750 int ret;
2751
fa1c114f 2752
8a63facc
BC		 2753 /*
2754 * Check if the MAC has multi-rate retry support.
2755 * We do this by trying to setup a fake extended
2756 * descriptor. MACs that don't have support will
2757 * return false w/o doing anything. MACs that do
2758 * support it will return true w/o doing anything.
2759 */
2760 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
67d2e2df 2761
8a63facc
BC		 2762 if (ret < 0)
2763 goto err;
2764 if (ret > 0)
e0d687bd 2765 __set_bit(ATH_STAT_MRRETRY, ah->status);
ccfe5552 2766
8a63facc
BC		 2767 /*
2768 * Collect the channel list. The 802.11 layer
6a2a0e73 2769 * is responsible for filtering this list based
8a63facc
BC		 2770 * on settings like the phy mode and regulatory
2771 * domain restrictions.
2772 */
2773 ret = ath5k_setup_bands(hw);
2774 if (ret) {
e0d687bd 2775 ATH5K_ERR(ah, "can't get channels\n");
8a63facc
BC		 2776 goto err;
2777 }
67d2e2df 2778
8a63facc
BC		 2779 /*
2780 * Allocate tx+rx descriptors and populate the lists.
2781 */
e0d687bd 2782 ret = ath5k_desc_alloc(ah);
8a63facc 2783 if (ret) {
e0d687bd 2784 ATH5K_ERR(ah, "can't allocate descriptors\n");
8a63facc
BC		 2785 goto err;
2786 }
fa1c114f 2787
8a63facc
BC		 2788 /*
2789 * Allocate hardware transmit queues: one queue for
2790 * beacon frames and one data queue for each QoS
2791 * priority. Note that hw functions handle resetting
2792 * these queues at the needed time.
2793 */
2794 ret = ath5k_beaconq_setup(ah);
2795 if (ret < 0) {
e0d687bd 2796 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n");
8a63facc
BC		 2797 goto err_desc;
2798 }
e0d687bd
PR		 2799 ah->bhalq = ret;
2800 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0);
2801 if (IS_ERR(ah->cabq)) {
2802 ATH5K_ERR(ah, "can't setup cab queue\n");
2803 ret = PTR_ERR(ah->cabq);
8a63facc
BC		 2804 goto err_bhal;
2805 }
fa1c114f 2806
22d8d9f8
BR		 2807 /* 5211 and 5212 usually support 10 queues but we better rely on the
2808 * capability information */
2809 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2810 /* This order matches mac80211's queue priority, so we can
2811 * directly use the mac80211 queue number without any mapping */
e0d687bd 2812 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
22d8d9f8 2813 if (IS_ERR(txq)) {
e0d687bd 2814 ATH5K_ERR(ah, "can't setup xmit queue\n");
22d8d9f8
BR		 2815 ret = PTR_ERR(txq);
2816 goto err_queues;
2817 }
e0d687bd 2818 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
22d8d9f8 2819 if (IS_ERR(txq)) {
e0d687bd 2820 ATH5K_ERR(ah, "can't setup xmit queue\n");
22d8d9f8
BR		 2821 ret = PTR_ERR(txq);
2822 goto err_queues;
2823 }
e0d687bd 2824 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
22d8d9f8 2825 if (IS_ERR(txq)) {
e0d687bd 2826 ATH5K_ERR(ah, "can't setup xmit queue\n");
22d8d9f8
BR		 2827 ret = PTR_ERR(txq);
2828 goto err_queues;
2829 }
e0d687bd 2830 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
22d8d9f8 2831 if (IS_ERR(txq)) {
e0d687bd 2832 ATH5K_ERR(ah, "can't setup xmit queue\n");
22d8d9f8
BR		 2833 ret = PTR_ERR(txq);
2834 goto err_queues;
2835 }
2836 hw->queues = 4;
2837 } else {
2838 /* older hardware (5210) can only support one data queue */
e0d687bd 2839 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
22d8d9f8 2840 if (IS_ERR(txq)) {
e0d687bd 2841 ATH5K_ERR(ah, "can't setup xmit queue\n");
22d8d9f8
BR		 2842 ret = PTR_ERR(txq);
2843 goto err_queues;
2844 }
2845 hw->queues = 1;
2846 }
fa1c114f 2847
e0d687bd
PR		 2848 tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah);
2849 tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah);
2850 tasklet_init(&ah->calib, ath5k_tasklet_calibrate, (unsigned long)ah);
2851 tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah);
2852 tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah);
be009370 2853
e0d687bd
PR		 2854 INIT_WORK(&ah->reset_work, ath5k_reset_work);
2855 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work);
fa1c114f 2856
fa9bfd61 2857 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
8a63facc 2858 if (ret) {
e0d687bd 2859 ATH5K_ERR(ah, "unable to read address from EEPROM\n");
8a63facc 2860 goto err_queues;
e30eb4ab 2861 }
2bed03eb 2862
8a63facc 2863 SET_IEEE80211_PERM_ADDR(hw, mac);
e0d687bd 2864 memcpy(&ah->lladdr, mac, ETH_ALEN);
8a63facc 2865 /* All MAC address bits matter for ACKs */
e0d687bd 2866 ath5k_update_bssid_mask_and_opmode(ah, NULL);
8a63facc
BC		 2867
2868 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2869 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2870 if (ret) {
e0d687bd 2871 ATH5K_ERR(ah, "can't initialize regulatory system\n");
8a63facc
BC		 2872 goto err_queues;
2873 }
2874
2875 ret = ieee80211_register_hw(hw);
2876 if (ret) {
e0d687bd 2877 ATH5K_ERR(ah, "can't register ieee80211 hw\n");
8a63facc
BC		 2878 goto err_queues;
2879 }
2880
2881 if (!ath_is_world_regd(regulatory))
2882 regulatory_hint(hw->wiphy, regulatory->alpha2);
2883
e0d687bd 2884 ath5k_init_leds(ah);
8a63facc 2885
e0d687bd 2886 ath5k_sysfs_register(ah);
8a63facc
BC		 2887
2888 return 0;
2889err_queues:
e0d687bd 2890 ath5k_txq_release(ah);
8a63facc 2891err_bhal:
e0d687bd 2892 ath5k_hw_release_tx_queue(ah, ah->bhalq);
8a63facc 2893err_desc:
e0d687bd 2894 ath5k_desc_free(ah);
8a63facc
BC		 2895err:
2896 return ret;
2897}
2898
132b1c3e 2899void
e0d687bd 2900ath5k_deinit_softc(struct ath5k_hw *ah)
8a63facc 2901{
e0d687bd 2902 struct ieee80211_hw *hw = ah->hw;
8a63facc
BC		 2903
2904 /*
2905 * NB: the order of these is important:
2906 * o call the 802.11 layer before detaching ath5k_hw to
2907 * ensure callbacks into the driver to delete global
2908 * key cache entries can be handled
2909 * o reclaim the tx queue data structures after calling
2910 * the 802.11 layer as we'll get called back to reclaim
2911 * node state and potentially want to use them
2912 * o to cleanup the tx queues the hal is called, so detach
2913 * it last
2914 * XXX: ??? detach ath5k_hw ???
2915 * Other than that, it's straightforward...
2916 */
2917 ieee80211_unregister_hw(hw);
e0d687bd
PR		 2918 ath5k_desc_free(ah);
2919 ath5k_txq_release(ah);
2920 ath5k_hw_release_tx_queue(ah, ah->bhalq);
2921 ath5k_unregister_leds(ah);
8a63facc 2922
e0d687bd 2923 ath5k_sysfs_unregister(ah);
8a63facc
BC		 2924 /*
2925 * NB: can't reclaim these until after ieee80211_ifdetach
2926 * returns because we'll get called back to reclaim node
2927 * state and potentially want to use them.
2928 */
e0d687bd
PR		 2929 ath5k_hw_deinit(ah);
2930 free_irq(ah->irq, ah);
8a63facc
BC		 2931}
2932
cd2c5486 2933bool
e0d687bd 2934ath5k_any_vif_assoc(struct ath5k_hw *ah)
b1ae1edf 2935{
e4b0b32a 2936 struct ath5k_vif_iter_data iter_data;
b1ae1edf
BG		 2937 iter_data.hw_macaddr = NULL;
2938 iter_data.any_assoc = false;
2939 iter_data.need_set_hw_addr = false;
2940 iter_data.found_active = true;
2941
e0d687bd 2942 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
b1ae1edf
BG		 2943 &iter_data);
2944 return iter_data.any_assoc;
2945}
2946
cd2c5486 2947void
f5cbc8ba 2948ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
8a63facc 2949{
e0d687bd 2950 struct ath5k_hw *ah = hw->priv;
8a63facc
BC		 2951 u32 rfilt;
2952 rfilt = ath5k_hw_get_rx_filter(ah);
2953 if (enable)
2954 rfilt |= AR5K_RX_FILTER_BEACON;
2955 else
2956 rfilt &= ~AR5K_RX_FILTER_BEACON;
2957 ath5k_hw_set_rx_filter(ah, rfilt);
e0d687bd 2958 ah->filter_flags = rfilt;
8a63facc 2959}
Linux kernel - Deliverables
This page took 0.873862 seconds and 5 git commands to generate.