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ath5k: move checks and stats into new function
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / desc.c
CommitLineData
c6e387a2
NK		 1/*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20/******************************\
21 Hardware Descriptor Functions
22\******************************/
23
24#include "ath5k.h"
25#include "reg.h"
26#include "debug.h"
27#include "base.h"
28
29/*
30 * TX Descriptors
31 */
32
33/*
34 * Initialize the 2-word tx control descriptor on 5210/5211
35 */
36static int
37ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
8127fbdc
BP		 38 unsigned int pkt_len, unsigned int hdr_len, int padsize,
39 enum ath5k_pkt_type type,
c6e387a2
NK		 40 unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0,
41 unsigned int key_index, unsigned int antenna_mode, unsigned int flags,
42 unsigned int rtscts_rate, unsigned int rtscts_duration)
43{
44 u32 frame_type;
45 struct ath5k_hw_2w_tx_ctl *tx_ctl;
46 unsigned int frame_len;
47
48 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
49
50 /*
51 * Validate input
52 * - Zero retries don't make sense.
53 * - A zero rate will put the HW into a mode where it continously sends
54 * noise on the channel, so it is important to avoid this.
55 */
56 if (unlikely(tx_tries0 == 0)) {
57 ATH5K_ERR(ah->ah_sc, "zero retries\n");
58 WARN_ON(1);
59 return -EINVAL;
60 }
61 if (unlikely(tx_rate0 == 0)) {
62 ATH5K_ERR(ah->ah_sc, "zero rate\n");
63 WARN_ON(1);
64 return -EINVAL;
65 }
66
67 /* Clear descriptor */
68 memset(&desc->ud.ds_tx5210, 0, sizeof(struct ath5k_hw_5210_tx_desc));
69
70 /* Setup control descriptor */
71
72 /* Verify and set frame length */
73
74 /* remove padding we might have added before */
8127fbdc 75 frame_len = pkt_len - padsize + FCS_LEN;
c6e387a2
NK		 76
77 if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
78 return -EINVAL;
79
80 tx_ctl->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
81
82 /* Verify and set buffer length */
83
84 /* NB: beacon's BufLen must be a multiple of 4 bytes */
85 if (type == AR5K_PKT_TYPE_BEACON)
86 pkt_len = roundup(pkt_len, 4);
87
88 if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
89 return -EINVAL;
90
91 tx_ctl->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
92
93 /*
94 * Verify and set header length
95 * XXX: I only found that on 5210 code, does it work on 5211 ?
96 */
97 if (ah->ah_version == AR5K_AR5210) {
98 if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN)
99 return -EINVAL;
100 tx_ctl->tx_control_0 |=
101 AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN);
102 }
103
8127fbdc 104 /*Differences between 5210-5211*/
c6e387a2
NK		 105 if (ah->ah_version == AR5K_AR5210) {
106 switch (type) {
107 case AR5K_PKT_TYPE_BEACON:
108 case AR5K_PKT_TYPE_PROBE_RESP:
109 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
110 case AR5K_PKT_TYPE_PIFS:
111 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
112 default:
113 frame_type = type /*<< 2 ?*/;
114 }
115
116 tx_ctl->tx_control_0 |=
117 AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) |
118 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
119
120 } else {
121 tx_ctl->tx_control_0 |=
122 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
123 AR5K_REG_SM(antenna_mode,
124 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
125 tx_ctl->tx_control_1 |=
126 AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE);
127 }
128#define _TX_FLAGS(_c, _flag) \
129 if (flags & AR5K_TXDESC_##_flag) { \
130 tx_ctl->tx_control_##_c |= \
131 AR5K_2W_TX_DESC_CTL##_c##_##_flag; \
132 }
133
134 _TX_FLAGS(0, CLRDMASK);
135 _TX_FLAGS(0, VEOL);
136 _TX_FLAGS(0, INTREQ);
137 _TX_FLAGS(0, RTSENA);
138 _TX_FLAGS(1, NOACK);
139
140#undef _TX_FLAGS
141
142 /*
143 * WEP crap
144 */
145 if (key_index != AR5K_TXKEYIX_INVALID) {
146 tx_ctl->tx_control_0 |=
147 AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
148 tx_ctl->tx_control_1 |=
149 AR5K_REG_SM(key_index,
150 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
151 }
152
153 /*
154 * RTS/CTS Duration [5210 ?]
155 */
156 if ((ah->ah_version == AR5K_AR5210) &&
157 (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
158 tx_ctl->tx_control_1 |= rtscts_duration &
159 AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
160
161 return 0;
162}
163
164/*
165 * Initialize the 4-word tx control descriptor on 5212
166 */
167static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
168 struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len,
8127fbdc 169 int padsize,
c6e387a2
NK		 170 enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
171 unsigned int tx_tries0, unsigned int key_index,
172 unsigned int antenna_mode, unsigned int flags,
173 unsigned int rtscts_rate,
174 unsigned int rtscts_duration)
175{
176 struct ath5k_hw_4w_tx_ctl *tx_ctl;
177 unsigned int frame_len;
178
c6e387a2
NK		 179 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
180
181 /*
182 * Validate input
183 * - Zero retries don't make sense.
184 * - A zero rate will put the HW into a mode where it continously sends
185 * noise on the channel, so it is important to avoid this.
186 */
187 if (unlikely(tx_tries0 == 0)) {
188 ATH5K_ERR(ah->ah_sc, "zero retries\n");
189 WARN_ON(1);
190 return -EINVAL;
191 }
192 if (unlikely(tx_rate0 == 0)) {
193 ATH5K_ERR(ah->ah_sc, "zero rate\n");
194 WARN_ON(1);
195 return -EINVAL;
196 }
197
8f655dde
NK		 198 tx_power += ah->ah_txpower.txp_offset;
199 if (tx_power > AR5K_TUNE_MAX_TXPOWER)
200 tx_power = AR5K_TUNE_MAX_TXPOWER;
201
c6e387a2
NK		 202 /* Clear descriptor */
203 memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc));
204
205 /* Setup control descriptor */
206
207 /* Verify and set frame length */
208
209 /* remove padding we might have added before */
8127fbdc 210 frame_len = pkt_len - padsize + FCS_LEN;
c6e387a2
NK		 211
212 if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
213 return -EINVAL;
214
215 tx_ctl->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
216
217 /* Verify and set buffer length */
218
219 /* NB: beacon's BufLen must be a multiple of 4 bytes */
220 if (type == AR5K_PKT_TYPE_BEACON)
221 pkt_len = roundup(pkt_len, 4);
222
223 if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
224 return -EINVAL;
225
226 tx_ctl->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
227
228 tx_ctl->tx_control_0 |=
229 AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
230 AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
231 tx_ctl->tx_control_1 |= AR5K_REG_SM(type,
232 AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
e9f08381 233 tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0,
c6e387a2
NK		 234 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
235 tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
236
237#define _TX_FLAGS(_c, _flag) \
238 if (flags & AR5K_TXDESC_##_flag) { \
239 tx_ctl->tx_control_##_c |= \
240 AR5K_4W_TX_DESC_CTL##_c##_##_flag; \
241 }
242
243 _TX_FLAGS(0, CLRDMASK);
244 _TX_FLAGS(0, VEOL);
245 _TX_FLAGS(0, INTREQ);
246 _TX_FLAGS(0, RTSENA);
247 _TX_FLAGS(0, CTSENA);
248 _TX_FLAGS(1, NOACK);
249
250#undef _TX_FLAGS
251
252 /*
253 * WEP crap
254 */
255 if (key_index != AR5K_TXKEYIX_INVALID) {
256 tx_ctl->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
257 tx_ctl->tx_control_1 |= AR5K_REG_SM(key_index,
258 AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
259 }
260
261 /*
262 * RTS/CTS
263 */
264 if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
265 if ((flags & AR5K_TXDESC_RTSENA) &&
266 (flags & AR5K_TXDESC_CTSENA))
267 return -EINVAL;
268 tx_ctl->tx_control_2 |= rtscts_duration &
269 AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
270 tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
271 AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
272 }
273
274 return 0;
275}
276
277/*
278 * Initialize a 4-word multi rate retry tx control descriptor on 5212
279 */
280static int
281ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
282 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
283 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3)
284{
285 struct ath5k_hw_4w_tx_ctl *tx_ctl;
286
287 /*
288 * Rates can be 0 as long as the retry count is 0 too.
289 * A zero rate and nonzero retry count will put the HW into a mode where
290 * it continously sends noise on the channel, so it is important to
291 * avoid this.
292 */
293 if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) ||
294 (tx_rate2 == 0 && tx_tries2 != 0) ||
295 (tx_rate3 == 0 && tx_tries3 != 0))) {
296 ATH5K_ERR(ah->ah_sc, "zero rate\n");
297 WARN_ON(1);
298 return -EINVAL;
299 }
300
301 if (ah->ah_version == AR5K_AR5212) {
302 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
303
304#define _XTX_TRIES(_n) \
305 if (tx_tries##_n) { \
306 tx_ctl->tx_control_2 |= \
307 AR5K_REG_SM(tx_tries##_n, \
308 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n); \
309 tx_ctl->tx_control_3 |= \
310 AR5K_REG_SM(tx_rate##_n, \
311 AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n); \
312 }
313
314 _XTX_TRIES(1);
315 _XTX_TRIES(2);
316 _XTX_TRIES(3);
317
318#undef _XTX_TRIES
319
320 return 1;
321 }
322
323 return 0;
324}
325
2f7fe870
FF		 326/* no mrr support for cards older than 5212 */
327static int
328ath5k_hw_setup_no_mrr(struct ath5k_hw *ah, struct ath5k_desc *desc,
329 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
330 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3)
331{
332 return 0;
333}
334
c6e387a2
NK		 335/*
336 * Proccess the tx status descriptor on 5210/5211
337 */
338static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
339 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
340{
341 struct ath5k_hw_2w_tx_ctl *tx_ctl;
342 struct ath5k_hw_tx_status *tx_status;
343
c6e387a2
NK		 344 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
345 tx_status = &desc->ud.ds_tx5210.tx_stat;
346
347 /* No frame has been send or error */
348 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
349 return -EINPROGRESS;
350
351 /*
352 * Get descriptor status
353 */
354 ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
355 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
356 ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
357 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
358 ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
359 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
360 /*TODO: ts->ts_virtcol + test*/
361 ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
362 AR5K_DESC_TX_STATUS1_SEQ_NUM);
363 ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
364 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
365 ts->ts_antenna = 1;
366 ts->ts_status = 0;
2f7fe870 367 ts->ts_rate[0] = AR5K_REG_MS(tx_ctl->tx_control_0,
c6e387a2 368 AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
2f7fe870
FF		 369 ts->ts_retry[0] = ts->ts_longretry;
370 ts->ts_final_idx = 0;
c6e387a2
NK		 371
372 if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
373 if (tx_status->tx_status_0 &
374 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
375 ts->ts_status |= AR5K_TXERR_XRETRY;
376
377 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
378 ts->ts_status |= AR5K_TXERR_FIFO;
379
380 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
381 ts->ts_status |= AR5K_TXERR_FILT;
382 }
383
384 return 0;
385}
386
387/*
388 * Proccess a tx status descriptor on 5212
389 */
390static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
391 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
392{
393 struct ath5k_hw_4w_tx_ctl *tx_ctl;
394 struct ath5k_hw_tx_status *tx_status;
395
c6e387a2
NK		 396 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
397 tx_status = &desc->ud.ds_tx5212.tx_stat;
398
399 /* No frame has been send or error */
400 if (unlikely(!(tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE)))
401 return -EINPROGRESS;
402
403 /*
404 * Get descriptor status
405 */
406 ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
407 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
408 ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
409 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
410 ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
411 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
412 ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
413 AR5K_DESC_TX_STATUS1_SEQ_NUM);
414 ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
415 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
416 ts->ts_antenna = (tx_status->tx_status_1 &
417 AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
418 ts->ts_status = 0;
419
2f7fe870
FF		 420 ts->ts_final_idx = AR5K_REG_MS(tx_status->tx_status_1,
421 AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX);
422
423 /* The longretry counter has the number of un-acked retries
424 * for the final rate. To get the total number of retries
425 * we have to add the retry counters for the other rates
426 * as well
427 */
428 ts->ts_retry[ts->ts_final_idx] = ts->ts_longretry;
429 switch (ts->ts_final_idx) {
430 case 3:
431 ts->ts_rate[3] = AR5K_REG_MS(tx_ctl->tx_control_3,
432 AR5K_4W_TX_DESC_CTL3_XMIT_RATE3);
433
434 ts->ts_retry[2] = AR5K_REG_MS(tx_ctl->tx_control_2,
435 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2);
436 ts->ts_longretry += ts->ts_retry[2];
437 /* fall through */
438 case 2:
439 ts->ts_rate[2] = AR5K_REG_MS(tx_ctl->tx_control_3,
440 AR5K_4W_TX_DESC_CTL3_XMIT_RATE2);
441
442 ts->ts_retry[1] = AR5K_REG_MS(tx_ctl->tx_control_2,
443 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
444 ts->ts_longretry += ts->ts_retry[1];
445 /* fall through */
c6e387a2 446 case 1:
2f7fe870 447 ts->ts_rate[1] = AR5K_REG_MS(tx_ctl->tx_control_3,
c6e387a2 448 AR5K_4W_TX_DESC_CTL3_XMIT_RATE1);
2f7fe870
FF		 449
450 ts->ts_retry[0] = AR5K_REG_MS(tx_ctl->tx_control_2,
c6e387a2 451 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
2f7fe870
FF		 452 ts->ts_longretry += ts->ts_retry[0];
453 /* fall through */
454 case 0:
455 ts->ts_rate[0] = tx_ctl->tx_control_3 &
456 AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
c6e387a2
NK		 457 break;
458 }
459
460 /* TX error */
461 if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
462 if (tx_status->tx_status_0 &
463 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
464 ts->ts_status |= AR5K_TXERR_XRETRY;
465
466 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
467 ts->ts_status |= AR5K_TXERR_FIFO;
468
469 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
470 ts->ts_status |= AR5K_TXERR_FILT;
471 }
472
473 return 0;
474}
475
476/*
477 * RX Descriptors
478 */
479
480/*
481 * Initialize an rx control descriptor
482 */
483static int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
484 u32 size, unsigned int flags)
485{
486 struct ath5k_hw_rx_ctl *rx_ctl;
487
c6e387a2
NK		 488 rx_ctl = &desc->ud.ds_rx.rx_ctl;
489
490 /*
491 * Clear the descriptor
492 * If we don't clean the status descriptor,
493 * while scanning we get too many results,
494 * most of them virtual, after some secs
495 * of scanning system hangs. M.F.
496 */
497 memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc));
498
499 /* Setup descriptor */
500 rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
501 if (unlikely(rx_ctl->rx_control_1 != size))
502 return -EINVAL;
503
504 if (flags & AR5K_RXDESC_INTREQ)
505 rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
506
507 return 0;
508}
509
510/*
511 * Proccess the rx status descriptor on 5210/5211
512 */
513static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
514 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
515{
516 struct ath5k_hw_rx_status *rx_status;
517
518 rx_status = &desc->ud.ds_rx.u.rx_stat;
519
520 /* No frame received / not ready */
521 if (unlikely(!(rx_status->rx_status_1 &
522 AR5K_5210_RX_DESC_STATUS1_DONE)))
523 return -EINPROGRESS;
524
525 /*
526 * Frame receive status
527 */
528 rs->rs_datalen = rx_status->rx_status_0 &
529 AR5K_5210_RX_DESC_STATUS0_DATA_LEN;
530 rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
531 AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL);
532 rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
533 AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE);
c7930339
BC		 534 rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
535 AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA);
536 rs->rs_more = !!(rx_status->rx_status_0 &
537 AR5K_5210_RX_DESC_STATUS0_MORE);
c6e387a2
NK		 538 /* TODO: this timestamp is 13 bit, later on we assume 15 bit */
539 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
540 AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
541 rs->rs_status = 0;
542 rs->rs_phyerr = 0;
543
544 /*
545 * Key table status
546 */
547 if (rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID)
548 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
549 AR5K_5210_RX_DESC_STATUS1_KEY_INDEX);
550 else
551 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
552
553 /*
554 * Receive/descriptor errors
555 */
556 if (!(rx_status->rx_status_1 &
557 AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
558 if (rx_status->rx_status_1 &
559 AR5K_5210_RX_DESC_STATUS1_CRC_ERROR)
560 rs->rs_status |= AR5K_RXERR_CRC;
561
562 if (rx_status->rx_status_1 &
563 AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN)
564 rs->rs_status |= AR5K_RXERR_FIFO;
565
566 if (rx_status->rx_status_1 &
567 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) {
568 rs->rs_status |= AR5K_RXERR_PHY;
569 rs->rs_phyerr |= AR5K_REG_MS(rx_status->rx_status_1,
570 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR);
571 }
572
573 if (rx_status->rx_status_1 &
574 AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
575 rs->rs_status |= AR5K_RXERR_DECRYPT;
576 }
577
578 return 0;
579}
580
581/*
582 * Proccess the rx status descriptor on 5212
583 */
584static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
585 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
586{
587 struct ath5k_hw_rx_status *rx_status;
588 struct ath5k_hw_rx_error *rx_err;
589
c6e387a2
NK		 590 rx_status = &desc->ud.ds_rx.u.rx_stat;
591
592 /* Overlay on error */
593 rx_err = &desc->ud.ds_rx.u.rx_err;
594
595 /* No frame received / not ready */
596 if (unlikely(!(rx_status->rx_status_1 &
597 AR5K_5212_RX_DESC_STATUS1_DONE)))
598 return -EINPROGRESS;
599
600 /*
601 * Frame receive status
602 */
603 rs->rs_datalen = rx_status->rx_status_0 &
604 AR5K_5212_RX_DESC_STATUS0_DATA_LEN;
605 rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
606 AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL);
607 rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
608 AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE);
c7930339
BC		 609 rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
610 AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA);
611 rs->rs_more = !!(rx_status->rx_status_0 &
612 AR5K_5212_RX_DESC_STATUS0_MORE);
c6e387a2
NK		 613 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
614 AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
615 rs->rs_status = 0;
616 rs->rs_phyerr = 0;
617
618 /*
619 * Key table status
620 */
621 if (rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID)
622 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
623 AR5K_5212_RX_DESC_STATUS1_KEY_INDEX);
624 else
625 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
626
627 /*
628 * Receive/descriptor errors
629 */
630 if (!(rx_status->rx_status_1 &
631 AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
632 if (rx_status->rx_status_1 &
633 AR5K_5212_RX_DESC_STATUS1_CRC_ERROR)
634 rs->rs_status |= AR5K_RXERR_CRC;
635
636 if (rx_status->rx_status_1 &
637 AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) {
638 rs->rs_status |= AR5K_RXERR_PHY;
639 rs->rs_phyerr |= AR5K_REG_MS(rx_err->rx_error_1,
640 AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE);
2111ac0d 641 ath5k_ani_phy_error_report(ah, rs->rs_phyerr);
c6e387a2
NK		 642 }
643
644 if (rx_status->rx_status_1 &
645 AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
646 rs->rs_status |= AR5K_RXERR_DECRYPT;
647
648 if (rx_status->rx_status_1 &
649 AR5K_5212_RX_DESC_STATUS1_MIC_ERROR)
650 rs->rs_status |= AR5K_RXERR_MIC;
651 }
652
653 return 0;
654}
655
656/*
657 * Init function pointers inside ath5k_hw struct
658 */
659int ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
660{
661
662 if (ah->ah_version != AR5K_AR5210 &&
663 ah->ah_version != AR5K_AR5211 &&
664 ah->ah_version != AR5K_AR5212)
665 return -ENOTSUPP;
666
c6e387a2
NK		 667 if (ah->ah_version == AR5K_AR5212) {
668 ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc;
669 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
670 ah->ah_setup_mrr_tx_desc = ath5k_hw_setup_mrr_tx_desc;
671 ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
672 } else {
673 ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc;
674 ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
2f7fe870 675 ah->ah_setup_mrr_tx_desc = ath5k_hw_setup_no_mrr;
c6e387a2
NK		 676 ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
677 }
678
679 if (ah->ah_version == AR5K_AR5212)
680 ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status;
681 else if (ah->ah_version <= AR5K_AR5211)
682 ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status;
683
684 return 0;
685}
686
Linux kernel - Deliverables
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