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c6e387a2 NK |
1 | /* |
2 | * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> | |
3 | * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> | |
4 | * | |
5 | * Permission to use, copy, modify, and distribute this software for any | |
6 | * purpose with or without fee is hereby granted, provided that the above | |
7 | * copyright notice and this permission notice appear in all copies. | |
8 | * | |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
16 | * | |
17 | */ | |
18 | ||
19 | /*************************************\ | |
20 | * DMA and interrupt masking functions * | |
21 | \*************************************/ | |
22 | ||
23 | /* | |
24 | * dma.c - DMA and interrupt masking functions | |
25 | * | |
26 | * Here we setup descriptor pointers (rxdp/txdp) start/stop dma engine and | |
27 | * handle queue setup for 5210 chipset (rest are handled on qcu.c). | |
6a2a0e73 | 28 | * Also we setup interrupt mask register (IMR) and read the various interrupt |
c6e387a2 NK |
29 | * status registers (ISR). |
30 | * | |
31 | * TODO: Handle SISR on 5211+ and introduce a function to return the queue | |
32 | * number that resulted the interrupt. | |
33 | */ | |
34 | ||
35 | #include "ath5k.h" | |
36 | #include "reg.h" | |
37 | #include "debug.h" | |
c6e387a2 | 38 | |
9320b5c4 | 39 | |
c6e387a2 NK |
40 | /*********\ |
41 | * Receive * | |
42 | \*********/ | |
43 | ||
44 | /** | |
45 | * ath5k_hw_start_rx_dma - Start DMA receive | |
46 | * | |
47 | * @ah: The &struct ath5k_hw | |
48 | */ | |
49 | void ath5k_hw_start_rx_dma(struct ath5k_hw *ah) | |
50 | { | |
c6e387a2 NK |
51 | ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR); |
52 | ath5k_hw_reg_read(ah, AR5K_CR); | |
53 | } | |
54 | ||
55 | /** | |
56 | * ath5k_hw_stop_rx_dma - Stop DMA receive | |
57 | * | |
58 | * @ah: The &struct ath5k_hw | |
59 | */ | |
14fae2d4 | 60 | static int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah) |
c6e387a2 NK |
61 | { |
62 | unsigned int i; | |
63 | ||
c6e387a2 NK |
64 | ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR); |
65 | ||
66 | /* | |
67 | * It may take some time to disable the DMA receive unit | |
68 | */ | |
509a106e | 69 | for (i = 1000; i > 0 && |
c6e387a2 NK |
70 | (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0; |
71 | i--) | |
b3a28e68 NK |
72 | udelay(100); |
73 | ||
f0e134a5 | 74 | if (!i) |
e0d687bd | 75 | ATH5K_DBG(ah, ATH5K_DEBUG_DMA, |
b3a28e68 | 76 | "failed to stop RX DMA !\n"); |
c6e387a2 NK |
77 | |
78 | return i ? 0 : -EBUSY; | |
79 | } | |
80 | ||
81 | /** | |
82 | * ath5k_hw_get_rxdp - Get RX Descriptor's address | |
83 | * | |
84 | * @ah: The &struct ath5k_hw | |
c6e387a2 NK |
85 | */ |
86 | u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah) | |
87 | { | |
88 | return ath5k_hw_reg_read(ah, AR5K_RXDP); | |
89 | } | |
90 | ||
91 | /** | |
92 | * ath5k_hw_set_rxdp - Set RX Descriptor's address | |
93 | * | |
94 | * @ah: The &struct ath5k_hw | |
95 | * @phys_addr: RX descriptor address | |
96 | * | |
e8325ed8 | 97 | * Returns -EIO if rx is active |
c6e387a2 | 98 | */ |
e8325ed8 | 99 | int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr) |
c6e387a2 | 100 | { |
e8325ed8 | 101 | if (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) { |
e0d687bd | 102 | ATH5K_DBG(ah, ATH5K_DEBUG_DMA, |
e8325ed8 NK |
103 | "tried to set RXDP while rx was active !\n"); |
104 | return -EIO; | |
105 | } | |
106 | ||
c6e387a2 | 107 | ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP); |
e8325ed8 | 108 | return 0; |
c6e387a2 NK |
109 | } |
110 | ||
111 | ||
112 | /**********\ | |
113 | * Transmit * | |
114 | \**********/ | |
115 | ||
116 | /** | |
117 | * ath5k_hw_start_tx_dma - Start DMA transmit for a specific queue | |
118 | * | |
119 | * @ah: The &struct ath5k_hw | |
120 | * @queue: The hw queue number | |
121 | * | |
122 | * Start DMA transmit for a specific queue and since 5210 doesn't have | |
123 | * QCU/DCU, set up queue parameters for 5210 here based on queue type (one | |
124 | * queue for normal data and one queue for beacons). For queue setup | |
125 | * on newer chips check out qcu.c. Returns -EINVAL if queue number is out | |
126 | * of range or if queue is already disabled. | |
127 | * | |
128 | * NOTE: Must be called after setting up tx control descriptor for that | |
129 | * queue (see below). | |
130 | */ | |
131 | int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue) | |
132 | { | |
133 | u32 tx_queue; | |
134 | ||
c6e387a2 NK |
135 | AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); |
136 | ||
137 | /* Return if queue is declared inactive */ | |
138 | if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) | |
d41174fa | 139 | return -EINVAL; |
c6e387a2 NK |
140 | |
141 | if (ah->ah_version == AR5K_AR5210) { | |
142 | tx_queue = ath5k_hw_reg_read(ah, AR5K_CR); | |
143 | ||
144 | /* | |
145 | * Set the queue by type on 5210 | |
146 | */ | |
147 | switch (ah->ah_txq[queue].tqi_type) { | |
148 | case AR5K_TX_QUEUE_DATA: | |
149 | tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0; | |
150 | break; | |
151 | case AR5K_TX_QUEUE_BEACON: | |
152 | tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; | |
153 | ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE, | |
154 | AR5K_BSR); | |
155 | break; | |
156 | case AR5K_TX_QUEUE_CAB: | |
157 | tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1; | |
158 | ath5k_hw_reg_write(ah, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V | | |
159 | AR5K_BCR_BDMAE, AR5K_BSR); | |
160 | break; | |
161 | default: | |
162 | return -EINVAL; | |
163 | } | |
164 | /* Start queue */ | |
165 | ath5k_hw_reg_write(ah, tx_queue, AR5K_CR); | |
166 | ath5k_hw_reg_read(ah, AR5K_CR); | |
167 | } else { | |
168 | /* Return if queue is disabled */ | |
169 | if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue)) | |
170 | return -EIO; | |
171 | ||
172 | /* Start queue */ | |
173 | AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue); | |
174 | } | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
179 | /** | |
180 | * ath5k_hw_stop_tx_dma - Stop DMA transmit on a specific queue | |
181 | * | |
182 | * @ah: The &struct ath5k_hw | |
183 | * @queue: The hw queue number | |
184 | * | |
185 | * Stop DMA transmit on a specific hw queue and drain queue so we don't | |
186 | * have any pending frames. Returns -EBUSY if we still have pending frames, | |
d41174fa | 187 | * -EINVAL if queue number is out of range or inactive. |
c6e387a2 | 188 | * |
c6e387a2 | 189 | */ |
14fae2d4 | 190 | static int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue) |
c6e387a2 | 191 | { |
509a106e | 192 | unsigned int i = 40; |
c6e387a2 NK |
193 | u32 tx_queue, pending; |
194 | ||
c6e387a2 NK |
195 | AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); |
196 | ||
197 | /* Return if queue is declared inactive */ | |
198 | if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE) | |
d41174fa | 199 | return -EINVAL; |
c6e387a2 NK |
200 | |
201 | if (ah->ah_version == AR5K_AR5210) { | |
202 | tx_queue = ath5k_hw_reg_read(ah, AR5K_CR); | |
203 | ||
204 | /* | |
205 | * Set by queue type | |
206 | */ | |
207 | switch (ah->ah_txq[queue].tqi_type) { | |
208 | case AR5K_TX_QUEUE_DATA: | |
209 | tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0; | |
210 | break; | |
211 | case AR5K_TX_QUEUE_BEACON: | |
212 | case AR5K_TX_QUEUE_CAB: | |
213 | /* XXX Fix me... */ | |
214 | tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1; | |
215 | ath5k_hw_reg_write(ah, 0, AR5K_BSR); | |
216 | break; | |
217 | default: | |
218 | return -EINVAL; | |
219 | } | |
220 | ||
221 | /* Stop queue */ | |
222 | ath5k_hw_reg_write(ah, tx_queue, AR5K_CR); | |
223 | ath5k_hw_reg_read(ah, AR5K_CR); | |
224 | } else { | |
f7317ba2 NK |
225 | |
226 | /* | |
227 | * Enable DCU early termination to quickly | |
228 | * flush any pending frames from QCU | |
229 | */ | |
230 | AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue), | |
231 | AR5K_QCU_MISC_DCU_EARLY); | |
232 | ||
c6e387a2 NK |
233 | /* |
234 | * Schedule TX disable and wait until queue is empty | |
235 | */ | |
236 | AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue); | |
237 | ||
b3a28e68 NK |
238 | /* Wait for queue to stop */ |
239 | for (i = 1000; i > 0 && | |
240 | (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue) != 0); | |
241 | i--) | |
242 | udelay(100); | |
243 | ||
244 | if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue)) | |
e0d687bd | 245 | ATH5K_DBG(ah, ATH5K_DEBUG_DMA, |
b3a28e68 NK |
246 | "queue %i didn't stop !\n", queue); |
247 | ||
248 | /* Check for pending frames */ | |
249 | i = 1000; | |
c6e387a2 NK |
250 | do { |
251 | pending = ath5k_hw_reg_read(ah, | |
252 | AR5K_QUEUE_STATUS(queue)) & | |
253 | AR5K_QCU_STS_FRMPENDCNT; | |
254 | udelay(100); | |
255 | } while (--i && pending); | |
256 | ||
509a106e NK |
257 | /* For 2413+ order PCU to drop packets using |
258 | * QUIET mechanism */ | |
259 | if (ah->ah_mac_version >= (AR5K_SREV_AR2414 >> 4) && | |
e4bbf2f5 | 260 | pending) { |
509a106e NK |
261 | /* Set periodicity and duration */ |
262 | ath5k_hw_reg_write(ah, | |
263 | AR5K_REG_SM(100, AR5K_QUIET_CTL2_QT_PER)| | |
264 | AR5K_REG_SM(10, AR5K_QUIET_CTL2_QT_DUR), | |
265 | AR5K_QUIET_CTL2); | |
266 | ||
267 | /* Enable quiet period for current TSF */ | |
268 | ath5k_hw_reg_write(ah, | |
269 | AR5K_QUIET_CTL1_QT_EN | | |
270 | AR5K_REG_SM(ath5k_hw_reg_read(ah, | |
271 | AR5K_TSF_L32_5211) >> 10, | |
272 | AR5K_QUIET_CTL1_NEXT_QT_TSF), | |
273 | AR5K_QUIET_CTL1); | |
274 | ||
275 | /* Force channel idle high */ | |
276 | AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211, | |
eada7cad | 277 | AR5K_DIAG_SW_CHANNEL_IDLE_HIGH); |
509a106e NK |
278 | |
279 | /* Wait a while and disable mechanism */ | |
b3a28e68 | 280 | udelay(400); |
509a106e NK |
281 | AR5K_REG_DISABLE_BITS(ah, AR5K_QUIET_CTL1, |
282 | AR5K_QUIET_CTL1_QT_EN); | |
283 | ||
284 | /* Re-check for pending frames */ | |
b3a28e68 | 285 | i = 100; |
509a106e NK |
286 | do { |
287 | pending = ath5k_hw_reg_read(ah, | |
288 | AR5K_QUEUE_STATUS(queue)) & | |
289 | AR5K_QCU_STS_FRMPENDCNT; | |
290 | udelay(100); | |
291 | } while (--i && pending); | |
292 | ||
293 | AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5211, | |
eada7cad | 294 | AR5K_DIAG_SW_CHANNEL_IDLE_HIGH); |
b3a28e68 NK |
295 | |
296 | if (pending) | |
e0d687bd | 297 | ATH5K_DBG(ah, ATH5K_DEBUG_DMA, |
b3a28e68 NK |
298 | "quiet mechanism didn't work q:%i !\n", |
299 | queue); | |
509a106e NK |
300 | } |
301 | ||
f7317ba2 NK |
302 | /* |
303 | * Disable DCU early termination | |
304 | */ | |
305 | AR5K_REG_DISABLE_BITS(ah, AR5K_QUEUE_MISC(queue), | |
306 | AR5K_QCU_MISC_DCU_EARLY); | |
307 | ||
c6e387a2 NK |
308 | /* Clear register */ |
309 | ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD); | |
b3a28e68 | 310 | if (pending) { |
e0d687bd | 311 | ATH5K_DBG(ah, ATH5K_DEBUG_DMA, |
b3a28e68 NK |
312 | "tx dma didn't stop (q:%i, frm:%i) !\n", |
313 | queue, pending); | |
c6e387a2 | 314 | return -EBUSY; |
b3a28e68 | 315 | } |
c6e387a2 NK |
316 | } |
317 | ||
509a106e | 318 | /* TODO: Check for success on 5210 else return error */ |
c6e387a2 NK |
319 | return 0; |
320 | } | |
321 | ||
14fae2d4 NK |
322 | /** |
323 | * ath5k_hw_stop_beacon_queue - Stop beacon queue | |
324 | * | |
325 | * @ah The &struct ath5k_hw | |
326 | * @queue The queue number | |
327 | * | |
328 | * Returns -EIO if queue didn't stop | |
329 | */ | |
330 | int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue) | |
331 | { | |
332 | int ret; | |
333 | ret = ath5k_hw_stop_tx_dma(ah, queue); | |
334 | if (ret) { | |
e0d687bd | 335 | ATH5K_DBG(ah, ATH5K_DEBUG_DMA, |
14fae2d4 NK |
336 | "beacon queue didn't stop !\n"); |
337 | return -EIO; | |
338 | } | |
339 | return 0; | |
340 | } | |
341 | ||
c6e387a2 NK |
342 | /** |
343 | * ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue | |
344 | * | |
345 | * @ah: The &struct ath5k_hw | |
346 | * @queue: The hw queue number | |
347 | * | |
348 | * Get TX descriptor's address for a specific queue. For 5210 we ignore | |
349 | * the queue number and use tx queue type since we only have 2 queues. | |
350 | * We use TXDP0 for normal data queue and TXDP1 for beacon queue. | |
351 | * For newer chips with QCU/DCU we just read the corresponding TXDP register. | |
352 | * | |
353 | * XXX: Is TXDP read and clear ? | |
354 | */ | |
355 | u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue) | |
356 | { | |
357 | u16 tx_reg; | |
358 | ||
c6e387a2 NK |
359 | AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); |
360 | ||
361 | /* | |
362 | * Get the transmit queue descriptor pointer from the selected queue | |
363 | */ | |
364 | /*5210 doesn't have QCU*/ | |
365 | if (ah->ah_version == AR5K_AR5210) { | |
366 | switch (ah->ah_txq[queue].tqi_type) { | |
367 | case AR5K_TX_QUEUE_DATA: | |
368 | tx_reg = AR5K_NOQCU_TXDP0; | |
369 | break; | |
370 | case AR5K_TX_QUEUE_BEACON: | |
371 | case AR5K_TX_QUEUE_CAB: | |
372 | tx_reg = AR5K_NOQCU_TXDP1; | |
373 | break; | |
374 | default: | |
375 | return 0xffffffff; | |
376 | } | |
377 | } else { | |
378 | tx_reg = AR5K_QUEUE_TXDP(queue); | |
379 | } | |
380 | ||
381 | return ath5k_hw_reg_read(ah, tx_reg); | |
382 | } | |
383 | ||
384 | /** | |
385 | * ath5k_hw_set_txdp - Set TX Descriptor's address for a specific queue | |
386 | * | |
387 | * @ah: The &struct ath5k_hw | |
388 | * @queue: The hw queue number | |
389 | * | |
390 | * Set TX descriptor's address for a specific queue. For 5210 we ignore | |
391 | * the queue number and we use tx queue type since we only have 2 queues | |
392 | * so as above we use TXDP0 for normal data queue and TXDP1 for beacon queue. | |
393 | * For newer chips with QCU/DCU we just set the corresponding TXDP register. | |
394 | * Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still | |
395 | * active. | |
396 | */ | |
397 | int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr) | |
398 | { | |
399 | u16 tx_reg; | |
400 | ||
c6e387a2 NK |
401 | AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num); |
402 | ||
403 | /* | |
404 | * Set the transmit queue descriptor pointer register by type | |
405 | * on 5210 | |
406 | */ | |
407 | if (ah->ah_version == AR5K_AR5210) { | |
408 | switch (ah->ah_txq[queue].tqi_type) { | |
409 | case AR5K_TX_QUEUE_DATA: | |
410 | tx_reg = AR5K_NOQCU_TXDP0; | |
411 | break; | |
412 | case AR5K_TX_QUEUE_BEACON: | |
413 | case AR5K_TX_QUEUE_CAB: | |
414 | tx_reg = AR5K_NOQCU_TXDP1; | |
415 | break; | |
416 | default: | |
417 | return -EINVAL; | |
418 | } | |
419 | } else { | |
420 | /* | |
421 | * Set the transmit queue descriptor pointer for | |
422 | * the selected queue on QCU for 5211+ | |
423 | * (this won't work if the queue is still active) | |
424 | */ | |
425 | if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue)) | |
426 | return -EIO; | |
427 | ||
428 | tx_reg = AR5K_QUEUE_TXDP(queue); | |
429 | } | |
430 | ||
431 | /* Set descriptor pointer */ | |
432 | ath5k_hw_reg_write(ah, phys_addr, tx_reg); | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
437 | /** | |
438 | * ath5k_hw_update_tx_triglevel - Update tx trigger level | |
439 | * | |
440 | * @ah: The &struct ath5k_hw | |
441 | * @increase: Flag to force increase of trigger level | |
442 | * | |
443 | * This function increases/decreases the tx trigger level for the tx fifo | |
444 | * buffer (aka FIFO threshold) that is used to indicate when PCU flushes | |
a180a130 | 445 | * the buffer and transmits its data. Lowering this results sending small |
c6e387a2 NK |
446 | * frames more quickly but can lead to tx underruns, raising it a lot can |
447 | * result other problems (i think bmiss is related). Right now we start with | |
448 | * the lowest possible (64Bytes) and if we get tx underrun we increase it using | |
a180a130 | 449 | * the increase flag. Returns -EIO if we have reached maximum/minimum. |
c6e387a2 NK |
450 | * |
451 | * XXX: Link this with tx DMA size ? | |
452 | * XXX: Use it to save interrupts ? | |
453 | * TODO: Needs testing, i think it's related to bmiss... | |
454 | */ | |
455 | int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase) | |
456 | { | |
457 | u32 trigger_level, imr; | |
458 | int ret = -EIO; | |
459 | ||
c6e387a2 NK |
460 | /* |
461 | * Disable interrupts by setting the mask | |
462 | */ | |
463 | imr = ath5k_hw_set_imr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL); | |
464 | ||
465 | trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG), | |
466 | AR5K_TXCFG_TXFULL); | |
467 | ||
468 | if (!increase) { | |
469 | if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES) | |
470 | goto done; | |
471 | } else | |
472 | trigger_level += | |
473 | ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2); | |
474 | ||
475 | /* | |
476 | * Update trigger level on success | |
477 | */ | |
478 | if (ah->ah_version == AR5K_AR5210) | |
479 | ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL); | |
480 | else | |
481 | AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, | |
482 | AR5K_TXCFG_TXFULL, trigger_level); | |
483 | ||
484 | ret = 0; | |
485 | ||
486 | done: | |
487 | /* | |
488 | * Restore interrupt mask | |
489 | */ | |
490 | ath5k_hw_set_imr(ah, imr); | |
491 | ||
492 | return ret; | |
493 | } | |
494 | ||
9320b5c4 | 495 | |
c6e387a2 NK |
496 | /*******************\ |
497 | * Interrupt masking * | |
498 | \*******************/ | |
499 | ||
500 | /** | |
501 | * ath5k_hw_is_intr_pending - Check if we have pending interrupts | |
502 | * | |
503 | * @ah: The &struct ath5k_hw | |
504 | * | |
505 | * Check if we have pending interrupts to process. Returns 1 if we | |
506 | * have pending interrupts and 0 if we haven't. | |
507 | */ | |
508 | bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah) | |
509 | { | |
509a106e | 510 | return ath5k_hw_reg_read(ah, AR5K_INTPEND) == 1 ? 1 : 0; |
c6e387a2 NK |
511 | } |
512 | ||
513 | /** | |
514 | * ath5k_hw_get_isr - Get interrupt status | |
515 | * | |
516 | * @ah: The @struct ath5k_hw | |
517 | * @interrupt_mask: Driver's interrupt mask used to filter out | |
518 | * interrupts in sw. | |
519 | * | |
520 | * This function is used inside our interrupt handler to determine the reason | |
521 | * for the interrupt by reading Primary Interrupt Status Register. Returns an | |
522 | * abstract interrupt status mask which is mostly ISR with some uncommon bits | |
523 | * being mapped on some standard non hw-specific positions | |
524 | * (check out &ath5k_int). | |
525 | * | |
526 | * NOTE: We use read-and-clear register, so after this function is called ISR | |
527 | * is zeroed. | |
c6e387a2 NK |
528 | */ |
529 | int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask) | |
530 | { | |
531 | u32 data; | |
532 | ||
c6e387a2 NK |
533 | /* |
534 | * Read interrupt status from the Interrupt Status register | |
535 | * on 5210 | |
536 | */ | |
537 | if (ah->ah_version == AR5K_AR5210) { | |
538 | data = ath5k_hw_reg_read(ah, AR5K_ISR); | |
539 | if (unlikely(data == AR5K_INT_NOCARD)) { | |
540 | *interrupt_mask = data; | |
541 | return -ENODEV; | |
542 | } | |
543 | } else { | |
544 | /* | |
4c674c60 NK |
545 | * Read interrupt status from Interrupt |
546 | * Status Register shadow copy (Read And Clear) | |
547 | * | |
c6e387a2 NK |
548 | * Note: PISR/SISR Not available on 5210 |
549 | */ | |
550 | data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR); | |
4c674c60 NK |
551 | if (unlikely(data == AR5K_INT_NOCARD)) { |
552 | *interrupt_mask = data; | |
553 | return -ENODEV; | |
554 | } | |
c6e387a2 NK |
555 | } |
556 | ||
557 | /* | |
558 | * Get abstract interrupt mask (driver-compatible) | |
559 | */ | |
560 | *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr; | |
561 | ||
c6e387a2 | 562 | if (ah->ah_version != AR5K_AR5210) { |
4c674c60 NK |
563 | u32 sisr2 = ath5k_hw_reg_read(ah, AR5K_RAC_SISR2); |
564 | ||
c6e387a2 NK |
565 | /*HIU = Host Interface Unit (PCI etc)*/ |
566 | if (unlikely(data & (AR5K_ISR_HIUERR))) | |
567 | *interrupt_mask |= AR5K_INT_FATAL; | |
568 | ||
569 | /*Beacon Not Ready*/ | |
570 | if (unlikely(data & (AR5K_ISR_BNR))) | |
571 | *interrupt_mask |= AR5K_INT_BNR; | |
c6e387a2 | 572 | |
4c674c60 NK |
573 | if (unlikely(sisr2 & (AR5K_SISR2_SSERR | |
574 | AR5K_SISR2_DPERR | | |
575 | AR5K_SISR2_MCABT))) | |
576 | *interrupt_mask |= AR5K_INT_FATAL; | |
577 | ||
578 | if (data & AR5K_ISR_TIM) | |
579 | *interrupt_mask |= AR5K_INT_TIM; | |
580 | ||
581 | if (data & AR5K_ISR_BCNMISC) { | |
582 | if (sisr2 & AR5K_SISR2_TIM) | |
583 | *interrupt_mask |= AR5K_INT_TIM; | |
584 | if (sisr2 & AR5K_SISR2_DTIM) | |
585 | *interrupt_mask |= AR5K_INT_DTIM; | |
586 | if (sisr2 & AR5K_SISR2_DTIM_SYNC) | |
587 | *interrupt_mask |= AR5K_INT_DTIM_SYNC; | |
588 | if (sisr2 & AR5K_SISR2_BCN_TIMEOUT) | |
589 | *interrupt_mask |= AR5K_INT_BCN_TIMEOUT; | |
590 | if (sisr2 & AR5K_SISR2_CAB_TIMEOUT) | |
591 | *interrupt_mask |= AR5K_INT_CAB_TIMEOUT; | |
592 | } | |
593 | ||
594 | if (data & AR5K_ISR_RXDOPPLER) | |
595 | *interrupt_mask |= AR5K_INT_RX_DOPPLER; | |
596 | if (data & AR5K_ISR_QCBRORN) { | |
597 | *interrupt_mask |= AR5K_INT_QCBRORN; | |
598 | ah->ah_txq_isr |= AR5K_REG_MS( | |
599 | ath5k_hw_reg_read(ah, AR5K_RAC_SISR3), | |
600 | AR5K_SISR3_QCBRORN); | |
601 | } | |
602 | if (data & AR5K_ISR_QCBRURN) { | |
603 | *interrupt_mask |= AR5K_INT_QCBRURN; | |
604 | ah->ah_txq_isr |= AR5K_REG_MS( | |
605 | ath5k_hw_reg_read(ah, AR5K_RAC_SISR3), | |
606 | AR5K_SISR3_QCBRURN); | |
607 | } | |
608 | if (data & AR5K_ISR_QTRIG) { | |
609 | *interrupt_mask |= AR5K_INT_QTRIG; | |
610 | ah->ah_txq_isr |= AR5K_REG_MS( | |
611 | ath5k_hw_reg_read(ah, AR5K_RAC_SISR4), | |
612 | AR5K_SISR4_QTRIG); | |
613 | } | |
614 | ||
615 | if (data & AR5K_ISR_TXOK) | |
616 | ah->ah_txq_isr |= AR5K_REG_MS( | |
617 | ath5k_hw_reg_read(ah, AR5K_RAC_SISR0), | |
618 | AR5K_SISR0_QCU_TXOK); | |
619 | ||
620 | if (data & AR5K_ISR_TXDESC) | |
621 | ah->ah_txq_isr |= AR5K_REG_MS( | |
622 | ath5k_hw_reg_read(ah, AR5K_RAC_SISR0), | |
623 | AR5K_SISR0_QCU_TXDESC); | |
624 | ||
625 | if (data & AR5K_ISR_TXERR) | |
626 | ah->ah_txq_isr |= AR5K_REG_MS( | |
627 | ath5k_hw_reg_read(ah, AR5K_RAC_SISR1), | |
628 | AR5K_SISR1_QCU_TXERR); | |
629 | ||
630 | if (data & AR5K_ISR_TXEOL) | |
631 | ah->ah_txq_isr |= AR5K_REG_MS( | |
632 | ath5k_hw_reg_read(ah, AR5K_RAC_SISR1), | |
633 | AR5K_SISR1_QCU_TXEOL); | |
634 | ||
635 | if (data & AR5K_ISR_TXURN) | |
636 | ah->ah_txq_isr |= AR5K_REG_MS( | |
637 | ath5k_hw_reg_read(ah, AR5K_RAC_SISR2), | |
638 | AR5K_SISR2_QCU_TXURN); | |
639 | } else { | |
640 | if (unlikely(data & (AR5K_ISR_SSERR | AR5K_ISR_MCABT | |
641 | | AR5K_ISR_HIUERR | AR5K_ISR_DPERR))) | |
642 | *interrupt_mask |= AR5K_INT_FATAL; | |
643 | ||
644 | /* | |
645 | * XXX: BMISS interrupts may occur after association. | |
646 | * I found this on 5210 code but it needs testing. If this is | |
647 | * true we should disable them before assoc and re-enable them | |
73ac36ea | 648 | * after a successful assoc + some jiffies. |
4c674c60 NK |
649 | interrupt_mask &= ~AR5K_INT_BMISS; |
650 | */ | |
651 | } | |
c6e387a2 NK |
652 | |
653 | /* | |
654 | * In case we didn't handle anything, | |
655 | * print the register value. | |
656 | */ | |
657 | if (unlikely(*interrupt_mask == 0 && net_ratelimit())) | |
4c674c60 | 658 | ATH5K_PRINTF("ISR: 0x%08x IMR: 0x%08x\n", data, ah->ah_imr); |
c6e387a2 NK |
659 | |
660 | return 0; | |
661 | } | |
662 | ||
663 | /** | |
664 | * ath5k_hw_set_imr - Set interrupt mask | |
665 | * | |
666 | * @ah: The &struct ath5k_hw | |
667 | * @new_mask: The new interrupt mask to be set | |
668 | * | |
669 | * Set the interrupt mask in hw to save interrupts. We do that by mapping | |
670 | * ath5k_int bits to hw-specific bits to remove abstraction and writing | |
671 | * Interrupt Mask Register. | |
672 | */ | |
673 | enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask) | |
674 | { | |
675 | enum ath5k_int old_mask, int_mask; | |
676 | ||
4c674c60 NK |
677 | old_mask = ah->ah_imr; |
678 | ||
c6e387a2 NK |
679 | /* |
680 | * Disable card interrupts to prevent any race conditions | |
4c674c60 NK |
681 | * (they will be re-enabled afterwards if AR5K_INT GLOBAL |
682 | * is set again on the new mask). | |
c6e387a2 | 683 | */ |
4c674c60 NK |
684 | if (old_mask & AR5K_INT_GLOBAL) { |
685 | ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER); | |
686 | ath5k_hw_reg_read(ah, AR5K_IER); | |
687 | } | |
c6e387a2 NK |
688 | |
689 | /* | |
690 | * Add additional, chipset-dependent interrupt mask flags | |
691 | * and write them to the IMR (interrupt mask register). | |
692 | */ | |
693 | int_mask = new_mask & AR5K_INT_COMMON; | |
694 | ||
c6e387a2 | 695 | if (ah->ah_version != AR5K_AR5210) { |
4c674c60 NK |
696 | /* Preserve per queue TXURN interrupt mask */ |
697 | u32 simr2 = ath5k_hw_reg_read(ah, AR5K_SIMR2) | |
698 | & AR5K_SIMR2_QCU_TXURN; | |
699 | ||
c6e387a2 NK |
700 | if (new_mask & AR5K_INT_FATAL) { |
701 | int_mask |= AR5K_IMR_HIUERR; | |
4c674c60 NK |
702 | simr2 |= (AR5K_SIMR2_MCABT | AR5K_SIMR2_SSERR |
703 | | AR5K_SIMR2_DPERR); | |
c6e387a2 | 704 | } |
4c674c60 NK |
705 | |
706 | /*Beacon Not Ready*/ | |
707 | if (new_mask & AR5K_INT_BNR) | |
708 | int_mask |= AR5K_INT_BNR; | |
709 | ||
710 | if (new_mask & AR5K_INT_TIM) | |
711 | int_mask |= AR5K_IMR_TIM; | |
712 | ||
713 | if (new_mask & AR5K_INT_TIM) | |
714 | simr2 |= AR5K_SISR2_TIM; | |
715 | if (new_mask & AR5K_INT_DTIM) | |
716 | simr2 |= AR5K_SISR2_DTIM; | |
717 | if (new_mask & AR5K_INT_DTIM_SYNC) | |
718 | simr2 |= AR5K_SISR2_DTIM_SYNC; | |
719 | if (new_mask & AR5K_INT_BCN_TIMEOUT) | |
720 | simr2 |= AR5K_SISR2_BCN_TIMEOUT; | |
721 | if (new_mask & AR5K_INT_CAB_TIMEOUT) | |
722 | simr2 |= AR5K_SISR2_CAB_TIMEOUT; | |
723 | ||
724 | if (new_mask & AR5K_INT_RX_DOPPLER) | |
725 | int_mask |= AR5K_IMR_RXDOPPLER; | |
726 | ||
727 | /* Note: Per queue interrupt masks | |
6a2a0e73 | 728 | * are set via ath5k_hw_reset_tx_queue() (qcu.c) */ |
4c674c60 NK |
729 | ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR); |
730 | ath5k_hw_reg_write(ah, simr2, AR5K_SIMR2); | |
731 | ||
732 | } else { | |
733 | if (new_mask & AR5K_INT_FATAL) | |
734 | int_mask |= (AR5K_IMR_SSERR | AR5K_IMR_MCABT | |
735 | | AR5K_IMR_HIUERR | AR5K_IMR_DPERR); | |
736 | ||
737 | ath5k_hw_reg_write(ah, int_mask, AR5K_IMR); | |
c6e387a2 NK |
738 | } |
739 | ||
4c674c60 NK |
740 | /* If RXNOFRM interrupt is masked disable it |
741 | * by setting AR5K_RXNOFRM to zero */ | |
742 | if (!(new_mask & AR5K_INT_RXNOFRM)) | |
743 | ath5k_hw_reg_write(ah, 0, AR5K_RXNOFRM); | |
c6e387a2 NK |
744 | |
745 | /* Store new interrupt mask */ | |
746 | ah->ah_imr = new_mask; | |
747 | ||
4c674c60 NK |
748 | /* ..re-enable interrupts if AR5K_INT_GLOBAL is set */ |
749 | if (new_mask & AR5K_INT_GLOBAL) { | |
750 | ath5k_hw_reg_write(ah, AR5K_IER_ENABLE, AR5K_IER); | |
751 | ath5k_hw_reg_read(ah, AR5K_IER); | |
752 | } | |
c6e387a2 NK |
753 | |
754 | return old_mask; | |
755 | } | |
756 | ||
9320b5c4 NK |
757 | |
758 | /********************\ | |
759 | Init/Stop functions | |
760 | \********************/ | |
761 | ||
762 | /** | |
763 | * ath5k_hw_dma_init - Initialize DMA unit | |
764 | * | |
765 | * @ah: The &struct ath5k_hw | |
766 | * | |
767 | * Set DMA size and pre-enable interrupts | |
768 | * (driver handles tx/rx buffer setup and | |
769 | * dma start/stop) | |
770 | * | |
771 | * XXX: Save/restore RXDP/TXDP registers ? | |
772 | */ | |
773 | void ath5k_hw_dma_init(struct ath5k_hw *ah) | |
774 | { | |
775 | /* | |
776 | * Set Rx/Tx DMA Configuration | |
777 | * | |
778 | * Set standard DMA size (128). Note that | |
779 | * a DMA size of 512 causes rx overruns and tx errors | |
780 | * on pci-e cards (tested on 5424 but since rx overruns | |
781 | * also occur on 5416/5418 with madwifi we set 128 | |
782 | * for all PCI-E cards to be safe). | |
783 | * | |
784 | * XXX: need to check 5210 for this | |
6a2a0e73 | 785 | * TODO: Check out tx trigger level, it's always 64 on dumps but I |
9320b5c4 NK |
786 | * guess we can tweak it and see how it goes ;-) |
787 | */ | |
788 | if (ah->ah_version != AR5K_AR5210) { | |
789 | AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, | |
790 | AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B); | |
791 | AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG, | |
792 | AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B); | |
793 | } | |
794 | ||
795 | /* Pre-enable interrupts on 5211/5212*/ | |
796 | if (ah->ah_version != AR5K_AR5210) | |
797 | ath5k_hw_set_imr(ah, ah->ah_imr); | |
798 | ||
799 | } | |
d41174fa NK |
800 | |
801 | /** | |
802 | * ath5k_hw_dma_stop - stop DMA unit | |
803 | * | |
804 | * @ah: The &struct ath5k_hw | |
805 | * | |
806 | * Stop tx/rx DMA and interrupts. Returns | |
807 | * -EBUSY if tx or rx dma failed to stop. | |
808 | * | |
809 | * XXX: Sometimes DMA unit hangs and we have | |
810 | * stuck frames on tx queues, only a reset | |
811 | * can fix that. | |
812 | */ | |
813 | int ath5k_hw_dma_stop(struct ath5k_hw *ah) | |
814 | { | |
815 | int i, qmax, err; | |
816 | err = 0; | |
817 | ||
818 | /* Disable interrupts */ | |
819 | ath5k_hw_set_imr(ah, 0); | |
820 | ||
821 | /* Stop rx dma */ | |
822 | err = ath5k_hw_stop_rx_dma(ah); | |
823 | if (err) | |
824 | return err; | |
825 | ||
826 | /* Clear any pending interrupts | |
827 | * and disable tx dma */ | |
828 | if (ah->ah_version != AR5K_AR5210) { | |
829 | ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR); | |
830 | qmax = AR5K_NUM_TX_QUEUES; | |
831 | } else { | |
832 | /* PISR/SISR Not available on 5210 */ | |
833 | ath5k_hw_reg_read(ah, AR5K_ISR); | |
834 | qmax = AR5K_NUM_TX_QUEUES_NOQCU; | |
835 | } | |
836 | ||
837 | for (i = 0; i < qmax; i++) { | |
838 | err = ath5k_hw_stop_tx_dma(ah, i); | |
839 | /* -EINVAL -> queue inactive */ | |
15411c27 | 840 | if (err && err != -EINVAL) |
d41174fa NK |
841 | return err; |
842 | } | |
843 | ||
15411c27 | 844 | return 0; |
d41174fa | 845 | } |