Commit | Line | Data |
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fa1c114f JS |
1 | /* |
2 | * Initial register settings functions | |
3 | * | |
c6e387a2 | 4 | * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> |
a406c139 | 5 | * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com> |
c6e387a2 | 6 | * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com> |
fa1c114f JS |
7 | * |
8 | * Permission to use, copy, modify, and distribute this software for any | |
9 | * purpose with or without fee is hereby granted, provided that the above | |
10 | * copyright notice and this permission notice appear in all copies. | |
11 | * | |
12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
13 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
14 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
15 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
16 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
17 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
18 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
19 | * | |
20 | */ | |
21 | ||
22 | #include "ath5k.h" | |
fa1c114f | 23 | #include "reg.h" |
c6e387a2 NK |
24 | #include "debug.h" |
25 | #include "base.h" | |
fa1c114f JS |
26 | |
27 | /* | |
28 | * Mode-independent initial register writes | |
29 | */ | |
30 | ||
31 | struct ath5k_ini { | |
32 | u16 ini_register; | |
33 | u32 ini_value; | |
34 | ||
35 | enum { | |
36 | AR5K_INI_WRITE = 0, /* Default */ | |
37 | AR5K_INI_READ = 1, /* Cleared on read */ | |
38 | } ini_mode; | |
39 | }; | |
40 | ||
41 | /* | |
42 | * Mode specific initial register values | |
43 | */ | |
44 | ||
45 | struct ath5k_ini_mode { | |
46 | u16 mode_register; | |
47 | u32 mode_value[5]; | |
48 | }; | |
49 | ||
50 | /* Initial register settings for AR5210 */ | |
51 | static const struct ath5k_ini ar5210_ini[] = { | |
52 | /* PCU and MAC registers */ | |
53 | { AR5K_NOQCU_TXDP0, 0 }, | |
54 | { AR5K_NOQCU_TXDP1, 0 }, | |
55 | { AR5K_RXDP, 0 }, | |
56 | { AR5K_CR, 0 }, | |
57 | { AR5K_ISR, 0, AR5K_INI_READ }, | |
58 | { AR5K_IMR, 0 }, | |
59 | { AR5K_IER, AR5K_IER_DISABLE }, | |
60 | { AR5K_BSR, 0, AR5K_INI_READ }, | |
61 | { AR5K_TXCFG, AR5K_DMASIZE_128B }, | |
62 | { AR5K_RXCFG, AR5K_DMASIZE_128B }, | |
63 | { AR5K_CFG, AR5K_INIT_CFG }, | |
c6e387a2 NK |
64 | { AR5K_TOPS, 8 }, |
65 | { AR5K_RXNOFRM, 8 }, | |
66 | { AR5K_RPGTO, 0 }, | |
67 | { AR5K_TXNOFRM, 0 }, | |
fa1c114f JS |
68 | { AR5K_SFR, 0 }, |
69 | { AR5K_MIBC, 0 }, | |
70 | { AR5K_MISC, 0 }, | |
71 | { AR5K_RX_FILTER_5210, 0 }, | |
72 | { AR5K_MCAST_FILTER0_5210, 0 }, | |
73 | { AR5K_MCAST_FILTER1_5210, 0 }, | |
74 | { AR5K_TX_MASK0, 0 }, | |
75 | { AR5K_TX_MASK1, 0 }, | |
76 | { AR5K_CLR_TMASK, 0 }, | |
77 | { AR5K_TRIG_LVL, AR5K_TUNE_MIN_TX_FIFO_THRES }, | |
78 | { AR5K_DIAG_SW_5210, 0 }, | |
79 | { AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES }, | |
80 | { AR5K_TSF_L32_5210, 0 }, | |
81 | { AR5K_TIMER0_5210, 0 }, | |
82 | { AR5K_TIMER1_5210, 0xffffffff }, | |
83 | { AR5K_TIMER2_5210, 0xffffffff }, | |
84 | { AR5K_TIMER3_5210, 1 }, | |
85 | { AR5K_CFP_DUR_5210, 0 }, | |
86 | { AR5K_CFP_PERIOD_5210, 0 }, | |
87 | /* PHY registers */ | |
88 | { AR5K_PHY(0), 0x00000047 }, | |
89 | { AR5K_PHY_AGC, 0x00000000 }, | |
90 | { AR5K_PHY(3), 0x09848ea6 }, | |
91 | { AR5K_PHY(4), 0x3d32e000 }, | |
92 | { AR5K_PHY(5), 0x0000076b }, | |
93 | { AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE }, | |
94 | { AR5K_PHY(8), 0x02020200 }, | |
95 | { AR5K_PHY(9), 0x00000e0e }, | |
96 | { AR5K_PHY(10), 0x0a020201 }, | |
97 | { AR5K_PHY(11), 0x00036ffc }, | |
98 | { AR5K_PHY(12), 0x00000000 }, | |
99 | { AR5K_PHY(13), 0x00000e0e }, | |
100 | { AR5K_PHY(14), 0x00000007 }, | |
101 | { AR5K_PHY(15), 0x00020100 }, | |
102 | { AR5K_PHY(16), 0x89630000 }, | |
103 | { AR5K_PHY(17), 0x1372169c }, | |
104 | { AR5K_PHY(18), 0x0018b633 }, | |
105 | { AR5K_PHY(19), 0x1284613c }, | |
106 | { AR5K_PHY(20), 0x0de8b8e0 }, | |
107 | { AR5K_PHY(21), 0x00074859 }, | |
108 | { AR5K_PHY(22), 0x7e80beba }, | |
109 | { AR5K_PHY(23), 0x313a665e }, | |
110 | { AR5K_PHY_AGCCTL, 0x00001d08 }, | |
111 | { AR5K_PHY(25), 0x0001ce00 }, | |
112 | { AR5K_PHY(26), 0x409a4190 }, | |
113 | { AR5K_PHY(28), 0x0000000f }, | |
114 | { AR5K_PHY(29), 0x00000080 }, | |
115 | { AR5K_PHY(30), 0x00000004 }, | |
116 | { AR5K_PHY(31), 0x00000018 }, /* 0x987c */ | |
117 | { AR5K_PHY(64), 0x00000000 }, /* 0x9900 */ | |
118 | { AR5K_PHY(65), 0x00000000 }, | |
119 | { AR5K_PHY(66), 0x00000000 }, | |
120 | { AR5K_PHY(67), 0x00800000 }, | |
121 | { AR5K_PHY(68), 0x00000003 }, | |
122 | /* BB gain table (64bytes) */ | |
123 | { AR5K_BB_GAIN(0), 0x00000000 }, | |
124 | { AR5K_BB_GAIN(1), 0x00000020 }, | |
125 | { AR5K_BB_GAIN(2), 0x00000010 }, | |
126 | { AR5K_BB_GAIN(3), 0x00000030 }, | |
127 | { AR5K_BB_GAIN(4), 0x00000008 }, | |
128 | { AR5K_BB_GAIN(5), 0x00000028 }, | |
129 | { AR5K_BB_GAIN(6), 0x00000028 }, | |
130 | { AR5K_BB_GAIN(7), 0x00000004 }, | |
131 | { AR5K_BB_GAIN(8), 0x00000024 }, | |
132 | { AR5K_BB_GAIN(9), 0x00000014 }, | |
133 | { AR5K_BB_GAIN(10), 0x00000034 }, | |
134 | { AR5K_BB_GAIN(11), 0x0000000c }, | |
135 | { AR5K_BB_GAIN(12), 0x0000002c }, | |
136 | { AR5K_BB_GAIN(13), 0x00000002 }, | |
137 | { AR5K_BB_GAIN(14), 0x00000022 }, | |
138 | { AR5K_BB_GAIN(15), 0x00000012 }, | |
139 | { AR5K_BB_GAIN(16), 0x00000032 }, | |
140 | { AR5K_BB_GAIN(17), 0x0000000a }, | |
141 | { AR5K_BB_GAIN(18), 0x0000002a }, | |
142 | { AR5K_BB_GAIN(19), 0x00000001 }, | |
143 | { AR5K_BB_GAIN(20), 0x00000021 }, | |
144 | { AR5K_BB_GAIN(21), 0x00000011 }, | |
145 | { AR5K_BB_GAIN(22), 0x00000031 }, | |
146 | { AR5K_BB_GAIN(23), 0x00000009 }, | |
147 | { AR5K_BB_GAIN(24), 0x00000029 }, | |
148 | { AR5K_BB_GAIN(25), 0x00000005 }, | |
149 | { AR5K_BB_GAIN(26), 0x00000025 }, | |
150 | { AR5K_BB_GAIN(27), 0x00000015 }, | |
151 | { AR5K_BB_GAIN(28), 0x00000035 }, | |
152 | { AR5K_BB_GAIN(29), 0x0000000d }, | |
153 | { AR5K_BB_GAIN(30), 0x0000002d }, | |
154 | { AR5K_BB_GAIN(31), 0x00000003 }, | |
155 | { AR5K_BB_GAIN(32), 0x00000023 }, | |
156 | { AR5K_BB_GAIN(33), 0x00000013 }, | |
157 | { AR5K_BB_GAIN(34), 0x00000033 }, | |
158 | { AR5K_BB_GAIN(35), 0x0000000b }, | |
159 | { AR5K_BB_GAIN(36), 0x0000002b }, | |
160 | { AR5K_BB_GAIN(37), 0x00000007 }, | |
161 | { AR5K_BB_GAIN(38), 0x00000027 }, | |
162 | { AR5K_BB_GAIN(39), 0x00000017 }, | |
163 | { AR5K_BB_GAIN(40), 0x00000037 }, | |
164 | { AR5K_BB_GAIN(41), 0x0000000f }, | |
165 | { AR5K_BB_GAIN(42), 0x0000002f }, | |
166 | { AR5K_BB_GAIN(43), 0x0000002f }, | |
167 | { AR5K_BB_GAIN(44), 0x0000002f }, | |
168 | { AR5K_BB_GAIN(45), 0x0000002f }, | |
169 | { AR5K_BB_GAIN(46), 0x0000002f }, | |
170 | { AR5K_BB_GAIN(47), 0x0000002f }, | |
171 | { AR5K_BB_GAIN(48), 0x0000002f }, | |
172 | { AR5K_BB_GAIN(49), 0x0000002f }, | |
173 | { AR5K_BB_GAIN(50), 0x0000002f }, | |
174 | { AR5K_BB_GAIN(51), 0x0000002f }, | |
175 | { AR5K_BB_GAIN(52), 0x0000002f }, | |
176 | { AR5K_BB_GAIN(53), 0x0000002f }, | |
177 | { AR5K_BB_GAIN(54), 0x0000002f }, | |
178 | { AR5K_BB_GAIN(55), 0x0000002f }, | |
179 | { AR5K_BB_GAIN(56), 0x0000002f }, | |
180 | { AR5K_BB_GAIN(57), 0x0000002f }, | |
181 | { AR5K_BB_GAIN(58), 0x0000002f }, | |
182 | { AR5K_BB_GAIN(59), 0x0000002f }, | |
183 | { AR5K_BB_GAIN(60), 0x0000002f }, | |
184 | { AR5K_BB_GAIN(61), 0x0000002f }, | |
185 | { AR5K_BB_GAIN(62), 0x0000002f }, | |
186 | { AR5K_BB_GAIN(63), 0x0000002f }, | |
187 | /* 5110 RF gain table (64btes) */ | |
188 | { AR5K_RF_GAIN(0), 0x0000001d }, | |
189 | { AR5K_RF_GAIN(1), 0x0000005d }, | |
190 | { AR5K_RF_GAIN(2), 0x0000009d }, | |
191 | { AR5K_RF_GAIN(3), 0x000000dd }, | |
192 | { AR5K_RF_GAIN(4), 0x0000011d }, | |
193 | { AR5K_RF_GAIN(5), 0x00000021 }, | |
194 | { AR5K_RF_GAIN(6), 0x00000061 }, | |
195 | { AR5K_RF_GAIN(7), 0x000000a1 }, | |
196 | { AR5K_RF_GAIN(8), 0x000000e1 }, | |
197 | { AR5K_RF_GAIN(9), 0x00000031 }, | |
198 | { AR5K_RF_GAIN(10), 0x00000071 }, | |
199 | { AR5K_RF_GAIN(11), 0x000000b1 }, | |
200 | { AR5K_RF_GAIN(12), 0x0000001c }, | |
201 | { AR5K_RF_GAIN(13), 0x0000005c }, | |
202 | { AR5K_RF_GAIN(14), 0x00000029 }, | |
203 | { AR5K_RF_GAIN(15), 0x00000069 }, | |
204 | { AR5K_RF_GAIN(16), 0x000000a9 }, | |
205 | { AR5K_RF_GAIN(17), 0x00000020 }, | |
206 | { AR5K_RF_GAIN(18), 0x00000019 }, | |
207 | { AR5K_RF_GAIN(19), 0x00000059 }, | |
208 | { AR5K_RF_GAIN(20), 0x00000099 }, | |
209 | { AR5K_RF_GAIN(21), 0x00000030 }, | |
210 | { AR5K_RF_GAIN(22), 0x00000005 }, | |
211 | { AR5K_RF_GAIN(23), 0x00000025 }, | |
212 | { AR5K_RF_GAIN(24), 0x00000065 }, | |
213 | { AR5K_RF_GAIN(25), 0x000000a5 }, | |
214 | { AR5K_RF_GAIN(26), 0x00000028 }, | |
215 | { AR5K_RF_GAIN(27), 0x00000068 }, | |
216 | { AR5K_RF_GAIN(28), 0x0000001f }, | |
217 | { AR5K_RF_GAIN(29), 0x0000001e }, | |
218 | { AR5K_RF_GAIN(30), 0x00000018 }, | |
219 | { AR5K_RF_GAIN(31), 0x00000058 }, | |
220 | { AR5K_RF_GAIN(32), 0x00000098 }, | |
221 | { AR5K_RF_GAIN(33), 0x00000003 }, | |
222 | { AR5K_RF_GAIN(34), 0x00000004 }, | |
223 | { AR5K_RF_GAIN(35), 0x00000044 }, | |
224 | { AR5K_RF_GAIN(36), 0x00000084 }, | |
225 | { AR5K_RF_GAIN(37), 0x00000013 }, | |
226 | { AR5K_RF_GAIN(38), 0x00000012 }, | |
227 | { AR5K_RF_GAIN(39), 0x00000052 }, | |
228 | { AR5K_RF_GAIN(40), 0x00000092 }, | |
229 | { AR5K_RF_GAIN(41), 0x000000d2 }, | |
230 | { AR5K_RF_GAIN(42), 0x0000002b }, | |
231 | { AR5K_RF_GAIN(43), 0x0000002a }, | |
232 | { AR5K_RF_GAIN(44), 0x0000006a }, | |
233 | { AR5K_RF_GAIN(45), 0x000000aa }, | |
234 | { AR5K_RF_GAIN(46), 0x0000001b }, | |
235 | { AR5K_RF_GAIN(47), 0x0000001a }, | |
236 | { AR5K_RF_GAIN(48), 0x0000005a }, | |
237 | { AR5K_RF_GAIN(49), 0x0000009a }, | |
238 | { AR5K_RF_GAIN(50), 0x000000da }, | |
239 | { AR5K_RF_GAIN(51), 0x00000006 }, | |
240 | { AR5K_RF_GAIN(52), 0x00000006 }, | |
241 | { AR5K_RF_GAIN(53), 0x00000006 }, | |
242 | { AR5K_RF_GAIN(54), 0x00000006 }, | |
243 | { AR5K_RF_GAIN(55), 0x00000006 }, | |
244 | { AR5K_RF_GAIN(56), 0x00000006 }, | |
245 | { AR5K_RF_GAIN(57), 0x00000006 }, | |
246 | { AR5K_RF_GAIN(58), 0x00000006 }, | |
247 | { AR5K_RF_GAIN(59), 0x00000006 }, | |
248 | { AR5K_RF_GAIN(60), 0x00000006 }, | |
249 | { AR5K_RF_GAIN(61), 0x00000006 }, | |
250 | { AR5K_RF_GAIN(62), 0x00000006 }, | |
251 | { AR5K_RF_GAIN(63), 0x00000006 }, | |
252 | /* PHY activation */ | |
253 | { AR5K_PHY(53), 0x00000020 }, | |
254 | { AR5K_PHY(51), 0x00000004 }, | |
255 | { AR5K_PHY(50), 0x00060106 }, | |
256 | { AR5K_PHY(39), 0x0000006d }, | |
257 | { AR5K_PHY(48), 0x00000000 }, | |
258 | { AR5K_PHY(52), 0x00000014 }, | |
259 | { AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE }, | |
260 | }; | |
261 | ||
262 | /* Initial register settings for AR5211 */ | |
263 | static const struct ath5k_ini ar5211_ini[] = { | |
264 | { AR5K_RXDP, 0x00000000 }, | |
265 | { AR5K_RTSD0, 0x84849c9c }, | |
266 | { AR5K_RTSD1, 0x7c7c7c7c }, | |
267 | { AR5K_RXCFG, 0x00000005 }, | |
268 | { AR5K_MIBC, 0x00000000 }, | |
269 | { AR5K_TOPS, 0x00000008 }, | |
270 | { AR5K_RXNOFRM, 0x00000008 }, | |
271 | { AR5K_TXNOFRM, 0x00000010 }, | |
272 | { AR5K_RPGTO, 0x00000000 }, | |
273 | { AR5K_RFCNT, 0x0000001f }, | |
274 | { AR5K_QUEUE_TXDP(0), 0x00000000 }, | |
275 | { AR5K_QUEUE_TXDP(1), 0x00000000 }, | |
276 | { AR5K_QUEUE_TXDP(2), 0x00000000 }, | |
277 | { AR5K_QUEUE_TXDP(3), 0x00000000 }, | |
278 | { AR5K_QUEUE_TXDP(4), 0x00000000 }, | |
279 | { AR5K_QUEUE_TXDP(5), 0x00000000 }, | |
280 | { AR5K_QUEUE_TXDP(6), 0x00000000 }, | |
281 | { AR5K_QUEUE_TXDP(7), 0x00000000 }, | |
282 | { AR5K_QUEUE_TXDP(8), 0x00000000 }, | |
283 | { AR5K_QUEUE_TXDP(9), 0x00000000 }, | |
284 | { AR5K_DCU_FP, 0x00000000 }, | |
285 | { AR5K_STA_ID1, 0x00000000 }, | |
286 | { AR5K_BSS_ID0, 0x00000000 }, | |
287 | { AR5K_BSS_ID1, 0x00000000 }, | |
288 | { AR5K_RSSI_THR, 0x00000000 }, | |
289 | { AR5K_CFP_PERIOD_5211, 0x00000000 }, | |
290 | { AR5K_TIMER0_5211, 0x00000030 }, | |
291 | { AR5K_TIMER1_5211, 0x0007ffff }, | |
292 | { AR5K_TIMER2_5211, 0x01ffffff }, | |
293 | { AR5K_TIMER3_5211, 0x00000031 }, | |
294 | { AR5K_CFP_DUR_5211, 0x00000000 }, | |
295 | { AR5K_RX_FILTER_5211, 0x00000000 }, | |
296 | { AR5K_MCAST_FILTER0_5211, 0x00000000 }, | |
297 | { AR5K_MCAST_FILTER1_5211, 0x00000002 }, | |
298 | { AR5K_DIAG_SW_5211, 0x00000000 }, | |
299 | { AR5K_ADDAC_TEST, 0x00000000 }, | |
300 | { AR5K_DEFAULT_ANTENNA, 0x00000000 }, | |
301 | /* PHY registers */ | |
302 | { AR5K_PHY_AGC, 0x00000000 }, | |
303 | { AR5K_PHY(3), 0x2d849093 }, | |
304 | { AR5K_PHY(4), 0x7d32e000 }, | |
305 | { AR5K_PHY(5), 0x00000f6b }, | |
306 | { AR5K_PHY_ACT, 0x00000000 }, | |
307 | { AR5K_PHY(11), 0x00026ffe }, | |
308 | { AR5K_PHY(12), 0x00000000 }, | |
309 | { AR5K_PHY(15), 0x00020100 }, | |
310 | { AR5K_PHY(16), 0x206a017a }, | |
311 | { AR5K_PHY(19), 0x1284613c }, | |
312 | { AR5K_PHY(21), 0x00000859 }, | |
313 | { AR5K_PHY(26), 0x409a4190 }, /* 0x9868 */ | |
314 | { AR5K_PHY(27), 0x050cb081 }, | |
315 | { AR5K_PHY(28), 0x0000000f }, | |
316 | { AR5K_PHY(29), 0x00000080 }, | |
317 | { AR5K_PHY(30), 0x0000000c }, | |
318 | { AR5K_PHY(64), 0x00000000 }, | |
319 | { AR5K_PHY(65), 0x00000000 }, | |
320 | { AR5K_PHY(66), 0x00000000 }, | |
321 | { AR5K_PHY(67), 0x00800000 }, | |
322 | { AR5K_PHY(68), 0x00000001 }, | |
323 | { AR5K_PHY(71), 0x0000092a }, | |
324 | { AR5K_PHY_IQ, 0x00000000 }, | |
325 | { AR5K_PHY(73), 0x00058a05 }, | |
326 | { AR5K_PHY(74), 0x00000001 }, | |
327 | { AR5K_PHY(75), 0x00000000 }, | |
328 | { AR5K_PHY_PAPD_PROBE, 0x00000000 }, | |
329 | { AR5K_PHY(77), 0x00000000 }, /* 0x9934 */ | |
330 | { AR5K_PHY(78), 0x00000000 }, /* 0x9938 */ | |
331 | { AR5K_PHY(79), 0x0000003f }, /* 0x993c */ | |
332 | { AR5K_PHY(80), 0x00000004 }, | |
333 | { AR5K_PHY(82), 0x00000000 }, | |
334 | { AR5K_PHY(83), 0x00000000 }, | |
335 | { AR5K_PHY(84), 0x00000000 }, | |
336 | { AR5K_PHY_RADAR, 0x5d50f14c }, | |
337 | { AR5K_PHY(86), 0x00000018 }, | |
338 | { AR5K_PHY(87), 0x004b6a8e }, | |
339 | /* Initial Power table (32bytes) | |
340 | * common on all cards/modes. | |
341 | * Note: Table is rewritten during | |
342 | * txpower setup later using calibration | |
a406c139 | 343 | * data etc. so next write is non-common */ |
fa1c114f JS |
344 | { AR5K_PHY_PCDAC_TXPOWER(1), 0x06ff05ff }, |
345 | { AR5K_PHY_PCDAC_TXPOWER(2), 0x07ff07ff }, | |
346 | { AR5K_PHY_PCDAC_TXPOWER(3), 0x08ff08ff }, | |
347 | { AR5K_PHY_PCDAC_TXPOWER(4), 0x09ff09ff }, | |
348 | { AR5K_PHY_PCDAC_TXPOWER(5), 0x0aff0aff }, | |
349 | { AR5K_PHY_PCDAC_TXPOWER(6), 0x0bff0bff }, | |
350 | { AR5K_PHY_PCDAC_TXPOWER(7), 0x0cff0cff }, | |
351 | { AR5K_PHY_PCDAC_TXPOWER(8), 0x0dff0dff }, | |
352 | { AR5K_PHY_PCDAC_TXPOWER(9), 0x0fff0eff }, | |
353 | { AR5K_PHY_PCDAC_TXPOWER(10), 0x12ff12ff }, | |
354 | { AR5K_PHY_PCDAC_TXPOWER(11), 0x14ff13ff }, | |
355 | { AR5K_PHY_PCDAC_TXPOWER(12), 0x16ff15ff }, | |
356 | { AR5K_PHY_PCDAC_TXPOWER(13), 0x19ff17ff }, | |
357 | { AR5K_PHY_PCDAC_TXPOWER(14), 0x1bff1aff }, | |
358 | { AR5K_PHY_PCDAC_TXPOWER(15), 0x1eff1dff }, | |
359 | { AR5K_PHY_PCDAC_TXPOWER(16), 0x23ff20ff }, | |
360 | { AR5K_PHY_PCDAC_TXPOWER(17), 0x27ff25ff }, | |
361 | { AR5K_PHY_PCDAC_TXPOWER(18), 0x2cff29ff }, | |
362 | { AR5K_PHY_PCDAC_TXPOWER(19), 0x31ff2fff }, | |
363 | { AR5K_PHY_PCDAC_TXPOWER(20), 0x37ff34ff }, | |
364 | { AR5K_PHY_PCDAC_TXPOWER(21), 0x3aff3aff }, | |
365 | { AR5K_PHY_PCDAC_TXPOWER(22), 0x3aff3aff }, | |
366 | { AR5K_PHY_PCDAC_TXPOWER(23), 0x3aff3aff }, | |
367 | { AR5K_PHY_PCDAC_TXPOWER(24), 0x3aff3aff }, | |
368 | { AR5K_PHY_PCDAC_TXPOWER(25), 0x3aff3aff }, | |
369 | { AR5K_PHY_PCDAC_TXPOWER(26), 0x3aff3aff }, | |
370 | { AR5K_PHY_PCDAC_TXPOWER(27), 0x3aff3aff }, | |
371 | { AR5K_PHY_PCDAC_TXPOWER(28), 0x3aff3aff }, | |
372 | { AR5K_PHY_PCDAC_TXPOWER(29), 0x3aff3aff }, | |
373 | { AR5K_PHY_PCDAC_TXPOWER(30), 0x3aff3aff }, | |
a406c139 | 374 | { AR5K_PHY_PCDAC_TXPOWER(31), 0x3aff3aff }, |
fa1c114f JS |
375 | { AR5K_PHY_CCKTXCTL, 0x00000000 }, |
376 | { AR5K_PHY(642), 0x503e4646 }, | |
377 | { AR5K_PHY_GAIN_2GHZ, 0x6480416c }, | |
378 | { AR5K_PHY(644), 0x0199a003 }, | |
379 | { AR5K_PHY(645), 0x044cd610 }, | |
380 | { AR5K_PHY(646), 0x13800040 }, | |
381 | { AR5K_PHY(647), 0x1be00060 }, | |
382 | { AR5K_PHY(648), 0x0c53800a }, | |
383 | { AR5K_PHY(649), 0x0014df3b }, | |
384 | { AR5K_PHY(650), 0x000001b5 }, | |
385 | { AR5K_PHY(651), 0x00000020 }, | |
386 | }; | |
387 | ||
388 | /* Initial mode-specific settings for AR5211 | |
a406c139 NK |
389 | * 5211 supports OFDM-only g (draft g) but we |
390 | * need to test it ! | |
fa1c114f JS |
391 | */ |
392 | static const struct ath5k_ini_mode ar5211_ini_mode[] = { | |
393 | { AR5K_TXCFG, | |
a406c139 NK |
394 | /* a aTurbo b g (OFDM) */ |
395 | { 0x00000015, 0x00000015, 0x0000001d, 0x00000015 } }, | |
fa1c114f | 396 | { AR5K_QUEUE_DFS_LOCAL_IFS(0), |
a406c139 | 397 | { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, |
fa1c114f | 398 | { AR5K_QUEUE_DFS_LOCAL_IFS(1), |
a406c139 | 399 | { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, |
fa1c114f | 400 | { AR5K_QUEUE_DFS_LOCAL_IFS(2), |
a406c139 | 401 | { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, |
fa1c114f | 402 | { AR5K_QUEUE_DFS_LOCAL_IFS(3), |
a406c139 | 403 | { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, |
fa1c114f | 404 | { AR5K_QUEUE_DFS_LOCAL_IFS(4), |
a406c139 | 405 | { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, |
fa1c114f | 406 | { AR5K_QUEUE_DFS_LOCAL_IFS(5), |
a406c139 | 407 | { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, |
fa1c114f | 408 | { AR5K_QUEUE_DFS_LOCAL_IFS(6), |
a406c139 | 409 | { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, |
fa1c114f | 410 | { AR5K_QUEUE_DFS_LOCAL_IFS(7), |
a406c139 | 411 | { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, |
fa1c114f | 412 | { AR5K_QUEUE_DFS_LOCAL_IFS(8), |
a406c139 | 413 | { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, |
fa1c114f | 414 | { AR5K_QUEUE_DFS_LOCAL_IFS(9), |
a406c139 | 415 | { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } }, |
fa1c114f | 416 | { AR5K_DCU_GBL_IFS_SLOT, |
a406c139 | 417 | { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } }, |
fa1c114f | 418 | { AR5K_DCU_GBL_IFS_SIFS, |
a406c139 | 419 | { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } }, |
fa1c114f | 420 | { AR5K_DCU_GBL_IFS_EIFS, |
a406c139 | 421 | { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } }, |
fa1c114f | 422 | { AR5K_DCU_GBL_IFS_MISC, |
a406c139 | 423 | { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } }, |
fa1c114f | 424 | { AR5K_TIME_OUT, |
a406c139 | 425 | { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } }, |
fa1c114f | 426 | { AR5K_USEC_5211, |
a406c139 | 427 | { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } }, |
fa1c114f | 428 | { AR5K_PHY_TURBO, |
a406c139 | 429 | { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } }, |
fa1c114f | 430 | { AR5K_PHY(8), |
a406c139 | 431 | { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } }, |
fa1c114f | 432 | { AR5K_PHY(9), |
a406c139 | 433 | { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } }, |
fa1c114f | 434 | { AR5K_PHY(10), |
a406c139 | 435 | { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } }, |
fa1c114f | 436 | { AR5K_PHY(13), |
a406c139 | 437 | { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, |
fa1c114f | 438 | { AR5K_PHY(14), |
a406c139 | 439 | { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } }, |
fa1c114f | 440 | { AR5K_PHY(17), |
a406c139 | 441 | { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } }, |
fa1c114f | 442 | { AR5K_PHY(18), |
a406c139 | 443 | { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } }, |
fa1c114f | 444 | { AR5K_PHY(20), |
a406c139 | 445 | { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } }, |
fa1c114f | 446 | { AR5K_PHY_SIG, |
a406c139 | 447 | { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } }, |
fa1c114f | 448 | { AR5K_PHY_AGCCOARSE, |
a406c139 | 449 | { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } }, |
fa1c114f | 450 | { AR5K_PHY_AGCCTL, |
a406c139 | 451 | { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } }, |
fa1c114f | 452 | { AR5K_PHY_NF, |
a406c139 | 453 | { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, |
fa1c114f | 454 | { AR5K_PHY_RX_DELAY, |
a406c139 | 455 | { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } }, |
fa1c114f | 456 | { AR5K_PHY(70), |
a406c139 | 457 | { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } }, |
fa1c114f | 458 | { AR5K_PHY_FRAME_CTL_5211, |
a406c139 NK |
459 | { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } }, |
460 | { AR5K_PHY_PCDAC_TXPOWER_BASE, | |
461 | { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } }, | |
fa1c114f | 462 | { AR5K_RF_BUFFER_CONTROL_4, |
a406c139 | 463 | { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } }, |
fa1c114f JS |
464 | }; |
465 | ||
466 | /* Initial register settings for AR5212 */ | |
a406c139 | 467 | static const struct ath5k_ini ar5212_ini_common_start[] = { |
fa1c114f JS |
468 | { AR5K_RXDP, 0x00000000 }, |
469 | { AR5K_RXCFG, 0x00000005 }, | |
470 | { AR5K_MIBC, 0x00000000 }, | |
471 | { AR5K_TOPS, 0x00000008 }, | |
472 | { AR5K_RXNOFRM, 0x00000008 }, | |
473 | { AR5K_TXNOFRM, 0x00000010 }, | |
474 | { AR5K_RPGTO, 0x00000000 }, | |
475 | { AR5K_RFCNT, 0x0000001f }, | |
476 | { AR5K_QUEUE_TXDP(0), 0x00000000 }, | |
477 | { AR5K_QUEUE_TXDP(1), 0x00000000 }, | |
478 | { AR5K_QUEUE_TXDP(2), 0x00000000 }, | |
479 | { AR5K_QUEUE_TXDP(3), 0x00000000 }, | |
480 | { AR5K_QUEUE_TXDP(4), 0x00000000 }, | |
481 | { AR5K_QUEUE_TXDP(5), 0x00000000 }, | |
482 | { AR5K_QUEUE_TXDP(6), 0x00000000 }, | |
483 | { AR5K_QUEUE_TXDP(7), 0x00000000 }, | |
484 | { AR5K_QUEUE_TXDP(8), 0x00000000 }, | |
485 | { AR5K_QUEUE_TXDP(9), 0x00000000 }, | |
486 | { AR5K_DCU_FP, 0x00000000 }, | |
487 | { AR5K_DCU_TXP, 0x00000000 }, | |
a406c139 NK |
488 | /* Tx filter table 0 (32 entries) */ |
489 | { AR5K_DCU_TX_FILTER_0(0), 0x00000000 }, /* DCU 0 */ | |
490 | { AR5K_DCU_TX_FILTER_0(1), 0x00000000 }, | |
491 | { AR5K_DCU_TX_FILTER_0(2), 0x00000000 }, | |
492 | { AR5K_DCU_TX_FILTER_0(3), 0x00000000 }, | |
493 | { AR5K_DCU_TX_FILTER_0(4), 0x00000000 }, /* DCU 1 */ | |
494 | { AR5K_DCU_TX_FILTER_0(5), 0x00000000 }, | |
495 | { AR5K_DCU_TX_FILTER_0(6), 0x00000000 }, | |
496 | { AR5K_DCU_TX_FILTER_0(7), 0x00000000 }, | |
497 | { AR5K_DCU_TX_FILTER_0(8), 0x00000000 }, /* DCU 2 */ | |
498 | { AR5K_DCU_TX_FILTER_0(9), 0x00000000 }, | |
499 | { AR5K_DCU_TX_FILTER_0(10), 0x00000000 }, | |
500 | { AR5K_DCU_TX_FILTER_0(11), 0x00000000 }, | |
501 | { AR5K_DCU_TX_FILTER_0(12), 0x00000000 }, /* DCU 3 */ | |
502 | { AR5K_DCU_TX_FILTER_0(13), 0x00000000 }, | |
503 | { AR5K_DCU_TX_FILTER_0(14), 0x00000000 }, | |
504 | { AR5K_DCU_TX_FILTER_0(15), 0x00000000 }, | |
505 | { AR5K_DCU_TX_FILTER_0(16), 0x00000000 }, /* DCU 4 */ | |
506 | { AR5K_DCU_TX_FILTER_0(17), 0x00000000 }, | |
507 | { AR5K_DCU_TX_FILTER_0(18), 0x00000000 }, | |
508 | { AR5K_DCU_TX_FILTER_0(19), 0x00000000 }, | |
509 | { AR5K_DCU_TX_FILTER_0(20), 0x00000000 }, /* DCU 5 */ | |
510 | { AR5K_DCU_TX_FILTER_0(21), 0x00000000 }, | |
511 | { AR5K_DCU_TX_FILTER_0(22), 0x00000000 }, | |
512 | { AR5K_DCU_TX_FILTER_0(23), 0x00000000 }, | |
513 | { AR5K_DCU_TX_FILTER_0(24), 0x00000000 }, /* DCU 6 */ | |
514 | { AR5K_DCU_TX_FILTER_0(25), 0x00000000 }, | |
515 | { AR5K_DCU_TX_FILTER_0(26), 0x00000000 }, | |
516 | { AR5K_DCU_TX_FILTER_0(27), 0x00000000 }, | |
517 | { AR5K_DCU_TX_FILTER_0(28), 0x00000000 }, /* DCU 7 */ | |
518 | { AR5K_DCU_TX_FILTER_0(29), 0x00000000 }, | |
519 | { AR5K_DCU_TX_FILTER_0(30), 0x00000000 }, | |
520 | { AR5K_DCU_TX_FILTER_0(31), 0x00000000 }, | |
521 | /* Tx filter table 1 (16 entries) */ | |
522 | { AR5K_DCU_TX_FILTER_1(0), 0x00000000 }, | |
523 | { AR5K_DCU_TX_FILTER_1(1), 0x00000000 }, | |
524 | { AR5K_DCU_TX_FILTER_1(2), 0x00000000 }, | |
525 | { AR5K_DCU_TX_FILTER_1(3), 0x00000000 }, | |
526 | { AR5K_DCU_TX_FILTER_1(4), 0x00000000 }, | |
527 | { AR5K_DCU_TX_FILTER_1(5), 0x00000000 }, | |
528 | { AR5K_DCU_TX_FILTER_1(6), 0x00000000 }, | |
529 | { AR5K_DCU_TX_FILTER_1(7), 0x00000000 }, | |
530 | { AR5K_DCU_TX_FILTER_1(8), 0x00000000 }, | |
531 | { AR5K_DCU_TX_FILTER_1(9), 0x00000000 }, | |
532 | { AR5K_DCU_TX_FILTER_1(10), 0x00000000 }, | |
533 | { AR5K_DCU_TX_FILTER_1(11), 0x00000000 }, | |
534 | { AR5K_DCU_TX_FILTER_1(12), 0x00000000 }, | |
535 | { AR5K_DCU_TX_FILTER_1(13), 0x00000000 }, | |
536 | { AR5K_DCU_TX_FILTER_1(14), 0x00000000 }, | |
537 | { AR5K_DCU_TX_FILTER_1(15), 0x00000000 }, | |
538 | { AR5K_DCU_TX_FILTER_CLR, 0x00000000 }, | |
539 | { AR5K_DCU_TX_FILTER_SET, 0x00000000 }, | |
fa1c114f JS |
540 | { AR5K_STA_ID1, 0x00000000 }, |
541 | { AR5K_BSS_ID0, 0x00000000 }, | |
542 | { AR5K_BSS_ID1, 0x00000000 }, | |
a406c139 NK |
543 | { AR5K_BEACON_5211, 0x00000000 }, |
544 | { AR5K_CFP_PERIOD_5211, 0x00000000 }, | |
545 | { AR5K_TIMER0_5211, 0x00000030 }, | |
546 | { AR5K_TIMER1_5211, 0x0007ffff }, | |
547 | { AR5K_TIMER2_5211, 0x01ffffff }, | |
548 | { AR5K_TIMER3_5211, 0x00000031 }, | |
549 | { AR5K_CFP_DUR_5211, 0x00000000 }, | |
fa1c114f JS |
550 | { AR5K_RX_FILTER_5211, 0x00000000 }, |
551 | { AR5K_DIAG_SW_5211, 0x00000000 }, | |
552 | { AR5K_ADDAC_TEST, 0x00000000 }, | |
553 | { AR5K_DEFAULT_ANTENNA, 0x00000000 }, | |
a406c139 | 554 | { AR5K_FRAME_CTL_QOSM, 0x000fc78f }, |
fa1c114f JS |
555 | { AR5K_XRMODE, 0x2a82301a }, |
556 | { AR5K_XRDELAY, 0x05dc01e0 }, | |
557 | { AR5K_XRTIMEOUT, 0x1f402710 }, | |
558 | { AR5K_XRCHIRP, 0x01f40000 }, | |
559 | { AR5K_XRSTOMP, 0x00001e1c }, | |
a406c139 NK |
560 | { AR5K_SLEEP0, 0x0002aaaa }, |
561 | { AR5K_SLEEP1, 0x02005555 }, | |
562 | { AR5K_SLEEP2, 0x00000000 }, | |
fa1c114f JS |
563 | { AR5K_BSS_IDM0, 0xffffffff }, |
564 | { AR5K_BSS_IDM1, 0x0000ffff }, | |
565 | { AR5K_TXPC, 0x00000000 }, | |
566 | { AR5K_PROFCNT_TX, 0x00000000 }, | |
567 | { AR5K_PROFCNT_RX, 0x00000000 }, | |
568 | { AR5K_PROFCNT_RXCLR, 0x00000000 }, | |
569 | { AR5K_PROFCNT_CYCLE, 0x00000000 }, | |
a406c139 NK |
570 | { AR5K_QUIET_CTL1, 0x00000088 }, |
571 | /* Initial rate duration table (32 entries )*/ | |
fa1c114f JS |
572 | { AR5K_RATE_DUR(0), 0x00000000 }, |
573 | { AR5K_RATE_DUR(1), 0x0000008c }, | |
574 | { AR5K_RATE_DUR(2), 0x000000e4 }, | |
575 | { AR5K_RATE_DUR(3), 0x000002d5 }, | |
576 | { AR5K_RATE_DUR(4), 0x00000000 }, | |
577 | { AR5K_RATE_DUR(5), 0x00000000 }, | |
578 | { AR5K_RATE_DUR(6), 0x000000a0 }, | |
579 | { AR5K_RATE_DUR(7), 0x000001c9 }, | |
580 | { AR5K_RATE_DUR(8), 0x0000002c }, | |
581 | { AR5K_RATE_DUR(9), 0x0000002c }, | |
582 | { AR5K_RATE_DUR(10), 0x00000030 }, | |
583 | { AR5K_RATE_DUR(11), 0x0000003c }, | |
584 | { AR5K_RATE_DUR(12), 0x0000002c }, | |
585 | { AR5K_RATE_DUR(13), 0x0000002c }, | |
586 | { AR5K_RATE_DUR(14), 0x00000030 }, | |
587 | { AR5K_RATE_DUR(15), 0x0000003c }, | |
588 | { AR5K_RATE_DUR(16), 0x00000000 }, | |
589 | { AR5K_RATE_DUR(17), 0x00000000 }, | |
590 | { AR5K_RATE_DUR(18), 0x00000000 }, | |
591 | { AR5K_RATE_DUR(19), 0x00000000 }, | |
592 | { AR5K_RATE_DUR(20), 0x00000000 }, | |
593 | { AR5K_RATE_DUR(21), 0x00000000 }, | |
594 | { AR5K_RATE_DUR(22), 0x00000000 }, | |
595 | { AR5K_RATE_DUR(23), 0x00000000 }, | |
596 | { AR5K_RATE_DUR(24), 0x000000d5 }, | |
597 | { AR5K_RATE_DUR(25), 0x000000df }, | |
598 | { AR5K_RATE_DUR(26), 0x00000102 }, | |
599 | { AR5K_RATE_DUR(27), 0x0000013a }, | |
600 | { AR5K_RATE_DUR(28), 0x00000075 }, | |
601 | { AR5K_RATE_DUR(29), 0x0000007f }, | |
602 | { AR5K_RATE_DUR(30), 0x000000a2 }, | |
603 | { AR5K_RATE_DUR(31), 0x00000000 }, | |
a406c139 | 604 | { AR5K_QUIET_CTL2, 0x00010002 }, |
fa1c114f | 605 | { AR5K_TSF_PARM, 0x00000001 }, |
a406c139 | 606 | { AR5K_QOS_NOACK, 0x000000c0 }, |
fa1c114f | 607 | { AR5K_PHY_ERR_FIL, 0x00000000 }, |
a406c139 NK |
608 | { AR5K_XRLAT_TX, 0x00000168 }, |
609 | { AR5K_ACKSIFS, 0x00000000 }, | |
610 | /* Rate -> db table | |
611 | * notice ...03<-02<-01<-00 ! */ | |
612 | { AR5K_RATE2DB(0), 0x03020100 }, | |
613 | { AR5K_RATE2DB(1), 0x07060504 }, | |
614 | { AR5K_RATE2DB(2), 0x0b0a0908 }, | |
615 | { AR5K_RATE2DB(3), 0x0f0e0d0c }, | |
616 | { AR5K_RATE2DB(4), 0x13121110 }, | |
617 | { AR5K_RATE2DB(5), 0x17161514 }, | |
618 | { AR5K_RATE2DB(6), 0x1b1a1918 }, | |
619 | { AR5K_RATE2DB(7), 0x1f1e1d1c }, | |
620 | /* Db -> Rate table */ | |
621 | { AR5K_DB2RATE(0), 0x03020100 }, | |
622 | { AR5K_DB2RATE(1), 0x07060504 }, | |
623 | { AR5K_DB2RATE(2), 0x0b0a0908 }, | |
624 | { AR5K_DB2RATE(3), 0x0f0e0d0c }, | |
625 | { AR5K_DB2RATE(4), 0x13121110 }, | |
626 | { AR5K_DB2RATE(5), 0x17161514 }, | |
627 | { AR5K_DB2RATE(6), 0x1b1a1918 }, | |
628 | { AR5K_DB2RATE(7), 0x1f1e1d1c }, | |
629 | /* PHY registers (Common settings | |
630 | * for all chips/modes) */ | |
631 | { AR5K_PHY(3), 0xad848e19 }, | |
632 | { AR5K_PHY(4), 0x7d28e000 }, | |
633 | { AR5K_PHY_TIMING_3, 0x9c0a9f6b }, | |
634 | { AR5K_PHY_ACT, 0x00000000 }, | |
635 | { AR5K_PHY(16), 0x206a017a }, | |
636 | { AR5K_PHY(21), 0x00000859 }, | |
637 | { AR5K_PHY_BIN_MASK_1, 0x00000000 }, | |
638 | { AR5K_PHY_BIN_MASK_2, 0x00000000 }, | |
639 | { AR5K_PHY_BIN_MASK_3, 0x00000000 }, | |
640 | { AR5K_PHY_BIN_MASK_CTL, 0x00800000 }, | |
641 | { AR5K_PHY_ANT_CTL, 0x00000001 }, | |
fa1c114f | 642 | /*{ AR5K_PHY(71), 0x0000092a },*/ /* Old value */ |
a406c139 NK |
643 | { AR5K_PHY_MAX_RX_LEN, 0x00000c80 }, |
644 | { AR5K_PHY_IQ, 0x05100000 }, | |
645 | { AR5K_PHY_WARM_RESET, 0x00000001 }, | |
646 | { AR5K_PHY_CTL, 0x00000004 }, | |
fa1c114f JS |
647 | { AR5K_PHY_TXPOWER_RATE1, 0x1e1f2022 }, |
648 | { AR5K_PHY_TXPOWER_RATE2, 0x0a0b0c0d }, | |
649 | { AR5K_PHY_TXPOWER_RATE_MAX, 0x0000003f }, | |
a406c139 NK |
650 | { AR5K_PHY(82), 0x9280b212 }, |
651 | { AR5K_PHY_RADAR, 0x5d50e188 }, | |
fa1c114f | 652 | /*{ AR5K_PHY(86), 0x000000ff },*/ |
a406c139 NK |
653 | { AR5K_PHY(87), 0x004b6a8e }, |
654 | { AR5K_PHY_NFTHRES, 0x000003ce }, | |
655 | { AR5K_PHY_RESTART, 0x192fb515 }, | |
656 | { AR5K_PHY(94), 0x00000001 }, | |
657 | { AR5K_PHY_RFBUS_REQ, 0x00000000 }, | |
fa1c114f JS |
658 | /*{ AR5K_PHY(644), 0x0080a333 },*/ /* Old value */ |
659 | /*{ AR5K_PHY(645), 0x00206c10 },*/ /* Old value */ | |
a406c139 NK |
660 | { AR5K_PHY(644), 0x00806333 }, |
661 | { AR5K_PHY(645), 0x00106c10 }, | |
662 | { AR5K_PHY(646), 0x009c4060 }, | |
663 | /* { AR5K_PHY(647), 0x1483800a }, */ | |
664 | /* { AR5K_PHY(648), 0x01831061 }, */ /* Old value */ | |
665 | { AR5K_PHY(648), 0x018830c6 }, | |
666 | { AR5K_PHY(649), 0x00000400 }, | |
fa1c114f | 667 | /*{ AR5K_PHY(650), 0x000001b5 },*/ |
a406c139 | 668 | { AR5K_PHY(651), 0x00000000 }, |
fa1c114f | 669 | { AR5K_PHY_TXPOWER_RATE3, 0x20202020 }, |
77ded01c | 670 | { AR5K_PHY_TXPOWER_RATE4, 0x20202020 }, |
fa1c114f | 671 | /*{ AR5K_PHY(655), 0x13c889af },*/ |
a406c139 NK |
672 | { AR5K_PHY(656), 0x38490a20 }, |
673 | { AR5K_PHY(657), 0x00007bb6 }, | |
674 | { AR5K_PHY(658), 0x0fff3ffc }, | |
fa1c114f JS |
675 | }; |
676 | ||
677 | /* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */ | |
678 | static const struct ath5k_ini_mode ar5212_ini_mode_start[] = { | |
fa1c114f | 679 | { AR5K_QUEUE_DFS_LOCAL_IFS(0), |
a406c139 NK |
680 | /* a/XR aTurbo b g (DYN) gTurbo */ |
681 | { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, | |
fa1c114f | 682 | { AR5K_QUEUE_DFS_LOCAL_IFS(1), |
a406c139 | 683 | { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, |
fa1c114f | 684 | { AR5K_QUEUE_DFS_LOCAL_IFS(2), |
a406c139 | 685 | { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, |
fa1c114f | 686 | { AR5K_QUEUE_DFS_LOCAL_IFS(3), |
a406c139 | 687 | { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, |
fa1c114f | 688 | { AR5K_QUEUE_DFS_LOCAL_IFS(4), |
a406c139 | 689 | { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, |
fa1c114f | 690 | { AR5K_QUEUE_DFS_LOCAL_IFS(5), |
a406c139 | 691 | { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, |
fa1c114f | 692 | { AR5K_QUEUE_DFS_LOCAL_IFS(6), |
a406c139 | 693 | { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, |
fa1c114f | 694 | { AR5K_QUEUE_DFS_LOCAL_IFS(7), |
a406c139 | 695 | { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, |
fa1c114f | 696 | { AR5K_QUEUE_DFS_LOCAL_IFS(8), |
a406c139 | 697 | { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, |
fa1c114f | 698 | { AR5K_QUEUE_DFS_LOCAL_IFS(9), |
a406c139 | 699 | { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } }, |
fa1c114f | 700 | { AR5K_DCU_GBL_IFS_SIFS, |
a406c139 | 701 | { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } }, |
fa1c114f | 702 | { AR5K_DCU_GBL_IFS_SLOT, |
a406c139 | 703 | { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } }, |
fa1c114f | 704 | { AR5K_DCU_GBL_IFS_EIFS, |
a406c139 | 705 | { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } }, |
fa1c114f | 706 | { AR5K_DCU_GBL_IFS_MISC, |
a406c139 | 707 | { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } }, |
fa1c114f | 708 | { AR5K_TIME_OUT, |
a406c139 | 709 | { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } }, |
fa1c114f | 710 | { AR5K_PHY_TURBO, |
a406c139 | 711 | { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } }, |
fa1c114f | 712 | { AR5K_PHY(8), |
a406c139 NK |
713 | { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } }, |
714 | { AR5K_PHY_RF_CTL2, | |
715 | { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e } }, | |
716 | { AR5K_PHY_SETTLING, | |
717 | { 0x1372161c, 0x13721c25, 0x13721722, 0x137216a2, 0x13721c25 } }, | |
fa1c114f | 718 | { AR5K_PHY_AGCCTL, |
77ded01c | 719 | { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d18, 0x00009d10 } }, |
fa1c114f | 720 | { AR5K_PHY_NF, |
a406c139 NK |
721 | { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } }, |
722 | { AR5K_PHY_WEAK_OFDM_HIGH_THR, | |
723 | { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } }, | |
fa1c114f | 724 | { AR5K_PHY(70), |
a406c139 NK |
725 | { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } }, |
726 | { AR5K_PHY_OFDM_SELFCORR, | |
727 | { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } }, | |
fa1c114f | 728 | { 0xa230, |
a406c139 | 729 | { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } }, |
fa1c114f JS |
730 | }; |
731 | ||
732 | /* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */ | |
a406c139 | 733 | static const struct ath5k_ini_mode rf5111_ini_mode_end[] = { |
fa1c114f | 734 | { AR5K_TXCFG, |
a406c139 NK |
735 | /* a/XR aTurbo b g (DYN) gTurbo */ |
736 | { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } }, | |
fa1c114f | 737 | { AR5K_USEC_5211, |
a406c139 NK |
738 | { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x12e00fab, 0x09880fcf } }, |
739 | { AR5K_PHY_RF_CTL3, | |
740 | { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 } }, | |
741 | { AR5K_PHY_RF_CTL4, | |
742 | { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, | |
743 | { AR5K_PHY_PA_CTL, | |
744 | { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } }, | |
745 | { AR5K_PHY_GAIN, | |
746 | { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 } }, | |
747 | { AR5K_PHY_DESIRED_SIZE, | |
748 | { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } }, | |
fa1c114f | 749 | { AR5K_PHY_SIG, |
a406c139 | 750 | { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } }, |
fa1c114f | 751 | { AR5K_PHY_AGCCOARSE, |
a406c139 NK |
752 | { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e } }, |
753 | { AR5K_PHY_WEAK_OFDM_LOW_THR, | |
754 | { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 } }, | |
fa1c114f | 755 | { AR5K_PHY_RX_DELAY, |
a406c139 | 756 | { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 } }, |
fa1c114f | 757 | { AR5K_PHY_FRAME_CTL_5211, |
a406c139 | 758 | { 0xf7b81020, 0xf7b81020, 0xf7b80d20, 0xf7b81020, 0xf7b81020 } }, |
fa1c114f | 759 | { AR5K_PHY_GAIN_2GHZ, |
a406c139 NK |
760 | { 0x642c416a, 0x642c416a, 0x6440416a, 0x6440416a, 0x6440416a } }, |
761 | { AR5K_PHY_CCK_RX_CTL_4, | |
762 | { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } }, | |
763 | }; | |
764 | ||
765 | static const struct ath5k_ini rf5111_ini_common_end[] = { | |
766 | { AR5K_DCU_FP, 0x00000000 }, | |
767 | { AR5K_PHY_AGC, 0x00000000 }, | |
768 | { AR5K_PHY_ADC_CTL, 0x00022ffe }, | |
769 | { 0x983c, 0x00020100 }, | |
770 | { AR5K_PHY_GAIN_OFFSET, 0x1284613c }, | |
771 | { AR5K_PHY_PAPD_PROBE, 0x00004883 }, | |
772 | { 0x9940, 0x00000004 }, | |
773 | { 0x9958, 0x000000ff }, | |
774 | { 0x9974, 0x00000000 }, | |
775 | { AR5K_PHY_SPENDING, 0x00000018 }, | |
776 | { AR5K_PHY_CCKTXCTL, 0x00000000 }, | |
777 | { AR5K_PHY_CCK_CROSSCORR, 0xd03e6788 }, | |
778 | { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 }, | |
779 | { 0xa23c, 0x13c889af }, | |
fa1c114f JS |
780 | }; |
781 | ||
782 | /* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */ | |
a406c139 | 783 | static const struct ath5k_ini_mode rf5112_ini_mode_end[] = { |
fa1c114f | 784 | { AR5K_TXCFG, |
a406c139 NK |
785 | /* a/XR aTurbo b g (DYN) gTurbo */ |
786 | { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } }, | |
fa1c114f | 787 | { AR5K_USEC_5211, |
a406c139 NK |
788 | { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } }, |
789 | { AR5K_PHY_RF_CTL3, | |
790 | { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } }, | |
791 | { AR5K_PHY_RF_CTL4, | |
792 | { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, | |
793 | { AR5K_PHY_PA_CTL, | |
794 | { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } }, | |
795 | { AR5K_PHY_GAIN, | |
796 | { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } }, | |
797 | { AR5K_PHY_DESIRED_SIZE, | |
798 | { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } }, | |
fa1c114f | 799 | { AR5K_PHY_SIG, |
77ded01c | 800 | { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e, 0x7e800d2e } }, |
fa1c114f | 801 | { AR5K_PHY_AGCCOARSE, |
a406c139 NK |
802 | { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } }, |
803 | { AR5K_PHY_WEAK_OFDM_LOW_THR, | |
804 | { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } }, | |
fa1c114f | 805 | { AR5K_PHY_RX_DELAY, |
a406c139 | 806 | { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } }, |
fa1c114f | 807 | { AR5K_PHY_FRAME_CTL_5211, |
a406c139 | 808 | { 0xf7b81020, 0xf7b81020, 0xf7b80d10, 0xf7b81010, 0xf7b81010 } }, |
fa1c114f | 809 | { AR5K_PHY_CCKTXCTL, |
a406c139 NK |
810 | { 0x00000000, 0x00000000, 0x00000008, 0x00000008, 0x00000008 } }, |
811 | { AR5K_PHY_CCK_CROSSCORR, | |
812 | { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, | |
fa1c114f | 813 | { AR5K_PHY_GAIN_2GHZ, |
a406c139 NK |
814 | { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } }, |
815 | { AR5K_PHY_CCK_RX_CTL_4, | |
816 | { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } }, | |
817 | }; | |
818 | ||
819 | static const struct ath5k_ini rf5112_ini_common_end[] = { | |
820 | { AR5K_DCU_FP, 0x00000000 }, | |
821 | { AR5K_PHY_AGC, 0x00000000 }, | |
822 | { AR5K_PHY_ADC_CTL, 0x00022ffe }, | |
823 | { 0x983c, 0x00020100 }, | |
824 | { AR5K_PHY_GAIN_OFFSET, 0x1284613c }, | |
825 | { AR5K_PHY_PAPD_PROBE, 0x00004882 }, | |
826 | { 0x9940, 0x00000004 }, | |
827 | { 0x9958, 0x000000ff }, | |
828 | { 0x9974, 0x00000000 }, | |
829 | { AR5K_PHY_DAG_CCK_CTL, 0x000001b5 }, | |
830 | { 0xa23c, 0x13c889af }, | |
fa1c114f JS |
831 | }; |
832 | ||
833 | /* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */ | |
fa1c114f JS |
834 | static const struct ath5k_ini_mode rf5413_ini_mode_end[] = { |
835 | { AR5K_TXCFG, | |
a406c139 NK |
836 | /* a/XR aTurbo b g (DYN) gTurbo */ |
837 | { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } }, | |
fa1c114f | 838 | { AR5K_USEC_5211, |
a406c139 NK |
839 | { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } }, |
840 | { AR5K_PHY_RF_CTL3, | |
841 | { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } }, | |
842 | { AR5K_PHY_RF_CTL4, | |
843 | { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, | |
844 | { AR5K_PHY_PA_CTL, | |
845 | { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } }, | |
846 | { AR5K_PHY_GAIN, | |
847 | { 0x0018fa61, 0x0018fa61, 0x001a1a63, 0x001a1a63, 0x001a1a63 } }, | |
848 | { AR5K_PHY_DESIRED_SIZE, | |
849 | { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } }, | |
fa1c114f | 850 | { AR5K_PHY_SIG, |
a406c139 | 851 | { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } }, |
fa1c114f | 852 | { AR5K_PHY_AGCCOARSE, |
a406c139 NK |
853 | { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } }, |
854 | { AR5K_PHY_WEAK_OFDM_LOW_THR, | |
855 | { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } }, | |
fa1c114f | 856 | { AR5K_PHY_RX_DELAY, |
a406c139 | 857 | { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } }, |
fa1c114f | 858 | { AR5K_PHY_FRAME_CTL_5211, |
a406c139 | 859 | { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } }, |
fa1c114f | 860 | { AR5K_PHY_CCKTXCTL, |
a406c139 NK |
861 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, |
862 | { AR5K_PHY_CCK_CROSSCORR, | |
863 | { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, | |
fa1c114f | 864 | { AR5K_PHY_GAIN_2GHZ, |
a406c139 NK |
865 | { 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 } }, |
866 | { AR5K_PHY_CCK_RX_CTL_4, | |
867 | { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } }, | |
fa1c114f | 868 | { 0xa300, |
a406c139 | 869 | { 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 } }, |
fa1c114f | 870 | { 0xa304, |
a406c139 | 871 | { 0x30032602, 0x30032602, 0x30032602, 0x30032602, 0x30032602 } }, |
fa1c114f | 872 | { 0xa308, |
a406c139 | 873 | { 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06 } }, |
fa1c114f | 874 | { 0xa30c, |
a406c139 | 875 | { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } }, |
fa1c114f | 876 | { 0xa310, |
a406c139 | 877 | { 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f } }, |
fa1c114f | 878 | { 0xa314, |
a406c139 | 879 | { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } }, |
fa1c114f | 880 | { 0xa318, |
a406c139 | 881 | { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } }, |
fa1c114f | 882 | { 0xa31c, |
a406c139 | 883 | { 0x90cf865b, 0x90cf865b, 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } }, |
fa1c114f | 884 | { 0xa320, |
a406c139 | 885 | { 0x9d4f970f, 0x9d4f970f, 0x9b4f970f, 0x9b4f970f, 0x9b4f970f } }, |
fa1c114f | 886 | { 0xa324, |
a406c139 | 887 | { 0xa7cfa38f, 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f, 0xa3cf9f8f } }, |
fa1c114f | 888 | { 0xa328, |
a406c139 | 889 | { 0xb55faf1f, 0xb55faf1f, 0xb35faf1f, 0xb35faf1f, 0xb35faf1f } }, |
fa1c114f | 890 | { 0xa32c, |
a406c139 | 891 | { 0xbddfb99f, 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f, 0xbbdfb99f } }, |
fa1c114f | 892 | { 0xa330, |
a406c139 | 893 | { 0xcb7fc53f, 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f, 0xcb7fc73f } }, |
fa1c114f | 894 | { 0xa334, |
a406c139 NK |
895 | { 0xd5ffd1bf, 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } }, |
896 | }; | |
897 | ||
898 | static const struct ath5k_ini rf5413_ini_common_end[] = { | |
899 | { AR5K_DCU_FP, 0x000003e0 }, | |
900 | { AR5K_5414_CBCFG, 0x00000010 }, | |
901 | { AR5K_SEQ_MASK, 0x0000000f }, | |
902 | { 0x809c, 0x00000000 }, | |
903 | { 0x80a0, 0x00000000 }, | |
904 | { AR5K_MIC_QOS_CTL, 0x00000000 }, | |
905 | { AR5K_MIC_QOS_SEL, 0x00000000 }, | |
906 | { AR5K_MISC_MODE, 0x00000000 }, | |
907 | { AR5K_OFDM_FIL_CNT, 0x00000000 }, | |
908 | { AR5K_CCK_FIL_CNT, 0x00000000 }, | |
909 | { AR5K_PHYERR_CNT1, 0x00000000 }, | |
910 | { AR5K_PHYERR_CNT1_MASK, 0x00000000 }, | |
911 | { AR5K_PHYERR_CNT2, 0x00000000 }, | |
912 | { AR5K_PHYERR_CNT2_MASK, 0x00000000 }, | |
913 | { AR5K_TSF_THRES, 0x00000000 }, | |
914 | { 0x8140, 0x800003f9 }, | |
915 | { 0x8144, 0x00000000 }, | |
916 | { AR5K_PHY_AGC, 0x00000000 }, | |
917 | { AR5K_PHY_ADC_CTL, 0x0000a000 }, | |
918 | { 0x983c, 0x00200400 }, | |
919 | { AR5K_PHY_GAIN_OFFSET, 0x1284233c }, | |
920 | { AR5K_PHY_SCR, 0x0000001f }, | |
921 | { AR5K_PHY_SLMT, 0x00000080 }, | |
922 | { AR5K_PHY_SCAL, 0x0000000e }, | |
923 | { 0x9958, 0x00081fff }, | |
924 | { AR5K_PHY_TIMING_7, 0x00000000 }, | |
925 | { AR5K_PHY_TIMING_8, 0x02800000 }, | |
926 | { AR5K_PHY_TIMING_11, 0x00000000 }, | |
927 | { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 }, | |
928 | { 0x99e4, 0xaaaaaaaa }, | |
929 | { 0x99e8, 0x3c466478 }, | |
930 | { 0x99ec, 0x000000aa }, | |
931 | { AR5K_PHY_SCLOCK, 0x0000000c }, | |
932 | { AR5K_PHY_SDELAY, 0x000000ff }, | |
933 | { AR5K_PHY_SPENDING, 0x00000014 }, | |
934 | { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 }, | |
935 | { 0xa23c, 0x93c889af }, | |
936 | { AR5K_PHY_FAST_ADC, 0x00000001 }, | |
937 | { 0xa250, 0x0000a000 }, | |
938 | { AR5K_PHY_BLUETOOTH, 0x00000000 }, | |
939 | { AR5K_PHY_TPC_RG1, 0x0cc75380 }, | |
940 | { 0xa25c, 0x0f0f0f01 }, | |
941 | { 0xa260, 0x5f690f01 }, | |
942 | { 0xa264, 0x00418a11 }, | |
943 | { 0xa268, 0x00000000 }, | |
944 | { AR5K_PHY_TPC_RG5, 0x0c30c16a }, | |
945 | { 0xa270, 0x00820820 }, | |
946 | { 0xa274, 0x081b7caa }, | |
947 | { 0xa278, 0x1ce739ce }, | |
948 | { 0xa27c, 0x051701ce }, | |
949 | { 0xa338, 0x00000000 }, | |
950 | { 0xa33c, 0x00000000 }, | |
951 | { 0xa340, 0x00000000 }, | |
952 | { 0xa344, 0x00000000 }, | |
953 | { 0xa348, 0x3fffffff }, | |
954 | { 0xa34c, 0x3fffffff }, | |
955 | { 0xa350, 0x3fffffff }, | |
956 | { 0xa354, 0x0003ffff }, | |
957 | { 0xa358, 0x79a8aa1f }, | |
958 | { 0xa35c, 0x066c420f }, | |
959 | { 0xa360, 0x0f282207 }, | |
960 | { 0xa364, 0x17601685 }, | |
961 | { 0xa368, 0x1f801104 }, | |
962 | { 0xa36c, 0x37a00c03 }, | |
963 | { 0xa370, 0x3fc40883 }, | |
964 | { 0xa374, 0x57c00803 }, | |
965 | { 0xa378, 0x5fd80682 }, | |
966 | { 0xa37c, 0x7fe00482 }, | |
967 | { 0xa380, 0x7f3c7bba }, | |
968 | { 0xa384, 0xf3307ff0 }, | |
fa1c114f JS |
969 | }; |
970 | ||
f714dd6d | 971 | /* Initial mode-specific settings for RF2413/2414 (Written after ar5212_ini) */ |
a406c139 | 972 | /* XXX: a mode ? */ |
f714dd6d NK |
973 | static const struct ath5k_ini_mode rf2413_ini_mode_end[] = { |
974 | { AR5K_TXCFG, | |
a406c139 NK |
975 | /* a/XR aTurbo b g (DYN) gTurbo */ |
976 | { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } }, | |
f714dd6d | 977 | { AR5K_USEC_5211, |
a406c139 NK |
978 | { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } }, |
979 | { AR5K_PHY_RF_CTL3, | |
980 | { 0x0a020001, 0x0a020001, 0x05020000, 0x0a020001, 0x0a020001 } }, | |
981 | { AR5K_PHY_RF_CTL4, | |
982 | { 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00 } }, | |
983 | { AR5K_PHY_PA_CTL, | |
984 | { 0x00000002, 0x00000002, 0x0000000a, 0x0000000a, 0x0000000a } }, | |
985 | { AR5K_PHY_GAIN, | |
986 | { 0x0018da6d, 0x0018da6d, 0x001a6a64, 0x001a6a64, 0x001a6a64 } }, | |
987 | { AR5K_PHY_DESIRED_SIZE, | |
988 | { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da, 0x0de8b0da } }, | |
f714dd6d | 989 | { AR5K_PHY_SIG, |
a406c139 | 990 | { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e, 0x7e800d2e } }, |
f714dd6d | 991 | { AR5K_PHY_AGCCOARSE, |
a406c139 NK |
992 | { 0x3137665e, 0x3137665e, 0x3137665e, 0x3139605e, 0x3137665e } }, |
993 | { AR5K_PHY_WEAK_OFDM_LOW_THR, | |
994 | { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } }, | |
f714dd6d | 995 | { AR5K_PHY_RX_DELAY, |
a406c139 | 996 | { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } }, |
f714dd6d | 997 | { AR5K_PHY_FRAME_CTL_5211, |
a406c139 | 998 | { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } }, |
f714dd6d | 999 | { AR5K_PHY_CCKTXCTL, |
a406c139 NK |
1000 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, |
1001 | { AR5K_PHY_CCK_CROSSCORR, | |
1002 | { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, | |
f714dd6d | 1003 | { AR5K_PHY_GAIN_2GHZ, |
a406c139 NK |
1004 | { 0x002c0140, 0x002c0140, 0x0042c140, 0x0042c140, 0x0042c140 } }, |
1005 | { AR5K_PHY_CCK_RX_CTL_4, | |
1006 | { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } }, | |
1007 | }; | |
1008 | ||
1009 | static const struct ath5k_ini rf2413_ini_common_end[] = { | |
1010 | { AR5K_DCU_FP, 0x000003e0 }, | |
1011 | { AR5K_SEQ_MASK, 0x0000000f }, | |
1012 | { AR5K_MIC_QOS_CTL, 0x00000000 }, | |
1013 | { AR5K_MIC_QOS_SEL, 0x00000000 }, | |
1014 | { AR5K_MISC_MODE, 0x00000000 }, | |
1015 | { AR5K_OFDM_FIL_CNT, 0x00000000 }, | |
1016 | { AR5K_CCK_FIL_CNT, 0x00000000 }, | |
1017 | { AR5K_PHYERR_CNT1, 0x00000000 }, | |
1018 | { AR5K_PHYERR_CNT1_MASK, 0x00000000 }, | |
1019 | { AR5K_PHYERR_CNT2, 0x00000000 }, | |
1020 | { AR5K_PHYERR_CNT2_MASK, 0x00000000 }, | |
1021 | { AR5K_TSF_THRES, 0x00000000 }, | |
1022 | { 0x8140, 0x800000a8 }, | |
1023 | { 0x8144, 0x00000000 }, | |
1024 | { AR5K_PHY_AGC, 0x00000000 }, | |
1025 | { AR5K_PHY_ADC_CTL, 0x0000a000 }, | |
1026 | { 0x983c, 0x00200400 }, | |
1027 | { AR5K_PHY_GAIN_OFFSET, 0x1284233c }, | |
1028 | { AR5K_PHY_SCR, 0x0000001f }, | |
1029 | { AR5K_PHY_SLMT, 0x00000080 }, | |
1030 | { AR5K_PHY_SCAL, 0x0000000e }, | |
1031 | { 0x9958, 0x000000ff }, | |
1032 | { AR5K_PHY_TIMING_7, 0x00000000 }, | |
1033 | { AR5K_PHY_TIMING_8, 0x02800000 }, | |
1034 | { AR5K_PHY_TIMING_11, 0x00000000 }, | |
1035 | { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 }, | |
1036 | { 0x99e4, 0xaaaaaaaa }, | |
1037 | { 0x99e8, 0x3c466478 }, | |
1038 | { 0x99ec, 0x000000aa }, | |
1039 | { AR5K_PHY_SCLOCK, 0x0000000c }, | |
1040 | { AR5K_PHY_SDELAY, 0x000000ff }, | |
1041 | { AR5K_PHY_SPENDING, 0x00000014 }, | |
1042 | { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 }, | |
1043 | { 0xa23c, 0x93c889af }, | |
1044 | { AR5K_PHY_FAST_ADC, 0x00000001 }, | |
1045 | { 0xa250, 0x0000a000 }, | |
1046 | { AR5K_PHY_BLUETOOTH, 0x00000000 }, | |
1047 | { AR5K_PHY_TPC_RG1, 0x0cc75380 }, | |
1048 | { 0xa25c, 0x0f0f0f01 }, | |
1049 | { 0xa260, 0x5f690f01 }, | |
1050 | { 0xa264, 0x00418a11 }, | |
1051 | { 0xa268, 0x00000000 }, | |
1052 | { AR5K_PHY_TPC_RG5, 0x0c30c16a }, | |
1053 | { 0xa270, 0x00820820 }, | |
1054 | { 0xa274, 0x001b7caa }, | |
1055 | { 0xa278, 0x1ce739ce }, | |
1056 | { 0xa27c, 0x051701ce }, | |
1057 | { 0xa300, 0x18010000 }, | |
1058 | { 0xa304, 0x30032602 }, | |
1059 | { 0xa308, 0x48073e06 }, | |
1060 | { 0xa30c, 0x560b4c0a }, | |
1061 | { 0xa310, 0x641a600f }, | |
1062 | { 0xa314, 0x784f6e1b }, | |
1063 | { 0xa318, 0x868f7c5a }, | |
1064 | { 0xa31c, 0x8ecf865b }, | |
1065 | { 0xa320, 0x9d4f970f }, | |
1066 | { 0xa324, 0xa5cfa18f }, | |
1067 | { 0xa328, 0xb55faf1f }, | |
1068 | { 0xa32c, 0xbddfb99f }, | |
1069 | { 0xa330, 0xcd7fc73f }, | |
1070 | { 0xa334, 0xd5ffd1bf }, | |
1071 | { 0xa338, 0x00000000 }, | |
1072 | { 0xa33c, 0x00000000 }, | |
1073 | { 0xa340, 0x00000000 }, | |
1074 | { 0xa344, 0x00000000 }, | |
1075 | { 0xa348, 0x3fffffff }, | |
1076 | { 0xa34c, 0x3fffffff }, | |
1077 | { 0xa350, 0x3fffffff }, | |
1078 | { 0xa354, 0x0003ffff }, | |
1079 | { 0xa358, 0x79a8aa1f }, | |
1080 | { 0xa35c, 0x066c420f }, | |
1081 | { 0xa360, 0x0f282207 }, | |
1082 | { 0xa364, 0x17601685 }, | |
1083 | { 0xa368, 0x1f801104 }, | |
1084 | { 0xa36c, 0x37a00c03 }, | |
1085 | { 0xa370, 0x3fc40883 }, | |
1086 | { 0xa374, 0x57c00803 }, | |
1087 | { 0xa378, 0x5fd80682 }, | |
1088 | { 0xa37c, 0x7fe00482 }, | |
1089 | { 0xa380, 0x7f3c7bba }, | |
1090 | { 0xa384, 0xf3307ff0 }, | |
f714dd6d NK |
1091 | }; |
1092 | ||
136bfc79 | 1093 | /* Initial mode-specific settings for RF2425 (Written after ar5212_ini) */ |
a406c139 | 1094 | /* XXX: a mode ? */ |
136bfc79 NK |
1095 | static const struct ath5k_ini_mode rf2425_ini_mode_end[] = { |
1096 | { AR5K_TXCFG, | |
a406c139 NK |
1097 | /* a/XR aTurbo b g (DYN) gTurbo */ |
1098 | { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } }, | |
136bfc79 | 1099 | { AR5K_USEC_5211, |
a406c139 | 1100 | { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } }, |
136bfc79 | 1101 | { AR5K_PHY_TURBO, |
a406c139 NK |
1102 | { 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000001 } }, |
1103 | { AR5K_PHY_RF_CTL3, | |
1104 | { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } }, | |
1105 | { AR5K_PHY_RF_CTL4, | |
1106 | { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } }, | |
1107 | { AR5K_PHY_PA_CTL, | |
1108 | { 0x00000003, 0x00000003, 0x0000000b, 0x0000000b, 0x0000000b } }, | |
1109 | { AR5K_PHY_SETTLING, | |
1110 | { 0x1372161c, 0x13721c25, 0x13721722, 0x13721422, 0x13721c25 } }, | |
1111 | { AR5K_PHY_GAIN, | |
1112 | { 0x0018fa61, 0x0018fa61, 0x00199a65, 0x00199a65, 0x00199a65 } }, | |
1113 | { AR5K_PHY_DESIRED_SIZE, | |
1114 | { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } }, | |
136bfc79 | 1115 | { AR5K_PHY_SIG, |
a406c139 | 1116 | { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } }, |
136bfc79 | 1117 | { AR5K_PHY_AGCCOARSE, |
a406c139 NK |
1118 | { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } }, |
1119 | { AR5K_PHY_WEAK_OFDM_LOW_THR, | |
1120 | { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } }, | |
136bfc79 | 1121 | { AR5K_PHY_RX_DELAY, |
a406c139 | 1122 | { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } }, |
136bfc79 | 1123 | { AR5K_PHY_FRAME_CTL_5211, |
a406c139 | 1124 | { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } }, |
136bfc79 | 1125 | { AR5K_PHY_CCKTXCTL, |
a406c139 NK |
1126 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, |
1127 | { AR5K_PHY_CCK_CROSSCORR, | |
1128 | { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } }, | |
136bfc79 | 1129 | { AR5K_PHY_GAIN_2GHZ, |
a406c139 NK |
1130 | { 0x00000140, 0x00000140, 0x0052c140, 0x0052c140, 0x0052c140 } }, |
1131 | { AR5K_PHY_CCK_RX_CTL_4, | |
1132 | { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } }, | |
136bfc79 | 1133 | { 0xa324, |
a406c139 | 1134 | { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } }, |
136bfc79 | 1135 | { 0xa328, |
a406c139 | 1136 | { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } }, |
136bfc79 | 1137 | { 0xa32c, |
a406c139 | 1138 | { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } }, |
136bfc79 | 1139 | { 0xa330, |
a406c139 | 1140 | { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } }, |
136bfc79 | 1141 | { 0xa334, |
a406c139 NK |
1142 | { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } }, |
1143 | }; | |
1144 | ||
1145 | static const struct ath5k_ini rf2425_ini_common_end[] = { | |
1146 | { AR5K_DCU_FP, 0x000003e0 }, | |
1147 | { AR5K_SEQ_MASK, 0x0000000f }, | |
1148 | { 0x809c, 0x00000000 }, | |
1149 | { 0x80a0, 0x00000000 }, | |
1150 | { AR5K_MIC_QOS_CTL, 0x00000000 }, | |
1151 | { AR5K_MIC_QOS_SEL, 0x00000000 }, | |
1152 | { AR5K_MISC_MODE, 0x00000000 }, | |
1153 | { AR5K_OFDM_FIL_CNT, 0x00000000 }, | |
1154 | { AR5K_CCK_FIL_CNT, 0x00000000 }, | |
1155 | { AR5K_PHYERR_CNT1, 0x00000000 }, | |
1156 | { AR5K_PHYERR_CNT1_MASK, 0x00000000 }, | |
1157 | { AR5K_PHYERR_CNT2, 0x00000000 }, | |
1158 | { AR5K_PHYERR_CNT2_MASK, 0x00000000 }, | |
1159 | { AR5K_TSF_THRES, 0x00000000 }, | |
1160 | { 0x8140, 0x800003f9 }, | |
1161 | { 0x8144, 0x00000000 }, | |
1162 | { AR5K_PHY_AGC, 0x00000000 }, | |
1163 | { AR5K_PHY_ADC_CTL, 0x0000a000 }, | |
1164 | { 0x983c, 0x00200400 }, | |
1165 | { AR5K_PHY_GAIN_OFFSET, 0x1284233c }, | |
1166 | { AR5K_PHY_SCR, 0x0000001f }, | |
1167 | { AR5K_PHY_SLMT, 0x00000080 }, | |
1168 | { AR5K_PHY_SCAL, 0x0000000e }, | |
1169 | { 0x9958, 0x00081fff }, | |
1170 | { AR5K_PHY_TIMING_7, 0x00000000 }, | |
1171 | { AR5K_PHY_TIMING_8, 0x02800000 }, | |
1172 | { AR5K_PHY_TIMING_11, 0x00000000 }, | |
1173 | { 0x99dc, 0xfebadbe8 }, | |
1174 | { AR5K_PHY_HEAVY_CLIP_ENABLE, 0x00000000 }, | |
1175 | { 0x99e4, 0xaaaaaaaa }, | |
1176 | { 0x99e8, 0x3c466478 }, | |
1177 | { 0x99ec, 0x000000aa }, | |
1178 | { AR5K_PHY_SCLOCK, 0x0000000c }, | |
1179 | { AR5K_PHY_SDELAY, 0x000000ff }, | |
1180 | { AR5K_PHY_SPENDING, 0x00000014 }, | |
1181 | { AR5K_PHY_DAG_CCK_CTL, 0x000009b5 }, | |
1182 | { AR5K_PHY_TXPOWER_RATE3, 0x20202020 }, | |
1183 | { AR5K_PHY_TXPOWER_RATE4, 0x20202020 }, | |
1184 | { 0xa23c, 0x93c889af }, | |
1185 | { AR5K_PHY_FAST_ADC, 0x00000001 }, | |
1186 | { 0xa250, 0x0000a000 }, | |
1187 | { AR5K_PHY_BLUETOOTH, 0x00000000 }, | |
1188 | { AR5K_PHY_TPC_RG1, 0x0cc75380 }, | |
1189 | { 0xa25c, 0x0f0f0f01 }, | |
1190 | { 0xa260, 0x5f690f01 }, | |
1191 | { 0xa264, 0x00418a11 }, | |
1192 | { 0xa268, 0x00000000 }, | |
1193 | { AR5K_PHY_TPC_RG5, 0x0c30c166 }, | |
1194 | { 0xa270, 0x00820820 }, | |
1195 | { 0xa274, 0x081a3caa }, | |
1196 | { 0xa278, 0x1ce739ce }, | |
1197 | { 0xa27c, 0x051701ce }, | |
1198 | { 0xa300, 0x16010000 }, | |
1199 | { 0xa304, 0x2c032402 }, | |
1200 | { 0xa308, 0x48433e42 }, | |
1201 | { 0xa30c, 0x5a0f500b }, | |
1202 | { 0xa310, 0x6c4b624a }, | |
1203 | { 0xa314, 0x7e8b748a }, | |
1204 | { 0xa318, 0x96cf8ccb }, | |
1205 | { 0xa31c, 0xa34f9d0f }, | |
1206 | { 0xa320, 0xa7cfa58f }, | |
1207 | { 0xa348, 0x3fffffff }, | |
1208 | { 0xa34c, 0x3fffffff }, | |
1209 | { 0xa350, 0x3fffffff }, | |
1210 | { 0xa354, 0x0003ffff }, | |
1211 | { 0xa358, 0x79a8aa1f }, | |
1212 | { 0xa35c, 0x066c420f }, | |
1213 | { 0xa360, 0x0f282207 }, | |
1214 | { 0xa364, 0x17601685 }, | |
1215 | { 0xa368, 0x1f801104 }, | |
1216 | { 0xa36c, 0x37a00c03 }, | |
1217 | { 0xa370, 0x3fc40883 }, | |
1218 | { 0xa374, 0x57c00803 }, | |
1219 | { 0xa378, 0x5fd80682 }, | |
1220 | { 0xa37c, 0x7fe00482 }, | |
1221 | { 0xa380, 0x7f3c7bba }, | |
1222 | { 0xa384, 0xf3307ff0 }, | |
136bfc79 NK |
1223 | }; |
1224 | ||
fa1c114f JS |
1225 | /* |
1226 | * Initial BaseBand Gain settings for RF5111/5112 (AR5210 comes with | |
1227 | * RF5110 only so initial BB Gain settings are included in AR5K_AR5210_INI) | |
1228 | */ | |
1229 | ||
1230 | /* RF5111 Initial BaseBand Gain settings */ | |
1231 | static const struct ath5k_ini rf5111_ini_bbgain[] = { | |
1232 | { AR5K_BB_GAIN(0), 0x00000000 }, | |
1233 | { AR5K_BB_GAIN(1), 0x00000020 }, | |
1234 | { AR5K_BB_GAIN(2), 0x00000010 }, | |
1235 | { AR5K_BB_GAIN(3), 0x00000030 }, | |
1236 | { AR5K_BB_GAIN(4), 0x00000008 }, | |
1237 | { AR5K_BB_GAIN(5), 0x00000028 }, | |
1238 | { AR5K_BB_GAIN(6), 0x00000004 }, | |
1239 | { AR5K_BB_GAIN(7), 0x00000024 }, | |
1240 | { AR5K_BB_GAIN(8), 0x00000014 }, | |
1241 | { AR5K_BB_GAIN(9), 0x00000034 }, | |
1242 | { AR5K_BB_GAIN(10), 0x0000000c }, | |
1243 | { AR5K_BB_GAIN(11), 0x0000002c }, | |
1244 | { AR5K_BB_GAIN(12), 0x00000002 }, | |
1245 | { AR5K_BB_GAIN(13), 0x00000022 }, | |
1246 | { AR5K_BB_GAIN(14), 0x00000012 }, | |
1247 | { AR5K_BB_GAIN(15), 0x00000032 }, | |
1248 | { AR5K_BB_GAIN(16), 0x0000000a }, | |
1249 | { AR5K_BB_GAIN(17), 0x0000002a }, | |
1250 | { AR5K_BB_GAIN(18), 0x00000006 }, | |
1251 | { AR5K_BB_GAIN(19), 0x00000026 }, | |
1252 | { AR5K_BB_GAIN(20), 0x00000016 }, | |
1253 | { AR5K_BB_GAIN(21), 0x00000036 }, | |
1254 | { AR5K_BB_GAIN(22), 0x0000000e }, | |
1255 | { AR5K_BB_GAIN(23), 0x0000002e }, | |
1256 | { AR5K_BB_GAIN(24), 0x00000001 }, | |
1257 | { AR5K_BB_GAIN(25), 0x00000021 }, | |
1258 | { AR5K_BB_GAIN(26), 0x00000011 }, | |
1259 | { AR5K_BB_GAIN(27), 0x00000031 }, | |
1260 | { AR5K_BB_GAIN(28), 0x00000009 }, | |
1261 | { AR5K_BB_GAIN(29), 0x00000029 }, | |
1262 | { AR5K_BB_GAIN(30), 0x00000005 }, | |
1263 | { AR5K_BB_GAIN(31), 0x00000025 }, | |
1264 | { AR5K_BB_GAIN(32), 0x00000015 }, | |
1265 | { AR5K_BB_GAIN(33), 0x00000035 }, | |
1266 | { AR5K_BB_GAIN(34), 0x0000000d }, | |
1267 | { AR5K_BB_GAIN(35), 0x0000002d }, | |
1268 | { AR5K_BB_GAIN(36), 0x00000003 }, | |
1269 | { AR5K_BB_GAIN(37), 0x00000023 }, | |
1270 | { AR5K_BB_GAIN(38), 0x00000013 }, | |
1271 | { AR5K_BB_GAIN(39), 0x00000033 }, | |
1272 | { AR5K_BB_GAIN(40), 0x0000000b }, | |
1273 | { AR5K_BB_GAIN(41), 0x0000002b }, | |
1274 | { AR5K_BB_GAIN(42), 0x0000002b }, | |
1275 | { AR5K_BB_GAIN(43), 0x0000002b }, | |
1276 | { AR5K_BB_GAIN(44), 0x0000002b }, | |
1277 | { AR5K_BB_GAIN(45), 0x0000002b }, | |
1278 | { AR5K_BB_GAIN(46), 0x0000002b }, | |
1279 | { AR5K_BB_GAIN(47), 0x0000002b }, | |
1280 | { AR5K_BB_GAIN(48), 0x0000002b }, | |
1281 | { AR5K_BB_GAIN(49), 0x0000002b }, | |
1282 | { AR5K_BB_GAIN(50), 0x0000002b }, | |
1283 | { AR5K_BB_GAIN(51), 0x0000002b }, | |
1284 | { AR5K_BB_GAIN(52), 0x0000002b }, | |
1285 | { AR5K_BB_GAIN(53), 0x0000002b }, | |
1286 | { AR5K_BB_GAIN(54), 0x0000002b }, | |
1287 | { AR5K_BB_GAIN(55), 0x0000002b }, | |
1288 | { AR5K_BB_GAIN(56), 0x0000002b }, | |
1289 | { AR5K_BB_GAIN(57), 0x0000002b }, | |
1290 | { AR5K_BB_GAIN(58), 0x0000002b }, | |
1291 | { AR5K_BB_GAIN(59), 0x0000002b }, | |
1292 | { AR5K_BB_GAIN(60), 0x0000002b }, | |
1293 | { AR5K_BB_GAIN(61), 0x0000002b }, | |
1294 | { AR5K_BB_GAIN(62), 0x00000002 }, | |
1295 | { AR5K_BB_GAIN(63), 0x00000016 }, | |
1296 | }; | |
1297 | ||
a406c139 | 1298 | /* RF5112 Initial BaseBand Gain settings (Same for RF5413/5414+) */ |
fa1c114f JS |
1299 | static const struct ath5k_ini rf5112_ini_bbgain[] = { |
1300 | { AR5K_BB_GAIN(0), 0x00000000 }, | |
1301 | { AR5K_BB_GAIN(1), 0x00000001 }, | |
1302 | { AR5K_BB_GAIN(2), 0x00000002 }, | |
1303 | { AR5K_BB_GAIN(3), 0x00000003 }, | |
1304 | { AR5K_BB_GAIN(4), 0x00000004 }, | |
1305 | { AR5K_BB_GAIN(5), 0x00000005 }, | |
1306 | { AR5K_BB_GAIN(6), 0x00000008 }, | |
1307 | { AR5K_BB_GAIN(7), 0x00000009 }, | |
1308 | { AR5K_BB_GAIN(8), 0x0000000a }, | |
1309 | { AR5K_BB_GAIN(9), 0x0000000b }, | |
1310 | { AR5K_BB_GAIN(10), 0x0000000c }, | |
1311 | { AR5K_BB_GAIN(11), 0x0000000d }, | |
1312 | { AR5K_BB_GAIN(12), 0x00000010 }, | |
1313 | { AR5K_BB_GAIN(13), 0x00000011 }, | |
1314 | { AR5K_BB_GAIN(14), 0x00000012 }, | |
1315 | { AR5K_BB_GAIN(15), 0x00000013 }, | |
1316 | { AR5K_BB_GAIN(16), 0x00000014 }, | |
1317 | { AR5K_BB_GAIN(17), 0x00000015 }, | |
1318 | { AR5K_BB_GAIN(18), 0x00000018 }, | |
1319 | { AR5K_BB_GAIN(19), 0x00000019 }, | |
1320 | { AR5K_BB_GAIN(20), 0x0000001a }, | |
1321 | { AR5K_BB_GAIN(21), 0x0000001b }, | |
1322 | { AR5K_BB_GAIN(22), 0x0000001c }, | |
1323 | { AR5K_BB_GAIN(23), 0x0000001d }, | |
1324 | { AR5K_BB_GAIN(24), 0x00000020 }, | |
1325 | { AR5K_BB_GAIN(25), 0x00000021 }, | |
1326 | { AR5K_BB_GAIN(26), 0x00000022 }, | |
1327 | { AR5K_BB_GAIN(27), 0x00000023 }, | |
1328 | { AR5K_BB_GAIN(28), 0x00000024 }, | |
1329 | { AR5K_BB_GAIN(29), 0x00000025 }, | |
1330 | { AR5K_BB_GAIN(30), 0x00000028 }, | |
1331 | { AR5K_BB_GAIN(31), 0x00000029 }, | |
1332 | { AR5K_BB_GAIN(32), 0x0000002a }, | |
1333 | { AR5K_BB_GAIN(33), 0x0000002b }, | |
1334 | { AR5K_BB_GAIN(34), 0x0000002c }, | |
1335 | { AR5K_BB_GAIN(35), 0x0000002d }, | |
1336 | { AR5K_BB_GAIN(36), 0x00000030 }, | |
1337 | { AR5K_BB_GAIN(37), 0x00000031 }, | |
1338 | { AR5K_BB_GAIN(38), 0x00000032 }, | |
1339 | { AR5K_BB_GAIN(39), 0x00000033 }, | |
1340 | { AR5K_BB_GAIN(40), 0x00000034 }, | |
1341 | { AR5K_BB_GAIN(41), 0x00000035 }, | |
1342 | { AR5K_BB_GAIN(42), 0x00000035 }, | |
1343 | { AR5K_BB_GAIN(43), 0x00000035 }, | |
1344 | { AR5K_BB_GAIN(44), 0x00000035 }, | |
1345 | { AR5K_BB_GAIN(45), 0x00000035 }, | |
1346 | { AR5K_BB_GAIN(46), 0x00000035 }, | |
1347 | { AR5K_BB_GAIN(47), 0x00000035 }, | |
1348 | { AR5K_BB_GAIN(48), 0x00000035 }, | |
1349 | { AR5K_BB_GAIN(49), 0x00000035 }, | |
1350 | { AR5K_BB_GAIN(50), 0x00000035 }, | |
1351 | { AR5K_BB_GAIN(51), 0x00000035 }, | |
1352 | { AR5K_BB_GAIN(52), 0x00000035 }, | |
1353 | { AR5K_BB_GAIN(53), 0x00000035 }, | |
1354 | { AR5K_BB_GAIN(54), 0x00000035 }, | |
1355 | { AR5K_BB_GAIN(55), 0x00000035 }, | |
1356 | { AR5K_BB_GAIN(56), 0x00000035 }, | |
1357 | { AR5K_BB_GAIN(57), 0x00000035 }, | |
1358 | { AR5K_BB_GAIN(58), 0x00000035 }, | |
1359 | { AR5K_BB_GAIN(59), 0x00000035 }, | |
1360 | { AR5K_BB_GAIN(60), 0x00000035 }, | |
1361 | { AR5K_BB_GAIN(61), 0x00000035 }, | |
1362 | { AR5K_BB_GAIN(62), 0x00000010 }, | |
1363 | { AR5K_BB_GAIN(63), 0x0000001a }, | |
1364 | }; | |
1365 | ||
1366 | ||
1367 | /* | |
1368 | * Write initial register dump | |
1369 | */ | |
1370 | static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size, | |
1371 | const struct ath5k_ini *ini_regs, bool change_channel) | |
1372 | { | |
1373 | unsigned int i; | |
1374 | ||
1375 | /* Write initial registers */ | |
1376 | for (i = 0; i < size; i++) { | |
1377 | /* On channel change there is | |
1378 | * no need to mess with PCU */ | |
1379 | if (change_channel && | |
1380 | ini_regs[i].ini_register >= AR5K_PCU_MIN && | |
1381 | ini_regs[i].ini_register <= AR5K_PCU_MAX) | |
1382 | continue; | |
1383 | ||
1384 | switch (ini_regs[i].ini_mode) { | |
1385 | case AR5K_INI_READ: | |
1386 | /* Cleared on read */ | |
1387 | ath5k_hw_reg_read(ah, ini_regs[i].ini_register); | |
1388 | break; | |
1389 | case AR5K_INI_WRITE: | |
1390 | default: | |
1391 | AR5K_REG_WAIT(i); | |
1392 | ath5k_hw_reg_write(ah, ini_regs[i].ini_value, | |
1393 | ini_regs[i].ini_register); | |
1394 | } | |
1395 | } | |
1396 | } | |
1397 | ||
1398 | static void ath5k_hw_ini_mode_registers(struct ath5k_hw *ah, | |
1399 | unsigned int size, const struct ath5k_ini_mode *ini_mode, | |
1400 | u8 mode) | |
1401 | { | |
1402 | unsigned int i; | |
1403 | ||
1404 | for (i = 0; i < size; i++) { | |
1405 | AR5K_REG_WAIT(i); | |
1406 | ath5k_hw_reg_write(ah, ini_mode[i].mode_value[mode], | |
1407 | (u32)ini_mode[i].mode_register); | |
1408 | } | |
1409 | ||
1410 | } | |
1411 | ||
1412 | int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel) | |
1413 | { | |
1414 | /* | |
1415 | * Write initial register settings | |
1416 | */ | |
1417 | ||
1418 | /* For AR5212 and combatible */ | |
0bbac08f | 1419 | if (ah->ah_version == AR5K_AR5212) { |
fa1c114f JS |
1420 | |
1421 | /* First set of mode-specific settings */ | |
1422 | ath5k_hw_ini_mode_registers(ah, | |
1423 | ARRAY_SIZE(ar5212_ini_mode_start), | |
1424 | ar5212_ini_mode_start, mode); | |
1425 | ||
1426 | /* | |
1427 | * Write initial settings common for all modes | |
1428 | */ | |
a406c139 NK |
1429 | ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini_common_start), |
1430 | ar5212_ini_common_start, change_channel); | |
fa1c114f JS |
1431 | |
1432 | /* Second set of mode-specific settings */ | |
a406c139 NK |
1433 | switch (ah->ah_radio) { |
1434 | case AR5K_RF5111: | |
f714dd6d | 1435 | |
fa1c114f | 1436 | ath5k_hw_ini_mode_registers(ah, |
a406c139 NK |
1437 | ARRAY_SIZE(rf5111_ini_mode_end), |
1438 | rf5111_ini_mode_end, mode); | |
1439 | ||
1440 | ath5k_hw_ini_registers(ah, | |
1441 | ARRAY_SIZE(rf5111_ini_common_end), | |
1442 | rf5111_ini_common_end, change_channel); | |
f714dd6d | 1443 | |
fa1c114f JS |
1444 | /* Baseband gain table */ |
1445 | ath5k_hw_ini_registers(ah, | |
1446 | ARRAY_SIZE(rf5111_ini_bbgain), | |
1447 | rf5111_ini_bbgain, change_channel); | |
f714dd6d | 1448 | |
a406c139 NK |
1449 | break; |
1450 | case AR5K_RF5112: | |
f714dd6d | 1451 | |
fa1c114f | 1452 | ath5k_hw_ini_mode_registers(ah, |
a406c139 NK |
1453 | ARRAY_SIZE(rf5112_ini_mode_end), |
1454 | rf5112_ini_mode_end, mode); | |
1455 | ||
1456 | ath5k_hw_ini_registers(ah, | |
1457 | ARRAY_SIZE(rf5112_ini_common_end), | |
1458 | rf5112_ini_common_end, change_channel); | |
f714dd6d | 1459 | |
fa1c114f JS |
1460 | ath5k_hw_ini_registers(ah, |
1461 | ARRAY_SIZE(rf5112_ini_bbgain), | |
1462 | rf5112_ini_bbgain, change_channel); | |
f714dd6d | 1463 | |
a406c139 NK |
1464 | break; |
1465 | case AR5K_RF5413: | |
f714dd6d | 1466 | |
fa1c114f JS |
1467 | ath5k_hw_ini_mode_registers(ah, |
1468 | ARRAY_SIZE(rf5413_ini_mode_end), | |
1469 | rf5413_ini_mode_end, mode); | |
f714dd6d | 1470 | |
a406c139 NK |
1471 | ath5k_hw_ini_registers(ah, |
1472 | ARRAY_SIZE(rf5413_ini_common_end), | |
1473 | rf5413_ini_common_end, change_channel); | |
1474 | ||
f714dd6d NK |
1475 | ath5k_hw_ini_registers(ah, |
1476 | ARRAY_SIZE(rf5112_ini_bbgain), | |
1477 | rf5112_ini_bbgain, change_channel); | |
1478 | ||
a406c139 NK |
1479 | break; |
1480 | case AR5K_RF2316: | |
1481 | case AR5K_RF2413: | |
f714dd6d NK |
1482 | |
1483 | ath5k_hw_ini_mode_registers(ah, | |
1484 | ARRAY_SIZE(rf2413_ini_mode_end), | |
1485 | rf2413_ini_mode_end, mode); | |
1486 | ||
fa1c114f | 1487 | ath5k_hw_ini_registers(ah, |
a406c139 NK |
1488 | ARRAY_SIZE(rf2413_ini_common_end), |
1489 | rf2413_ini_common_end, change_channel); | |
136bfc79 | 1490 | |
a406c139 NK |
1491 | /* Override settings from rf2413_ini_common_end */ |
1492 | if (ah->ah_radio == AR5K_RF2316) { | |
1493 | ath5k_hw_reg_write(ah, 0x00004000, | |
1494 | AR5K_PHY_AGC); | |
1495 | ath5k_hw_reg_write(ah, 0x081b7caa, | |
1496 | 0xa274); | |
136bfc79 NK |
1497 | } |
1498 | ||
a406c139 NK |
1499 | ath5k_hw_ini_registers(ah, |
1500 | ARRAY_SIZE(rf5112_ini_bbgain), | |
1501 | rf5112_ini_bbgain, change_channel); | |
1502 | break; | |
1503 | case AR5K_RF2317: | |
1504 | case AR5K_RF2425: | |
136bfc79 NK |
1505 | |
1506 | ath5k_hw_ini_mode_registers(ah, | |
1507 | ARRAY_SIZE(rf2425_ini_mode_end), | |
1508 | rf2425_ini_mode_end, mode); | |
1509 | ||
a406c139 | 1510 | ath5k_hw_ini_registers(ah, |
504f3655 NK |
1511 | ARRAY_SIZE(rf2425_ini_common_end), |
1512 | rf2425_ini_common_end, change_channel); | |
a406c139 | 1513 | |
136bfc79 NK |
1514 | ath5k_hw_ini_registers(ah, |
1515 | ARRAY_SIZE(rf5112_ini_bbgain), | |
1516 | rf5112_ini_bbgain, change_channel); | |
a406c139 NK |
1517 | break; |
1518 | default: | |
1519 | return -EINVAL; | |
136bfc79 | 1520 | |
fa1c114f | 1521 | } |
136bfc79 | 1522 | |
fa1c114f JS |
1523 | /* For AR5211 */ |
1524 | } else if (ah->ah_version == AR5K_AR5211) { | |
1525 | ||
400ec45a LR |
1526 | /* AR5K_MODE_11B */ |
1527 | if (mode > 2) { | |
1528 | ATH5K_ERR(ah->ah_sc, | |
1529 | "unsupported channel mode: %d\n", mode); | |
fa1c114f JS |
1530 | return -EINVAL; |
1531 | } | |
1532 | ||
1533 | /* Mode-specific settings */ | |
1534 | ath5k_hw_ini_mode_registers(ah, ARRAY_SIZE(ar5211_ini_mode), | |
1535 | ar5211_ini_mode, mode); | |
1536 | ||
1537 | /* | |
1538 | * Write initial settings common for all modes | |
1539 | */ | |
1540 | ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5211_ini), | |
1541 | ar5211_ini, change_channel); | |
1542 | ||
1543 | /* AR5211 only comes with 5111 */ | |
1544 | ||
1545 | /* Baseband gain table */ | |
1546 | ath5k_hw_ini_registers(ah, ARRAY_SIZE(rf5111_ini_bbgain), | |
1547 | rf5111_ini_bbgain, change_channel); | |
1548 | /* For AR5210 (for mode settings check out ath5k_hw_reset_tx_queue) */ | |
1549 | } else if (ah->ah_version == AR5K_AR5210) { | |
1550 | ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5210_ini), | |
1551 | ar5210_ini, change_channel); | |
1552 | } | |
1553 | ||
1554 | return 0; | |
1555 | } |