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drivers/net/wireless/ath/ath5k: Change constant name
[deliverable/linux.git] / drivers / net / wireless / ath / ath5k / phy.c
CommitLineData
fa1c114f
JS		 1/*
2 * PHY functions
3 *
c6e387a2 4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
33a31826 5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
c6e387a2 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
8f655dde 7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
fa1c114f
JS		 8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 *
21 */
22
c6e387a2
NK		 23#define _ATH5K_PHY
24
fa1c114f
JS		 25#include <linux/delay.h>
26
27#include "ath5k.h"
28#include "reg.h"
29#include "base.h"
33a31826
NK		 30#include "rfbuffer.h"
31#include "rfgain.h"
fa1c114f
JS		 32
33/*
34 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
35 */
8892e4ec
NK		 36static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
37 const struct ath5k_rf_reg *rf_regs,
38 u32 val, u8 reg_id, bool set)
fa1c114f 39{
8892e4ec
NK		 40 const struct ath5k_rf_reg *rfreg = NULL;
41 u8 offset, bank, num_bits, col, position;
42 u16 entry;
43 u32 mask, data, last_bit, bits_shifted, first_bit;
44 u32 *rfb;
45 s32 bits_left;
fa1c114f
JS		 46 int i;
47
48 data = 0;
8892e4ec 49 rfb = ah->ah_rf_banks;
fa1c114f 50
8892e4ec
NK		 51 for (i = 0; i < ah->ah_rf_regs_count; i++) {
52 if (rf_regs[i].index == reg_id) {
53 rfreg = &rf_regs[i];
54 break;
55 }
56 }
57
58 if (rfb == NULL || rfreg == NULL) {
59 ATH5K_PRINTF("Rf register not found!\n");
fa1c114f
JS		 60 /* should not happen */
61 return 0;
8892e4ec
NK		 62 }
63
64 bank = rfreg->bank;
65 num_bits = rfreg->field.len;
66 first_bit = rfreg->field.pos;
67 col = rfreg->field.col;
68
69 /* first_bit is an offset from bank's
70 * start. Since we have all banks on
71 * the same array, we use this offset
72 * to mark each bank's start */
73 offset = ah->ah_offset[bank];
fa1c114f 74
8892e4ec
NK		 75 /* Boundary check */
76 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
fa1c114f
JS		 77 ATH5K_PRINTF("invalid values at offset %u\n", offset);
78 return 0;
79 }
80
8892e4ec
NK		 81 entry = ((first_bit - 1) / 8) + offset;
82 position = (first_bit - 1) % 8;
fa1c114f 83
e9010e2f 84 if (set)
8892e4ec 85 data = ath5k_hw_bitswap(val, num_bits);
fa1c114f 86
8892e4ec
NK		 87 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
88 position = 0, entry++) {
89
90 last_bit = (position + bits_left > 8) ? 8 :
91 position + bits_left;
92
93 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
94 (col * 8);
fa1c114f 95
e9010e2f 96 if (set) {
8892e4ec
NK		 97 rfb[entry] &= ~mask;
98 rfb[entry] |= ((data << position) << (col * 8)) & mask;
fa1c114f
JS		 99 data >>= (8 - position);
100 } else {
8892e4ec
NK		 101 data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
102 << bits_shifted;
103 bits_shifted += last_bit - position;
fa1c114f
JS		 104 }
105
8892e4ec 106 bits_left -= 8 - position;
fa1c114f
JS		 107 }
108
8892e4ec 109 data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
fa1c114f
JS		 110
111 return data;
112}
113
6f3b414a
NK		 114/**********************\
115* RF Gain optimization *
116\**********************/
117
118/*
119 * This code is used to optimize rf gain on different environments
120 * (temprature mostly) based on feedback from a power detector.
121 *
122 * It's only used on RF5111 and RF5112, later RF chips seem to have
123 * auto adjustment on hw -notice they have a much smaller BANK 7 and
124 * no gain optimization ladder-.
125 *
126 * For more infos check out this patent doc
127 * http://www.freepatentsonline.com/7400691.html
128 *
129 * This paper describes power drops as seen on the receiver due to
130 * probe packets
131 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
132 * %20of%20Power%20Control.pdf
133 *
134 * And this is the MadWiFi bug entry related to the above
135 * http://madwifi-project.org/ticket/1659
136 * with various measurements and diagrams
137 *
138 * TODO: Deal with power drops due to probes by setting an apropriate
139 * tx power on the probe packets ! Make this part of the calibration process.
140 */
141
142/* Initialize ah_gain durring attach */
143int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
144{
145 /* Initialize the gain optimization values */
146 switch (ah->ah_radio) {
147 case AR5K_RF5111:
148 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
149 ah->ah_gain.g_low = 20;
150 ah->ah_gain.g_high = 35;
151 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
152 break;
153 case AR5K_RF5112:
154 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
155 ah->ah_gain.g_low = 20;
156 ah->ah_gain.g_high = 85;
157 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
158 break;
159 default:
160 return -EINVAL;
161 }
162
163 return 0;
164}
165
166/* Schedule a gain probe check on the next transmited packet.
167 * That means our next packet is going to be sent with lower
168 * tx power and a Peak to Average Power Detector (PAPD) will try
169 * to measure the gain.
170 *
6f3b414a
NK		 171 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc)
172 * just after we enable the probe so that we don't mess with
173 * standard traffic ? Maybe it's time to use sw interrupts and
174 * a probe tasklet !!!
175 */
176static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
177{
178
179 /* Skip if gain calibration is inactive or
180 * we already handle a probe request */
181 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
182 return;
183
8f655dde
NK		 184 /* Send the packet with 2dB below max power as
185 * patent doc suggest */
a0823810 186 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
6f3b414a
NK		 187 AR5K_PHY_PAPD_PROBE_TXPOWER) |
188 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
189
190 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
191
192}
193
194/* Calculate gain_F measurement correction
195 * based on the current step for RF5112 rev. 2 */
196static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
fa1c114f
JS		 197{
198 u32 mix, step;
199 u32 *rf;
6f3b414a
NK		 200 const struct ath5k_gain_opt *go;
201 const struct ath5k_gain_opt_step *g_step;
8892e4ec 202 const struct ath5k_rf_reg *rf_regs;
6f3b414a
NK		 203
204 /* Only RF5112 Rev. 2 supports it */
205 if ((ah->ah_radio != AR5K_RF5112) ||
206 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
207 return 0;
208
209 go = &rfgain_opt_5112;
8892e4ec
NK		 210 rf_regs = rf_regs_5112a;
211 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
6f3b414a
NK		 212
213 g_step = &go->go_step[ah->ah_gain.g_step_idx];
fa1c114f
JS		 214
215 if (ah->ah_rf_banks == NULL)
216 return 0;
217
218 rf = ah->ah_rf_banks;
219 ah->ah_gain.g_f_corr = 0;
220
6f3b414a 221 /* No VGA (Variable Gain Amplifier) override, skip */
8892e4ec 222 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
fa1c114f
JS		 223 return 0;
224
6f3b414a 225 /* Mix gain stepping */
8892e4ec 226 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
6f3b414a
NK		 227
228 /* Mix gain override */
229 mix = g_step->gos_param[0];
fa1c114f
JS		 230
231 switch (mix) {
232 case 3:
233 ah->ah_gain.g_f_corr = step * 2;
234 break;
235 case 2:
236 ah->ah_gain.g_f_corr = (step - 5) * 2;
237 break;
238 case 1:
239 ah->ah_gain.g_f_corr = step;
240 break;
241 default:
242 ah->ah_gain.g_f_corr = 0;
243 break;
244 }
245
246 return ah->ah_gain.g_f_corr;
247}
248
6f3b414a
NK		 249/* Check if current gain_F measurement is in the range of our
250 * power detector windows. If we get a measurement outside range
251 * we know it's not accurate (detectors can't measure anything outside
252 * their detection window) so we must ignore it */
253static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
fa1c114f 254{
8892e4ec 255 const struct ath5k_rf_reg *rf_regs;
6f3b414a 256 u32 step, mix_ovr, level[4];
fa1c114f
JS		 257 u32 *rf;
258
259 if (ah->ah_rf_banks == NULL)
260 return false;
261
262 rf = ah->ah_rf_banks;
263
264 if (ah->ah_radio == AR5K_RF5111) {
8892e4ec
NK		 265
266 rf_regs = rf_regs_5111;
267 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
268
269 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
270 false);
271
fa1c114f 272 level[0] = 0;
6f3b414a
NK		 273 level[1] = (step == 63) ? 50 : step + 4;
274 level[2] = (step != 63) ? 64 : level[0];
275 level[3] = level[2] + 50 ;
fa1c114f
JS		 276
277 ah->ah_gain.g_high = level[3] -
6f3b414a 278 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
fa1c114f 279 ah->ah_gain.g_low = level[0] +
6f3b414a 280 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
fa1c114f 281 } else {
8892e4ec
NK		 282
283 rf_regs = rf_regs_5112;
284 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
285
286 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
287 false);
288
fa1c114f
JS		 289 level[0] = level[2] = 0;
290
6f3b414a 291 if (mix_ovr == 1) {
fa1c114f
JS		 292 level[1] = level[3] = 83;
293 } else {
294 level[1] = level[3] = 107;
295 ah->ah_gain.g_high = 55;
296 }
297 }
298
299 return (ah->ah_gain.g_current >= level[0] &&
300 ah->ah_gain.g_current <= level[1]) ||
301 (ah->ah_gain.g_current >= level[2] &&
302 ah->ah_gain.g_current <= level[3]);
303}
304
6f3b414a
NK		 305/* Perform gain_F adjustment by choosing the right set
306 * of parameters from rf gain optimization ladder */
307static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
fa1c114f
JS		 308{
309 const struct ath5k_gain_opt *go;
6f3b414a 310 const struct ath5k_gain_opt_step *g_step;
fa1c114f
JS		 311 int ret = 0;
312
313 switch (ah->ah_radio) {
314 case AR5K_RF5111:
315 go = &rfgain_opt_5111;
316 break;
317 case AR5K_RF5112:
fa1c114f
JS		 318 go = &rfgain_opt_5112;
319 break;
320 default:
321 return 0;
322 }
323
6f3b414a 324 g_step = &go->go_step[ah->ah_gain.g_step_idx];
fa1c114f
JS		 325
326 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
6f3b414a
NK		 327
328 /* Reached maximum */
fa1c114f
JS		 329 if (ah->ah_gain.g_step_idx == 0)
330 return -1;
6f3b414a 331
fa1c114f
JS		 332 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
333 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
334 ah->ah_gain.g_step_idx > 0;
6f3b414a 335 g_step = &go->go_step[ah->ah_gain.g_step_idx])
fa1c114f
JS		 336 ah->ah_gain.g_target -= 2 *
337 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
6f3b414a 338 g_step->gos_gain);
fa1c114f
JS		 339
340 ret = 1;
341 goto done;
342 }
343
344 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
6f3b414a
NK		 345
346 /* Reached minimum */
fa1c114f
JS		 347 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
348 return -2;
6f3b414a 349
fa1c114f
JS		 350 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
351 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
352 ah->ah_gain.g_step_idx < go->go_steps_count-1;
6f3b414a 353 g_step = &go->go_step[ah->ah_gain.g_step_idx])
fa1c114f
JS		 354 ah->ah_gain.g_target -= 2 *
355 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
6f3b414a 356 g_step->gos_gain);
fa1c114f
JS		 357
358 ret = 2;
359 goto done;
360 }
361
362done:
363 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
364 "ret %d, gain step %u, current gain %u, target gain %u\n",
365 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
366 ah->ah_gain.g_target);
367
368 return ret;
369}
370
6f3b414a
NK		 371/* Main callback for thermal rf gain calibration engine
372 * Check for a new gain reading and schedule an adjustment
373 * if needed.
374 *
375 * TODO: Use sw interrupt to schedule reset if gain_F needs
376 * adjustment */
377enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
378{
379 u32 data, type;
380 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
381
382 ATH5K_TRACE(ah->ah_sc);
383
384 if (ah->ah_rf_banks == NULL ||
385 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
386 return AR5K_RFGAIN_INACTIVE;
387
388 /* No check requested, either engine is inactive
389 * or an adjustment is already requested */
390 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
391 goto done;
392
393 /* Read the PAPD (Peak to Average Power Detector)
394 * register */
395 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
396
397 /* No probe is scheduled, read gain_F measurement */
398 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
399 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
400 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
401
402 /* If tx packet is CCK correct the gain_F measurement
403 * by cck ofdm gain delta */
404 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
405 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
406 ah->ah_gain.g_current +=
407 ee->ee_cck_ofdm_gain_delta;
408 else
409 ah->ah_gain.g_current +=
410 AR5K_GAIN_CCK_PROBE_CORR;
411 }
412
413 /* Further correct gain_F measurement for
414 * RF5112A radios */
415 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
416 ath5k_hw_rf_gainf_corr(ah);
417 ah->ah_gain.g_current =
418 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
419 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
420 0;
421 }
422
423 /* Check if measurement is ok and if we need
424 * to adjust gain, schedule a gain adjustment,
425 * else switch back to the acive state */
426 if (ath5k_hw_rf_check_gainf_readback(ah) &&
427 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
428 ath5k_hw_rf_gainf_adjust(ah)) {
429 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
430 } else {
431 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
432 }
433 }
434
435done:
436 return ah->ah_gain.g_state;
437}
438
439/* Write initial rf gain table to set the RF sensitivity
440 * this one works on all RF chips and has nothing to do
441 * with gain_F calibration */
442int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
443{
444 const struct ath5k_ini_rfgain *ath5k_rfg;
445 unsigned int i, size;
446
447 switch (ah->ah_radio) {
448 case AR5K_RF5111:
449 ath5k_rfg = rfgain_5111;
450 size = ARRAY_SIZE(rfgain_5111);
451 break;
452 case AR5K_RF5112:
453 ath5k_rfg = rfgain_5112;
454 size = ARRAY_SIZE(rfgain_5112);
455 break;
456 case AR5K_RF2413:
457 ath5k_rfg = rfgain_2413;
458 size = ARRAY_SIZE(rfgain_2413);
459 break;
460 case AR5K_RF2316:
461 ath5k_rfg = rfgain_2316;
462 size = ARRAY_SIZE(rfgain_2316);
463 break;
464 case AR5K_RF5413:
465 ath5k_rfg = rfgain_5413;
466 size = ARRAY_SIZE(rfgain_5413);
467 break;
468 case AR5K_RF2317:
469 case AR5K_RF2425:
470 ath5k_rfg = rfgain_2425;
471 size = ARRAY_SIZE(rfgain_2425);
472 break;
473 default:
474 return -EINVAL;
475 }
476
477 switch (freq) {
478 case AR5K_INI_RFGAIN_2GHZ:
479 case AR5K_INI_RFGAIN_5GHZ:
480 break;
481 default:
482 return -EINVAL;
483 }
484
485 for (i = 0; i < size; i++) {
486 AR5K_REG_WAIT(i);
487 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
488 (u32)ath5k_rfg[i].rfg_register);
489 }
490
491 return 0;
492}
493
494
495
496/********************\
497* RF Registers setup *
498\********************/
499
8892e4ec 500
fa1c114f 501/*
8892e4ec 502 * Setup RF registers by writing rf buffer on hw
fa1c114f 503 */
8892e4ec
NK		 504int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
505 unsigned int mode)
fa1c114f 506{
8892e4ec
NK		 507 const struct ath5k_rf_reg *rf_regs;
508 const struct ath5k_ini_rfbuffer *ini_rfb;
509 const struct ath5k_gain_opt *go = NULL;
510 const struct ath5k_gain_opt_step *g_step;
fa1c114f 511 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
8892e4ec
NK		 512 u8 ee_mode = 0;
513 u32 *rfb;
514 int i, obdb = -1, bank = -1;
fa1c114f 515
8892e4ec
NK		 516 switch (ah->ah_radio) {
517 case AR5K_RF5111:
518 rf_regs = rf_regs_5111;
519 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
520 ini_rfb = rfb_5111;
521 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
522 go = &rfgain_opt_5111;
523 break;
524 case AR5K_RF5112:
525 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
526 rf_regs = rf_regs_5112a;
527 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
528 ini_rfb = rfb_5112a;
529 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
530 } else {
531 rf_regs = rf_regs_5112;
532 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
533 ini_rfb = rfb_5112;
534 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
535 }
536 go = &rfgain_opt_5112;
537 break;
538 case AR5K_RF2413:
539 rf_regs = rf_regs_2413;
540 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
541 ini_rfb = rfb_2413;
542 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
543 break;
544 case AR5K_RF2316:
545 rf_regs = rf_regs_2316;
546 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
547 ini_rfb = rfb_2316;
548 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
549 break;
550 case AR5K_RF5413:
551 rf_regs = rf_regs_5413;
552 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
553 ini_rfb = rfb_5413;
554 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
555 break;
556 case AR5K_RF2317:
557 rf_regs = rf_regs_2425;
558 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
559 ini_rfb = rfb_2317;
560 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
561 break;
562 case AR5K_RF2425:
563 rf_regs = rf_regs_2425;
564 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
565 if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
566 ini_rfb = rfb_2425;
567 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
568 } else {
569 ini_rfb = rfb_2417;
570 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
571 }
572 break;
573 default:
574 return -EINVAL;
575 }
fa1c114f 576
8892e4ec
NK		 577 /* If it's the first time we set rf buffer, allocate
578 * ah->ah_rf_banks based on ah->ah_rf_banks_size
579 * we set above */
580 if (ah->ah_rf_banks == NULL) {
581 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
582 GFP_KERNEL);
583 if (ah->ah_rf_banks == NULL) {
584 ATH5K_ERR(ah->ah_sc, "out of memory\n");
585 return -ENOMEM;
586 }
587 }
fa1c114f
JS		 588
589 /* Copy values to modify them */
8892e4ec
NK		 590 rfb = ah->ah_rf_banks;
591
592 for (i = 0; i < ah->ah_rf_banks_size; i++) {
593 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
fa1c114f
JS		 594 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
595 return -EINVAL;
596 }
597
8892e4ec
NK		 598 /* Bank changed, write down the offset */
599 if (bank != ini_rfb[i].rfb_bank) {
600 bank = ini_rfb[i].rfb_bank;
fa1c114f
JS		 601 ah->ah_offset[bank] = i;
602 }
603
8892e4ec 604 rfb[i] = ini_rfb[i].rfb_mode_data[mode];
fa1c114f
JS		 605 }
606
8892e4ec 607 /* Set Output and Driver bias current (OB/DB) */
d8ee398d 608 if (channel->hw_value & CHANNEL_2GHZ) {
8892e4ec 609
d8ee398d 610 if (channel->hw_value & CHANNEL_CCK)
fa1c114f
JS		 611 ee_mode = AR5K_EEPROM_MODE_11B;
612 else
613 ee_mode = AR5K_EEPROM_MODE_11G;
fa1c114f 614
8892e4ec
NK		 615 /* For RF511X/RF211X combination we
616 * use b_OB and b_DB parameters stored
617 * in eeprom on ee->ee_ob[ee_mode][0]
618 *
619 * For all other chips we use OB/DB for 2Ghz
620 * stored in the b/g modal section just like
621 * 802.11a on ee->ee_ob[ee_mode][1] */
622 if ((ah->ah_radio == AR5K_RF5111) ||
623 (ah->ah_radio == AR5K_RF5112))
624 obdb = 0;
625 else
626 obdb = 1;
fa1c114f 627
8892e4ec
NK		 628 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
629 AR5K_RF_OB_2GHZ, true);
fa1c114f 630
8892e4ec
NK		 631 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
632 AR5K_RF_DB_2GHZ, true);
633
634 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
635 } else if ((channel->hw_value & CHANNEL_5GHZ) ||
636 (ah->ah_radio == AR5K_RF5111)) {
637
638 /* For 11a, Turbo and XR we need to choose
639 * OB/DB based on frequency range */
fa1c114f 640 ee_mode = AR5K_EEPROM_MODE_11A;
d8ee398d
LR		 641 obdb = channel->center_freq >= 5725 ? 3 :
642 (channel->center_freq >= 5500 ? 2 :
643 (channel->center_freq >= 5260 ? 1 :
644 (channel->center_freq > 4000 ? 0 : -1)));
fa1c114f 645
8892e4ec 646 if (obdb < 0)
fa1c114f
JS		 647 return -EINVAL;
648
8892e4ec
NK		 649 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
650 AR5K_RF_OB_5GHZ, true);
651
652 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
653 AR5K_RF_DB_5GHZ, true);
fa1c114f
JS		 654 }
655
8892e4ec 656 g_step = &go->go_step[ah->ah_gain.g_step_idx];
fa1c114f 657
8892e4ec
NK		 658 /* Bank Modifications (chip-specific) */
659 if (ah->ah_radio == AR5K_RF5111) {
fa1c114f 660
8892e4ec
NK		 661 /* Set gain_F settings according to current step */
662 if (channel->hw_value & CHANNEL_OFDM) {
fa1c114f 663
8892e4ec
NK		 664 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
665 AR5K_PHY_FRAME_CTL_TX_CLIP,
666 g_step->gos_param[0]);
fa1c114f 667
8892e4ec
NK		 668 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
669 AR5K_RF_PWD_90, true);
fa1c114f 670
8892e4ec
NK		 671 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
672 AR5K_RF_PWD_84, true);
fa1c114f 673
8892e4ec
NK		 674 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
675 AR5K_RF_RFGAIN_SEL, true);
fa1c114f 676
8892e4ec
NK		 677 /* We programmed gain_F parameters, switch back
678 * to active state */
679 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
6f3b414a 680
8892e4ec 681 }
fa1c114f 682
8892e4ec 683 /* Bank 6/7 setup */
fa1c114f 684
8892e4ec
NK		 685 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
686 AR5K_RF_PWD_XPD, true);
fa1c114f 687
8892e4ec
NK		 688 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
689 AR5K_RF_XPD_GAIN, true);
fa1c114f 690
8892e4ec
NK		 691 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
692 AR5K_RF_GAIN_I, true);
fa1c114f 693
8892e4ec
NK		 694 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
695 AR5K_RF_PLO_SEL, true);
fa1c114f 696
8892e4ec 697 /* TODO: Half/quarter channel support */
fa1c114f
JS		 698 }
699
8892e4ec 700 if (ah->ah_radio == AR5K_RF5112) {
fa1c114f 701
8892e4ec
NK		 702 /* Set gain_F settings according to current step */
703 if (channel->hw_value & CHANNEL_OFDM) {
fa1c114f 704
8892e4ec
NK		 705 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
706 AR5K_RF_MIXGAIN_OVR, true);
fa1c114f 707
8892e4ec
NK		 708 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
709 AR5K_RF_PWD_138, true);
e71c9fac 710
8892e4ec
NK		 711 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
712 AR5K_RF_PWD_137, true);
fa1c114f 713
8892e4ec
NK		 714 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
715 AR5K_RF_PWD_136, true);
fa1c114f 716
8892e4ec
NK		 717 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
718 AR5K_RF_PWD_132, true);
fa1c114f 719
8892e4ec
NK		 720 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
721 AR5K_RF_PWD_131, true);
fa1c114f 722
8892e4ec
NK		 723 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
724 AR5K_RF_PWD_130, true);
fa1c114f 725
8892e4ec
NK		 726 /* We programmed gain_F parameters, switch back
727 * to active state */
728 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
729 }
fa1c114f 730
8892e4ec 731 /* Bank 6/7 setup */
6f3b414a 732
8892e4ec
NK		 733 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
734 AR5K_RF_XPD_SEL, true);
6f3b414a 735
8892e4ec
NK		 736 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
737 /* Rev. 1 supports only one xpd */
738 ath5k_hw_rfb_op(ah, rf_regs,
739 ee->ee_x_gain[ee_mode],
740 AR5K_RF_XPD_GAIN, true);
fa1c114f 741
8892e4ec
NK		 742 } else {
743 /* TODO: Set high and low gain bits */
744 ath5k_hw_rfb_op(ah, rf_regs,
745 ee->ee_x_gain[ee_mode],
746 AR5K_RF_PD_GAIN_LO, true);
747 ath5k_hw_rfb_op(ah, rf_regs,
748 ee->ee_x_gain[ee_mode],
749 AR5K_RF_PD_GAIN_HI, true);
fa1c114f 750
8892e4ec
NK		 751 /* Lower synth voltage on Rev 2 */
752 ath5k_hw_rfb_op(ah, rf_regs, 2,
753 AR5K_RF_HIGH_VC_CP, true);
fa1c114f 754
8892e4ec
NK		 755 ath5k_hw_rfb_op(ah, rf_regs, 2,
756 AR5K_RF_MID_VC_CP, true);
fa1c114f 757
8892e4ec
NK		 758 ath5k_hw_rfb_op(ah, rf_regs, 2,
759 AR5K_RF_LOW_VC_CP, true);
136bfc79 760
8892e4ec
NK		 761 ath5k_hw_rfb_op(ah, rf_regs, 2,
762 AR5K_RF_PUSH_UP, true);
136bfc79 763
8892e4ec
NK		 764 /* Decrease power consumption on 5213+ BaseBand */
765 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
766 ath5k_hw_rfb_op(ah, rf_regs, 1,
767 AR5K_RF_PAD2GND, true);
136bfc79 768
8892e4ec
NK		 769 ath5k_hw_rfb_op(ah, rf_regs, 1,
770 AR5K_RF_XB2_LVL, true);
136bfc79 771
8892e4ec
NK		 772 ath5k_hw_rfb_op(ah, rf_regs, 1,
773 AR5K_RF_XB5_LVL, true);
fa1c114f 774
8892e4ec
NK		 775 ath5k_hw_rfb_op(ah, rf_regs, 1,
776 AR5K_RF_PWD_167, true);
fa1c114f 777
8892e4ec
NK		 778 ath5k_hw_rfb_op(ah, rf_regs, 1,
779 AR5K_RF_PWD_166, true);
780 }
fa1c114f
JS		 781 }
782
8892e4ec
NK		 783 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
784 AR5K_RF_GAIN_I, true);
fa1c114f 785
8892e4ec 786 /* TODO: Half/quarter channel support */
fa1c114f 787
8892e4ec 788 }
fa1c114f 789
8892e4ec
NK		 790 if (ah->ah_radio == AR5K_RF5413 &&
791 channel->hw_value & CHANNEL_2GHZ) {
fa1c114f 792
8892e4ec
NK		 793 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
794 true);
fa1c114f 795
8892e4ec
NK		 796 /* Set optimum value for early revisions (on pci-e chips) */
797 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
798 ah->ah_mac_srev < AR5K_SREV_AR5413)
799 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
800 AR5K_RF_PWD_ICLOBUF_2G, true);
fa1c114f 801
fa1c114f
JS		 802 }
803
8892e4ec
NK		 804 /* Write RF banks on hw */
805 for (i = 0; i < ah->ah_rf_banks_size; i++) {
806 AR5K_REG_WAIT(i);
807 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
808 }
fa1c114f 809
8892e4ec 810 return 0;
fa1c114f
JS		 811}
812
fa1c114f 813
fa1c114f
JS		 814/**************************\
815 PHY/RF channel functions
816\**************************/
817
818/*
819 * Check if a channel is supported
820 */
821bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
822{
823 /* Check if the channel is in our supported range */
824 if (flags & CHANNEL_2GHZ) {
825 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
826 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
827 return true;
828 } else if (flags & CHANNEL_5GHZ)
829 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
830 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
831 return true;
832
833 return false;
834}
835
836/*
837 * Convertion needed for RF5110
838 */
839static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
840{
841 u32 athchan;
842
843 /*
844 * Convert IEEE channel/MHz to an internal channel value used
845 * by the AR5210 chipset. This has not been verified with
846 * newer chipsets like the AR5212A who have a completely
847 * different RF/PHY part.
848 */
400ec45a
LR		 849 athchan = (ath5k_hw_bitswap(
850 (ieee80211_frequency_to_channel(
851 channel->center_freq) - 24) / 2, 5)
852 << 1) | (1 << 6) | 0x1;
fa1c114f
JS		 853 return athchan;
854}
855
856/*
857 * Set channel on RF5110
858 */
859static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
860 struct ieee80211_channel *channel)
861{
862 u32 data;
863
864 /*
865 * Set the channel and wait
866 */
867 data = ath5k_hw_rf5110_chan2athchan(channel);
868 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
869 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
870 mdelay(1);
871
872 return 0;
873}
874
875/*
876 * Convertion needed for 5111
877 */
878static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
879 struct ath5k_athchan_2ghz *athchan)
880{
881 int channel;
882
883 /* Cast this value to catch negative channel numbers (>= -19) */
884 channel = (int)ieee;
885
886 /*
887 * Map 2GHz IEEE channel to 5GHz Atheros channel
888 */
889 if (channel <= 13) {
890 athchan->a2_athchan = 115 + channel;
891 athchan->a2_flags = 0x46;
892 } else if (channel == 14) {
893 athchan->a2_athchan = 124;
894 athchan->a2_flags = 0x44;
895 } else if (channel >= 15 && channel <= 26) {
896 athchan->a2_athchan = ((channel - 14) * 4) + 132;
897 athchan->a2_flags = 0x46;
898 } else
899 return -EINVAL;
900
901 return 0;
902}
903
904/*
905 * Set channel on 5111
906 */
907static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
908 struct ieee80211_channel *channel)
909{
910 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
400ec45a
LR		 911 unsigned int ath5k_channel =
912 ieee80211_frequency_to_channel(channel->center_freq);
fa1c114f
JS		 913 u32 data0, data1, clock;
914 int ret;
915
916 /*
917 * Set the channel on the RF5111 radio
918 */
919 data0 = data1 = 0;
920
d8ee398d 921 if (channel->hw_value & CHANNEL_2GHZ) {
fa1c114f 922 /* Map 2GHz channel to 5GHz Atheros channel ID */
400ec45a
LR		 923 ret = ath5k_hw_rf5111_chan2athchan(
924 ieee80211_frequency_to_channel(channel->center_freq),
925 &ath5k_channel_2ghz);
fa1c114f
JS		 926 if (ret)
927 return ret;
928
929 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
930 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
931 << 5) | (1 << 4);
932 }
933
934 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
935 clock = 1;
936 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
937 (clock << 1) | (1 << 10) | 1;
938 } else {
939 clock = 0;
940 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
941 << 2) | (clock << 1) | (1 << 10) | 1;
942 }
943
944 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
945 AR5K_RF_BUFFER);
946 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
947 AR5K_RF_BUFFER_CONTROL_3);
948
949 return 0;
950}
951
952/*
953 * Set channel on 5112 and newer
954 */
955static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
956 struct ieee80211_channel *channel)
957{
958 u32 data, data0, data1, data2;
959 u16 c;
960
961 data = data0 = data1 = data2 = 0;
d8ee398d 962 c = channel->center_freq;
fa1c114f 963
fa1c114f
JS		 964 if (c < 4800) {
965 if (!((c - 2224) % 5)) {
966 data0 = ((2 * (c - 704)) - 3040) / 10;
967 data1 = 1;
968 } else if (!((c - 2192) % 5)) {
969 data0 = ((2 * (c - 672)) - 3040) / 10;
970 data1 = 0;
971 } else
972 return -EINVAL;
973
974 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
cc6323c7 975 } else if ((c - (c % 5)) != 2 || c > 5435) {
fa1c114f
JS		 976 if (!(c % 20) && c >= 5120) {
977 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
978 data2 = ath5k_hw_bitswap(3, 2);
979 } else if (!(c % 10)) {
980 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
981 data2 = ath5k_hw_bitswap(2, 2);
982 } else if (!(c % 5)) {
983 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
984 data2 = ath5k_hw_bitswap(1, 2);
985 } else
986 return -EINVAL;
cc6323c7
NK		 987 } else {
988 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
989 data2 = ath5k_hw_bitswap(0, 2);
fa1c114f
JS		 990 }
991
992 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
993
994 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
995 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
996
997 return 0;
998}
999
cc6323c7
NK		 1000/*
1001 * Set the channel on the RF2425
1002 */
1003static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1004 struct ieee80211_channel *channel)
1005{
1006 u32 data, data0, data2;
1007 u16 c;
1008
1009 data = data0 = data2 = 0;
1010 c = channel->center_freq;
1011
1012 if (c < 4800) {
1013 data0 = ath5k_hw_bitswap((c - 2272), 8);
1014 data2 = 0;
1015 /* ? 5GHz ? */
1016 } else if ((c - (c % 5)) != 2 || c > 5435) {
1017 if (!(c % 20) && c < 5120)
1018 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1019 else if (!(c % 10))
1020 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1021 else if (!(c % 5))
1022 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1023 else
1024 return -EINVAL;
1025 data2 = ath5k_hw_bitswap(1, 2);
1026 } else {
1027 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
1028 data2 = ath5k_hw_bitswap(0, 2);
1029 }
1030
1031 data = (data0 << 4) | data2 << 2 | 0x1001;
1032
1033 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1034 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1035
1036 return 0;
1037}
1038
fa1c114f
JS		 1039/*
1040 * Set a channel on the radio chip
1041 */
1042int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
1043{
1044 int ret;
fa1c114f 1045 /*
400ec45a
LR		 1046 * Check bounds supported by the PHY (we don't care about regultory
1047 * restrictions at this point). Note: hw_value already has the band
1048 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1049 * of the band by that */
1050 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
fa1c114f 1051 ATH5K_ERR(ah->ah_sc,
400ec45a
LR		 1052 "channel frequency (%u MHz) out of supported "
1053 "band range\n",
d8ee398d 1054 channel->center_freq);
400ec45a 1055 return -EINVAL;
fa1c114f
JS		 1056 }
1057
1058 /*
1059 * Set the channel and wait
1060 */
1061 switch (ah->ah_radio) {
1062 case AR5K_RF5110:
1063 ret = ath5k_hw_rf5110_channel(ah, channel);
1064 break;
1065 case AR5K_RF5111:
1066 ret = ath5k_hw_rf5111_channel(ah, channel);
1067 break;
cc6323c7
NK		 1068 case AR5K_RF2425:
1069 ret = ath5k_hw_rf2425_channel(ah, channel);
1070 break;
fa1c114f
JS		 1071 default:
1072 ret = ath5k_hw_rf5112_channel(ah, channel);
1073 break;
1074 }
1075
1076 if (ret)
1077 return ret;
1078
cc6323c7
NK		 1079 /* Set JAPAN setting for channel 14 */
1080 if (channel->center_freq == 2484) {
1081 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1082 AR5K_PHY_CCKTXCTL_JAPAN);
1083 } else {
1084 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1085 AR5K_PHY_CCKTXCTL_WORLD);
1086 }
1087
46026e8f 1088 ah->ah_current_channel = channel;
d8ee398d 1089 ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
fa1c114f
JS		 1090
1091 return 0;
1092}
1093
1094/*****************\
1095 PHY calibration
1096\*****************/
1097
1098/**
1099 * ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration
1100 *
1101 * @ah: struct ath5k_hw pointer we are operating on
1102 * @freq: the channel frequency, just used for error logging
1103 *
1104 * This function performs a noise floor calibration of the PHY and waits for
1105 * it to complete. Then the noise floor value is compared to some maximum
1106 * noise floor we consider valid.
1107 *
1108 * Note that this is different from what the madwifi HAL does: it reads the
1109 * noise floor and afterwards initiates the calibration. Since the noise floor
1110 * calibration can take some time to finish, depending on the current channel
1111 * use, that avoids the occasional timeout warnings we are seeing now.
1112 *
1113 * See the following link for an Atheros patent on noise floor calibration:
1114 * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \
1115 * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7
1116 *
f860ee26
NK		 1117 * XXX: Since during noise floor calibration antennas are detached according to
1118 * the patent, we should stop tx queues here.
fa1c114f
JS		 1119 */
1120int
1121ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq)
1122{
1123 int ret;
1124 unsigned int i;
1125 s32 noise_floor;
1126
1127 /*
f860ee26 1128 * Enable noise floor calibration
fa1c114f
JS		 1129 */
1130 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1131 AR5K_PHY_AGCCTL_NF);
1132
1133 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1134 AR5K_PHY_AGCCTL_NF, 0, false);
1135 if (ret) {
1136 ATH5K_ERR(ah->ah_sc,
1137 "noise floor calibration timeout (%uMHz)\n", freq);
f860ee26 1138 return -EAGAIN;
fa1c114f
JS		 1139 }
1140
1141 /* Wait until the noise floor is calibrated and read the value */
1142 for (i = 20; i > 0; i--) {
1143 mdelay(1);
1144 noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1145 noise_floor = AR5K_PHY_NF_RVAL(noise_floor);
1146 if (noise_floor & AR5K_PHY_NF_ACTIVE) {
1147 noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
1148
1149 if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
1150 break;
1151 }
1152 }
1153
1154 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1155 "noise floor %d\n", noise_floor);
1156
1157 if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
1158 ATH5K_ERR(ah->ah_sc,
1159 "noise floor calibration failed (%uMHz)\n", freq);
f860ee26 1160 return -EAGAIN;
fa1c114f
JS		 1161 }
1162
1163 ah->ah_noise_floor = noise_floor;
1164
1165 return 0;
1166}
1167
1168/*
1169 * Perform a PHY calibration on RF5110
1170 * -Fix BPSK/QAM Constellation (I/Q correction)
1171 * -Calculate Noise Floor
1172 */
1173static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1174 struct ieee80211_channel *channel)
1175{
1176 u32 phy_sig, phy_agc, phy_sat, beacon;
1177 int ret;
1178
1179 /*
1180 * Disable beacons and RX/TX queues, wait
1181 */
1182 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1183 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1184 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1185 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1186
84e463fa 1187 mdelay(2);
fa1c114f
JS		 1188
1189 /*
1190 * Set the channel (with AGC turned off)
1191 */
1192 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1193 udelay(10);
1194 ret = ath5k_hw_channel(ah, channel);
1195
1196 /*
1197 * Activate PHY and wait
1198 */
1199 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1200 mdelay(1);
1201
1202 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1203
1204 if (ret)
1205 return ret;
1206
1207 /*
1208 * Calibrate the radio chip
1209 */
1210
1211 /* Remember normal state */
1212 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1213 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1214 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1215
1216 /* Update radio registers */
1217 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1218 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1219
1220 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1221 AR5K_PHY_AGCCOARSE_LO)) |
1222 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1223 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1224
1225 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1226 AR5K_PHY_ADCSAT_THR)) |
1227 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1228 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1229
1230 udelay(20);
1231
1232 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1233 udelay(10);
1234 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1235 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1236
1237 mdelay(1);
1238
1239 /*
1240 * Enable calibration and wait until completion
1241 */
1242 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1243
1244 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1245 AR5K_PHY_AGCCTL_CAL, 0, false);
1246
1247 /* Reset to normal state */
1248 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1249 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1250 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1251
1252 if (ret) {
1253 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
d8ee398d 1254 channel->center_freq);
fa1c114f
JS		 1255 return ret;
1256 }
1257
8b0162a3 1258 ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
fa1c114f
JS		 1259
1260 /*
1261 * Re-enable RX/TX and beacons
1262 */
1263 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1264 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1265 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1266
1267 return 0;
1268}
1269
1270/*
f860ee26 1271 * Perform a PHY calibration on RF5111/5112 and newer chips
fa1c114f
JS		 1272 */
1273static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
1274 struct ieee80211_channel *channel)
1275{
1276 u32 i_pwr, q_pwr;
1277 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
f860ee26 1278 int i;
fa1c114f
JS		 1279 ATH5K_TRACE(ah->ah_sc);
1280
e9010e2f 1281 if (!ah->ah_calibration ||
f860ee26 1282 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
fa1c114f
JS		 1283 goto done;
1284
f860ee26
NK		 1285 /* Calibration has finished, get the results and re-run */
1286 for (i = 0; i <= 10; i++) {
1287 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1288 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1289 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1290 }
fa1c114f 1291
fa1c114f 1292 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
f860ee26 1293 q_coffd = q_pwr >> 7;
fa1c114f 1294
f860ee26 1295 /* No correction */
fa1c114f
JS		 1296 if (i_coffd == 0 || q_coffd == 0)
1297 goto done;
1298
1299 i_coff = ((-iq_corr) / i_coffd) & 0x3f;
fa1c114f 1300
f860ee26
NK		 1301 /* Boundary check */
1302 if (i_coff > 31)
1303 i_coff = 31;
1304 if (i_coff < -32)
1305 i_coff = -32;
1306
1307 q_coff = (((s32)i_pwr / q_coffd) - 128) & 0x1f;
1308
1309 /* Boundary check */
1310 if (q_coff > 15)
1311 q_coff = 15;
1312 if (q_coff < -16)
1313 q_coff = -16;
1314
1315 /* Commit new I/Q value */
fa1c114f
JS		 1316 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE |
1317 ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
1318
f860ee26
NK		 1319 /* Re-enable calibration -if we don't we'll commit
1320 * the same values again and again */
1321 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1322 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1323 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
1324
fa1c114f 1325done:
f860ee26
NK		 1326
1327 /* TODO: Separate noise floor calibration from I/Q calibration
1328 * since noise floor calibration interrupts rx path while I/Q
1329 * calibration doesn't. We don't need to run noise floor calibration
1330 * as often as I/Q calibration.*/
d8ee398d 1331 ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
fa1c114f 1332
6f3b414a
NK		 1333 /* Initiate a gain_F calibration */
1334 ath5k_hw_request_rfgain_probe(ah);
fa1c114f
JS		 1335
1336 return 0;
1337}
1338
1339/*
1340 * Perform a PHY calibration
1341 */
1342int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1343 struct ieee80211_channel *channel)
1344{
1345 int ret;
1346
1347 if (ah->ah_radio == AR5K_RF5110)
1348 ret = ath5k_hw_rf5110_calibrate(ah, channel);
1349 else
1350 ret = ath5k_hw_rf511x_calibrate(ah, channel);
1351
1352 return ret;
1353}
1354
57e6c56d
NK		 1355/***************************\
1356* Spur mitigation functions *
1357\***************************/
1358
1359bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1360 struct ieee80211_channel *channel)
1361{
1362 u8 refclk_freq;
1363
1364 if ((ah->ah_radio == AR5K_RF5112) ||
1365 (ah->ah_radio == AR5K_RF5413) ||
1366 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
1367 refclk_freq = 40;
1368 else
1369 refclk_freq = 32;
1370
1371 if ((channel->center_freq % refclk_freq != 0) &&
1372 ((channel->center_freq % refclk_freq < 10) ||
1373 (channel->center_freq % refclk_freq > 22)))
1374 return true;
1375 else
1376 return false;
1377}
1378
1379void
1380ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1381 struct ieee80211_channel *channel)
1382{
1383 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1384 u32 mag_mask[4] = {0, 0, 0, 0};
1385 u32 pilot_mask[2] = {0, 0};
1386 /* Note: fbin values are scaled up by 2 */
1387 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
1388 s32 spur_delta_phase, spur_freq_sigma_delta;
1389 s32 spur_offset, num_symbols_x16;
1390 u8 num_symbol_offsets, i, freq_band;
1391
1392 /* Convert current frequency to fbin value (the same way channels
1393 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
1394 * up by 2 so we can compare it later */
1395 if (channel->hw_value & CHANNEL_2GHZ) {
1396 chan_fbin = (channel->center_freq - 2300) * 10;
1397 freq_band = AR5K_EEPROM_BAND_2GHZ;
1398 } else {
1399 chan_fbin = (channel->center_freq - 4900) * 10;
1400 freq_band = AR5K_EEPROM_BAND_5GHZ;
1401 }
1402
1403 /* Check if any spur_chan_fbin from EEPROM is
1404 * within our current channel's spur detection range */
1405 spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
1406 spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
1407 /* XXX: Half/Quarter channels ?*/
1408 if (channel->hw_value & CHANNEL_TURBO)
1409 spur_detection_window *= 2;
1410
1411 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1412 spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
1413
1414 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
1415 * so it's zero if we got nothing from EEPROM */
1416 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
1417 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1418 break;
1419 }
1420
1421 if ((chan_fbin - spur_detection_window <=
1422 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
1423 (chan_fbin + spur_detection_window >=
1424 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
1425 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1426 break;
1427 }
1428 }
1429
1430 /* We need to enable spur filter for this channel */
1431 if (spur_chan_fbin) {
1432 spur_offset = spur_chan_fbin - chan_fbin;
1433 /*
1434 * Calculate deltas:
1435 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
1436 * spur_delta_phase -> spur_offset / chip_freq << 11
1437 * Note: Both values have 100KHz resolution
1438 */
1439 /* XXX: Half/Quarter rate channels ? */
1440 switch (channel->hw_value) {
1441 case CHANNEL_A:
1442 /* Both sample_freq and chip_freq are 40MHz */
1443 spur_delta_phase = (spur_offset << 17) / 25;
1444 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1445 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1446 break;
1447 case CHANNEL_G:
1448 /* sample_freq -> 40MHz chip_freq -> 44MHz
1449 * (for b compatibility) */
1450 spur_freq_sigma_delta = (spur_offset << 8) / 55;
1451 spur_delta_phase = (spur_offset << 17) / 25;
1452 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1453 break;
1454 case CHANNEL_T:
1455 case CHANNEL_TG:
1456 /* Both sample_freq and chip_freq are 80MHz */
1457 spur_delta_phase = (spur_offset << 16) / 25;
1458 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1459 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz;
1460 break;
1461 default:
1462 return;
1463 }
1464
1465 /* Calculate pilot and magnitude masks */
1466
1467 /* Scale up spur_offset by 1000 to switch to 100HZ resolution
1468 * and divide by symbol_width to find how many symbols we have
1469 * Note: number of symbols is scaled up by 16 */
1470 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
1471
1472 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
1473 if (!(num_symbols_x16 & 0xF))
1474 /* _X_ */
1475 num_symbol_offsets = 3;
1476 else
1477 /* _xx_ */
1478 num_symbol_offsets = 4;
1479
1480 for (i = 0; i < num_symbol_offsets; i++) {
1481
1482 /* Calculate pilot mask */
1483 s32 curr_sym_off =
1484 (num_symbols_x16 / 16) + i + 25;
1485
1486 /* Pilot magnitude mask seems to be a way to
1487 * declare the boundaries for our detection
1488 * window or something, it's 2 for the middle
1489 * value(s) where the symbol is expected to be
1490 * and 1 on the boundary values */
1491 u8 plt_mag_map =
1492 (i == 0 || i == (num_symbol_offsets - 1))
1493 ? 1 : 2;
1494
1495 if (curr_sym_off >= 0 && curr_sym_off <= 32) {
1496 if (curr_sym_off <= 25)
1497 pilot_mask[0] |= 1 << curr_sym_off;
1498 else if (curr_sym_off >= 27)
1499 pilot_mask[0] |= 1 << (curr_sym_off - 1);
1500 } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
1501 pilot_mask[1] |= 1 << (curr_sym_off - 33);
1502
1503 /* Calculate magnitude mask (for viterbi decoder) */
1504 if (curr_sym_off >= -1 && curr_sym_off <= 14)
1505 mag_mask[0] |=
1506 plt_mag_map << (curr_sym_off + 1) * 2;
1507 else if (curr_sym_off >= 15 && curr_sym_off <= 30)
1508 mag_mask[1] |=
1509 plt_mag_map << (curr_sym_off - 15) * 2;
1510 else if (curr_sym_off >= 31 && curr_sym_off <= 46)
1511 mag_mask[2] |=
1512 plt_mag_map << (curr_sym_off - 31) * 2;
1513 else if (curr_sym_off >= 46 && curr_sym_off <= 53)
1514 mag_mask[3] |=
1515 plt_mag_map << (curr_sym_off - 47) * 2;
1516
1517 }
1518
1519 /* Write settings on hw to enable spur filter */
1520 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1521 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
1522 /* XXX: Self correlator also ? */
1523 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1524 AR5K_PHY_IQ_PILOT_MASK_EN |
1525 AR5K_PHY_IQ_CHAN_MASK_EN |
1526 AR5K_PHY_IQ_SPUR_FILT_EN);
1527
1528 /* Set delta phase and freq sigma delta */
1529 ath5k_hw_reg_write(ah,
1530 AR5K_REG_SM(spur_delta_phase,
1531 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
1532 AR5K_REG_SM(spur_freq_sigma_delta,
1533 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
1534 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
1535 AR5K_PHY_TIMING_11);
1536
1537 /* Write pilot masks */
1538 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
1539 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1540 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1541 pilot_mask[1]);
1542
1543 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
1544 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1545 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1546 pilot_mask[1]);
1547
1548 /* Write magnitude masks */
1549 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
1550 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
1551 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
1552 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1553 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1554 mag_mask[3]);
1555
1556 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
1557 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
1558 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
1559 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1560 AR5K_PHY_BIN_MASK2_4_MASK_4,
1561 mag_mask[3]);
1562
1563 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
1564 AR5K_PHY_IQ_SPUR_FILT_EN) {
1565 /* Clean up spur mitigation settings and disable fliter */
1566 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1567 AR5K_PHY_BIN_MASK_CTL_RATE, 0);
1568 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
1569 AR5K_PHY_IQ_PILOT_MASK_EN |
1570 AR5K_PHY_IQ_CHAN_MASK_EN |
1571 AR5K_PHY_IQ_SPUR_FILT_EN);
1572 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
1573
1574 /* Clear pilot masks */
1575 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
1576 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1577 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1578 0);
1579
1580 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
1581 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1582 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1583 0);
1584
1585 /* Clear magnitude masks */
1586 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
1587 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
1588 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
1589 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1590 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1591 0);
1592
1593 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
1594 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
1595 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
1596 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1597 AR5K_PHY_BIN_MASK2_4_MASK_4,
1598 0);
1599 }
1600}
1601
1602/********************\
1603 Misc PHY functions
1604\********************/
1605
fa1c114f
JS		 1606int ath5k_hw_phy_disable(struct ath5k_hw *ah)
1607{
1608 ATH5K_TRACE(ah->ah_sc);
1609 /*Just a try M.F.*/
1610 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
1611
1612 return 0;
1613}
1614
fa1c114f
JS		 1615/*
1616 * Get the PHY Chip revision
1617 */
1618u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
1619{
1620 unsigned int i;
1621 u32 srev;
1622 u16 ret;
1623
1624 ATH5K_TRACE(ah->ah_sc);
1625
1626 /*
1627 * Set the radio chip access register
1628 */
1629 switch (chan) {
1630 case CHANNEL_2GHZ:
1631 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
1632 break;
1633 case CHANNEL_5GHZ:
1634 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1635 break;
1636 default:
1637 return 0;
1638 }
1639
1640 mdelay(2);
1641
1642 /* ...wait until PHY is ready and read the selected radio revision */
1643 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
1644
1645 for (i = 0; i < 8; i++)
1646 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
1647
1648 if (ah->ah_version == AR5K_AR5210) {
1649 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
1650 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
1651 } else {
1652 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
1653 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
1654 ((srev & 0x0f) << 4), 8);
1655 }
1656
1657 /* Reset to the 5GHz mode */
1658 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1659
1660 return ret;
1661}
1662
2bed03eb
NK		 1663/*****************\
1664* Antenna control *
1665\*****************/
1666
fa1c114f 1667void /*TODO:Boundary check*/
2bed03eb 1668ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
fa1c114f
JS		 1669{
1670 ATH5K_TRACE(ah->ah_sc);
2bed03eb 1671
fa1c114f 1672 if (ah->ah_version != AR5K_AR5210)
2bed03eb 1673 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
fa1c114f
JS		 1674}
1675
1676unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah)
1677{
1678 ATH5K_TRACE(ah->ah_sc);
2bed03eb 1679
fa1c114f 1680 if (ah->ah_version != AR5K_AR5210)
2bed03eb 1681 return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA) & 0x7;
fa1c114f
JS		 1682
1683 return false; /*XXX: What do we return for 5210 ?*/
1684}
1685
2bed03eb
NK		 1686/*
1687 * Enable/disable fast rx antenna diversity
1688 */
1689static void
1690ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
1691{
1692 switch (ee_mode) {
1693 case AR5K_EEPROM_MODE_11G:
1694 /* XXX: This is set to
1695 * disabled on initvals !!! */
1696 case AR5K_EEPROM_MODE_11A:
1697 if (enable)
1698 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
1699 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1700 else
1701 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1702 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1703 break;
1704 case AR5K_EEPROM_MODE_11B:
1705 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1706 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1707 break;
1708 default:
1709 return;
1710 }
1711
1712 if (enable) {
1713 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1714 AR5K_PHY_RESTART_DIV_GC, 0xc);
1715
1716 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1717 AR5K_PHY_FAST_ANT_DIV_EN);
1718 } else {
1719 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1720 AR5K_PHY_RESTART_DIV_GC, 0x8);
1721
1722 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1723 AR5K_PHY_FAST_ANT_DIV_EN);
1724 }
1725}
1726
1727/*
1728 * Set antenna operating mode
1729 */
1730void
1731ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
1732{
46026e8f 1733 struct ieee80211_channel *channel = ah->ah_current_channel;
2bed03eb
NK		 1734 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
1735 bool use_def_for_sg;
1736 u8 def_ant, tx_ant, ee_mode;
1737 u32 sta_id1 = 0;
1738
1739 def_ant = ah->ah_def_ant;
1740
1741 ATH5K_TRACE(ah->ah_sc);
1742
1743 switch (channel->hw_value & CHANNEL_MODES) {
1744 case CHANNEL_A:
1745 case CHANNEL_T:
1746 case CHANNEL_XR:
1747 ee_mode = AR5K_EEPROM_MODE_11A;
1748 break;
1749 case CHANNEL_G:
1750 case CHANNEL_TG:
1751 ee_mode = AR5K_EEPROM_MODE_11G;
1752 break;
1753 case CHANNEL_B:
1754 ee_mode = AR5K_EEPROM_MODE_11B;
1755 break;
1756 default:
1757 ATH5K_ERR(ah->ah_sc,
1758 "invalid channel: %d\n", channel->center_freq);
1759 return;
1760 }
1761
1762 switch (ant_mode) {
1763 case AR5K_ANTMODE_DEFAULT:
1764 tx_ant = 0;
1765 use_def_for_tx = false;
1766 update_def_on_tx = false;
1767 use_def_for_rts = false;
1768 use_def_for_sg = false;
1769 fast_div = true;
1770 break;
1771 case AR5K_ANTMODE_FIXED_A:
1772 def_ant = 1;
1773 tx_ant = 0;
1774 use_def_for_tx = true;
1775 update_def_on_tx = false;
1776 use_def_for_rts = true;
1777 use_def_for_sg = true;
1778 fast_div = false;
1779 break;
1780 case AR5K_ANTMODE_FIXED_B:
1781 def_ant = 2;
1782 tx_ant = 0;
1783 use_def_for_tx = true;
1784 update_def_on_tx = false;
1785 use_def_for_rts = true;
1786 use_def_for_sg = true;
1787 fast_div = false;
1788 break;
1789 case AR5K_ANTMODE_SINGLE_AP:
1790 def_ant = 1; /* updated on tx */
1791 tx_ant = 0;
1792 use_def_for_tx = true;
1793 update_def_on_tx = true;
1794 use_def_for_rts = true;
1795 use_def_for_sg = true;
1796 fast_div = true;
1797 break;
1798 case AR5K_ANTMODE_SECTOR_AP:
1799 tx_ant = 1; /* variable */
1800 use_def_for_tx = false;
1801 update_def_on_tx = false;
1802 use_def_for_rts = true;
1803 use_def_for_sg = false;
1804 fast_div = false;
1805 break;
1806 case AR5K_ANTMODE_SECTOR_STA:
1807 tx_ant = 1; /* variable */
1808 use_def_for_tx = true;
1809 update_def_on_tx = false;
1810 use_def_for_rts = true;
1811 use_def_for_sg = false;
1812 fast_div = true;
1813 break;
1814 case AR5K_ANTMODE_DEBUG:
1815 def_ant = 1;
1816 tx_ant = 2;
1817 use_def_for_tx = false;
1818 update_def_on_tx = false;
1819 use_def_for_rts = false;
1820 use_def_for_sg = false;
1821 fast_div = false;
1822 break;
1823 default:
1824 return;
1825 }
1826
1827 ah->ah_tx_ant = tx_ant;
1828 ah->ah_ant_mode = ant_mode;
1829
1830 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
1831 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
1832 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
1833 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
1834
1835 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
1836
1837 if (sta_id1)
1838 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
1839
1840 /* Note: set diversity before default antenna
1841 * because it won't work correctly */
1842 ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
1843 ath5k_hw_set_def_antenna(ah, def_ant);
1844}
1845
8f655dde
NK		 1846
1847/****************\
1848* TX power setup *
1849\****************/
1850
1851/*
1852 * Helper functions
1853 */
1854
1855/*
1856 * Do linear interpolation between two given (x, y) points
1857 */
1858static s16
1859ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
1860 s16 y_left, s16 y_right)
1861{
1862 s16 ratio, result;
1863
1864 /* Avoid divide by zero and skip interpolation
1865 * if we have the same point */
1866 if ((x_left == x_right) || (y_left == y_right))
1867 return y_left;
1868
1869 /*
1870 * Since we use ints and not fps, we need to scale up in
1871 * order to get a sane ratio value (or else we 'll eg. get
1872 * always 1 instead of 1.25, 1.75 etc). We scale up by 100
1873 * to have some accuracy both for 0.5 and 0.25 steps.
1874 */
1875 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left));
1876
1877 /* Now scale down to be in range */
1878 result = y_left + (ratio * (target - x_left) / 100);
1879
1880 return result;
1881}
1882
1883/*
1884 * Find vertical boundary (min pwr) for the linear PCDAC curve.
1885 *
1886 * Since we have the top of the curve and we draw the line below
1887 * until we reach 1 (1 pcdac step) we need to know which point
1888 * (x value) that is so that we don't go below y axis and have negative
1889 * pcdac values when creating the curve, or fill the table with zeroes.
1890 */
1891static s16
1892ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
1893 const s16 *pwrL, const s16 *pwrR)
1894{
1895 s8 tmp;
1896 s16 min_pwrL, min_pwrR;
64cdb0e3
FR		 1897 s16 pwr_i;
1898
9c8b3edd
BC		 1899 if (WARN_ON(stepL[0] == stepL[1] || stepR[0] == stepR[1]))
1900 return 0;
1901
64cdb0e3
FR		 1902 if (pwrL[0] == pwrL[1])
1903 min_pwrL = pwrL[0];
1904 else {
1905 pwr_i = pwrL[0];
1906 do {
1907 pwr_i--;
1908 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
1909 pwrL[0], pwrL[1],
1910 stepL[0], stepL[1]);
1911 } while (tmp > 1);
1912
1913 min_pwrL = pwr_i;
1914 }
8f655dde 1915
64cdb0e3
FR		 1916 if (pwrR[0] == pwrR[1])
1917 min_pwrR = pwrR[0];
1918 else {
1919 pwr_i = pwrR[0];
1920 do {
1921 pwr_i--;
1922 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
1923 pwrR[0], pwrR[1],
1924 stepR[0], stepR[1]);
1925 } while (tmp > 1);
1926
1927 min_pwrR = pwr_i;
1928 }
8f655dde
NK		 1929
1930 /* Keep the right boundary so that it works for both curves */
1931 return max(min_pwrL, min_pwrR);
1932}
1933
1934/*
1935 * Interpolate (pwr,vpd) points to create a Power to PDADC or a
1936 * Power to PCDAC curve.
1937 *
1938 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
1939 * steps (offsets) on y axis. Power can go up to 31.5dB and max
1940 * PCDAC/PDADC step for each curve is 64 but we can write more than
1941 * one curves on hw so we can go up to 128 (which is the max step we
1942 * can write on the final table).
1943 *
1944 * We write y values (PCDAC/PDADC steps) on hw.
1945 */
1946static void
1947ath5k_create_power_curve(s16 pmin, s16 pmax,
1948 const s16 *pwr, const u8 *vpd,
1949 u8 num_points,
1950 u8 *vpd_table, u8 type)
1951{
1952 u8 idx[2] = { 0, 1 };
1953 s16 pwr_i = 2*pmin;
1954 int i;
1955
1956 if (num_points < 2)
1957 return;
1958
1959 /* We want the whole line, so adjust boundaries
1960 * to cover the entire power range. Note that
1961 * power values are already 0.25dB so no need
1962 * to multiply pwr_i by 2 */
1963 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
1964 pwr_i = pmin;
1965 pmin = 0;
1966 pmax = 63;
1967 }
1968
1969 /* Find surrounding turning points (TPs)
1970 * and interpolate between them */
1971 for (i = 0; (i <= (u16) (pmax - pmin)) &&
1972 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
1973
1974 /* We passed the right TP, move to the next set of TPs
1975 * if we pass the last TP, extrapolate above using the last
1976 * two TPs for ratio */
1977 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
1978 idx[0]++;
1979 idx[1]++;
1980 }
1981
1982 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
1983 pwr[idx[0]], pwr[idx[1]],
1984 vpd[idx[0]], vpd[idx[1]]);
1985
1986 /* Increase by 0.5dB
1987 * (0.25 dB units) */
1988 pwr_i += 2;
1989 }
1990}
1991
1992/*
1993 * Get the surrounding per-channel power calibration piers
1994 * for a given frequency so that we can interpolate between
1995 * them and come up with an apropriate dataset for our current
1996 * channel.
1997 */
1998static void
1999ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
2000 struct ieee80211_channel *channel,
2001 struct ath5k_chan_pcal_info **pcinfo_l,
2002 struct ath5k_chan_pcal_info **pcinfo_r)
2003{
2004 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2005 struct ath5k_chan_pcal_info *pcinfo;
2006 u8 idx_l, idx_r;
2007 u8 mode, max, i;
2008 u32 target = channel->center_freq;
2009
2010 idx_l = 0;
2011 idx_r = 0;
2012
2013 if (!(channel->hw_value & CHANNEL_OFDM)) {
2014 pcinfo = ee->ee_pwr_cal_b;
2015 mode = AR5K_EEPROM_MODE_11B;
2016 } else if (channel->hw_value & CHANNEL_2GHZ) {
2017 pcinfo = ee->ee_pwr_cal_g;
2018 mode = AR5K_EEPROM_MODE_11G;
2019 } else {
2020 pcinfo = ee->ee_pwr_cal_a;
2021 mode = AR5K_EEPROM_MODE_11A;
2022 }
2023 max = ee->ee_n_piers[mode] - 1;
2024
2025 /* Frequency is below our calibrated
2026 * range. Use the lowest power curve
2027 * we have */
2028 if (target < pcinfo[0].freq) {
2029 idx_l = idx_r = 0;
2030 goto done;
2031 }
2032
2033 /* Frequency is above our calibrated
2034 * range. Use the highest power curve
2035 * we have */
2036 if (target > pcinfo[max].freq) {
2037 idx_l = idx_r = max;
2038 goto done;
2039 }
2040
2041 /* Frequency is inside our calibrated
2042 * channel range. Pick the surrounding
2043 * calibration piers so that we can
2044 * interpolate */
2045 for (i = 0; i <= max; i++) {
2046
2047 /* Frequency matches one of our calibration
2048 * piers, no need to interpolate, just use
2049 * that calibration pier */
2050 if (pcinfo[i].freq == target) {
2051 idx_l = idx_r = i;
2052 goto done;
2053 }
2054
2055 /* We found a calibration pier that's above
2056 * frequency, use this pier and the previous
2057 * one to interpolate */
2058 if (target < pcinfo[i].freq) {
2059 idx_r = i;
2060 idx_l = idx_r - 1;
2061 goto done;
2062 }
2063 }
2064
2065done:
2066 *pcinfo_l = &pcinfo[idx_l];
2067 *pcinfo_r = &pcinfo[idx_r];
2068
2069 return;
2070}
2071
2072/*
2073 * Get the surrounding per-rate power calibration data
2074 * for a given frequency and interpolate between power
2075 * values to set max target power supported by hw for
2076 * each rate.
2077 */
2078static void
2079ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
2080 struct ieee80211_channel *channel,
2081 struct ath5k_rate_pcal_info *rates)
2082{
2083 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2084 struct ath5k_rate_pcal_info *rpinfo;
2085 u8 idx_l, idx_r;
2086 u8 mode, max, i;
2087 u32 target = channel->center_freq;
2088
2089 idx_l = 0;
2090 idx_r = 0;
2091
2092 if (!(channel->hw_value & CHANNEL_OFDM)) {
2093 rpinfo = ee->ee_rate_tpwr_b;
2094 mode = AR5K_EEPROM_MODE_11B;
2095 } else if (channel->hw_value & CHANNEL_2GHZ) {
2096 rpinfo = ee->ee_rate_tpwr_g;
2097 mode = AR5K_EEPROM_MODE_11G;
2098 } else {
2099 rpinfo = ee->ee_rate_tpwr_a;
2100 mode = AR5K_EEPROM_MODE_11A;
2101 }
2102 max = ee->ee_rate_target_pwr_num[mode] - 1;
2103
2104 /* Get the surrounding calibration
2105 * piers - same as above */
2106 if (target < rpinfo[0].freq) {
2107 idx_l = idx_r = 0;
2108 goto done;
2109 }
2110
2111 if (target > rpinfo[max].freq) {
2112 idx_l = idx_r = max;
2113 goto done;
2114 }
2115
2116 for (i = 0; i <= max; i++) {
2117
2118 if (rpinfo[i].freq == target) {
2119 idx_l = idx_r = i;
2120 goto done;
2121 }
2122
2123 if (target < rpinfo[i].freq) {
2124 idx_r = i;
2125 idx_l = idx_r - 1;
2126 goto done;
2127 }
2128 }
2129
2130done:
2131 /* Now interpolate power value, based on the frequency */
2132 rates->freq = target;
2133
2134 rates->target_power_6to24 =
2135 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2136 rpinfo[idx_r].freq,
2137 rpinfo[idx_l].target_power_6to24,
2138 rpinfo[idx_r].target_power_6to24);
2139
2140 rates->target_power_36 =
2141 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2142 rpinfo[idx_r].freq,
2143 rpinfo[idx_l].target_power_36,
2144 rpinfo[idx_r].target_power_36);
2145
2146 rates->target_power_48 =
2147 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2148 rpinfo[idx_r].freq,
2149 rpinfo[idx_l].target_power_48,
2150 rpinfo[idx_r].target_power_48);
2151
2152 rates->target_power_54 =
2153 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2154 rpinfo[idx_r].freq,
2155 rpinfo[idx_l].target_power_54,
2156 rpinfo[idx_r].target_power_54);
2157}
2158
2159/*
2160 * Get the max edge power for this channel if
2161 * we have such data from EEPROM's Conformance Test
2162 * Limits (CTL), and limit max power if needed.
8f655dde
NK		 2163 */
2164static void
2165ath5k_get_max_ctl_power(struct ath5k_hw *ah,
2166 struct ieee80211_channel *channel)
2167{
2168 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2169 struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
2170 u8 *ctl_val = ee->ee_ctl;
2171 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
2172 s16 edge_pwr = 0;
2173 u8 rep_idx;
2174 u8 i, ctl_mode;
2175 u8 ctl_idx = 0xFF;
2176 u32 target = channel->center_freq;
2177
6752ee90
BC		 2178 ctl_mode = ath_regd_get_band_ctl(&ah->ah_regulatory, channel->band);
2179
8f655dde
NK		 2180 switch (channel->hw_value & CHANNEL_MODES) {
2181 case CHANNEL_A:
6752ee90 2182 ctl_mode |= AR5K_CTL_11A;
8f655dde
NK		 2183 break;
2184 case CHANNEL_G:
6752ee90 2185 ctl_mode |= AR5K_CTL_11G;
8f655dde
NK		 2186 break;
2187 case CHANNEL_B:
6752ee90 2188 ctl_mode |= AR5K_CTL_11B;
8f655dde
NK		 2189 break;
2190 case CHANNEL_T:
6752ee90 2191 ctl_mode |= AR5K_CTL_TURBO;
8f655dde
NK		 2192 break;
2193 case CHANNEL_TG:
6752ee90 2194 ctl_mode |= AR5K_CTL_TURBOG;
8f655dde
NK		 2195 break;
2196 case CHANNEL_XR:
2197 /* Fall through */
2198 default:
2199 return;
2200 }
2201
2202 for (i = 0; i < ee->ee_ctls; i++) {
2203 if (ctl_val[i] == ctl_mode) {
2204 ctl_idx = i;
2205 break;
2206 }
2207 }
2208
2209 /* If we have a CTL dataset available grab it and find the
2210 * edge power for our frequency */
2211 if (ctl_idx == 0xFF)
2212 return;
2213
2214 /* Edge powers are sorted by frequency from lower
2215 * to higher. Each CTL corresponds to 8 edge power
2216 * measurements. */
2217 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
2218
2219 /* Don't do boundaries check because we
2220 * might have more that one bands defined
2221 * for this mode */
2222
2223 /* Get the edge power that's closer to our
2224 * frequency */
2225 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
2226 rep_idx += i;
2227 if (target <= rep[rep_idx].freq)
2228 edge_pwr = (s16) rep[rep_idx].edge;
2229 }
2230
2231 if (edge_pwr)
2232 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr);
2233}
2234
2235
2236/*
2237 * Power to PCDAC table functions
2238 */
2239
fa1c114f 2240/*
8f655dde
NK		 2241 * Fill Power to PCDAC table on RF5111
2242 *
2243 * No further processing is needed for RF5111, the only thing we have to
2244 * do is fill the values below and above calibration range since eeprom data
2245 * may not cover the entire PCDAC table.
fa1c114f 2246 */
8f655dde
NK		 2247static void
2248ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
2249 s16 *table_max)
2250{
2251 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2252 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0];
2253 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
2254 s16 min_pwr, max_pwr;
2255
2256 /* Get table boundaries */
2257 min_pwr = table_min[0];
2258 pcdac_0 = pcdac_tmp[0];
2259
2260 max_pwr = table_max[0];
2261 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
2262
2263 /* Extrapolate below minimum using pcdac_0 */
2264 pcdac_i = 0;
2265 for (i = 0; i < min_pwr; i++)
2266 pcdac_out[pcdac_i++] = pcdac_0;
2267
2268 /* Copy values from pcdac_tmp */
2269 pwr_idx = min_pwr;
2270 for (i = 0 ; pwr_idx <= max_pwr &&
2271 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
2272 pcdac_out[pcdac_i++] = pcdac_tmp[i];
2273 pwr_idx++;
2274 }
2275
2276 /* Extrapolate above maximum */
2277 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
2278 pcdac_out[pcdac_i++] = pcdac_n;
2279
2280}
fa1c114f
JS		 2281
2282/*
8f655dde
NK		 2283 * Combine available XPD Curves and fill Linear Power to PCDAC table
2284 * on RF5112
2285 *
2286 * RFX112 can have up to 2 curves (one for low txpower range and one for
2287 * higher txpower range). We need to put them both on pcdac_out and place
2288 * them in the correct location. In case we only have one curve available
2289 * just fit it on pcdac_out (it's supposed to cover the entire range of
2290 * available pwr levels since it's always the higher power curve). Extrapolate
2291 * below and above final table if needed.
fa1c114f 2292 */
8f655dde
NK		 2293static void
2294ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2295 s16 *table_max, u8 pdcurves)
fa1c114f 2296{
8f655dde
NK		 2297 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2298 u8 *pcdac_low_pwr;
2299 u8 *pcdac_high_pwr;
2300 u8 *pcdac_tmp;
2301 u8 pwr;
2302 s16 max_pwr_idx;
2303 s16 min_pwr_idx;
2304 s16 mid_pwr_idx = 0;
2305 /* Edge flag turs on the 7nth bit on the PCDAC
2306 * to delcare the higher power curve (force values
2307 * to be greater than 64). If we only have one curve
2308 * we don't need to set this, if we have 2 curves and
2309 * fill the table backwards this can also be used to
2310 * switch from higher power curve to lower power curve */
2311 u8 edge_flag;
2312 int i;
2313
2314 /* When we have only one curve available
2315 * that's the higher power curve. If we have
2316 * two curves the first is the high power curve
2317 * and the next is the low power curve. */
2318 if (pdcurves > 1) {
2319 pcdac_low_pwr = ah->ah_txpower.tmpL[1];
2320 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2321 mid_pwr_idx = table_max[1] - table_min[1] - 1;
2322 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2323
2324 /* If table size goes beyond 31.5dB, keep the
2325 * upper 31.5dB range when setting tx power.
2326 * Note: 126 = 31.5 dB in quarter dB steps */
2327 if (table_max[0] - table_min[1] > 126)
2328 min_pwr_idx = table_max[0] - 126;
2329 else
2330 min_pwr_idx = table_min[1];
2331
2332 /* Since we fill table backwards
2333 * start from high power curve */
2334 pcdac_tmp = pcdac_high_pwr;
2335
2336 edge_flag = 0x40;
2337#if 0
2338 /* If both min and max power limits are in lower
2339 * power curve's range, only use the low power curve.
2340 * TODO: min/max levels are related to target
2341 * power values requested from driver/user
2342 * XXX: Is this really needed ? */
2343 if (min_pwr < table_max[1] &&
2344 max_pwr < table_max[1]) {
2345 edge_flag = 0;
2346 pcdac_tmp = pcdac_low_pwr;
2347 max_pwr_idx = (table_max[1] - table_min[1])/2;
2348 }
fa1c114f 2349#endif
8f655dde
NK		 2350 } else {
2351 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
2352 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2353 min_pwr_idx = table_min[0];
2354 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2355 pcdac_tmp = pcdac_high_pwr;
2356 edge_flag = 0;
2357 }
2358
2359 /* This is used when setting tx power*/
2360 ah->ah_txpower.txp_min_idx = min_pwr_idx/2;
2361
2362 /* Fill Power to PCDAC table backwards */
2363 pwr = max_pwr_idx;
2364 for (i = 63; i >= 0; i--) {
2365 /* Entering lower power range, reset
2366 * edge flag and set pcdac_tmp to lower
2367 * power curve.*/
2368 if (edge_flag == 0x40 &&
2369 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
2370 edge_flag = 0x00;
2371 pcdac_tmp = pcdac_low_pwr;
2372 pwr = mid_pwr_idx/2;
2373 }
2374
2375 /* Don't go below 1, extrapolate below if we have
2376 * already swithced to the lower power curve -or
2377 * we only have one curve and edge_flag is zero
2378 * anyway */
2379 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
2380 while (i >= 0) {
2381 pcdac_out[i] = pcdac_out[i + 1];
2382 i--;
2383 }
2384 break;
2385 }
2386
2387 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
2388
2389 /* Extrapolate above if pcdac is greater than
2390 * 126 -this can happen because we OR pcdac_out
2391 * value with edge_flag on high power curve */
2392 if (pcdac_out[i] > 126)
2393 pcdac_out[i] = 126;
2394
2395 /* Decrease by a 0.5dB step */
2396 pwr--;
2397 }
fa1c114f
JS		 2398}
2399
8f655dde
NK		 2400/* Write PCDAC values on hw */
2401static void
2402ath5k_setup_pcdac_table(struct ath5k_hw *ah)
2403{
2404 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2405 int i;
2406
2407 /*
2408 * Write TX power values
2409 */
2410 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2411 ath5k_hw_reg_write(ah,
2412 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) |
2413 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16),
2414 AR5K_PHY_PCDAC_TXPOWER(i));
2415 }
2416}
2417
2418
fa1c114f 2419/*
8f655dde 2420 * Power to PDADC table functions
fa1c114f 2421 */
8f655dde
NK		 2422
2423/*
2424 * Set the gain boundaries and create final Power to PDADC table
2425 *
2426 * We can have up to 4 pd curves, we need to do a simmilar process
2427 * as we do for RF5112. This time we don't have an edge_flag but we
2428 * set the gain boundaries on a separate register.
2429 */
2430static void
2431ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
2432 s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
fa1c114f 2433{
8f655dde
NK		 2434 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
2435 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2436 u8 *pdadc_tmp;
2437 s16 pdadc_0;
2438 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
2439 u8 pd_gain_overlap;
2440
2441 /* Note: Register value is initialized on initvals
2442 * there is no feedback from hw.
2443 * XXX: What about pd_gain_overlap from EEPROM ? */
2444 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
2445 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
2446
2447 /* Create final PDADC table */
2448 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
2449 pdadc_tmp = ah->ah_txpower.tmpL[pdg];
2450
2451 if (pdg == pdcurves - 1)
2452 /* 2 dB boundary stretch for last
2453 * (higher power) curve */
2454 gain_boundaries[pdg] = pwr_max[pdg] + 4;
2455 else
2456 /* Set gain boundary in the middle
2457 * between this curve and the next one */
2458 gain_boundaries[pdg] =
2459 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
2460
2461 /* Sanity check in case our 2 db stretch got out of
2462 * range. */
2463 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
2464 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
2465
2466 /* For the first curve (lower power)
2467 * start from 0 dB */
2468 if (pdg == 0)
2469 pdadc_0 = 0;
2470 else
2471 /* For the other curves use the gain overlap */
2472 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
2473 pd_gain_overlap;
fa1c114f 2474
8f655dde
NK		 2475 /* Force each power step to be at least 0.5 dB */
2476 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
2477 pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
2478 else
2479 pwr_step = 1;
2480
2481 /* If pdadc_0 is negative, we need to extrapolate
2482 * below this pdgain by a number of pwr_steps */
2483 while ((pdadc_0 < 0) && (pdadc_i < 128)) {
2484 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
2485 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
2486 pdadc_0++;
2487 }
2488
2489 /* Set last pwr level, using gain boundaries */
2490 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
2491 /* Limit it to be inside pwr range */
2492 table_size = pwr_max[pdg] - pwr_min[pdg];
2493 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
2494
2495 /* Fill pdadc_out table */
2496 while (pdadc_0 < max_idx)
2497 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
2498
2499 /* Need to extrapolate above this pdgain? */
2500 if (pdadc_n <= max_idx)
2501 continue;
2502
2503 /* Force each power step to be at least 0.5 dB */
2504 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
2505 pwr_step = pdadc_tmp[table_size - 1] -
2506 pdadc_tmp[table_size - 2];
2507 else
2508 pwr_step = 1;
2509
2510 /* Extrapolate above */
2511 while ((pdadc_0 < (s16) pdadc_n) &&
2512 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
2513 s16 tmp = pdadc_tmp[table_size - 1] +
2514 (pdadc_0 - max_idx) * pwr_step;
2515 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
2516 pdadc_0++;
2517 }
fa1c114f
JS		 2518 }
2519
8f655dde
NK		 2520 while (pdg < AR5K_EEPROM_N_PD_GAINS) {
2521 gain_boundaries[pdg] = gain_boundaries[pdg - 1];
2522 pdg++;
2523 }
2524
2525 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
2526 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
2527 pdadc_i++;
2528 }
2529
2530 /* Set gain boundaries */
2531 ath5k_hw_reg_write(ah,
2532 AR5K_REG_SM(pd_gain_overlap,
2533 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
2534 AR5K_REG_SM(gain_boundaries[0],
2535 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
2536 AR5K_REG_SM(gain_boundaries[1],
2537 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
2538 AR5K_REG_SM(gain_boundaries[2],
2539 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
2540 AR5K_REG_SM(gain_boundaries[3],
2541 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
2542 AR5K_PHY_TPC_RG5);
2543
2544 /* Used for setting rate power table */
2545 ah->ah_txpower.txp_min_idx = pwr_min[0];
2546
2547}
2548
2549/* Write PDADC values on hw */
2550static void
2551ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah,
2552 u8 pdcurves, u8 *pdg_to_idx)
2553{
2554 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2555 u32 reg;
2556 u8 i;
2557
2558 /* Select the right pdgain curves */
2559
2560 /* Clear current settings */
2561 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
2562 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
2563 AR5K_PHY_TPC_RG1_PDGAIN_2 |
2564 AR5K_PHY_TPC_RG1_PDGAIN_3 |
2565 AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2566
903b474e 2567 /*
8f655dde 2568 * Use pd_gains curve from eeprom
136bfc79 2569 *
8f655dde
NK		 2570 * This overrides the default setting from initvals
2571 * in case some vendors (e.g. Zcomax) don't use the default
2572 * curves. If we don't honor their settings we 'll get a
2573 * 5dB (1 * gain overlap ?) drop.
903b474e 2574 */
8f655dde 2575 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
903b474e 2576
8f655dde
NK		 2577 switch (pdcurves) {
2578 case 3:
2579 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
2580 /* Fall through */
2581 case 2:
2582 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
2583 /* Fall through */
2584 case 1:
2585 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
2586 break;
2587 }
2588 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
fa1c114f
JS		 2589
2590 /*
2591 * Write TX power values
2592 */
2593 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2594 ath5k_hw_reg_write(ah,
8f655dde
NK		 2595 ((pdadc_out[4*i + 0] & 0xff) << 0) |
2596 ((pdadc_out[4*i + 1] & 0xff) << 8) |
2597 ((pdadc_out[4*i + 2] & 0xff) << 16) |
2598 ((pdadc_out[4*i + 3] & 0xff) << 24),
2599 AR5K_PHY_PDADC_TXPOWER(i));
2600 }
2601}
2602
2603
2604/*
2605 * Common code for PCDAC/PDADC tables
2606 */
2607
2608/*
2609 * This is the main function that uses all of the above
2610 * to set PCDAC/PDADC table on hw for the current channel.
2611 * This table is used for tx power calibration on the basband,
2612 * without it we get weird tx power levels and in some cases
2613 * distorted spectral mask
2614 */
2615static int
2616ath5k_setup_channel_powertable(struct ath5k_hw *ah,
2617 struct ieee80211_channel *channel,
2618 u8 ee_mode, u8 type)
2619{
2620 struct ath5k_pdgain_info *pdg_L, *pdg_R;
2621 struct ath5k_chan_pcal_info *pcinfo_L;
2622 struct ath5k_chan_pcal_info *pcinfo_R;
2623 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2624 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
2625 s16 table_min[AR5K_EEPROM_N_PD_GAINS];
2626 s16 table_max[AR5K_EEPROM_N_PD_GAINS];
2627 u8 *tmpL;
2628 u8 *tmpR;
2629 u32 target = channel->center_freq;
2630 int pdg, i;
2631
2632 /* Get surounding freq piers for this channel */
2633 ath5k_get_chan_pcal_surrounding_piers(ah, channel,
2634 &pcinfo_L,
2635 &pcinfo_R);
2636
2637 /* Loop over pd gain curves on
2638 * surounding freq piers by index */
2639 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
2640
2641 /* Fill curves in reverse order
2642 * from lower power (max gain)
2643 * to higher power. Use curve -> idx
2644 * backmaping we did on eeprom init */
2645 u8 idx = pdg_curve_to_idx[pdg];
2646
2647 /* Grab the needed curves by index */
2648 pdg_L = &pcinfo_L->pd_curves[idx];
2649 pdg_R = &pcinfo_R->pd_curves[idx];
2650
2651 /* Initialize the temp tables */
2652 tmpL = ah->ah_txpower.tmpL[pdg];
2653 tmpR = ah->ah_txpower.tmpR[pdg];
2654
2655 /* Set curve's x boundaries and create
2656 * curves so that they cover the same
2657 * range (if we don't do that one table
2658 * will have values on some range and the
2659 * other one won't have any so interpolation
2660 * will fail) */
2661 table_min[pdg] = min(pdg_L->pd_pwr[0],
2662 pdg_R->pd_pwr[0]) / 2;
2663
2664 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2665 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
2666
2667 /* Now create the curves on surrounding channels
2668 * and interpolate if needed to get the final
2669 * curve for this gain on this channel */
2670 switch (type) {
2671 case AR5K_PWRTABLE_LINEAR_PCDAC:
2672 /* Override min/max so that we don't loose
2673 * accuracy (don't divide by 2) */
2674 table_min[pdg] = min(pdg_L->pd_pwr[0],
2675 pdg_R->pd_pwr[0]);
2676
2677 table_max[pdg] =
2678 max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2679 pdg_R->pd_pwr[pdg_R->pd_points - 1]);
2680
2681 /* Override minimum so that we don't get
2682 * out of bounds while extrapolating
2683 * below. Don't do this when we have 2
2684 * curves and we are on the high power curve
2685 * because table_min is ok in this case */
2686 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
2687
2688 table_min[pdg] =
2689 ath5k_get_linear_pcdac_min(pdg_L->pd_step,
2690 pdg_R->pd_step,
2691 pdg_L->pd_pwr,
2692 pdg_R->pd_pwr);
2693
2694 /* Don't go too low because we will
2695 * miss the upper part of the curve.
2696 * Note: 126 = 31.5dB (max power supported)
2697 * in 0.25dB units */
2698 if (table_max[pdg] - table_min[pdg] > 126)
2699 table_min[pdg] = table_max[pdg] - 126;
2700 }
2701
2702 /* Fall through */
2703 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2704 case AR5K_PWRTABLE_PWR_TO_PDADC:
2705
2706 ath5k_create_power_curve(table_min[pdg],
2707 table_max[pdg],
2708 pdg_L->pd_pwr,
2709 pdg_L->pd_step,
2710 pdg_L->pd_points, tmpL, type);
2711
2712 /* We are in a calibration
2713 * pier, no need to interpolate
2714 * between freq piers */
2715 if (pcinfo_L == pcinfo_R)
2716 continue;
2717
2718 ath5k_create_power_curve(table_min[pdg],
2719 table_max[pdg],
2720 pdg_R->pd_pwr,
2721 pdg_R->pd_step,
2722 pdg_R->pd_points, tmpR, type);
2723 break;
2724 default:
2725 return -EINVAL;
2726 }
2727
2728 /* Interpolate between curves
2729 * of surounding freq piers to
2730 * get the final curve for this
2731 * pd gain. Re-use tmpL for interpolation
2732 * output */
2733 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
2734 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2735 tmpL[i] = (u8) ath5k_get_interpolated_value(target,
2736 (s16) pcinfo_L->freq,
2737 (s16) pcinfo_R->freq,
2738 (s16) tmpL[i],
2739 (s16) tmpR[i]);
2740 }
fa1c114f
JS		 2741 }
2742
8f655dde
NK		 2743 /* Now we have a set of curves for this
2744 * channel on tmpL (x range is table_max - table_min
2745 * and y values are tmpL[pdg][]) sorted in the same
2746 * order as EEPROM (because we've used the backmaping).
2747 * So for RF5112 it's from higher power to lower power
2748 * and for RF2413 it's from lower power to higher power.
2749 * For RF5111 we only have one curve. */
2750
2751 /* Fill min and max power levels for this
2752 * channel by interpolating the values on
2753 * surounding channels to complete the dataset */
2754 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
2755 (s16) pcinfo_L->freq,
2756 (s16) pcinfo_R->freq,
2757 pcinfo_L->min_pwr, pcinfo_R->min_pwr);
2758
2759 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
2760 (s16) pcinfo_L->freq,
2761 (s16) pcinfo_R->freq,
2762 pcinfo_L->max_pwr, pcinfo_R->max_pwr);
2763
2764 /* We are ready to go, fill PCDAC/PDADC
2765 * table and write settings on hardware */
2766 switch (type) {
2767 case AR5K_PWRTABLE_LINEAR_PCDAC:
2768 /* For RF5112 we can have one or two curves
2769 * and each curve covers a certain power lvl
2770 * range so we need to do some more processing */
2771 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
2772 ee->ee_pd_gains[ee_mode]);
2773
2774 /* Set txp.offset so that we can
2775 * match max power value with max
2776 * table index */
2777 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
2778
2779 /* Write settings on hw */
2780 ath5k_setup_pcdac_table(ah);
2781 break;
2782 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2783 /* We are done for RF5111 since it has only
2784 * one curve, just fit the curve on the table */
2785 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
2786
2787 /* No rate powertable adjustment for RF5111 */
2788 ah->ah_txpower.txp_min_idx = 0;
2789 ah->ah_txpower.txp_offset = 0;
2790
2791 /* Write settings on hw */
2792 ath5k_setup_pcdac_table(ah);
2793 break;
2794 case AR5K_PWRTABLE_PWR_TO_PDADC:
2795 /* Set PDADC boundaries and fill
2796 * final PDADC table */
2797 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
2798 ee->ee_pd_gains[ee_mode]);
2799
2800 /* Write settings on hw */
2801 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx);
2802
2803 /* Set txp.offset, note that table_min
2804 * can be negative */
2805 ah->ah_txpower.txp_offset = table_min[0];
2806 break;
2807 default:
2808 return -EINVAL;
2809 }
2810
2811 return 0;
2812}
2813
2814
2815/*
2816 * Per-rate tx power setting
2817 *
2818 * This is the code that sets the desired tx power (below
2819 * maximum) on hw for each rate (we also have TPC that sets
2820 * power per packet). We do that by providing an index on the
2821 * PCDAC/PDADC table we set up.
2822 */
2823
2824/*
2825 * Set rate power table
2826 *
2827 * For now we only limit txpower based on maximum tx power
2828 * supported by hw (what's inside rate_info). We need to limit
2829 * this even more, based on regulatory domain etc.
2830 *
2831 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
2832 * and is indexed as follows:
2833 * rates[0] - rates[7] -> OFDM rates
2834 * rates[8] - rates[14] -> CCK rates
2835 * rates[15] -> XR rates (they all have the same power)
2836 */
2837static void
2838ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
2839 struct ath5k_rate_pcal_info *rate_info,
2840 u8 ee_mode)
2841{
2842 unsigned int i;
2843 u16 *rates;
2844
2845 /* max_pwr is power level we got from driver/user in 0.5dB
2846 * units, switch to 0.25dB units so we can compare */
2847 max_pwr *= 2;
2848 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
2849
2850 /* apply rate limits */
2851 rates = ah->ah_txpower.txp_rates_power_table;
2852
2853 /* OFDM rates 6 to 24Mb/s */
2854 for (i = 0; i < 5; i++)
2855 rates[i] = min(max_pwr, rate_info->target_power_6to24);
2856
2857 /* Rest OFDM rates */
2858 rates[5] = min(rates[0], rate_info->target_power_36);
2859 rates[6] = min(rates[0], rate_info->target_power_48);
2860 rates[7] = min(rates[0], rate_info->target_power_54);
2861
2862 /* CCK rates */
2863 /* 1L */
2864 rates[8] = min(rates[0], rate_info->target_power_6to24);
2865 /* 2L */
2866 rates[9] = min(rates[0], rate_info->target_power_36);
2867 /* 2S */
2868 rates[10] = min(rates[0], rate_info->target_power_36);
2869 /* 5L */
2870 rates[11] = min(rates[0], rate_info->target_power_48);
2871 /* 5S */
2872 rates[12] = min(rates[0], rate_info->target_power_48);
2873 /* 11L */
2874 rates[13] = min(rates[0], rate_info->target_power_54);
2875 /* 11S */
2876 rates[14] = min(rates[0], rate_info->target_power_54);
2877
2878 /* XR rates */
2879 rates[15] = min(rates[0], rate_info->target_power_6to24);
2880
2881 /* CCK rates have different peak to average ratio
2882 * so we have to tweak their power so that gainf
2883 * correction works ok. For this we use OFDM to
2884 * CCK delta from eeprom */
2885 if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
2886 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
2887 for (i = 8; i <= 15; i++)
2888 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
2889
a0823810
NK		 2890 /* Now that we have all rates setup use table offset to
2891 * match the power range set by user with the power indices
2892 * on PCDAC/PDADC table */
2893 for (i = 0; i < 16; i++) {
2894 rates[i] += ah->ah_txpower.txp_offset;
2895 /* Don't get out of bounds */
2896 if (rates[i] > 63)
2897 rates[i] = 63;
2898 }
2899
2900 /* Min/max in 0.25dB units */
2901 ah->ah_txpower.txp_min_pwr = 2 * rates[7];
2902 ah->ah_txpower.txp_max_pwr = 2 * rates[0];
8f655dde
NK		 2903 ah->ah_txpower.txp_ofdm = rates[7];
2904}
2905
2906
2907/*
2908 * Set transmition power
2909 */
2910int
2911ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
2912 u8 ee_mode, u8 txpower)
2913{
2914 struct ath5k_rate_pcal_info rate_info;
2915 u8 type;
2916 int ret;
2917
2918 ATH5K_TRACE(ah->ah_sc);
2919 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
2920 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
2921 return -EINVAL;
2922 }
2923 if (txpower == 0)
2924 txpower = AR5K_TUNE_DEFAULT_TXPOWER;
2925
2926 /* Reset TX power values */
2927 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
2928 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
2929 ah->ah_txpower.txp_min_pwr = 0;
2930 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;
2931
2932 /* Initialize TX power table */
2933 switch (ah->ah_radio) {
2934 case AR5K_RF5111:
2935 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
2936 break;
2937 case AR5K_RF5112:
2938 type = AR5K_PWRTABLE_LINEAR_PCDAC;
2939 break;
2940 case AR5K_RF2413:
2941 case AR5K_RF5413:
2942 case AR5K_RF2316:
2943 case AR5K_RF2317:
2944 case AR5K_RF2425:
2945 type = AR5K_PWRTABLE_PWR_TO_PDADC;
2946 break;
2947 default:
2948 return -EINVAL;
2949 }
2950
2951 /* FIXME: Only on channel/mode change */
2952 ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type);
2953 if (ret)
2954 return ret;
2955
2956 /* Limit max power if we have a CTL available */
2957 ath5k_get_max_ctl_power(ah, channel);
2958
2959 /* FIXME: Tx power limit for this regdomain
2960 * XXX: Mac80211/CRDA will do that anyway ? */
2961
2962 /* FIXME: Antenna reduction stuff */
2963
2964 /* FIXME: Limit power on turbo modes */
2965
2966 /* FIXME: TPC scale reduction */
2967
2968 /* Get surounding channels for per-rate power table
2969 * calibration */
2970 ath5k_get_rate_pcal_data(ah, channel, &rate_info);
2971
2972 /* Setup rate power table */
2973 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
2974
2975 /* Write rate power table on hw */
fa1c114f
JS		 2976 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
2977 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
2978 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
2979
2980 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
2981 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
2982 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
2983
2984 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
2985 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
2986 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
2987
2988 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
2989 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
2990 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
2991
8f655dde
NK		 2992 /* FIXME: TPC support */
2993 if (ah->ah_txpower.txp_tpc) {
fa1c114f
JS		 2994 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
2995 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
8f655dde
NK		 2996
2997 ath5k_hw_reg_write(ah,
2998 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
2999 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
3000 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
3001 AR5K_TPC);
3002 } else {
fa1c114f
JS		 3003 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
3004 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
8f655dde 3005 }
fa1c114f
JS		 3006
3007 return 0;
3008}
3009
a0823810 3010int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
fa1c114f
JS		 3011{
3012 /*Just a try M.F.*/
46026e8f 3013 struct ieee80211_channel *channel = ah->ah_current_channel;
a0823810 3014 u8 ee_mode;
fa1c114f
JS		 3015
3016 ATH5K_TRACE(ah->ah_sc);
a0823810
NK		 3017
3018 switch (channel->hw_value & CHANNEL_MODES) {
3019 case CHANNEL_A:
3020 case CHANNEL_T:
3021 case CHANNEL_XR:
3022 ee_mode = AR5K_EEPROM_MODE_11A;
3023 break;
3024 case CHANNEL_G:
3025 case CHANNEL_TG:
3026 ee_mode = AR5K_EEPROM_MODE_11G;
3027 break;
3028 case CHANNEL_B:
3029 ee_mode = AR5K_EEPROM_MODE_11B;
3030 break;
3031 default:
3032 ATH5K_ERR(ah->ah_sc,
3033 "invalid channel: %d\n", channel->center_freq);
3034 return -EINVAL;
3035 }
3036
fa1c114f 3037 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
8f655dde 3038 "changing txpower to %d\n", txpower);
fa1c114f 3039
a0823810 3040 return ath5k_hw_txpower(ah, channel, ee_mode, txpower);
fa1c114f 3041}
c6e387a2
NK		 3042
3043#undef _ATH5K_PHY
Linux kernel - Deliverables
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