Commit | Line | Data |
---|---|---|
fa1c114f | 1 | /* |
c6e387a2 NK |
2 | * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> |
3 | * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> | |
4 | * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com> | |
fa1c114f JS |
5 | * |
6 | * Permission to use, copy, modify, and distribute this software for any | |
7 | * purpose with or without fee is hereby granted, provided that the above | |
8 | * copyright notice and this permission notice appear in all copies. | |
9 | * | |
10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
17 | * | |
18 | */ | |
19 | ||
20 | /* | |
21 | * Register values for Atheros 5210/5211/5212 cards from OpenBSD's ar5k | |
22 | * maintained by Reyk Floeter | |
23 | * | |
24 | * I tried to document those registers by looking at ar5k code, some | |
25 | * 802.11 (802.11e mostly) papers and by reading various public available | |
26 | * Atheros presentations and papers like these: | |
27 | * | |
28 | * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf | |
29 | * http://www.it.iitb.ac.in/~janak/wifire/01222734.pdf | |
30 | * | |
31 | * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf | |
1bef016a NK |
32 | * |
33 | * This file also contains register values found on a memory dump of | |
34 | * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal | |
35 | * released by Atheros and on various debug messages found on the net. | |
fa1c114f JS |
36 | */ |
37 | ||
38 | ||
39 | ||
40 | /*====MAC DMA REGISTERS====*/ | |
41 | ||
42 | /* | |
43 | * AR5210-Specific TXDP registers | |
44 | * 5210 has only 2 transmit queues so no DCU/QCU, just | |
45 | * 2 transmit descriptor pointers... | |
46 | */ | |
47 | #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */ | |
48 | #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */ | |
49 | ||
50 | /* | |
51 | * Mac Control Register | |
52 | */ | |
53 | #define AR5K_CR 0x0008 /* Register Address */ | |
54 | #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */ | |
55 | #define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */ | |
56 | #define AR5K_CR_RXE 0x00000004 /* RX Enable */ | |
57 | #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */ | |
58 | #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */ | |
59 | #define AR5K_CR_RXD 0x00000020 /* RX Disable */ | |
0bacdf30 | 60 | #define AR5K_CR_SWI 0x00000040 /* Software Interrupt */ |
fa1c114f JS |
61 | |
62 | /* | |
63 | * RX Descriptor Pointer register | |
64 | */ | |
65 | #define AR5K_RXDP 0x000c | |
66 | ||
67 | /* | |
68 | * Configuration and status register | |
69 | */ | |
70 | #define AR5K_CFG 0x0014 /* Register Address */ | |
71 | #define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */ | |
0bacdf30 | 72 | #define AR5K_CFG_SWTB 0x00000002 /* Byte-swap TX buffer */ |
fa1c114f | 73 | #define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */ |
0bacdf30 NK |
74 | #define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer */ |
75 | #define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register access */ | |
4fb7404e | 76 | #define AR5K_CFG_IBSS 0x00000020 /* 0-BSS, 1-IBSS [5211+] */ |
fa1c114f JS |
77 | #define AR5K_CFG_PHY_OK 0x00000100 /* [5211+] */ |
78 | #define AR5K_CFG_EEBS 0x00000200 /* EEPROM is busy */ | |
0bacdf30 | 79 | #define AR5K_CFG_CLKGD 0x00000400 /* Clock gated (Disable dynamic clock) */ |
fa1c114f JS |
80 | #define AR5K_CFG_TXCNT 0x00007800 /* Tx frame count (?) [5210] */ |
81 | #define AR5K_CFG_TXCNT_S 11 | |
82 | #define AR5K_CFG_TXFSTAT 0x00008000 /* Tx frame status (?) [5210] */ | |
83 | #define AR5K_CFG_TXFSTRT 0x00010000 /* [5210] */ | |
0bacdf30 | 84 | #define AR5K_CFG_PCI_THRES 0x00060000 /* PCI Master req q threshold [5211+] */ |
fa1c114f JS |
85 | #define AR5K_CFG_PCI_THRES_S 17 |
86 | ||
87 | /* | |
88 | * Interrupt enable register | |
89 | */ | |
90 | #define AR5K_IER 0x0024 /* Register Address */ | |
91 | #define AR5K_IER_DISABLE 0x00000000 /* Disable card interrupts */ | |
92 | #define AR5K_IER_ENABLE 0x00000001 /* Enable card interrupts */ | |
93 | ||
94 | ||
95 | /* | |
96 | * 0x0028 is Beacon Control Register on 5210 | |
97 | * and first RTS duration register on 5211 | |
98 | */ | |
99 | ||
100 | /* | |
101 | * Beacon control register [5210] | |
102 | */ | |
103 | #define AR5K_BCR 0x0028 /* Register Address */ | |
104 | #define AR5K_BCR_AP 0x00000000 /* AP mode */ | |
105 | #define AR5K_BCR_ADHOC 0x00000001 /* Ad-Hoc mode */ | |
106 | #define AR5K_BCR_BDMAE 0x00000002 /* DMA enable */ | |
107 | #define AR5K_BCR_TQ1FV 0x00000004 /* Use Queue1 for CAB traffic */ | |
108 | #define AR5K_BCR_TQ1V 0x00000008 /* Use Queue1 for Beacon traffic */ | |
109 | #define AR5K_BCR_BCGET 0x00000010 | |
110 | ||
111 | /* | |
112 | * First RTS duration register [5211] | |
113 | */ | |
114 | #define AR5K_RTSD0 0x0028 /* Register Address */ | |
115 | #define AR5K_RTSD0_6 0x000000ff /* 6Mb RTS duration mask (?) */ | |
116 | #define AR5K_RTSD0_6_S 0 /* 6Mb RTS duration shift (?) */ | |
117 | #define AR5K_RTSD0_9 0x0000ff00 /* 9Mb*/ | |
118 | #define AR5K_RTSD0_9_S 8 | |
119 | #define AR5K_RTSD0_12 0x00ff0000 /* 12Mb*/ | |
120 | #define AR5K_RTSD0_12_S 16 | |
121 | #define AR5K_RTSD0_18 0xff000000 /* 16Mb*/ | |
122 | #define AR5K_RTSD0_18_S 24 | |
123 | ||
124 | ||
125 | /* | |
126 | * 0x002c is Beacon Status Register on 5210 | |
127 | * and second RTS duration register on 5211 | |
128 | */ | |
129 | ||
130 | /* | |
131 | * Beacon status register [5210] | |
132 | * | |
133 | * As i can see in ar5k_ar5210_tx_start Reyk uses some of the values of BCR | |
134 | * for this register, so i guess TQ1V,TQ1FV and BDMAE have the same meaning | |
135 | * here and SNP/SNAP means "snapshot" (so this register gets synced with BCR). | |
136 | * So SNAPPEDBCRVALID sould also stand for "snapped BCR -values- valid", so i | |
137 | * renamed it to SNAPSHOTSVALID to make more sense. I realy have no idea what | |
138 | * else can it be. I also renamed SNPBCMD to SNPADHOC to match BCR. | |
139 | */ | |
140 | #define AR5K_BSR 0x002c /* Register Address */ | |
141 | #define AR5K_BSR_BDLYSW 0x00000001 /* SW Beacon delay (?) */ | |
142 | #define AR5K_BSR_BDLYDMA 0x00000002 /* DMA Beacon delay (?) */ | |
143 | #define AR5K_BSR_TXQ1F 0x00000004 /* Beacon queue (1) finished */ | |
144 | #define AR5K_BSR_ATIMDLY 0x00000008 /* ATIM delay (?) */ | |
145 | #define AR5K_BSR_SNPADHOC 0x00000100 /* Ad-hoc mode set (?) */ | |
146 | #define AR5K_BSR_SNPBDMAE 0x00000200 /* Beacon DMA enabled (?) */ | |
147 | #define AR5K_BSR_SNPTQ1FV 0x00000400 /* Queue1 is used for CAB traffic (?) */ | |
148 | #define AR5K_BSR_SNPTQ1V 0x00000800 /* Queue1 is used for Beacon traffic (?) */ | |
149 | #define AR5K_BSR_SNAPSHOTSVALID 0x00001000 /* BCR snapshots are valid (?) */ | |
150 | #define AR5K_BSR_SWBA_CNT 0x00ff0000 | |
151 | ||
152 | /* | |
153 | * Second RTS duration register [5211] | |
154 | */ | |
155 | #define AR5K_RTSD1 0x002c /* Register Address */ | |
156 | #define AR5K_RTSD1_24 0x000000ff /* 24Mb */ | |
157 | #define AR5K_RTSD1_24_S 0 | |
158 | #define AR5K_RTSD1_36 0x0000ff00 /* 36Mb */ | |
159 | #define AR5K_RTSD1_36_S 8 | |
160 | #define AR5K_RTSD1_48 0x00ff0000 /* 48Mb */ | |
161 | #define AR5K_RTSD1_48_S 16 | |
162 | #define AR5K_RTSD1_54 0xff000000 /* 54Mb */ | |
163 | #define AR5K_RTSD1_54_S 24 | |
164 | ||
165 | ||
166 | /* | |
167 | * Transmit configuration register | |
168 | */ | |
0bacdf30 NK |
169 | #define AR5K_TXCFG 0x0030 /* Register Address */ |
170 | #define AR5K_TXCFG_SDMAMR 0x00000007 /* DMA size (read) */ | |
171 | #define AR5K_TXCFG_SDMAMR_S 0 | |
172 | #define AR5K_TXCFG_B_MODE 0x00000008 /* Set b mode for 5111 (enable 2111) */ | |
173 | #define AR5K_TXCFG_TXFSTP 0x00000008 /* TX DMA full Stop [5210] */ | |
174 | #define AR5K_TXCFG_TXFULL 0x000003f0 /* TX Triger level mask */ | |
175 | #define AR5K_TXCFG_TXFULL_S 4 | |
176 | #define AR5K_TXCFG_TXFULL_0B 0x00000000 | |
177 | #define AR5K_TXCFG_TXFULL_64B 0x00000010 | |
178 | #define AR5K_TXCFG_TXFULL_128B 0x00000020 | |
179 | #define AR5K_TXCFG_TXFULL_192B 0x00000030 | |
180 | #define AR5K_TXCFG_TXFULL_256B 0x00000040 | |
181 | #define AR5K_TXCFG_TXCONT_EN 0x00000080 | |
182 | #define AR5K_TXCFG_DMASIZE 0x00000100 /* Flag for passing DMA size [5210] */ | |
183 | #define AR5K_TXCFG_JUMBO_DESC_EN 0x00000400 /* Enable jumbo tx descriptors [5211+] */ | |
184 | #define AR5K_TXCFG_ADHOC_BCN_ATIM 0x00000800 /* Adhoc Beacon ATIM Policy */ | |
185 | #define AR5K_TXCFG_ATIM_WINDOW_DEF_DIS 0x00001000 /* Disable ATIM window defer [5211+] */ | |
186 | #define AR5K_TXCFG_RTSRND 0x00001000 /* [5211+] */ | |
187 | #define AR5K_TXCFG_FRMPAD_DIS 0x00002000 /* [5211+] */ | |
188 | #define AR5K_TXCFG_RDY_CBR_DIS 0x00004000 /* Ready time CBR disable [5211+] */ | |
189 | #define AR5K_TXCFG_JUMBO_FRM_MODE 0x00008000 /* Jumbo frame mode [5211+] */ | |
e8f055f0 | 190 | #define AR5K_TXCFG_DCU_DBL_BUF_DIS 0x00008000 /* Disable double buffering on DCU */ |
0bacdf30 | 191 | #define AR5K_TXCFG_DCU_CACHING_DIS 0x00010000 /* Disable DCU caching */ |
fa1c114f JS |
192 | |
193 | /* | |
194 | * Receive configuration register | |
195 | */ | |
196 | #define AR5K_RXCFG 0x0034 /* Register Address */ | |
0bacdf30 | 197 | #define AR5K_RXCFG_SDMAMW 0x00000007 /* DMA size (write) */ |
fa1c114f | 198 | #define AR5K_RXCFG_SDMAMW_S 0 |
0bacdf30 NK |
199 | #define AR5K_RXCFG_ZLFDMA 0x00000008 /* Enable Zero-length frame DMA */ |
200 | #define AR5K_RXCFG_DEF_ANTENNA 0x00000010 /* Default antenna (?) */ | |
201 | #define AR5K_RXCFG_JUMBO_RXE 0x00000020 /* Enable jumbo rx descriptors [5211+] */ | |
202 | #define AR5K_RXCFG_JUMBO_WRAP 0x00000040 /* Wrap jumbo frames [5211+] */ | |
203 | #define AR5K_RXCFG_SLE_ENTRY 0x00000080 /* Sleep entry policy */ | |
fa1c114f JS |
204 | |
205 | /* | |
206 | * Receive jumbo descriptor last address register | |
207 | * Only found in 5211 (?) | |
208 | */ | |
209 | #define AR5K_RXJLA 0x0038 | |
210 | ||
211 | /* | |
212 | * MIB control register | |
213 | */ | |
214 | #define AR5K_MIBC 0x0040 /* Register Address */ | |
0bacdf30 NK |
215 | #define AR5K_MIBC_COW 0x00000001 /* Warn test indicator */ |
216 | #define AR5K_MIBC_FMC 0x00000002 /* Freeze MIB Counters */ | |
217 | #define AR5K_MIBC_CMC 0x00000004 /* Clean MIB Counters */ | |
218 | #define AR5K_MIBC_MCS 0x00000008 /* MIB counter strobe */ | |
fa1c114f JS |
219 | |
220 | /* | |
221 | * Timeout prescale register | |
222 | */ | |
223 | #define AR5K_TOPS 0x0044 | |
0bacdf30 | 224 | #define AR5K_TOPS_M 0x0000ffff |
fa1c114f JS |
225 | |
226 | /* | |
227 | * Receive timeout register (no frame received) | |
228 | */ | |
229 | #define AR5K_RXNOFRM 0x0048 | |
0bacdf30 | 230 | #define AR5K_RXNOFRM_M 0x000003ff |
fa1c114f JS |
231 | |
232 | /* | |
233 | * Transmit timeout register (no frame sent) | |
234 | */ | |
235 | #define AR5K_TXNOFRM 0x004c | |
0bacdf30 NK |
236 | #define AR5K_TXNOFRM_M 0x000003ff |
237 | #define AR5K_TXNOFRM_QCU 0x000ffc00 | |
4c674c60 | 238 | #define AR5K_TXNOFRM_QCU_S 10 |
fa1c114f JS |
239 | |
240 | /* | |
241 | * Receive frame gap timeout register | |
242 | */ | |
243 | #define AR5K_RPGTO 0x0050 | |
0bacdf30 | 244 | #define AR5K_RPGTO_M 0x000003ff |
fa1c114f JS |
245 | |
246 | /* | |
247 | * Receive frame count limit register | |
248 | */ | |
249 | #define AR5K_RFCNT 0x0054 | |
250 | #define AR5K_RFCNT_M 0x0000001f /* [5211+] (?) */ | |
251 | #define AR5K_RFCNT_RFCL 0x0000000f /* [5210] */ | |
252 | ||
253 | /* | |
254 | * Misc settings register | |
0bacdf30 | 255 | * (reserved0-3) |
fa1c114f JS |
256 | */ |
257 | #define AR5K_MISC 0x0058 /* Register Address */ | |
258 | #define AR5K_MISC_DMA_OBS_M 0x000001e0 | |
259 | #define AR5K_MISC_DMA_OBS_S 5 | |
260 | #define AR5K_MISC_MISC_OBS_M 0x00000e00 | |
261 | #define AR5K_MISC_MISC_OBS_S 9 | |
262 | #define AR5K_MISC_MAC_OBS_LSB_M 0x00007000 | |
263 | #define AR5K_MISC_MAC_OBS_LSB_S 12 | |
264 | #define AR5K_MISC_MAC_OBS_MSB_M 0x00038000 | |
265 | #define AR5K_MISC_MAC_OBS_MSB_S 15 | |
266 | #define AR5K_MISC_LED_DECAY 0x001c0000 /* [5210] */ | |
267 | #define AR5K_MISC_LED_BLINK 0x00e00000 /* [5210] */ | |
268 | ||
269 | /* | |
270 | * QCU/DCU clock gating register (5311) | |
0bacdf30 | 271 | * (reserved4-5) |
fa1c114f JS |
272 | */ |
273 | #define AR5K_QCUDCU_CLKGT 0x005c /* Register Address (?) */ | |
274 | #define AR5K_QCUDCU_CLKGT_QCU 0x0000ffff /* Mask for QCU clock */ | |
275 | #define AR5K_QCUDCU_CLKGT_DCU 0x07ff0000 /* Mask for DCU clock */ | |
276 | ||
277 | /* | |
278 | * Interrupt Status Registers | |
279 | * | |
280 | * For 5210 there is only one status register but for | |
281 | * 5211/5212 we have one primary and 4 secondary registers. | |
282 | * So we have AR5K_ISR for 5210 and AR5K_PISR /SISRx for 5211/5212. | |
283 | * Most of these bits are common for all chipsets. | |
284 | */ | |
285 | #define AR5K_ISR 0x001c /* Register Address [5210] */ | |
286 | #define AR5K_PISR 0x0080 /* Register Address [5211+] */ | |
287 | #define AR5K_ISR_RXOK 0x00000001 /* Frame successfuly recieved */ | |
288 | #define AR5K_ISR_RXDESC 0x00000002 /* RX descriptor request */ | |
289 | #define AR5K_ISR_RXERR 0x00000004 /* Receive error */ | |
290 | #define AR5K_ISR_RXNOFRM 0x00000008 /* No frame received (receive timeout) */ | |
291 | #define AR5K_ISR_RXEOL 0x00000010 /* Empty RX descriptor */ | |
292 | #define AR5K_ISR_RXORN 0x00000020 /* Receive FIFO overrun */ | |
293 | #define AR5K_ISR_TXOK 0x00000040 /* Frame successfuly transmited */ | |
294 | #define AR5K_ISR_TXDESC 0x00000080 /* TX descriptor request */ | |
295 | #define AR5K_ISR_TXERR 0x00000100 /* Transmit error */ | |
296 | #define AR5K_ISR_TXNOFRM 0x00000200 /* No frame transmited (transmit timeout) */ | |
297 | #define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */ | |
298 | #define AR5K_ISR_TXURN 0x00000800 /* Transmit FIFO underrun */ | |
299 | #define AR5K_ISR_MIB 0x00001000 /* Update MIB counters */ | |
0bacdf30 | 300 | #define AR5K_ISR_SWI 0x00002000 /* Software interrupt */ |
fa1c114f | 301 | #define AR5K_ISR_RXPHY 0x00004000 /* PHY error */ |
0bacdf30 | 302 | #define AR5K_ISR_RXKCM 0x00008000 /* RX Key cache miss */ |
fa1c114f | 303 | #define AR5K_ISR_SWBA 0x00010000 /* Software beacon alert */ |
1bef016a | 304 | #define AR5K_ISR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */ |
fa1c114f JS |
305 | #define AR5K_ISR_BMISS 0x00040000 /* Beacon missed */ |
306 | #define AR5K_ISR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ | |
307 | #define AR5K_ISR_BNR 0x00100000 /* Beacon not ready [5211+] */ | |
0bacdf30 NK |
308 | #define AR5K_ISR_MCABT 0x00100000 /* Master Cycle Abort [5210] */ |
309 | #define AR5K_ISR_RXCHIRP 0x00200000 /* CHIRP Received [5212+] */ | |
310 | #define AR5K_ISR_SSERR 0x00200000 /* Signaled System Error [5210] */ | |
311 | #define AR5K_ISR_DPERR 0x00400000 /* Det par Error (?) [5210] */ | |
1bef016a NK |
312 | #define AR5K_ISR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */ |
313 | #define AR5K_ISR_TIM 0x00800000 /* [5211+] */ | |
314 | #define AR5K_ISR_BCNMISC 0x00800000 /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT, | |
315 | CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */ | |
316 | #define AR5K_ISR_GPIO 0x01000000 /* GPIO (rf kill) */ | |
317 | #define AR5K_ISR_QCBRORN 0x02000000 /* QCU CBR overrun [5211+] */ | |
318 | #define AR5K_ISR_QCBRURN 0x04000000 /* QCU CBR underrun [5211+] */ | |
319 | #define AR5K_ISR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */ | |
fa1c114f JS |
320 | |
321 | /* | |
322 | * Secondary status registers [5211+] (0 - 4) | |
323 | * | |
1bef016a NK |
324 | * These give the status for each QCU, only QCUs 0-9 are |
325 | * represented. | |
fa1c114f JS |
326 | */ |
327 | #define AR5K_SISR0 0x0084 /* Register Address [5211+] */ | |
328 | #define AR5K_SISR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */ | |
1bef016a | 329 | #define AR5K_SISR0_QCU_TXOK_S 0 |
fa1c114f | 330 | #define AR5K_SISR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */ |
1bef016a | 331 | #define AR5K_SISR0_QCU_TXDESC_S 16 |
fa1c114f JS |
332 | |
333 | #define AR5K_SISR1 0x0088 /* Register Address [5211+] */ | |
334 | #define AR5K_SISR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */ | |
1bef016a | 335 | #define AR5K_SISR1_QCU_TXERR_S 0 |
fa1c114f | 336 | #define AR5K_SISR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */ |
1bef016a | 337 | #define AR5K_SISR1_QCU_TXEOL_S 16 |
fa1c114f JS |
338 | |
339 | #define AR5K_SISR2 0x008c /* Register Address [5211+] */ | |
340 | #define AR5K_SISR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ | |
1bef016a | 341 | #define AR5K_SISR2_QCU_TXURN_S 0 |
f974cfdd PR |
342 | #define AR5K_SISR2_MCABT 0x00010000 /* Master Cycle Abort */ |
343 | #define AR5K_SISR2_SSERR 0x00020000 /* Signaled System Error */ | |
344 | #define AR5K_SISR2_DPERR 0x00040000 /* Bus parity error */ | |
fa1c114f JS |
345 | #define AR5K_SISR2_TIM 0x01000000 /* [5212+] */ |
346 | #define AR5K_SISR2_CAB_END 0x02000000 /* [5212+] */ | |
0bacdf30 NK |
347 | #define AR5K_SISR2_DTIM_SYNC 0x04000000 /* DTIM sync lost [5212+] */ |
348 | #define AR5K_SISR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */ | |
349 | #define AR5K_SISR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */ | |
fa1c114f | 350 | #define AR5K_SISR2_DTIM 0x20000000 /* [5212+] */ |
1bef016a | 351 | #define AR5K_SISR2_TSFOOR 0x80000000 /* TSF OOR (?) */ |
fa1c114f JS |
352 | |
353 | #define AR5K_SISR3 0x0090 /* Register Address [5211+] */ | |
354 | #define AR5K_SISR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ | |
4c674c60 | 355 | #define AR5K_SISR3_QCBRORN_S 0 |
fa1c114f | 356 | #define AR5K_SISR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */ |
1bef016a | 357 | #define AR5K_SISR3_QCBRURN_S 16 |
fa1c114f JS |
358 | |
359 | #define AR5K_SISR4 0x0094 /* Register Address [5211+] */ | |
360 | #define AR5K_SISR4_QTRIG 0x000003ff /* Mask for QTRIG */ | |
1bef016a | 361 | #define AR5K_SISR4_QTRIG_S 0 |
fa1c114f JS |
362 | |
363 | /* | |
364 | * Shadow read-and-clear interrupt status registers [5211+] | |
365 | */ | |
366 | #define AR5K_RAC_PISR 0x00c0 /* Read and clear PISR */ | |
367 | #define AR5K_RAC_SISR0 0x00c4 /* Read and clear SISR0 */ | |
368 | #define AR5K_RAC_SISR1 0x00c8 /* Read and clear SISR1 */ | |
369 | #define AR5K_RAC_SISR2 0x00cc /* Read and clear SISR2 */ | |
370 | #define AR5K_RAC_SISR3 0x00d0 /* Read and clear SISR3 */ | |
371 | #define AR5K_RAC_SISR4 0x00d4 /* Read and clear SISR4 */ | |
372 | ||
373 | /* | |
374 | * Interrupt Mask Registers | |
375 | * | |
376 | * As whith ISRs 5210 has one IMR (AR5K_IMR) and 5211/5212 has one primary | |
377 | * (AR5K_PIMR) and 4 secondary IMRs (AR5K_SIMRx). Note that ISR/IMR flags match. | |
378 | */ | |
379 | #define AR5K_IMR 0x0020 /* Register Address [5210] */ | |
380 | #define AR5K_PIMR 0x00a0 /* Register Address [5211+] */ | |
381 | #define AR5K_IMR_RXOK 0x00000001 /* Frame successfuly recieved*/ | |
382 | #define AR5K_IMR_RXDESC 0x00000002 /* RX descriptor request*/ | |
383 | #define AR5K_IMR_RXERR 0x00000004 /* Receive error*/ | |
384 | #define AR5K_IMR_RXNOFRM 0x00000008 /* No frame received (receive timeout)*/ | |
385 | #define AR5K_IMR_RXEOL 0x00000010 /* Empty RX descriptor*/ | |
386 | #define AR5K_IMR_RXORN 0x00000020 /* Receive FIFO overrun*/ | |
387 | #define AR5K_IMR_TXOK 0x00000040 /* Frame successfuly transmited*/ | |
388 | #define AR5K_IMR_TXDESC 0x00000080 /* TX descriptor request*/ | |
389 | #define AR5K_IMR_TXERR 0x00000100 /* Transmit error*/ | |
390 | #define AR5K_IMR_TXNOFRM 0x00000200 /* No frame transmited (transmit timeout)*/ | |
391 | #define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/ | |
392 | #define AR5K_IMR_TXURN 0x00000800 /* Transmit FIFO underrun*/ | |
393 | #define AR5K_IMR_MIB 0x00001000 /* Update MIB counters*/ | |
0bacdf30 | 394 | #define AR5K_IMR_SWI 0x00002000 /* Software interrupt */ |
fa1c114f | 395 | #define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/ |
0bacdf30 | 396 | #define AR5K_IMR_RXKCM 0x00008000 /* RX Key cache miss */ |
fa1c114f | 397 | #define AR5K_IMR_SWBA 0x00010000 /* Software beacon alert*/ |
1bef016a | 398 | #define AR5K_IMR_BRSSI 0x00020000 /* Beacon rssi below threshold (?) */ |
fa1c114f JS |
399 | #define AR5K_IMR_BMISS 0x00040000 /* Beacon missed*/ |
400 | #define AR5K_IMR_HIUERR 0x00080000 /* Host Interface Unit error [5211+] */ | |
401 | #define AR5K_IMR_BNR 0x00100000 /* Beacon not ready [5211+] */ | |
0bacdf30 NK |
402 | #define AR5K_IMR_MCABT 0x00100000 /* Master Cycle Abort [5210] */ |
403 | #define AR5K_IMR_RXCHIRP 0x00200000 /* CHIRP Received [5212+]*/ | |
404 | #define AR5K_IMR_SSERR 0x00200000 /* Signaled System Error [5210] */ | |
405 | #define AR5K_IMR_DPERR 0x00400000 /* Det par Error (?) [5210] */ | |
1bef016a | 406 | #define AR5K_IMR_RXDOPPLER 0x00400000 /* Doppler chirp received [5212+] */ |
fa1c114f | 407 | #define AR5K_IMR_TIM 0x00800000 /* [5211+] */ |
1bef016a NK |
408 | #define AR5K_IMR_BCNMISC 0x00800000 /* 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT, |
409 | CAB_TIMEOUT and DTIM bits from SISR2 [5212+] */ | |
fa1c114f | 410 | #define AR5K_IMR_GPIO 0x01000000 /* GPIO (rf kill)*/ |
1bef016a NK |
411 | #define AR5K_IMR_QCBRORN 0x02000000 /* QCU CBR overrun (?) [5211+] */ |
412 | #define AR5K_IMR_QCBRURN 0x04000000 /* QCU CBR underrun (?) [5211+] */ | |
413 | #define AR5K_IMR_QTRIG 0x08000000 /* QCU scheduling trigger [5211+] */ | |
fa1c114f JS |
414 | |
415 | /* | |
416 | * Secondary interrupt mask registers [5211+] (0 - 4) | |
417 | */ | |
418 | #define AR5K_SIMR0 0x00a4 /* Register Address [5211+] */ | |
419 | #define AR5K_SIMR0_QCU_TXOK 0x000003ff /* Mask for QCU_TXOK */ | |
420 | #define AR5K_SIMR0_QCU_TXOK_S 0 | |
421 | #define AR5K_SIMR0_QCU_TXDESC 0x03ff0000 /* Mask for QCU_TXDESC */ | |
422 | #define AR5K_SIMR0_QCU_TXDESC_S 16 | |
423 | ||
424 | #define AR5K_SIMR1 0x00a8 /* Register Address [5211+] */ | |
425 | #define AR5K_SIMR1_QCU_TXERR 0x000003ff /* Mask for QCU_TXERR */ | |
426 | #define AR5K_SIMR1_QCU_TXERR_S 0 | |
427 | #define AR5K_SIMR1_QCU_TXEOL 0x03ff0000 /* Mask for QCU_TXEOL */ | |
428 | #define AR5K_SIMR1_QCU_TXEOL_S 16 | |
429 | ||
430 | #define AR5K_SIMR2 0x00ac /* Register Address [5211+] */ | |
431 | #define AR5K_SIMR2_QCU_TXURN 0x000003ff /* Mask for QCU_TXURN */ | |
432 | #define AR5K_SIMR2_QCU_TXURN_S 0 | |
f974cfdd PR |
433 | #define AR5K_SIMR2_MCABT 0x00010000 /* Master Cycle Abort */ |
434 | #define AR5K_SIMR2_SSERR 0x00020000 /* Signaled System Error */ | |
435 | #define AR5K_SIMR2_DPERR 0x00040000 /* Bus parity error */ | |
fa1c114f JS |
436 | #define AR5K_SIMR2_TIM 0x01000000 /* [5212+] */ |
437 | #define AR5K_SIMR2_CAB_END 0x02000000 /* [5212+] */ | |
0bacdf30 NK |
438 | #define AR5K_SIMR2_DTIM_SYNC 0x04000000 /* DTIM Sync lost [5212+] */ |
439 | #define AR5K_SIMR2_BCN_TIMEOUT 0x08000000 /* Beacon Timeout [5212+] */ | |
440 | #define AR5K_SIMR2_CAB_TIMEOUT 0x10000000 /* CAB Timeout [5212+] */ | |
fa1c114f | 441 | #define AR5K_SIMR2_DTIM 0x20000000 /* [5212+] */ |
1bef016a | 442 | #define AR5K_SIMR2_TSFOOR 0x80000000 /* TSF OOR (?) */ |
fa1c114f JS |
443 | |
444 | #define AR5K_SIMR3 0x00b0 /* Register Address [5211+] */ | |
445 | #define AR5K_SIMR3_QCBRORN 0x000003ff /* Mask for QCBRORN */ | |
446 | #define AR5K_SIMR3_QCBRORN_S 0 | |
447 | #define AR5K_SIMR3_QCBRURN 0x03ff0000 /* Mask for QCBRURN */ | |
448 | #define AR5K_SIMR3_QCBRURN_S 16 | |
449 | ||
450 | #define AR5K_SIMR4 0x00b4 /* Register Address [5211+] */ | |
451 | #define AR5K_SIMR4_QTRIG 0x000003ff /* Mask for QTRIG */ | |
452 | #define AR5K_SIMR4_QTRIG_S 0 | |
453 | ||
0bacdf30 NK |
454 | /* |
455 | * DMA Debug registers 0-7 | |
456 | * 0xe0 - 0xfc | |
457 | */ | |
fa1c114f JS |
458 | |
459 | /* | |
460 | * Decompression mask registers [5212+] | |
461 | */ | |
0bacdf30 NK |
462 | #define AR5K_DCM_ADDR 0x0400 /*Decompression mask address (index) */ |
463 | #define AR5K_DCM_DATA 0x0404 /*Decompression mask data */ | |
464 | ||
465 | /* | |
466 | * Wake On Wireless pattern control register [5212+] | |
467 | */ | |
468 | #define AR5K_WOW_PCFG 0x0410 /* Register Address */ | |
469 | #define AR5K_WOW_PCFG_PAT_MATCH_EN 0x00000001 /* Pattern match enable */ | |
470 | #define AR5K_WOW_PCFG_LONG_FRAME_POL 0x00000002 /* Long frame policy */ | |
471 | #define AR5K_WOW_PCFG_WOBMISS 0x00000004 /* Wake on bea(con) miss (?) */ | |
472 | #define AR5K_WOW_PCFG_PAT_0_EN 0x00000100 /* Enable pattern 0 */ | |
473 | #define AR5K_WOW_PCFG_PAT_1_EN 0x00000200 /* Enable pattern 1 */ | |
474 | #define AR5K_WOW_PCFG_PAT_2_EN 0x00000400 /* Enable pattern 2 */ | |
475 | #define AR5K_WOW_PCFG_PAT_3_EN 0x00000800 /* Enable pattern 3 */ | |
476 | #define AR5K_WOW_PCFG_PAT_4_EN 0x00001000 /* Enable pattern 4 */ | |
477 | #define AR5K_WOW_PCFG_PAT_5_EN 0x00002000 /* Enable pattern 5 */ | |
478 | ||
479 | /* | |
480 | * Wake On Wireless pattern index register (?) [5212+] | |
481 | */ | |
482 | #define AR5K_WOW_PAT_IDX 0x0414 | |
483 | ||
484 | /* | |
485 | * Wake On Wireless pattern data register [5212+] | |
486 | */ | |
487 | #define AR5K_WOW_PAT_DATA 0x0418 /* Register Address */ | |
488 | #define AR5K_WOW_PAT_DATA_0_3_V 0x00000001 /* Pattern 0, 3 value */ | |
489 | #define AR5K_WOW_PAT_DATA_1_4_V 0x00000100 /* Pattern 1, 4 value */ | |
490 | #define AR5K_WOW_PAT_DATA_2_5_V 0x00010000 /* Pattern 2, 5 value */ | |
491 | #define AR5K_WOW_PAT_DATA_0_3_M 0x01000000 /* Pattern 0, 3 mask */ | |
492 | #define AR5K_WOW_PAT_DATA_1_4_M 0x04000000 /* Pattern 1, 4 mask */ | |
493 | #define AR5K_WOW_PAT_DATA_2_5_M 0x10000000 /* Pattern 2, 5 mask */ | |
fa1c114f JS |
494 | |
495 | /* | |
496 | * Decompression configuration registers [5212+] | |
497 | */ | |
0bacdf30 NK |
498 | #define AR5K_DCCFG 0x0420 /* Register Address */ |
499 | #define AR5K_DCCFG_GLOBAL_EN 0x00000001 /* Enable decompression on all queues */ | |
500 | #define AR5K_DCCFG_BYPASS_EN 0x00000002 /* Bypass decompression */ | |
501 | #define AR5K_DCCFG_BCAST_EN 0x00000004 /* Enable decompression for bcast frames */ | |
502 | #define AR5K_DCCFG_MCAST_EN 0x00000008 /* Enable decompression for mcast frames */ | |
fa1c114f JS |
503 | |
504 | /* | |
505 | * Compression configuration registers [5212+] | |
506 | */ | |
0bacdf30 NK |
507 | #define AR5K_CCFG 0x0600 /* Register Address */ |
508 | #define AR5K_CCFG_WINDOW_SIZE 0x00000007 /* Compression window size */ | |
509 | #define AR5K_CCFG_CPC_EN 0x00000008 /* Enable performance counters */ | |
510 | ||
511 | #define AR5K_CCFG_CCU 0x0604 /* Register Address */ | |
512 | #define AR5K_CCFG_CCU_CUP_EN 0x00000001 /* CCU Catchup enable */ | |
513 | #define AR5K_CCFG_CCU_CREDIT 0x00000002 /* CCU Credit (field) */ | |
514 | #define AR5K_CCFG_CCU_CD_THRES 0x00000080 /* CCU Cyc(lic?) debt threshold (field) */ | |
515 | #define AR5K_CCFG_CCU_CUP_LCNT 0x00010000 /* CCU Catchup lit(?) count */ | |
516 | #define AR5K_CCFG_CCU_INIT 0x00100200 /* Initial value during reset */ | |
fa1c114f JS |
517 | |
518 | /* | |
519 | * Compression performance counter registers [5212+] | |
520 | */ | |
521 | #define AR5K_CPC0 0x0610 /* Compression performance counter 0 */ | |
522 | #define AR5K_CPC1 0x0614 /* Compression performance counter 1*/ | |
523 | #define AR5K_CPC2 0x0618 /* Compression performance counter 2 */ | |
524 | #define AR5K_CPC3 0x061c /* Compression performance counter 3 */ | |
0bacdf30 | 525 | #define AR5K_CPCOVF 0x0620 /* Compression performance overflow */ |
fa1c114f JS |
526 | |
527 | ||
528 | /* | |
529 | * Queue control unit (QCU) registers [5211+] | |
530 | * | |
531 | * Card has 12 TX Queues but i see that only 0-9 are used (?) | |
532 | * both in binary HAL (see ah.h) and ar5k. Each queue has it's own | |
533 | * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate) | |
534 | * configuration register (0x08c0 - 0x08ec), a ready time configuration | |
535 | * register (0x0900 - 0x092c), a misc configuration register (0x09c0 - | |
536 | * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some | |
537 | * global registers, QCU transmit enable/disable and "one shot arm (?)" | |
538 | * set/clear, which contain status for all queues (we shift by 1 for each | |
539 | * queue). To access these registers easily we define some macros here | |
540 | * that are used inside HAL. For more infos check out *_tx_queue functs. | |
fa1c114f JS |
541 | */ |
542 | ||
543 | /* | |
544 | * Generic QCU Register access macros | |
545 | */ | |
546 | #define AR5K_QUEUE_REG(_r, _q) (((_q) << 2) + _r) | |
547 | #define AR5K_QCU_GLOBAL_READ(_r, _q) (AR5K_REG_READ(_r) & (1 << _q)) | |
548 | #define AR5K_QCU_GLOBAL_WRITE(_r, _q) AR5K_REG_WRITE(_r, (1 << _q)) | |
549 | ||
550 | /* | |
551 | * QCU Transmit descriptor pointer registers | |
552 | */ | |
553 | #define AR5K_QCU_TXDP_BASE 0x0800 /* Register Address - Queue0 TXDP */ | |
554 | #define AR5K_QUEUE_TXDP(_q) AR5K_QUEUE_REG(AR5K_QCU_TXDP_BASE, _q) | |
555 | ||
556 | /* | |
557 | * QCU Transmit enable register | |
558 | */ | |
559 | #define AR5K_QCU_TXE 0x0840 | |
560 | #define AR5K_ENABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXE, _q) | |
561 | #define AR5K_QUEUE_ENABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXE, _q) | |
562 | ||
563 | /* | |
564 | * QCU Transmit disable register | |
565 | */ | |
566 | #define AR5K_QCU_TXD 0x0880 | |
567 | #define AR5K_DISABLE_QUEUE(_q) AR5K_QCU_GLOBAL_WRITE(AR5K_QCU_TXD, _q) | |
568 | #define AR5K_QUEUE_DISABLED(_q) AR5K_QCU_GLOBAL_READ(AR5K_QCU_TXD, _q) | |
569 | ||
570 | /* | |
571 | * QCU Constant Bit Rate configuration registers | |
572 | */ | |
573 | #define AR5K_QCU_CBRCFG_BASE 0x08c0 /* Register Address - Queue0 CBRCFG */ | |
574 | #define AR5K_QCU_CBRCFG_INTVAL 0x00ffffff /* CBR Interval mask */ | |
575 | #define AR5K_QCU_CBRCFG_INTVAL_S 0 | |
576 | #define AR5K_QCU_CBRCFG_ORN_THRES 0xff000000 /* CBR overrun threshold mask */ | |
577 | #define AR5K_QCU_CBRCFG_ORN_THRES_S 24 | |
578 | #define AR5K_QUEUE_CBRCFG(_q) AR5K_QUEUE_REG(AR5K_QCU_CBRCFG_BASE, _q) | |
579 | ||
580 | /* | |
581 | * QCU Ready time configuration registers | |
582 | */ | |
583 | #define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */ | |
584 | #define AR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff /* Ready time interval mask */ | |
585 | #define AR5K_QCU_RDYTIMECFG_INTVAL_S 0 | |
fa1c114f JS |
586 | #define AR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 /* Ready time enable mask */ |
587 | #define AR5K_QUEUE_RDYTIMECFG(_q) AR5K_QUEUE_REG(AR5K_QCU_RDYTIMECFG_BASE, _q) | |
588 | ||
589 | /* | |
590 | * QCU one shot arm set registers | |
591 | */ | |
592 | #define AR5K_QCU_ONESHOTARM_SET 0x0940 /* Register Address -QCU "one shot arm set (?)" */ | |
593 | #define AR5K_QCU_ONESHOTARM_SET_M 0x0000ffff | |
594 | ||
595 | /* | |
596 | * QCU one shot arm clear registers | |
597 | */ | |
598 | #define AR5K_QCU_ONESHOTARM_CLEAR 0x0980 /* Register Address -QCU "one shot arm clear (?)" */ | |
599 | #define AR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff | |
600 | ||
601 | /* | |
602 | * QCU misc registers | |
603 | */ | |
604 | #define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */ | |
605 | #define AR5K_QCU_MISC_FRSHED_M 0x0000000f /* Frame sheduling mask */ | |
0bacdf30 NK |
606 | #define AR5K_QCU_MISC_FRSHED_ASAP 0 /* ASAP */ |
607 | #define AR5K_QCU_MISC_FRSHED_CBR 1 /* Constant Bit Rate */ | |
1bef016a NK |
608 | #define AR5K_QCU_MISC_FRSHED_DBA_GT 2 /* DMA Beacon alert gated */ |
609 | #define AR5K_QCU_MISC_FRSHED_TIM_GT 3 /* TIMT gated */ | |
610 | #define AR5K_QCU_MISC_FRSHED_BCN_SENT_GT 4 /* Beacon sent gated */ | |
fa1c114f | 611 | #define AR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 /* Oneshot enable */ |
1bef016a NK |
612 | #define AR5K_QCU_MISC_CBREXP_DIS 0x00000020 /* Disable CBR expired counter (normal queue) */ |
613 | #define AR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040 /* Disable CBR expired counter (beacon queue) */ | |
0bacdf30 | 614 | #define AR5K_QCU_MISC_BCN_ENABLE 0x00000080 /* Enable Beacon use */ |
1bef016a NK |
615 | #define AR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 /* CBR expired threshold enabled */ |
616 | #define AR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200 /* TXE reset when RDYTIME expired or VEOL */ | |
0bacdf30 NK |
617 | #define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400 /* CBR threshold (counter) reset */ |
618 | #define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU early termination */ | |
619 | #define AR5K_QCU_MISC_DCU_CMP_EN 0x00001000 /* Enable frame compression */ | |
fa1c114f JS |
620 | #define AR5K_QUEUE_MISC(_q) AR5K_QUEUE_REG(AR5K_QCU_MISC_BASE, _q) |
621 | ||
622 | ||
623 | /* | |
624 | * QCU status registers | |
625 | */ | |
626 | #define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */ | |
627 | #define AR5K_QCU_STS_FRMPENDCNT 0x00000003 /* Frames pending counter */ | |
0bacdf30 | 628 | #define AR5K_QCU_STS_CBREXPCNT 0x0000ff00 /* CBR expired counter */ |
fa1c114f JS |
629 | #define AR5K_QUEUE_STATUS(_q) AR5K_QUEUE_REG(AR5K_QCU_STS_BASE, _q) |
630 | ||
631 | /* | |
632 | * QCU ready time shutdown register | |
633 | */ | |
634 | #define AR5K_QCU_RDYTIMESHDN 0x0a40 | |
635 | #define AR5K_QCU_RDYTIMESHDN_M 0x000003ff | |
636 | ||
637 | /* | |
638 | * QCU compression buffer base registers [5212+] | |
639 | */ | |
640 | #define AR5K_QCU_CBB_SELECT 0x0b00 | |
641 | #define AR5K_QCU_CBB_ADDR 0x0b04 | |
0bacdf30 | 642 | #define AR5K_QCU_CBB_ADDR_S 9 |
fa1c114f JS |
643 | |
644 | /* | |
645 | * QCU compression buffer configuration register [5212+] | |
0bacdf30 | 646 | * (buffer size) |
fa1c114f JS |
647 | */ |
648 | #define AR5K_QCU_CBCFG 0x0b08 | |
649 | ||
650 | ||
651 | ||
652 | /* | |
653 | * Distributed Coordination Function (DCF) control unit (DCU) | |
654 | * registers [5211+] | |
655 | * | |
656 | * These registers control the various characteristics of each queue | |
657 | * for 802.11e (WME) combatibility so they go together with | |
658 | * QCU registers in pairs. For each queue we have a QCU mask register, | |
659 | * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c), | |
660 | * a retry limit register (0x1080 - 0x10ac), a channel time register | |
661 | * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and | |
662 | * a sequence number register (0x1140 - 0x116c). It seems that "global" | |
663 | * registers here afect all queues (see use of DCU_GBL_IFS_SLOT in ar5k). | |
664 | * We use the same macros here for easier register access. | |
665 | * | |
666 | */ | |
667 | ||
668 | /* | |
669 | * DCU QCU mask registers | |
670 | */ | |
671 | #define AR5K_DCU_QCUMASK_BASE 0x1000 /* Register Address -Queue0 DCU_QCUMASK */ | |
672 | #define AR5K_DCU_QCUMASK_M 0x000003ff | |
673 | #define AR5K_QUEUE_QCUMASK(_q) AR5K_QUEUE_REG(AR5K_DCU_QCUMASK_BASE, _q) | |
674 | ||
675 | /* | |
676 | * DCU local Inter Frame Space settings register | |
677 | */ | |
678 | #define AR5K_DCU_LCL_IFS_BASE 0x1040 /* Register Address -Queue0 DCU_LCL_IFS */ | |
679 | #define AR5K_DCU_LCL_IFS_CW_MIN 0x000003ff /* Minimum Contention Window */ | |
680 | #define AR5K_DCU_LCL_IFS_CW_MIN_S 0 | |
681 | #define AR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00 /* Maximum Contention Window */ | |
682 | #define AR5K_DCU_LCL_IFS_CW_MAX_S 10 | |
683 | #define AR5K_DCU_LCL_IFS_AIFS 0x0ff00000 /* Arbitrated Interframe Space */ | |
684 | #define AR5K_DCU_LCL_IFS_AIFS_S 20 | |
1bef016a | 685 | #define AR5K_DCU_LCL_IFS_AIFS_MAX 0xfc /* Anything above that can cause DCU to hang */ |
fa1c114f JS |
686 | #define AR5K_QUEUE_DFS_LOCAL_IFS(_q) AR5K_QUEUE_REG(AR5K_DCU_LCL_IFS_BASE, _q) |
687 | ||
688 | /* | |
689 | * DCU retry limit registers | |
690 | */ | |
691 | #define AR5K_DCU_RETRY_LMT_BASE 0x1080 /* Register Address -Queue0 DCU_RETRY_LMT */ | |
692 | #define AR5K_DCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */ | |
693 | #define AR5K_DCU_RETRY_LMT_SH_RETRY_S 0 | |
694 | #define AR5K_DCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry limit mask */ | |
695 | #define AR5K_DCU_RETRY_LMT_LG_RETRY_S 4 | |
696 | #define AR5K_DCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask (?) */ | |
697 | #define AR5K_DCU_RETRY_LMT_SSH_RETRY_S 8 | |
698 | #define AR5K_DCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask (?) */ | |
699 | #define AR5K_DCU_RETRY_LMT_SLG_RETRY_S 14 | |
700 | #define AR5K_QUEUE_DFS_RETRY_LIMIT(_q) AR5K_QUEUE_REG(AR5K_DCU_RETRY_LMT_BASE, _q) | |
701 | ||
702 | /* | |
703 | * DCU channel time registers | |
704 | */ | |
705 | #define AR5K_DCU_CHAN_TIME_BASE 0x10c0 /* Register Address -Queue0 DCU_CHAN_TIME */ | |
706 | #define AR5K_DCU_CHAN_TIME_DUR 0x000fffff /* Channel time duration */ | |
707 | #define AR5K_DCU_CHAN_TIME_DUR_S 0 | |
708 | #define AR5K_DCU_CHAN_TIME_ENABLE 0x00100000 /* Enable channel time */ | |
709 | #define AR5K_QUEUE_DFS_CHANNEL_TIME(_q) AR5K_QUEUE_REG(AR5K_DCU_CHAN_TIME_BASE, _q) | |
710 | ||
711 | /* | |
712 | * DCU misc registers [5211+] | |
713 | * | |
1bef016a | 714 | * Note: Arbiter lockout control controls the |
fa1c114f JS |
715 | * behaviour on low priority queues when we have multiple queues |
716 | * with pending frames. Intra-frame lockout means we wait until | |
717 | * the queue's current frame transmits (with post frame backoff and bursting) | |
718 | * before we transmit anything else and global lockout means we | |
719 | * wait for the whole queue to finish before higher priority queues | |
720 | * can transmit (this is used on beacon and CAB queues). | |
721 | * No lockout means there is no special handling. | |
722 | */ | |
723 | #define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */ | |
1bef016a NK |
724 | #define AR5K_DCU_MISC_BACKOFF 0x0000003f /* Mask for backoff threshold */ |
725 | #define AR5K_DCU_MISC_ETS_RTS_POL 0x00000040 /* End of transmission series | |
726 | station RTS/data failure count | |
727 | reset policy (?) */ | |
728 | #define AR5K_DCU_MISC_ETS_CW_POL 0x00000080 /* End of transmission series | |
729 | CW reset policy */ | |
730 | #define AR5K_DCU_MISC_FRAG_WAIT 0x00000100 /* Wait for next fragment */ | |
fa1c114f | 731 | #define AR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 /* Enable backoff while bursting */ |
0bacdf30 NK |
732 | #define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll enable */ |
733 | #define AR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 /* Persistent backoff */ | |
734 | #define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch */ | |
fa1c114f | 735 | #define AR5K_DCU_MISC_VIRTCOL 0x0000c000 /* Mask for Virtual Collision (?) */ |
1bef016a NK |
736 | #define AR5K_DCU_MISC_VIRTCOL_NORMAL 0 |
737 | #define AR5K_DCU_MISC_VIRTCOL_IGNORE 1 | |
0bacdf30 | 738 | #define AR5K_DCU_MISC_BCN_ENABLE 0x00010000 /* Enable Beacon use */ |
fa1c114f JS |
739 | #define AR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 /* Arbiter lockout control mask */ |
740 | #define AR5K_DCU_MISC_ARBLOCK_CTL_S 17 | |
0bacdf30 | 741 | #define AR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 /* No arbiter lockout */ |
fa1c114f JS |
742 | #define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 /* Intra-frame lockout */ |
743 | #define AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL 2 /* Global lockout */ | |
0bacdf30 NK |
744 | #define AR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 /* Ignore Arbiter lockout */ |
745 | #define AR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Disable sequence number increment */ | |
746 | #define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff */ | |
747 | #define AR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual Collision cw policy */ | |
748 | #define AR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 /* Blown IFS policy (?) */ | |
fa1c114f JS |
749 | #define AR5K_DCU_MISC_SEQNUM_CTL 0x01000000 /* Sequence number control (?) */ |
750 | #define AR5K_QUEUE_DFS_MISC(_q) AR5K_QUEUE_REG(AR5K_DCU_MISC_BASE, _q) | |
751 | ||
752 | /* | |
753 | * DCU frame sequence number registers | |
754 | */ | |
0bacdf30 NK |
755 | #define AR5K_DCU_SEQNUM_BASE 0x1140 |
756 | #define AR5K_DCU_SEQNUM_M 0x00000fff | |
e8f055f0 | 757 | #define AR5K_QUEUE_DCU_SEQNUM(_q) AR5K_QUEUE_REG(AR5K_DCU_SEQNUM_BASE, _q) |
fa1c114f JS |
758 | |
759 | /* | |
0bacdf30 | 760 | * DCU global IFS SIFS register |
fa1c114f JS |
761 | */ |
762 | #define AR5K_DCU_GBL_IFS_SIFS 0x1030 | |
763 | #define AR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff | |
764 | ||
765 | /* | |
0bacdf30 | 766 | * DCU global IFS slot interval register |
fa1c114f JS |
767 | */ |
768 | #define AR5K_DCU_GBL_IFS_SLOT 0x1070 | |
769 | #define AR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff | |
770 | ||
771 | /* | |
0bacdf30 | 772 | * DCU global IFS EIFS register |
fa1c114f JS |
773 | */ |
774 | #define AR5K_DCU_GBL_IFS_EIFS 0x10b0 | |
775 | #define AR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff | |
776 | ||
777 | /* | |
0bacdf30 NK |
778 | * DCU global IFS misc register |
779 | * | |
780 | * LFSR stands for Linear Feedback Shift Register | |
781 | * and it's used for generating pseudo-random | |
782 | * number sequences. | |
783 | * | |
784 | * (If i understand corectly, random numbers are | |
785 | * used for idle sensing -multiplied with cwmin/max etc-) | |
fa1c114f JS |
786 | */ |
787 | #define AR5K_DCU_GBL_IFS_MISC 0x10f0 /* Register Address */ | |
0bacdf30 NK |
788 | #define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007 /* LFSR Slice Select */ |
789 | #define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode */ | |
790 | #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask */ | |
791 | #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 /* USEC Duration mask */ | |
1bef016a | 792 | #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S 10 |
0bacdf30 | 793 | #define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000 /* DCU Arbiter delay mask */ |
1bef016a | 794 | #define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST 0x00400000 /* SIFS cnt reset policy (?) */ |
0bacdf30 NK |
795 | #define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST 0x00800000 /* AIFS cnt reset policy (?) */ |
796 | #define AR5K_DCU_GBL_IFS_MISC_RND_LFSR_SL_DIS 0x01000000 /* Disable random LFSR slice */ | |
fa1c114f JS |
797 | |
798 | /* | |
799 | * DCU frame prefetch control register | |
800 | */ | |
0bacdf30 NK |
801 | #define AR5K_DCU_FP 0x1230 /* Register Address */ |
802 | #define AR5K_DCU_FP_NOBURST_DCU_EN 0x00000001 /* Enable non-burst prefetch on DCU (?) */ | |
803 | #define AR5K_DCU_FP_NOBURST_EN 0x00000010 /* Enable non-burst prefetch (?) */ | |
804 | #define AR5K_DCU_FP_BURST_DCU_EN 0x00000020 /* Enable burst prefetch on DCU (?) */ | |
fa1c114f JS |
805 | |
806 | /* | |
807 | * DCU transmit pause control/status register | |
808 | */ | |
809 | #define AR5K_DCU_TXP 0x1270 /* Register Address */ | |
0bacdf30 NK |
810 | #define AR5K_DCU_TXP_M 0x000003ff /* Tx pause mask */ |
811 | #define AR5K_DCU_TXP_STATUS 0x00010000 /* Tx pause status */ | |
812 | ||
813 | /* | |
814 | * DCU transmit filter table 0 (32 entries) | |
a406c139 NK |
815 | * each entry contains a 32bit slice of the |
816 | * 128bit tx filter for each DCU (4 slices per DCU) | |
0bacdf30 NK |
817 | */ |
818 | #define AR5K_DCU_TX_FILTER_0_BASE 0x1038 | |
819 | #define AR5K_DCU_TX_FILTER_0(_n) (AR5K_DCU_TX_FILTER_0_BASE + (_n * 64)) | |
fa1c114f JS |
820 | |
821 | /* | |
0bacdf30 | 822 | * DCU transmit filter table 1 (16 entries) |
fa1c114f | 823 | */ |
0bacdf30 | 824 | #define AR5K_DCU_TX_FILTER_1_BASE 0x103c |
a406c139 | 825 | #define AR5K_DCU_TX_FILTER_1(_n) (AR5K_DCU_TX_FILTER_1_BASE + (_n * 64)) |
fa1c114f JS |
826 | |
827 | /* | |
828 | * DCU clear transmit filter register | |
829 | */ | |
830 | #define AR5K_DCU_TX_FILTER_CLR 0x143c | |
831 | ||
832 | /* | |
833 | * DCU set transmit filter register | |
834 | */ | |
835 | #define AR5K_DCU_TX_FILTER_SET 0x147c | |
836 | ||
837 | /* | |
838 | * Reset control register | |
fa1c114f JS |
839 | */ |
840 | #define AR5K_RESET_CTL 0x4000 /* Register Address */ | |
841 | #define AR5K_RESET_CTL_PCU 0x00000001 /* Protocol Control Unit reset */ | |
842 | #define AR5K_RESET_CTL_DMA 0x00000002 /* DMA (Rx/Tx) reset [5210] */ | |
843 | #define AR5K_RESET_CTL_BASEBAND 0x00000002 /* Baseband reset [5211+] */ | |
844 | #define AR5K_RESET_CTL_MAC 0x00000004 /* MAC reset (PCU+Baseband ?) [5210] */ | |
845 | #define AR5K_RESET_CTL_PHY 0x00000008 /* PHY reset [5210] */ | |
846 | #define AR5K_RESET_CTL_PCI 0x00000010 /* PCI Core reset (interrupts etc) */ | |
fa1c114f JS |
847 | |
848 | /* | |
849 | * Sleep control register | |
850 | */ | |
851 | #define AR5K_SLEEP_CTL 0x4004 /* Register Address */ | |
852 | #define AR5K_SLEEP_CTL_SLDUR 0x0000ffff /* Sleep duration mask */ | |
853 | #define AR5K_SLEEP_CTL_SLDUR_S 0 | |
854 | #define AR5K_SLEEP_CTL_SLE 0x00030000 /* Sleep enable mask */ | |
855 | #define AR5K_SLEEP_CTL_SLE_S 16 | |
856 | #define AR5K_SLEEP_CTL_SLE_WAKE 0x00000000 /* Force chip awake */ | |
857 | #define AR5K_SLEEP_CTL_SLE_SLP 0x00010000 /* Force chip sleep */ | |
1bef016a | 858 | #define AR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 /* Normal sleep policy */ |
fa1c114f | 859 | #define AR5K_SLEEP_CTL_SLE_UNITS 0x00000008 /* [5211+] */ |
1bef016a NK |
860 | #define AR5K_SLEEP_CTL_DUR_TIM_POL 0x00040000 /* Sleep duration timing policy */ |
861 | #define AR5K_SLEEP_CTL_DUR_WRITE_POL 0x00080000 /* Sleep duration write policy */ | |
862 | #define AR5K_SLEEP_CTL_SLE_POL 0x00100000 /* Sleep policy mode */ | |
fa1c114f JS |
863 | |
864 | /* | |
865 | * Interrupt pending register | |
866 | */ | |
867 | #define AR5K_INTPEND 0x4008 | |
868 | #define AR5K_INTPEND_M 0x00000001 | |
869 | ||
870 | /* | |
871 | * Sleep force register | |
872 | */ | |
873 | #define AR5K_SFR 0x400c | |
0bacdf30 | 874 | #define AR5K_SFR_EN 0x00000001 |
fa1c114f JS |
875 | |
876 | /* | |
877 | * PCI configuration register | |
1bef016a | 878 | * TODO: Fix LED stuff |
fa1c114f JS |
879 | */ |
880 | #define AR5K_PCICFG 0x4010 /* Register Address */ | |
881 | #define AR5K_PCICFG_EEAE 0x00000001 /* Eeprom access enable [5210] */ | |
1bef016a | 882 | #define AR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002 /* Enable sleep clock */ |
fa1c114f JS |
883 | #define AR5K_PCICFG_CLKRUNEN 0x00000004 /* CLKRUN enable [5211+] */ |
884 | #define AR5K_PCICFG_EESIZE 0x00000018 /* Mask for EEPROM size [5211+] */ | |
885 | #define AR5K_PCICFG_EESIZE_S 3 | |
886 | #define AR5K_PCICFG_EESIZE_4K 0 /* 4K */ | |
887 | #define AR5K_PCICFG_EESIZE_8K 1 /* 8K */ | |
888 | #define AR5K_PCICFG_EESIZE_16K 2 /* 16K */ | |
1bef016a | 889 | #define AR5K_PCICFG_EESIZE_FAIL 3 /* Failed to get size [5211+] */ |
fa1c114f JS |
890 | #define AR5K_PCICFG_LED 0x00000060 /* Led status [5211+] */ |
891 | #define AR5K_PCICFG_LED_NONE 0x00000000 /* Default [5211+] */ | |
892 | #define AR5K_PCICFG_LED_PEND 0x00000020 /* Scan / Auth pending */ | |
893 | #define AR5K_PCICFG_LED_ASSOC 0x00000040 /* Associated */ | |
894 | #define AR5K_PCICFG_BUS_SEL 0x00000380 /* Mask for "bus select" [5211+] (?) */ | |
1bef016a NK |
895 | #define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix */ |
896 | #define AR5K_PCICFG_SL_INTEN 0x00000800 /* Enable interrupts when asleep */ | |
fa1c114f | 897 | #define AR5K_PCICFG_LED_BCTL 0x00001000 /* Led blink (?) [5210] */ |
1bef016a NK |
898 | #define AR5K_PCICFG_RETRY_FIX 0x00001000 /* Enable pci core retry fix */ |
899 | #define AR5K_PCICFG_SL_INPEN 0x00002000 /* Sleep even whith pending interrupts*/ | |
fa1c114f JS |
900 | #define AR5K_PCICFG_SPWR_DN 0x00010000 /* Mask for power status */ |
901 | #define AR5K_PCICFG_LEDMODE 0x000e0000 /* Ledmode [5211+] */ | |
902 | #define AR5K_PCICFG_LEDMODE_PROP 0x00000000 /* Blink on standard traffic [5211+] */ | |
903 | #define AR5K_PCICFG_LEDMODE_PROM 0x00020000 /* Default mode (blink on any traffic) [5211+] */ | |
904 | #define AR5K_PCICFG_LEDMODE_PWR 0x00040000 /* Some other blinking mode (?) [5211+] */ | |
905 | #define AR5K_PCICFG_LEDMODE_RAND 0x00060000 /* Random blinking (?) [5211+] */ | |
0bacdf30 | 906 | #define AR5K_PCICFG_LEDBLINK 0x00700000 /* Led blink rate */ |
fa1c114f | 907 | #define AR5K_PCICFG_LEDBLINK_S 20 |
0bacdf30 | 908 | #define AR5K_PCICFG_LEDSLOW 0x00800000 /* Slowest led blink rate [5211+] */ |
fa1c114f JS |
909 | #define AR5K_PCICFG_LEDSTATE \ |
910 | (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \ | |
911 | AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW) | |
1bef016a NK |
912 | #define AR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000 /* Sleep clock rate */ |
913 | #define AR5K_PCICFG_SLEEP_CLOCK_RATE_S 24 | |
fa1c114f JS |
914 | |
915 | /* | |
916 | * "General Purpose Input/Output" (GPIO) control register | |
917 | * | |
918 | * I'm not sure about this but after looking at the code | |
919 | * for all chipsets here is what i got. | |
920 | * | |
921 | * We have 6 GPIOs (pins), each GPIO has 4 modes (2 bits) | |
922 | * Mode 0 -> always input | |
923 | * Mode 1 -> output when GPIODO for this GPIO is set to 0 | |
924 | * Mode 2 -> output when GPIODO for this GPIO is set to 1 | |
925 | * Mode 3 -> always output | |
926 | * | |
927 | * For more infos check out get_gpio/set_gpio and | |
928 | * set_gpio_input/set_gpio_output functs. | |
929 | * For more infos on gpio interrupt check out set_gpio_intr. | |
930 | */ | |
931 | #define AR5K_NUM_GPIO 6 | |
932 | ||
933 | #define AR5K_GPIOCR 0x4014 /* Register Address */ | |
934 | #define AR5K_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO interrupt */ | |
1bef016a NK |
935 | #define AR5K_GPIOCR_INT_SELL 0x00000000 /* Generate interrupt when pin is low */ |
936 | #define AR5K_GPIOCR_INT_SELH 0x00010000 /* Generate interrupt when pin is high */ | |
fa1c114f JS |
937 | #define AR5K_GPIOCR_IN(n) (0 << ((n) * 2)) /* Mode 0 for pin n */ |
938 | #define AR5K_GPIOCR_OUT0(n) (1 << ((n) * 2)) /* Mode 1 for pin n */ | |
939 | #define AR5K_GPIOCR_OUT1(n) (2 << ((n) * 2)) /* Mode 2 for pin n */ | |
940 | #define AR5K_GPIOCR_OUT(n) (3 << ((n) * 2)) /* Mode 3 for pin n */ | |
941 | #define AR5K_GPIOCR_INT_SEL(n) ((n) << 12) /* Interrupt for GPIO pin n */ | |
942 | ||
943 | /* | |
944 | * "General Purpose Input/Output" (GPIO) data output register | |
945 | */ | |
946 | #define AR5K_GPIODO 0x4018 | |
947 | ||
948 | /* | |
949 | * "General Purpose Input/Output" (GPIO) data input register | |
950 | */ | |
951 | #define AR5K_GPIODI 0x401c | |
952 | #define AR5K_GPIODI_M 0x0000002f | |
953 | ||
fa1c114f JS |
954 | /* |
955 | * Silicon revision register | |
956 | */ | |
957 | #define AR5K_SREV 0x4020 /* Register Address */ | |
958 | #define AR5K_SREV_REV 0x0000000f /* Mask for revision */ | |
959 | #define AR5K_SREV_REV_S 0 | |
960 | #define AR5K_SREV_VER 0x000000ff /* Mask for version */ | |
961 | #define AR5K_SREV_VER_S 4 | |
962 | ||
1bef016a NK |
963 | /* |
964 | * TXE write posting register | |
965 | */ | |
966 | #define AR5K_TXEPOST 0x4028 | |
967 | ||
968 | /* | |
969 | * QCU sleep mask | |
970 | */ | |
971 | #define AR5K_QCU_SLEEP_MASK 0x402c | |
972 | ||
973 | /* 0x4068 is compression buffer configuration | |
974 | * register on 5414 and pm configuration register | |
975 | * on 5424 and newer pci-e chips. */ | |
976 | ||
977 | /* | |
978 | * Compression buffer configuration | |
979 | * register (enable/disable) [5414] | |
980 | */ | |
981 | #define AR5K_5414_CBCFG 0x4068 | |
982 | #define AR5K_5414_CBCFG_BUF_DIS 0x10 /* Disable buffer */ | |
983 | ||
984 | /* | |
985 | * PCI-E Power managment configuration | |
986 | * and status register [5424+] | |
987 | */ | |
988 | #define AR5K_PCIE_PM_CTL 0x4068 /* Register address */ | |
989 | /* Only 5424 */ | |
990 | #define AR5K_PCIE_PM_CTL_L1_WHEN_D2 0x00000001 /* enable PCIe core enter L1 | |
991 | when d2_sleep_en is asserted */ | |
992 | #define AR5K_PCIE_PM_CTL_L0_L0S_CLEAR 0x00000002 /* Clear L0 and L0S counters */ | |
993 | #define AR5K_PCIE_PM_CTL_L0_L0S_EN 0x00000004 /* Start L0 nd L0S counters */ | |
994 | #define AR5K_PCIE_PM_CTL_LDRESET_EN 0x00000008 /* Enable reset when link goes | |
995 | down */ | |
996 | /* Wake On Wireless */ | |
997 | #define AR5K_PCIE_PM_CTL_PME_EN 0x00000010 /* PME Enable */ | |
998 | #define AR5K_PCIE_PM_CTL_AUX_PWR_DET 0x00000020 /* Aux power detect */ | |
999 | #define AR5K_PCIE_PM_CTL_PME_CLEAR 0x00000040 /* Clear PME */ | |
1000 | #define AR5K_PCIE_PM_CTL_PSM_D0 0x00000080 | |
1001 | #define AR5K_PCIE_PM_CTL_PSM_D1 0x00000100 | |
1002 | #define AR5K_PCIE_PM_CTL_PSM_D2 0x00000200 | |
1003 | #define AR5K_PCIE_PM_CTL_PSM_D3 0x00000400 | |
1004 | ||
1005 | /* | |
1006 | * PCI-E Workaround enable register | |
1007 | */ | |
1008 | #define AR5K_PCIE_WAEN 0x407c | |
fa1c114f | 1009 | |
1bef016a NK |
1010 | /* |
1011 | * PCI-E Serializer/Desirializer | |
1012 | * registers | |
1013 | */ | |
1014 | #define AR5K_PCIE_SERDES 0x4080 | |
1015 | #define AR5K_PCIE_SERDES_RESET 0x4084 | |
fa1c114f JS |
1016 | |
1017 | /*====EEPROM REGISTERS====*/ | |
1018 | ||
1019 | /* | |
1020 | * EEPROM access registers | |
1021 | * | |
1022 | * Here we got a difference between 5210/5211-12 | |
1023 | * read data register for 5210 is at 0x6800 and | |
1024 | * status register is at 0x6c00. There is also | |
1025 | * no eeprom command register on 5210 and the | |
1026 | * offsets are different. | |
1027 | * | |
1028 | * To read eeprom data for a specific offset: | |
1029 | * 5210 - enable eeprom access (AR5K_PCICFG_EEAE) | |
1030 | * read AR5K_EEPROM_BASE +(4 * offset) | |
1031 | * check the eeprom status register | |
1032 | * and read eeprom data register. | |
1033 | * | |
1034 | * 5211 - write offset to AR5K_EEPROM_BASE | |
1035 | * 5212 write AR5K_EEPROM_CMD_READ on AR5K_EEPROM_CMD | |
1036 | * check the eeprom status register | |
1037 | * and read eeprom data register. | |
1038 | * | |
1039 | * To write eeprom data for a specific offset: | |
1040 | * 5210 - enable eeprom access (AR5K_PCICFG_EEAE) | |
1041 | * write data to AR5K_EEPROM_BASE +(4 * offset) | |
1042 | * check the eeprom status register | |
1043 | * 5211 - write AR5K_EEPROM_CMD_RESET on AR5K_EEPROM_CMD | |
1044 | * 5212 write offset to AR5K_EEPROM_BASE | |
1045 | * write data to data register | |
1046 | * write AR5K_EEPROM_CMD_WRITE on AR5K_EEPROM_CMD | |
1047 | * check the eeprom status register | |
1048 | * | |
1049 | * For more infos check eeprom_* functs and the ar5k.c | |
1050 | * file posted in madwifi-devel mailing list. | |
1051 | * http://sourceforge.net/mailarchive/message.php?msg_id=8966525 | |
1052 | * | |
1053 | */ | |
1054 | #define AR5K_EEPROM_BASE 0x6000 | |
1055 | ||
fa1c114f JS |
1056 | /* |
1057 | * EEPROM data register | |
1058 | */ | |
1059 | #define AR5K_EEPROM_DATA_5211 0x6004 | |
1060 | #define AR5K_EEPROM_DATA_5210 0x6800 | |
1061 | #define AR5K_EEPROM_DATA (ah->ah_version == AR5K_AR5210 ? \ | |
1062 | AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211) | |
1063 | ||
1064 | /* | |
1065 | * EEPROM command register | |
1066 | */ | |
1067 | #define AR5K_EEPROM_CMD 0x6008 /* Register Addres */ | |
1068 | #define AR5K_EEPROM_CMD_READ 0x00000001 /* EEPROM read */ | |
1069 | #define AR5K_EEPROM_CMD_WRITE 0x00000002 /* EEPROM write */ | |
1070 | #define AR5K_EEPROM_CMD_RESET 0x00000004 /* EEPROM reset */ | |
1071 | ||
1072 | /* | |
1073 | * EEPROM status register | |
1074 | */ | |
1075 | #define AR5K_EEPROM_STAT_5210 0x6c00 /* Register Address [5210] */ | |
1076 | #define AR5K_EEPROM_STAT_5211 0x600c /* Register Address [5211+] */ | |
1077 | #define AR5K_EEPROM_STATUS (ah->ah_version == AR5K_AR5210 ? \ | |
1078 | AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211) | |
1079 | #define AR5K_EEPROM_STAT_RDERR 0x00000001 /* EEPROM read failed */ | |
1080 | #define AR5K_EEPROM_STAT_RDDONE 0x00000002 /* EEPROM read successful */ | |
1081 | #define AR5K_EEPROM_STAT_WRERR 0x00000004 /* EEPROM write failed */ | |
1082 | #define AR5K_EEPROM_STAT_WRDONE 0x00000008 /* EEPROM write successful */ | |
1083 | ||
1084 | /* | |
0bacdf30 | 1085 | * EEPROM config register |
fa1c114f | 1086 | */ |
0bacdf30 | 1087 | #define AR5K_EEPROM_CFG 0x6010 /* Register Addres */ |
1bef016a NK |
1088 | #define AR5K_EEPROM_CFG_SIZE 0x00000003 /* Size determination override */ |
1089 | #define AR5K_EEPROM_CFG_SIZE_AUTO 0 | |
1090 | #define AR5K_EEPROM_CFG_SIZE_4KBIT 1 | |
1091 | #define AR5K_EEPROM_CFG_SIZE_8KBIT 2 | |
1092 | #define AR5K_EEPROM_CFG_SIZE_16KBIT 3 | |
0bacdf30 NK |
1093 | #define AR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004 /* Disable write wait */ |
1094 | #define AR5K_EEPROM_CFG_CLK_RATE 0x00000018 /* Clock rate */ | |
1bef016a NK |
1095 | #define AR5K_EEPROM_CFG_CLK_RATE_S 3 |
1096 | #define AR5K_EEPROM_CFG_CLK_RATE_156KHZ 0 | |
1097 | #define AR5K_EEPROM_CFG_CLK_RATE_312KHZ 1 | |
1098 | #define AR5K_EEPROM_CFG_CLK_RATE_625KHZ 2 | |
1099 | #define AR5K_EEPROM_CFG_PROT_KEY 0x00ffff00 /* Protection key */ | |
1100 | #define AR5K_EEPROM_CFG_PROT_KEY_S 8 | |
0bacdf30 | 1101 | #define AR5K_EEPROM_CFG_LIND_EN 0x01000000 /* Enable length indicator (?) */ |
fa1c114f JS |
1102 | |
1103 | ||
1bef016a NK |
1104 | /* |
1105 | * TODO: Wake On Wireless registers | |
1106 | * Range 0x7000 - 0x7ce0 | |
1107 | */ | |
1108 | ||
fa1c114f JS |
1109 | /* |
1110 | * Protocol Control Unit (PCU) registers | |
1111 | */ | |
1112 | /* | |
1113 | * Used for checking initial register writes | |
1114 | * during channel reset (see reset func) | |
1115 | */ | |
1116 | #define AR5K_PCU_MIN 0x8000 | |
1117 | #define AR5K_PCU_MAX 0x8fff | |
1118 | ||
1119 | /* | |
f07a6c49 | 1120 | * First station id register (Lower 32 bits of MAC address) |
fa1c114f | 1121 | */ |
f07a6c49 NK |
1122 | #define AR5K_STA_ID0 0x8000 |
1123 | #define AR5K_STA_ID0_ARRD_L32 0xffffffff | |
fa1c114f JS |
1124 | |
1125 | /* | |
f07a6c49 | 1126 | * Second station id register (Upper 16 bits of MAC address + PCU settings) |
fa1c114f JS |
1127 | */ |
1128 | #define AR5K_STA_ID1 0x8004 /* Register Address */ | |
f07a6c49 | 1129 | #define AR5K_STA_ID1_ADDR_U16 0x0000ffff /* Upper 16 bits of MAC addres */ |
fa1c114f JS |
1130 | #define AR5K_STA_ID1_AP 0x00010000 /* Set AP mode */ |
1131 | #define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */ | |
0bacdf30 | 1132 | #define AR5K_STA_ID1_PWR_SV 0x00040000 /* Power save reporting */ |
fa1c114f JS |
1133 | #define AR5K_STA_ID1_NO_KEYSRCH 0x00080000 /* No key search */ |
1134 | #define AR5K_STA_ID1_NO_PSPOLL 0x00100000 /* No power save polling [5210] */ | |
1135 | #define AR5K_STA_ID1_PCF_5211 0x00100000 /* Enable PCF on [5211+] */ | |
1136 | #define AR5K_STA_ID1_PCF_5210 0x00200000 /* Enable PCF on [5210]*/ | |
1137 | #define AR5K_STA_ID1_PCF (ah->ah_version == AR5K_AR5210 ? \ | |
1138 | AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211) | |
1139 | #define AR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 /* Use default antenna */ | |
1140 | #define AR5K_STA_ID1_DESC_ANTENNA 0x00400000 /* Update antenna from descriptor */ | |
0bacdf30 NK |
1141 | #define AR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 /* Use default antenna for RTS */ |
1142 | #define AR5K_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mbit/s for ACK/CTS */ | |
1bef016a NK |
1143 | #define AR5K_STA_ID1_BASE_RATE_11B 0x02000000 /* Use 11b base rate for ACK/CTS [5211+] */ |
1144 | #define AR5K_STA_ID1_SELFGEN_DEF_ANT 0x04000000 /* Use def. antenna for self generated frames */ | |
0bacdf30 | 1145 | #define AR5K_STA_ID1_CRYPT_MIC_EN 0x08000000 /* Enable MIC */ |
1bef016a | 1146 | #define AR5K_STA_ID1_KEYSRCH_MODE 0x10000000 /* Look up key when key id != 0 */ |
0bacdf30 | 1147 | #define AR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000 /* Preserve sequence number */ |
1bef016a NK |
1148 | #define AR5K_STA_ID1_CBCIV_ENDIAN 0x40000000 /* ??? */ |
1149 | #define AR5K_STA_ID1_KEYSRCH_MCAST 0x80000000 /* Do key cache search for mcast frames */ | |
fa1c114f | 1150 | |
2bed03eb NK |
1151 | #define AR5K_STA_ID1_ANTENNA_SETTINGS (AR5K_STA_ID1_DEFAULT_ANTENNA | \ |
1152 | AR5K_STA_ID1_DESC_ANTENNA | \ | |
1153 | AR5K_STA_ID1_RTS_DEF_ANTENNA | \ | |
1154 | AR5K_STA_ID1_SELFGEN_DEF_ANT) | |
1155 | ||
fa1c114f JS |
1156 | /* |
1157 | * First BSSID register (MAC address, lower 32bits) | |
1158 | */ | |
1159 | #define AR5K_BSS_ID0 0x8008 | |
1160 | ||
1161 | /* | |
1162 | * Second BSSID register (MAC address in upper 16 bits) | |
1163 | * | |
1164 | * AID: Association ID | |
1165 | */ | |
1166 | #define AR5K_BSS_ID1 0x800c | |
1167 | #define AR5K_BSS_ID1_AID 0xffff0000 | |
1168 | #define AR5K_BSS_ID1_AID_S 16 | |
1169 | ||
1170 | /* | |
1171 | * Backoff slot time register | |
1172 | */ | |
1173 | #define AR5K_SLOT_TIME 0x8010 | |
1174 | ||
1175 | /* | |
1176 | * ACK/CTS timeout register | |
1177 | */ | |
1178 | #define AR5K_TIME_OUT 0x8014 /* Register Address */ | |
1179 | #define AR5K_TIME_OUT_ACK 0x00001fff /* ACK timeout mask */ | |
1180 | #define AR5K_TIME_OUT_ACK_S 0 | |
1181 | #define AR5K_TIME_OUT_CTS 0x1fff0000 /* CTS timeout mask */ | |
1182 | #define AR5K_TIME_OUT_CTS_S 16 | |
1183 | ||
1184 | /* | |
1185 | * RSSI threshold register | |
1186 | */ | |
1187 | #define AR5K_RSSI_THR 0x8018 /* Register Address */ | |
1188 | #define AR5K_RSSI_THR_M 0x000000ff /* Mask for RSSI threshold [5211+] */ | |
1189 | #define AR5K_RSSI_THR_BMISS_5210 0x00000700 /* Mask for Beacon Missed threshold [5210] */ | |
1190 | #define AR5K_RSSI_THR_BMISS_5210_S 8 | |
1191 | #define AR5K_RSSI_THR_BMISS_5211 0x0000ff00 /* Mask for Beacon Missed threshold [5211+] */ | |
1192 | #define AR5K_RSSI_THR_BMISS_5211_S 8 | |
1193 | #define AR5K_RSSI_THR_BMISS (ah->ah_version == AR5K_AR5210 ? \ | |
1194 | AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211) | |
1195 | #define AR5K_RSSI_THR_BMISS_S 8 | |
1196 | ||
1197 | /* | |
1198 | * 5210 has more PCU registers because there is no QCU/DCU | |
1199 | * so queue parameters are set here, this way a lot common | |
1200 | * registers have different address for 5210. To make things | |
1201 | * easier we define a macro based on ah->ah_version for common | |
1202 | * registers with different addresses and common flags. | |
1203 | */ | |
1204 | ||
1205 | /* | |
1206 | * Retry limit register | |
1207 | * | |
1208 | * Retry limit register for 5210 (no QCU/DCU so it's done in PCU) | |
1209 | */ | |
0bacdf30 | 1210 | #define AR5K_NODCU_RETRY_LMT 0x801c /* Register Address */ |
fa1c114f JS |
1211 | #define AR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f /* Short retry limit mask */ |
1212 | #define AR5K_NODCU_RETRY_LMT_SH_RETRY_S 0 | |
1213 | #define AR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 /* Long retry mask */ | |
1214 | #define AR5K_NODCU_RETRY_LMT_LG_RETRY_S 4 | |
1215 | #define AR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00 /* Station short retry limit mask */ | |
1216 | #define AR5K_NODCU_RETRY_LMT_SSH_RETRY_S 8 | |
1217 | #define AR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000 /* Station long retry limit mask */ | |
1218 | #define AR5K_NODCU_RETRY_LMT_SLG_RETRY_S 14 | |
1219 | #define AR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000 /* Minimum contention window mask */ | |
1220 | #define AR5K_NODCU_RETRY_LMT_CW_MIN_S 20 | |
1221 | ||
1222 | /* | |
1223 | * Transmit latency register | |
1224 | */ | |
1225 | #define AR5K_USEC_5210 0x8020 /* Register Address [5210] */ | |
1226 | #define AR5K_USEC_5211 0x801c /* Register Address [5211+] */ | |
1227 | #define AR5K_USEC (ah->ah_version == AR5K_AR5210 ? \ | |
1228 | AR5K_USEC_5210 : AR5K_USEC_5211) | |
0bacdf30 | 1229 | #define AR5K_USEC_1 0x0000007f /* clock cycles for 1us */ |
fa1c114f | 1230 | #define AR5K_USEC_1_S 0 |
0bacdf30 | 1231 | #define AR5K_USEC_32 0x00003f80 /* clock cycles for 1us while on 32Mhz clock */ |
fa1c114f JS |
1232 | #define AR5K_USEC_32_S 7 |
1233 | #define AR5K_USEC_TX_LATENCY_5211 0x007fc000 | |
1234 | #define AR5K_USEC_TX_LATENCY_5211_S 14 | |
1235 | #define AR5K_USEC_RX_LATENCY_5211 0x1f800000 | |
1236 | #define AR5K_USEC_RX_LATENCY_5211_S 23 | |
1237 | #define AR5K_USEC_TX_LATENCY_5210 0x000fc000 /* also for 5311 */ | |
1238 | #define AR5K_USEC_TX_LATENCY_5210_S 14 | |
1239 | #define AR5K_USEC_RX_LATENCY_5210 0x03f00000 /* also for 5311 */ | |
1240 | #define AR5K_USEC_RX_LATENCY_5210_S 20 | |
1241 | ||
1242 | /* | |
1243 | * PCU beacon control register | |
1244 | */ | |
0bacdf30 NK |
1245 | #define AR5K_BEACON_5210 0x8024 /*Register Address [5210] */ |
1246 | #define AR5K_BEACON_5211 0x8020 /*Register Address [5211+] */ | |
fa1c114f JS |
1247 | #define AR5K_BEACON (ah->ah_version == AR5K_AR5210 ? \ |
1248 | AR5K_BEACON_5210 : AR5K_BEACON_5211) | |
0bacdf30 | 1249 | #define AR5K_BEACON_PERIOD 0x0000ffff /* Mask for beacon period */ |
fa1c114f | 1250 | #define AR5K_BEACON_PERIOD_S 0 |
0bacdf30 | 1251 | #define AR5K_BEACON_TIM 0x007f0000 /* Mask for TIM offset */ |
fa1c114f | 1252 | #define AR5K_BEACON_TIM_S 16 |
0bacdf30 NK |
1253 | #define AR5K_BEACON_ENABLE 0x00800000 /* Enable beacons */ |
1254 | #define AR5K_BEACON_RESET_TSF 0x01000000 /* Force TSF reset */ | |
fa1c114f JS |
1255 | |
1256 | /* | |
1257 | * CFP period register | |
1258 | */ | |
1259 | #define AR5K_CFP_PERIOD_5210 0x8028 | |
1260 | #define AR5K_CFP_PERIOD_5211 0x8024 | |
1261 | #define AR5K_CFP_PERIOD (ah->ah_version == AR5K_AR5210 ? \ | |
1262 | AR5K_CFP_PERIOD_5210 : AR5K_CFP_PERIOD_5211) | |
1263 | ||
1264 | /* | |
1265 | * Next beacon time register | |
1266 | */ | |
1267 | #define AR5K_TIMER0_5210 0x802c | |
1268 | #define AR5K_TIMER0_5211 0x8028 | |
1269 | #define AR5K_TIMER0 (ah->ah_version == AR5K_AR5210 ? \ | |
1270 | AR5K_TIMER0_5210 : AR5K_TIMER0_5211) | |
1271 | ||
1272 | /* | |
1273 | * Next DMA beacon alert register | |
1274 | */ | |
1275 | #define AR5K_TIMER1_5210 0x8030 | |
1276 | #define AR5K_TIMER1_5211 0x802c | |
1277 | #define AR5K_TIMER1 (ah->ah_version == AR5K_AR5210 ? \ | |
1278 | AR5K_TIMER1_5210 : AR5K_TIMER1_5211) | |
1279 | ||
1280 | /* | |
1281 | * Next software beacon alert register | |
1282 | */ | |
1283 | #define AR5K_TIMER2_5210 0x8034 | |
1284 | #define AR5K_TIMER2_5211 0x8030 | |
1285 | #define AR5K_TIMER2 (ah->ah_version == AR5K_AR5210 ? \ | |
1286 | AR5K_TIMER2_5210 : AR5K_TIMER2_5211) | |
1287 | ||
1288 | /* | |
1289 | * Next ATIM window time register | |
1290 | */ | |
1291 | #define AR5K_TIMER3_5210 0x8038 | |
1292 | #define AR5K_TIMER3_5211 0x8034 | |
1293 | #define AR5K_TIMER3 (ah->ah_version == AR5K_AR5210 ? \ | |
1294 | AR5K_TIMER3_5210 : AR5K_TIMER3_5211) | |
1295 | ||
1296 | ||
1297 | /* | |
1298 | * 5210 First inter frame spacing register (IFS) | |
1299 | */ | |
1300 | #define AR5K_IFS0 0x8040 | |
1301 | #define AR5K_IFS0_SIFS 0x000007ff | |
1302 | #define AR5K_IFS0_SIFS_S 0 | |
1303 | #define AR5K_IFS0_DIFS 0x007ff800 | |
1304 | #define AR5K_IFS0_DIFS_S 11 | |
1305 | ||
1306 | /* | |
1307 | * 5210 Second inter frame spacing register (IFS) | |
1308 | */ | |
1309 | #define AR5K_IFS1 0x8044 | |
1310 | #define AR5K_IFS1_PIFS 0x00000fff | |
1311 | #define AR5K_IFS1_PIFS_S 0 | |
1312 | #define AR5K_IFS1_EIFS 0x03fff000 | |
1313 | #define AR5K_IFS1_EIFS_S 12 | |
1314 | #define AR5K_IFS1_CS_EN 0x04000000 | |
1315 | ||
1316 | ||
1317 | /* | |
1318 | * CFP duration register | |
1319 | */ | |
1320 | #define AR5K_CFP_DUR_5210 0x8048 | |
1321 | #define AR5K_CFP_DUR_5211 0x8038 | |
1322 | #define AR5K_CFP_DUR (ah->ah_version == AR5K_AR5210 ? \ | |
1323 | AR5K_CFP_DUR_5210 : AR5K_CFP_DUR_5211) | |
1324 | ||
1325 | /* | |
1326 | * Receive filter register | |
fa1c114f JS |
1327 | */ |
1328 | #define AR5K_RX_FILTER_5210 0x804c /* Register Address [5210] */ | |
1329 | #define AR5K_RX_FILTER_5211 0x803c /* Register Address [5211+] */ | |
1330 | #define AR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \ | |
1331 | AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211) | |
1332 | #define AR5K_RX_FILTER_UCAST 0x00000001 /* Don't filter unicast frames */ | |
1333 | #define AR5K_RX_FILTER_MCAST 0x00000002 /* Don't filter multicast frames */ | |
1334 | #define AR5K_RX_FILTER_BCAST 0x00000004 /* Don't filter broadcast frames */ | |
1335 | #define AR5K_RX_FILTER_CONTROL 0x00000008 /* Don't filter control frames */ | |
1336 | #define AR5K_RX_FILTER_BEACON 0x00000010 /* Don't filter beacon frames */ | |
1337 | #define AR5K_RX_FILTER_PROM 0x00000020 /* Set promiscuous mode */ | |
1338 | #define AR5K_RX_FILTER_XRPOLL 0x00000040 /* Don't filter XR poll frame [5212+] */ | |
1339 | #define AR5K_RX_FILTER_PROBEREQ 0x00000080 /* Don't filter probe requests [5212+] */ | |
1340 | #define AR5K_RX_FILTER_PHYERR_5212 0x00000100 /* Don't filter phy errors [5212+] */ | |
1341 | #define AR5K_RX_FILTER_RADARERR_5212 0x00000200 /* Don't filter phy radar errors [5212+] */ | |
1342 | #define AR5K_RX_FILTER_PHYERR_5211 0x00000040 /* [5211] */ | |
1343 | #define AR5K_RX_FILTER_RADARERR_5211 0x00000080 /* [5211] */ | |
1344 | #define AR5K_RX_FILTER_PHYERR \ | |
1345 | ((ah->ah_version == AR5K_AR5211 ? \ | |
1346 | AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212)) | |
1347 | #define AR5K_RX_FILTER_RADARERR \ | |
1348 | ((ah->ah_version == AR5K_AR5211 ? \ | |
1349 | AR5K_RX_FILTER_RADARERR_5211 : AR5K_RX_FILTER_RADARERR_5212)) | |
1350 | ||
1351 | /* | |
1352 | * Multicast filter register (lower 32 bits) | |
1353 | */ | |
1354 | #define AR5K_MCAST_FILTER0_5210 0x8050 | |
1355 | #define AR5K_MCAST_FILTER0_5211 0x8040 | |
1356 | #define AR5K_MCAST_FILTER0 (ah->ah_version == AR5K_AR5210 ? \ | |
1357 | AR5K_MCAST_FILTER0_5210 : AR5K_MCAST_FILTER0_5211) | |
1358 | ||
1359 | /* | |
1360 | * Multicast filter register (higher 16 bits) | |
1361 | */ | |
1362 | #define AR5K_MCAST_FILTER1_5210 0x8054 | |
1363 | #define AR5K_MCAST_FILTER1_5211 0x8044 | |
1364 | #define AR5K_MCAST_FILTER1 (ah->ah_version == AR5K_AR5210 ? \ | |
1365 | AR5K_MCAST_FILTER1_5210 : AR5K_MCAST_FILTER1_5211) | |
1366 | ||
1367 | ||
1368 | /* | |
1369 | * Transmit mask register (lower 32 bits) [5210] | |
1370 | */ | |
1371 | #define AR5K_TX_MASK0 0x8058 | |
1372 | ||
1373 | /* | |
1374 | * Transmit mask register (higher 16 bits) [5210] | |
1375 | */ | |
1376 | #define AR5K_TX_MASK1 0x805c | |
1377 | ||
1378 | /* | |
1379 | * Clear transmit mask [5210] | |
1380 | */ | |
1381 | #define AR5K_CLR_TMASK 0x8060 | |
1382 | ||
1383 | /* | |
1384 | * Trigger level register (before transmission) [5210] | |
1385 | */ | |
1386 | #define AR5K_TRIG_LVL 0x8064 | |
1387 | ||
1388 | ||
1389 | /* | |
1390 | * PCU control register | |
1391 | * | |
1392 | * Only DIS_RX is used in the code, the rest i guess are | |
1393 | * for tweaking/diagnostics. | |
1394 | */ | |
1395 | #define AR5K_DIAG_SW_5210 0x8068 /* Register Address [5210] */ | |
1396 | #define AR5K_DIAG_SW_5211 0x8048 /* Register Address [5211+] */ | |
1397 | #define AR5K_DIAG_SW (ah->ah_version == AR5K_AR5210 ? \ | |
1398 | AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211) | |
0bacdf30 NK |
1399 | #define AR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 /* Disable ACKs if WEP key is invalid */ |
1400 | #define AR5K_DIAG_SW_DIS_ACK 0x00000002 /* Disable ACKs */ | |
1401 | #define AR5K_DIAG_SW_DIS_CTS 0x00000004 /* Disable CTSs */ | |
1402 | #define AR5K_DIAG_SW_DIS_ENC 0x00000008 /* Disable encryption */ | |
1403 | #define AR5K_DIAG_SW_DIS_DEC 0x00000010 /* Disable decryption */ | |
fa1c114f JS |
1404 | #define AR5K_DIAG_SW_DIS_TX 0x00000020 /* Disable transmit [5210] */ |
1405 | #define AR5K_DIAG_SW_DIS_RX_5210 0x00000040 /* Disable recieve */ | |
1406 | #define AR5K_DIAG_SW_DIS_RX_5211 0x00000020 | |
1407 | #define AR5K_DIAG_SW_DIS_RX (ah->ah_version == AR5K_AR5210 ? \ | |
1408 | AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211) | |
1409 | #define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 /* Loopback (i guess it goes with DIS_TX) [5210] */ | |
1410 | #define AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040 | |
1411 | #define AR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \ | |
1412 | AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211) | |
1bef016a | 1413 | #define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 /* Corrupted FCS */ |
fa1c114f JS |
1414 | #define AR5K_DIAG_SW_CORR_FCS_5211 0x00000080 |
1415 | #define AR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \ | |
1416 | AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211) | |
1bef016a | 1417 | #define AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 /* Dump channel info */ |
fa1c114f JS |
1418 | #define AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100 |
1419 | #define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \ | |
1420 | AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211) | |
1bef016a NK |
1421 | #define AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 /* Enable fixed scrambler seed */ |
1422 | #define AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200 | |
fa1c114f JS |
1423 | #define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \ |
1424 | AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211) | |
1425 | #define AR5K_DIAG_SW_ECO_ENABLE 0x00000400 /* [5211+] */ | |
1426 | #define AR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 /* [5210] */ | |
0bacdf30 | 1427 | #define AR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 /* Scrambler seed mask */ |
fa1c114f JS |
1428 | #define AR5K_DIAG_SW_SCRAM_SEED_S 10 |
1429 | #define AR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 /* Disable seqnum increment (?)[5210] */ | |
1430 | #define AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 | |
1bef016a | 1431 | #define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 /* Accept frames of non-zero protocol number */ |
fa1c114f JS |
1432 | #define AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \ |
1433 | AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211) | |
1bef016a | 1434 | #define AR5K_DIAG_SW_OBSPT_M 0x000c0000 /* Observation point select (?) */ |
fa1c114f | 1435 | #define AR5K_DIAG_SW_OBSPT_S 18 |
1bef016a NK |
1436 | #define AR5K_DIAG_SW_RX_CLEAR_HIGH 0x0010000 /* Force RX Clear high */ |
1437 | #define AR5K_DIAG_SW_IGNORE_CARR_SENSE 0x0020000 /* Ignore virtual carrier sense */ | |
509a106e | 1438 | #define AR5K_DIAG_SW_CHANEL_IDLE_HIGH 0x0040000 /* Force channel idle high */ |
1bef016a | 1439 | #define AR5K_DIAG_SW_PHEAR_ME 0x0080000 /* ??? */ |
fa1c114f JS |
1440 | |
1441 | /* | |
1442 | * TSF (clock) register (lower 32 bits) | |
1443 | */ | |
1444 | #define AR5K_TSF_L32_5210 0x806c | |
1445 | #define AR5K_TSF_L32_5211 0x804c | |
1446 | #define AR5K_TSF_L32 (ah->ah_version == AR5K_AR5210 ? \ | |
1447 | AR5K_TSF_L32_5210 : AR5K_TSF_L32_5211) | |
1448 | ||
1449 | /* | |
1450 | * TSF (clock) register (higher 32 bits) | |
1451 | */ | |
1452 | #define AR5K_TSF_U32_5210 0x8070 | |
1453 | #define AR5K_TSF_U32_5211 0x8050 | |
1454 | #define AR5K_TSF_U32 (ah->ah_version == AR5K_AR5210 ? \ | |
1455 | AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211) | |
1456 | ||
1457 | /* | |
a406c139 | 1458 | * Last beacon timestamp register (Read Only) |
fa1c114f JS |
1459 | */ |
1460 | #define AR5K_LAST_TSTP 0x8080 | |
1461 | ||
1462 | /* | |
1463 | * ADDAC test register [5211+] | |
1464 | */ | |
0bacdf30 NK |
1465 | #define AR5K_ADDAC_TEST 0x8054 /* Register Address */ |
1466 | #define AR5K_ADDAC_TEST_TXCONT 0x00000001 /* Test continuous tx */ | |
1467 | #define AR5K_ADDAC_TEST_TST_MODE 0x00000002 /* Test mode */ | |
1468 | #define AR5K_ADDAC_TEST_LOOP_EN 0x00000004 /* Enable loop */ | |
1469 | #define AR5K_ADDAC_TEST_LOOP_LEN 0x00000008 /* Loop length (field) */ | |
1470 | #define AR5K_ADDAC_TEST_USE_U8 0x00004000 /* Use upper 8 bits */ | |
1471 | #define AR5K_ADDAC_TEST_MSB 0x00008000 /* State of MSB */ | |
1472 | #define AR5K_ADDAC_TEST_TRIG_SEL 0x00010000 /* Trigger select */ | |
1473 | #define AR5K_ADDAC_TEST_TRIG_PTY 0x00020000 /* Trigger polarity */ | |
1474 | #define AR5K_ADDAC_TEST_RXCONT 0x00040000 /* Continuous capture */ | |
1475 | #define AR5K_ADDAC_TEST_CAPTURE 0x00080000 /* Begin capture */ | |
e8f055f0 | 1476 | #define AR5K_ADDAC_TEST_TST_ARM 0x00100000 /* ARM rx buffer for capture */ |
fa1c114f JS |
1477 | |
1478 | /* | |
1479 | * Default antenna register [5211+] | |
1480 | */ | |
1481 | #define AR5K_DEFAULT_ANTENNA 0x8058 | |
1482 | ||
0bacdf30 NK |
1483 | /* |
1484 | * Frame control QoS mask register (?) [5211+] | |
1485 | * (FC_QOS_MASK) | |
1486 | */ | |
1487 | #define AR5K_FRAME_CTL_QOSM 0x805c | |
fa1c114f | 1488 | |
0bacdf30 NK |
1489 | /* |
1490 | * Seq mask register (?) [5211+] | |
1491 | */ | |
1492 | #define AR5K_SEQ_MASK 0x8060 | |
fa1c114f JS |
1493 | |
1494 | /* | |
1495 | * Retry count register [5210] | |
1496 | */ | |
1497 | #define AR5K_RETRY_CNT 0x8084 /* Register Address [5210] */ | |
1498 | #define AR5K_RETRY_CNT_SSH 0x0000003f /* Station short retry count (?) */ | |
1499 | #define AR5K_RETRY_CNT_SLG 0x00000fc0 /* Station long retry count (?) */ | |
1500 | ||
1501 | /* | |
1502 | * Back-off status register [5210] | |
1503 | */ | |
1504 | #define AR5K_BACKOFF 0x8088 /* Register Address [5210] */ | |
1505 | #define AR5K_BACKOFF_CW 0x000003ff /* Backoff Contention Window (?) */ | |
1506 | #define AR5K_BACKOFF_CNT 0x03ff0000 /* Backoff count (?) */ | |
1507 | ||
1508 | ||
1509 | ||
1510 | /* | |
1511 | * NAV register (current) | |
1512 | */ | |
1513 | #define AR5K_NAV_5210 0x808c | |
1514 | #define AR5K_NAV_5211 0x8084 | |
1515 | #define AR5K_NAV (ah->ah_version == AR5K_AR5210 ? \ | |
1516 | AR5K_NAV_5210 : AR5K_NAV_5211) | |
1517 | ||
1518 | /* | |
1519 | * RTS success register | |
1520 | */ | |
1521 | #define AR5K_RTS_OK_5210 0x8090 | |
1522 | #define AR5K_RTS_OK_5211 0x8088 | |
1523 | #define AR5K_RTS_OK (ah->ah_version == AR5K_AR5210 ? \ | |
1524 | AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211) | |
1525 | ||
1526 | /* | |
1527 | * RTS failure register | |
1528 | */ | |
1529 | #define AR5K_RTS_FAIL_5210 0x8094 | |
1530 | #define AR5K_RTS_FAIL_5211 0x808c | |
1531 | #define AR5K_RTS_FAIL (ah->ah_version == AR5K_AR5210 ? \ | |
1532 | AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211) | |
1533 | ||
1534 | /* | |
1535 | * ACK failure register | |
1536 | */ | |
1537 | #define AR5K_ACK_FAIL_5210 0x8098 | |
1538 | #define AR5K_ACK_FAIL_5211 0x8090 | |
1539 | #define AR5K_ACK_FAIL (ah->ah_version == AR5K_AR5210 ? \ | |
1540 | AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211) | |
1541 | ||
1542 | /* | |
1543 | * FCS failure register | |
1544 | */ | |
1545 | #define AR5K_FCS_FAIL_5210 0x809c | |
1546 | #define AR5K_FCS_FAIL_5211 0x8094 | |
1547 | #define AR5K_FCS_FAIL (ah->ah_version == AR5K_AR5210 ? \ | |
1548 | AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211) | |
1549 | ||
1550 | /* | |
1551 | * Beacon count register | |
1552 | */ | |
1553 | #define AR5K_BEACON_CNT_5210 0x80a0 | |
1554 | #define AR5K_BEACON_CNT_5211 0x8098 | |
1555 | #define AR5K_BEACON_CNT (ah->ah_version == AR5K_AR5210 ? \ | |
1556 | AR5K_BEACON_CNT_5210 : AR5K_BEACON_CNT_5211) | |
1557 | ||
1558 | ||
1559 | /*===5212 Specific PCU registers===*/ | |
1560 | ||
8f655dde NK |
1561 | /* |
1562 | * Transmit power control register | |
1563 | */ | |
1564 | #define AR5K_TPC 0x80e8 | |
1565 | #define AR5K_TPC_ACK 0x0000003f /* ack frames */ | |
1566 | #define AR5K_TPC_ACK_S 0 | |
1567 | #define AR5K_TPC_CTS 0x00003f00 /* cts frames */ | |
1568 | #define AR5K_TPC_CTS_S 8 | |
1569 | #define AR5K_TPC_CHIRP 0x003f0000 /* chirp frames */ | |
1570 | #define AR5K_TPC_CHIRP_S 16 | |
1571 | #define AR5K_TPC_DOPPLER 0x0f000000 /* doppler chirp span */ | |
1572 | #define AR5K_TPC_DOPPLER_S 24 | |
1573 | ||
fa1c114f JS |
1574 | /* |
1575 | * XR (eXtended Range) mode register | |
1576 | */ | |
0bacdf30 NK |
1577 | #define AR5K_XRMODE 0x80c0 /* Register Address */ |
1578 | #define AR5K_XRMODE_POLL_TYPE_M 0x0000003f /* Mask for Poll type (?) */ | |
fa1c114f | 1579 | #define AR5K_XRMODE_POLL_TYPE_S 0 |
0bacdf30 | 1580 | #define AR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c /* Mask for Poll subtype (?) */ |
fa1c114f | 1581 | #define AR5K_XRMODE_POLL_SUBTYPE_S 2 |
0bacdf30 NK |
1582 | #define AR5K_XRMODE_POLL_WAIT_ALL 0x00000080 /* Wait for poll */ |
1583 | #define AR5K_XRMODE_SIFS_DELAY 0x000fff00 /* Mask for SIFS delay */ | |
1584 | #define AR5K_XRMODE_FRAME_HOLD_M 0xfff00000 /* Mask for frame hold (?) */ | |
fa1c114f JS |
1585 | #define AR5K_XRMODE_FRAME_HOLD_S 20 |
1586 | ||
1587 | /* | |
1588 | * XR delay register | |
1589 | */ | |
0bacdf30 NK |
1590 | #define AR5K_XRDELAY 0x80c4 /* Register Address */ |
1591 | #define AR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff /* Mask for slot delay */ | |
fa1c114f | 1592 | #define AR5K_XRDELAY_SLOT_DELAY_S 0 |
0bacdf30 | 1593 | #define AR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000 /* Mask for CHIRP data delay */ |
fa1c114f JS |
1594 | #define AR5K_XRDELAY_CHIRP_DELAY_S 16 |
1595 | ||
1596 | /* | |
1597 | * XR timeout register | |
1598 | */ | |
0bacdf30 NK |
1599 | #define AR5K_XRTIMEOUT 0x80c8 /* Register Address */ |
1600 | #define AR5K_XRTIMEOUT_CHIRP_M 0x0000ffff /* Mask for CHIRP timeout */ | |
fa1c114f | 1601 | #define AR5K_XRTIMEOUT_CHIRP_S 0 |
0bacdf30 | 1602 | #define AR5K_XRTIMEOUT_POLL_M 0xffff0000 /* Mask for Poll timeout */ |
fa1c114f JS |
1603 | #define AR5K_XRTIMEOUT_POLL_S 16 |
1604 | ||
1605 | /* | |
1606 | * XR chirp register | |
1607 | */ | |
0bacdf30 NK |
1608 | #define AR5K_XRCHIRP 0x80cc /* Register Address */ |
1609 | #define AR5K_XRCHIRP_SEND 0x00000001 /* Send CHIRP */ | |
1610 | #define AR5K_XRCHIRP_GAP 0xffff0000 /* Mask for CHIRP gap (?) */ | |
fa1c114f JS |
1611 | |
1612 | /* | |
1613 | * XR stomp register | |
1614 | */ | |
0bacdf30 NK |
1615 | #define AR5K_XRSTOMP 0x80d0 /* Register Address */ |
1616 | #define AR5K_XRSTOMP_TX 0x00000001 /* Stomp Tx (?) */ | |
1617 | #define AR5K_XRSTOMP_RX 0x00000002 /* Stomp Rx (?) */ | |
1618 | #define AR5K_XRSTOMP_TX_RSSI 0x00000004 /* Stomp Tx RSSI (?) */ | |
1619 | #define AR5K_XRSTOMP_TX_BSSID 0x00000008 /* Stomp Tx BSSID (?) */ | |
1620 | #define AR5K_XRSTOMP_DATA 0x00000010 /* Stomp data (?)*/ | |
1621 | #define AR5K_XRSTOMP_RSSI_THRES 0x0000ff00 /* Mask for XR RSSI threshold */ | |
fa1c114f JS |
1622 | |
1623 | /* | |
1624 | * First enhanced sleep register | |
1625 | */ | |
0bacdf30 NK |
1626 | #define AR5K_SLEEP0 0x80d4 /* Register Address */ |
1627 | #define AR5K_SLEEP0_NEXT_DTIM 0x0007ffff /* Mask for next DTIM (?) */ | |
fa1c114f | 1628 | #define AR5K_SLEEP0_NEXT_DTIM_S 0 |
0bacdf30 NK |
1629 | #define AR5K_SLEEP0_ASSUME_DTIM 0x00080000 /* Assume DTIM */ |
1630 | #define AR5K_SLEEP0_ENH_SLEEP_EN 0x00100000 /* Enable enchanced sleep control */ | |
1631 | #define AR5K_SLEEP0_CABTO 0xff000000 /* Mask for CAB Time Out */ | |
fa1c114f JS |
1632 | #define AR5K_SLEEP0_CABTO_S 24 |
1633 | ||
1634 | /* | |
1635 | * Second enhanced sleep register | |
1636 | */ | |
0bacdf30 NK |
1637 | #define AR5K_SLEEP1 0x80d8 /* Register Address */ |
1638 | #define AR5K_SLEEP1_NEXT_TIM 0x0007ffff /* Mask for next TIM (?) */ | |
fa1c114f | 1639 | #define AR5K_SLEEP1_NEXT_TIM_S 0 |
0bacdf30 | 1640 | #define AR5K_SLEEP1_BEACON_TO 0xff000000 /* Mask for Beacon Time Out */ |
fa1c114f JS |
1641 | #define AR5K_SLEEP1_BEACON_TO_S 24 |
1642 | ||
1643 | /* | |
1644 | * Third enhanced sleep register | |
1645 | */ | |
0bacdf30 NK |
1646 | #define AR5K_SLEEP2 0x80dc /* Register Address */ |
1647 | #define AR5K_SLEEP2_TIM_PER 0x0000ffff /* Mask for TIM period (?) */ | |
fa1c114f | 1648 | #define AR5K_SLEEP2_TIM_PER_S 0 |
0bacdf30 | 1649 | #define AR5K_SLEEP2_DTIM_PER 0xffff0000 /* Mask for DTIM period (?) */ |
fa1c114f JS |
1650 | #define AR5K_SLEEP2_DTIM_PER_S 16 |
1651 | ||
1652 | /* | |
1653 | * BSSID mask registers | |
1654 | */ | |
0bacdf30 NK |
1655 | #define AR5K_BSS_IDM0 0x80e0 /* Upper bits */ |
1656 | #define AR5K_BSS_IDM1 0x80e4 /* Lower bits */ | |
fa1c114f JS |
1657 | |
1658 | /* | |
1659 | * TX power control (TPC) register | |
0bacdf30 NK |
1660 | * |
1661 | * XXX: PCDAC steps (0.5dbm) or DBM ? | |
1662 | * | |
fa1c114f | 1663 | */ |
0bacdf30 | 1664 | #define AR5K_TXPC 0x80e8 /* Register Address */ |
1bef016a | 1665 | #define AR5K_TXPC_ACK_M 0x0000003f /* ACK tx power */ |
fa1c114f | 1666 | #define AR5K_TXPC_ACK_S 0 |
1bef016a | 1667 | #define AR5K_TXPC_CTS_M 0x00003f00 /* CTS tx power */ |
fa1c114f | 1668 | #define AR5K_TXPC_CTS_S 8 |
1bef016a NK |
1669 | #define AR5K_TXPC_CHIRP_M 0x003f0000 /* CHIRP tx power */ |
1670 | #define AR5K_TXPC_CHIRP_S 16 | |
1671 | #define AR5K_TXPC_DOPPLER 0x0f000000 /* Doppler chirp span (?) */ | |
1672 | #define AR5K_TXPC_DOPPLER_S 24 | |
fa1c114f JS |
1673 | |
1674 | /* | |
1675 | * Profile count registers | |
1676 | */ | |
0bacdf30 NK |
1677 | #define AR5K_PROFCNT_TX 0x80ec /* Tx count */ |
1678 | #define AR5K_PROFCNT_RX 0x80f0 /* Rx count */ | |
1679 | #define AR5K_PROFCNT_RXCLR 0x80f4 /* Clear Rx count */ | |
1680 | #define AR5K_PROFCNT_CYCLE 0x80f8 /* Cycle count (?) */ | |
1681 | ||
1682 | /* | |
1bef016a | 1683 | * Quiet period control registers |
0bacdf30 NK |
1684 | */ |
1685 | #define AR5K_QUIET_CTL1 0x80fc /* Register Address */ | |
1bef016a | 1686 | #define AR5K_QUIET_CTL1_NEXT_QT_TSF 0x0000ffff /* Next quiet period TSF (TU) */ |
509a106e | 1687 | #define AR5K_QUIET_CTL1_NEXT_QT_TSF_S 0 |
1bef016a NK |
1688 | #define AR5K_QUIET_CTL1_QT_EN 0x00010000 /* Enable quiet period */ |
1689 | #define AR5K_QUIET_CTL1_ACK_CTS_EN 0x00020000 /* Send ACK/CTS during quiet period */ | |
1690 | ||
0bacdf30 | 1691 | #define AR5K_QUIET_CTL2 0x8100 /* Register Address */ |
1bef016a NK |
1692 | #define AR5K_QUIET_CTL2_QT_PER 0x0000ffff /* Mask for quiet period periodicity */ |
1693 | #define AR5K_QUIET_CTL2_QT_PER_S 0 | |
1694 | #define AR5K_QUIET_CTL2_QT_DUR 0xffff0000 /* Mask for quiet period duration */ | |
1695 | #define AR5K_QUIET_CTL2_QT_DUR_S 16 | |
fa1c114f JS |
1696 | |
1697 | /* | |
1698 | * TSF parameter register | |
1699 | */ | |
0bacdf30 | 1700 | #define AR5K_TSF_PARM 0x8104 /* Register Address */ |
e8f055f0 | 1701 | #define AR5K_TSF_PARM_INC 0x000000ff /* Mask for TSF increment */ |
fa1c114f JS |
1702 | #define AR5K_TSF_PARM_INC_S 0 |
1703 | ||
0bacdf30 | 1704 | /* |
1bef016a | 1705 | * QoS NOACK policy |
0bacdf30 | 1706 | */ |
1bef016a NK |
1707 | #define AR5K_QOS_NOACK 0x8108 /* Register Address */ |
1708 | #define AR5K_QOS_NOACK_2BIT_VALUES 0x0000000f /* ??? */ | |
1709 | #define AR5K_QOS_NOACK_2BIT_VALUES_S 0 | |
1710 | #define AR5K_QOS_NOACK_BIT_OFFSET 0x00000070 /* ??? */ | |
1711 | #define AR5K_QOS_NOACK_BIT_OFFSET_S 4 | |
1712 | #define AR5K_QOS_NOACK_BYTE_OFFSET 0x00000180 /* ??? */ | |
e8f055f0 | 1713 | #define AR5K_QOS_NOACK_BYTE_OFFSET_S 7 |
0bacdf30 | 1714 | |
fa1c114f JS |
1715 | /* |
1716 | * PHY error filter register | |
1717 | */ | |
1718 | #define AR5K_PHY_ERR_FIL 0x810c | |
0bacdf30 NK |
1719 | #define AR5K_PHY_ERR_FIL_RADAR 0x00000020 /* Radar signal */ |
1720 | #define AR5K_PHY_ERR_FIL_OFDM 0x00020000 /* OFDM false detect (ANI) */ | |
1721 | #define AR5K_PHY_ERR_FIL_CCK 0x02000000 /* CCK false detect (ANI) */ | |
1722 | ||
1723 | /* | |
1724 | * XR latency register | |
1725 | */ | |
1726 | #define AR5K_XRLAT_TX 0x8110 | |
fa1c114f JS |
1727 | |
1728 | /* | |
0bacdf30 NK |
1729 | * ACK SIFS register |
1730 | */ | |
1731 | #define AR5K_ACKSIFS 0x8114 /* Register Address */ | |
1732 | #define AR5K_ACKSIFS_INC 0x00000000 /* ACK SIFS Increment (field) */ | |
1733 | ||
1734 | /* | |
1735 | * MIC QoS control register (?) | |
1736 | */ | |
1bef016a NK |
1737 | #define AR5K_MIC_QOS_CTL 0x8118 /* Register Address */ |
1738 | #define AR5K_MIC_QOS_CTL_OFF(_n) (1 << (_n * 2)) | |
1739 | #define AR5K_MIC_QOS_CTL_MQ_EN 0x00010000 /* Enable MIC QoS */ | |
0bacdf30 NK |
1740 | |
1741 | /* | |
1742 | * MIC QoS select register (?) | |
1743 | */ | |
1bef016a NK |
1744 | #define AR5K_MIC_QOS_SEL 0x811c |
1745 | #define AR5K_MIC_QOS_SEL_OFF(_n) (1 << (_n * 4)) | |
0bacdf30 NK |
1746 | |
1747 | /* | |
1748 | * Misc mode control register (?) | |
1749 | */ | |
1750 | #define AR5K_MISC_MODE 0x8120 /* Register Address */ | |
1751 | #define AR5K_MISC_MODE_FBSSID_MATCH 0x00000001 /* Force BSSID match */ | |
1752 | #define AR5K_MISC_MODE_ACKSIFS_MEM 0x00000002 /* ACK SIFS memory (?) */ | |
f650470a | 1753 | #define AR5K_MISC_MODE_COMBINED_MIC 0x00000004 /* use rx/tx MIC key */ |
0bacdf30 NK |
1754 | /* more bits */ |
1755 | ||
1756 | /* | |
1757 | * OFDM Filter counter | |
1758 | */ | |
1759 | #define AR5K_OFDM_FIL_CNT 0x8124 | |
1760 | ||
1761 | /* | |
1762 | * CCK Filter counter | |
1763 | */ | |
1764 | #define AR5K_CCK_FIL_CNT 0x8128 | |
1765 | ||
1766 | /* | |
1767 | * PHY Error Counters (?) | |
1768 | */ | |
1769 | #define AR5K_PHYERR_CNT1 0x812c | |
1770 | #define AR5K_PHYERR_CNT1_MASK 0x8130 | |
1771 | ||
1772 | #define AR5K_PHYERR_CNT2 0x8134 | |
1773 | #define AR5K_PHYERR_CNT2_MASK 0x8138 | |
1774 | ||
1775 | /* | |
1776 | * TSF Threshold register (?) | |
1777 | */ | |
1778 | #define AR5K_TSF_THRES 0x813c | |
1779 | ||
1bef016a NK |
1780 | /* |
1781 | * TODO: Wake On Wireless registers | |
1782 | * Range: 0x8147 - 0x818c | |
1783 | */ | |
1784 | ||
0bacdf30 NK |
1785 | /* |
1786 | * Rate -> ACK SIFS mapping table (32 entries) | |
1787 | */ | |
1788 | #define AR5K_RATE_ACKSIFS_BASE 0x8680 /* Register Address */ | |
1789 | #define AR5K_RATE_ACKSIFS(_n) (AR5K_RATE_ACKSIFS_BSE + ((_n) << 2)) | |
1790 | #define AR5K_RATE_ACKSIFS_NORMAL 0x00000001 /* Normal SIFS (field) */ | |
1791 | #define AR5K_RATE_ACKSIFS_TURBO 0x00000400 /* Turbo SIFS (field) */ | |
1792 | ||
1793 | /* | |
1794 | * Rate -> duration mapping table (32 entries) | |
fa1c114f JS |
1795 | */ |
1796 | #define AR5K_RATE_DUR_BASE 0x8700 | |
1797 | #define AR5K_RATE_DUR(_n) (AR5K_RATE_DUR_BASE + ((_n) << 2)) | |
1798 | ||
0bacdf30 NK |
1799 | /* |
1800 | * Rate -> db mapping table | |
1801 | * (8 entries, each one has 4 8bit fields) | |
1802 | */ | |
1803 | #define AR5K_RATE2DB_BASE 0x87c0 | |
1804 | #define AR5K_RATE2DB(_n) (AR5K_RATE2DB_BASE + ((_n) << 2)) | |
1805 | ||
1806 | /* | |
1807 | * db -> Rate mapping table | |
1808 | * (8 entries, each one has 4 8bit fields) | |
1809 | */ | |
1810 | #define AR5K_DB2RATE_BASE 0x87e0 | |
1811 | #define AR5K_DB2RATE(_n) (AR5K_DB2RATE_BASE + ((_n) << 2)) | |
1812 | ||
fa1c114f JS |
1813 | /*===5212 end===*/ |
1814 | ||
1815 | /* | |
1816 | * Key table (WEP) register | |
1817 | */ | |
1818 | #define AR5K_KEYTABLE_0_5210 0x9000 | |
1819 | #define AR5K_KEYTABLE_0_5211 0x8800 | |
1820 | #define AR5K_KEYTABLE_5210(_n) (AR5K_KEYTABLE_0_5210 + ((_n) << 5)) | |
1821 | #define AR5K_KEYTABLE_5211(_n) (AR5K_KEYTABLE_0_5211 + ((_n) << 5)) | |
1822 | #define AR5K_KEYTABLE(_n) (ah->ah_version == AR5K_AR5210 ? \ | |
1823 | AR5K_KEYTABLE_5210(_n) : AR5K_KEYTABLE_5211(_n)) | |
1824 | #define AR5K_KEYTABLE_OFF(_n, x) (AR5K_KEYTABLE(_n) + (x << 2)) | |
1825 | #define AR5K_KEYTABLE_TYPE(_n) AR5K_KEYTABLE_OFF(_n, 5) | |
1826 | #define AR5K_KEYTABLE_TYPE_40 0x00000000 | |
1827 | #define AR5K_KEYTABLE_TYPE_104 0x00000001 | |
1828 | #define AR5K_KEYTABLE_TYPE_128 0x00000003 | |
1829 | #define AR5K_KEYTABLE_TYPE_TKIP 0x00000004 /* [5212+] */ | |
1830 | #define AR5K_KEYTABLE_TYPE_AES 0x00000005 /* [5211+] */ | |
1831 | #define AR5K_KEYTABLE_TYPE_CCM 0x00000006 /* [5212+] */ | |
1832 | #define AR5K_KEYTABLE_TYPE_NULL 0x00000007 /* [5211+] */ | |
1833 | #define AR5K_KEYTABLE_ANTENNA 0x00000008 /* [5212+] */ | |
1834 | #define AR5K_KEYTABLE_MAC0(_n) AR5K_KEYTABLE_OFF(_n, 6) | |
1835 | #define AR5K_KEYTABLE_MAC1(_n) AR5K_KEYTABLE_OFF(_n, 7) | |
1836 | #define AR5K_KEYTABLE_VALID 0x00008000 | |
1837 | ||
f07a6c49 NK |
1838 | /* If key type is TKIP and MIC is enabled |
1839 | * MIC key goes in offset entry + 64 */ | |
1840 | #define AR5K_KEYTABLE_MIC_OFFSET 64 | |
1841 | ||
fa1c114f JS |
1842 | /* WEP 40-bit = 40-bit entered key + 24 bit IV = 64-bit |
1843 | * WEP 104-bit = 104-bit entered key + 24-bit IV = 128-bit | |
1844 | * WEP 128-bit = 128-bit entered key + 24 bit IV = 152-bit | |
1845 | * | |
1846 | * Some vendors have introduced bigger WEP keys to address | |
1847 | * security vulnerabilities in WEP. This includes: | |
1848 | * | |
1849 | * WEP 232-bit = 232-bit entered key + 24 bit IV = 256-bit | |
1850 | * | |
1851 | * We can expand this if we find ar5k Atheros cards with a larger | |
1852 | * key table size. | |
1853 | */ | |
1854 | #define AR5K_KEYTABLE_SIZE_5210 64 | |
1855 | #define AR5K_KEYTABLE_SIZE_5211 128 | |
1856 | #define AR5K_KEYTABLE_SIZE (ah->ah_version == AR5K_AR5210 ? \ | |
1857 | AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211) | |
1858 | ||
1859 | ||
1860 | /*===PHY REGISTERS===*/ | |
1861 | ||
1862 | /* | |
0bacdf30 | 1863 | * PHY registers start |
fa1c114f JS |
1864 | */ |
1865 | #define AR5K_PHY_BASE 0x9800 | |
1866 | #define AR5K_PHY(_n) (AR5K_PHY_BASE + ((_n) << 2)) | |
0bacdf30 NK |
1867 | |
1868 | /* | |
1869 | * TST_2 (Misc config parameters) | |
1870 | */ | |
1871 | #define AR5K_PHY_TST2 0x9800 /* Register Address */ | |
e8f055f0 NK |
1872 | #define AR5K_PHY_TST2_TRIG_SEL 0x00000007 /* Trigger select (?)*/ |
1873 | #define AR5K_PHY_TST2_TRIG 0x00000010 /* Trigger (?) */ | |
1874 | #define AR5K_PHY_TST2_CBUS_MODE 0x00000060 /* Cardbus mode (?) */ | |
0bacdf30 NK |
1875 | #define AR5K_PHY_TST2_CLK32 0x00000400 /* CLK_OUT is CLK32 (32Khz external) */ |
1876 | #define AR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800 /* Enable Chancor dump (?) */ | |
1877 | #define AR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000 /* Even Chancor dump (?) */ | |
1878 | #define AR5K_PHY_TST2_RFSILENT_EN 0x00002000 /* Enable RFSILENT */ | |
e8f055f0 | 1879 | #define AR5K_PHY_TST2_ALT_RFDATA 0x00004000 /* Alternate RFDATA (5-2GHz switch ?) */ |
0bacdf30 NK |
1880 | #define AR5K_PHY_TST2_MINI_OBS_EN 0x00008000 /* Enable mini OBS (?) */ |
1881 | #define AR5K_PHY_TST2_RX2_IS_RX5_INV 0x00010000 /* 2GHz rx path is the 5GHz path inverted (?) */ | |
1882 | #define AR5K_PHY_TST2_SLOW_CLK160 0x00020000 /* Slow CLK160 (?) */ | |
1883 | #define AR5K_PHY_TST2_AGC_OBS_SEL_3 0x00040000 /* AGC OBS Select 3 (?) */ | |
1884 | #define AR5K_PHY_TST2_BBB_OBS_SEL 0x00080000 /* BB OBS Select (field ?) */ | |
1885 | #define AR5K_PHY_TST2_ADC_OBS_SEL 0x00800000 /* ADC OBS Select (field ?) */ | |
1886 | #define AR5K_PHY_TST2_RX_CLR_SEL 0x08000000 /* RX Clear Select (?) */ | |
1887 | #define AR5K_PHY_TST2_FORCE_AGC_CLR 0x10000000 /* Force AGC clear (?) */ | |
1888 | #define AR5K_PHY_SHIFT_2GHZ 0x00004007 /* Used to access 2GHz radios */ | |
1889 | #define AR5K_PHY_SHIFT_5GHZ 0x00000007 /* Used to access 5GHz radios (default) */ | |
fa1c114f JS |
1890 | |
1891 | /* | |
1892 | * PHY frame control register [5110] /turbo mode register [5111+] | |
1893 | * | |
1894 | * There is another frame control register for [5111+] | |
1895 | * at address 0x9944 (see below) but the 2 first flags | |
1896 | * are common here between 5110 frame control register | |
1897 | * and [5111+] turbo mode register, so this also works as | |
1898 | * a "turbo mode register" for 5110. We treat this one as | |
1899 | * a frame control register for 5110 below. | |
1900 | */ | |
0bacdf30 NK |
1901 | #define AR5K_PHY_TURBO 0x9804 /* Register Address */ |
1902 | #define AR5K_PHY_TURBO_MODE 0x00000001 /* Enable turbo mode */ | |
1bef016a NK |
1903 | #define AR5K_PHY_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode */ |
1904 | #define AR5K_PHY_TURBO_MIMO 0x00000004 /* Set turbo for mimo mimo */ | |
fa1c114f JS |
1905 | |
1906 | /* | |
1907 | * PHY agility command register | |
0bacdf30 | 1908 | * (aka TST_1) |
fa1c114f | 1909 | */ |
0bacdf30 NK |
1910 | #define AR5K_PHY_AGC 0x9808 /* Register Address */ |
1911 | #define AR5K_PHY_TST1 0x9808 | |
1912 | #define AR5K_PHY_AGC_DISABLE 0x08000000 /* Disable AGC to A2 (?)*/ | |
1913 | #define AR5K_PHY_TST1_TXHOLD 0x00003800 /* Set tx hold (?) */ | |
1bef016a NK |
1914 | #define AR5K_PHY_TST1_TXSRC_SRC 0x00000002 /* Used with bit 7 (?) */ |
1915 | #define AR5K_PHY_TST1_TXSRC_SRC_S 1 | |
1916 | #define AR5K_PHY_TST1_TXSRC_ALT 0x00000080 /* Set input to tsdac (?) */ | |
1917 | #define AR5K_PHY_TST1_TXSRC_ALT_S 7 | |
1918 | ||
fa1c114f JS |
1919 | |
1920 | /* | |
0bacdf30 | 1921 | * PHY timing register 3 [5112+] |
fa1c114f JS |
1922 | */ |
1923 | #define AR5K_PHY_TIMING_3 0x9814 | |
1924 | #define AR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000 | |
1925 | #define AR5K_PHY_TIMING_3_DSC_MAN_S 17 | |
1926 | #define AR5K_PHY_TIMING_3_DSC_EXP 0x0001e000 | |
1927 | #define AR5K_PHY_TIMING_3_DSC_EXP_S 13 | |
1928 | ||
1929 | /* | |
1930 | * PHY chip revision register | |
1931 | */ | |
1932 | #define AR5K_PHY_CHIP_ID 0x9818 | |
1933 | ||
1934 | /* | |
1935 | * PHY activation register | |
1936 | */ | |
0bacdf30 NK |
1937 | #define AR5K_PHY_ACT 0x981c /* Register Address */ |
1938 | #define AR5K_PHY_ACT_ENABLE 0x00000001 /* Activate PHY */ | |
1939 | #define AR5K_PHY_ACT_DISABLE 0x00000002 /* Deactivate PHY */ | |
1940 | ||
1941 | /* | |
1942 | * PHY RF control registers | |
0bacdf30 NK |
1943 | */ |
1944 | #define AR5K_PHY_RF_CTL2 0x9824 /* Register Address */ | |
1bef016a NK |
1945 | #define AR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f /* TX frame to TX data start */ |
1946 | #define AR5K_PHY_RF_CTL2_TXF2TXD_START_S 0 | |
0bacdf30 NK |
1947 | |
1948 | #define AR5K_PHY_RF_CTL3 0x9828 /* Register Address */ | |
e8f055f0 NK |
1949 | #define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000ff00 /* TX end to XLNA on */ |
1950 | #define AR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 8 | |
1bef016a NK |
1951 | |
1952 | #define AR5K_PHY_ADC_CTL 0x982c | |
1953 | #define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF 0x00000003 | |
1954 | #define AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_S 0 | |
1955 | #define AR5K_PHY_ADC_CTL_PWD_DAC_OFF 0x00002000 | |
1956 | #define AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OFF 0x00004000 | |
1957 | #define AR5K_PHY_ADC_CTL_PWD_ADC_OFF 0x00008000 | |
1958 | #define AR5K_PHY_ADC_CTL_INBUFGAIN_ON 0x00030000 | |
1959 | #define AR5K_PHY_ADC_CTL_INBUFGAIN_ON_S 16 | |
0bacdf30 NK |
1960 | |
1961 | #define AR5K_PHY_RF_CTL4 0x9834 /* Register Address */ | |
1962 | #define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001 /* TX frame to XPA A on (field) */ | |
1963 | #define AR5K_PHY_RF_CTL4_TXF2XPA_B_ON 0x00000100 /* TX frame to XPA B on (field) */ | |
1964 | #define AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF 0x00010000 /* TX end to XPA A off (field) */ | |
1965 | #define AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF 0x01000000 /* TX end to XPA B off (field) */ | |
1966 | ||
1967 | /* | |
1968 | * Pre-Amplifier control register | |
1969 | * (XPA -> external pre-amplifier) | |
1970 | */ | |
1971 | #define AR5K_PHY_PA_CTL 0x9838 /* Register Address */ | |
1972 | #define AR5K_PHY_PA_CTL_XPA_A_HI 0x00000001 /* XPA A high (?) */ | |
1973 | #define AR5K_PHY_PA_CTL_XPA_B_HI 0x00000002 /* XPA B high (?) */ | |
1974 | #define AR5K_PHY_PA_CTL_XPA_A_EN 0x00000004 /* Enable XPA A */ | |
1975 | #define AR5K_PHY_PA_CTL_XPA_B_EN 0x00000008 /* Enable XPA B */ | |
1976 | ||
1977 | /* | |
1978 | * PHY settling register | |
1979 | */ | |
1980 | #define AR5K_PHY_SETTLING 0x9844 /* Register Address */ | |
1bef016a NK |
1981 | #define AR5K_PHY_SETTLING_AGC 0x0000007f /* AGC settling time */ |
1982 | #define AR5K_PHY_SETTLING_AGC_S 0 | |
1983 | #define AR5K_PHY_SETTLING_SWITCH 0x00003f80 /* Switch settlig time */ | |
e8f055f0 | 1984 | #define AR5K_PHY_SETTLING_SWITCH_S 7 |
0bacdf30 NK |
1985 | |
1986 | /* | |
1987 | * PHY Gain registers | |
1988 | */ | |
1989 | #define AR5K_PHY_GAIN 0x9848 /* Register Address */ | |
1bef016a NK |
1990 | #define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000 /* TX-RX Attenuation */ |
1991 | #define AR5K_PHY_GAIN_TXRX_ATTEN_S 12 | |
1992 | #define AR5K_PHY_GAIN_TXRX_RF_MAX 0x007c0000 | |
1993 | #define AR5K_PHY_GAIN_TXRX_RF_MAX_S 18 | |
0bacdf30 NK |
1994 | |
1995 | #define AR5K_PHY_GAIN_OFFSET 0x984c /* Register Address */ | |
1996 | #define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000 /* RX-TX flag (?) */ | |
1997 | ||
1998 | /* | |
c6e387a2 | 1999 | * Desired ADC/PGA size register |
0bacdf30 NK |
2000 | * (for more infos read ANI patent) |
2001 | */ | |
2002 | #define AR5K_PHY_DESIRED_SIZE 0x9850 /* Register Address */ | |
1bef016a NK |
2003 | #define AR5K_PHY_DESIRED_SIZE_ADC 0x000000ff /* ADC desired size */ |
2004 | #define AR5K_PHY_DESIRED_SIZE_ADC_S 0 | |
2005 | #define AR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00 /* PGA desired size */ | |
2006 | #define AR5K_PHY_DESIRED_SIZE_PGA_S 8 | |
2007 | #define AR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000 /* Total desired size */ | |
2008 | #define AR5K_PHY_DESIRED_SIZE_TOT_S 20 | |
fa1c114f JS |
2009 | |
2010 | /* | |
2011 | * PHY signal register | |
0bacdf30 | 2012 | * (for more infos read ANI patent) |
fa1c114f | 2013 | */ |
0bacdf30 | 2014 | #define AR5K_PHY_SIG 0x9858 /* Register Address */ |
1bef016a | 2015 | #define AR5K_PHY_SIG_FIRSTEP 0x0003f000 /* FIRSTEP */ |
fa1c114f | 2016 | #define AR5K_PHY_SIG_FIRSTEP_S 12 |
1bef016a | 2017 | #define AR5K_PHY_SIG_FIRPWR 0x03fc0000 /* FIPWR */ |
fa1c114f JS |
2018 | #define AR5K_PHY_SIG_FIRPWR_S 18 |
2019 | ||
2020 | /* | |
2021 | * PHY coarse agility control register | |
0bacdf30 | 2022 | * (for more infos read ANI patent) |
fa1c114f | 2023 | */ |
0bacdf30 | 2024 | #define AR5K_PHY_AGCCOARSE 0x985c /* Register Address */ |
1bef016a | 2025 | #define AR5K_PHY_AGCCOARSE_LO 0x00007f80 /* AGC Coarse low */ |
fa1c114f | 2026 | #define AR5K_PHY_AGCCOARSE_LO_S 7 |
1bef016a | 2027 | #define AR5K_PHY_AGCCOARSE_HI 0x003f8000 /* AGC Coarse high */ |
fa1c114f JS |
2028 | #define AR5K_PHY_AGCCOARSE_HI_S 15 |
2029 | ||
2030 | /* | |
2031 | * PHY agility control register | |
2032 | */ | |
2033 | #define AR5K_PHY_AGCCTL 0x9860 /* Register address */ | |
2034 | #define AR5K_PHY_AGCCTL_CAL 0x00000001 /* Enable PHY calibration */ | |
2035 | #define AR5K_PHY_AGCCTL_NF 0x00000002 /* Enable Noise Floor calibration */ | |
2bed03eb | 2036 | #define AR5K_PHY_AGCCTL_OFDM_DIV_DIS 0x00000008 /* Disable antenna diversity on OFDM modes */ |
1bef016a | 2037 | #define AR5K_PHY_AGCCTL_NF_EN 0x00008000 /* Enable nf calibration to happen (?) */ |
2bed03eb | 2038 | #define AR5K_PHY_AGCTL_FLTR_CAL 0x00010000 /* Allow filter calibration (?) */ |
1bef016a | 2039 | #define AR5K_PHY_AGCCTL_NF_NOUPDATE 0x00020000 /* Don't update nf automaticaly */ |
fa1c114f JS |
2040 | |
2041 | /* | |
2042 | * PHY noise floor status register | |
2043 | */ | |
0bacdf30 NK |
2044 | #define AR5K_PHY_NF 0x9864 /* Register address */ |
2045 | #define AR5K_PHY_NF_M 0x000001ff /* Noise floor mask */ | |
2046 | #define AR5K_PHY_NF_ACTIVE 0x00000100 /* Noise floor calibration still active */ | |
fa1c114f JS |
2047 | #define AR5K_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_PHY_NF_M) |
2048 | #define AR5K_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_PHY_NF_M) + 1) | |
2049 | #define AR5K_PHY_NF_SVAL(_n) (((_n) & AR5K_PHY_NF_M) | (1 << 9)) | |
1bef016a NK |
2050 | #define AR5K_PHY_NF_THRESH62 0x0007f000 /* Thresh62 -check ANI patent- (field) */ |
2051 | #define AR5K_PHY_NF_THRESH62_S 12 | |
2052 | #define AR5K_PHY_NF_MINCCA_PWR 0x0ff80000 /* ??? */ | |
2053 | #define AR5K_PHY_NF_MINCCA_PWR_S 19 | |
fa1c114f JS |
2054 | |
2055 | /* | |
2056 | * PHY ADC saturation register [5110] | |
2057 | */ | |
2058 | #define AR5K_PHY_ADCSAT 0x9868 | |
2059 | #define AR5K_PHY_ADCSAT_ICNT 0x0001f800 | |
2060 | #define AR5K_PHY_ADCSAT_ICNT_S 11 | |
2061 | #define AR5K_PHY_ADCSAT_THR 0x000007e0 | |
2062 | #define AR5K_PHY_ADCSAT_THR_S 5 | |
2063 | ||
0bacdf30 NK |
2064 | /* |
2065 | * PHY Weak ofdm signal detection threshold registers (ANI) [5212+] | |
2066 | */ | |
2067 | ||
2068 | /* High thresholds */ | |
2069 | #define AR5K_PHY_WEAK_OFDM_HIGH_THR 0x9868 | |
2070 | #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT 0x0000001f | |
2071 | #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT_S 0 | |
2072 | #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1 0x00fe0000 | |
2073 | #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_S 17 | |
2074 | #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2 0x7f000000 | |
2075 | #define AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_S 24 | |
2076 | ||
2077 | /* Low thresholds */ | |
2078 | #define AR5K_PHY_WEAK_OFDM_LOW_THR 0x986c | |
2079 | #define AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN 0x00000001 | |
2080 | #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT 0x00003f00 | |
2081 | #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT_S 8 | |
2082 | #define AR5K_PHY_WEAK_OFDM_LOW_THR_M1 0x001fc000 | |
2083 | #define AR5K_PHY_WEAK_OFDM_LOW_THR_M1_S 14 | |
2084 | #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2 0x0fe00000 | |
2085 | #define AR5K_PHY_WEAK_OFDM_LOW_THR_M2_S 21 | |
2086 | ||
2087 | ||
fa1c114f JS |
2088 | /* |
2089 | * PHY sleep registers [5112+] | |
2090 | */ | |
2091 | #define AR5K_PHY_SCR 0x9870 | |
1bef016a | 2092 | |
fa1c114f JS |
2093 | #define AR5K_PHY_SLMT 0x9874 |
2094 | #define AR5K_PHY_SLMT_32MHZ 0x0000007f | |
1bef016a | 2095 | |
fa1c114f JS |
2096 | #define AR5K_PHY_SCAL 0x9878 |
2097 | #define AR5K_PHY_SCAL_32MHZ 0x0000000e | |
e8f055f0 NK |
2098 | #define AR5K_PHY_SCAL_32MHZ_2417 0x0000000a |
2099 | #define AR5K_PHY_SCAL_32MHZ_HB63 0x00000032 | |
1bef016a | 2100 | |
fa1c114f JS |
2101 | /* |
2102 | * PHY PLL (Phase Locked Loop) control register | |
2103 | */ | |
2104 | #define AR5K_PHY_PLL 0x987c | |
1bef016a NK |
2105 | #define AR5K_PHY_PLL_20MHZ 0x00000013 /* For half rate (?) */ |
2106 | /* 40MHz -> 5GHz band */ | |
2107 | #define AR5K_PHY_PLL_40MHZ_5211 0x00000018 | |
fa1c114f | 2108 | #define AR5K_PHY_PLL_40MHZ_5212 0x000000aa |
1bef016a | 2109 | #define AR5K_PHY_PLL_40MHZ_5413 0x00000004 |
fa1c114f JS |
2110 | #define AR5K_PHY_PLL_40MHZ (ah->ah_version == AR5K_AR5211 ? \ |
2111 | AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212) | |
1bef016a NK |
2112 | /* 44MHz -> 2.4GHz band */ |
2113 | #define AR5K_PHY_PLL_44MHZ_5211 0x00000019 | |
fa1c114f JS |
2114 | #define AR5K_PHY_PLL_44MHZ_5212 0x000000ab |
2115 | #define AR5K_PHY_PLL_44MHZ (ah->ah_version == AR5K_AR5211 ? \ | |
2116 | AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212) | |
1bef016a | 2117 | |
fa1c114f JS |
2118 | #define AR5K_PHY_PLL_RF5111 0x00000000 |
2119 | #define AR5K_PHY_PLL_RF5112 0x00000040 | |
0bacdf30 NK |
2120 | #define AR5K_PHY_PLL_HALF_RATE 0x00000100 |
2121 | #define AR5K_PHY_PLL_QUARTER_RATE 0x00000200 | |
fa1c114f JS |
2122 | |
2123 | /* | |
2124 | * RF Buffer register | |
2125 | * | |
fa1c114f JS |
2126 | * It's obvious from the code that 0x989c is the buffer register but |
2127 | * for the other special registers that we write to after sending each | |
2128 | * packet, i have no idea. So i'll name them BUFFER_CONTROL_X registers | |
2129 | * for now. It's interesting that they are also used for some other operations. | |
fa1c114f JS |
2130 | */ |
2131 | ||
2132 | #define AR5K_RF_BUFFER 0x989c | |
2133 | #define AR5K_RF_BUFFER_CONTROL_0 0x98c0 /* Channel on 5110 */ | |
2134 | #define AR5K_RF_BUFFER_CONTROL_1 0x98c4 /* Bank 7 on 5112 */ | |
2135 | #define AR5K_RF_BUFFER_CONTROL_2 0x98cc /* Bank 7 on 5111 */ | |
2136 | ||
2137 | #define AR5K_RF_BUFFER_CONTROL_3 0x98d0 /* Bank 2 on 5112 */ | |
2138 | /* Channel set on 5111 */ | |
2139 | /* Used to read radio revision*/ | |
2140 | ||
2141 | #define AR5K_RF_BUFFER_CONTROL_4 0x98d4 /* RF Stage register on 5110 */ | |
2142 | /* Bank 0,1,2,6 on 5111 */ | |
2143 | /* Bank 1 on 5112 */ | |
2144 | /* Used during activation on 5111 */ | |
2145 | ||
2146 | #define AR5K_RF_BUFFER_CONTROL_5 0x98d8 /* Bank 3 on 5111 */ | |
2147 | /* Used during activation on 5111 */ | |
2148 | /* Channel on 5112 */ | |
2149 | /* Bank 6 on 5112 */ | |
2150 | ||
2151 | #define AR5K_RF_BUFFER_CONTROL_6 0x98dc /* Bank 3 on 5112 */ | |
2152 | ||
2153 | /* | |
2154 | * PHY RF stage register [5210] | |
2155 | */ | |
2156 | #define AR5K_PHY_RFSTG 0x98d4 | |
2157 | #define AR5K_PHY_RFSTG_DISABLE 0x00000021 | |
2158 | ||
1bef016a NK |
2159 | /* |
2160 | * BIN masks (?) | |
2161 | */ | |
2162 | #define AR5K_PHY_BIN_MASK_1 0x9900 | |
2163 | #define AR5K_PHY_BIN_MASK_2 0x9904 | |
2164 | #define AR5K_PHY_BIN_MASK_3 0x9908 | |
2165 | ||
2166 | #define AR5K_PHY_BIN_MASK_CTL 0x990c | |
2167 | #define AR5K_PHY_BIN_MASK_CTL_MASK_4 0x00003fff | |
2168 | #define AR5K_PHY_BIN_MASK_CTL_MASK_4_S 0 | |
2169 | #define AR5K_PHY_BIN_MASK_CTL_RATE 0xff000000 | |
2170 | #define AR5K_PHY_BIN_MASK_CTL_RATE_S 24 | |
2171 | ||
0bacdf30 NK |
2172 | /* |
2173 | * PHY Antenna control register | |
2174 | */ | |
2175 | #define AR5K_PHY_ANT_CTL 0x9910 /* Register Address */ | |
2176 | #define AR5K_PHY_ANT_CTL_TXRX_EN 0x00000001 /* Enable TX/RX (?) */ | |
2177 | #define AR5K_PHY_ANT_CTL_SECTORED_ANT 0x00000004 /* Sectored Antenna */ | |
2178 | #define AR5K_PHY_ANT_CTL_HITUNE5 0x00000008 /* Hitune5 (?) */ | |
e8f055f0 NK |
2179 | #define AR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x000003f0 /* Switch table idle (?) */ |
2180 | #define AR5K_PHY_ANT_CTL_SWTABLE_IDLE_S 4 | |
0bacdf30 | 2181 | |
fa1c114f JS |
2182 | /* |
2183 | * PHY receiver delay register [5111+] | |
2184 | */ | |
0bacdf30 NK |
2185 | #define AR5K_PHY_RX_DELAY 0x9914 /* Register Address */ |
2186 | #define AR5K_PHY_RX_DELAY_M 0x00003fff /* Mask for RX activate to receive delay (/100ns) */ | |
2187 | ||
2188 | /* | |
2189 | * PHY max rx length register (?) [5111] | |
2190 | */ | |
2191 | #define AR5K_PHY_MAX_RX_LEN 0x991c | |
fa1c114f JS |
2192 | |
2193 | /* | |
0bacdf30 NK |
2194 | * PHY timing register 4 |
2195 | * I(nphase)/Q(adrature) calibration register [5111+] | |
fa1c114f | 2196 | */ |
0bacdf30 | 2197 | #define AR5K_PHY_IQ 0x9920 /* Register Address */ |
fa1c114f JS |
2198 | #define AR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f /* Mask for q correction info */ |
2199 | #define AR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 /* Mask for i correction info */ | |
2200 | #define AR5K_PHY_IQ_CORR_Q_I_COFF_S 5 | |
2201 | #define AR5K_PHY_IQ_CORR_ENABLE 0x00000800 /* Enable i/q correction */ | |
0bacdf30 | 2202 | #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 /* Mask for max number of samples in log scale */ |
fa1c114f JS |
2203 | #define AR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12 |
2204 | #define AR5K_PHY_IQ_RUN 0x00010000 /* Run i/q calibration */ | |
0bacdf30 NK |
2205 | #define AR5K_PHY_IQ_USE_PT_DF 0x00020000 /* Use pilot track df (?) */ |
2206 | #define AR5K_PHY_IQ_EARLY_TRIG_THR 0x00200000 /* Early trigger threshold (?) (field) */ | |
2207 | #define AR5K_PHY_IQ_PILOT_MASK_EN 0x10000000 /* Enable pilot mask (?) */ | |
2208 | #define AR5K_PHY_IQ_CHAN_MASK_EN 0x20000000 /* Enable channel mask (?) */ | |
2209 | #define AR5K_PHY_IQ_SPUR_FILT_EN 0x40000000 /* Enable spur filter */ | |
2210 | #define AR5K_PHY_IQ_SPUR_RSSI_EN 0x80000000 /* Enable spur rssi */ | |
fa1c114f | 2211 | |
0bacdf30 NK |
2212 | /* |
2213 | * PHY timing register 5 | |
2214 | * OFDM Self-correlator Cyclic RSSI threshold params | |
2215 | * (Check out bb_cycpwr_thr1 on ANI patent) | |
2216 | */ | |
2217 | #define AR5K_PHY_OFDM_SELFCORR 0x9924 /* Register Address */ | |
2218 | #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_EN 0x00000001 /* Enable cyclic RSSI thr 1 */ | |
2219 | #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1 0x000000fe /* Mask for Cyclic RSSI threshold 1 */ | |
e8f055f0 | 2220 | #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1_S 1 |
0bacdf30 NK |
2221 | #define AR5K_PHY_OFDM_SELFCORR_CYPWR_THR3 0x00000100 /* Cyclic RSSI threshold 3 (field) (?) */ |
2222 | #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR_EN 0x00008000 /* Enable 1A RSSI threshold (?) */ | |
2223 | #define AR5K_PHY_OFDM_SELFCORR_RSSI_1ATHR 0x00010000 /* 1A RSSI threshold (field) (?) */ | |
2224 | #define AR5K_PHY_OFDM_SELFCORR_LSCTHR_HIRSSI 0x00800000 /* Long sc threshold hi rssi (?) */ | |
2225 | ||
2226 | /* | |
2227 | * PHY-only warm reset register | |
2228 | */ | |
2229 | #define AR5K_PHY_WARM_RESET 0x9928 | |
2230 | ||
2231 | /* | |
2232 | * PHY-only control register | |
2233 | */ | |
2234 | #define AR5K_PHY_CTL 0x992c /* Register Address */ | |
2235 | #define AR5K_PHY_CTL_RX_DRAIN_RATE 0x00000001 /* RX drain rate (?) */ | |
2236 | #define AR5K_PHY_CTL_LATE_TX_SIG_SYM 0x00000002 /* Late tx signal symbol (?) */ | |
2237 | #define AR5K_PHY_CTL_GEN_SCRAMBLER 0x00000004 /* Generate scrambler */ | |
2238 | #define AR5K_PHY_CTL_TX_ANT_SEL 0x00000008 /* TX antenna select */ | |
2239 | #define AR5K_PHY_CTL_TX_ANT_STATIC 0x00000010 /* Static TX antenna */ | |
2240 | #define AR5K_PHY_CTL_RX_ANT_SEL 0x00000020 /* RX antenna select */ | |
2241 | #define AR5K_PHY_CTL_RX_ANT_STATIC 0x00000040 /* Static RX antenna */ | |
2242 | #define AR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080 /* Enable low freq sleep */ | |
fa1c114f JS |
2243 | |
2244 | /* | |
a406c139 | 2245 | * PHY PAPD probe register [5111+] |
fa1c114f JS |
2246 | */ |
2247 | #define AR5K_PHY_PAPD_PROBE 0x9930 | |
0bacdf30 NK |
2248 | #define AR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001 |
2249 | #define AR5K_PHY_PAPD_PROBE_PCDAC_BIAS 0x00000002 | |
2250 | #define AR5K_PHY_PAPD_PROBE_COMP_GAIN 0x00000040 | |
fa1c114f JS |
2251 | #define AR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00 |
2252 | #define AR5K_PHY_PAPD_PROBE_TXPOWER_S 9 | |
2253 | #define AR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000 | |
0bacdf30 | 2254 | #define AR5K_PHY_PAPD_PROBE_PREDIST_EN 0x00010000 |
fa1c114f JS |
2255 | #define AR5K_PHY_PAPD_PROBE_TYPE 0x01800000 /* [5112+] */ |
2256 | #define AR5K_PHY_PAPD_PROBE_TYPE_S 23 | |
2257 | #define AR5K_PHY_PAPD_PROBE_TYPE_OFDM 0 | |
2258 | #define AR5K_PHY_PAPD_PROBE_TYPE_XR 1 | |
2259 | #define AR5K_PHY_PAPD_PROBE_TYPE_CCK 2 | |
2260 | #define AR5K_PHY_PAPD_PROBE_GAINF 0xfe000000 | |
2261 | #define AR5K_PHY_PAPD_PROBE_GAINF_S 25 | |
2262 | #define AR5K_PHY_PAPD_PROBE_INI_5111 0x00004883 /* [5212+] */ | |
2263 | #define AR5K_PHY_PAPD_PROBE_INI_5112 0x00004882 /* [5212+] */ | |
2264 | ||
fa1c114f JS |
2265 | /* |
2266 | * PHY TX rate power registers [5112+] | |
2267 | */ | |
2268 | #define AR5K_PHY_TXPOWER_RATE1 0x9934 | |
2269 | #define AR5K_PHY_TXPOWER_RATE2 0x9938 | |
2270 | #define AR5K_PHY_TXPOWER_RATE_MAX 0x993c | |
2271 | #define AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE 0x00000040 | |
2272 | #define AR5K_PHY_TXPOWER_RATE3 0xa234 | |
2273 | #define AR5K_PHY_TXPOWER_RATE4 0xa238 | |
2274 | ||
2275 | /* | |
2276 | * PHY frame control register [5111+] | |
2277 | */ | |
2278 | #define AR5K_PHY_FRAME_CTL_5210 0x9804 | |
2279 | #define AR5K_PHY_FRAME_CTL_5211 0x9944 | |
2280 | #define AR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \ | |
2281 | AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211) | |
2282 | /*---[5111+]---*/ | |
0bacdf30 | 2283 | #define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 /* Mask for tx clip (?) */ |
fa1c114f | 2284 | #define AR5K_PHY_FRAME_CTL_TX_CLIP_S 3 |
0bacdf30 | 2285 | #define AR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000 /* Prepend chan info */ |
1bef016a NK |
2286 | #define AR5K_PHY_FRAME_CTL_EMU 0x80000000 |
2287 | #define AR5K_PHY_FRAME_CTL_EMU_S 31 | |
fa1c114f | 2288 | /*---[5110/5111]---*/ |
0bacdf30 NK |
2289 | #define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 /* PHY timing error */ |
2290 | #define AR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 /* Parity error */ | |
2291 | #define AR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000 /* Illegal rate */ | |
2292 | #define AR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000 /* Illegal length */ | |
fa1c114f | 2293 | #define AR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000 |
0bacdf30 | 2294 | #define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 /* TX underrun */ |
fa1c114f JS |
2295 | #define AR5K_PHY_FRAME_CTL_INI AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ |
2296 | AR5K_PHY_FRAME_CTL_TXURN_ERR | \ | |
2297 | AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ | |
2298 | AR5K_PHY_FRAME_CTL_ILLRATE_ERR | \ | |
2299 | AR5K_PHY_FRAME_CTL_PARITY_ERR | \ | |
2300 | AR5K_PHY_FRAME_CTL_TIMING_ERR | |
2301 | ||
e8f055f0 NK |
2302 | /* |
2303 | * PHY Tx Power adjustment register [5212A+] | |
2304 | */ | |
2305 | #define AR5K_PHY_TX_PWR_ADJ 0x994c | |
2306 | #define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA 0x00000fc0 | |
2307 | #define AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DELTA_S 6 | |
2308 | #define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX 0x00fc0000 | |
2309 | #define AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_INDEX_S 18 | |
2310 | ||
fa1c114f JS |
2311 | /* |
2312 | * PHY radar detection register [5111+] | |
2313 | */ | |
2314 | #define AR5K_PHY_RADAR 0x9954 | |
fa1c114f | 2315 | #define AR5K_PHY_RADAR_ENABLE 0x00000001 |
1bef016a NK |
2316 | #define AR5K_PHY_RADAR_DISABLE 0x00000000 |
2317 | #define AR5K_PHY_RADAR_INBANDTHR 0x0000003e /* Inband threshold | |
2318 | 5-bits, units unknown {0..31} | |
2319 | (? MHz ?) */ | |
fa1c114f JS |
2320 | #define AR5K_PHY_RADAR_INBANDTHR_S 1 |
2321 | ||
1bef016a NK |
2322 | #define AR5K_PHY_RADAR_PRSSI_THR 0x00000fc0 /* Pulse RSSI/SNR threshold |
2323 | 6-bits, dBm range {0..63} | |
2324 | in dBm units. */ | |
2325 | #define AR5K_PHY_RADAR_PRSSI_THR_S 6 | |
2326 | ||
2327 | #define AR5K_PHY_RADAR_PHEIGHT_THR 0x0003f000 /* Pulse height threshold | |
2328 | 6-bits, dBm range {0..63} | |
2329 | in dBm units. */ | |
2330 | #define AR5K_PHY_RADAR_PHEIGHT_THR_S 12 | |
2331 | ||
2332 | #define AR5K_PHY_RADAR_RSSI_THR 0x00fc0000 /* Radar RSSI/SNR threshold. | |
2333 | 6-bits, dBm range {0..63} | |
2334 | in dBm units. */ | |
2335 | #define AR5K_PHY_RADAR_RSSI_THR_S 18 | |
2336 | ||
2337 | #define AR5K_PHY_RADAR_FIRPWR_THR 0x7f000000 /* Finite Impulse Response | |
2338 | filter power out threshold. | |
2339 | 7-bits, standard power range | |
2340 | {0..127} in 1/2 dBm units. */ | |
2341 | #define AR5K_PHY_RADAR_FIRPWR_THRS 24 | |
2342 | ||
fa1c114f | 2343 | /* |
1bef016a | 2344 | * PHY antenna switch table registers |
fa1c114f JS |
2345 | */ |
2346 | #define AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960 | |
2347 | #define AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964 | |
2348 | ||
0bacdf30 NK |
2349 | /* |
2350 | * PHY Noise floor threshold | |
2351 | */ | |
2352 | #define AR5K_PHY_NFTHRES 0x9968 | |
2353 | ||
fa1c114f | 2354 | /* |
1bef016a | 2355 | * Sigma Delta register (?) [5213] |
fa1c114f | 2356 | */ |
1bef016a NK |
2357 | #define AR5K_PHY_SIGMA_DELTA 0x996C |
2358 | #define AR5K_PHY_SIGMA_DELTA_ADC_SEL 0x00000003 | |
2359 | #define AR5K_PHY_SIGMA_DELTA_ADC_SEL_S 0 | |
2360 | #define AR5K_PHY_SIGMA_DELTA_FILT2 0x000000f8 | |
2361 | #define AR5K_PHY_SIGMA_DELTA_FILT2_S 3 | |
2362 | #define AR5K_PHY_SIGMA_DELTA_FILT1 0x00001f00 | |
2363 | #define AR5K_PHY_SIGMA_DELTA_FILT1_S 8 | |
e8f055f0 | 2364 | #define AR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000 |
1bef016a NK |
2365 | #define AR5K_PHY_SIGMA_DELTA_ADC_CLIP_S 13 |
2366 | ||
2367 | /* | |
2368 | * RF restart register [5112+] (?) | |
2369 | */ | |
2370 | #define AR5K_PHY_RESTART 0x9970 /* restart */ | |
2371 | #define AR5K_PHY_RESTART_DIV_GC 0x001c0000 /* Fast diversity gc_limit (?) */ | |
2372 | #define AR5K_PHY_RESTART_DIV_GC_S 18 | |
2373 | ||
2374 | /* | |
2375 | * RF Bus access request register (for synth-oly channel switching) | |
2376 | */ | |
2377 | #define AR5K_PHY_RFBUS_REQ 0x997C | |
2378 | #define AR5K_PHY_RFBUS_REQ_REQUEST 0x00000001 | |
fa1c114f JS |
2379 | |
2380 | /* | |
1bef016a NK |
2381 | * Spur mitigation masks (?) |
2382 | */ | |
2383 | #define AR5K_PHY_TIMING_7 0x9980 | |
2384 | #define AR5K_PHY_TIMING_8 0x9984 | |
2385 | #define AR5K_PHY_TIMING_8_PILOT_MASK_2 0x000fffff | |
2386 | #define AR5K_PHY_TIMING_8_PILOT_MASK_2_S 0 | |
2387 | ||
2388 | #define AR5K_PHY_BIN_MASK2_1 0x9988 | |
2389 | #define AR5K_PHY_BIN_MASK2_2 0x998c | |
2390 | #define AR5K_PHY_BIN_MASK2_3 0x9990 | |
2391 | ||
2392 | #define AR5K_PHY_BIN_MASK2_4 0x9994 | |
2393 | #define AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff | |
2394 | #define AR5K_PHY_BIN_MASK2_4_MASK_4_S 0 | |
2395 | ||
a406c139 NK |
2396 | #define AR5K_PHY_TIMING_9 0x9998 |
2397 | #define AR5K_PHY_TIMING_10 0x999c | |
2398 | #define AR5K_PHY_TIMING_10_PILOT_MASK_2 0x000fffff | |
2399 | #define AR5K_PHY_TIMING_10_PILOT_MASK_2_S 0 | |
1bef016a NK |
2400 | |
2401 | /* | |
2402 | * Spur mitigation control | |
2403 | */ | |
a406c139 NK |
2404 | #define AR5K_PHY_TIMING_11 0x99a0 /* Register address */ |
2405 | #define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE 0x000fffff /* Spur delta phase */ | |
2406 | #define AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE_S 0 | |
2407 | #define AR5K_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000 /* Freq sigma delta */ | |
2408 | #define AR5K_PHY_TIMING_11_SPUR_FREQ_SD_S 20 | |
2409 | #define AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC 0x40000000 /* Spur filter in AGC detector */ | |
2410 | #define AR5K_PHY_TIMING_11_USE_SPUR_IN_SELFCOR 0x80000000 /* Spur filter in OFDM self correlator */ | |
1bef016a NK |
2411 | |
2412 | /* | |
2413 | * Gain tables | |
fa1c114f | 2414 | */ |
0bacdf30 | 2415 | #define AR5K_BB_GAIN_BASE 0x9b00 /* BaseBand Amplifier Gain table base address */ |
fa1c114f | 2416 | #define AR5K_BB_GAIN(_n) (AR5K_BB_GAIN_BASE + ((_n) << 2)) |
0bacdf30 | 2417 | #define AR5K_RF_GAIN_BASE 0x9a00 /* RF Amplrifier Gain table base address */ |
fa1c114f JS |
2418 | #define AR5K_RF_GAIN(_n) (AR5K_RF_GAIN_BASE + ((_n) << 2)) |
2419 | ||
2420 | /* | |
2421 | * PHY timing IQ calibration result register [5111+] | |
2422 | */ | |
0bacdf30 NK |
2423 | #define AR5K_PHY_IQRES_CAL_PWR_I 0x9c10 /* I (Inphase) power value */ |
2424 | #define AR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 /* Q (Quadrature) power value */ | |
fa1c114f JS |
2425 | #define AR5K_PHY_IQRES_CAL_CORR 0x9c18 /* I/Q Correlation */ |
2426 | ||
2427 | /* | |
2428 | * PHY current RSSI register [5111+] | |
2429 | */ | |
0bacdf30 NK |
2430 | #define AR5K_PHY_CURRENT_RSSI 0x9c1c |
2431 | ||
2432 | /* | |
1bef016a | 2433 | * PHY RF Bus grant register |
0bacdf30 NK |
2434 | */ |
2435 | #define AR5K_PHY_RFBUS_GRANT 0x9c20 | |
1bef016a | 2436 | #define AR5K_PHY_RFBUS_GRANT_OK 0x00000001 |
0bacdf30 NK |
2437 | |
2438 | /* | |
2439 | * PHY ADC test register | |
2440 | */ | |
2441 | #define AR5K_PHY_ADC_TEST 0x9c24 | |
2442 | #define AR5K_PHY_ADC_TEST_I 0x00000001 | |
2443 | #define AR5K_PHY_ADC_TEST_Q 0x00000200 | |
2444 | ||
2445 | /* | |
2446 | * PHY DAC test register | |
2447 | */ | |
2448 | #define AR5K_PHY_DAC_TEST 0x9c28 | |
2449 | #define AR5K_PHY_DAC_TEST_I 0x00000001 | |
2450 | #define AR5K_PHY_DAC_TEST_Q 0x00000200 | |
2451 | ||
2452 | /* | |
2453 | * PHY PTAT register (?) | |
2454 | */ | |
2455 | #define AR5K_PHY_PTAT 0x9c2c | |
2456 | ||
2457 | /* | |
2458 | * PHY Illegal TX rate register [5112+] | |
2459 | */ | |
2460 | #define AR5K_PHY_BAD_TX_RATE 0x9c30 | |
2461 | ||
2462 | /* | |
2463 | * PHY SPUR Power register [5112+] | |
2464 | */ | |
2465 | #define AR5K_PHY_SPUR_PWR 0x9c34 /* Register Address */ | |
2466 | #define AR5K_PHY_SPUR_PWR_I 0x00000001 /* SPUR Power estimate for I (field) */ | |
2467 | #define AR5K_PHY_SPUR_PWR_Q 0x00000100 /* SPUR Power estimate for Q (field) */ | |
2468 | #define AR5K_PHY_SPUR_PWR_FILT 0x00010000 /* Power with SPUR removed (field) */ | |
2469 | ||
2470 | /* | |
2471 | * PHY Channel status register [5112+] (?) | |
2472 | */ | |
2473 | #define AR5K_PHY_CHAN_STATUS 0x9c38 | |
2474 | #define AR5K_PHY_CHAN_STATUS_BT_ACT 0x00000001 | |
2475 | #define AR5K_PHY_CHAN_STATUS_RX_CLR_RAW 0x00000002 | |
2476 | #define AR5K_PHY_CHAN_STATUS_RX_CLR_MAC 0x00000004 | |
2477 | #define AR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x00000008 | |
2478 | ||
1bef016a NK |
2479 | /* |
2480 | * Heavy clip enable register | |
2481 | */ | |
2482 | #define AR5K_PHY_HEAVY_CLIP_ENABLE 0x99e0 | |
2483 | ||
2484 | /* | |
2485 | * PHY clock sleep registers [5112+] | |
2486 | */ | |
2487 | #define AR5K_PHY_SCLOCK 0x99f0 | |
2488 | #define AR5K_PHY_SCLOCK_32MHZ 0x0000000c | |
2489 | #define AR5K_PHY_SDELAY 0x99f4 | |
2490 | #define AR5K_PHY_SDELAY_32MHZ 0x000000ff | |
2491 | #define AR5K_PHY_SPENDING 0x99f8 | |
e8f055f0 | 2492 | |
1bef016a | 2493 | |
0bacdf30 NK |
2494 | /* |
2495 | * PHY PAPD I (power?) table (?) | |
2496 | * (92! entries) | |
2497 | */ | |
2498 | #define AR5K_PHY_PAPD_I_BASE 0xa000 | |
2499 | #define AR5K_PHY_PAPD_I(_n) (AR5K_PHY_PAPD_I_BASE + ((_n) << 2)) | |
fa1c114f JS |
2500 | |
2501 | /* | |
2502 | * PHY PCDAC TX power table | |
2503 | */ | |
a406c139 | 2504 | #define AR5K_PHY_PCDAC_TXPOWER_BASE 0xa180 |
fa1c114f JS |
2505 | #define AR5K_PHY_PCDAC_TXPOWER(_n) (AR5K_PHY_PCDAC_TXPOWER_BASE + ((_n) << 2)) |
2506 | ||
2507 | /* | |
2508 | * PHY mode register [5111+] | |
2509 | */ | |
0bacdf30 NK |
2510 | #define AR5K_PHY_MODE 0x0a200 /* Register Address */ |
2511 | #define AR5K_PHY_MODE_MOD 0x00000001 /* PHY Modulation bit */ | |
fa1c114f JS |
2512 | #define AR5K_PHY_MODE_MOD_OFDM 0 |
2513 | #define AR5K_PHY_MODE_MOD_CCK 1 | |
0bacdf30 | 2514 | #define AR5K_PHY_MODE_FREQ 0x00000002 /* Freq mode bit */ |
fa1c114f JS |
2515 | #define AR5K_PHY_MODE_FREQ_5GHZ 0 |
2516 | #define AR5K_PHY_MODE_FREQ_2GHZ 2 | |
0bacdf30 | 2517 | #define AR5K_PHY_MODE_MOD_DYN 0x00000004 /* Enable Dynamic OFDM/CCK mode [5112+] */ |
fa1c114f JS |
2518 | #define AR5K_PHY_MODE_RAD 0x00000008 /* [5212+] */ |
2519 | #define AR5K_PHY_MODE_RAD_RF5111 0 | |
2520 | #define AR5K_PHY_MODE_RAD_RF5112 8 | |
0bacdf30 NK |
2521 | #define AR5K_PHY_MODE_XR 0x00000010 /* Enable XR mode [5112+] */ |
2522 | #define AR5K_PHY_MODE_HALF_RATE 0x00000020 /* Enable Half rate (test) */ | |
2523 | #define AR5K_PHY_MODE_QUARTER_RATE 0x00000040 /* Enable Quarter rat (test) */ | |
fa1c114f JS |
2524 | |
2525 | /* | |
2526 | * PHY CCK transmit control register [5111+ (?)] | |
2527 | */ | |
2528 | #define AR5K_PHY_CCKTXCTL 0xa204 | |
2529 | #define AR5K_PHY_CCKTXCTL_WORLD 0x00000000 | |
2530 | #define AR5K_PHY_CCKTXCTL_JAPAN 0x00000010 | |
0bacdf30 NK |
2531 | #define AR5K_PHY_CCKTXCTL_SCRAMBLER_DIS 0x00000001 |
2532 | #define AR5K_PHY_CCKTXCTK_DAC_SCALE 0x00000004 | |
2533 | ||
2534 | /* | |
2535 | * PHY CCK Cross-correlator Barker RSSI threshold register [5212+] | |
2536 | */ | |
2537 | #define AR5K_PHY_CCK_CROSSCORR 0xa208 | |
2bed03eb | 2538 | #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR 0x0000003f |
0bacdf30 | 2539 | #define AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR_S 0 |
fa1c114f | 2540 | |
1bef016a NK |
2541 | /* Same address is used for antenna diversity activation */ |
2542 | #define AR5K_PHY_FAST_ANT_DIV 0xa208 | |
2543 | #define AR5K_PHY_FAST_ANT_DIV_EN 0x00002000 | |
2544 | ||
fa1c114f JS |
2545 | /* |
2546 | * PHY 2GHz gain register [5111+] | |
2547 | */ | |
1bef016a NK |
2548 | #define AR5K_PHY_GAIN_2GHZ 0xa20c |
2549 | #define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000 | |
fa1c114f | 2550 | #define AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18 |
1bef016a NK |
2551 | #define AR5K_PHY_GAIN_2GHZ_INI_5111 0x6480416c |
2552 | ||
2553 | #define AR5K_PHY_CCK_RX_CTL_4 0xa21c | |
2554 | #define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT 0x01f80000 | |
2555 | #define AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_SHORT_S 19 | |
2556 | ||
2557 | #define AR5K_PHY_DAG_CCK_CTL 0xa228 | |
2558 | #define AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THR 0x00000200 | |
2559 | #define AR5K_PHY_DAG_CCK_CTL_RSSI_THR 0x0001fc00 | |
2560 | #define AR5K_PHY_DAG_CCK_CTL_RSSI_THR_S 10 | |
2561 | ||
2562 | #define AR5K_PHY_FAST_ADC 0xa24c | |
2563 | ||
2564 | #define AR5K_PHY_BLUETOOTH 0xa254 | |
2565 | ||
2566 | /* | |
2567 | * Transmit Power Control register | |
2568 | * [2413+] | |
2569 | */ | |
2570 | #define AR5K_PHY_TPC_RG1 0xa258 | |
2571 | #define AR5K_PHY_TPC_RG1_NUM_PD_GAIN 0x0000c000 | |
2572 | #define AR5K_PHY_TPC_RG1_NUM_PD_GAIN_S 14 | |
8f655dde NK |
2573 | #define AR5K_PHY_TPC_RG1_PDGAIN_1 0x00030000 |
2574 | #define AR5K_PHY_TPC_RG1_PDGAIN_1_S 16 | |
2575 | #define AR5K_PHY_TPC_RG1_PDGAIN_2 0x000c0000 | |
2576 | #define AR5K_PHY_TPC_RG1_PDGAIN_2_S 18 | |
2577 | #define AR5K_PHY_TPC_RG1_PDGAIN_3 0x00300000 | |
2578 | #define AR5K_PHY_TPC_RG1_PDGAIN_3_S 20 | |
1bef016a NK |
2579 | |
2580 | #define AR5K_PHY_TPC_RG5 0xa26C | |
2581 | #define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP 0x0000000F | |
2582 | #define AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP_S 0 | |
2583 | #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1 0x000003F0 | |
2584 | #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1_S 4 | |
2585 | #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2 0x0000FC00 | |
2586 | #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2_S 10 | |
2587 | #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3 0x003F0000 | |
2588 | #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3_S 16 | |
2589 | #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4 0x0FC00000 | |
2590 | #define AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4_S 22 | |
a406c139 NK |
2591 | |
2592 | /* | |
2593 | * PHY PDADC Tx power table | |
2594 | */ | |
2595 | #define AR5K_PHY_PDADC_TXPOWER_BASE 0xa280 | |
2596 | #define AR5K_PHY_PDADC_TXPOWER(_n) (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2)) |