[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / ar9003_aic.c

/*
 * Copyright (c) 2015 Qualcomm Atheros Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include "hw.h"
#include "hw-ops.h"
#include "ar9003_mci.h"
#include "ar9003_aic.h"
#include "reg_aic.h"

static const u8 com_att_db_table[ATH_AIC_MAX_COM_ATT_DB_TABLE] = {
	0, 3, 9, 15, 21, 27
};

static const u16 aic_lin_table[ATH_AIC_MAX_AIC_LIN_TABLE] = {
	8191, 7300, 6506, 5799, 5168, 4606, 4105, 3659,
	3261, 2906, 2590, 2309, 2057, 1834, 1634, 1457,
	1298, 1157, 1031, 919,	819,  730,  651,  580,
	517,  461,  411,  366,	326,  291,  259,  231,
	206,  183,  163,  146,	130,  116,  103,  92,
	82,   73,   65,	  58,	52,   46,   41,	  37,
	33,   29,   26,	  23,	21,   18,   16,	  15,
	13,   12,   10,	  9,	8,    7,    7,	  6,
	5,    5,    4,	  4,	3
};

static bool ar9003_hw_is_aic_enabled(struct ath_hw *ah)
{
	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;

	/*
	 * Disable AIC for now, until we have all the
	 * HW code and the driver-layer support ready.
	 */
	return false;

	if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_AIC)
		return false;

	return true;
}

static int16_t ar9003_aic_find_valid(struct ath_aic_sram_info *cal_sram,
				     bool dir, u8 index)
{
	int16_t i;

	if (dir) {
		for (i = index + 1; i < ATH_AIC_MAX_BT_CHANNEL; i++) {
			if (cal_sram[i].valid)
				break;
		}
	} else {
		for (i = index - 1; i >= 0; i--) {
			if (cal_sram[i].valid)
				break;
		}
	}

	if ((i >= ATH_AIC_MAX_BT_CHANNEL) || (i < 0))
		i = -1;

	return i;
}

/*
 * type 0: aic_lin_table, 1: com_att_db_table
 */
static int16_t ar9003_aic_find_index(u8 type, int16_t value)
{
	int16_t i = -1;

	if (type == 0) {
		for (i = ATH_AIC_MAX_AIC_LIN_TABLE - 1; i >= 0; i--) {
			if (aic_lin_table[i] >= value)
				break;
		}
	} else if (type == 1) {
		for (i = 0; i < ATH_AIC_MAX_COM_ATT_DB_TABLE; i++) {
			if (com_att_db_table[i] > value) {
				i--;
				break;
			}
		}

		if (i >= ATH_AIC_MAX_COM_ATT_DB_TABLE)
			i = -1;
	}

	return i;
}

static void ar9003_aic_gain_table(struct ath_hw *ah)
{
	u32 aic_atten_word[19], i;

	/* Config LNA gain difference */
	REG_WRITE(ah, AR_PHY_BT_COEX_4, 0x2c200a00);
	REG_WRITE(ah, AR_PHY_BT_COEX_5, 0x5c4e4438);

	/* Program gain table */
	aic_atten_word[0] = (0x1 & 0xf) << 14 | (0x1f & 0x1f) << 9 | (0x0 & 0xf) << 5 |
		(0x1f & 0x1f); /* -01 dB: 4'd1, 5'd31,  00 dB: 4'd0, 5'd31 */
	aic_atten_word[1] = (0x3 & 0xf) << 14 | (0x1f & 0x1f) << 9 | (0x2 & 0xf) << 5 |
		(0x1f & 0x1f); /* -03 dB: 4'd3, 5'd31, -02 dB: 4'd2, 5'd31 */
	aic_atten_word[2] = (0x5 & 0xf) << 14 | (0x1f & 0x1f) << 9 | (0x4 & 0xf) << 5 |
		(0x1f & 0x1f); /* -05 dB: 4'd5, 5'd31, -04 dB: 4'd4, 5'd31 */
	aic_atten_word[3] = (0x1 & 0xf) << 14 | (0x1e & 0x1f) << 9 | (0x0 & 0xf) << 5 |
		(0x1e & 0x1f); /* -07 dB: 4'd1, 5'd30, -06 dB: 4'd0, 5'd30 */
	aic_atten_word[4] = (0x3 & 0xf) << 14 | (0x1e & 0x1f) << 9 | (0x2 & 0xf) << 5 |
		(0x1e & 0x1f); /* -09 dB: 4'd3, 5'd30, -08 dB: 4'd2, 5'd30 */
	aic_atten_word[5] = (0x5 & 0xf) << 14 | (0x1e & 0x1f) << 9 | (0x4 & 0xf) << 5 |
		(0x1e & 0x1f); /* -11 dB: 4'd5, 5'd30, -10 dB: 4'd4, 5'd30 */
	aic_atten_word[6] = (0x1 & 0xf) << 14 | (0xf & 0x1f) << 9  | (0x0 & 0xf) << 5 |
		(0xf & 0x1f);  /* -13 dB: 4'd1, 5'd15, -12 dB: 4'd0, 5'd15 */
	aic_atten_word[7] = (0x3 & 0xf) << 14 | (0xf & 0x1f) << 9  | (0x2 & 0xf) << 5 |
		(0xf & 0x1f);  /* -15 dB: 4'd3, 5'd15, -14 dB: 4'd2, 5'd15 */
	aic_atten_word[8] = (0x5 & 0xf) << 14 | (0xf & 0x1f) << 9  | (0x4 & 0xf) << 5 |
		(0xf & 0x1f);  /* -17 dB: 4'd5, 5'd15, -16 dB: 4'd4, 5'd15 */
	aic_atten_word[9] = (0x1 & 0xf) << 14 | (0x7 & 0x1f) << 9  | (0x0 & 0xf) << 5 |
		(0x7 & 0x1f);  /* -19 dB: 4'd1, 5'd07, -18 dB: 4'd0, 5'd07 */
	aic_atten_word[10] = (0x3 & 0xf) << 14 | (0x7 & 0x1f) << 9  | (0x2 & 0xf) << 5 |
		(0x7 & 0x1f);  /* -21 dB: 4'd3, 5'd07, -20 dB: 4'd2, 5'd07 */
	aic_atten_word[11] = (0x5 & 0xf) << 14 | (0x7 & 0x1f) << 9  | (0x4 & 0xf) << 5 |
		(0x7 & 0x1f);  /* -23 dB: 4'd5, 5'd07, -22 dB: 4'd4, 5'd07 */
	aic_atten_word[12] = (0x7 & 0xf) << 14 | (0x7 & 0x1f) << 9  | (0x6 & 0xf) << 5 |
		(0x7 & 0x1f);  /* -25 dB: 4'd7, 5'd07, -24 dB: 4'd6, 5'd07 */
	aic_atten_word[13] = (0x3 & 0xf) << 14 | (0x3 & 0x1f) << 9  | (0x2 & 0xf) << 5 |
		(0x3 & 0x1f);  /* -27 dB: 4'd3, 5'd03, -26 dB: 4'd2, 5'd03 */
	aic_atten_word[14] = (0x5 & 0xf) << 14 | (0x3 & 0x1f) << 9  | (0x4 & 0xf) << 5 |
		(0x3 & 0x1f);  /* -29 dB: 4'd5, 5'd03, -28 dB: 4'd4, 5'd03 */
	aic_atten_word[15] = (0x1 & 0xf) << 14 | (0x1 & 0x1f) << 9  | (0x0 & 0xf) << 5 |
		(0x1 & 0x1f);  /* -31 dB: 4'd1, 5'd01, -30 dB: 4'd0, 5'd01 */
	aic_atten_word[16] = (0x3 & 0xf) << 14 | (0x1 & 0x1f) << 9  | (0x2 & 0xf) << 5 |
		(0x1 & 0x1f);  /* -33 dB: 4'd3, 5'd01, -32 dB: 4'd2, 5'd01 */
	aic_atten_word[17] = (0x5 & 0xf) << 14 | (0x1 & 0x1f) << 9  | (0x4 & 0xf) << 5 |
		(0x1 & 0x1f);  /* -35 dB: 4'd5, 5'd01, -34 dB: 4'd4, 5'd01 */
	aic_atten_word[18] = (0x7 & 0xf) << 14 | (0x1 & 0x1f) << 9  | (0x6 & 0xf) << 5 |
		(0x1 & 0x1f);  /* -37 dB: 4'd7, 5'd01, -36 dB: 4'd6, 5'd01 */

	/* Write to Gain table with auto increment enabled. */
	REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000),
		  (ATH_AIC_SRAM_AUTO_INCREMENT |
		   ATH_AIC_SRAM_GAIN_TABLE_OFFSET));

	for (i = 0; i < 19; i++) {
		REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000),
			  aic_atten_word[i]);
	}
}

static void ar9003_aic_cal_start(struct ath_hw *ah, u8 min_valid_count)
{
	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;
	int i;

	/* Write to Gain table with auto increment enabled. */
	REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000),
		  (ATH_AIC_SRAM_AUTO_INCREMENT |
		   ATH_AIC_SRAM_CAL_OFFSET));

	for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) {
		REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000), 0);
		aic->aic_sram[i] = 0;
	}

	REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B0,
		  (SM(0, AR_PHY_AIC_MON_ENABLE) |
		   SM(127, AR_PHY_AIC_CAL_MAX_HOP_COUNT) |
		   SM(min_valid_count, AR_PHY_AIC_CAL_MIN_VALID_COUNT) |
		   SM(37, AR_PHY_AIC_F_WLAN) |
		   SM(1, AR_PHY_AIC_CAL_CH_VALID_RESET) |
		   SM(0, AR_PHY_AIC_CAL_ENABLE) |
		   SM(0x40, AR_PHY_AIC_BTTX_PWR_THR) |
		   SM(0, AR_PHY_AIC_ENABLE)));

	REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B1,
		  (SM(0, AR_PHY_AIC_MON_ENABLE) |
		   SM(1, AR_PHY_AIC_CAL_CH_VALID_RESET) |
		   SM(0, AR_PHY_AIC_CAL_ENABLE) |
		   SM(0x40, AR_PHY_AIC_BTTX_PWR_THR) |
		   SM(0, AR_PHY_AIC_ENABLE)));

	REG_WRITE(ah, AR_PHY_AIC_CTRL_1_B0,
		  (SM(8, AR_PHY_AIC_CAL_BT_REF_DELAY) |
		   SM(0, AR_PHY_AIC_BT_IDLE_CFG) |
		   SM(1, AR_PHY_AIC_STDBY_COND) |
		   SM(37, AR_PHY_AIC_STDBY_ROT_ATT_DB) |
		   SM(5, AR_PHY_AIC_STDBY_COM_ATT_DB) |
		   SM(15, AR_PHY_AIC_RSSI_MAX) |
		   SM(0, AR_PHY_AIC_RSSI_MIN)));

	REG_WRITE(ah, AR_PHY_AIC_CTRL_1_B1,
		  (SM(15, AR_PHY_AIC_RSSI_MAX) |
		   SM(0, AR_PHY_AIC_RSSI_MIN)));

	REG_WRITE(ah, AR_PHY_AIC_CTRL_2_B0,
		  (SM(44, AR_PHY_AIC_RADIO_DELAY) |
		   SM(8, AR_PHY_AIC_CAL_STEP_SIZE_CORR) |
		   SM(12, AR_PHY_AIC_CAL_ROT_IDX_CORR) |
		   SM(2, AR_PHY_AIC_CAL_CONV_CHECK_FACTOR) |
		   SM(5, AR_PHY_AIC_ROT_IDX_COUNT_MAX) |
		   SM(0, AR_PHY_AIC_CAL_SYNTH_TOGGLE) |
		   SM(0, AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX) |
		   SM(200, AR_PHY_AIC_CAL_SYNTH_SETTLING)));

	REG_WRITE(ah, AR_PHY_AIC_CTRL_3_B0,
		  (SM(2, AR_PHY_AIC_MON_MAX_HOP_COUNT) |
		   SM(1, AR_PHY_AIC_MON_MIN_STALE_COUNT) |
		   SM(1, AR_PHY_AIC_MON_PWR_EST_LONG) |
		   SM(2, AR_PHY_AIC_MON_PD_TALLY_SCALING) |
		   SM(10, AR_PHY_AIC_MON_PERF_THR) |
		   SM(2, AR_PHY_AIC_CAL_TARGET_MAG_SETTING) |
		   SM(1, AR_PHY_AIC_CAL_PERF_CHECK_FACTOR) |
		   SM(1, AR_PHY_AIC_CAL_PWR_EST_LONG)));

	REG_WRITE(ah, AR_PHY_AIC_CTRL_4_B0,
		  (SM(2, AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO) |
		   SM(3, AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO) |
		   SM(0, AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING) |
		   SM(2, AR_PHY_AIC_CAL_COM_ATT_DB_BACKOFF) |
		   SM(1, AR_PHY_AIC_CAL_COM_ATT_DB_FIXED)));

	REG_WRITE(ah, AR_PHY_AIC_CTRL_4_B1,
		  (SM(2, AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO) |
		   SM(3, AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO) |
		   SM(0, AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING) |
		   SM(2, AR_PHY_AIC_CAL_COM_ATT_DB_BACKOFF) |
		   SM(1, AR_PHY_AIC_CAL_COM_ATT_DB_FIXED)));

	ar9003_aic_gain_table(ah);

	/* Need to enable AIC reference signal in BT modem. */
	REG_WRITE(ah, ATH_AIC_BT_JUPITER_CTRL,
		  (REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) |
		   ATH_AIC_BT_AIC_ENABLE));

	aic->aic_cal_start_time = REG_READ(ah, AR_TSF_L32);

	/* Start calibration */
	REG_CLR_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);
	REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_CH_VALID_RESET);
	REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);

	aic->aic_caled_chan = 0;
	aic->aic_cal_state = AIC_CAL_STATE_STARTED;
}

static bool ar9003_aic_cal_post_process(struct ath_hw *ah)
{
	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;
	struct ath_aic_sram_info cal_sram[ATH_AIC_MAX_BT_CHANNEL];
	struct ath_aic_out_info aic_sram[ATH_AIC_MAX_BT_CHANNEL];
	u32 dir_path_gain_idx, quad_path_gain_idx, value;
	u32 fixed_com_att_db;
	int8_t dir_path_sign, quad_path_sign;
	int16_t i;
	bool ret = true;

	memset(&cal_sram, 0, sizeof(cal_sram));
	memset(&aic_sram, 0, sizeof(aic_sram));

	for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) {
		value = aic->aic_sram[i];

		cal_sram[i].valid =
			MS(value, AR_PHY_AIC_SRAM_VALID);
		cal_sram[i].rot_quad_att_db =
			MS(value, AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB);
		cal_sram[i].vga_quad_sign =
			MS(value, AR_PHY_AIC_SRAM_VGA_QUAD_SIGN);
		cal_sram[i].rot_dir_att_db =
			MS(value, AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB);
		cal_sram[i].vga_dir_sign =
			MS(value, AR_PHY_AIC_SRAM_VGA_DIR_SIGN);
		cal_sram[i].com_att_6db =
			MS(value, AR_PHY_AIC_SRAM_COM_ATT_6DB);

		if (cal_sram[i].valid) {
			dir_path_gain_idx = cal_sram[i].rot_dir_att_db +
				com_att_db_table[cal_sram[i].com_att_6db];
			quad_path_gain_idx = cal_sram[i].rot_quad_att_db +
				com_att_db_table[cal_sram[i].com_att_6db];

			dir_path_sign = (cal_sram[i].vga_dir_sign) ? 1 : -1;
			quad_path_sign = (cal_sram[i].vga_quad_sign) ? 1 : -1;

			aic_sram[i].dir_path_gain_lin = dir_path_sign *
				aic_lin_table[dir_path_gain_idx];
			aic_sram[i].quad_path_gain_lin = quad_path_sign *
				aic_lin_table[quad_path_gain_idx];
		}
	}

	for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) {
		int16_t start_idx, end_idx;

		if (cal_sram[i].valid)
			continue;

		start_idx = ar9003_aic_find_valid(cal_sram, 0, i);
		end_idx = ar9003_aic_find_valid(cal_sram, 1, i);

		if (start_idx < 0) {
			/* extrapolation */
			start_idx = end_idx;
			end_idx = ar9003_aic_find_valid(cal_sram, 1, start_idx);

			if (end_idx < 0) {
				ret = false;
				break;
			}

			aic_sram[i].dir_path_gain_lin =
				((aic_sram[start_idx].dir_path_gain_lin -
				  aic_sram[end_idx].dir_path_gain_lin) *
				 (start_idx - i) + ((end_idx - i) >> 1)) /
				(end_idx - i) +
				aic_sram[start_idx].dir_path_gain_lin;
			aic_sram[i].quad_path_gain_lin =
				((aic_sram[start_idx].quad_path_gain_lin -
				  aic_sram[end_idx].quad_path_gain_lin) *
				 (start_idx - i) + ((end_idx - i) >> 1)) /
				(end_idx - i) +
				aic_sram[start_idx].quad_path_gain_lin;
		}

		if (end_idx < 0) {
			/* extrapolation */
			end_idx = ar9003_aic_find_valid(cal_sram, 0, start_idx);

			if (end_idx < 0) {
				ret = false;
				break;
			}

			aic_sram[i].dir_path_gain_lin =
				((aic_sram[start_idx].dir_path_gain_lin -
				  aic_sram[end_idx].dir_path_gain_lin) *
				 (i - start_idx) + ((start_idx - end_idx) >> 1)) /
				(start_idx - end_idx) +
				aic_sram[start_idx].dir_path_gain_lin;
			aic_sram[i].quad_path_gain_lin =
				((aic_sram[start_idx].quad_path_gain_lin -
				  aic_sram[end_idx].quad_path_gain_lin) *
				 (i - start_idx) + ((start_idx - end_idx) >> 1)) /
				(start_idx - end_idx) +
				aic_sram[start_idx].quad_path_gain_lin;

		} else if (start_idx >= 0){
			/* interpolation */
			aic_sram[i].dir_path_gain_lin =
				(((end_idx - i) * aic_sram[start_idx].dir_path_gain_lin) +
				 ((i - start_idx) * aic_sram[end_idx].dir_path_gain_lin) +
				 ((end_idx - start_idx) >> 1)) /
				(end_idx - start_idx);
			aic_sram[i].quad_path_gain_lin =
				(((end_idx - i) * aic_sram[start_idx].quad_path_gain_lin) +
				 ((i - start_idx) * aic_sram[end_idx].quad_path_gain_lin) +
				 ((end_idx - start_idx) >> 1))/
				(end_idx - start_idx);
		}
	}

	/* From dir/quad_path_gain_lin to sram. */
	i = ar9003_aic_find_valid(cal_sram, 1, 0);
	if (i < 0) {
		i = 0;
		ret = false;
	}
	fixed_com_att_db = com_att_db_table[cal_sram[i].com_att_6db];

	for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) {
		int16_t rot_dir_path_att_db, rot_quad_path_att_db;

		aic_sram[i].sram.vga_dir_sign =
			(aic_sram[i].dir_path_gain_lin >= 0) ? 1 : 0;
		aic_sram[i].sram.vga_quad_sign=
			(aic_sram[i].quad_path_gain_lin >= 0) ? 1 : 0;

		rot_dir_path_att_db =
			ar9003_aic_find_index(0, abs(aic_sram[i].dir_path_gain_lin)) -
			fixed_com_att_db;
		rot_quad_path_att_db =
			ar9003_aic_find_index(0, abs(aic_sram[i].quad_path_gain_lin)) -
			fixed_com_att_db;

		aic_sram[i].sram.com_att_6db =
			ar9003_aic_find_index(1, fixed_com_att_db);

		aic_sram[i].sram.valid = 1;

		aic_sram[i].sram.rot_dir_att_db =
			min(max(rot_dir_path_att_db,
				(int16_t)ATH_AIC_MIN_ROT_DIR_ATT_DB),
			    ATH_AIC_MAX_ROT_DIR_ATT_DB);
		aic_sram[i].sram.rot_quad_att_db =
			min(max(rot_quad_path_att_db,
				(int16_t)ATH_AIC_MIN_ROT_QUAD_ATT_DB),
			    ATH_AIC_MAX_ROT_QUAD_ATT_DB);
	}

	for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) {
		aic->aic_sram[i] = (SM(aic_sram[i].sram.vga_dir_sign,
				       AR_PHY_AIC_SRAM_VGA_DIR_SIGN) |
				    SM(aic_sram[i].sram.vga_quad_sign,
				       AR_PHY_AIC_SRAM_VGA_QUAD_SIGN) |
				    SM(aic_sram[i].sram.com_att_6db,
				       AR_PHY_AIC_SRAM_COM_ATT_6DB) |
				    SM(aic_sram[i].sram.valid,
				       AR_PHY_AIC_SRAM_VALID) |
				    SM(aic_sram[i].sram.rot_dir_att_db,
				       AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB) |
				    SM(aic_sram[i].sram.rot_quad_att_db,
				       AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB));
	}

	return ret;
}

static void ar9003_aic_cal_done(struct ath_hw *ah)
{
	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;

	/* Disable AIC reference signal in BT modem. */
	REG_WRITE(ah, ATH_AIC_BT_JUPITER_CTRL,
		  (REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) &
		   ~ATH_AIC_BT_AIC_ENABLE));

	if (ar9003_aic_cal_post_process(ah))
		aic->aic_cal_state = AIC_CAL_STATE_DONE;
	else
		aic->aic_cal_state = AIC_CAL_STATE_ERROR;
}

static u8 ar9003_aic_cal_continue(struct ath_hw *ah, bool cal_once)
{
	struct ath_common *common = ath9k_hw_common(ah);
	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;
	int i, num_chan;

	num_chan = MS(mci_hw->config, ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN);

	if (!num_chan) {
		aic->aic_cal_state = AIC_CAL_STATE_ERROR;
		return aic->aic_cal_state;
	}

	if (cal_once) {
		for (i = 0; i < 10000; i++) {
			if ((REG_READ(ah, AR_PHY_AIC_CTRL_0_B1) &
			     AR_PHY_AIC_CAL_ENABLE) == 0)
				break;

			udelay(100);
		}
	}

	/*
	 * Use AR_PHY_AIC_CAL_ENABLE bit instead of AR_PHY_AIC_CAL_DONE.
	 * Sometimes CAL_DONE bit is not asserted.
	 */
	if ((REG_READ(ah, AR_PHY_AIC_CTRL_0_B1) &
	     AR_PHY_AIC_CAL_ENABLE) != 0) {
		ath_dbg(common, MCI, "AIC cal is not done after 40ms");
		goto exit;
	}

	REG_WRITE(ah, AR_PHY_AIC_SRAM_ADDR_B1,
		  (ATH_AIC_SRAM_CAL_OFFSET | ATH_AIC_SRAM_AUTO_INCREMENT));

	for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) {
		u32 value;

		value = REG_READ(ah, AR_PHY_AIC_SRAM_DATA_B1);

		if (value & 0x01) {
			if (aic->aic_sram[i] == 0)
				aic->aic_caled_chan++;

			aic->aic_sram[i] = value;

			if (!cal_once)
				break;
		}
	}

	if ((aic->aic_caled_chan >= num_chan) || cal_once) {
		ar9003_aic_cal_done(ah);
	} else {
		/* Start calibration */
		REG_CLR_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);
		REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1,
			    AR_PHY_AIC_CAL_CH_VALID_RESET);
		REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);
	}
exit:
	return aic->aic_cal_state;

}

u8 ar9003_aic_calibration_single(struct ath_hw *ah)
{
	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
	u8 cal_ret;
	int num_chan;

	num_chan = MS(mci_hw->config, ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN);

	ar9003_aic_cal_start(ah, num_chan);
	cal_ret = ar9003_aic_cal_continue(ah, true);

	return cal_ret;
}

void ar9003_hw_attach_aic_ops(struct ath_hw *ah)
{
	struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);

	priv_ops->is_aic_enabled = ar9003_hw_is_aic_enabled;
}
Commit	Line	Data
637625f2 SM	1	/*
	2	* Copyright (c) 2015 Qualcomm Atheros Inc.
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#include "hw.h"
	18	#include "hw-ops.h"
	19	#include "ar9003_mci.h"
	20	#include "ar9003_aic.h"
6dacafea	21	#include "reg_aic.h"
637625f2	22
188f1a12 SM	23	static const u8 com_att_db_table[ATH_AIC_MAX_COM_ATT_DB_TABLE] = {
	24	0, 3, 9, 15, 21, 27
	25	};
	26
	27	static const u16 aic_lin_table[ATH_AIC_MAX_AIC_LIN_TABLE] = {
	28	8191, 7300, 6506, 5799, 5168, 4606, 4105, 3659,
	29	3261, 2906, 2590, 2309, 2057, 1834, 1634, 1457,
	30	1298, 1157, 1031, 919, 819, 730, 651, 580,
	31	517, 461, 411, 366, 326, 291, 259, 231,
	32	206, 183, 163, 146, 130, 116, 103, 92,
	33	82, 73, 65, 58, 52, 46, 41, 37,
	34	33, 29, 26, 23, 21, 18, 16, 15,
	35	13, 12, 10, 9, 8, 7, 7, 6,
	36	5, 5, 4, 4, 3
	37	};
	38
637625f2 SM	39	static bool ar9003_hw_is_aic_enabled(struct ath_hw *ah)
	40	{
	41	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
	42
208837ee SM	43	/*
	44	* Disable AIC for now, until we have all the
	45	* HW code and the driver-layer support ready.
	46	*/
	47	return false;
	48
637625f2 SM	49	if (mci_hw->config & ATH_MCI_CONFIG_DISABLE_AIC)
	50	return false;
	51
	52	return true;
	53	}
	54
188f1a12 SM	55	static int16_t ar9003_aic_find_valid(struct ath_aic_sram_info *cal_sram,
	56	bool dir, u8 index)
	57	{
	58	int16_t i;
	59
	60	if (dir) {
	61	for (i = index + 1; i < ATH_AIC_MAX_BT_CHANNEL; i++) {
	62	if (cal_sram[i].valid)
	63	break;
	64	}
	65	} else {
	66	for (i = index - 1; i >= 0; i--) {
	67	if (cal_sram[i].valid)
	68	break;
	69	}
	70	}
	71
	72	if ((i >= ATH_AIC_MAX_BT_CHANNEL) \|\| (i < 0))
	73	i = -1;
	74
	75	return i;
	76	}
	77
	78	/*
	79	* type 0: aic_lin_table, 1: com_att_db_table
	80	*/
	81	static int16_t ar9003_aic_find_index(u8 type, int16_t value)
	82	{
	83	int16_t i = -1;
	84
	85	if (type == 0) {
	86	for (i = ATH_AIC_MAX_AIC_LIN_TABLE - 1; i >= 0; i--) {
	87	if (aic_lin_table[i] >= value)
	88	break;
	89	}
	90	} else if (type == 1) {
	91	for (i = 0; i < ATH_AIC_MAX_COM_ATT_DB_TABLE; i++) {
	92	if (com_att_db_table[i] > value) {
	93	i--;
	94	break;
	95	}
	96	}
	97
	98	if (i >= ATH_AIC_MAX_COM_ATT_DB_TABLE)
	99	i = -1;
	100	}
	101
	102	return i;
	103	}
	104
b6ab9ae2 SM	105	static void ar9003_aic_gain_table(struct ath_hw *ah)
	106	{
	107	u32 aic_atten_word[19], i;
	108
	109	/* Config LNA gain difference */
	110	REG_WRITE(ah, AR_PHY_BT_COEX_4, 0x2c200a00);
	111	REG_WRITE(ah, AR_PHY_BT_COEX_5, 0x5c4e4438);
	112
	113	/* Program gain table */
	114	aic_atten_word[0] = (0x1 & 0xf) << 14 \| (0x1f & 0x1f) << 9 \| (0x0 & 0xf) << 5 \|
	115	(0x1f & 0x1f); /* -01 dB: 4'd1, 5'd31, 00 dB: 4'd0, 5'd31 */
	116	aic_atten_word[1] = (0x3 & 0xf) << 14 \| (0x1f & 0x1f) << 9 \| (0x2 & 0xf) << 5 \|
	117	(0x1f & 0x1f); /* -03 dB: 4'd3, 5'd31, -02 dB: 4'd2, 5'd31 */
	118	aic_atten_word[2] = (0x5 & 0xf) << 14 \| (0x1f & 0x1f) << 9 \| (0x4 & 0xf) << 5 \|
	119	(0x1f & 0x1f); /* -05 dB: 4'd5, 5'd31, -04 dB: 4'd4, 5'd31 */
	120	aic_atten_word[3] = (0x1 & 0xf) << 14 \| (0x1e & 0x1f) << 9 \| (0x0 & 0xf) << 5 \|
	121	(0x1e & 0x1f); /* -07 dB: 4'd1, 5'd30, -06 dB: 4'd0, 5'd30 */
	122	aic_atten_word[4] = (0x3 & 0xf) << 14 \| (0x1e & 0x1f) << 9 \| (0x2 & 0xf) << 5 \|
	123	(0x1e & 0x1f); /* -09 dB: 4'd3, 5'd30, -08 dB: 4'd2, 5'd30 */
	124	aic_atten_word[5] = (0x5 & 0xf) << 14 \| (0x1e & 0x1f) << 9 \| (0x4 & 0xf) << 5 \|
	125	(0x1e & 0x1f); /* -11 dB: 4'd5, 5'd30, -10 dB: 4'd4, 5'd30 */
	126	aic_atten_word[6] = (0x1 & 0xf) << 14 \| (0xf & 0x1f) << 9 \| (0x0 & 0xf) << 5 \|
	127	(0xf & 0x1f); /* -13 dB: 4'd1, 5'd15, -12 dB: 4'd0, 5'd15 */
	128	aic_atten_word[7] = (0x3 & 0xf) << 14 \| (0xf & 0x1f) << 9 \| (0x2 & 0xf) << 5 \|
	129	(0xf & 0x1f); /* -15 dB: 4'd3, 5'd15, -14 dB: 4'd2, 5'd15 */
	130	aic_atten_word[8] = (0x5 & 0xf) << 14 \| (0xf & 0x1f) << 9 \| (0x4 & 0xf) << 5 \|
	131	(0xf & 0x1f); /* -17 dB: 4'd5, 5'd15, -16 dB: 4'd4, 5'd15 */
	132	aic_atten_word[9] = (0x1 & 0xf) << 14 \| (0x7 & 0x1f) << 9 \| (0x0 & 0xf) << 5 \|
	133	(0x7 & 0x1f); /* -19 dB: 4'd1, 5'd07, -18 dB: 4'd0, 5'd07 */
	134	aic_atten_word[10] = (0x3 & 0xf) << 14 \| (0x7 & 0x1f) << 9 \| (0x2 & 0xf) << 5 \|
	135	(0x7 & 0x1f); /* -21 dB: 4'd3, 5'd07, -20 dB: 4'd2, 5'd07 */
	136	aic_atten_word[11] = (0x5 & 0xf) << 14 \| (0x7 & 0x1f) << 9 \| (0x4 & 0xf) << 5 \|
	137	(0x7 & 0x1f); /* -23 dB: 4'd5, 5'd07, -22 dB: 4'd4, 5'd07 */
	138	aic_atten_word[12] = (0x7 & 0xf) << 14 \| (0x7 & 0x1f) << 9 \| (0x6 & 0xf) << 5 \|
	139	(0x7 & 0x1f); /* -25 dB: 4'd7, 5'd07, -24 dB: 4'd6, 5'd07 */
	140	aic_atten_word[13] = (0x3 & 0xf) << 14 \| (0x3 & 0x1f) << 9 \| (0x2 & 0xf) << 5 \|
	141	(0x3 & 0x1f); /* -27 dB: 4'd3, 5'd03, -26 dB: 4'd2, 5'd03 */
	142	aic_atten_word[14] = (0x5 & 0xf) << 14 \| (0x3 & 0x1f) << 9 \| (0x4 & 0xf) << 5 \|
	143	(0x3 & 0x1f); /* -29 dB: 4'd5, 5'd03, -28 dB: 4'd4, 5'd03 */
	144	aic_atten_word[15] = (0x1 & 0xf) << 14 \| (0x1 & 0x1f) << 9 \| (0x0 & 0xf) << 5 \|
	145	(0x1 & 0x1f); /* -31 dB: 4'd1, 5'd01, -30 dB: 4'd0, 5'd01 */
	146	aic_atten_word[16] = (0x3 & 0xf) << 14 \| (0x1 & 0x1f) << 9 \| (0x2 & 0xf) << 5 \|
	147	(0x1 & 0x1f); /* -33 dB: 4'd3, 5'd01, -32 dB: 4'd2, 5'd01 */
	148	aic_atten_word[17] = (0x5 & 0xf) << 14 \| (0x1 & 0x1f) << 9 \| (0x4 & 0xf) << 5 \|
	149	(0x1 & 0x1f); /* -35 dB: 4'd5, 5'd01, -34 dB: 4'd4, 5'd01 */
	150	aic_atten_word[18] = (0x7 & 0xf) << 14 \| (0x1 & 0x1f) << 9 \| (0x6 & 0xf) << 5 \|
	151	(0x1 & 0x1f); /* -37 dB: 4'd7, 5'd01, -36 dB: 4'd6, 5'd01 */
	152
	153	/* Write to Gain table with auto increment enabled. */
	154	REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000),
	155	(ATH_AIC_SRAM_AUTO_INCREMENT \|
	156	ATH_AIC_SRAM_GAIN_TABLE_OFFSET));
	157
	158	for (i = 0; i < 19; i++) {
	159	REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000),
	160	aic_atten_word[i]);
	161	}
	162	}
	163
	164	static void ar9003_aic_cal_start(struct ath_hw *ah, u8 min_valid_count)
	165	{
	166	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;
	167	int i;
	168
169	/* Write to Gain table with auto increment enabled. */
170	REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000),
171	(ATH_AIC_SRAM_AUTO_INCREMENT \|
172	ATH_AIC_SRAM_CAL_OFFSET));
173
174	for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) {
175	REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000), 0);
176	aic->aic_sram[i] = 0;
177	}
178
179	REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B0,
180	(SM(0, AR_PHY_AIC_MON_ENABLE) \|
181	SM(127, AR_PHY_AIC_CAL_MAX_HOP_COUNT) \|
182	SM(min_valid_count, AR_PHY_AIC_CAL_MIN_VALID_COUNT) \|
183	SM(37, AR_PHY_AIC_F_WLAN) \|
184	SM(1, AR_PHY_AIC_CAL_CH_VALID_RESET) \|
185	SM(0, AR_PHY_AIC_CAL_ENABLE) \|
186	SM(0x40, AR_PHY_AIC_BTTX_PWR_THR) \|
187	SM(0, AR_PHY_AIC_ENABLE)));
188
189	REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B1,
190	(SM(0, AR_PHY_AIC_MON_ENABLE) \|
191	SM(1, AR_PHY_AIC_CAL_CH_VALID_RESET) \|
192	SM(0, AR_PHY_AIC_CAL_ENABLE) \|
193	SM(0x40, AR_PHY_AIC_BTTX_PWR_THR) \|
194	SM(0, AR_PHY_AIC_ENABLE)));
195
196	REG_WRITE(ah, AR_PHY_AIC_CTRL_1_B0,
197	(SM(8, AR_PHY_AIC_CAL_BT_REF_DELAY) \|
198	SM(0, AR_PHY_AIC_BT_IDLE_CFG) \|
199	SM(1, AR_PHY_AIC_STDBY_COND) \|
200	SM(37, AR_PHY_AIC_STDBY_ROT_ATT_DB) \|
201	SM(5, AR_PHY_AIC_STDBY_COM_ATT_DB) \|
202	SM(15, AR_PHY_AIC_RSSI_MAX) \|
203	SM(0, AR_PHY_AIC_RSSI_MIN)));
204
205	REG_WRITE(ah, AR_PHY_AIC_CTRL_1_B1,
206	(SM(15, AR_PHY_AIC_RSSI_MAX) \|
207	SM(0, AR_PHY_AIC_RSSI_MIN)));
208
209	REG_WRITE(ah, AR_PHY_AIC_CTRL_2_B0,
210	(SM(44, AR_PHY_AIC_RADIO_DELAY) \|
211	SM(8, AR_PHY_AIC_CAL_STEP_SIZE_CORR) \|
212	SM(12, AR_PHY_AIC_CAL_ROT_IDX_CORR) \|
213	SM(2, AR_PHY_AIC_CAL_CONV_CHECK_FACTOR) \|
214	SM(5, AR_PHY_AIC_ROT_IDX_COUNT_MAX) \|
215	SM(0, AR_PHY_AIC_CAL_SYNTH_TOGGLE) \|
216	SM(0, AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX) \|
217	SM(200, AR_PHY_AIC_CAL_SYNTH_SETTLING)));
218
219	REG_WRITE(ah, AR_PHY_AIC_CTRL_3_B0,
220	(SM(2, AR_PHY_AIC_MON_MAX_HOP_COUNT) \|
221	SM(1, AR_PHY_AIC_MON_MIN_STALE_COUNT) \|
222	SM(1, AR_PHY_AIC_MON_PWR_EST_LONG) \|
223	SM(2, AR_PHY_AIC_MON_PD_TALLY_SCALING) \|
224	SM(10, AR_PHY_AIC_MON_PERF_THR) \|
225	SM(2, AR_PHY_AIC_CAL_TARGET_MAG_SETTING) \|
226	SM(1, AR_PHY_AIC_CAL_PERF_CHECK_FACTOR) \|
227	SM(1, AR_PHY_AIC_CAL_PWR_EST_LONG)));
228
229	REG_WRITE(ah, AR_PHY_AIC_CTRL_4_B0,
230	(SM(2, AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO) \|
231	SM(3, AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO) \|
232	SM(0, AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING) \|
233	SM(2, AR_PHY_AIC_CAL_COM_ATT_DB_BACKOFF) \|
234	SM(1, AR_PHY_AIC_CAL_COM_ATT_DB_FIXED)));
235
236	REG_WRITE(ah, AR_PHY_AIC_CTRL_4_B1,
237	(SM(2, AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO) \|
238	SM(3, AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO) \|
239	SM(0, AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING) \|
240	SM(2, AR_PHY_AIC_CAL_COM_ATT_DB_BACKOFF) \|
241	SM(1, AR_PHY_AIC_CAL_COM_ATT_DB_FIXED)));
242
243	ar9003_aic_gain_table(ah);
244
245	/* Need to enable AIC reference signal in BT modem. */
246	REG_WRITE(ah, ATH_AIC_BT_JUPITER_CTRL,
247	(REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) \|
248	ATH_AIC_BT_AIC_ENABLE));
249
250	aic->aic_cal_start_time = REG_READ(ah, AR_TSF_L32);
251
252	/* Start calibration */
253	REG_CLR_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);
254	REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_CH_VALID_RESET);
255	REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);
256
257	aic->aic_caled_chan = 0;
258	aic->aic_cal_state = AIC_CAL_STATE_STARTED;
259	}
260
188f1a12 SM	261	static bool ar9003_aic_cal_post_process(struct ath_hw *ah)
	262	{
	263	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;
	264	struct ath_aic_sram_info cal_sram[ATH_AIC_MAX_BT_CHANNEL];
	265	struct ath_aic_out_info aic_sram[ATH_AIC_MAX_BT_CHANNEL];
	266	u32 dir_path_gain_idx, quad_path_gain_idx, value;
	267	u32 fixed_com_att_db;
	268	int8_t dir_path_sign, quad_path_sign;
	269	int16_t i;
	270	bool ret = true;
	271
	272	memset(&cal_sram, 0, sizeof(cal_sram));
	273	memset(&aic_sram, 0, sizeof(aic_sram));
	274
	275	for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) {
	276	value = aic->aic_sram[i];
	277
	278	cal_sram[i].valid =
	279	MS(value, AR_PHY_AIC_SRAM_VALID);
	280	cal_sram[i].rot_quad_att_db =
	281	MS(value, AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB);
	282	cal_sram[i].vga_quad_sign =
	283	MS(value, AR_PHY_AIC_SRAM_VGA_QUAD_SIGN);
	284	cal_sram[i].rot_dir_att_db =
	285	MS(value, AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB);
	286	cal_sram[i].vga_dir_sign =
	287	MS(value, AR_PHY_AIC_SRAM_VGA_DIR_SIGN);
	288	cal_sram[i].com_att_6db =
	289	MS(value, AR_PHY_AIC_SRAM_COM_ATT_6DB);
	290
	291	if (cal_sram[i].valid) {
	292	dir_path_gain_idx = cal_sram[i].rot_dir_att_db +
	293	com_att_db_table[cal_sram[i].com_att_6db];
	294	quad_path_gain_idx = cal_sram[i].rot_quad_att_db +
	295	com_att_db_table[cal_sram[i].com_att_6db];
	296
	297	dir_path_sign = (cal_sram[i].vga_dir_sign) ? 1 : -1;
	298	quad_path_sign = (cal_sram[i].vga_quad_sign) ? 1 : -1;
	299
	300	aic_sram[i].dir_path_gain_lin = dir_path_sign *
	301	aic_lin_table[dir_path_gain_idx];
	302	aic_sram[i].quad_path_gain_lin = quad_path_sign *
	303	aic_lin_table[quad_path_gain_idx];
	304	}
	305	}
	306
	307	for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) {
	308	int16_t start_idx, end_idx;
	309
	310	if (cal_sram[i].valid)
	311	continue;
	312
	313	start_idx = ar9003_aic_find_valid(cal_sram, 0, i);
	314	end_idx = ar9003_aic_find_valid(cal_sram, 1, i);
	315
	316	if (start_idx < 0) {
	317	/* extrapolation */
	318	start_idx = end_idx;
	319	end_idx = ar9003_aic_find_valid(cal_sram, 1, start_idx);
	320
	321	if (end_idx < 0) {
	322	ret = false;
	323	break;
	324	}
325
326	aic_sram[i].dir_path_gain_lin =
327	((aic_sram[start_idx].dir_path_gain_lin -
328	aic_sram[end_idx].dir_path_gain_lin) *
329	(start_idx - i) + ((end_idx - i) >> 1)) /
330	(end_idx - i) +
331	aic_sram[start_idx].dir_path_gain_lin;
332	aic_sram[i].quad_path_gain_lin =
333	((aic_sram[start_idx].quad_path_gain_lin -
334	aic_sram[end_idx].quad_path_gain_lin) *
335	(start_idx - i) + ((end_idx - i) >> 1)) /
336	(end_idx - i) +
337	aic_sram[start_idx].quad_path_gain_lin;
338	}
339
340	if (end_idx < 0) {
341	/* extrapolation */
342	end_idx = ar9003_aic_find_valid(cal_sram, 0, start_idx);
343
344	if (end_idx < 0) {
345	ret = false;
346	break;
347	}
348
349	aic_sram[i].dir_path_gain_lin =
350	((aic_sram[start_idx].dir_path_gain_lin -
351	aic_sram[end_idx].dir_path_gain_lin) *
352	(i - start_idx) + ((start_idx - end_idx) >> 1)) /
353	(start_idx - end_idx) +
354	aic_sram[start_idx].dir_path_gain_lin;
355	aic_sram[i].quad_path_gain_lin =
356	((aic_sram[start_idx].quad_path_gain_lin -
357	aic_sram[end_idx].quad_path_gain_lin) *
358	(i - start_idx) + ((start_idx - end_idx) >> 1)) /
359	(start_idx - end_idx) +
360	aic_sram[start_idx].quad_path_gain_lin;
361
362	} else if (start_idx >= 0){
363	/* interpolation */
364	aic_sram[i].dir_path_gain_lin =
365	(((end_idx - i) * aic_sram[start_idx].dir_path_gain_lin) +
366	((i - start_idx) * aic_sram[end_idx].dir_path_gain_lin) +
367	((end_idx - start_idx) >> 1)) /
368	(end_idx - start_idx);
369	aic_sram[i].quad_path_gain_lin =
370	(((end_idx - i) * aic_sram[start_idx].quad_path_gain_lin) +
371	((i - start_idx) * aic_sram[end_idx].quad_path_gain_lin) +
372	((end_idx - start_idx) >> 1))/
373	(end_idx - start_idx);
374	}
375	}
376
377	/* From dir/quad_path_gain_lin to sram. */
378	i = ar9003_aic_find_valid(cal_sram, 1, 0);
379	if (i < 0) {
380	i = 0;
381	ret = false;
382	}
383	fixed_com_att_db = com_att_db_table[cal_sram[i].com_att_6db];
384
385	for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) {
386	int16_t rot_dir_path_att_db, rot_quad_path_att_db;
387
388	aic_sram[i].sram.vga_dir_sign =
389	(aic_sram[i].dir_path_gain_lin >= 0) ? 1 : 0;
390	aic_sram[i].sram.vga_quad_sign=
391	(aic_sram[i].quad_path_gain_lin >= 0) ? 1 : 0;
392
393	rot_dir_path_att_db =
394	ar9003_aic_find_index(0, abs(aic_sram[i].dir_path_gain_lin)) -
395	fixed_com_att_db;
396	rot_quad_path_att_db =
397	ar9003_aic_find_index(0, abs(aic_sram[i].quad_path_gain_lin)) -
398	fixed_com_att_db;
399
400	aic_sram[i].sram.com_att_6db =
401	ar9003_aic_find_index(1, fixed_com_att_db);
402
403	aic_sram[i].sram.valid = 1;
404
405	aic_sram[i].sram.rot_dir_att_db =
406	min(max(rot_dir_path_att_db,
407	(int16_t)ATH_AIC_MIN_ROT_DIR_ATT_DB),
408	ATH_AIC_MAX_ROT_DIR_ATT_DB);
409	aic_sram[i].sram.rot_quad_att_db =
410	min(max(rot_quad_path_att_db,
411	(int16_t)ATH_AIC_MIN_ROT_QUAD_ATT_DB),
412	ATH_AIC_MAX_ROT_QUAD_ATT_DB);
413	}
414
415	for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) {
416	aic->aic_sram[i] = (SM(aic_sram[i].sram.vga_dir_sign,
417	AR_PHY_AIC_SRAM_VGA_DIR_SIGN) \|
418	SM(aic_sram[i].sram.vga_quad_sign,
419	AR_PHY_AIC_SRAM_VGA_QUAD_SIGN) \|
420	SM(aic_sram[i].sram.com_att_6db,
421	AR_PHY_AIC_SRAM_COM_ATT_6DB) \|
422	SM(aic_sram[i].sram.valid,
423	AR_PHY_AIC_SRAM_VALID) \|
424	SM(aic_sram[i].sram.rot_dir_att_db,
425	AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB) \|
426	SM(aic_sram[i].sram.rot_quad_att_db,
427	AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB));
428	}
429
430	return ret;
431	}
432
716eed4c SM	433	static void ar9003_aic_cal_done(struct ath_hw *ah)
716eed4c SM	434	{
188f1a12 SM	435	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;
188f1a12 SM	436
716eed4c SM	437	/* Disable AIC reference signal in BT modem. */
	438	REG_WRITE(ah, ATH_AIC_BT_JUPITER_CTRL,
	439	(REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) &
	440	~ATH_AIC_BT_AIC_ENABLE));
188f1a12 SM	441
	442	if (ar9003_aic_cal_post_process(ah))
	443	aic->aic_cal_state = AIC_CAL_STATE_DONE;
	444	else
	445	aic->aic_cal_state = AIC_CAL_STATE_ERROR;
716eed4c SM	446	}
	447
	448	static u8 ar9003_aic_cal_continue(struct ath_hw *ah, bool cal_once)
	449	{
	450	struct ath_common *common = ath9k_hw_common(ah);
	451	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
	452	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;
	453	int i, num_chan;
	454
	455	num_chan = MS(mci_hw->config, ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN);
	456
	457	if (!num_chan) {
	458	aic->aic_cal_state = AIC_CAL_STATE_ERROR;
	459	return aic->aic_cal_state;
	460	}
	461
	462	if (cal_once) {
	463	for (i = 0; i < 10000; i++) {
	464	if ((REG_READ(ah, AR_PHY_AIC_CTRL_0_B1) &
	465	AR_PHY_AIC_CAL_ENABLE) == 0)
	466	break;
	467
	468	udelay(100);
	469	}
	470	}
	471
	472	/*
	473	* Use AR_PHY_AIC_CAL_ENABLE bit instead of AR_PHY_AIC_CAL_DONE.
	474	* Sometimes CAL_DONE bit is not asserted.
	475	*/
	476	if ((REG_READ(ah, AR_PHY_AIC_CTRL_0_B1) &
	477	AR_PHY_AIC_CAL_ENABLE) != 0) {
	478	ath_dbg(common, MCI, "AIC cal is not done after 40ms");
	479	goto exit;
	480	}
	481
	482	REG_WRITE(ah, AR_PHY_AIC_SRAM_ADDR_B1,
	483	(ATH_AIC_SRAM_CAL_OFFSET \| ATH_AIC_SRAM_AUTO_INCREMENT));
	484
	485	for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) {
	486	u32 value;
	487
	488	value = REG_READ(ah, AR_PHY_AIC_SRAM_DATA_B1);
	489
	490	if (value & 0x01) {
	491	if (aic->aic_sram[i] == 0)
	492	aic->aic_caled_chan++;
	493
	494	aic->aic_sram[i] = value;
	495
	496	if (!cal_once)
	497	break;
	498	}
	499	}
	500
	501	if ((aic->aic_caled_chan >= num_chan) \|\| cal_once) {
	502	ar9003_aic_cal_done(ah);
	503	} else {
	504	/* Start calibration */
	505	REG_CLR_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);
	506	REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1,
	507	AR_PHY_AIC_CAL_CH_VALID_RESET);
	508	REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);
	509	}
510	exit:
511	return aic->aic_cal_state;
512
513	}
514
b6ab9ae2 SM	515	u8 ar9003_aic_calibration_single(struct ath_hw *ah)
	516	{
	517	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
716eed4c	518	u8 cal_ret;
b6ab9ae2 SM	519	int num_chan;
	520
	521	num_chan = MS(mci_hw->config, ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN);
	522
	523	ar9003_aic_cal_start(ah, num_chan);
716eed4c	524	cal_ret = ar9003_aic_cal_continue(ah, true);
b6ab9ae2 SM	525
	526	return cal_ret;
	527	}
	528
637625f2 SM	529	void ar9003_hw_attach_aic_ops(struct ath_hw *ah)
	530	{
	531	struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
	532
	533	priv_ops->is_aic_enabled = ar9003_hw_is_aic_enabled;
	534	}