Commit | Line | Data |
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b5aec950 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
b5aec950 S |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
78fa99ab | 17 | #include <asm/unaligned.h> |
c46917bb | 18 | #include "hw.h" |
8fe65368 | 19 | #include "ar9002_phy.h" |
b5aec950 S |
20 | |
21 | static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah) | |
22 | { | |
23 | return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF); | |
24 | } | |
25 | ||
26 | static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah) | |
27 | { | |
28 | return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF); | |
29 | } | |
30 | ||
b5aec950 | 31 | #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) |
04cf53f4 SM |
32 | |
33 | static bool __ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) | |
34 | { | |
b5aec950 | 35 | u16 *eep_data = (u16 *)&ah->eeprom.map4k; |
04cf53f4 | 36 | int addr, eep_start_loc = 64; |
b5aec950 S |
37 | |
38 | for (addr = 0; addr < SIZE_EEPROM_4K; addr++) { | |
0e4b9f2f | 39 | if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) |
b5aec950 | 40 | return false; |
b5aec950 S |
41 | eep_data++; |
42 | } | |
43 | ||
44 | return true; | |
b5aec950 S |
45 | } |
46 | ||
04cf53f4 SM |
47 | static bool __ath9k_hw_usb_4k_fill_eeprom(struct ath_hw *ah) |
48 | { | |
49 | u16 *eep_data = (u16 *)&ah->eeprom.map4k; | |
50 | ||
51 | ath9k_hw_usb_gen_fill_eeprom(ah, eep_data, 64, SIZE_EEPROM_4K); | |
52 | ||
53 | return true; | |
54 | } | |
55 | ||
56 | static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah) | |
57 | { | |
58 | struct ath_common *common = ath9k_hw_common(ah); | |
59 | ||
60 | if (!ath9k_hw_use_flash(ah)) { | |
d2182b69 | 61 | ath_dbg(common, EEPROM, "Reading from EEPROM, not flash\n"); |
04cf53f4 SM |
62 | } |
63 | ||
64 | if (common->bus_ops->ath_bus_type == ATH_USB) | |
65 | return __ath9k_hw_usb_4k_fill_eeprom(ah); | |
66 | else | |
67 | return __ath9k_hw_4k_fill_eeprom(ah); | |
68 | } | |
69 | ||
4f011a2e RM |
70 | #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS) |
71 | static u32 ath9k_dump_4k_modal_eeprom(char *buf, u32 len, u32 size, | |
72 | struct modal_eep_4k_header *modal_hdr) | |
73 | { | |
74 | PR_EEP("Chain0 Ant. Control", modal_hdr->antCtrlChain[0]); | |
75 | PR_EEP("Ant. Common Control", modal_hdr->antCtrlCommon); | |
76 | PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]); | |
77 | PR_EEP("Switch Settle", modal_hdr->switchSettling); | |
78 | PR_EEP("Chain0 TxRxAtten", modal_hdr->txRxAttenCh[0]); | |
79 | PR_EEP("Chain0 RxTxMargin", modal_hdr->rxTxMarginCh[0]); | |
80 | PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize); | |
81 | PR_EEP("PGA Desired size", modal_hdr->pgaDesiredSize); | |
82 | PR_EEP("Chain0 xlna Gain", modal_hdr->xlnaGainCh[0]); | |
83 | PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff); | |
84 | PR_EEP("txEndToRxOn", modal_hdr->txEndToRxOn); | |
85 | PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn); | |
86 | PR_EEP("CCA Threshold)", modal_hdr->thresh62); | |
87 | PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]); | |
88 | PR_EEP("xpdGain", modal_hdr->xpdGain); | |
89 | PR_EEP("External PD", modal_hdr->xpd); | |
90 | PR_EEP("Chain0 I Coefficient", modal_hdr->iqCalICh[0]); | |
91 | PR_EEP("Chain0 Q Coefficient", modal_hdr->iqCalQCh[0]); | |
92 | PR_EEP("pdGainOverlap", modal_hdr->pdGainOverlap); | |
93 | PR_EEP("O/D Bias Version", modal_hdr->version); | |
94 | PR_EEP("CCK OutputBias", modal_hdr->ob_0); | |
95 | PR_EEP("BPSK OutputBias", modal_hdr->ob_1); | |
96 | PR_EEP("QPSK OutputBias", modal_hdr->ob_2); | |
97 | PR_EEP("16QAM OutputBias", modal_hdr->ob_3); | |
98 | PR_EEP("64QAM OutputBias", modal_hdr->ob_4); | |
99 | PR_EEP("CCK Driver1_Bias", modal_hdr->db1_0); | |
100 | PR_EEP("BPSK Driver1_Bias", modal_hdr->db1_1); | |
101 | PR_EEP("QPSK Driver1_Bias", modal_hdr->db1_2); | |
102 | PR_EEP("16QAM Driver1_Bias", modal_hdr->db1_3); | |
103 | PR_EEP("64QAM Driver1_Bias", modal_hdr->db1_4); | |
104 | PR_EEP("CCK Driver2_Bias", modal_hdr->db2_0); | |
105 | PR_EEP("BPSK Driver2_Bias", modal_hdr->db2_1); | |
106 | PR_EEP("QPSK Driver2_Bias", modal_hdr->db2_2); | |
107 | PR_EEP("16QAM Driver2_Bias", modal_hdr->db2_3); | |
108 | PR_EEP("64QAM Driver2_Bias", modal_hdr->db2_4); | |
109 | PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl); | |
110 | PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart); | |
111 | PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn); | |
112 | PR_EEP("HT40 Power Inc.", modal_hdr->ht40PowerIncForPdadc); | |
113 | PR_EEP("Chain0 bswAtten", modal_hdr->bswAtten[0]); | |
114 | PR_EEP("Chain0 bswMargin", modal_hdr->bswMargin[0]); | |
115 | PR_EEP("HT40 Switch Settle", modal_hdr->swSettleHt40); | |
116 | PR_EEP("Chain0 xatten2Db", modal_hdr->xatten2Db[0]); | |
117 | PR_EEP("Chain0 xatten2Margin", modal_hdr->xatten2Margin[0]); | |
118 | PR_EEP("Ant. Diversity ctl1", modal_hdr->antdiv_ctl1); | |
119 | PR_EEP("Ant. Diversity ctl2", modal_hdr->antdiv_ctl2); | |
120 | PR_EEP("TX Diversity", modal_hdr->tx_diversity); | |
121 | ||
122 | return len; | |
123 | } | |
124 | ||
125 | static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, | |
126 | u8 *buf, u32 len, u32 size) | |
127 | { | |
128 | struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; | |
129 | struct base_eep_header_4k *pBase = &eep->baseEepHeader; | |
130 | ||
131 | if (!dump_base_hdr) { | |
132 | len += snprintf(buf + len, size - len, | |
133 | "%20s :\n", "2GHz modal Header"); | |
d25360b1 | 134 | len = ath9k_dump_4k_modal_eeprom(buf, len, size, |
4f011a2e RM |
135 | &eep->modalHeader); |
136 | goto out; | |
137 | } | |
138 | ||
139 | PR_EEP("Major Version", pBase->version >> 12); | |
140 | PR_EEP("Minor Version", pBase->version & 0xFFF); | |
141 | PR_EEP("Checksum", pBase->checksum); | |
142 | PR_EEP("Length", pBase->length); | |
143 | PR_EEP("RegDomain1", pBase->regDmn[0]); | |
144 | PR_EEP("RegDomain2", pBase->regDmn[1]); | |
145 | PR_EEP("TX Mask", pBase->txMask); | |
146 | PR_EEP("RX Mask", pBase->rxMask); | |
147 | PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A)); | |
148 | PR_EEP("Allow 2GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11G)); | |
149 | PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags & | |
150 | AR5416_OPFLAGS_N_2G_HT20)); | |
151 | PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags & | |
152 | AR5416_OPFLAGS_N_2G_HT40)); | |
153 | PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags & | |
154 | AR5416_OPFLAGS_N_5G_HT20)); | |
155 | PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags & | |
156 | AR5416_OPFLAGS_N_5G_HT40)); | |
157 | PR_EEP("Big Endian", !!(pBase->eepMisc & 0x01)); | |
158 | PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF); | |
159 | PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF); | |
160 | PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF); | |
161 | PR_EEP("TX Gain type", pBase->txGainType); | |
162 | ||
163 | len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress", | |
164 | pBase->macAddr); | |
165 | ||
166 | out: | |
167 | if (len > size) | |
168 | len = size; | |
169 | ||
170 | return len; | |
171 | } | |
172 | #else | |
173 | static u32 ath9k_hw_4k_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, | |
174 | u8 *buf, u32 len, u32 size) | |
175 | { | |
176 | return 0; | |
177 | } | |
178 | #endif | |
179 | ||
180 | ||
04cf53f4 SM |
181 | #undef SIZE_EEPROM_4K |
182 | ||
b5aec950 S |
183 | static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah) |
184 | { | |
185 | #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16)) | |
c46917bb | 186 | struct ath_common *common = ath9k_hw_common(ah); |
2c208890 | 187 | struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; |
b5aec950 S |
188 | u16 *eepdata, temp, magic, magic2; |
189 | u32 sum = 0, el; | |
190 | bool need_swap = false; | |
191 | int i, addr; | |
192 | ||
193 | ||
194 | if (!ath9k_hw_use_flash(ah)) { | |
0e4b9f2f | 195 | if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, |
b5aec950 | 196 | &magic)) { |
3800276a | 197 | ath_err(common, "Reading Magic # failed\n"); |
b5aec950 S |
198 | return false; |
199 | } | |
200 | ||
d2182b69 | 201 | ath_dbg(common, EEPROM, "Read Magic = 0x%04X\n", magic); |
b5aec950 S |
202 | |
203 | if (magic != AR5416_EEPROM_MAGIC) { | |
204 | magic2 = swab16(magic); | |
205 | ||
206 | if (magic2 == AR5416_EEPROM_MAGIC) { | |
207 | need_swap = true; | |
208 | eepdata = (u16 *) (&ah->eeprom); | |
209 | ||
210 | for (addr = 0; addr < EEPROM_4K_SIZE; addr++) { | |
211 | temp = swab16(*eepdata); | |
212 | *eepdata = temp; | |
213 | eepdata++; | |
214 | } | |
215 | } else { | |
3800276a | 216 | ath_err(common, |
226afe68 | 217 | "Invalid EEPROM Magic. Endianness mismatch.\n"); |
b5aec950 S |
218 | return -EINVAL; |
219 | } | |
220 | } | |
221 | } | |
222 | ||
d2182b69 | 223 | ath_dbg(common, EEPROM, "need_swap = %s\n", |
226afe68 | 224 | need_swap ? "True" : "False"); |
b5aec950 S |
225 | |
226 | if (need_swap) | |
227 | el = swab16(ah->eeprom.map4k.baseEepHeader.length); | |
228 | else | |
229 | el = ah->eeprom.map4k.baseEepHeader.length; | |
230 | ||
231 | if (el > sizeof(struct ar5416_eeprom_4k)) | |
232 | el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16); | |
233 | else | |
234 | el = el / sizeof(u16); | |
235 | ||
236 | eepdata = (u16 *)(&ah->eeprom); | |
237 | ||
238 | for (i = 0; i < el; i++) | |
239 | sum ^= *eepdata++; | |
240 | ||
241 | if (need_swap) { | |
242 | u32 integer; | |
243 | u16 word; | |
244 | ||
d2182b69 | 245 | ath_dbg(common, EEPROM, |
226afe68 | 246 | "EEPROM Endianness is not native.. Changing\n"); |
b5aec950 S |
247 | |
248 | word = swab16(eep->baseEepHeader.length); | |
249 | eep->baseEepHeader.length = word; | |
250 | ||
251 | word = swab16(eep->baseEepHeader.checksum); | |
252 | eep->baseEepHeader.checksum = word; | |
253 | ||
254 | word = swab16(eep->baseEepHeader.version); | |
255 | eep->baseEepHeader.version = word; | |
256 | ||
257 | word = swab16(eep->baseEepHeader.regDmn[0]); | |
258 | eep->baseEepHeader.regDmn[0] = word; | |
259 | ||
260 | word = swab16(eep->baseEepHeader.regDmn[1]); | |
261 | eep->baseEepHeader.regDmn[1] = word; | |
262 | ||
263 | word = swab16(eep->baseEepHeader.rfSilent); | |
264 | eep->baseEepHeader.rfSilent = word; | |
265 | ||
266 | word = swab16(eep->baseEepHeader.blueToothOptions); | |
267 | eep->baseEepHeader.blueToothOptions = word; | |
268 | ||
269 | word = swab16(eep->baseEepHeader.deviceCap); | |
270 | eep->baseEepHeader.deviceCap = word; | |
271 | ||
272 | integer = swab32(eep->modalHeader.antCtrlCommon); | |
273 | eep->modalHeader.antCtrlCommon = integer; | |
274 | ||
275 | for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) { | |
276 | integer = swab32(eep->modalHeader.antCtrlChain[i]); | |
277 | eep->modalHeader.antCtrlChain[i] = integer; | |
278 | } | |
279 | ||
4ddfcd7d | 280 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
b5aec950 S |
281 | word = swab16(eep->modalHeader.spurChans[i].spurChan); |
282 | eep->modalHeader.spurChans[i].spurChan = word; | |
283 | } | |
284 | } | |
285 | ||
286 | if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || | |
287 | ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { | |
3800276a JP |
288 | ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n", |
289 | sum, ah->eep_ops->get_eeprom_ver(ah)); | |
b5aec950 S |
290 | return -EINVAL; |
291 | } | |
292 | ||
293 | return 0; | |
294 | #undef EEPROM_4K_SIZE | |
295 | } | |
296 | ||
297 | static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah, | |
298 | enum eeprom_param param) | |
299 | { | |
300 | struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; | |
301 | struct modal_eep_4k_header *pModal = &eep->modalHeader; | |
302 | struct base_eep_header_4k *pBase = &eep->baseEepHeader; | |
970bf9d4 GJ |
303 | u16 ver_minor; |
304 | ||
305 | ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK; | |
b5aec950 S |
306 | |
307 | switch (param) { | |
308 | case EEP_NFTHRESH_2: | |
309 | return pModal->noiseFloorThreshCh[0]; | |
49101676 | 310 | case EEP_MAC_LSW: |
78fa99ab | 311 | return get_unaligned_be16(pBase->macAddr); |
49101676 | 312 | case EEP_MAC_MID: |
78fa99ab | 313 | return get_unaligned_be16(pBase->macAddr + 2); |
49101676 | 314 | case EEP_MAC_MSW: |
78fa99ab | 315 | return get_unaligned_be16(pBase->macAddr + 4); |
b5aec950 S |
316 | case EEP_REG_0: |
317 | return pBase->regDmn[0]; | |
b5aec950 S |
318 | case EEP_OP_CAP: |
319 | return pBase->deviceCap; | |
320 | case EEP_OP_MODE: | |
321 | return pBase->opCapFlags; | |
322 | case EEP_RF_SILENT: | |
323 | return pBase->rfSilent; | |
324 | case EEP_OB_2: | |
7f63845f | 325 | return pModal->ob_0; |
b5aec950 | 326 | case EEP_DB_2: |
7f63845f | 327 | return pModal->db1_1; |
b5aec950 | 328 | case EEP_MINOR_REV: |
970bf9d4 | 329 | return ver_minor; |
b5aec950 S |
330 | case EEP_TX_MASK: |
331 | return pBase->txMask; | |
332 | case EEP_RX_MASK: | |
333 | return pBase->rxMask; | |
334 | case EEP_FRAC_N_5G: | |
335 | return 0; | |
e41f0bfc SB |
336 | case EEP_PWR_TABLE_OFFSET: |
337 | return AR5416_PWR_TABLE_OFFSET_DB; | |
754dc536 VT |
338 | case EEP_MODAL_VER: |
339 | return pModal->version; | |
340 | case EEP_ANT_DIV_CTL1: | |
341 | return pModal->antdiv_ctl1; | |
970bf9d4 | 342 | case EEP_TXGAIN_TYPE: |
f3d4505d | 343 | return pBase->txGainType; |
ca2c68cc FF |
344 | case EEP_ANTENNA_GAIN_2G: |
345 | return pModal->antennaGainCh[0]; | |
b5aec950 S |
346 | default: |
347 | return 0; | |
348 | } | |
349 | } | |
350 | ||
b5aec950 | 351 | static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah, |
e832bf10 | 352 | struct ath9k_channel *chan) |
b5aec950 | 353 | { |
c46917bb | 354 | struct ath_common *common = ath9k_hw_common(ah); |
b5aec950 S |
355 | struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; |
356 | struct cal_data_per_freq_4k *pRawDataset; | |
357 | u8 *pCalBChans = NULL; | |
358 | u16 pdGainOverlap_t2; | |
359 | static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; | |
4ddfcd7d | 360 | u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; |
b5aec950 | 361 | u16 numPiers, i, j; |
b5aec950 S |
362 | u16 numXpdGain, xpdMask; |
363 | u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 }; | |
364 | u32 reg32, regOffset, regChainOffset; | |
365 | ||
366 | xpdMask = pEepData->modalHeader.xpdGain; | |
367 | ||
368 | if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
369 | AR5416_EEP_MINOR_VER_2) { | |
370 | pdGainOverlap_t2 = | |
371 | pEepData->modalHeader.pdGainOverlap; | |
372 | } else { | |
373 | pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), | |
374 | AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); | |
375 | } | |
376 | ||
377 | pCalBChans = pEepData->calFreqPier2G; | |
378 | numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS; | |
379 | ||
380 | numXpdGain = 0; | |
381 | ||
4ddfcd7d FF |
382 | for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { |
383 | if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { | |
b5aec950 S |
384 | if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS) |
385 | break; | |
386 | xpdGainValues[numXpdGain] = | |
4ddfcd7d | 387 | (u16)(AR5416_PD_GAINS_IN_MASK - i); |
b5aec950 S |
388 | numXpdGain++; |
389 | } | |
390 | } | |
391 | ||
392 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, | |
393 | (numXpdGain - 1) & 0x3); | |
394 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, | |
395 | xpdGainValues[0]); | |
396 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, | |
397 | xpdGainValues[1]); | |
398 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0); | |
399 | ||
400 | for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) { | |
1b8714f7 | 401 | regChainOffset = i * 0x1000; |
b5aec950 S |
402 | |
403 | if (pEepData->baseEepHeader.txMask & (1 << i)) { | |
404 | pRawDataset = pEepData->calPierData2G[i]; | |
405 | ||
115277a3 | 406 | ath9k_hw_get_gain_boundaries_pdadcs(ah, chan, |
b5aec950 S |
407 | pRawDataset, pCalBChans, |
408 | numPiers, pdGainOverlap_t2, | |
6eb90d46 | 409 | gainBoundaries, |
b5aec950 S |
410 | pdadcValues, numXpdGain); |
411 | ||
7d0d0df0 S |
412 | ENABLE_REGWRITE_BUFFER(ah); |
413 | ||
1b8714f7 FF |
414 | REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, |
415 | SM(pdGainOverlap_t2, | |
416 | AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | |
417 | | SM(gainBoundaries[0], | |
418 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | |
419 | | SM(gainBoundaries[1], | |
420 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | |
421 | | SM(gainBoundaries[2], | |
422 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | |
423 | | SM(gainBoundaries[3], | |
424 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); | |
b5aec950 S |
425 | |
426 | regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; | |
427 | for (j = 0; j < 32; j++) { | |
78fa99ab | 428 | reg32 = get_unaligned_le32(&pdadcValues[4 * j]); |
b5aec950 S |
429 | REG_WRITE(ah, regOffset, reg32); |
430 | ||
d2182b69 | 431 | ath_dbg(common, EEPROM, |
226afe68 JP |
432 | "PDADC (%d,%4x): %4.4x %8.8x\n", |
433 | i, regChainOffset, regOffset, | |
434 | reg32); | |
d2182b69 | 435 | ath_dbg(common, EEPROM, |
226afe68 JP |
436 | "PDADC: Chain %d | " |
437 | "PDADC %3d Value %3d | " | |
438 | "PDADC %3d Value %3d | " | |
439 | "PDADC %3d Value %3d | " | |
440 | "PDADC %3d Value %3d |\n", | |
441 | i, 4 * j, pdadcValues[4 * j], | |
442 | 4 * j + 1, pdadcValues[4 * j + 1], | |
443 | 4 * j + 2, pdadcValues[4 * j + 2], | |
444 | 4 * j + 3, pdadcValues[4 * j + 3]); | |
b5aec950 S |
445 | |
446 | regOffset += 4; | |
447 | } | |
7d0d0df0 S |
448 | |
449 | REGWRITE_BUFFER_FLUSH(ah); | |
b5aec950 S |
450 | } |
451 | } | |
b5aec950 S |
452 | } |
453 | ||
454 | static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, | |
455 | struct ath9k_channel *chan, | |
456 | int16_t *ratesArray, | |
457 | u16 cfgCtl, | |
ca2c68cc | 458 | u16 antenna_reduction, |
b5aec950 S |
459 | u16 powerLimit) |
460 | { | |
180d674b S |
461 | #define CMP_TEST_GRP \ |
462 | (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) == \ | |
463 | pEepData->ctlIndex[i]) \ | |
464 | || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \ | |
465 | ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL)) | |
b5aec950 S |
466 | |
467 | int i; | |
180d674b | 468 | u16 twiceMinEdgePower; |
a261f0e9 | 469 | u16 twiceMaxEdgePower; |
ca2c68cc | 470 | u16 scaledPower = 0, minCtlPower; |
07b2fa5a JP |
471 | u16 numCtlModes; |
472 | const u16 *pCtlMode; | |
473 | u16 ctlMode, freq; | |
180d674b | 474 | struct chan_centers centers; |
b5aec950 | 475 | struct cal_ctl_data_4k *rep; |
180d674b | 476 | struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; |
b5aec950 S |
477 | struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { |
478 | 0, { 0, 0, 0, 0} | |
479 | }; | |
480 | struct cal_target_power_leg targetPowerOfdmExt = { | |
481 | 0, { 0, 0, 0, 0} }, targetPowerCckExt = { | |
482 | 0, { 0, 0, 0, 0 } | |
483 | }; | |
484 | struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { | |
485 | 0, {0, 0, 0, 0} | |
486 | }; | |
07b2fa5a JP |
487 | static const u16 ctlModesFor11g[] = { |
488 | CTL_11B, CTL_11G, CTL_2GHT20, | |
489 | CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 | |
490 | }; | |
b5aec950 S |
491 | |
492 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
493 | ||
ca2c68cc | 494 | scaledPower = powerLimit - antenna_reduction; |
b5aec950 S |
495 | numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; |
496 | pCtlMode = ctlModesFor11g; | |
497 | ||
498 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
499 | pEepData->calTargetPowerCck, | |
500 | AR5416_NUM_2G_CCK_TARGET_POWERS, | |
501 | &targetPowerCck, 4, false); | |
502 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
503 | pEepData->calTargetPower2G, | |
504 | AR5416_NUM_2G_20_TARGET_POWERS, | |
505 | &targetPowerOfdm, 4, false); | |
506 | ath9k_hw_get_target_powers(ah, chan, | |
507 | pEepData->calTargetPower2GHT20, | |
508 | AR5416_NUM_2G_20_TARGET_POWERS, | |
509 | &targetPowerHt20, 8, false); | |
510 | ||
511 | if (IS_CHAN_HT40(chan)) { | |
512 | numCtlModes = ARRAY_SIZE(ctlModesFor11g); | |
513 | ath9k_hw_get_target_powers(ah, chan, | |
514 | pEepData->calTargetPower2GHT40, | |
515 | AR5416_NUM_2G_40_TARGET_POWERS, | |
516 | &targetPowerHt40, 8, true); | |
517 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
518 | pEepData->calTargetPowerCck, | |
519 | AR5416_NUM_2G_CCK_TARGET_POWERS, | |
520 | &targetPowerCckExt, 4, true); | |
521 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
522 | pEepData->calTargetPower2G, | |
523 | AR5416_NUM_2G_20_TARGET_POWERS, | |
524 | &targetPowerOfdmExt, 4, true); | |
525 | } | |
526 | ||
527 | for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { | |
528 | bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || | |
529 | (pCtlMode[ctlMode] == CTL_2GHT40); | |
180d674b | 530 | |
b5aec950 S |
531 | if (isHt40CtlMode) |
532 | freq = centers.synth_center; | |
533 | else if (pCtlMode[ctlMode] & EXT_ADDITIVE) | |
534 | freq = centers.ext_center; | |
535 | else | |
536 | freq = centers.ctl_center; | |
537 | ||
a261f0e9 | 538 | twiceMaxEdgePower = MAX_RATE_POWER; |
b5aec950 S |
539 | |
540 | for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) && | |
180d674b S |
541 | pEepData->ctlIndex[i]; i++) { |
542 | ||
543 | if (CMP_TEST_GRP) { | |
b5aec950 S |
544 | rep = &(pEepData->ctlData[i]); |
545 | ||
180d674b S |
546 | twiceMinEdgePower = ath9k_hw_get_max_edge_power( |
547 | freq, | |
548 | rep->ctlEdges[ | |
549 | ar5416_get_ntxchains(ah->txchainmask) - 1], | |
550 | IS_CHAN_2GHZ(chan), | |
551 | AR5416_EEP4K_NUM_BAND_EDGES); | |
b5aec950 S |
552 | |
553 | if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { | |
554 | twiceMaxEdgePower = | |
555 | min(twiceMaxEdgePower, | |
556 | twiceMinEdgePower); | |
557 | } else { | |
558 | twiceMaxEdgePower = twiceMinEdgePower; | |
559 | break; | |
560 | } | |
561 | } | |
562 | } | |
563 | ||
564 | minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); | |
565 | ||
566 | switch (pCtlMode[ctlMode]) { | |
567 | case CTL_11B: | |
180d674b | 568 | for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) { |
b5aec950 S |
569 | targetPowerCck.tPow2x[i] = |
570 | min((u16)targetPowerCck.tPow2x[i], | |
571 | minCtlPower); | |
572 | } | |
573 | break; | |
574 | case CTL_11G: | |
180d674b | 575 | for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) { |
b5aec950 S |
576 | targetPowerOfdm.tPow2x[i] = |
577 | min((u16)targetPowerOfdm.tPow2x[i], | |
578 | minCtlPower); | |
579 | } | |
580 | break; | |
581 | case CTL_2GHT20: | |
180d674b | 582 | for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) { |
b5aec950 S |
583 | targetPowerHt20.tPow2x[i] = |
584 | min((u16)targetPowerHt20.tPow2x[i], | |
585 | minCtlPower); | |
586 | } | |
587 | break; | |
588 | case CTL_11B_EXT: | |
180d674b S |
589 | targetPowerCckExt.tPow2x[0] = |
590 | min((u16)targetPowerCckExt.tPow2x[0], | |
591 | minCtlPower); | |
b5aec950 S |
592 | break; |
593 | case CTL_11G_EXT: | |
180d674b S |
594 | targetPowerOfdmExt.tPow2x[0] = |
595 | min((u16)targetPowerOfdmExt.tPow2x[0], | |
596 | minCtlPower); | |
b5aec950 S |
597 | break; |
598 | case CTL_2GHT40: | |
180d674b | 599 | for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { |
b5aec950 S |
600 | targetPowerHt40.tPow2x[i] = |
601 | min((u16)targetPowerHt40.tPow2x[i], | |
602 | minCtlPower); | |
603 | } | |
604 | break; | |
605 | default: | |
606 | break; | |
607 | } | |
608 | } | |
609 | ||
180d674b S |
610 | ratesArray[rate6mb] = |
611 | ratesArray[rate9mb] = | |
612 | ratesArray[rate12mb] = | |
613 | ratesArray[rate18mb] = | |
614 | ratesArray[rate24mb] = | |
615 | targetPowerOfdm.tPow2x[0]; | |
616 | ||
b5aec950 S |
617 | ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; |
618 | ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; | |
619 | ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; | |
620 | ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; | |
621 | ||
622 | for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) | |
623 | ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; | |
624 | ||
625 | ratesArray[rate1l] = targetPowerCck.tPow2x[0]; | |
626 | ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1]; | |
627 | ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; | |
628 | ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3]; | |
629 | ||
630 | if (IS_CHAN_HT40(chan)) { | |
631 | for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { | |
632 | ratesArray[rateHt40_0 + i] = | |
633 | targetPowerHt40.tPow2x[i]; | |
634 | } | |
635 | ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; | |
636 | ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; | |
637 | ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; | |
638 | ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; | |
639 | } | |
180d674b S |
640 | |
641 | #undef CMP_TEST_GRP | |
b5aec950 S |
642 | } |
643 | ||
644 | static void ath9k_hw_4k_set_txpower(struct ath_hw *ah, | |
bf466fb6 S |
645 | struct ath9k_channel *chan, |
646 | u16 cfgCtl, | |
647 | u8 twiceAntennaReduction, | |
de40f316 | 648 | u8 powerLimit, bool test) |
b5aec950 | 649 | { |
608b88cb | 650 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
b5aec950 S |
651 | struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; |
652 | struct modal_eep_4k_header *pModal = &pEepData->modalHeader; | |
653 | int16_t ratesArray[Ar5416RateSize]; | |
b5aec950 S |
654 | u8 ht40PowerIncForPdadc = 2; |
655 | int i; | |
656 | ||
657 | memset(ratesArray, 0, sizeof(ratesArray)); | |
658 | ||
659 | if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
660 | AR5416_EEP_MINOR_VER_2) { | |
661 | ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; | |
662 | } | |
663 | ||
664 | ath9k_hw_set_4k_power_per_rate_table(ah, chan, | |
bf466fb6 S |
665 | &ratesArray[0], cfgCtl, |
666 | twiceAntennaReduction, | |
bf466fb6 | 667 | powerLimit); |
b5aec950 | 668 | |
e832bf10 | 669 | ath9k_hw_set_4k_power_cal_table(ah, chan); |
b5aec950 | 670 | |
de40f316 | 671 | regulatory->max_power_level = 0; |
b5aec950 | 672 | for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { |
4ddfcd7d FF |
673 | if (ratesArray[i] > MAX_RATE_POWER) |
674 | ratesArray[i] = MAX_RATE_POWER; | |
de40f316 FF |
675 | |
676 | if (ratesArray[i] > regulatory->max_power_level) | |
677 | regulatory->max_power_level = ratesArray[i]; | |
b5aec950 S |
678 | } |
679 | ||
de40f316 FF |
680 | if (test) |
681 | return; | |
bf466fb6 | 682 | |
1b8714f7 FF |
683 | for (i = 0; i < Ar5416RateSize; i++) |
684 | ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2; | |
b5aec950 | 685 | |
7d0d0df0 S |
686 | ENABLE_REGWRITE_BUFFER(ah); |
687 | ||
bf466fb6 | 688 | /* OFDM power per rate */ |
b5aec950 S |
689 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, |
690 | ATH9K_POW_SM(ratesArray[rate18mb], 24) | |
691 | | ATH9K_POW_SM(ratesArray[rate12mb], 16) | |
692 | | ATH9K_POW_SM(ratesArray[rate9mb], 8) | |
693 | | ATH9K_POW_SM(ratesArray[rate6mb], 0)); | |
694 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, | |
695 | ATH9K_POW_SM(ratesArray[rate54mb], 24) | |
696 | | ATH9K_POW_SM(ratesArray[rate48mb], 16) | |
697 | | ATH9K_POW_SM(ratesArray[rate36mb], 8) | |
698 | | ATH9K_POW_SM(ratesArray[rate24mb], 0)); | |
699 | ||
bf466fb6 S |
700 | /* CCK power per rate */ |
701 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, | |
702 | ATH9K_POW_SM(ratesArray[rate2s], 24) | |
703 | | ATH9K_POW_SM(ratesArray[rate2l], 16) | |
704 | | ATH9K_POW_SM(ratesArray[rateXr], 8) | |
705 | | ATH9K_POW_SM(ratesArray[rate1l], 0)); | |
706 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, | |
707 | ATH9K_POW_SM(ratesArray[rate11s], 24) | |
708 | | ATH9K_POW_SM(ratesArray[rate11l], 16) | |
709 | | ATH9K_POW_SM(ratesArray[rate5_5s], 8) | |
710 | | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); | |
711 | ||
712 | /* HT20 power per rate */ | |
b5aec950 S |
713 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, |
714 | ATH9K_POW_SM(ratesArray[rateHt20_3], 24) | |
715 | | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) | |
716 | | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) | |
717 | | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); | |
718 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, | |
719 | ATH9K_POW_SM(ratesArray[rateHt20_7], 24) | |
720 | | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) | |
721 | | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) | |
722 | | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); | |
723 | ||
bf466fb6 | 724 | /* HT40 power per rate */ |
b5aec950 S |
725 | if (IS_CHAN_HT40(chan)) { |
726 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, | |
727 | ATH9K_POW_SM(ratesArray[rateHt40_3] + | |
728 | ht40PowerIncForPdadc, 24) | |
729 | | ATH9K_POW_SM(ratesArray[rateHt40_2] + | |
730 | ht40PowerIncForPdadc, 16) | |
731 | | ATH9K_POW_SM(ratesArray[rateHt40_1] + | |
732 | ht40PowerIncForPdadc, 8) | |
733 | | ATH9K_POW_SM(ratesArray[rateHt40_0] + | |
734 | ht40PowerIncForPdadc, 0)); | |
735 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, | |
736 | ATH9K_POW_SM(ratesArray[rateHt40_7] + | |
737 | ht40PowerIncForPdadc, 24) | |
738 | | ATH9K_POW_SM(ratesArray[rateHt40_6] + | |
739 | ht40PowerIncForPdadc, 16) | |
740 | | ATH9K_POW_SM(ratesArray[rateHt40_5] + | |
741 | ht40PowerIncForPdadc, 8) | |
742 | | ATH9K_POW_SM(ratesArray[rateHt40_4] + | |
743 | ht40PowerIncForPdadc, 0)); | |
b5aec950 S |
744 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, |
745 | ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) | |
746 | | ATH9K_POW_SM(ratesArray[rateExtCck], 16) | |
747 | | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) | |
748 | | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); | |
749 | } | |
7d0d0df0 S |
750 | |
751 | REGWRITE_BUFFER_FLUSH(ah); | |
b5aec950 S |
752 | } |
753 | ||
b5aec950 S |
754 | static void ath9k_hw_4k_set_gain(struct ath_hw *ah, |
755 | struct modal_eep_4k_header *pModal, | |
756 | struct ar5416_eeprom_4k *eep, | |
a37414a2 | 757 | u8 txRxAttenLocal) |
b5aec950 | 758 | { |
a37414a2 | 759 | REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0, |
b5aec950 S |
760 | pModal->antCtrlChain[0]); |
761 | ||
a37414a2 S |
762 | REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), |
763 | (REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & | |
b5aec950 S |
764 | ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | |
765 | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | | |
766 | SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | | |
767 | SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); | |
768 | ||
769 | if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
770 | AR5416_EEP_MINOR_VER_3) { | |
771 | txRxAttenLocal = pModal->txRxAttenCh[0]; | |
772 | ||
a37414a2 | 773 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, |
b5aec950 | 774 | AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]); |
a37414a2 | 775 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, |
b5aec950 | 776 | AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); |
a37414a2 | 777 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, |
b5aec950 S |
778 | AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, |
779 | pModal->xatten2Margin[0]); | |
a37414a2 | 780 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, |
b5aec950 S |
781 | AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]); |
782 | ||
783 | /* Set the block 1 value to block 0 value */ | |
784 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, | |
785 | AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, | |
786 | pModal->bswMargin[0]); | |
787 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, | |
788 | AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]); | |
789 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, | |
790 | AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, | |
791 | pModal->xatten2Margin[0]); | |
792 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000, | |
793 | AR_PHY_GAIN_2GHZ_XATTEN2_DB, | |
794 | pModal->xatten2Db[0]); | |
795 | } | |
796 | ||
a37414a2 | 797 | REG_RMW_FIELD(ah, AR_PHY_RXGAIN, |
b5aec950 | 798 | AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); |
a37414a2 | 799 | REG_RMW_FIELD(ah, AR_PHY_RXGAIN, |
b5aec950 S |
800 | AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); |
801 | ||
802 | REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, | |
803 | AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal); | |
804 | REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000, | |
805 | AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]); | |
b5aec950 S |
806 | } |
807 | ||
808 | /* | |
809 | * Read EEPROM header info and program the device for correct operation | |
810 | * given the channel value. | |
811 | */ | |
812 | static void ath9k_hw_4k_set_board_values(struct ath_hw *ah, | |
813 | struct ath9k_channel *chan) | |
814 | { | |
815 | struct modal_eep_4k_header *pModal; | |
816 | struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k; | |
d88525e8 | 817 | struct base_eep_header_4k *pBase = &eep->baseEepHeader; |
b5aec950 S |
818 | u8 txRxAttenLocal; |
819 | u8 ob[5], db1[5], db2[5]; | |
820 | u8 ant_div_control1, ant_div_control2; | |
1b8714f7 | 821 | u8 bb_desired_scale; |
b5aec950 S |
822 | u32 regVal; |
823 | ||
824 | pModal = &eep->modalHeader; | |
825 | txRxAttenLocal = 23; | |
826 | ||
df3c8b2b | 827 | REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); |
b5aec950 S |
828 | |
829 | /* Single chain for 4K EEPROM*/ | |
a37414a2 | 830 | ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal); |
b5aec950 S |
831 | |
832 | /* Initialize Ant Diversity settings from EEPROM */ | |
833 | if (pModal->version >= 3) { | |
7f63845f S |
834 | ant_div_control1 = pModal->antdiv_ctl1; |
835 | ant_div_control2 = pModal->antdiv_ctl2; | |
836 | ||
837 | regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); | |
838 | regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); | |
839 | ||
840 | regVal |= SM(ant_div_control1, | |
841 | AR_PHY_9285_ANT_DIV_CTL); | |
842 | regVal |= SM(ant_div_control2, | |
843 | AR_PHY_9285_ANT_DIV_ALT_LNACONF); | |
844 | regVal |= SM((ant_div_control2 >> 2), | |
845 | AR_PHY_9285_ANT_DIV_MAIN_LNACONF); | |
846 | regVal |= SM((ant_div_control1 >> 1), | |
847 | AR_PHY_9285_ANT_DIV_ALT_GAINTB); | |
848 | regVal |= SM((ant_div_control1 >> 2), | |
849 | AR_PHY_9285_ANT_DIV_MAIN_GAINTB); | |
850 | ||
851 | ||
852 | REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal); | |
853 | regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); | |
854 | regVal = REG_READ(ah, AR_PHY_CCK_DETECT); | |
855 | regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); | |
856 | regVal |= SM((ant_div_control1 >> 3), | |
857 | AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV); | |
858 | ||
859 | REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal); | |
860 | regVal = REG_READ(ah, AR_PHY_CCK_DETECT); | |
b5aec950 S |
861 | } |
862 | ||
863 | if (pModal->version >= 2) { | |
7f63845f S |
864 | ob[0] = pModal->ob_0; |
865 | ob[1] = pModal->ob_1; | |
866 | ob[2] = pModal->ob_2; | |
867 | ob[3] = pModal->ob_3; | |
868 | ob[4] = pModal->ob_4; | |
869 | ||
870 | db1[0] = pModal->db1_0; | |
871 | db1[1] = pModal->db1_1; | |
872 | db1[2] = pModal->db1_2; | |
873 | db1[3] = pModal->db1_3; | |
874 | db1[4] = pModal->db1_4; | |
875 | ||
876 | db2[0] = pModal->db2_0; | |
877 | db2[1] = pModal->db2_1; | |
878 | db2[2] = pModal->db2_2; | |
879 | db2[3] = pModal->db2_3; | |
880 | db2[4] = pModal->db2_4; | |
b5aec950 | 881 | } else if (pModal->version == 1) { |
7f63845f S |
882 | ob[0] = pModal->ob_0; |
883 | ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1; | |
884 | db1[0] = pModal->db1_0; | |
885 | db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1; | |
886 | db2[0] = pModal->db2_0; | |
887 | db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1; | |
b5aec950 S |
888 | } else { |
889 | int i; | |
7f63845f | 890 | |
b5aec950 | 891 | for (i = 0; i < 5; i++) { |
7f63845f S |
892 | ob[i] = pModal->ob_0; |
893 | db1[i] = pModal->db1_0; | |
894 | db2[i] = pModal->db1_0; | |
b5aec950 S |
895 | } |
896 | } | |
897 | ||
898 | if (AR_SREV_9271(ah)) { | |
899 | ath9k_hw_analog_shift_rmw(ah, | |
900 | AR9285_AN_RF2G3, | |
901 | AR9271_AN_RF2G3_OB_cck, | |
902 | AR9271_AN_RF2G3_OB_cck_S, | |
903 | ob[0]); | |
904 | ath9k_hw_analog_shift_rmw(ah, | |
905 | AR9285_AN_RF2G3, | |
906 | AR9271_AN_RF2G3_OB_psk, | |
907 | AR9271_AN_RF2G3_OB_psk_S, | |
908 | ob[1]); | |
909 | ath9k_hw_analog_shift_rmw(ah, | |
910 | AR9285_AN_RF2G3, | |
911 | AR9271_AN_RF2G3_OB_qam, | |
912 | AR9271_AN_RF2G3_OB_qam_S, | |
913 | ob[2]); | |
914 | ath9k_hw_analog_shift_rmw(ah, | |
915 | AR9285_AN_RF2G3, | |
916 | AR9271_AN_RF2G3_DB_1, | |
917 | AR9271_AN_RF2G3_DB_1_S, | |
918 | db1[0]); | |
919 | ath9k_hw_analog_shift_rmw(ah, | |
920 | AR9285_AN_RF2G4, | |
921 | AR9271_AN_RF2G4_DB_2, | |
922 | AR9271_AN_RF2G4_DB_2_S, | |
923 | db2[0]); | |
924 | } else { | |
925 | ath9k_hw_analog_shift_rmw(ah, | |
926 | AR9285_AN_RF2G3, | |
927 | AR9285_AN_RF2G3_OB_0, | |
928 | AR9285_AN_RF2G3_OB_0_S, | |
929 | ob[0]); | |
930 | ath9k_hw_analog_shift_rmw(ah, | |
931 | AR9285_AN_RF2G3, | |
932 | AR9285_AN_RF2G3_OB_1, | |
933 | AR9285_AN_RF2G3_OB_1_S, | |
934 | ob[1]); | |
935 | ath9k_hw_analog_shift_rmw(ah, | |
936 | AR9285_AN_RF2G3, | |
937 | AR9285_AN_RF2G3_OB_2, | |
938 | AR9285_AN_RF2G3_OB_2_S, | |
939 | ob[2]); | |
940 | ath9k_hw_analog_shift_rmw(ah, | |
941 | AR9285_AN_RF2G3, | |
942 | AR9285_AN_RF2G3_OB_3, | |
943 | AR9285_AN_RF2G3_OB_3_S, | |
944 | ob[3]); | |
945 | ath9k_hw_analog_shift_rmw(ah, | |
946 | AR9285_AN_RF2G3, | |
947 | AR9285_AN_RF2G3_OB_4, | |
948 | AR9285_AN_RF2G3_OB_4_S, | |
949 | ob[4]); | |
950 | ||
951 | ath9k_hw_analog_shift_rmw(ah, | |
952 | AR9285_AN_RF2G3, | |
953 | AR9285_AN_RF2G3_DB1_0, | |
954 | AR9285_AN_RF2G3_DB1_0_S, | |
955 | db1[0]); | |
956 | ath9k_hw_analog_shift_rmw(ah, | |
957 | AR9285_AN_RF2G3, | |
958 | AR9285_AN_RF2G3_DB1_1, | |
959 | AR9285_AN_RF2G3_DB1_1_S, | |
960 | db1[1]); | |
961 | ath9k_hw_analog_shift_rmw(ah, | |
962 | AR9285_AN_RF2G3, | |
963 | AR9285_AN_RF2G3_DB1_2, | |
964 | AR9285_AN_RF2G3_DB1_2_S, | |
965 | db1[2]); | |
966 | ath9k_hw_analog_shift_rmw(ah, | |
967 | AR9285_AN_RF2G4, | |
968 | AR9285_AN_RF2G4_DB1_3, | |
969 | AR9285_AN_RF2G4_DB1_3_S, | |
970 | db1[3]); | |
971 | ath9k_hw_analog_shift_rmw(ah, | |
972 | AR9285_AN_RF2G4, | |
973 | AR9285_AN_RF2G4_DB1_4, | |
974 | AR9285_AN_RF2G4_DB1_4_S, db1[4]); | |
975 | ||
976 | ath9k_hw_analog_shift_rmw(ah, | |
977 | AR9285_AN_RF2G4, | |
978 | AR9285_AN_RF2G4_DB2_0, | |
979 | AR9285_AN_RF2G4_DB2_0_S, | |
980 | db2[0]); | |
981 | ath9k_hw_analog_shift_rmw(ah, | |
982 | AR9285_AN_RF2G4, | |
983 | AR9285_AN_RF2G4_DB2_1, | |
984 | AR9285_AN_RF2G4_DB2_1_S, | |
985 | db2[1]); | |
986 | ath9k_hw_analog_shift_rmw(ah, | |
987 | AR9285_AN_RF2G4, | |
988 | AR9285_AN_RF2G4_DB2_2, | |
989 | AR9285_AN_RF2G4_DB2_2_S, | |
990 | db2[2]); | |
991 | ath9k_hw_analog_shift_rmw(ah, | |
992 | AR9285_AN_RF2G4, | |
993 | AR9285_AN_RF2G4_DB2_3, | |
994 | AR9285_AN_RF2G4_DB2_3_S, | |
995 | db2[3]); | |
996 | ath9k_hw_analog_shift_rmw(ah, | |
997 | AR9285_AN_RF2G4, | |
998 | AR9285_AN_RF2G4_DB2_4, | |
999 | AR9285_AN_RF2G4_DB2_4_S, | |
1000 | db2[4]); | |
1001 | } | |
1002 | ||
1003 | ||
b5aec950 S |
1004 | REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, |
1005 | pModal->switchSettling); | |
1006 | REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, | |
1007 | pModal->adcDesiredSize); | |
1008 | ||
1009 | REG_WRITE(ah, AR_PHY_RF_CTL4, | |
1010 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | | |
1011 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | | |
1012 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) | | |
1013 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); | |
1014 | ||
1015 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, | |
1016 | pModal->txEndToRxOn); | |
0cab6559 LR |
1017 | |
1018 | if (AR_SREV_9271_10(ah)) | |
1019 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, | |
1020 | pModal->txEndToRxOn); | |
b5aec950 S |
1021 | REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, |
1022 | pModal->thresh62); | |
1023 | REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, | |
1024 | pModal->thresh62); | |
1025 | ||
1026 | if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
1027 | AR5416_EEP_MINOR_VER_2) { | |
1028 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START, | |
1029 | pModal->txFrameToDataStart); | |
1030 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON, | |
1031 | pModal->txFrameToPaOn); | |
1032 | } | |
1033 | ||
1034 | if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
1035 | AR5416_EEP_MINOR_VER_3) { | |
1036 | if (IS_CHAN_HT40(chan)) | |
1037 | REG_RMW_FIELD(ah, AR_PHY_SETTLING, | |
1038 | AR_PHY_SETTLING_SWITCH, | |
1039 | pModal->swSettleHt40); | |
1040 | } | |
1b8714f7 FF |
1041 | |
1042 | bb_desired_scale = (pModal->bb_scale_smrt_antenna & | |
1043 | EEP_4K_BB_DESIRED_SCALE_MASK); | |
1044 | if ((pBase->txGainType == 0) && (bb_desired_scale != 0)) { | |
1045 | u32 pwrctrl, mask, clr; | |
1046 | ||
1047 | mask = BIT(0)|BIT(5)|BIT(10)|BIT(15)|BIT(20)|BIT(25); | |
1048 | pwrctrl = mask * bb_desired_scale; | |
1049 | clr = mask * 0x1f; | |
1050 | REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr); | |
1051 | REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr); | |
1052 | REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr); | |
1053 | ||
1054 | mask = BIT(0)|BIT(5)|BIT(15); | |
1055 | pwrctrl = mask * bb_desired_scale; | |
1056 | clr = mask * 0x1f; | |
1057 | REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr); | |
1058 | ||
1059 | mask = BIT(0)|BIT(5); | |
1060 | pwrctrl = mask * bb_desired_scale; | |
1061 | clr = mask * 0x1f; | |
1062 | REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr); | |
1063 | REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr); | |
d88525e8 | 1064 | } |
b5aec950 S |
1065 | } |
1066 | ||
b5aec950 S |
1067 | static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) |
1068 | { | |
1069 | #define EEP_MAP4K_SPURCHAN \ | |
1070 | (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan) | |
c46917bb | 1071 | struct ath_common *common = ath9k_hw_common(ah); |
b5aec950 S |
1072 | |
1073 | u16 spur_val = AR_NO_SPUR; | |
1074 | ||
d2182b69 | 1075 | ath_dbg(common, ANI, "Getting spur idx:%d is2Ghz:%d val:%x\n", |
226afe68 | 1076 | i, is2GHz, ah->config.spurchans[i][is2GHz]); |
b5aec950 S |
1077 | |
1078 | switch (ah->config.spurmode) { | |
1079 | case SPUR_DISABLE: | |
1080 | break; | |
1081 | case SPUR_ENABLE_IOCTL: | |
1082 | spur_val = ah->config.spurchans[i][is2GHz]; | |
d2182b69 JP |
1083 | ath_dbg(common, ANI, "Getting spur val from new loc. %d\n", |
1084 | spur_val); | |
b5aec950 S |
1085 | break; |
1086 | case SPUR_ENABLE_EEPROM: | |
1087 | spur_val = EEP_MAP4K_SPURCHAN; | |
1088 | break; | |
1089 | } | |
1090 | ||
1091 | return spur_val; | |
1092 | ||
1093 | #undef EEP_MAP4K_SPURCHAN | |
1094 | } | |
1095 | ||
1096 | const struct eeprom_ops eep_4k_ops = { | |
1097 | .check_eeprom = ath9k_hw_4k_check_eeprom, | |
1098 | .get_eeprom = ath9k_hw_4k_get_eeprom, | |
1099 | .fill_eeprom = ath9k_hw_4k_fill_eeprom, | |
4f011a2e | 1100 | .dump_eeprom = ath9k_hw_4k_dump_eeprom, |
b5aec950 S |
1101 | .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver, |
1102 | .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev, | |
b5aec950 | 1103 | .set_board_values = ath9k_hw_4k_set_board_values, |
b5aec950 S |
1104 | .set_txpower = ath9k_hw_4k_set_txpower, |
1105 | .get_spur_channel = ath9k_hw_4k_get_spur_channel | |
1106 | }; |