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b5aec950 S |
1 | /* |
2 | * Copyright (c) 2008-2009 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
c46917bb | 17 | #include "hw.h" |
8fe65368 | 18 | #include "ar9002_phy.h" |
b5aec950 S |
19 | |
20 | static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah) | |
21 | { | |
22 | return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF; | |
23 | } | |
24 | ||
25 | static int ath9k_hw_AR9287_get_eeprom_rev(struct ath_hw *ah) | |
26 | { | |
27 | return (ah->eeprom.map9287.baseEepHeader.version) & 0xFFF; | |
28 | } | |
29 | ||
30 | static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw *ah) | |
31 | { | |
32 | struct ar9287_eeprom *eep = &ah->eeprom.map9287; | |
c46917bb | 33 | struct ath_common *common = ath9k_hw_common(ah); |
b5aec950 S |
34 | u16 *eep_data; |
35 | int addr, eep_start_loc = AR9287_EEP_START_LOC; | |
36 | eep_data = (u16 *)eep; | |
37 | ||
38 | if (!ath9k_hw_use_flash(ah)) { | |
c46917bb LR |
39 | ath_print(common, ATH_DBG_EEPROM, |
40 | "Reading from EEPROM, not flash\n"); | |
b5aec950 S |
41 | } |
42 | ||
43 | for (addr = 0; addr < sizeof(struct ar9287_eeprom) / sizeof(u16); | |
44 | addr++) { | |
5bb12791 LR |
45 | if (!ath9k_hw_nvram_read(common, |
46 | addr + eep_start_loc, eep_data)) { | |
c46917bb | 47 | ath_print(common, ATH_DBG_EEPROM, |
60ece404 | 48 | "Unable to read eeprom region\n"); |
b5aec950 S |
49 | return false; |
50 | } | |
51 | eep_data++; | |
52 | } | |
53 | return true; | |
54 | } | |
55 | ||
56 | static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah) | |
57 | { | |
58 | u32 sum = 0, el, integer; | |
59 | u16 temp, word, magic, magic2, *eepdata; | |
60 | int i, addr; | |
61 | bool need_swap = false; | |
62 | struct ar9287_eeprom *eep = &ah->eeprom.map9287; | |
c46917bb | 63 | struct ath_common *common = ath9k_hw_common(ah); |
b5aec950 S |
64 | |
65 | if (!ath9k_hw_use_flash(ah)) { | |
5bb12791 LR |
66 | if (!ath9k_hw_nvram_read(common, |
67 | AR5416_EEPROM_MAGIC_OFFSET, &magic)) { | |
c46917bb LR |
68 | ath_print(common, ATH_DBG_FATAL, |
69 | "Reading Magic # failed\n"); | |
b5aec950 S |
70 | return false; |
71 | } | |
72 | ||
c46917bb LR |
73 | ath_print(common, ATH_DBG_EEPROM, |
74 | "Read Magic = 0x%04X\n", magic); | |
b5aec950 S |
75 | if (magic != AR5416_EEPROM_MAGIC) { |
76 | magic2 = swab16(magic); | |
77 | ||
78 | if (magic2 == AR5416_EEPROM_MAGIC) { | |
79 | need_swap = true; | |
80 | eepdata = (u16 *)(&ah->eeprom); | |
81 | ||
82 | for (addr = 0; | |
83 | addr < sizeof(struct ar9287_eeprom) / sizeof(u16); | |
84 | addr++) { | |
85 | temp = swab16(*eepdata); | |
86 | *eepdata = temp; | |
87 | eepdata++; | |
88 | } | |
89 | } else { | |
c46917bb LR |
90 | ath_print(common, ATH_DBG_FATAL, |
91 | "Invalid EEPROM Magic. " | |
92 | "endianness mismatch.\n"); | |
b5aec950 S |
93 | return -EINVAL; |
94 | } | |
95 | } | |
96 | } | |
c46917bb LR |
97 | ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n", need_swap ? |
98 | "True" : "False"); | |
b5aec950 S |
99 | |
100 | if (need_swap) | |
101 | el = swab16(ah->eeprom.map9287.baseEepHeader.length); | |
102 | else | |
103 | el = ah->eeprom.map9287.baseEepHeader.length; | |
104 | ||
105 | if (el > sizeof(struct ar9287_eeprom)) | |
106 | el = sizeof(struct ar9287_eeprom) / sizeof(u16); | |
107 | else | |
108 | el = el / sizeof(u16); | |
109 | ||
110 | eepdata = (u16 *)(&ah->eeprom); | |
111 | for (i = 0; i < el; i++) | |
112 | sum ^= *eepdata++; | |
113 | ||
114 | if (need_swap) { | |
115 | word = swab16(eep->baseEepHeader.length); | |
116 | eep->baseEepHeader.length = word; | |
117 | ||
118 | word = swab16(eep->baseEepHeader.checksum); | |
119 | eep->baseEepHeader.checksum = word; | |
120 | ||
121 | word = swab16(eep->baseEepHeader.version); | |
122 | eep->baseEepHeader.version = word; | |
123 | ||
124 | word = swab16(eep->baseEepHeader.regDmn[0]); | |
125 | eep->baseEepHeader.regDmn[0] = word; | |
126 | ||
127 | word = swab16(eep->baseEepHeader.regDmn[1]); | |
128 | eep->baseEepHeader.regDmn[1] = word; | |
129 | ||
130 | word = swab16(eep->baseEepHeader.rfSilent); | |
131 | eep->baseEepHeader.rfSilent = word; | |
132 | ||
133 | word = swab16(eep->baseEepHeader.blueToothOptions); | |
134 | eep->baseEepHeader.blueToothOptions = word; | |
135 | ||
136 | word = swab16(eep->baseEepHeader.deviceCap); | |
137 | eep->baseEepHeader.deviceCap = word; | |
138 | ||
139 | integer = swab32(eep->modalHeader.antCtrlCommon); | |
140 | eep->modalHeader.antCtrlCommon = integer; | |
141 | ||
142 | for (i = 0; i < AR9287_MAX_CHAINS; i++) { | |
143 | integer = swab32(eep->modalHeader.antCtrlChain[i]); | |
144 | eep->modalHeader.antCtrlChain[i] = integer; | |
145 | } | |
146 | ||
147 | for (i = 0; i < AR9287_EEPROM_MODAL_SPURS; i++) { | |
148 | word = swab16(eep->modalHeader.spurChans[i].spurChan); | |
149 | eep->modalHeader.spurChans[i].spurChan = word; | |
150 | } | |
151 | } | |
152 | ||
153 | if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER | |
154 | || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { | |
c46917bb LR |
155 | ath_print(common, ATH_DBG_FATAL, |
156 | "Bad EEPROM checksum 0x%x or revision 0x%04x\n", | |
157 | sum, ah->eep_ops->get_eeprom_ver(ah)); | |
b5aec950 S |
158 | return -EINVAL; |
159 | } | |
160 | ||
161 | return 0; | |
162 | } | |
163 | ||
164 | static u32 ath9k_hw_AR9287_get_eeprom(struct ath_hw *ah, | |
165 | enum eeprom_param param) | |
166 | { | |
167 | struct ar9287_eeprom *eep = &ah->eeprom.map9287; | |
168 | struct modal_eep_ar9287_header *pModal = &eep->modalHeader; | |
169 | struct base_eep_ar9287_header *pBase = &eep->baseEepHeader; | |
170 | u16 ver_minor; | |
171 | ||
172 | ver_minor = pBase->version & AR9287_EEP_VER_MINOR_MASK; | |
173 | switch (param) { | |
174 | case EEP_NFTHRESH_2: | |
175 | return pModal->noiseFloorThreshCh[0]; | |
176 | case AR_EEPROM_MAC(0): | |
177 | return pBase->macAddr[0] << 8 | pBase->macAddr[1]; | |
178 | case AR_EEPROM_MAC(1): | |
179 | return pBase->macAddr[2] << 8 | pBase->macAddr[3]; | |
180 | case AR_EEPROM_MAC(2): | |
181 | return pBase->macAddr[4] << 8 | pBase->macAddr[5]; | |
182 | case EEP_REG_0: | |
183 | return pBase->regDmn[0]; | |
184 | case EEP_REG_1: | |
185 | return pBase->regDmn[1]; | |
186 | case EEP_OP_CAP: | |
187 | return pBase->deviceCap; | |
188 | case EEP_OP_MODE: | |
189 | return pBase->opCapFlags; | |
190 | case EEP_RF_SILENT: | |
191 | return pBase->rfSilent; | |
192 | case EEP_MINOR_REV: | |
193 | return ver_minor; | |
194 | case EEP_TX_MASK: | |
195 | return pBase->txMask; | |
196 | case EEP_RX_MASK: | |
197 | return pBase->rxMask; | |
198 | case EEP_DEV_TYPE: | |
199 | return pBase->deviceType; | |
200 | case EEP_OL_PWRCTRL: | |
201 | return pBase->openLoopPwrCntl; | |
202 | case EEP_TEMPSENSE_SLOPE: | |
203 | if (ver_minor >= AR9287_EEP_MINOR_VER_2) | |
204 | return pBase->tempSensSlope; | |
205 | else | |
206 | return 0; | |
207 | case EEP_TEMPSENSE_SLOPE_PAL_ON: | |
208 | if (ver_minor >= AR9287_EEP_MINOR_VER_3) | |
209 | return pBase->tempSensSlopePalOn; | |
210 | else | |
211 | return 0; | |
212 | default: | |
213 | return 0; | |
214 | } | |
215 | } | |
216 | ||
217 | ||
218 | static void ath9k_hw_get_AR9287_gain_boundaries_pdadcs(struct ath_hw *ah, | |
219 | struct ath9k_channel *chan, | |
220 | struct cal_data_per_freq_ar9287 *pRawDataSet, | |
221 | u8 *bChans, u16 availPiers, | |
222 | u16 tPdGainOverlap, int16_t *pMinCalPower, | |
223 | u16 *pPdGainBoundaries, u8 *pPDADCValues, | |
224 | u16 numXpdGains) | |
225 | { | |
226 | #define TMP_VAL_VPD_TABLE \ | |
227 | ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep)); | |
228 | ||
229 | int i, j, k; | |
230 | int16_t ss; | |
231 | u16 idxL = 0, idxR = 0, numPiers; | |
232 | u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR; | |
233 | u8 minPwrT4[AR9287_NUM_PD_GAINS]; | |
234 | u8 maxPwrT4[AR9287_NUM_PD_GAINS]; | |
235 | int16_t vpdStep; | |
236 | int16_t tmpVal; | |
237 | u16 sizeCurrVpdTable, maxIndex, tgtIndex; | |
238 | bool match; | |
239 | int16_t minDelta = 0; | |
240 | struct chan_centers centers; | |
241 | static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS] | |
242 | [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; | |
243 | static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS] | |
244 | [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; | |
245 | static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS] | |
246 | [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; | |
247 | ||
248 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
249 | ||
250 | for (numPiers = 0; numPiers < availPiers; numPiers++) { | |
251 | if (bChans[numPiers] == AR9287_BCHAN_UNUSED) | |
252 | break; | |
253 | } | |
254 | ||
255 | match = ath9k_hw_get_lower_upper_index( | |
256 | (u8)FREQ2FBIN(centers.synth_center, | |
257 | IS_CHAN_2GHZ(chan)), bChans, numPiers, | |
258 | &idxL, &idxR); | |
259 | ||
260 | if (match) { | |
261 | for (i = 0; i < numXpdGains; i++) { | |
262 | minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; | |
263 | maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; | |
264 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | |
265 | pRawDataSet[idxL].pwrPdg[i], | |
266 | pRawDataSet[idxL].vpdPdg[i], | |
267 | AR9287_PD_GAIN_ICEPTS, vpdTableI[i]); | |
268 | } | |
269 | } else { | |
270 | for (i = 0; i < numXpdGains; i++) { | |
271 | pVpdL = pRawDataSet[idxL].vpdPdg[i]; | |
272 | pPwrL = pRawDataSet[idxL].pwrPdg[i]; | |
273 | pVpdR = pRawDataSet[idxR].vpdPdg[i]; | |
274 | pPwrR = pRawDataSet[idxR].pwrPdg[i]; | |
275 | ||
276 | minPwrT4[i] = max(pPwrL[0], pPwrR[0]); | |
277 | ||
278 | maxPwrT4[i] = | |
279 | min(pPwrL[AR9287_PD_GAIN_ICEPTS - 1], | |
280 | pPwrR[AR9287_PD_GAIN_ICEPTS - 1]); | |
281 | ||
282 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | |
283 | pPwrL, pVpdL, | |
284 | AR9287_PD_GAIN_ICEPTS, | |
285 | vpdTableL[i]); | |
286 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | |
287 | pPwrR, pVpdR, | |
288 | AR9287_PD_GAIN_ICEPTS, | |
289 | vpdTableR[i]); | |
290 | ||
291 | for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { | |
292 | vpdTableI[i][j] = | |
293 | (u8)(ath9k_hw_interpolate((u16) | |
294 | FREQ2FBIN(centers. synth_center, | |
295 | IS_CHAN_2GHZ(chan)), | |
296 | bChans[idxL], bChans[idxR], | |
297 | vpdTableL[i][j], vpdTableR[i][j])); | |
298 | } | |
299 | } | |
300 | } | |
301 | *pMinCalPower = (int16_t)(minPwrT4[0] / 2); | |
302 | ||
303 | k = 0; | |
304 | for (i = 0; i < numXpdGains; i++) { | |
305 | if (i == (numXpdGains - 1)) | |
306 | pPdGainBoundaries[i] = (u16)(maxPwrT4[i] / 2); | |
307 | else | |
308 | pPdGainBoundaries[i] = (u16)((maxPwrT4[i] + | |
309 | minPwrT4[i+1]) / 4); | |
310 | ||
311 | pPdGainBoundaries[i] = min((u16)AR5416_MAX_RATE_POWER, | |
312 | pPdGainBoundaries[i]); | |
313 | ||
314 | ||
315 | if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) { | |
316 | minDelta = pPdGainBoundaries[0] - 23; | |
317 | pPdGainBoundaries[0] = 23; | |
318 | } else | |
319 | minDelta = 0; | |
320 | ||
321 | if (i == 0) { | |
322 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
323 | ss = (int16_t)(0 - (minPwrT4[i] / 2)); | |
324 | else | |
325 | ss = 0; | |
326 | } else | |
327 | ss = (int16_t)((pPdGainBoundaries[i-1] - | |
328 | (minPwrT4[i] / 2)) - | |
329 | tPdGainOverlap + 1 + minDelta); | |
330 | ||
331 | vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); | |
332 | vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); | |
333 | while ((ss < 0) && (k < (AR9287_NUM_PDADC_VALUES - 1))) { | |
334 | tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); | |
335 | pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal); | |
336 | ss++; | |
337 | } | |
338 | ||
339 | sizeCurrVpdTable = (u8)((maxPwrT4[i] - minPwrT4[i]) / 2 + 1); | |
340 | tgtIndex = (u8)(pPdGainBoundaries[i] + | |
341 | tPdGainOverlap - (minPwrT4[i] / 2)); | |
342 | maxIndex = (tgtIndex < sizeCurrVpdTable) ? | |
343 | tgtIndex : sizeCurrVpdTable; | |
344 | ||
345 | while ((ss < maxIndex) && (k < (AR9287_NUM_PDADC_VALUES - 1))) | |
346 | pPDADCValues[k++] = vpdTableI[i][ss++]; | |
347 | ||
348 | vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - | |
349 | vpdTableI[i][sizeCurrVpdTable - 2]); | |
350 | vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); | |
351 | if (tgtIndex > maxIndex) { | |
352 | while ((ss <= tgtIndex) && | |
353 | (k < (AR9287_NUM_PDADC_VALUES - 1))) { | |
354 | tmpVal = (int16_t) TMP_VAL_VPD_TABLE; | |
355 | pPDADCValues[k++] = (u8)((tmpVal > 255) ? | |
356 | 255 : tmpVal); | |
357 | ss++; | |
358 | } | |
359 | } | |
360 | } | |
361 | ||
362 | while (i < AR9287_PD_GAINS_IN_MASK) { | |
363 | pPdGainBoundaries[i] = pPdGainBoundaries[i-1]; | |
364 | i++; | |
365 | } | |
366 | ||
367 | while (k < AR9287_NUM_PDADC_VALUES) { | |
368 | pPDADCValues[k] = pPDADCValues[k-1]; | |
369 | k++; | |
370 | } | |
371 | ||
372 | #undef TMP_VAL_VPD_TABLE | |
373 | } | |
374 | ||
375 | static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah, | |
376 | struct ath9k_channel *chan, | |
377 | struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop, | |
378 | u8 *pCalChans, u16 availPiers, | |
379 | int8_t *pPwr) | |
380 | { | |
b5aec950 S |
381 | u16 idxL = 0, idxR = 0, numPiers; |
382 | bool match; | |
383 | struct chan_centers centers; | |
384 | ||
385 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
386 | ||
387 | for (numPiers = 0; numPiers < availPiers; numPiers++) { | |
388 | if (pCalChans[numPiers] == AR9287_BCHAN_UNUSED) | |
389 | break; | |
390 | } | |
391 | ||
392 | match = ath9k_hw_get_lower_upper_index( | |
393 | (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)), | |
394 | pCalChans, numPiers, | |
395 | &idxL, &idxR); | |
396 | ||
397 | if (match) { | |
d4fe5afa | 398 | *pPwr = (int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0]; |
b5aec950 | 399 | } else { |
d4fe5afa VN |
400 | *pPwr = ((int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0] + |
401 | (int8_t) pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2; | |
b5aec950 S |
402 | } |
403 | ||
b5aec950 S |
404 | } |
405 | ||
406 | static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah, | |
407 | int32_t txPower, u16 chain) | |
408 | { | |
409 | u32 tmpVal; | |
410 | u32 a; | |
411 | ||
412 | tmpVal = REG_READ(ah, 0xa270); | |
413 | tmpVal = tmpVal & 0xFCFFFFFF; | |
414 | tmpVal = tmpVal | (0x3 << 24); | |
415 | REG_WRITE(ah, 0xa270, tmpVal); | |
416 | ||
417 | tmpVal = REG_READ(ah, 0xb270); | |
418 | tmpVal = tmpVal & 0xFCFFFFFF; | |
419 | tmpVal = tmpVal | (0x3 << 24); | |
420 | REG_WRITE(ah, 0xb270, tmpVal); | |
421 | ||
422 | if (chain == 0) { | |
423 | tmpVal = REG_READ(ah, 0xa398); | |
424 | tmpVal = tmpVal & 0xff00ffff; | |
425 | a = (txPower)&0xff; | |
426 | tmpVal = tmpVal | (a << 16); | |
427 | REG_WRITE(ah, 0xa398, tmpVal); | |
428 | } | |
429 | ||
430 | if (chain == 1) { | |
431 | tmpVal = REG_READ(ah, 0xb398); | |
432 | tmpVal = tmpVal & 0xff00ffff; | |
433 | a = (txPower)&0xff; | |
434 | tmpVal = tmpVal | (a << 16); | |
435 | REG_WRITE(ah, 0xb398, tmpVal); | |
436 | } | |
437 | } | |
438 | ||
439 | static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah, | |
440 | struct ath9k_channel *chan, | |
441 | int16_t *pTxPowerIndexOffset) | |
442 | { | |
c46917bb | 443 | struct ath_common *common = ath9k_hw_common(ah); |
b5aec950 S |
444 | struct cal_data_per_freq_ar9287 *pRawDataset; |
445 | struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop; | |
446 | u8 *pCalBChans = NULL; | |
447 | u16 pdGainOverlap_t2; | |
448 | u8 pdadcValues[AR9287_NUM_PDADC_VALUES]; | |
449 | u16 gainBoundaries[AR9287_PD_GAINS_IN_MASK]; | |
450 | u16 numPiers = 0, i, j; | |
451 | int16_t tMinCalPower; | |
452 | u16 numXpdGain, xpdMask; | |
453 | u16 xpdGainValues[AR9287_NUM_PD_GAINS] = {0, 0, 0, 0}; | |
454 | u32 reg32, regOffset, regChainOffset; | |
455 | int16_t modalIdx, diff = 0; | |
456 | struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; | |
457 | modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0; | |
458 | xpdMask = pEepData->modalHeader.xpdGain; | |
459 | if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >= | |
460 | AR9287_EEP_MINOR_VER_2) | |
461 | pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap; | |
462 | else | |
463 | pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), | |
464 | AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); | |
465 | ||
466 | if (IS_CHAN_2GHZ(chan)) { | |
467 | pCalBChans = pEepData->calFreqPier2G; | |
468 | numPiers = AR9287_NUM_2G_CAL_PIERS; | |
469 | if (ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { | |
470 | pRawDatasetOpenLoop = | |
471 | (struct cal_data_op_loop_ar9287 *) | |
472 | pEepData->calPierData2G[0]; | |
473 | ah->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0]; | |
474 | } | |
475 | } | |
476 | ||
477 | numXpdGain = 0; | |
478 | for (i = 1; i <= AR9287_PD_GAINS_IN_MASK; i++) { | |
479 | if ((xpdMask >> (AR9287_PD_GAINS_IN_MASK - i)) & 1) { | |
480 | if (numXpdGain >= AR9287_NUM_PD_GAINS) | |
481 | break; | |
482 | xpdGainValues[numXpdGain] = | |
483 | (u16)(AR9287_PD_GAINS_IN_MASK-i); | |
484 | numXpdGain++; | |
485 | } | |
486 | } | |
487 | ||
488 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, | |
489 | (numXpdGain - 1) & 0x3); | |
490 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, | |
491 | xpdGainValues[0]); | |
492 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, | |
493 | xpdGainValues[1]); | |
494 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, | |
495 | xpdGainValues[2]); | |
496 | ||
497 | for (i = 0; i < AR9287_MAX_CHAINS; i++) { | |
498 | regChainOffset = i * 0x1000; | |
499 | if (pEepData->baseEepHeader.txMask & (1 << i)) { | |
500 | pRawDatasetOpenLoop = (struct cal_data_op_loop_ar9287 *) | |
501 | pEepData->calPierData2G[i]; | |
502 | if (ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { | |
503 | int8_t txPower; | |
504 | ar9287_eeprom_get_tx_gain_index(ah, chan, | |
505 | pRawDatasetOpenLoop, | |
506 | pCalBChans, numPiers, | |
507 | &txPower); | |
508 | ar9287_eeprom_olpc_set_pdadcs(ah, txPower, i); | |
509 | } else { | |
510 | pRawDataset = | |
511 | (struct cal_data_per_freq_ar9287 *) | |
512 | pEepData->calPierData2G[i]; | |
513 | ath9k_hw_get_AR9287_gain_boundaries_pdadcs( | |
514 | ah, chan, pRawDataset, | |
515 | pCalBChans, numPiers, | |
516 | pdGainOverlap_t2, | |
517 | &tMinCalPower, gainBoundaries, | |
518 | pdadcValues, numXpdGain); | |
519 | } | |
520 | ||
521 | if (i == 0) { | |
522 | if (!ath9k_hw_AR9287_get_eeprom( | |
523 | ah, EEP_OL_PWRCTRL)) { | |
524 | REG_WRITE(ah, AR_PHY_TPCRG5 + | |
525 | regChainOffset, | |
526 | SM(pdGainOverlap_t2, | |
527 | AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | | |
528 | SM(gainBoundaries[0], | |
529 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | |
530 | | SM(gainBoundaries[1], | |
531 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | |
532 | | SM(gainBoundaries[2], | |
533 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | |
534 | | SM(gainBoundaries[3], | |
535 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); | |
536 | } | |
537 | } | |
538 | ||
539 | if ((int32_t)AR9287_PWR_TABLE_OFFSET_DB != | |
540 | pEepData->baseEepHeader.pwrTableOffset) { | |
541 | diff = (u16) | |
542 | (pEepData->baseEepHeader.pwrTableOffset | |
543 | - (int32_t)AR9287_PWR_TABLE_OFFSET_DB); | |
544 | diff *= 2; | |
545 | ||
546 | for (j = 0; | |
547 | j < ((u16)AR9287_NUM_PDADC_VALUES-diff); | |
548 | j++) | |
549 | pdadcValues[j] = pdadcValues[j+diff]; | |
550 | ||
551 | for (j = (u16)(AR9287_NUM_PDADC_VALUES-diff); | |
552 | j < AR9287_NUM_PDADC_VALUES; j++) | |
553 | pdadcValues[j] = | |
554 | pdadcValues[ | |
555 | AR9287_NUM_PDADC_VALUES-diff]; | |
556 | } | |
557 | ||
558 | if (!ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { | |
559 | regOffset = AR_PHY_BASE + (672 << 2) + | |
560 | regChainOffset; | |
561 | for (j = 0; j < 32; j++) { | |
562 | reg32 = ((pdadcValues[4*j + 0] | |
563 | & 0xFF) << 0) | | |
564 | ((pdadcValues[4*j + 1] | |
565 | & 0xFF) << 8) | | |
566 | ((pdadcValues[4*j + 2] | |
567 | & 0xFF) << 16) | | |
568 | ((pdadcValues[4*j + 3] | |
569 | & 0xFF) << 24) ; | |
570 | REG_WRITE(ah, regOffset, reg32); | |
571 | ||
c46917bb LR |
572 | ath_print(common, ATH_DBG_EEPROM, |
573 | "PDADC (%d,%4x): %4.4x " | |
574 | "%8.8x\n", | |
575 | i, regChainOffset, regOffset, | |
576 | reg32); | |
577 | ||
578 | ath_print(common, ATH_DBG_EEPROM, | |
579 | "PDADC: Chain %d | " | |
580 | "PDADC %3d Value %3d | " | |
581 | "PDADC %3d Value %3d | " | |
582 | "PDADC %3d Value %3d | " | |
583 | "PDADC %3d Value %3d |\n", | |
584 | i, 4 * j, pdadcValues[4 * j], | |
585 | 4 * j + 1, | |
586 | pdadcValues[4 * j + 1], | |
587 | 4 * j + 2, | |
588 | pdadcValues[4 * j + 2], | |
589 | 4 * j + 3, | |
590 | pdadcValues[4 * j + 3]); | |
b5aec950 S |
591 | |
592 | regOffset += 4; | |
593 | } | |
594 | } | |
595 | } | |
596 | } | |
597 | ||
598 | *pTxPowerIndexOffset = 0; | |
599 | } | |
600 | ||
601 | static void ath9k_hw_set_AR9287_power_per_rate_table(struct ath_hw *ah, | |
602 | struct ath9k_channel *chan, int16_t *ratesArray, u16 cfgCtl, | |
603 | u16 AntennaReduction, u16 twiceMaxRegulatoryPower, | |
604 | u16 powerLimit) | |
605 | { | |
606 | #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 | |
607 | #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 | |
608b88cb | 608 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
b5aec950 S |
609 | u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; |
610 | static const u16 tpScaleReductionTable[5] = | |
611 | { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; | |
612 | int i; | |
613 | int16_t twiceLargestAntenna; | |
614 | struct cal_ctl_data_ar9287 *rep; | |
615 | struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} }, | |
616 | targetPowerCck = {0, {0, 0, 0, 0} }; | |
617 | struct cal_target_power_leg targetPowerOfdmExt = {0, {0, 0, 0, 0} }, | |
618 | targetPowerCckExt = {0, {0, 0, 0, 0} }; | |
619 | struct cal_target_power_ht targetPowerHt20, | |
620 | targetPowerHt40 = {0, {0, 0, 0, 0} }; | |
621 | u16 scaledPower = 0, minCtlPower, maxRegAllowedPower; | |
622 | u16 ctlModesFor11g[] = | |
623 | {CTL_11B, CTL_11G, CTL_2GHT20, | |
624 | CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40}; | |
625 | u16 numCtlModes = 0, *pCtlMode = NULL, ctlMode, freq; | |
626 | struct chan_centers centers; | |
627 | int tx_chainmask; | |
628 | u16 twiceMinEdgePower; | |
629 | struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; | |
630 | tx_chainmask = ah->txchainmask; | |
631 | ||
632 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
633 | ||
634 | twiceLargestAntenna = max(pEepData->modalHeader.antennaGainCh[0], | |
635 | pEepData->modalHeader.antennaGainCh[1]); | |
636 | ||
637 | twiceLargestAntenna = (int16_t)min((AntennaReduction) - | |
638 | twiceLargestAntenna, 0); | |
639 | ||
640 | maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; | |
608b88cb | 641 | if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) |
b5aec950 | 642 | maxRegAllowedPower -= |
608b88cb | 643 | (tpScaleReductionTable[(regulatory->tp_scale)] * 2); |
b5aec950 S |
644 | |
645 | scaledPower = min(powerLimit, maxRegAllowedPower); | |
646 | ||
647 | switch (ar5416_get_ntxchains(tx_chainmask)) { | |
648 | case 1: | |
649 | break; | |
650 | case 2: | |
651 | scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN; | |
652 | break; | |
653 | case 3: | |
654 | scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN; | |
655 | break; | |
656 | } | |
657 | scaledPower = max((u16)0, scaledPower); | |
658 | ||
659 | if (IS_CHAN_2GHZ(chan)) { | |
660 | numCtlModes = | |
661 | ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; | |
662 | pCtlMode = ctlModesFor11g; | |
663 | ||
664 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
665 | pEepData->calTargetPowerCck, | |
666 | AR9287_NUM_2G_CCK_TARGET_POWERS, | |
667 | &targetPowerCck, 4, false); | |
668 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
669 | pEepData->calTargetPower2G, | |
670 | AR9287_NUM_2G_20_TARGET_POWERS, | |
671 | &targetPowerOfdm, 4, false); | |
672 | ath9k_hw_get_target_powers(ah, chan, | |
673 | pEepData->calTargetPower2GHT20, | |
674 | AR9287_NUM_2G_20_TARGET_POWERS, | |
675 | &targetPowerHt20, 8, false); | |
676 | ||
677 | if (IS_CHAN_HT40(chan)) { | |
678 | numCtlModes = ARRAY_SIZE(ctlModesFor11g); | |
679 | ath9k_hw_get_target_powers(ah, chan, | |
680 | pEepData->calTargetPower2GHT40, | |
681 | AR9287_NUM_2G_40_TARGET_POWERS, | |
682 | &targetPowerHt40, 8, true); | |
683 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
684 | pEepData->calTargetPowerCck, | |
685 | AR9287_NUM_2G_CCK_TARGET_POWERS, | |
686 | &targetPowerCckExt, 4, true); | |
687 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
688 | pEepData->calTargetPower2G, | |
689 | AR9287_NUM_2G_20_TARGET_POWERS, | |
690 | &targetPowerOfdmExt, 4, true); | |
691 | } | |
692 | } | |
693 | ||
694 | for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { | |
695 | bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || | |
696 | (pCtlMode[ctlMode] == CTL_2GHT40); | |
697 | if (isHt40CtlMode) | |
698 | freq = centers.synth_center; | |
699 | else if (pCtlMode[ctlMode] & EXT_ADDITIVE) | |
700 | freq = centers.ext_center; | |
701 | else | |
702 | freq = centers.ctl_center; | |
703 | ||
704 | if (ah->eep_ops->get_eeprom_ver(ah) == 14 && | |
705 | ah->eep_ops->get_eeprom_rev(ah) <= 2) | |
706 | twiceMaxEdgePower = AR5416_MAX_RATE_POWER; | |
707 | ||
708 | for (i = 0; (i < AR9287_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { | |
709 | if ((((cfgCtl & ~CTL_MODE_M) | | |
710 | (pCtlMode[ctlMode] & CTL_MODE_M)) == | |
711 | pEepData->ctlIndex[i]) || | |
712 | (((cfgCtl & ~CTL_MODE_M) | | |
713 | (pCtlMode[ctlMode] & CTL_MODE_M)) == | |
714 | ((pEepData->ctlIndex[i] & | |
715 | CTL_MODE_M) | SD_NO_CTL))) { | |
716 | ||
717 | rep = &(pEepData->ctlData[i]); | |
718 | twiceMinEdgePower = ath9k_hw_get_max_edge_power( | |
719 | freq, | |
720 | rep->ctlEdges[ar5416_get_ntxchains( | |
721 | tx_chainmask) - 1], | |
722 | IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES); | |
723 | ||
724 | if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) | |
725 | twiceMaxEdgePower = min( | |
726 | twiceMaxEdgePower, | |
727 | twiceMinEdgePower); | |
728 | else { | |
729 | twiceMaxEdgePower = twiceMinEdgePower; | |
730 | break; | |
731 | } | |
732 | } | |
733 | } | |
734 | ||
735 | minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower); | |
736 | ||
737 | switch (pCtlMode[ctlMode]) { | |
738 | case CTL_11B: | |
739 | for (i = 0; | |
740 | i < ARRAY_SIZE(targetPowerCck.tPow2x); | |
741 | i++) { | |
742 | targetPowerCck.tPow2x[i] = (u8)min( | |
743 | (u16)targetPowerCck.tPow2x[i], | |
744 | minCtlPower); | |
745 | } | |
746 | break; | |
747 | case CTL_11A: | |
748 | case CTL_11G: | |
749 | for (i = 0; | |
750 | i < ARRAY_SIZE(targetPowerOfdm.tPow2x); | |
751 | i++) { | |
752 | targetPowerOfdm.tPow2x[i] = (u8)min( | |
753 | (u16)targetPowerOfdm.tPow2x[i], | |
754 | minCtlPower); | |
755 | } | |
756 | break; | |
757 | case CTL_5GHT20: | |
758 | case CTL_2GHT20: | |
759 | for (i = 0; | |
760 | i < ARRAY_SIZE(targetPowerHt20.tPow2x); | |
761 | i++) { | |
762 | targetPowerHt20.tPow2x[i] = (u8)min( | |
763 | (u16)targetPowerHt20.tPow2x[i], | |
764 | minCtlPower); | |
765 | } | |
766 | break; | |
767 | case CTL_11B_EXT: | |
768 | targetPowerCckExt.tPow2x[0] = (u8)min( | |
769 | (u16)targetPowerCckExt.tPow2x[0], | |
770 | minCtlPower); | |
771 | break; | |
772 | case CTL_11A_EXT: | |
773 | case CTL_11G_EXT: | |
774 | targetPowerOfdmExt.tPow2x[0] = (u8)min( | |
775 | (u16)targetPowerOfdmExt.tPow2x[0], | |
776 | minCtlPower); | |
777 | break; | |
778 | case CTL_5GHT40: | |
779 | case CTL_2GHT40: | |
780 | for (i = 0; | |
781 | i < ARRAY_SIZE(targetPowerHt40.tPow2x); | |
782 | i++) { | |
783 | targetPowerHt40.tPow2x[i] = (u8)min( | |
784 | (u16)targetPowerHt40.tPow2x[i], | |
785 | minCtlPower); | |
786 | } | |
787 | break; | |
788 | default: | |
789 | break; | |
790 | } | |
791 | } | |
792 | ||
793 | ratesArray[rate6mb] = | |
794 | ratesArray[rate9mb] = | |
795 | ratesArray[rate12mb] = | |
796 | ratesArray[rate18mb] = | |
797 | ratesArray[rate24mb] = | |
798 | targetPowerOfdm.tPow2x[0]; | |
799 | ||
800 | ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; | |
801 | ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; | |
802 | ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; | |
803 | ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; | |
804 | ||
805 | for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) | |
806 | ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; | |
807 | ||
808 | if (IS_CHAN_2GHZ(chan)) { | |
809 | ratesArray[rate1l] = targetPowerCck.tPow2x[0]; | |
810 | ratesArray[rate2s] = ratesArray[rate2l] = | |
811 | targetPowerCck.tPow2x[1]; | |
812 | ratesArray[rate5_5s] = ratesArray[rate5_5l] = | |
813 | targetPowerCck.tPow2x[2]; | |
814 | ratesArray[rate11s] = ratesArray[rate11l] = | |
815 | targetPowerCck.tPow2x[3]; | |
816 | } | |
817 | if (IS_CHAN_HT40(chan)) { | |
818 | for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) | |
819 | ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i]; | |
820 | ||
821 | ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; | |
822 | ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; | |
823 | ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; | |
824 | if (IS_CHAN_2GHZ(chan)) | |
825 | ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; | |
826 | } | |
827 | ||
828 | #undef REDUCE_SCALED_POWER_BY_TWO_CHAIN | |
829 | #undef REDUCE_SCALED_POWER_BY_THREE_CHAIN | |
830 | } | |
831 | ||
832 | static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah, | |
833 | struct ath9k_channel *chan, u16 cfgCtl, | |
834 | u8 twiceAntennaReduction, | |
835 | u8 twiceMaxRegulatoryPower, | |
836 | u8 powerLimit) | |
837 | { | |
838 | #define INCREASE_MAXPOW_BY_TWO_CHAIN 6 | |
839 | #define INCREASE_MAXPOW_BY_THREE_CHAIN 10 | |
c46917bb | 840 | struct ath_common *common = ath9k_hw_common(ah); |
608b88cb | 841 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
b5aec950 S |
842 | struct ar9287_eeprom *pEepData = &ah->eeprom.map9287; |
843 | struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader; | |
844 | int16_t ratesArray[Ar5416RateSize]; | |
845 | int16_t txPowerIndexOffset = 0; | |
846 | u8 ht40PowerIncForPdadc = 2; | |
847 | int i; | |
848 | ||
849 | memset(ratesArray, 0, sizeof(ratesArray)); | |
850 | ||
851 | if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >= | |
852 | AR9287_EEP_MINOR_VER_2) | |
853 | ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; | |
854 | ||
855 | ath9k_hw_set_AR9287_power_per_rate_table(ah, chan, | |
856 | &ratesArray[0], cfgCtl, | |
857 | twiceAntennaReduction, | |
858 | twiceMaxRegulatoryPower, | |
859 | powerLimit); | |
860 | ||
861 | ath9k_hw_set_AR9287_power_cal_table(ah, chan, &txPowerIndexOffset); | |
862 | ||
863 | for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { | |
864 | ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); | |
865 | if (ratesArray[i] > AR9287_MAX_RATE_POWER) | |
866 | ratesArray[i] = AR9287_MAX_RATE_POWER; | |
867 | } | |
868 | ||
869 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
870 | for (i = 0; i < Ar5416RateSize; i++) | |
871 | ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2; | |
872 | } | |
873 | ||
874 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, | |
875 | ATH9K_POW_SM(ratesArray[rate18mb], 24) | |
876 | | ATH9K_POW_SM(ratesArray[rate12mb], 16) | |
877 | | ATH9K_POW_SM(ratesArray[rate9mb], 8) | |
878 | | ATH9K_POW_SM(ratesArray[rate6mb], 0)); | |
879 | ||
880 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, | |
881 | ATH9K_POW_SM(ratesArray[rate54mb], 24) | |
882 | | ATH9K_POW_SM(ratesArray[rate48mb], 16) | |
883 | | ATH9K_POW_SM(ratesArray[rate36mb], 8) | |
884 | | ATH9K_POW_SM(ratesArray[rate24mb], 0)); | |
885 | ||
886 | if (IS_CHAN_2GHZ(chan)) { | |
887 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, | |
888 | ATH9K_POW_SM(ratesArray[rate2s], 24) | |
889 | | ATH9K_POW_SM(ratesArray[rate2l], 16) | |
890 | | ATH9K_POW_SM(ratesArray[rateXr], 8) | |
891 | | ATH9K_POW_SM(ratesArray[rate1l], 0)); | |
892 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, | |
893 | ATH9K_POW_SM(ratesArray[rate11s], 24) | |
894 | | ATH9K_POW_SM(ratesArray[rate11l], 16) | |
895 | | ATH9K_POW_SM(ratesArray[rate5_5s], 8) | |
896 | | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); | |
897 | } | |
898 | ||
899 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, | |
900 | ATH9K_POW_SM(ratesArray[rateHt20_3], 24) | |
901 | | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) | |
902 | | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) | |
903 | | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); | |
904 | ||
905 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, | |
906 | ATH9K_POW_SM(ratesArray[rateHt20_7], 24) | |
907 | | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) | |
908 | | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) | |
909 | | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); | |
910 | ||
911 | if (IS_CHAN_HT40(chan)) { | |
912 | if (ath9k_hw_AR9287_get_eeprom(ah, EEP_OL_PWRCTRL)) { | |
913 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, | |
914 | ATH9K_POW_SM(ratesArray[rateHt40_3], 24) | |
915 | | ATH9K_POW_SM(ratesArray[rateHt40_2], 16) | |
916 | | ATH9K_POW_SM(ratesArray[rateHt40_1], 8) | |
917 | | ATH9K_POW_SM(ratesArray[rateHt40_0], 0)); | |
918 | ||
919 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, | |
920 | ATH9K_POW_SM(ratesArray[rateHt40_7], 24) | |
921 | | ATH9K_POW_SM(ratesArray[rateHt40_6], 16) | |
922 | | ATH9K_POW_SM(ratesArray[rateHt40_5], 8) | |
923 | | ATH9K_POW_SM(ratesArray[rateHt40_4], 0)); | |
924 | } else { | |
925 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, | |
926 | ATH9K_POW_SM(ratesArray[rateHt40_3] + | |
927 | ht40PowerIncForPdadc, 24) | |
928 | | ATH9K_POW_SM(ratesArray[rateHt40_2] + | |
929 | ht40PowerIncForPdadc, 16) | |
930 | | ATH9K_POW_SM(ratesArray[rateHt40_1] + | |
931 | ht40PowerIncForPdadc, 8) | |
932 | | ATH9K_POW_SM(ratesArray[rateHt40_0] + | |
933 | ht40PowerIncForPdadc, 0)); | |
934 | ||
935 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, | |
936 | ATH9K_POW_SM(ratesArray[rateHt40_7] + | |
937 | ht40PowerIncForPdadc, 24) | |
938 | | ATH9K_POW_SM(ratesArray[rateHt40_6] + | |
939 | ht40PowerIncForPdadc, 16) | |
940 | | ATH9K_POW_SM(ratesArray[rateHt40_5] + | |
941 | ht40PowerIncForPdadc, 8) | |
942 | | ATH9K_POW_SM(ratesArray[rateHt40_4] + | |
943 | ht40PowerIncForPdadc, 0)); | |
944 | } | |
945 | ||
946 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, | |
947 | ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) | |
948 | | ATH9K_POW_SM(ratesArray[rateExtCck], 16) | |
949 | | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) | |
950 | | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); | |
951 | } | |
952 | ||
953 | if (IS_CHAN_2GHZ(chan)) | |
954 | i = rate1l; | |
955 | else | |
956 | i = rate6mb; | |
957 | ||
958 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
608b88cb | 959 | regulatory->max_power_level = |
b5aec950 S |
960 | ratesArray[i] + AR9287_PWR_TABLE_OFFSET_DB * 2; |
961 | else | |
608b88cb | 962 | regulatory->max_power_level = ratesArray[i]; |
b5aec950 S |
963 | |
964 | switch (ar5416_get_ntxchains(ah->txchainmask)) { | |
965 | case 1: | |
966 | break; | |
967 | case 2: | |
608b88cb | 968 | regulatory->max_power_level += |
b5aec950 S |
969 | INCREASE_MAXPOW_BY_TWO_CHAIN; |
970 | break; | |
971 | case 3: | |
608b88cb | 972 | regulatory->max_power_level += |
b5aec950 S |
973 | INCREASE_MAXPOW_BY_THREE_CHAIN; |
974 | break; | |
975 | default: | |
c46917bb LR |
976 | ath_print(common, ATH_DBG_EEPROM, |
977 | "Invalid chainmask configuration\n"); | |
b5aec950 S |
978 | break; |
979 | } | |
980 | } | |
981 | ||
982 | static void ath9k_hw_AR9287_set_addac(struct ath_hw *ah, | |
983 | struct ath9k_channel *chan) | |
984 | { | |
985 | } | |
986 | ||
987 | static void ath9k_hw_AR9287_set_board_values(struct ath_hw *ah, | |
988 | struct ath9k_channel *chan) | |
989 | { | |
990 | struct ar9287_eeprom *eep = &ah->eeprom.map9287; | |
991 | struct modal_eep_ar9287_header *pModal = &eep->modalHeader; | |
992 | u16 antWrites[AR9287_ANT_16S]; | |
993 | u32 regChainOffset; | |
994 | u8 txRxAttenLocal; | |
995 | int i, j, offset_num; | |
996 | ||
997 | pModal = &eep->modalHeader; | |
998 | ||
999 | antWrites[0] = (u16)((pModal->antCtrlCommon >> 28) & 0xF); | |
1000 | antWrites[1] = (u16)((pModal->antCtrlCommon >> 24) & 0xF); | |
1001 | antWrites[2] = (u16)((pModal->antCtrlCommon >> 20) & 0xF); | |
1002 | antWrites[3] = (u16)((pModal->antCtrlCommon >> 16) & 0xF); | |
1003 | antWrites[4] = (u16)((pModal->antCtrlCommon >> 12) & 0xF); | |
1004 | antWrites[5] = (u16)((pModal->antCtrlCommon >> 8) & 0xF); | |
1005 | antWrites[6] = (u16)((pModal->antCtrlCommon >> 4) & 0xF); | |
1006 | antWrites[7] = (u16)(pModal->antCtrlCommon & 0xF); | |
1007 | ||
1008 | offset_num = 8; | |
1009 | ||
1010 | for (i = 0, j = offset_num; i < AR9287_MAX_CHAINS; i++) { | |
1011 | antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 28) & 0xf); | |
1012 | antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 10) & 0x3); | |
1013 | antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 8) & 0x3); | |
1014 | antWrites[j++] = 0; | |
1015 | antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 6) & 0x3); | |
1016 | antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 4) & 0x3); | |
1017 | antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 2) & 0x3); | |
1018 | antWrites[j++] = (u16)(pModal->antCtrlChain[i] & 0x3); | |
1019 | } | |
1020 | ||
1021 | REG_WRITE(ah, AR_PHY_SWITCH_COM, | |
1022 | ah->eep_ops->get_eeprom_antenna_cfg(ah, chan)); | |
1023 | ||
1024 | for (i = 0; i < AR9287_MAX_CHAINS; i++) { | |
1025 | regChainOffset = i * 0x1000; | |
1026 | ||
1027 | REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, | |
1028 | pModal->antCtrlChain[i]); | |
1029 | ||
1030 | REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, | |
1031 | (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) | |
1032 | & ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | | |
1033 | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | | |
1034 | SM(pModal->iqCalICh[i], | |
1035 | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | | |
1036 | SM(pModal->iqCalQCh[i], | |
1037 | AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); | |
1038 | ||
1039 | txRxAttenLocal = pModal->txRxAttenCh[i]; | |
1040 | ||
1041 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, | |
1042 | AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, | |
1043 | pModal->bswMargin[i]); | |
1044 | REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, | |
1045 | AR_PHY_GAIN_2GHZ_XATTEN1_DB, | |
1046 | pModal->bswAtten[i]); | |
1047 | REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, | |
1048 | AR9280_PHY_RXGAIN_TXRX_ATTEN, | |
1049 | txRxAttenLocal); | |
1050 | REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, | |
1051 | AR9280_PHY_RXGAIN_TXRX_MARGIN, | |
1052 | pModal->rxTxMarginCh[i]); | |
1053 | } | |
1054 | ||
1055 | ||
1056 | if (IS_CHAN_HT40(chan)) | |
1057 | REG_RMW_FIELD(ah, AR_PHY_SETTLING, | |
1058 | AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40); | |
1059 | else | |
1060 | REG_RMW_FIELD(ah, AR_PHY_SETTLING, | |
1061 | AR_PHY_SETTLING_SWITCH, pModal->switchSettling); | |
1062 | ||
1063 | REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, | |
1064 | AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize); | |
1065 | ||
1066 | REG_WRITE(ah, AR_PHY_RF_CTL4, | |
1067 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | |
1068 | | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | |
1069 | | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) | |
1070 | | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); | |
1071 | ||
1072 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, | |
1073 | AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn); | |
1074 | ||
1075 | REG_RMW_FIELD(ah, AR_PHY_CCA, | |
1076 | AR9280_PHY_CCA_THRESH62, pModal->thresh62); | |
1077 | REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, | |
1078 | AR_PHY_EXT_CCA0_THRESH62, pModal->thresh62); | |
1079 | ||
1080 | ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0, AR9287_AN_RF2G3_DB1, | |
1081 | AR9287_AN_RF2G3_DB1_S, pModal->db1); | |
1082 | ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0, AR9287_AN_RF2G3_DB2, | |
1083 | AR9287_AN_RF2G3_DB2_S, pModal->db2); | |
1084 | ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0, | |
1085 | AR9287_AN_RF2G3_OB_CCK, | |
1086 | AR9287_AN_RF2G3_OB_CCK_S, pModal->ob_cck); | |
1087 | ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0, | |
1088 | AR9287_AN_RF2G3_OB_PSK, | |
1089 | AR9287_AN_RF2G3_OB_PSK_S, pModal->ob_psk); | |
1090 | ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0, | |
1091 | AR9287_AN_RF2G3_OB_QAM, | |
1092 | AR9287_AN_RF2G3_OB_QAM_S, pModal->ob_qam); | |
1093 | ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH0, | |
1094 | AR9287_AN_RF2G3_OB_PAL_OFF, | |
1095 | AR9287_AN_RF2G3_OB_PAL_OFF_S, | |
1096 | pModal->ob_pal_off); | |
1097 | ||
1098 | ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1, | |
1099 | AR9287_AN_RF2G3_DB1, AR9287_AN_RF2G3_DB1_S, | |
1100 | pModal->db1); | |
1101 | ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1, AR9287_AN_RF2G3_DB2, | |
1102 | AR9287_AN_RF2G3_DB2_S, pModal->db2); | |
1103 | ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1, | |
1104 | AR9287_AN_RF2G3_OB_CCK, | |
1105 | AR9287_AN_RF2G3_OB_CCK_S, pModal->ob_cck); | |
1106 | ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1, | |
1107 | AR9287_AN_RF2G3_OB_PSK, | |
1108 | AR9287_AN_RF2G3_OB_PSK_S, pModal->ob_psk); | |
1109 | ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1, | |
1110 | AR9287_AN_RF2G3_OB_QAM, | |
1111 | AR9287_AN_RF2G3_OB_QAM_S, pModal->ob_qam); | |
1112 | ath9k_hw_analog_shift_rmw(ah, AR9287_AN_RF2G3_CH1, | |
1113 | AR9287_AN_RF2G3_OB_PAL_OFF, | |
1114 | AR9287_AN_RF2G3_OB_PAL_OFF_S, | |
1115 | pModal->ob_pal_off); | |
1116 | ||
1117 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, | |
1118 | AR_PHY_TX_END_DATA_START, pModal->txFrameToDataStart); | |
1119 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, | |
1120 | AR_PHY_TX_END_PA_ON, pModal->txFrameToPaOn); | |
1121 | ||
1122 | ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TOP2, | |
1123 | AR9287_AN_TOP2_XPABIAS_LVL, | |
1124 | AR9287_AN_TOP2_XPABIAS_LVL_S, | |
1125 | pModal->xpaBiasLvl); | |
1126 | } | |
1127 | ||
1128 | static u8 ath9k_hw_AR9287_get_num_ant_config(struct ath_hw *ah, | |
1129 | enum ieee80211_band freq_band) | |
1130 | { | |
1131 | return 1; | |
1132 | } | |
1133 | ||
1134 | static u16 ath9k_hw_AR9287_get_eeprom_antenna_cfg(struct ath_hw *ah, | |
1135 | struct ath9k_channel *chan) | |
1136 | { | |
1137 | struct ar9287_eeprom *eep = &ah->eeprom.map9287; | |
1138 | struct modal_eep_ar9287_header *pModal = &eep->modalHeader; | |
1139 | ||
1140 | return pModal->antCtrlCommon & 0xFFFF; | |
1141 | } | |
1142 | ||
1143 | static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah, | |
1144 | u16 i, bool is2GHz) | |
1145 | { | |
1146 | #define EEP_MAP9287_SPURCHAN \ | |
1147 | (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan) | |
c46917bb | 1148 | struct ath_common *common = ath9k_hw_common(ah); |
b5aec950 S |
1149 | u16 spur_val = AR_NO_SPUR; |
1150 | ||
c46917bb LR |
1151 | ath_print(common, ATH_DBG_ANI, |
1152 | "Getting spur idx %d is2Ghz. %d val %x\n", | |
1153 | i, is2GHz, ah->config.spurchans[i][is2GHz]); | |
b5aec950 S |
1154 | |
1155 | switch (ah->config.spurmode) { | |
1156 | case SPUR_DISABLE: | |
1157 | break; | |
1158 | case SPUR_ENABLE_IOCTL: | |
1159 | spur_val = ah->config.spurchans[i][is2GHz]; | |
c46917bb LR |
1160 | ath_print(common, ATH_DBG_ANI, |
1161 | "Getting spur val from new loc. %d\n", spur_val); | |
b5aec950 S |
1162 | break; |
1163 | case SPUR_ENABLE_EEPROM: | |
1164 | spur_val = EEP_MAP9287_SPURCHAN; | |
1165 | break; | |
1166 | } | |
1167 | ||
1168 | return spur_val; | |
1169 | ||
1170 | #undef EEP_MAP9287_SPURCHAN | |
1171 | } | |
1172 | ||
0b8f6f2b | 1173 | const struct eeprom_ops eep_ar9287_ops = { |
b5aec950 S |
1174 | .check_eeprom = ath9k_hw_AR9287_check_eeprom, |
1175 | .get_eeprom = ath9k_hw_AR9287_get_eeprom, | |
1176 | .fill_eeprom = ath9k_hw_AR9287_fill_eeprom, | |
1177 | .get_eeprom_ver = ath9k_hw_AR9287_get_eeprom_ver, | |
1178 | .get_eeprom_rev = ath9k_hw_AR9287_get_eeprom_rev, | |
1179 | .get_num_ant_config = ath9k_hw_AR9287_get_num_ant_config, | |
1180 | .get_eeprom_antenna_cfg = ath9k_hw_AR9287_get_eeprom_antenna_cfg, | |
1181 | .set_board_values = ath9k_hw_AR9287_set_board_values, | |
1182 | .set_addac = ath9k_hw_AR9287_set_addac, | |
1183 | .set_txpower = ath9k_hw_AR9287_set_txpower, | |
1184 | .get_spur_channel = ath9k_hw_AR9287_get_spur_channel | |
1185 | }; |