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ath9k_htc: Fix beaconing in IBSS mode
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / htc_drv_init.c
CommitLineData
fb9987d0
S		 1/*
2 * Copyright (c) 2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "htc.h"
18
19MODULE_AUTHOR("Atheros Communications");
20MODULE_LICENSE("Dual BSD/GPL");
21MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices");
22
23static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
24module_param_named(debug, ath9k_debug, uint, 0);
25MODULE_PARM_DESC(debug, "Debugging mask");
26
e1572c5e
S		 27int htc_modparam_nohwcrypt;
28module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444);
fb9987d0
S		 29MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
30
31#define CHAN2G(_freq, _idx) { \
32 .center_freq = (_freq), \
33 .hw_value = (_idx), \
34 .max_power = 20, \
35}
36
37static struct ieee80211_channel ath9k_2ghz_channels[] = {
38 CHAN2G(2412, 0), /* Channel 1 */
39 CHAN2G(2417, 1), /* Channel 2 */
40 CHAN2G(2422, 2), /* Channel 3 */
41 CHAN2G(2427, 3), /* Channel 4 */
42 CHAN2G(2432, 4), /* Channel 5 */
43 CHAN2G(2437, 5), /* Channel 6 */
44 CHAN2G(2442, 6), /* Channel 7 */
45 CHAN2G(2447, 7), /* Channel 8 */
46 CHAN2G(2452, 8), /* Channel 9 */
47 CHAN2G(2457, 9), /* Channel 10 */
48 CHAN2G(2462, 10), /* Channel 11 */
49 CHAN2G(2467, 11), /* Channel 12 */
50 CHAN2G(2472, 12), /* Channel 13 */
51 CHAN2G(2484, 13), /* Channel 14 */
52};
53
54/* Atheros hardware rate code addition for short premble */
55#define SHPCHECK(__hw_rate, __flags) \
56 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0)
57
58#define RATE(_bitrate, _hw_rate, _flags) { \
59 .bitrate = (_bitrate), \
60 .flags = (_flags), \
61 .hw_value = (_hw_rate), \
62 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
63}
64
65static struct ieee80211_rate ath9k_legacy_rates[] = {
66 RATE(10, 0x1b, 0),
67 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */
68 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */
69 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */
70 RATE(60, 0x0b, 0),
71 RATE(90, 0x0f, 0),
72 RATE(120, 0x0a, 0),
73 RATE(180, 0x0e, 0),
74 RATE(240, 0x09, 0),
75 RATE(360, 0x0d, 0),
76 RATE(480, 0x08, 0),
77 RATE(540, 0x0c, 0),
78};
79
80static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
81{
82 int time_left;
83
84 /* Firmware can take up to 50ms to get ready, to be safe use 1 second */
85 time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ);
86 if (!time_left) {
87 dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n");
88 return -ETIMEDOUT;
89 }
90
91 return 0;
92}
93
94static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
95{
e1572c5e 96 ath9k_htc_exit_debug(priv->ah);
fb9987d0
S		 97 ath9k_hw_deinit(priv->ah);
98 tasklet_kill(&priv->wmi_tasklet);
99 tasklet_kill(&priv->rx_tasklet);
100 tasklet_kill(&priv->tx_tasklet);
101 kfree(priv->ah);
102 priv->ah = NULL;
103}
104
105static void ath9k_deinit_device(struct ath9k_htc_priv *priv)
106{
107 struct ieee80211_hw *hw = priv->hw;
108
109 wiphy_rfkill_stop_polling(hw->wiphy);
110 ath9k_deinit_leds(priv);
111 ieee80211_unregister_hw(hw);
112 ath9k_rx_cleanup(priv);
113 ath9k_tx_cleanup(priv);
114 ath9k_deinit_priv(priv);
115}
116
117static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
118 u16 service_id,
119 void (*tx) (void *,
120 struct sk_buff *,
121 enum htc_endpoint_id,
122 bool txok),
123 enum htc_endpoint_id *ep_id)
124{
125 struct htc_service_connreq req;
126
127 memset(&req, 0, sizeof(struct htc_service_connreq));
128
129 req.service_id = service_id;
130 req.ep_callbacks.priv = priv;
131 req.ep_callbacks.rx = ath9k_htc_rxep;
132 req.ep_callbacks.tx = tx;
133
134 return htc_connect_service(priv->htc, &req, ep_id);
135}
136
137static int ath9k_init_htc_services(struct ath9k_htc_priv *priv)
138{
139 int ret;
140
141 /* WMI CMD*/
142 ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep);
143 if (ret)
144 goto err;
145
146 /* Beacon */
9c6dda4e 147 ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep,
fb9987d0
S		 148 &priv->beacon_ep);
149 if (ret)
150 goto err;
151
152 /* CAB */
153 ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep,
154 &priv->cab_ep);
155 if (ret)
156 goto err;
157
158
159 /* UAPSD */
160 ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep,
161 &priv->uapsd_ep);
162 if (ret)
163 goto err;
164
165 /* MGMT */
166 ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep,
167 &priv->mgmt_ep);
168 if (ret)
169 goto err;
170
171 /* DATA BE */
172 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep,
173 &priv->data_be_ep);
174 if (ret)
175 goto err;
176
177 /* DATA BK */
178 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep,
179 &priv->data_bk_ep);
180 if (ret)
181 goto err;
182
183 /* DATA VI */
184 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep,
185 &priv->data_vi_ep);
186 if (ret)
187 goto err;
188
189 /* DATA VO */
190 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep,
191 &priv->data_vo_ep);
192 if (ret)
193 goto err;
194
195 ret = htc_init(priv->htc);
196 if (ret)
197 goto err;
198
199 return 0;
200
201err:
202 dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n");
203 return ret;
204}
205
206static int ath9k_reg_notifier(struct wiphy *wiphy,
207 struct regulatory_request *request)
208{
209 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
210 struct ath9k_htc_priv *priv = hw->priv;
211
212 return ath_reg_notifier_apply(wiphy, request,
213 ath9k_hw_regulatory(priv->ah));
214}
215
4a22fe10 216static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
fb9987d0
S		 217{
218 struct ath_hw *ah = (struct ath_hw *) hw_priv;
219 struct ath_common *common = ath9k_hw_common(ah);
220 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
221 __be32 val, reg = cpu_to_be32(reg_offset);
222 int r;
223
224 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
225 (u8 *) &reg, sizeof(reg),
226 (u8 *) &val, sizeof(val),
227 100);
228 if (unlikely(r)) {
229 ath_print(common, ATH_DBG_WMI,
230 "REGISTER READ FAILED: (0x%04x, %d)\n",
231 reg_offset, r);
232 return -EIO;
233 }
234
235 return be32_to_cpu(val);
236}
237
4a22fe10 238static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
fb9987d0
S		 239{
240 struct ath_hw *ah = (struct ath_hw *) hw_priv;
241 struct ath_common *common = ath9k_hw_common(ah);
242 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
243 __be32 buf[2] = {
244 cpu_to_be32(reg_offset),
245 cpu_to_be32(val),
246 };
247 int r;
248
249 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
250 (u8 *) &buf, sizeof(buf),
251 (u8 *) &val, sizeof(val),
252 100);
253 if (unlikely(r)) {
254 ath_print(common, ATH_DBG_WMI,
255 "REGISTER WRITE FAILED:(0x%04x, %d)\n",
256 reg_offset, r);
257 }
258}
259
4a22fe10
S		 260static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
261{
262 struct ath_hw *ah = (struct ath_hw *) hw_priv;
263 struct ath_common *common = ath9k_hw_common(ah);
264 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
265 u32 rsp_status;
266 int r;
267
268 mutex_lock(&priv->wmi->multi_write_mutex);
269
270 /* Store the register/value */
271 priv->wmi->multi_write[priv->wmi->multi_write_idx].reg =
272 cpu_to_be32(reg_offset);
273 priv->wmi->multi_write[priv->wmi->multi_write_idx].val =
274 cpu_to_be32(val);
275
276 priv->wmi->multi_write_idx++;
277
278 /* If the buffer is full, send it out. */
279 if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) {
280 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
281 (u8 *) &priv->wmi->multi_write,
282 sizeof(struct register_write) * priv->wmi->multi_write_idx,
283 (u8 *) &rsp_status, sizeof(rsp_status),
284 100);
285 if (unlikely(r)) {
286 ath_print(common, ATH_DBG_WMI,
287 "REGISTER WRITE FAILED, multi len: %d\n",
288 priv->wmi->multi_write_idx);
289 }
290 priv->wmi->multi_write_idx = 0;
291 }
292
293 mutex_unlock(&priv->wmi->multi_write_mutex);
294}
295
296static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)
297{
298 struct ath_hw *ah = (struct ath_hw *) hw_priv;
299 struct ath_common *common = ath9k_hw_common(ah);
300 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
301
302 if (atomic_read(&priv->wmi->mwrite_cnt))
303 ath9k_regwrite_buffer(hw_priv, val, reg_offset);
304 else
305 ath9k_regwrite_single(hw_priv, val, reg_offset);
306}
307
308static void ath9k_enable_regwrite_buffer(void *hw_priv)
309{
310 struct ath_hw *ah = (struct ath_hw *) hw_priv;
311 struct ath_common *common = ath9k_hw_common(ah);
312 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
313
314 atomic_inc(&priv->wmi->mwrite_cnt);
315}
316
317static void ath9k_disable_regwrite_buffer(void *hw_priv)
318{
319 struct ath_hw *ah = (struct ath_hw *) hw_priv;
320 struct ath_common *common = ath9k_hw_common(ah);
321 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
322
323 atomic_dec(&priv->wmi->mwrite_cnt);
324}
325
326static void ath9k_regwrite_flush(void *hw_priv)
327{
328 struct ath_hw *ah = (struct ath_hw *) hw_priv;
329 struct ath_common *common = ath9k_hw_common(ah);
330 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
331 u32 rsp_status;
332 int r;
333
334 mutex_lock(&priv->wmi->multi_write_mutex);
335
336 if (priv->wmi->multi_write_idx) {
337 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
338 (u8 *) &priv->wmi->multi_write,
339 sizeof(struct register_write) * priv->wmi->multi_write_idx,
340 (u8 *) &rsp_status, sizeof(rsp_status),
341 100);
342 if (unlikely(r)) {
343 ath_print(common, ATH_DBG_WMI,
344 "REGISTER WRITE FAILED, multi len: %d\n",
345 priv->wmi->multi_write_idx);
346 }
347 priv->wmi->multi_write_idx = 0;
348 }
349
350 mutex_unlock(&priv->wmi->multi_write_mutex);
351}
352
fb9987d0 353static const struct ath_ops ath9k_common_ops = {
4a22fe10
S		 354 .read = ath9k_regread,
355 .write = ath9k_regwrite,
356 .enable_write_buffer = ath9k_enable_regwrite_buffer,
357 .disable_write_buffer = ath9k_disable_regwrite_buffer,
358 .write_flush = ath9k_regwrite_flush,
fb9987d0
S		 359};
360
361static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
362{
363 *csz = L1_CACHE_BYTES >> 2;
364}
365
366static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
367{
368 struct ath_hw *ah = (struct ath_hw *) common->ah;
369
370 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
371
372 if (!ath9k_hw_wait(ah,
373 AR_EEPROM_STATUS_DATA,
374 AR_EEPROM_STATUS_DATA_BUSY |
375 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
376 AH_WAIT_TIMEOUT))
377 return false;
378
379 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
380 AR_EEPROM_STATUS_DATA_VAL);
381
382 return true;
383}
384
385static const struct ath_bus_ops ath9k_usb_bus_ops = {
497ad9ad 386 .ath_bus_type = ATH_USB,
fb9987d0
S		 387 .read_cachesize = ath_usb_read_cachesize,
388 .eeprom_read = ath_usb_eeprom_read,
389};
390
391static void setup_ht_cap(struct ath9k_htc_priv *priv,
392 struct ieee80211_sta_ht_cap *ht_info)
393{
394 ht_info->ht_supported = true;
395 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
396 IEEE80211_HT_CAP_SM_PS |
397 IEEE80211_HT_CAP_SGI_40 |
398 IEEE80211_HT_CAP_DSSSCCK40;
399
400 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
401 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
402
403 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
404 ht_info->mcs.rx_mask[0] = 0xff;
405 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
406}
407
408static int ath9k_init_queues(struct ath9k_htc_priv *priv)
409{
410 struct ath_common *common = ath9k_hw_common(priv->ah);
411 int i;
412
413 for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++)
414 priv->hwq_map[i] = -1;
415
416 if (!ath9k_htc_txq_setup(priv, ATH9K_WME_AC_BE)) {
417 ath_print(common, ATH_DBG_FATAL,
418 "Unable to setup xmit queue for BE traffic\n");
419 goto err;
420 }
421
422 if (!ath9k_htc_txq_setup(priv, ATH9K_WME_AC_BK)) {
423 ath_print(common, ATH_DBG_FATAL,
424 "Unable to setup xmit queue for BK traffic\n");
425 goto err;
426 }
427 if (!ath9k_htc_txq_setup(priv, ATH9K_WME_AC_VI)) {
428 ath_print(common, ATH_DBG_FATAL,
429 "Unable to setup xmit queue for VI traffic\n");
430 goto err;
431 }
432 if (!ath9k_htc_txq_setup(priv, ATH9K_WME_AC_VO)) {
433 ath_print(common, ATH_DBG_FATAL,
434 "Unable to setup xmit queue for VO traffic\n");
435 goto err;
436 }
437
438 return 0;
439
440err:
441 return -EINVAL;
442}
443
444static void ath9k_init_crypto(struct ath9k_htc_priv *priv)
445{
446 struct ath_common *common = ath9k_hw_common(priv->ah);
447 int i = 0;
448
449 /* Get the hardware key cache size. */
450 common->keymax = priv->ah->caps.keycache_size;
451 if (common->keymax > ATH_KEYMAX) {
452 ath_print(common, ATH_DBG_ANY,
453 "Warning, using only %u entries in %u key cache\n",
454 ATH_KEYMAX, common->keymax);
455 common->keymax = ATH_KEYMAX;
456 }
457
458 /*
459 * Reset the key cache since some parts do not
460 * reset the contents on initial power up.
461 */
462 for (i = 0; i < common->keymax; i++)
463 ath9k_hw_keyreset(priv->ah, (u16) i);
464
465 if (ath9k_hw_getcapability(priv->ah, ATH9K_CAP_CIPHER,
466 ATH9K_CIPHER_TKIP, NULL)) {
467 /*
468 * Whether we should enable h/w TKIP MIC.
469 * XXX: if we don't support WME TKIP MIC, then we wouldn't
470 * report WMM capable, so it's always safe to turn on
471 * TKIP MIC in this case.
472 */
473 ath9k_hw_setcapability(priv->ah, ATH9K_CAP_TKIP_MIC, 0, 1, NULL);
474 }
475
476 /*
477 * Check whether the separate key cache entries
478 * are required to handle both tx+rx MIC keys.
479 * With split mic keys the number of stations is limited
480 * to 27 otherwise 59.
481 */
482 if (ath9k_hw_getcapability(priv->ah, ATH9K_CAP_CIPHER,
483 ATH9K_CIPHER_TKIP, NULL)
484 && ath9k_hw_getcapability(priv->ah, ATH9K_CAP_CIPHER,
485 ATH9K_CIPHER_MIC, NULL)
486 && ath9k_hw_getcapability(priv->ah, ATH9K_CAP_TKIP_SPLIT,
487 0, NULL))
488 common->splitmic = 1;
489
490 /* turn on mcast key search if possible */
491 if (!ath9k_hw_getcapability(priv->ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
492 (void)ath9k_hw_setcapability(priv->ah, ATH9K_CAP_MCAST_KEYSRCH,
493 1, 1, NULL);
494}
495
496static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv)
497{
498 if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes)) {
499 priv->sbands[IEEE80211_BAND_2GHZ].channels =
500 ath9k_2ghz_channels;
501 priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
502 priv->sbands[IEEE80211_BAND_2GHZ].n_channels =
503 ARRAY_SIZE(ath9k_2ghz_channels);
504 priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
505 priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
506 ARRAY_SIZE(ath9k_legacy_rates);
507 }
508}
509
510static void ath9k_init_misc(struct ath9k_htc_priv *priv)
511{
512 struct ath_common *common = ath9k_hw_common(priv->ah);
513
514 common->tx_chainmask = priv->ah->caps.tx_chainmask;
515 common->rx_chainmask = priv->ah->caps.rx_chainmask;
516
517 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
518 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
519
520 priv->op_flags |= OP_TXAGGR;
9f01a84e 521 priv->ah->opmode = NL80211_IFTYPE_STATION;
fb9987d0
S		 522}
523
524static int ath9k_init_priv(struct ath9k_htc_priv *priv, u16 devid)
525{
526 struct ath_hw *ah = NULL;
527 struct ath_common *common;
528 int ret = 0, csz = 0;
529
530 priv->op_flags |= OP_INVALID;
531
532 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
533 if (!ah)
534 return -ENOMEM;
535
536 ah->hw_version.devid = devid;
537 ah->hw_version.subsysid = 0; /* FIXME */
538 priv->ah = ah;
539
540 common = ath9k_hw_common(ah);
541 common->ops = &ath9k_common_ops;
542 common->bus_ops = &ath9k_usb_bus_ops;
543 common->ah = ah;
544 common->hw = priv->hw;
545 common->priv = priv;
546 common->debug_mask = ath9k_debug;
547
548 spin_lock_init(&priv->wmi->wmi_lock);
549 spin_lock_init(&priv->beacon_lock);
7757dfed 550 spin_lock_init(&priv->tx_lock);
fb9987d0
S		 551 mutex_init(&priv->mutex);
552 mutex_init(&priv->aggr_work.mutex);
bde748a4 553 mutex_init(&priv->htc_pm_lock);
fb9987d0
S		 554 tasklet_init(&priv->wmi_tasklet, ath9k_wmi_tasklet,
555 (unsigned long)priv);
556 tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
557 (unsigned long)priv);
558 tasklet_init(&priv->tx_tasklet, ath9k_tx_tasklet, (unsigned long)priv);
559 INIT_DELAYED_WORK(&priv->ath9k_aggr_work, ath9k_htc_aggr_work);
560 INIT_DELAYED_WORK(&priv->ath9k_ani_work, ath9k_ani_work);
bde748a4 561 INIT_WORK(&priv->ps_work, ath9k_ps_work);
fb9987d0
S		 562
563 /*
564 * Cache line size is used to size and align various
565 * structures used to communicate with the hardware.
566 */
567 ath_read_cachesize(common, &csz);
568 common->cachelsz = csz << 2; /* convert to bytes */
569
570 ret = ath9k_hw_init(ah);
571 if (ret) {
572 ath_print(common, ATH_DBG_FATAL,
573 "Unable to initialize hardware; "
574 "initialization status: %d\n", ret);
575 goto err_hw;
576 }
577
e1572c5e 578 ret = ath9k_htc_init_debug(ah);
fb9987d0
S		 579 if (ret) {
580 ath_print(common, ATH_DBG_FATAL,
581 "Unable to create debugfs files\n");
582 goto err_debug;
583 }
584
585 ret = ath9k_init_queues(priv);
586 if (ret)
587 goto err_queues;
588
589 ath9k_init_crypto(priv);
590 ath9k_init_channels_rates(priv);
591 ath9k_init_misc(priv);
592
593 return 0;
594
595err_queues:
e1572c5e 596 ath9k_htc_exit_debug(ah);
fb9987d0
S		 597err_debug:
598 ath9k_hw_deinit(ah);
599err_hw:
600
601 kfree(ah);
602 priv->ah = NULL;
603
604 return ret;
605}
606
607static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
608 struct ieee80211_hw *hw)
609{
610 struct ath_common *common = ath9k_hw_common(priv->ah);
611
612 hw->flags = IEEE80211_HW_SIGNAL_DBM |
613 IEEE80211_HW_AMPDU_AGGREGATION |
614 IEEE80211_HW_SPECTRUM_MGMT |
32fbccaf 615 IEEE80211_HW_HAS_RATE_CONTROL |
bde748a4
VN		 616 IEEE80211_HW_RX_INCLUDES_FCS |
617 IEEE80211_HW_SUPPORTS_PS |
618 IEEE80211_HW_PS_NULLFUNC_STACK;
fb9987d0
S		 619
620 hw->wiphy->interface_modes =
621 BIT(NL80211_IFTYPE_STATION) |
622 BIT(NL80211_IFTYPE_ADHOC);
623
bde748a4
VN		 624 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
625
fb9987d0
S		 626 hw->queues = 4;
627 hw->channel_change_time = 5000;
628 hw->max_listen_interval = 10;
629 hw->vif_data_size = sizeof(struct ath9k_htc_vif);
630 hw->sta_data_size = sizeof(struct ath9k_htc_sta);
631
632 /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */
633 hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) +
634 sizeof(struct htc_frame_hdr) + 4;
635
636 if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes))
637 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
638 &priv->sbands[IEEE80211_BAND_2GHZ];
639
640 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
641 if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes))
642 setup_ht_cap(priv,
643 &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap);
644 }
645
646 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
647}
648
649static int ath9k_init_device(struct ath9k_htc_priv *priv, u16 devid)
650{
651 struct ieee80211_hw *hw = priv->hw;
652 struct ath_common *common;
653 struct ath_hw *ah;
654 int error = 0;
655 struct ath_regulatory *reg;
656
657 /* Bring up device */
658 error = ath9k_init_priv(priv, devid);
659 if (error != 0)
660 goto err_init;
661
662 ah = priv->ah;
663 common = ath9k_hw_common(ah);
664 ath9k_set_hw_capab(priv, hw);
665
666 /* Initialize regulatory */
667 error = ath_regd_init(&common->regulatory, priv->hw->wiphy,
668 ath9k_reg_notifier);
669 if (error)
670 goto err_regd;
671
672 reg = &common->regulatory;
673
674 /* Setup TX */
675 error = ath9k_tx_init(priv);
676 if (error != 0)
677 goto err_tx;
678
679 /* Setup RX */
680 error = ath9k_rx_init(priv);
681 if (error != 0)
682 goto err_rx;
683
684 /* Register with mac80211 */
685 error = ieee80211_register_hw(hw);
686 if (error)
687 goto err_register;
688
689 /* Handle world regulatory */
690 if (!ath_is_world_regd(reg)) {
691 error = regulatory_hint(hw->wiphy, reg->alpha2);
692 if (error)
693 goto err_world;
694 }
695
696 ath9k_init_leds(priv);
697 ath9k_start_rfkill_poll(priv);
698
699 return 0;
700
701err_world:
702 ieee80211_unregister_hw(hw);
703err_register:
704 ath9k_rx_cleanup(priv);
705err_rx:
706 ath9k_tx_cleanup(priv);
707err_tx:
708 /* Nothing */
709err_regd:
710 ath9k_deinit_priv(priv);
711err_init:
712 return error;
713}
714
715int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
716 u16 devid)
717{
718 struct ieee80211_hw *hw;
719 struct ath9k_htc_priv *priv;
720 int ret;
721
722 hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops);
723 if (!hw)
724 return -ENOMEM;
725
726 priv = hw->priv;
727 priv->hw = hw;
728 priv->htc = htc_handle;
729 priv->dev = dev;
730 htc_handle->drv_priv = priv;
731 SET_IEEE80211_DEV(hw, priv->dev);
732
733 ret = ath9k_htc_wait_for_target(priv);
734 if (ret)
735 goto err_free;
736
737 priv->wmi = ath9k_init_wmi(priv);
738 if (!priv->wmi) {
739 ret = -EINVAL;
740 goto err_free;
741 }
742
743 ret = ath9k_init_htc_services(priv);
744 if (ret)
745 goto err_init;
746
a3be14b7
S		 747 /* The device may have been unplugged earlier. */
748 priv->op_flags &= ~OP_UNPLUGGED;
749
fb9987d0
S		 750 ret = ath9k_init_device(priv, devid);
751 if (ret)
752 goto err_init;
753
754 return 0;
755
756err_init:
757 ath9k_deinit_wmi(priv);
758err_free:
759 ieee80211_free_hw(hw);
760 return ret;
761}
762
763void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
764{
765 if (htc_handle->drv_priv) {
a3be14b7
S		 766
767 /* Check if the device has been yanked out. */
768 if (hotunplug)
769 htc_handle->drv_priv->op_flags |= OP_UNPLUGGED;
770
fb9987d0
S		 771 ath9k_deinit_device(htc_handle->drv_priv);
772 ath9k_deinit_wmi(htc_handle->drv_priv);
773 ieee80211_free_hw(htc_handle->drv_priv->hw);
774 }
775}
776
777#ifdef CONFIG_PM
778int ath9k_htc_resume(struct htc_target *htc_handle)
779{
780 int ret;
781
782 ret = ath9k_htc_wait_for_target(htc_handle->drv_priv);
783 if (ret)
784 return ret;
785
786 ret = ath9k_init_htc_services(htc_handle->drv_priv);
787 return ret;
788}
789#endif
790
791static int __init ath9k_htc_init(void)
792{
793 int error;
794
e1572c5e 795 error = ath9k_htc_debug_create_root();
fb9987d0
S		 796 if (error < 0) {
797 printk(KERN_ERR
798 "ath9k_htc: Unable to create debugfs root: %d\n",
799 error);
800 goto err_dbg;
801 }
802
803 error = ath9k_hif_usb_init();
804 if (error < 0) {
805 printk(KERN_ERR
806 "ath9k_htc: No USB devices found,"
807 " driver not installed.\n");
808 error = -ENODEV;
809 goto err_usb;
810 }
811
812 return 0;
813
814err_usb:
e1572c5e 815 ath9k_htc_debug_remove_root();
fb9987d0
S		 816err_dbg:
817 return error;
818}
819module_init(ath9k_htc_init);
820
821static void __exit ath9k_htc_exit(void)
822{
823 ath9k_hif_usb_exit();
e1572c5e 824 ath9k_htc_debug_remove_root();
fb9987d0
S		 825 printk(KERN_INFO "ath9k_htc: Driver unloaded\n");
826}
827module_exit(ath9k_htc_exit);
Linux kernel - Deliverables
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