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ath9k: Fix primary station configuration
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
09d8e315 20#include <linux/time.h>
c67ce339 21#include <linux/bitops.h>
f078f209
LR		 22#include <asm/unaligned.h>
23
af03abec 24#include "hw.h"
d70357d5 25#include "hw-ops.h"
b622a720 26#include "ar9003_mac.h"
f4701b5a 27#include "ar9003_mci.h"
362cd03f 28#include "ar9003_phy.h"
462e58f2 29#include "ath9k.h"
f078f209 30
cbe61d8a 31static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 32
7322fd19
LR		 33MODULE_AUTHOR("Atheros Communications");
34MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
35MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
36MODULE_LICENSE("Dual BSD/GPL");
37
dfdac8ac 38static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 39{
dfdac8ac 40 struct ath_common *common = ath9k_hw_common(ah);
e4744ec7 41 struct ath9k_channel *chan = ah->curchan;
dfdac8ac 42 unsigned int clockrate;
cbe61d8a 43
087b6ff6
FF		 44 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
45 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
46 clockrate = 117;
e4744ec7 47 else if (!chan) /* should really check for CCK instead */
dfdac8ac 48 clockrate = ATH9K_CLOCK_RATE_CCK;
e4744ec7 49 else if (IS_CHAN_2GHZ(chan))
dfdac8ac
FF		 50 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
51 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
52 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 53 else
dfdac8ac
FF		 54 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
55
beae416b
MN		 56 if (chan) {
57 if (IS_CHAN_HT40(chan))
58 clockrate *= 2;
e4744ec7 59 if (IS_CHAN_HALF_RATE(chan))
906c7205 60 clockrate /= 2;
e4744ec7 61 if (IS_CHAN_QUARTER_RATE(chan))
906c7205
FF		 62 clockrate /= 4;
63 }
64
dfdac8ac 65 common->clockrate = clockrate;
f1dc5600
S		 66}
67
cbe61d8a 68static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 69{
dfdac8ac 70 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 71
dfdac8ac 72 return usecs * common->clockrate;
f1dc5600 73}
f078f209 74
0caa7b14 75bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 76{
77 int i;
78
0caa7b14
S		 79 BUG_ON(timeout < AH_TIME_QUANTUM);
80
81 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 82 if ((REG_READ(ah, reg) & mask) == val)
83 return true;
84
85 udelay(AH_TIME_QUANTUM);
86 }
04bd4638 87
d2182b69 88 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 89 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
90 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 91
f1dc5600 92 return false;
f078f209 93}
7322fd19 94EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 95
7c5adc8d
FF		 96void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
97 int hw_delay)
98{
1a5e6326 99 hw_delay /= 10;
7c5adc8d
FF		 100
101 if (IS_CHAN_HALF_RATE(chan))
102 hw_delay *= 2;
103 else if (IS_CHAN_QUARTER_RATE(chan))
104 hw_delay *= 4;
105
106 udelay(hw_delay + BASE_ACTIVATE_DELAY);
107}
108
0166b4be 109void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
a9b6b256
FF		 110 int column, unsigned int *writecnt)
111{
112 int r;
113
114 ENABLE_REGWRITE_BUFFER(ah);
115 for (r = 0; r < array->ia_rows; r++) {
116 REG_WRITE(ah, INI_RA(array, r, 0),
117 INI_RA(array, r, column));
118 DO_DELAY(*writecnt);
119 }
120 REGWRITE_BUFFER_FLUSH(ah);
121}
122
f078f209
LR		 123u32 ath9k_hw_reverse_bits(u32 val, u32 n)
124{
125 u32 retval;
126 int i;
127
128 for (i = 0, retval = 0; i < n; i++) {
129 retval = (retval << 1) | (val & 1);
130 val >>= 1;
131 }
132 return retval;
133}
134
cbe61d8a 135u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 136 u8 phy, int kbps,
f1dc5600
S		 137 u32 frameLen, u16 rateix,
138 bool shortPreamble)
f078f209 139{
f1dc5600 140 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 141
f1dc5600
S		 142 if (kbps == 0)
143 return 0;
f078f209 144
545750d3 145 switch (phy) {
46d14a58 146 case WLAN_RC_PHY_CCK:
f1dc5600 147 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 148 if (shortPreamble)
f1dc5600
S		 149 phyTime >>= 1;
150 numBits = frameLen << 3;
151 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
152 break;
46d14a58 153 case WLAN_RC_PHY_OFDM:
2660b81a 154 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 155 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
156 numBits = OFDM_PLCP_BITS + (frameLen << 3);
157 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
158 txTime = OFDM_SIFS_TIME_QUARTER
159 + OFDM_PREAMBLE_TIME_QUARTER
160 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 161 } else if (ah->curchan &&
162 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 163 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
164 numBits = OFDM_PLCP_BITS + (frameLen << 3);
165 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
166 txTime = OFDM_SIFS_TIME_HALF +
167 OFDM_PREAMBLE_TIME_HALF
168 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
169 } else {
170 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
171 numBits = OFDM_PLCP_BITS + (frameLen << 3);
172 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
173 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
174 + (numSymbols * OFDM_SYMBOL_TIME);
175 }
176 break;
177 default:
3800276a
JP		 178 ath_err(ath9k_hw_common(ah),
179 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 180 txTime = 0;
181 break;
182 }
f078f209 183
f1dc5600
S		 184 return txTime;
185}
7322fd19 186EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 187
cbe61d8a 188void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 189 struct ath9k_channel *chan,
190 struct chan_centers *centers)
f078f209 191{
f1dc5600 192 int8_t extoff;
f078f209 193
f1dc5600
S		 194 if (!IS_CHAN_HT40(chan)) {
195 centers->ctl_center = centers->ext_center =
196 centers->synth_center = chan->channel;
197 return;
f078f209 198 }
f078f209 199
8896934c 200 if (IS_CHAN_HT40PLUS(chan)) {
f1dc5600
S		 201 centers->synth_center =
202 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
203 extoff = 1;
204 } else {
205 centers->synth_center =
206 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
207 extoff = -1;
208 }
f078f209 209
f1dc5600
S		 210 centers->ctl_center =
211 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 212 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 213 centers->ext_center =
6420014c 214 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 215}
216
f1dc5600
S		 217/******************/
218/* Chip Revisions */
219/******************/
220
cbe61d8a 221static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 222{
f1dc5600 223 u32 val;
f078f209 224
ecb1d385
VT		 225 switch (ah->hw_version.devid) {
226 case AR5416_AR9100_DEVID:
227 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
228 break;
3762561a
GJ		 229 case AR9300_DEVID_AR9330:
230 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
231 if (ah->get_mac_revision) {
232 ah->hw_version.macRev = ah->get_mac_revision();
233 } else {
234 val = REG_READ(ah, AR_SREV);
235 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
236 }
237 return;
ecb1d385
VT		 238 case AR9300_DEVID_AR9340:
239 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
240 val = REG_READ(ah, AR_SREV);
241 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
242 return;
813831dc
GJ		 243 case AR9300_DEVID_QCA955X:
244 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
245 return;
e6b1e46e
SM		 246 case AR9300_DEVID_AR953X:
247 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
7a42e4e7
FF		 248 if (ah->get_mac_revision)
249 ah->hw_version.macRev = ah->get_mac_revision();
e6b1e46e 250 return;
ecb1d385
VT		 251 }
252
f1dc5600 253 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 254
f1dc5600
S		 255 if (val == 0xFF) {
256 val = REG_READ(ah, AR_SREV);
d535a42a
S		 257 ah->hw_version.macVersion =
258 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
259 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 260
77fac465 261 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
76ed94be
MSS		 262 ah->is_pciexpress = true;
263 else
264 ah->is_pciexpress = (val &
265 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 266 } else {
267 if (!AR_SREV_9100(ah))
d535a42a 268 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 269
d535a42a 270 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 271
d535a42a 272 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 273 ah->is_pciexpress = true;
f1dc5600 274 }
f078f209
LR		 275}
276
f1dc5600
S		 277/************************************/
278/* HW Attach, Detach, Init Routines */
279/************************************/
280
cbe61d8a 281static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 282{
040b74f7 283 if (!AR_SREV_5416(ah))
f1dc5600 284 return;
f078f209 285
f1dc5600
S		 286 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 295
f1dc5600 296 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 297}
298
1f3f0618 299/* This should work for all families including legacy */
cbe61d8a 300static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 301{
c46917bb 302 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 303 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 304 u32 regHold[2];
07b2fa5a
JP		 305 static const u32 patternData[4] = {
306 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
307 };
1f3f0618 308 int i, j, loop_max;
f078f209 309
1f3f0618
SB		 310 if (!AR_SREV_9300_20_OR_LATER(ah)) {
311 loop_max = 2;
312 regAddr[1] = AR_PHY_BASE + (8 << 2);
313 } else
314 loop_max = 1;
315
316 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 317 u32 addr = regAddr[i];
318 u32 wrData, rdData;
f078f209 319
f1dc5600
S		 320 regHold[i] = REG_READ(ah, addr);
321 for (j = 0; j < 0x100; j++) {
322 wrData = (j << 16) | j;
323 REG_WRITE(ah, addr, wrData);
324 rdData = REG_READ(ah, addr);
325 if (rdData != wrData) {
3800276a
JP		 326 ath_err(common,
327 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
328 addr, wrData, rdData);
f1dc5600
S		 329 return false;
330 }
331 }
332 for (j = 0; j < 4; j++) {
333 wrData = patternData[j];
334 REG_WRITE(ah, addr, wrData);
335 rdData = REG_READ(ah, addr);
336 if (wrData != rdData) {
3800276a
JP		 337 ath_err(common,
338 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
339 addr, wrData, rdData);
f1dc5600
S		 340 return false;
341 }
f078f209 342 }
f1dc5600 343 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 344 }
f1dc5600 345 udelay(100);
cbe61d8a 346
f078f209
LR		 347 return true;
348}
349
b8b0f377 350static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600 351{
f57cf939
SM		 352 struct ath_common *common = ath9k_hw_common(ah);
353
689e756f
FF		 354 ah->config.dma_beacon_response_time = 1;
355 ah->config.sw_beacon_response_time = 6;
2660b81a 356 ah->config.cwm_ignore_extcca = 0;
2660b81a 357 ah->config.analog_shiftreg = 1;
f078f209 358
0ce024cb 359 ah->config.rx_intr_mitigation = true;
6158425b 360
a64e1a45
SM		 361 if (AR_SREV_9300_20_OR_LATER(ah)) {
362 ah->config.rimt_last = 500;
363 ah->config.rimt_first = 2000;
364 } else {
365 ah->config.rimt_last = 250;
366 ah->config.rimt_first = 700;
367 }
368
6158425b
LR		 369 /*
370 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
371 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
372 * This means we use it for all AR5416 devices, and the few
373 * minor PCI AR9280 devices out there.
374 *
375 * Serialization is required because these devices do not handle
376 * well the case of two concurrent reads/writes due to the latency
377 * involved. During one read/write another read/write can be issued
378 * on another CPU while the previous read/write may still be working
379 * on our hardware, if we hit this case the hardware poops in a loop.
380 * We prevent this by serializing reads and writes.
381 *
382 * This issue is not present on PCI-Express devices or pre-AR5416
383 * devices (legacy, 802.11abg).
384 */
385 if (num_possible_cpus() > 1)
2d6a5e95 386 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f57cf939
SM		 387
388 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
389 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
390 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
391 !ah->is_pciexpress)) {
392 ah->config.serialize_regmode = SER_REG_MODE_ON;
393 } else {
394 ah->config.serialize_regmode = SER_REG_MODE_OFF;
395 }
396 }
397
398 ath_dbg(common, RESET, "serialize_regmode is %d\n",
399 ah->config.serialize_regmode);
400
401 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
402 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
403 else
404 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
f078f209
LR		 405}
406
50aca25b 407static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 408{
608b88cb
LR		 409 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
410
411 regulatory->country_code = CTRY_DEFAULT;
412 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 413
d535a42a 414 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 415 ah->hw_version.subvendorid = 0;
f078f209 416
f57cf939
SM		 417 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
418 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 419 if (AR_SREV_9100(ah))
420 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
f57cf939 421
e3f2acc7 422 ah->slottime = ATH9K_SLOT_TIME_9;
2660b81a 423 ah->globaltxtimeout = (u32) -1;
cbdec975 424 ah->power_mode = ATH9K_PM_UNDEFINED;
8efa7a81 425 ah->htc_reset_init = true;
f57cf939
SM		 426
427 ah->ani_function = ATH9K_ANI_ALL;
428 if (!AR_SREV_9300_20_OR_LATER(ah))
429 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
430
431 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
432 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
433 else
434 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209
LR		 435}
436
cbe61d8a 437static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 438{
1510718d 439 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 440 u32 sum;
441 int i;
442 u16 eeval;
07b2fa5a 443 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 444
445 sum = 0;
446 for (i = 0; i < 3; i++) {
49101676 447 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 448 sum += eeval;
1510718d
LR		 449 common->macaddr[2 * i] = eeval >> 8;
450 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 451 }
d8baa939 452 if (sum == 0 || sum == 0xffff * 3)
f078f209 453 return -EADDRNOTAVAIL;
f078f209
LR		 454
455 return 0;
456}
457
f637cfd6 458static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 459{
6cae913d 460 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 461 int ecode;
f078f209 462
6cae913d 463 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 464 if (!ath9k_hw_chip_test(ah))
465 return -ENODEV;
466 }
f078f209 467
ebd5a14a
LR		 468 if (!AR_SREV_9300_20_OR_LATER(ah)) {
469 ecode = ar9002_hw_rf_claim(ah);
470 if (ecode != 0)
471 return ecode;
472 }
f078f209 473
f637cfd6 474 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 475 if (ecode != 0)
476 return ecode;
7d01b221 477
d2182b69 478 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 479 ah->eep_ops->get_eeprom_ver(ah),
480 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 481
e323300d 482 ath9k_hw_ani_init(ah);
f078f209 483
d3b371cb
SM		 484 /*
485 * EEPROM needs to be initialized before we do this.
486 * This is required for regulatory compliance.
487 */
0c7c2bb4 488 if (AR_SREV_9300_20_OR_LATER(ah)) {
d3b371cb
SM		 489 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
490 if ((regdmn & 0xF0) == CTL_FCC) {
0c7c2bb4
SM		 491 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
492 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
d3b371cb
SM		 493 }
494 }
495
f078f209
LR		 496 return 0;
497}
498
c1b976d2 499static int ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 500{
c1b976d2
FF		 501 if (!AR_SREV_9300_20_OR_LATER(ah))
502 return ar9002_hw_attach_ops(ah);
503
504 ar9003_hw_attach_ops(ah);
505 return 0;
aa4058ae
LR		 506}
507
d70357d5
LR		 508/* Called for all hardware families */
509static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 510{
c46917bb 511 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 512 int r = 0;
aa4058ae 513
ac45c12d
SB		 514 ath9k_hw_read_revisions(ah);
515
de82582b
SM		 516 switch (ah->hw_version.macVersion) {
517 case AR_SREV_VERSION_5416_PCI:
518 case AR_SREV_VERSION_5416_PCIE:
519 case AR_SREV_VERSION_9160:
520 case AR_SREV_VERSION_9100:
521 case AR_SREV_VERSION_9280:
522 case AR_SREV_VERSION_9285:
523 case AR_SREV_VERSION_9287:
524 case AR_SREV_VERSION_9271:
525 case AR_SREV_VERSION_9300:
526 case AR_SREV_VERSION_9330:
527 case AR_SREV_VERSION_9485:
528 case AR_SREV_VERSION_9340:
529 case AR_SREV_VERSION_9462:
530 case AR_SREV_VERSION_9550:
531 case AR_SREV_VERSION_9565:
e6b1e46e 532 case AR_SREV_VERSION_9531:
de82582b
SM		 533 break;
534 default:
535 ath_err(common,
536 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
537 ah->hw_version.macVersion, ah->hw_version.macRev);
538 return -EOPNOTSUPP;
539 }
540
0a8d7cb0
SB		 541 /*
542 * Read back AR_WA into a permanent copy and set bits 14 and 17.
543 * We need to do this to avoid RMW of this register. We cannot
544 * read the reg when chip is asleep.
545 */
27251e00
SM		 546 if (AR_SREV_9300_20_OR_LATER(ah)) {
547 ah->WARegVal = REG_READ(ah, AR_WA);
548 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
549 AR_WA_ASPM_TIMER_BASED_DISABLE);
550 }
0a8d7cb0 551
aa4058ae 552 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 553 ath_err(common, "Couldn't reset chip\n");
95fafca2 554 return -EIO;
aa4058ae
LR		 555 }
556
a4a2954f
SM		 557 if (AR_SREV_9565(ah)) {
558 ah->WARegVal |= AR_WA_BIT22;
559 REG_WRITE(ah, AR_WA, ah->WARegVal);
560 }
561
bab1f62e
LR		 562 ath9k_hw_init_defaults(ah);
563 ath9k_hw_init_config(ah);
564
c1b976d2
FF		 565 r = ath9k_hw_attach_ops(ah);
566 if (r)
567 return r;
d70357d5 568
9ecdef4b 569 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 570 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 571 return -EIO;
aa4058ae
LR		 572 }
573
2c8e5937 574 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
c95b584b 575 AR_SREV_9330(ah) || AR_SREV_9550(ah))
d7e7d229
LR		 576 ah->is_pciexpress = false;
577
aa4058ae 578 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 579 ath9k_hw_init_cal_settings(ah);
580
69ce674b 581 if (!ah->is_pciexpress)
aa4058ae
LR		 582 ath9k_hw_disablepcie(ah);
583
f637cfd6 584 r = ath9k_hw_post_init(ah);
aa4058ae 585 if (r)
95fafca2 586 return r;
aa4058ae
LR		 587
588 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 589 r = ath9k_hw_fill_cap_info(ah);
590 if (r)
591 return r;
592
4f3acf81
LR		 593 r = ath9k_hw_init_macaddr(ah);
594 if (r) {
3800276a 595 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 596 return r;
f078f209
LR		 597 }
598
4598702d 599 ath9k_hw_init_hang_checks(ah);
f078f209 600
211f5859
LR		 601 common->state = ATH_HW_INITIALIZED;
602
4f3acf81 603 return 0;
f078f209
LR		 604}
605
d70357d5 606int ath9k_hw_init(struct ath_hw *ah)
f078f209 607{
d70357d5
LR		 608 int ret;
609 struct ath_common *common = ath9k_hw_common(ah);
f078f209 610
77fac465 611 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
d70357d5
LR		 612 switch (ah->hw_version.devid) {
613 case AR5416_DEVID_PCI:
614 case AR5416_DEVID_PCIE:
615 case AR5416_AR9100_DEVID:
616 case AR9160_DEVID_PCI:
617 case AR9280_DEVID_PCI:
618 case AR9280_DEVID_PCIE:
619 case AR9285_DEVID_PCIE:
db3cc53a
SB		 620 case AR9287_DEVID_PCI:
621 case AR9287_DEVID_PCIE:
d70357d5 622 case AR2427_DEVID_PCIE:
db3cc53a 623 case AR9300_DEVID_PCIE:
3050c914 624 case AR9300_DEVID_AR9485_PCIE:
999a7a88 625 case AR9300_DEVID_AR9330:
bca04689 626 case AR9300_DEVID_AR9340:
2b943a33 627 case AR9300_DEVID_QCA955X:
5a63ef0f 628 case AR9300_DEVID_AR9580:
423e38e8 629 case AR9300_DEVID_AR9462:
d4e5979c 630 case AR9485_DEVID_AR1111:
77fac465 631 case AR9300_DEVID_AR9565:
e6b1e46e 632 case AR9300_DEVID_AR953X:
d70357d5
LR		 633 break;
634 default:
635 if (common->bus_ops->ath_bus_type == ATH_USB)
636 break;
3800276a
JP		 637 ath_err(common, "Hardware device ID 0x%04x not supported\n",
638 ah->hw_version.devid);
d70357d5
LR		 639 return -EOPNOTSUPP;
640 }
f078f209 641
d70357d5
LR		 642 ret = __ath9k_hw_init(ah);
643 if (ret) {
3800276a
JP		 644 ath_err(common,
645 "Unable to initialize hardware; initialization status: %d\n",
646 ret);
d70357d5
LR		 647 return ret;
648 }
f078f209 649
d70357d5 650 return 0;
f078f209 651}
d70357d5 652EXPORT_SYMBOL(ath9k_hw_init);
f078f209 653
cbe61d8a 654static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 655{
7d0d0df0
S		 656 ENABLE_REGWRITE_BUFFER(ah);
657
f1dc5600
S		 658 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
659 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 660
f1dc5600
S		 661 REG_WRITE(ah, AR_QOS_NO_ACK,
662 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
663 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
664 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
665
666 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
667 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
668 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
669 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
670 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 671
672 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 673}
674
b84628eb 675u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 676{
f18e3c6b
MSS		 677 struct ath_common *common = ath9k_hw_common(ah);
678 int i = 0;
679
ca7a4deb
FF		 680 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
681 udelay(100);
682 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 683
f18e3c6b
MSS		 684 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
685
ca7a4deb 686 udelay(100);
b1415819 687
f18e3c6b
MSS		 688 if (WARN_ON_ONCE(i >= 100)) {
689 ath_err(common, "PLL4 meaurement not done\n");
690 break;
691 }
692
693 i++;
694 }
695
ca7a4deb 696 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 697}
698EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
699
cbe61d8a 700static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 701 struct ath9k_channel *chan)
f078f209 702{
d09b17f7
VT		 703 u32 pll;
704
a4a2954f 705 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3dfd7f60
VT		 706 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
707 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
708 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
709 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
710 AR_CH0_DPLL2_KD, 0x40);
711 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
712 AR_CH0_DPLL2_KI, 0x4);
22983c30 713
3dfd7f60
VT		 714 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
715 AR_CH0_BB_DPLL1_REFDIV, 0x5);
716 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
717 AR_CH0_BB_DPLL1_NINI, 0x58);
718 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
719 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 720
721 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 722 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
723 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
724 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 725 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 726 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 727
3dfd7f60 728 /* program BB PLL phase_shift to 0x6 */
22983c30 729 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 730 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
731
732 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
733 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 734 udelay(1000);
a5415d62
GJ		 735 } else if (AR_SREV_9330(ah)) {
736 u32 ddr_dpll2, pll_control2, kd;
737
738 if (ah->is_clk_25mhz) {
739 ddr_dpll2 = 0x18e82f01;
740 pll_control2 = 0xe04a3d;
741 kd = 0x1d;
742 } else {
743 ddr_dpll2 = 0x19e82f01;
744 pll_control2 = 0x886666;
745 kd = 0x3d;
746 }
747
748 /* program DDR PLL ki and kd value */
749 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
750
751 /* program DDR PLL phase_shift */
752 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
753 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
754
755 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
756 udelay(1000);
757
758 /* program refdiv, nint, frac to RTC register */
759 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
760
761 /* program BB PLL kd and ki value */
762 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
763 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
764
765 /* program BB PLL phase_shift */
766 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
767 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
2c323058 768 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
0b488ac6
VT		 769 u32 regval, pll2_divint, pll2_divfrac, refdiv;
770
771 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
772 udelay(1000);
773
774 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
775 udelay(100);
776
777 if (ah->is_clk_25mhz) {
2c323058
SM		 778 if (AR_SREV_9531(ah)) {
779 pll2_divint = 0x1c;
780 pll2_divfrac = 0xa3d2;
781 refdiv = 1;
782 } else {
783 pll2_divint = 0x54;
784 pll2_divfrac = 0x1eb85;
785 refdiv = 3;
786 }
0b488ac6 787 } else {
fc05a317
GJ		 788 if (AR_SREV_9340(ah)) {
789 pll2_divint = 88;
790 pll2_divfrac = 0;
791 refdiv = 5;
792 } else {
793 pll2_divint = 0x11;
76ac9ed6
RM		 794 pll2_divfrac =
795 AR_SREV_9531(ah) ? 0x26665 : 0x26666;
fc05a317
GJ		 796 refdiv = 1;
797 }
0b488ac6
VT		 798 }
799
800 regval = REG_READ(ah, AR_PHY_PLL_MODE);
2c323058
SM		 801 if (AR_SREV_9531(ah))
802 regval |= (0x1 << 22);
803 else
804 regval |= (0x1 << 16);
0b488ac6
VT		 805 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
806 udelay(100);
807
808 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
809 (pll2_divint << 18) | pll2_divfrac);
810 udelay(100);
811
812 regval = REG_READ(ah, AR_PHY_PLL_MODE);
fc05a317 813 if (AR_SREV_9340(ah))
2c323058
SM		 814 regval = (regval & 0x80071fff) |
815 (0x1 << 30) |
816 (0x1 << 13) |
817 (0x4 << 26) |
818 (0x18 << 19);
819 else if (AR_SREV_9531(ah))
820 regval = (regval & 0x01c00fff) |
821 (0x1 << 31) |
822 (0x2 << 29) |
823 (0xa << 25) |
824 (0x1 << 19) |
825 (0x6 << 12);
fc05a317 826 else
2c323058
SM		 827 regval = (regval & 0x80071fff) |
828 (0x3 << 30) |
829 (0x1 << 13) |
830 (0x4 << 26) |
831 (0x60 << 19);
0b488ac6 832 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
2c323058
SM		 833
834 if (AR_SREV_9531(ah))
835 REG_WRITE(ah, AR_PHY_PLL_MODE,
836 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
837 else
838 REG_WRITE(ah, AR_PHY_PLL_MODE,
839 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
840
0b488ac6 841 udelay(1000);
22983c30 842 }
d09b17f7
VT		 843
844 pll = ath9k_hw_compute_pll_control(ah, chan);
8565f8bf
SM		 845 if (AR_SREV_9565(ah))
846 pll |= 0x40000;
d03a66c1 847 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 848
fc05a317
GJ		 849 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
850 AR_SREV_9550(ah))
3dfd7f60
VT		 851 udelay(1000);
852
c75724d1
LR		 853 /* Switch the core clock for ar9271 to 117Mhz */
854 if (AR_SREV_9271(ah)) {
25e2ab17
S		 855 udelay(500);
856 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 857 }
858
f1dc5600
S		 859 udelay(RTC_PLL_SETTLE_DELAY);
860
861 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
0b488ac6 862
fc05a317 863 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
0b488ac6
VT		 864 if (ah->is_clk_25mhz) {
865 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
866 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
867 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
868 } else {
869 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
870 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
871 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
872 }
873 udelay(100);
874 }
f078f209
LR		 875}
876
cbe61d8a 877static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 878 enum nl80211_iftype opmode)
f078f209 879{
79d1d2b8 880 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 881 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 882 AR_IMR_TXURN |
883 AR_IMR_RXERR |
884 AR_IMR_RXORN |
885 AR_IMR_BCNMISC;
f078f209 886
c90d4f7b 887 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah))
79d1d2b8
VT		 888 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
889
66860240
VT		 890 if (AR_SREV_9300_20_OR_LATER(ah)) {
891 imr_reg |= AR_IMR_RXOK_HP;
892 if (ah->config.rx_intr_mitigation)
893 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
894 else
895 imr_reg |= AR_IMR_RXOK_LP;
f078f209 896
66860240
VT		 897 } else {
898 if (ah->config.rx_intr_mitigation)
899 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
900 else
901 imr_reg |= AR_IMR_RXOK;
902 }
f078f209 903
66860240
VT		 904 if (ah->config.tx_intr_mitigation)
905 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
906 else
907 imr_reg |= AR_IMR_TXOK;
f078f209 908
7d0d0df0
S		 909 ENABLE_REGWRITE_BUFFER(ah);
910
152d530d 911 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 912 ah->imrs2_reg |= AR_IMR_S2_GTT;
913 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 914
f1dc5600
S		 915 if (!AR_SREV_9100(ah)) {
916 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 917 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 918 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
919 }
66860240 920
7d0d0df0 921 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 922
66860240
VT		 923 if (AR_SREV_9300_20_OR_LATER(ah)) {
924 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
925 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
926 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
927 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
928 }
f078f209
LR		 929}
930
b6ba41bb
FF		 931static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
932{
933 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
934 val = min(val, (u32) 0xFFFF);
935 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
936}
937
0005baf4 938static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 939{
0005baf4
FF		 940 u32 val = ath9k_hw_mac_to_clks(ah, us);
941 val = min(val, (u32) 0xFFFF);
942 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 943}
944
0005baf4 945static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 946{
0005baf4
FF		 947 u32 val = ath9k_hw_mac_to_clks(ah, us);
948 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
949 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
950}
951
952static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
953{
954 u32 val = ath9k_hw_mac_to_clks(ah, us);
955 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
956 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 957}
f1dc5600 958
cbe61d8a 959static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 960{
f078f209 961 if (tu > 0xFFFF) {
d2182b69
JP		 962 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
963 tu);
2660b81a 964 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 965 return false;
966 } else {
967 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 968 ah->globaltxtimeout = tu;
f078f209
LR		 969 return true;
970 }
971}
972
0005baf4 973void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 974{
b6ba41bb 975 struct ath_common *common = ath9k_hw_common(ah);
b6ba41bb 976 const struct ath9k_channel *chan = ah->curchan;
e115b7ec 977 int acktimeout, ctstimeout, ack_offset = 0;
e239d859 978 int slottime;
0005baf4 979 int sifstime;
b6ba41bb
FF		 980 int rx_lat = 0, tx_lat = 0, eifs = 0;
981 u32 reg;
0005baf4 982
d2182b69 983 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 984 ah->misc_mode);
f078f209 985
b6ba41bb
FF		 986 if (!chan)
987 return;
988
2660b81a 989 if (ah->misc_mode != 0)
ca7a4deb 990 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 991
81a91d57
RM		 992 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
993 rx_lat = 41;
994 else
995 rx_lat = 37;
b6ba41bb
FF		 996 tx_lat = 54;
997
e88e4861
FF		 998 if (IS_CHAN_5GHZ(chan))
999 sifstime = 16;
1000 else
1001 sifstime = 10;
1002
b6ba41bb
FF		 1003 if (IS_CHAN_HALF_RATE(chan)) {
1004 eifs = 175;
1005 rx_lat *= 2;
1006 tx_lat *= 2;
1007 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1008 tx_lat += 11;
1009
92367fe7 1010 sifstime = 32;
e115b7ec 1011 ack_offset = 16;
b6ba41bb 1012 slottime = 13;
b6ba41bb
FF		 1013 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1014 eifs = 340;
81a91d57 1015 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 1016 tx_lat *= 4;
1017 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1018 tx_lat += 22;
1019
92367fe7 1020 sifstime = 64;
e115b7ec 1021 ack_offset = 32;
b6ba41bb 1022 slottime = 21;
b6ba41bb 1023 } else {
a7be039d
RM		 1024 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1025 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1026 reg = AR_USEC_ASYNC_FIFO;
1027 } else {
1028 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1029 common->clockrate;
1030 reg = REG_READ(ah, AR_USEC);
1031 }
b6ba41bb
FF		 1032 rx_lat = MS(reg, AR_USEC_RX_LAT);
1033 tx_lat = MS(reg, AR_USEC_TX_LAT);
1034
1035 slottime = ah->slottime;
b6ba41bb 1036 }
0005baf4 1037
e239d859 1038 /* As defined by IEEE 802.11-2007 17.3.8.6 */
f77f8234
MK		 1039 slottime += 3 * ah->coverage_class;
1040 acktimeout = slottime + sifstime + ack_offset;
adb5066a 1041 ctstimeout = acktimeout;
42c4568a
FF		 1042
1043 /*
1044 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1045 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1046 * This was initially only meant to work around an issue with delayed
1047 * BA frames in some implementations, but it has been found to fix ACK
1048 * timeout issues in other cases as well.
1049 */
e4744ec7 1050 if (IS_CHAN_2GHZ(chan) &&
e115b7ec 1051 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
42c4568a 1052 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1053 ctstimeout += 48 - sifstime - ah->slottime;
1054 }
1055
b6ba41bb
FF		 1056 ath9k_hw_set_sifs_time(ah, sifstime);
1057 ath9k_hw_setslottime(ah, slottime);
0005baf4 1058 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1059 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1060 if (ah->globaltxtimeout != (u32) -1)
1061 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1062
1063 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1064 REG_RMW(ah, AR_USEC,
1065 (common->clockrate - 1) |
1066 SM(rx_lat, AR_USEC_RX_LAT) |
1067 SM(tx_lat, AR_USEC_TX_LAT),
1068 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1069
f1dc5600 1070}
0005baf4 1071EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1072
285f2dda 1073void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1074{
211f5859
LR		 1075 struct ath_common *common = ath9k_hw_common(ah);
1076
736b3a27 1077 if (common->state < ATH_HW_INITIALIZED)
c1b976d2 1078 return;
211f5859 1079
9ecdef4b 1080 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
f1dc5600 1081}
285f2dda 1082EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1083
f1dc5600
S		 1084/*******/
1085/* INI */
1086/*******/
1087
8fe65368 1088u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1089{
1090 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1091
6b21fd20 1092 if (IS_CHAN_2GHZ(chan))
3a702e49
BC		 1093 ctl |= CTL_11G;
1094 else
1095 ctl |= CTL_11A;
1096
1097 return ctl;
1098}
1099
f1dc5600
S		 1100/****************************************/
1101/* Reset and Channel Switching Routines */
1102/****************************************/
f1dc5600 1103
cbe61d8a 1104static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1105{
57b32227 1106 struct ath_common *common = ath9k_hw_common(ah);
86c157b3 1107 int txbuf_size;
f1dc5600 1108
7d0d0df0
S		 1109 ENABLE_REGWRITE_BUFFER(ah);
1110
d7e7d229
LR		 1111 /*
1112 * set AHB_MODE not to do cacheline prefetches
1113 */
ca7a4deb
FF		 1114 if (!AR_SREV_9300_20_OR_LATER(ah))
1115 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1116
d7e7d229
LR		 1117 /*
1118 * let mac dma reads be in 128 byte chunks
1119 */
ca7a4deb 1120 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1121
7d0d0df0 1122 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1123
d7e7d229
LR		 1124 /*
1125 * Restore TX Trigger Level to its pre-reset value.
1126 * The initial value depends on whether aggregation is enabled, and is
1127 * adjusted whenever underruns are detected.
1128 */
57b32227
FF		 1129 if (!AR_SREV_9300_20_OR_LATER(ah))
1130 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1131
7d0d0df0 1132 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1133
d7e7d229
LR		 1134 /*
1135 * let mac dma writes be in 128 byte chunks
1136 */
ca7a4deb 1137 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1138
d7e7d229
LR		 1139 /*
1140 * Setup receive FIFO threshold to hold off TX activities
1141 */
f1dc5600
S		 1142 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1143
57b32227
FF		 1144 if (AR_SREV_9300_20_OR_LATER(ah)) {
1145 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1146 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1147
1148 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1149 ah->caps.rx_status_len);
1150 }
1151
d7e7d229
LR		 1152 /*
1153 * reduce the number of usable entries in PCU TXBUF to avoid
1154 * wrap around issues.
1155 */
f1dc5600 1156 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1157 /* For AR9285 the number of Fifos are reduced to half.
1158 * So set the usable tx buf size also to half to
1159 * avoid data/delimiter underruns
1160 */
86c157b3
FF		 1161 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1162 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1163 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1164 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1165 } else {
1166 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
f1dc5600 1167 }
744d4025 1168
86c157b3
FF		 1169 if (!AR_SREV_9271(ah))
1170 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1171
7d0d0df0 1172 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1173
744d4025
VT		 1174 if (AR_SREV_9300_20_OR_LATER(ah))
1175 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1176}
1177
cbe61d8a 1178static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1179{
ca7a4deb
FF		 1180 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1181 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1182
f1dc5600 1183 switch (opmode) {
d97809db 1184 case NL80211_IFTYPE_ADHOC:
ca7a4deb 1185 set |= AR_STA_ID1_ADHOC;
f1dc5600 1186 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1187 break;
2664d666 1188 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb
FF		 1189 case NL80211_IFTYPE_AP:
1190 set |= AR_STA_ID1_STA_AP;
1191 /* fall through */
d97809db 1192 case NL80211_IFTYPE_STATION:
ca7a4deb 1193 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1194 break;
5f841b41 1195 default:
ca7a4deb
FF		 1196 if (!ah->is_monitoring)
1197 set = 0;
5f841b41 1198 break;
f1dc5600 1199 }
ca7a4deb 1200 REG_RMW(ah, AR_STA_ID1, set, mask);
f1dc5600
S		 1201}
1202
8fe65368
LR		 1203void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1204 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1205{
1206 u32 coef_exp, coef_man;
1207
1208 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1209 if ((coef_scaled >> coef_exp) & 0x1)
1210 break;
1211
1212 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1213
1214 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1215
1216 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1217 *coef_exponent = coef_exp - 16;
1218}
1219
d7df7a55
SM		 1220/* AR9330 WAR:
1221 * call external reset function to reset WMAC if:
1222 * - doing a cold reset
1223 * - we have pending frames in the TX queues.
1224 */
1225static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1226{
1227 int i, npend = 0;
1228
1229 for (i = 0; i < AR_NUM_QCU; i++) {
1230 npend = ath9k_hw_numtxpending(ah, i);
1231 if (npend)
1232 break;
1233 }
1234
1235 if (ah->external_reset &&
1236 (npend || type == ATH9K_RESET_COLD)) {
1237 int reset_err = 0;
1238
1239 ath_dbg(ath9k_hw_common(ah), RESET,
1240 "reset MAC via external reset\n");
1241
1242 reset_err = ah->external_reset();
1243 if (reset_err) {
1244 ath_err(ath9k_hw_common(ah),
1245 "External reset failed, err=%d\n",
1246 reset_err);
1247 return false;
1248 }
1249
1250 REG_WRITE(ah, AR_RTC_RESET, 1);
1251 }
1252
1253 return true;
1254}
1255
cbe61d8a 1256static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1257{
1258 u32 rst_flags;
1259 u32 tmpReg;
1260
70768496 1261 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1262 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1263 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1264 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1265 }
1266
7d0d0df0
S		 1267 ENABLE_REGWRITE_BUFFER(ah);
1268
9a658d2b
LR		 1269 if (AR_SREV_9300_20_OR_LATER(ah)) {
1270 REG_WRITE(ah, AR_WA, ah->WARegVal);
1271 udelay(10);
1272 }
1273
f1dc5600
S		 1274 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1275 AR_RTC_FORCE_WAKE_ON_INT);
1276
1277 if (AR_SREV_9100(ah)) {
1278 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1279 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1280 } else {
1281 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
a37a9910
FF		 1282 if (AR_SREV_9340(ah))
1283 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1284 else
1285 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1286 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1287
1288 if (tmpReg) {
42d5bc3f 1289 u32 val;
f1dc5600 1290 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1291
1292 val = AR_RC_HOSTIF;
1293 if (!AR_SREV_9300_20_OR_LATER(ah))
1294 val |= AR_RC_AHB;
1295 REG_WRITE(ah, AR_RC, val);
1296
1297 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1298 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1299
1300 rst_flags = AR_RTC_RC_MAC_WARM;
1301 if (type == ATH9K_RESET_COLD)
1302 rst_flags |= AR_RTC_RC_MAC_COLD;
1303 }
1304
7d95847c 1305 if (AR_SREV_9330(ah)) {
d7df7a55
SM		 1306 if (!ath9k_hw_ar9330_reset_war(ah, type))
1307 return false;
7d95847c
GJ		 1308 }
1309
3863495b 1310 if (ath9k_hw_mci_is_enabled(ah))
506847ad 1311 ar9003_mci_check_gpm_offset(ah);
3863495b 1312
d03a66c1 1313 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1314
1315 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1316
4dc78c43
SM		 1317 if (AR_SREV_9300_20_OR_LATER(ah))
1318 udelay(50);
1319 else if (AR_SREV_9100(ah))
3683a07b 1320 mdelay(10);
4dc78c43
SM		 1321 else
1322 udelay(100);
f1dc5600 1323
d03a66c1 1324 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1325 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1326 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1327 return false;
1328 }
1329
1330 if (!AR_SREV_9100(ah))
1331 REG_WRITE(ah, AR_RC, 0);
1332
f1dc5600
S		 1333 if (AR_SREV_9100(ah))
1334 udelay(50);
1335
1336 return true;
1337}
1338
cbe61d8a 1339static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1340{
7d0d0df0
S		 1341 ENABLE_REGWRITE_BUFFER(ah);
1342
9a658d2b
LR		 1343 if (AR_SREV_9300_20_OR_LATER(ah)) {
1344 REG_WRITE(ah, AR_WA, ah->WARegVal);
1345 udelay(10);
1346 }
1347
f1dc5600
S		 1348 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1349 AR_RTC_FORCE_WAKE_ON_INT);
1350
42d5bc3f 1351 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1352 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1353
d03a66c1 1354 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1355
7d0d0df0 1356 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1357
afe36533 1358 udelay(2);
84e2169b
SB		 1359
1360 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1361 REG_WRITE(ah, AR_RC, 0);
1362
d03a66c1 1363 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1364
1365 if (!ath9k_hw_wait(ah,
1366 AR_RTC_STATUS,
1367 AR_RTC_STATUS_M,
0caa7b14
S		 1368 AR_RTC_STATUS_ON,
1369 AH_WAIT_TIMEOUT)) {
d2182b69 1370 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1371 return false;
f078f209
LR		 1372 }
1373
f1dc5600
S		 1374 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1375}
1376
cbe61d8a 1377static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1378{
7a9233ff 1379 bool ret = false;
2577c6e8 1380
9a658d2b
LR		 1381 if (AR_SREV_9300_20_OR_LATER(ah)) {
1382 REG_WRITE(ah, AR_WA, ah->WARegVal);
1383 udelay(10);
1384 }
1385
f1dc5600
S		 1386 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1387 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1388
ceb26a60
FF		 1389 if (!ah->reset_power_on)
1390 type = ATH9K_RESET_POWER_ON;
1391
f1dc5600
S		 1392 switch (type) {
1393 case ATH9K_RESET_POWER_ON:
7a9233ff 1394 ret = ath9k_hw_set_reset_power_on(ah);
da8fb123 1395 if (ret)
ceb26a60 1396 ah->reset_power_on = true;
7a9233ff 1397 break;
f1dc5600
S		 1398 case ATH9K_RESET_WARM:
1399 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1400 ret = ath9k_hw_set_reset(ah, type);
1401 break;
f1dc5600 1402 default:
7a9233ff 1403 break;
f1dc5600 1404 }
7a9233ff 1405
7a9233ff 1406 return ret;
f078f209
LR		 1407}
1408
cbe61d8a 1409static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1410 struct ath9k_channel *chan)
f078f209 1411{
9c083af8
FF		 1412 int reset_type = ATH9K_RESET_WARM;
1413
1414 if (AR_SREV_9280(ah)) {
1415 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1416 reset_type = ATH9K_RESET_POWER_ON;
1417 else
1418 reset_type = ATH9K_RESET_COLD;
3412f2f0
FF		 1419 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1420 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1421 reset_type = ATH9K_RESET_COLD;
9c083af8
FF		 1422
1423 if (!ath9k_hw_set_reset_reg(ah, reset_type))
f1dc5600 1424 return false;
f078f209 1425
9ecdef4b 1426 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1427 return false;
f078f209 1428
2660b81a 1429 ah->chip_fullsleep = false;
bfc441a4
FF		 1430
1431 if (AR_SREV_9330(ah))
1432 ar9003_hw_internal_regulator_apply(ah);
f1dc5600 1433 ath9k_hw_init_pll(ah, chan);
f078f209 1434
f1dc5600 1435 return true;
f078f209
LR		 1436}
1437
cbe61d8a 1438static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1439 struct ath9k_channel *chan)
f078f209 1440{
c46917bb 1441 struct ath_common *common = ath9k_hw_common(ah);
b840cffe
SM		 1442 struct ath9k_hw_capabilities *pCap = &ah->caps;
1443 bool band_switch = false, mode_diff = false;
70e89a71 1444 u8 ini_reloaded = 0;
8fe65368 1445 u32 qnum;
0a3b7bac 1446 int r;
5f0c04ea 1447
b840cffe 1448 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
af02efb3
FF		 1449 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1450 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1451 mode_diff = !!(flags_diff & ~CHANNEL_HT);
b840cffe 1452 }
f078f209
LR		 1453
1454 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1455 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1456 ath_dbg(common, QUEUE,
226afe68 1457 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1458 return false;
1459 }
1460 }
1461
8fe65368 1462 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1463 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1464 return false;
1465 }
1466
b840cffe 1467 if (band_switch || mode_diff) {
5f0c04ea
RM		 1468 ath9k_hw_mark_phy_inactive(ah);
1469 udelay(5);
1470
5f35c0fa
SM		 1471 if (band_switch)
1472 ath9k_hw_init_pll(ah, chan);
5f0c04ea
RM		 1473
1474 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1475 ath_err(common, "Failed to do fast channel change\n");
1476 return false;
1477 }
1478 }
1479
8fe65368 1480 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1481
8fe65368 1482 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1483 if (r) {
3800276a 1484 ath_err(common, "Failed to set channel\n");
0a3b7bac 1485 return false;
f078f209 1486 }
dfdac8ac 1487 ath9k_hw_set_clockrate(ah);
64ea57d0 1488 ath9k_hw_apply_txpower(ah, chan, false);
f078f209 1489
81c507a8 1490 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1491 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1492
70e89a71
SM		 1493 if (band_switch || ini_reloaded)
1494 ah->eep_ops->set_board_values(ah, chan);
5f0c04ea 1495
70e89a71
SM		 1496 ath9k_hw_init_bb(ah, chan);
1497 ath9k_hw_rfbus_done(ah);
5f0c04ea 1498
70e89a71
SM		 1499 if (band_switch || ini_reloaded) {
1500 ah->ah_flags |= AH_FASTCC;
1501 ath9k_hw_init_cal(ah, chan);
a126ff51 1502 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1503 }
1504
f1dc5600
S		 1505 return true;
1506}
1507
691680b8
FF		 1508static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1509{
1510 u32 gpio_mask = ah->gpio_mask;
1511 int i;
1512
1513 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1514 if (!(gpio_mask & 1))
1515 continue;
1516
1517 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1518 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1519 }
1520}
1521
1e516ca7
SM		 1522void ath9k_hw_check_nav(struct ath_hw *ah)
1523{
1524 struct ath_common *common = ath9k_hw_common(ah);
1525 u32 val;
1526
1527 val = REG_READ(ah, AR_NAV);
1528 if (val != 0xdeadbeef && val > 0x7fff) {
1529 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1530 REG_WRITE(ah, AR_NAV, 0);
1531 }
1532}
1533EXPORT_SYMBOL(ath9k_hw_check_nav);
1534
c9c99e5e 1535bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1536{
c9c99e5e 1537 int count = 50;
d31a36a6 1538 u32 reg, last_val;
c9c99e5e 1539
01e18918
RM		 1540 if (AR_SREV_9300(ah))
1541 return !ath9k_hw_detect_mac_hang(ah);
1542
e17f83ea 1543 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1544 return true;
1545
d31a36a6 1546 last_val = REG_READ(ah, AR_OBS_BUS_1);
c9c99e5e
FF		 1547 do {
1548 reg = REG_READ(ah, AR_OBS_BUS_1);
d31a36a6
FF		 1549 if (reg != last_val)
1550 return true;
3b319aae 1551
105ff411 1552 udelay(1);
d31a36a6 1553 last_val = reg;
c9c99e5e
FF		 1554 if ((reg & 0x7E7FFFEF) == 0x00702400)
1555 continue;
1556
1557 switch (reg & 0x7E000B00) {
1558 case 0x1E000000:
1559 case 0x52000B00:
1560 case 0x18000B00:
1561 continue;
1562 default:
1563 return true;
1564 }
1565 } while (count-- > 0);
3b319aae 1566
c9c99e5e 1567 return false;
3b319aae 1568}
c9c99e5e 1569EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1570
15d2b585
SM		 1571static void ath9k_hw_init_mfp(struct ath_hw *ah)
1572{
1573 /* Setup MFP options for CCMP */
1574 if (AR_SREV_9280_20_OR_LATER(ah)) {
1575 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1576 * frames when constructing CCMP AAD. */
1577 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1578 0xc7ff);
1579 ah->sw_mgmt_crypto = false;
1580 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1581 /* Disable hardware crypto for management frames */
1582 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1583 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1584 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1585 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1586 ah->sw_mgmt_crypto = true;
1587 } else {
1588 ah->sw_mgmt_crypto = true;
1589 }
1590}
1591
1592static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1593 u32 macStaId1, u32 saveDefAntenna)
1594{
1595 struct ath_common *common = ath9k_hw_common(ah);
1596
1597 ENABLE_REGWRITE_BUFFER(ah);
1598
ecbbed32 1599 REG_RMW(ah, AR_STA_ID1, macStaId1
15d2b585 1600 | AR_STA_ID1_RTS_USE_DEF
ecbbed32
FF		 1601 | ah->sta_id1_defaults,
1602 ~AR_STA_ID1_SADH_MASK);
15d2b585
SM		 1603 ath_hw_setbssidmask(common);
1604 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1605 ath9k_hw_write_associd(ah);
1606 REG_WRITE(ah, AR_ISR, ~0);
1607 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1608
1609 REGWRITE_BUFFER_FLUSH(ah);
1610
1611 ath9k_hw_set_operating_mode(ah, ah->opmode);
1612}
1613
1614static void ath9k_hw_init_queues(struct ath_hw *ah)
1615{
1616 int i;
1617
1618 ENABLE_REGWRITE_BUFFER(ah);
1619
1620 for (i = 0; i < AR_NUM_DCU; i++)
1621 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1622
1623 REGWRITE_BUFFER_FLUSH(ah);
1624
1625 ah->intr_txqs = 0;
1626 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1627 ath9k_hw_resettxqueue(ah, i);
1628}
1629
1630/*
1631 * For big endian systems turn on swapping for descriptors
1632 */
1633static void ath9k_hw_init_desc(struct ath_hw *ah)
1634{
1635 struct ath_common *common = ath9k_hw_common(ah);
1636
1637 if (AR_SREV_9100(ah)) {
1638 u32 mask;
1639 mask = REG_READ(ah, AR_CFG);
1640 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1641 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1642 mask);
1643 } else {
1644 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1645 REG_WRITE(ah, AR_CFG, mask);
1646 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1647 REG_READ(ah, AR_CFG));
1648 }
1649 } else {
1650 if (common->bus_ops->ath_bus_type == ATH_USB) {
1651 /* Configure AR9271 target WLAN */
1652 if (AR_SREV_9271(ah))
1653 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1654 else
1655 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1656 }
1657#ifdef __BIG_ENDIAN
1658 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
2c323058 1659 AR_SREV_9550(ah) || AR_SREV_9531(ah))
15d2b585
SM		 1660 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1661 else
1662 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1663#endif
1664 }
1665}
1666
caed6579
SM		 1667/*
1668 * Fast channel change:
1669 * (Change synthesizer based on channel freq without resetting chip)
caed6579
SM		 1670 */
1671static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1672{
1673 struct ath_common *common = ath9k_hw_common(ah);
b840cffe 1674 struct ath9k_hw_capabilities *pCap = &ah->caps;
caed6579
SM		 1675 int ret;
1676
1677 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1678 goto fail;
1679
1680 if (ah->chip_fullsleep)
1681 goto fail;
1682
1683 if (!ah->curchan)
1684 goto fail;
1685
1686 if (chan->channel == ah->curchan->channel)
1687 goto fail;
1688
feb7bc99
FF		 1689 if ((ah->curchan->channelFlags | chan->channelFlags) &
1690 (CHANNEL_HALF | CHANNEL_QUARTER))
1691 goto fail;
1692
b840cffe 1693 /*
6b21fd20 1694 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
b840cffe 1695 */
6b21fd20 1696 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
af02efb3 1697 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
6b21fd20 1698 goto fail;
caed6579
SM		 1699
1700 if (!ath9k_hw_check_alive(ah))
1701 goto fail;
1702
1703 /*
1704 * For AR9462, make sure that calibration data for
1705 * re-using are present.
1706 */
8a90555f 1707 if (AR_SREV_9462(ah) && (ah->caldata &&
4b9b42bf
SM		 1708 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1709 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1710 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
caed6579
SM		 1711 goto fail;
1712
1713 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1714 ah->curchan->channel, chan->channel);
1715
1716 ret = ath9k_hw_channel_change(ah, chan);
1717 if (!ret)
1718 goto fail;
1719
5955b2b0 1720 if (ath9k_hw_mci_is_enabled(ah))
1bde95fa 1721 ar9003_mci_2g5g_switch(ah, false);
caed6579 1722
88033318
RM		 1723 ath9k_hw_loadnf(ah, ah->curchan);
1724 ath9k_hw_start_nfcal(ah, true);
1725
caed6579
SM		 1726 if (AR_SREV_9271(ah))
1727 ar9002_hw_load_ani_reg(ah, chan);
1728
1729 return 0;
1730fail:
1731 return -EINVAL;
1732}
1733
8d7e09dd
FF		 1734u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur)
1735{
1736 struct timespec ts;
1737 s64 usec;
1738
1739 if (!cur) {
1740 getrawmonotonic(&ts);
1741 cur = &ts;
1742 }
1743
1744 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000;
1745 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000;
1746
1747 return (u32) usec;
1748}
1749EXPORT_SYMBOL(ath9k_hw_get_tsf_offset);
1750
cbe61d8a 1751int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 1752 struct ath9k_hw_cal_data *caldata, bool fastcc)
f078f209 1753{
1510718d 1754 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1755 u32 saveLedState;
f078f209
LR		 1756 u32 saveDefAntenna;
1757 u32 macStaId1;
46fe782c 1758 u64 tsf = 0;
09d8e315 1759 s64 usec = 0;
15d2b585 1760 int r;
caed6579 1761 bool start_mci_reset = false;
63d32967
MSS		 1762 bool save_fullsleep = ah->chip_fullsleep;
1763
5955b2b0 1764 if (ath9k_hw_mci_is_enabled(ah)) {
528e5d36
SM		 1765 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1766 if (start_mci_reset)
1767 return 0;
63d32967
MSS		 1768 }
1769
9ecdef4b 1770 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1771 return -EIO;
f078f209 1772
caed6579
SM		 1773 if (ah->curchan && !ah->chip_fullsleep)
1774 ath9k_hw_getnf(ah, ah->curchan);
f078f209 1775
20bd2a09 1776 ah->caldata = caldata;
fcb9a3de 1777 if (caldata && (chan->channel != caldata->channel ||
6b21fd20 1778 chan->channelFlags != caldata->channelFlags)) {
20bd2a09
FF		 1779 /* Operating channel changed, reset channel calibration data */
1780 memset(caldata, 0, sizeof(*caldata));
1781 ath9k_init_nfcal_hist_buffer(ah, chan);
51dea9be 1782 } else if (caldata) {
4b9b42bf 1783 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
20bd2a09 1784 }
5bc225ac 1785 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
20bd2a09 1786
caed6579
SM		 1787 if (fastcc) {
1788 r = ath9k_hw_do_fastcc(ah, chan);
1789 if (!r)
1790 return r;
f078f209
LR		 1791 }
1792
5955b2b0 1793 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1794 ar9003_mci_stop_bt(ah, save_fullsleep);
63d32967 1795
f078f209
LR		 1796 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1797 if (saveDefAntenna == 0)
1798 saveDefAntenna = 1;
1799
1800 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1801
09d8e315
FF		 1802 /* Save TSF before chip reset, a cold reset clears it */
1803 tsf = ath9k_hw_gettsf64(ah);
6438e0dd 1804 usec = ktime_to_us(ktime_get_raw());
46fe782c 1805
f078f209
LR		 1806 saveLedState = REG_READ(ah, AR_CFG_LED) &
1807 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1808 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1809
1810 ath9k_hw_mark_phy_inactive(ah);
1811
45ef6a0b
VT		 1812 ah->paprd_table_write_done = false;
1813
05020d23 1814 /* Only required on the first reset */
d7e7d229
LR		 1815 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1816 REG_WRITE(ah,
1817 AR9271_RESET_POWER_DOWN_CONTROL,
1818 AR9271_RADIO_RF_RST);
1819 udelay(50);
1820 }
1821
f078f209 1822 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1823 ath_err(common, "Chip reset failed\n");
ae8d2858 1824 return -EINVAL;
f078f209
LR		 1825 }
1826
05020d23 1827 /* Only required on the first reset */
d7e7d229
LR		 1828 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1829 ah->htc_reset_init = false;
1830 REG_WRITE(ah,
1831 AR9271_RESET_POWER_DOWN_CONTROL,
1832 AR9271_GATE_MAC_CTL);
1833 udelay(50);
1834 }
1835
46fe782c 1836 /* Restore TSF */
6438e0dd 1837 usec = ktime_to_us(ktime_get_raw()) - usec;
09d8e315 1838 ath9k_hw_settsf64(ah, tsf + usec);
46fe782c 1839
7a37081e 1840 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1841 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1842
e9141f71
S		 1843 if (!AR_SREV_9300_20_OR_LATER(ah))
1844 ar9002_hw_enable_async_fifo(ah);
1845
25c56eec 1846 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1847 if (r)
1848 return r;
f078f209 1849
935d00cc
LB		 1850 ath9k_hw_set_rfmode(ah, chan);
1851
5955b2b0 1852 if (ath9k_hw_mci_is_enabled(ah))
63d32967
MSS		 1853 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1854
f860d526
FF		 1855 /*
1856 * Some AR91xx SoC devices frequently fail to accept TSF writes
1857 * right after the chip reset. When that happens, write a new
1858 * value after the initvals have been applied, with an offset
1859 * based on measured time difference
1860 */
1861 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1862 tsf += 1500;
1863 ath9k_hw_settsf64(ah, tsf);
1864 }
1865
15d2b585 1866 ath9k_hw_init_mfp(ah);
0ced0e17 1867
81c507a8 1868 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1869 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1870 ah->eep_ops->set_board_values(ah, chan);
a7765828 1871
15d2b585 1872 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
00e0003e 1873
8fe65368 1874 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1875 if (r)
1876 return r;
f078f209 1877
dfdac8ac
FF		 1878 ath9k_hw_set_clockrate(ah);
1879
15d2b585 1880 ath9k_hw_init_queues(ah);
2660b81a 1881 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1882 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1883 ath9k_hw_init_qos(ah);
1884
2660b81a 1885 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
55821324 1886 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3b319aae 1887
0005baf4 1888 ath9k_hw_init_global_settings(ah);
f078f209 1889
fe2b6afb
FF		 1890 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1891 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1892 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1893 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1894 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1895 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1896 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 1897 }
1898
ca7a4deb 1899 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1900
1901 ath9k_hw_set_dma(ah);
1902
ed6ebd8b
RM		 1903 if (!ath9k_hw_mci_is_enabled(ah))
1904 REG_WRITE(ah, AR_OBS, 8);
f078f209 1905
0ce024cb 1906 if (ah->config.rx_intr_mitigation) {
a64e1a45
SM		 1907 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
1908 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
f078f209
LR		 1909 }
1910
7f62a136
VT		 1911 if (ah->config.tx_intr_mitigation) {
1912 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1913 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1914 }
1915
f078f209
LR		 1916 ath9k_hw_init_bb(ah, chan);
1917
77a5a664 1918 if (caldata) {
4b9b42bf
SM		 1919 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
1920 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
77a5a664 1921 }
ae8d2858 1922 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1923 return -EIO;
f078f209 1924
5955b2b0 1925 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
528e5d36 1926 return -EIO;
63d32967 1927
7d0d0df0 1928 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1929
8fe65368 1930 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1931 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1932
7d0d0df0 1933 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1934
15d2b585 1935 ath9k_hw_init_desc(ah);
f078f209 1936
dbccdd1d 1937 if (ath9k_hw_btcoex_is_enabled(ah))
42cc41ed
VT		 1938 ath9k_hw_btcoex_enable(ah);
1939
5955b2b0 1940 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1941 ar9003_mci_check_bt(ah);
63d32967 1942
1fe860ed
RM		 1943 ath9k_hw_loadnf(ah, chan);
1944 ath9k_hw_start_nfcal(ah, true);
1945
a7abaf7d 1946 if (AR_SREV_9300_20_OR_LATER(ah))
aea702b7 1947 ar9003_hw_bb_watchdog_config(ah);
a7abaf7d
SM		 1948
1949 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
51ac8cbb 1950 ar9003_hw_disable_phy_restart(ah);
51ac8cbb 1951
691680b8
FF		 1952 ath9k_hw_apply_gpio_override(ah);
1953
7bdea96a 1954 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
362cd03f
SM		 1955 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
1956
4307b0fe
LB		 1957 if (ah->hw->conf.radar_enabled) {
1958 /* set HW specific DFS configuration */
1959 ath9k_hw_set_radar_params(ah);
1960 }
1961
ae8d2858 1962 return 0;
f078f209 1963}
7322fd19 1964EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1965
f1dc5600
S		 1966/******************************/
1967/* Power Management (Chipset) */
1968/******************************/
1969
42d5bc3f
LR		 1970/*
1971 * Notify Power Mgt is disabled in self-generated frames.
1972 * If requested, force chip to sleep.
1973 */
31604cf0 1974static void ath9k_set_power_sleep(struct ath_hw *ah)
f078f209 1975{
f1dc5600 1976 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2577c6e8 1977
a4a2954f 1978 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
153dccd4
RM		 1979 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
1980 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
1981 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
31604cf0
SM		 1982 /* xxx Required for WLAN only case ? */
1983 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
1984 udelay(100);
1985 }
2577c6e8 1986
31604cf0
SM		 1987 /*
1988 * Clear the RTC force wake bit to allow the
1989 * mac to go to sleep.
1990 */
1991 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1992
153dccd4 1993 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 1994 udelay(100);
2577c6e8 1995
31604cf0
SM		 1996 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1997 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 1998
31604cf0
SM		 1999 /* Shutdown chip. Active low */
2000 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2001 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2002 udelay(2);
f1dc5600 2003 }
9a658d2b
LR		 2004
2005 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 2006 if (AR_SREV_9300_20_OR_LATER(ah))
2007 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2008}
2009
bbd79af5
LR		 2010/*
2011 * Notify Power Management is enabled in self-generating
2012 * frames. If request, set power mode of chip to
2013 * auto/normal. Duration in units of 128us (1/8 TU).
2014 */
31604cf0 2015static void ath9k_set_power_network_sleep(struct ath_hw *ah)
f078f209 2016{
31604cf0 2017 struct ath9k_hw_capabilities *pCap = &ah->caps;
2577c6e8 2018
f1dc5600 2019 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2020
31604cf0
SM		 2021 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2022 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2023 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2024 AR_RTC_FORCE_WAKE_ON_INT);
2025 } else {
2577c6e8 2026
31604cf0
SM		 2027 /* When chip goes into network sleep, it could be waken
2028 * up by MCI_INT interrupt caused by BT's HW messages
2029 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2030 * rate (~100us). This will cause chip to leave and
2031 * re-enter network sleep mode frequently, which in
2032 * consequence will have WLAN MCI HW to generate lots of
2033 * SYS_WAKING and SYS_SLEEPING messages which will make
2034 * BT CPU to busy to process.
2035 */
153dccd4
RM		 2036 if (ath9k_hw_mci_is_enabled(ah))
2037 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2038 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
31604cf0
SM		 2039 /*
2040 * Clear the RTC force wake bit to allow the
2041 * mac to go to sleep.
2042 */
153dccd4 2043 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
31604cf0 2044
153dccd4 2045 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2046 udelay(30);
f078f209 2047 }
9a658d2b
LR		 2048
2049 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2050 if (AR_SREV_9300_20_OR_LATER(ah))
2051 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2052}
2053
31604cf0 2054static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
f078f209 2055{
f1dc5600
S		 2056 u32 val;
2057 int i;
f078f209 2058
9a658d2b
LR		 2059 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2060 if (AR_SREV_9300_20_OR_LATER(ah)) {
2061 REG_WRITE(ah, AR_WA, ah->WARegVal);
2062 udelay(10);
2063 }
2064
31604cf0
SM		 2065 if ((REG_READ(ah, AR_RTC_STATUS) &
2066 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2067 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2068 return false;
f1dc5600 2069 }
31604cf0
SM		 2070 if (!AR_SREV_9300_20_OR_LATER(ah))
2071 ath9k_hw_init_pll(ah, NULL);
2072 }
2073 if (AR_SREV_9100(ah))
2074 REG_SET_BIT(ah, AR_RTC_RESET,
2075 AR_RTC_RESET_EN);
2076
2077 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2078 AR_RTC_FORCE_WAKE_EN);
04575f21 2079 if (AR_SREV_9100(ah))
3683a07b 2080 mdelay(10);
04575f21
SM		 2081 else
2082 udelay(50);
f078f209 2083
31604cf0
SM		 2084 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2085 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2086 if (val == AR_RTC_STATUS_ON)
2087 break;
2088 udelay(50);
f1dc5600
S		 2089 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2090 AR_RTC_FORCE_WAKE_EN);
31604cf0
SM		 2091 }
2092 if (i == 0) {
2093 ath_err(ath9k_hw_common(ah),
2094 "Failed to wakeup in %uus\n",
2095 POWER_UP_TIME / 20);
2096 return false;
f078f209
LR		 2097 }
2098
cdbe408d
RM		 2099 if (ath9k_hw_mci_is_enabled(ah))
2100 ar9003_mci_set_power_awake(ah);
2101
f1dc5600 2102 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2103
f1dc5600 2104 return true;
f078f209
LR		 2105}
2106
9ecdef4b 2107bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2108{
c46917bb 2109 struct ath_common *common = ath9k_hw_common(ah);
31604cf0 2110 int status = true;
f1dc5600
S		 2111 static const char *modes[] = {
2112 "AWAKE",
2113 "FULL-SLEEP",
2114 "NETWORK SLEEP",
2115 "UNDEFINED"
2116 };
f1dc5600 2117
cbdec975
GJ		 2118 if (ah->power_mode == mode)
2119 return status;
2120
d2182b69 2121 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2122 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2123
2124 switch (mode) {
2125 case ATH9K_PM_AWAKE:
31604cf0 2126 status = ath9k_hw_set_power_awake(ah);
f1dc5600
S		 2127 break;
2128 case ATH9K_PM_FULL_SLEEP:
5955b2b0 2129 if (ath9k_hw_mci_is_enabled(ah))
d1ca8b8e 2130 ar9003_mci_set_full_sleep(ah);
1010911e 2131
31604cf0 2132 ath9k_set_power_sleep(ah);
2660b81a 2133 ah->chip_fullsleep = true;
f1dc5600
S		 2134 break;
2135 case ATH9K_PM_NETWORK_SLEEP:
31604cf0 2136 ath9k_set_power_network_sleep(ah);
f1dc5600 2137 break;
f078f209 2138 default:
3800276a 2139 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2140 return false;
2141 }
2660b81a 2142 ah->power_mode = mode;
f1dc5600 2143
69f4aab1
LR		 2144 /*
2145 * XXX: If this warning never comes up after a while then
2146 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2147 * ath9k_hw_setpower() return type void.
2148 */
97dcec57
SM		 2149
2150 if (!(ah->ah_flags & AH_UNPLUGGED))
2151 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2152
f1dc5600 2153 return status;
f078f209 2154}
7322fd19 2155EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2156
f1dc5600
S		 2157/*******************/
2158/* Beacon Handling */
2159/*******************/
2160
cbe61d8a 2161void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2162{
f078f209
LR		 2163 int flags = 0;
2164
7d0d0df0
S		 2165 ENABLE_REGWRITE_BUFFER(ah);
2166
2660b81a 2167 switch (ah->opmode) {
d97809db 2168 case NL80211_IFTYPE_ADHOC:
f078f209
LR		 2169 REG_SET_BIT(ah, AR_TXCFG,
2170 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2664d666 2171 case NL80211_IFTYPE_MESH_POINT:
d97809db 2172 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2173 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2174 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2175 TU_TO_USEC(ah->config.dma_beacon_response_time));
2176 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2177 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2178 flags |=
2179 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2180 break;
d97809db 2181 default:
d2182b69
JP		 2182 ath_dbg(ath9k_hw_common(ah), BEACON,
2183 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2184 return;
2185 break;
f078f209
LR		 2186 }
2187
dd347f2f
FF		 2188 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2189 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2190 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
f078f209 2191
7d0d0df0 2192 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2193
f078f209
LR		 2194 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2195}
7322fd19 2196EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2197
cbe61d8a 2198void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2199 const struct ath9k_beacon_state *bs)
f078f209
LR		 2200{
2201 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2202 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2203 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2204
7d0d0df0
S		 2205 ENABLE_REGWRITE_BUFFER(ah);
2206
4ed15762
FF		 2207 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2208 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2209 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
f078f209 2210
7d0d0df0 2211 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2212
f078f209
LR		 2213 REG_RMW_FIELD(ah, AR_RSSI_THR,
2214 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2215
f29f5c08 2216 beaconintval = bs->bs_intval;
f078f209
LR		 2217
2218 if (bs->bs_sleepduration > beaconintval)
2219 beaconintval = bs->bs_sleepduration;
2220
2221 dtimperiod = bs->bs_dtimperiod;
2222 if (bs->bs_sleepduration > dtimperiod)
2223 dtimperiod = bs->bs_sleepduration;
2224
2225 if (beaconintval == dtimperiod)
2226 nextTbtt = bs->bs_nextdtim;
2227 else
2228 nextTbtt = bs->bs_nexttbtt;
2229
d2182b69
JP		 2230 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2231 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2232 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2233 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2234
7d0d0df0
S		 2235 ENABLE_REGWRITE_BUFFER(ah);
2236
4ed15762
FF		 2237 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2238 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
f078f209 2239
f1dc5600
S		 2240 REG_WRITE(ah, AR_SLEEP1,
2241 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2242 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2243
f1dc5600
S		 2244 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2245 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2246 else
2247 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2248
f1dc5600
S		 2249 REG_WRITE(ah, AR_SLEEP2,
2250 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2251
4ed15762
FF		 2252 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2253 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
f078f209 2254
7d0d0df0 2255 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2256
f1dc5600
S		 2257 REG_SET_BIT(ah, AR_TIMER_MODE,
2258 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2259 AR_DTIM_TIMER_EN);
f078f209 2260
4af9cf4f
S		 2261 /* TSF Out of Range Threshold */
2262 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2263}
7322fd19 2264EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2265
f1dc5600
S		 2266/*******************/
2267/* HW Capabilities */
2268/*******************/
2269
6054069a
FF		 2270static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2271{
2272 eeprom_chainmask &= chip_chainmask;
2273 if (eeprom_chainmask)
2274 return eeprom_chainmask;
2275 else
2276 return chip_chainmask;
2277}
2278
9a66af33
ZK		 2279/**
2280 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2281 * @ah: the atheros hardware data structure
2282 *
2283 * We enable DFS support upstream on chipsets which have passed a series
2284 * of tests. The testing requirements are going to be documented. Desired
2285 * test requirements are documented at:
2286 *
2287 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2288 *
2289 * Once a new chipset gets properly tested an individual commit can be used
2290 * to document the testing for DFS for that chipset.
2291 */
2292static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2293{
2294
2295 switch (ah->hw_version.macVersion) {
73e4937d
ZK		 2296 /* for temporary testing DFS with 9280 */
2297 case AR_SREV_VERSION_9280:
9a66af33
ZK		 2298 /* AR9580 will likely be our first target to get testing on */
2299 case AR_SREV_VERSION_9580:
73e4937d 2300 return true;
9a66af33
ZK		 2301 default:
2302 return false;
2303 }
2304}
2305
a9a29ce6 2306int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2307{
2660b81a 2308 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2309 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2310 struct ath_common *common = ath9k_hw_common(ah);
6054069a 2311 unsigned int chip_chainmask;
608b88cb 2312
0ff2b5c0 2313 u16 eeval;
47c80de6 2314 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2315
f74df6fb 2316 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2317 regulatory->current_rd = eeval;
f078f209 2318
2660b81a 2319 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2320 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2321 if (regulatory->current_rd == 0x64 ||
2322 regulatory->current_rd == 0x65)
2323 regulatory->current_rd += 5;
2324 else if (regulatory->current_rd == 0x41)
2325 regulatory->current_rd = 0x43;
d2182b69
JP		 2326 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2327 regulatory->current_rd);
f1dc5600 2328 }
f078f209 2329
f74df6fb 2330 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6 2331 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3800276a
JP		 2332 ath_err(common,
2333 "no band has been marked as supported in EEPROM\n");
a9a29ce6
GJ		 2334 return -EINVAL;
2335 }
2336
d4659912
FF		 2337 if (eeval & AR5416_OPFLAGS_11A)
2338 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 2339
d4659912
FF		 2340 if (eeval & AR5416_OPFLAGS_11G)
2341 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 2342
e41db61d
SM		 2343 if (AR_SREV_9485(ah) ||
2344 AR_SREV_9285(ah) ||
2345 AR_SREV_9330(ah) ||
2346 AR_SREV_9565(ah))
6054069a 2347 chip_chainmask = 1;
ba5736a5
MSS		 2348 else if (AR_SREV_9462(ah))
2349 chip_chainmask = 3;
6054069a
FF		 2350 else if (!AR_SREV_9280_20_OR_LATER(ah))
2351 chip_chainmask = 7;
2352 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2353 chip_chainmask = 3;
2354 else
2355 chip_chainmask = 7;
2356
f74df6fb 2357 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2358 /*
2359 * For AR9271 we will temporarilly uses the rx chainmax as read from
2360 * the EEPROM.
2361 */
8147f5de 2362 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2363 !(eeval & AR5416_OPFLAGS_11A) &&
2364 !(AR_SREV_9271(ah)))
2365 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2366 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2367 else if (AR_SREV_9100(ah))
2368 pCap->rx_chainmask = 0x7;
8147f5de 2369 else
d7e7d229 2370 /* Use rx_chainmask from EEPROM. */
8147f5de 2371 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2372
6054069a
FF		 2373 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2374 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2375 ah->txchainmask = pCap->tx_chainmask;
2376 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2377
7a37081e 2378 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2379
02d2ebb2
FF		 2380 /* enable key search for every frame in an aggregate */
2381 if (AR_SREV_9300_20_OR_LATER(ah))
2382 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2383
ce2220d1
BR		 2384 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2385
0db156e9 2386 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2387 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2388 else
2389 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2390
5b5fa355
S		 2391 if (AR_SREV_9271(ah))
2392 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 2393 else if (AR_DEVID_7010(ah))
2394 pCap->num_gpio_pins = AR7010_NUM_GPIO;
6321eb09
MSS		 2395 else if (AR_SREV_9300_20_OR_LATER(ah))
2396 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2397 else if (AR_SREV_9287_11_OR_LATER(ah))
2398 pCap->num_gpio_pins = AR9287_NUM_GPIO;
e17f83ea 2399 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2400 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 2401 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 2402 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2403 else
2404 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2405
1b2538b2 2406 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2407 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2408 else
f1dc5600 2409 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2410
74e13060 2411#ifdef CONFIG_ATH9K_RFKILL
2660b81a
S		 2412 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2413 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2414 ah->rfkill_gpio =
2415 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2416 ah->rfkill_polarity =
2417 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2418
2419 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2420 }
f1dc5600 2421#endif
d5d1154f 2422 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2423 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2424 else
2425 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2426
e7594072 2427 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2428 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2429 else
2430 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2431
ceb26445 2432 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2433 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
a4a2954f 2434 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
784ad503
VT		 2435 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2436
ceb26445
VT		 2437 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2438 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2439 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2440 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2441 pCap->txs_len = sizeof(struct ar9003_txs);
162c3be3
VT		 2442 } else {
2443 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2444 if (AR_SREV_9280_20(ah))
6b42e8d0 2445 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2446 }
1adf02ff 2447
6c84ce08
VT		 2448 if (AR_SREV_9300_20_OR_LATER(ah))
2449 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2450
6ee63f55
SB		 2451 if (AR_SREV_9300_20_OR_LATER(ah))
2452 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2453
a42acef0 2454 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2455 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2456
f85c3371 2457 if (AR_SREV_9285(ah)) {
754dc536
VT		 2458 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2459 ant_div_ctl1 =
2460 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2461 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
754dc536 2462 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2463 ath_info(common, "Enable LNA combining\n");
2464 }
754dc536 2465 }
f85c3371
SM		 2466 }
2467
ea066d5a
MSS		 2468 if (AR_SREV_9300_20_OR_LATER(ah)) {
2469 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2470 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2471 }
2472
06236e53 2473 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
21d2c63a 2474 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2475 if ((ant_div_ctl1 >> 0x6) == 0x3) {
21d2c63a 2476 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2477 ath_info(common, "Enable LNA combining\n");
2478 }
21d2c63a 2479 }
754dc536 2480
9a66af33
ZK		 2481 if (ath9k_hw_dfs_tested(ah))
2482 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2483
47c80de6
VT		 2484 tx_chainmask = pCap->tx_chainmask;
2485 rx_chainmask = pCap->rx_chainmask;
2486 while (tx_chainmask || rx_chainmask) {
2487 if (tx_chainmask & BIT(0))
2488 pCap->max_txchains++;
2489 if (rx_chainmask & BIT(0))
2490 pCap->max_rxchains++;
2491
2492 tx_chainmask >>= 1;
2493 rx_chainmask >>= 1;
2494 }
2495
a4a2954f 2496 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3789d59c
MSS		 2497 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2498 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2499
2b5e54e2 2500 if (AR_SREV_9462_20_OR_LATER(ah))
3789d59c 2501 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
3789d59c
MSS		 2502 }
2503
846e438f
SM		 2504 if (AR_SREV_9462(ah))
2505 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE;
d687809b 2506
0f21ee8d
SM		 2507 if (AR_SREV_9300_20_OR_LATER(ah) &&
2508 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2509 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2510
a9a29ce6 2511 return 0;
f078f209
LR		 2512}
2513
f1dc5600
S		 2514/****************************/
2515/* GPIO / RFKILL / Antennae */
2516/****************************/
f078f209 2517
cbe61d8a 2518static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2519 u32 gpio, u32 type)
2520{
2521 int addr;
2522 u32 gpio_shift, tmp;
f078f209 2523
f1dc5600
S		 2524 if (gpio > 11)
2525 addr = AR_GPIO_OUTPUT_MUX3;
2526 else if (gpio > 5)
2527 addr = AR_GPIO_OUTPUT_MUX2;
2528 else
2529 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2530
f1dc5600 2531 gpio_shift = (gpio % 6) * 5;
f078f209 2532
f1dc5600
S		 2533 if (AR_SREV_9280_20_OR_LATER(ah)
2534 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2535 REG_RMW(ah, addr, (type << gpio_shift),
2536 (0x1f << gpio_shift));
f078f209 2537 } else {
f1dc5600
S		 2538 tmp = REG_READ(ah, addr);
2539 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2540 tmp &= ~(0x1f << gpio_shift);
2541 tmp |= (type << gpio_shift);
2542 REG_WRITE(ah, addr, tmp);
f078f209 2543 }
f078f209
LR		 2544}
2545
cbe61d8a 2546void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2547{
f1dc5600 2548 u32 gpio_shift;
f078f209 2549
9680e8a3 2550 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2551
88c1f4f6
S		 2552 if (AR_DEVID_7010(ah)) {
2553 gpio_shift = gpio;
2554 REG_RMW(ah, AR7010_GPIO_OE,
2555 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2556 (AR7010_GPIO_OE_MASK << gpio_shift));
2557 return;
2558 }
f078f209 2559
88c1f4f6 2560 gpio_shift = gpio << 1;
f1dc5600
S		 2561 REG_RMW(ah,
2562 AR_GPIO_OE_OUT,
2563 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2564 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2565}
7322fd19 2566EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2567
cbe61d8a 2568u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2569{
cb33c412
SB		 2570#define MS_REG_READ(x, y) \
2571 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2572
2660b81a 2573 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2574 return 0xffffffff;
f078f209 2575
88c1f4f6
S		 2576 if (AR_DEVID_7010(ah)) {
2577 u32 val;
2578 val = REG_READ(ah, AR7010_GPIO_IN);
2579 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2580 } else if (AR_SREV_9300_20_OR_LATER(ah))
9306990a
VT		 2581 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2582 AR_GPIO_BIT(gpio)) != 0;
783dfca1 2583 else if (AR_SREV_9271(ah))
5b5fa355 2584 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2585 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2586 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2587 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2588 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2589 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2590 return MS_REG_READ(AR928X, gpio) != 0;
2591 else
2592 return MS_REG_READ(AR, gpio) != 0;
f078f209 2593}
7322fd19 2594EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2595
cbe61d8a 2596void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2597 u32 ah_signal_type)
f078f209 2598{
f1dc5600 2599 u32 gpio_shift;
f078f209 2600
88c1f4f6
S		 2601 if (AR_DEVID_7010(ah)) {
2602 gpio_shift = gpio;
2603 REG_RMW(ah, AR7010_GPIO_OE,
2604 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2605 (AR7010_GPIO_OE_MASK << gpio_shift));
2606 return;
2607 }
f078f209 2608
88c1f4f6 2609 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2610 gpio_shift = 2 * gpio;
f1dc5600
S		 2611 REG_RMW(ah,
2612 AR_GPIO_OE_OUT,
2613 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2614 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2615}
7322fd19 2616EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2617
cbe61d8a 2618void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2619{
88c1f4f6
S		 2620 if (AR_DEVID_7010(ah)) {
2621 val = val ? 0 : 1;
2622 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2623 AR_GPIO_BIT(gpio));
2624 return;
2625 }
2626
5b5fa355
S		 2627 if (AR_SREV_9271(ah))
2628 val = ~val;
2629
f1dc5600
S		 2630 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2631 AR_GPIO_BIT(gpio));
f078f209 2632}
7322fd19 2633EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2634
cbe61d8a 2635void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2636{
f1dc5600 2637 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2638}
7322fd19 2639EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2640
f1dc5600
S		 2641/*********************/
2642/* General Operation */
2643/*********************/
2644
cbe61d8a 2645u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2646{
f1dc5600
S		 2647 u32 bits = REG_READ(ah, AR_RX_FILTER);
2648 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2649
f1dc5600
S		 2650 if (phybits & AR_PHY_ERR_RADAR)
2651 bits |= ATH9K_RX_FILTER_PHYRADAR;
2652 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2653 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2654
f1dc5600 2655 return bits;
f078f209 2656}
7322fd19 2657EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2658
cbe61d8a 2659void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2660{
f1dc5600 2661 u32 phybits;
f078f209 2662
7d0d0df0
S		 2663 ENABLE_REGWRITE_BUFFER(ah);
2664
a4a2954f 2665 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2577c6e8
SB		 2666 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2667
7ea310be
S		 2668 REG_WRITE(ah, AR_RX_FILTER, bits);
2669
f1dc5600
S		 2670 phybits = 0;
2671 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2672 phybits |= AR_PHY_ERR_RADAR;
2673 if (bits & ATH9K_RX_FILTER_PHYERR)
2674 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2675 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2676
f1dc5600 2677 if (phybits)
ca7a4deb 2678 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2679 else
ca7a4deb 2680 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2681
2682 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2683}
7322fd19 2684EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2685
cbe61d8a 2686bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2687{
99922a45
RM		 2688 if (ath9k_hw_mci_is_enabled(ah))
2689 ar9003_mci_bt_gain_ctrl(ah);
2690
63a75b91
SB		 2691 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2692 return false;
2693
2694 ath9k_hw_init_pll(ah, NULL);
8efa7a81 2695 ah->htc_reset_init = true;
63a75b91 2696 return true;
f1dc5600 2697}
7322fd19 2698EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2699
cbe61d8a 2700bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2701{
9ecdef4b 2702 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2703 return false;
f078f209 2704
63a75b91
SB		 2705 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2706 return false;
2707
2708 ath9k_hw_init_pll(ah, NULL);
2709 return true;
f078f209 2710}
7322fd19 2711EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2712
ca2c68cc
FF		 2713static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2714{
2715 enum eeprom_param gain_param;
2716
2717 if (IS_CHAN_2GHZ(chan))
2718 gain_param = EEP_ANTENNA_GAIN_2G;
2719 else
2720 gain_param = EEP_ANTENNA_GAIN_5G;
2721
2722 return ah->eep_ops->get_eeprom(ah, gain_param);
2723}
2724
64ea57d0
GJ		 2725void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2726 bool test)
ca2c68cc
FF		 2727{
2728 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2729 struct ieee80211_channel *channel;
2730 int chan_pwr, new_pwr, max_gain;
2731 int ant_gain, ant_reduction = 0;
2732
2733 if (!chan)
2734 return;
2735
2736 channel = chan->chan;
2737 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2738 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2739 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2740
2741 ant_gain = get_antenna_gain(ah, chan);
2742 if (ant_gain > max_gain)
2743 ant_reduction = ant_gain - max_gain;
2744
2745 ah->eep_ops->set_txpower(ah, chan,
2746 ath9k_regd_get_ctl(reg, chan),
64ea57d0 2747 ant_reduction, new_pwr, test);
ca2c68cc
FF		 2748}
2749
de40f316 2750void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2751{
ca2c68cc 2752 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2753 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2754 struct ieee80211_channel *channel = chan->chan;
9c204b46 2755
48ef5c42 2756 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2757 if (test)
ca2c68cc 2758 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2759
64ea57d0 2760 ath9k_hw_apply_txpower(ah, chan, test);
6f255425 2761
ca2c68cc
FF		 2762 if (test)
2763 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2764}
7322fd19 2765EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2766
cbe61d8a 2767void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2768{
2660b81a 2769 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2770}
7322fd19 2771EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2772
cbe61d8a 2773void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2774{
f1dc5600
S		 2775 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2776 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2777}
7322fd19 2778EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2779
f2b2143e 2780void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2781{
1510718d
LR		 2782 struct ath_common *common = ath9k_hw_common(ah);
2783
2784 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2785 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2786 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2787}
7322fd19 2788EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2789
1c0fc65e
BP		 2790#define ATH9K_MAX_TSF_READ 10
2791
cbe61d8a 2792u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2793{
1c0fc65e
BP		 2794 u32 tsf_lower, tsf_upper1, tsf_upper2;
2795 int i;
2796
2797 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2798 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2799 tsf_lower = REG_READ(ah, AR_TSF_L32);
2800 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2801 if (tsf_upper2 == tsf_upper1)
2802 break;
2803 tsf_upper1 = tsf_upper2;
2804 }
f078f209 2805
1c0fc65e 2806 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2807
1c0fc65e 2808 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2809}
7322fd19 2810EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2811
cbe61d8a 2812void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2813{
27abe060 2814 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2815 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2816}
7322fd19 2817EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2818
cbe61d8a 2819void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2820{
f9b604f6
GJ		 2821 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2822 AH_TSF_WRITE_TIMEOUT))
d2182b69 2823 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 2824 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2825
f1dc5600
S		 2826 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2827}
7322fd19 2828EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2829
60ca9f87 2830void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
f1dc5600 2831{
60ca9f87 2832 if (set)
2660b81a 2833 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2834 else
2660b81a 2835 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2836}
7322fd19 2837EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2838
e4744ec7 2839void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 2840{
2841 u32 macmode;
2842
e4744ec7 2843 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2844 macmode = AR_2040_JOINED_RX_CLEAR;
2845 else
2846 macmode = 0;
f078f209 2847
f1dc5600 2848 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2849}
ff155a45
VT		 2850
2851/* HW Generic timers configuration */
2852
2853static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2854{
2855 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2856 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2857 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2858 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2859 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2860 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2861 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2862 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2863 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2864 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2865 AR_NDP2_TIMER_MODE, 0x0002},
2866 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2867 AR_NDP2_TIMER_MODE, 0x0004},
2868 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2869 AR_NDP2_TIMER_MODE, 0x0008},
2870 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2871 AR_NDP2_TIMER_MODE, 0x0010},
2872 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2873 AR_NDP2_TIMER_MODE, 0x0020},
2874 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2875 AR_NDP2_TIMER_MODE, 0x0040},
2876 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2877 AR_NDP2_TIMER_MODE, 0x0080}
2878};
2879
2880/* HW generic timer primitives */
2881
dd347f2f 2882u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2883{
2884 return REG_READ(ah, AR_TSF_L32);
2885}
dd347f2f 2886EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2887
2888struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2889 void (*trigger)(void *),
2890 void (*overflow)(void *),
2891 void *arg,
2892 u8 timer_index)
2893{
2894 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2895 struct ath_gen_timer *timer;
2896
c67ce339
FF		 2897 if ((timer_index < AR_FIRST_NDP_TIMER) ||
2898 (timer_index >= ATH_MAX_GEN_TIMER))
2899 return NULL;
2900
ff155a45 2901 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
14f8dc49 2902 if (timer == NULL)
ff155a45 2903 return NULL;
ff155a45
VT		 2904
2905 /* allocate a hardware generic timer slot */
2906 timer_table->timers[timer_index] = timer;
2907 timer->index = timer_index;
2908 timer->trigger = trigger;
2909 timer->overflow = overflow;
2910 timer->arg = arg;
2911
2912 return timer;
2913}
7322fd19 2914EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2915
cd9bf689
LR		 2916void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2917 struct ath_gen_timer *timer,
c67ce339 2918 u32 timer_next,
cd9bf689 2919 u32 timer_period)
ff155a45
VT		 2920{
2921 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
c67ce339 2922 u32 mask = 0;
788f6875 2923
c67ce339 2924 timer_table->timer_mask |= BIT(timer->index);
ff155a45 2925
ff155a45
VT		 2926 /*
2927 * Program generic timer registers
2928 */
2929 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2930 timer_next);
2931 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2932 timer_period);
2933 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2934 gen_tmr_configuration[timer->index].mode_mask);
2935
a4a2954f 2936 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2577c6e8 2937 /*
423e38e8 2938 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 2939 * to use. But we still follow the old rule, 0 - 7 use tsf and
2940 * 8 - 15 use tsf2.
2941 */
2942 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
2943 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2944 (1 << timer->index));
2945 else
2946 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2947 (1 << timer->index));
2948 }
2949
c67ce339
FF		 2950 if (timer->trigger)
2951 mask |= SM(AR_GENTMR_BIT(timer->index),
2952 AR_IMR_S5_GENTIMER_TRIG);
2953 if (timer->overflow)
2954 mask |= SM(AR_GENTMR_BIT(timer->index),
2955 AR_IMR_S5_GENTIMER_THRESH);
2956
2957 REG_SET_BIT(ah, AR_IMR_S5, mask);
2958
2959 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
2960 ah->imask |= ATH9K_INT_GENTIMER;
2961 ath9k_hw_set_interrupts(ah);
2962 }
ff155a45 2963}
7322fd19 2964EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 2965
cd9bf689 2966void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 2967{
2968 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2969
ff155a45
VT		 2970 /* Clear generic timer enable bits. */
2971 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2972 gen_tmr_configuration[timer->index].mode_mask);
2973
b7f59766
SM		 2974 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2975 /*
2976 * Need to switch back to TSF if it was using TSF2.
2977 */
2978 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
2979 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2980 (1 << timer->index));
2981 }
2982 }
2983
ff155a45
VT		 2984 /* Disable both trigger and thresh interrupt masks */
2985 REG_CLR_BIT(ah, AR_IMR_S5,
2986 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2987 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2988
c67ce339
FF		 2989 timer_table->timer_mask &= ~BIT(timer->index);
2990
2991 if (timer_table->timer_mask == 0) {
2992 ah->imask &= ~ATH9K_INT_GENTIMER;
2993 ath9k_hw_set_interrupts(ah);
2994 }
ff155a45 2995}
7322fd19 2996EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 2997
2998void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2999{
3000 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3001
3002 /* free the hardware generic timer slot */
3003 timer_table->timers[timer->index] = NULL;
3004 kfree(timer);
3005}
7322fd19 3006EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3007
3008/*
3009 * Generic Timer Interrupts handling
3010 */
3011void ath_gen_timer_isr(struct ath_hw *ah)
3012{
3013 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3014 struct ath_gen_timer *timer;
c67ce339
FF		 3015 unsigned long trigger_mask, thresh_mask;
3016 unsigned int index;
ff155a45
VT		 3017
3018 /* get hardware generic timer interrupt status */
3019 trigger_mask = ah->intr_gen_timer_trigger;
3020 thresh_mask = ah->intr_gen_timer_thresh;
c67ce339
FF		 3021 trigger_mask &= timer_table->timer_mask;
3022 thresh_mask &= timer_table->timer_mask;
ff155a45 3023
c67ce339 3024 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3025 timer = timer_table->timers[index];
c67ce339
FF		 3026 if (!timer)
3027 continue;
3028 if (!timer->overflow)
3029 continue;
a6a172b2
FF		 3030
3031 trigger_mask &= ~BIT(index);
ff155a45
VT		 3032 timer->overflow(timer->arg);
3033 }
3034
c67ce339 3035 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3036 timer = timer_table->timers[index];
c67ce339
FF		 3037 if (!timer)
3038 continue;
3039 if (!timer->trigger)
3040 continue;
ff155a45
VT		 3041 timer->trigger(timer->arg);
3042 }
3043}
7322fd19 3044EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3045
05020d23
S		 3046/********/
3047/* HTC */
3048/********/
3049
2da4f01a
LR		 3050static struct {
3051 u32 version;
3052 const char * name;
3053} ath_mac_bb_names[] = {
3054 /* Devices with external radios */
3055 { AR_SREV_VERSION_5416_PCI, "5416" },
3056 { AR_SREV_VERSION_5416_PCIE, "5418" },
3057 { AR_SREV_VERSION_9100, "9100" },
3058 { AR_SREV_VERSION_9160, "9160" },
3059 /* Single-chip solutions */
3060 { AR_SREV_VERSION_9280, "9280" },
3061 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3062 { AR_SREV_VERSION_9287, "9287" },
3063 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3064 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3065 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3066 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3067 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3068 { AR_SREV_VERSION_9462, "9462" },
485124cb 3069 { AR_SREV_VERSION_9550, "9550" },
77fac465 3070 { AR_SREV_VERSION_9565, "9565" },
c08148bb 3071 { AR_SREV_VERSION_9531, "9531" },
2da4f01a
LR		 3072};
3073
3074/* For devices with external radios */
3075static struct {
3076 u16 version;
3077 const char * name;
3078} ath_rf_names[] = {
3079 { 0, "5133" },
3080 { AR_RAD5133_SREV_MAJOR, "5133" },
3081 { AR_RAD5122_SREV_MAJOR, "5122" },
3082 { AR_RAD2133_SREV_MAJOR, "2133" },
3083 { AR_RAD2122_SREV_MAJOR, "2122" }
3084};
3085
3086/*
3087 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3088 */
f934c4d9 3089static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3090{
3091 int i;
3092
3093 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3094 if (ath_mac_bb_names[i].version == mac_bb_version) {
3095 return ath_mac_bb_names[i].name;
3096 }
3097 }
3098
3099 return "????";
3100}
2da4f01a
LR		 3101
3102/*
3103 * Return the RF name. "????" is returned if the RF is unknown.
3104 * Used for devices with external radios.
3105 */
f934c4d9 3106static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3107{
3108 int i;
3109
3110 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3111 if (ath_rf_names[i].version == rf_version) {
3112 return ath_rf_names[i].name;
3113 }
3114 }
3115
3116 return "????";
3117}
f934c4d9
LR		 3118
3119void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3120{
3121 int used;
3122
3123 /* chipsets >= AR9280 are single-chip */
7a37081e 3124 if (AR_SREV_9280_20_OR_LATER(ah)) {
5e88ba62
ZK		 3125 used = scnprintf(hw_name, len,
3126 "Atheros AR%s Rev:%x",
3127 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3128 ah->hw_version.macRev);
f934c4d9
LR		 3129 }
3130 else {
5e88ba62
ZK		 3131 used = scnprintf(hw_name, len,
3132 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3133 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3134 ah->hw_version.macRev,
3135 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3136 & AR_RADIO_SREV_MAJOR)),
3137 ah->hw_version.phyRev);
f934c4d9
LR		 3138 }
3139
3140 hw_name[used] = '\0';
3141}
3142EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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