Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
b3950e6a | 2 | * Copyright (c) 2008-2010 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/io.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
f078f209 LR |
19 | #include <asm/unaligned.h> |
20 | ||
af03abec | 21 | #include "hw.h" |
d70357d5 | 22 | #include "hw-ops.h" |
cfe8cba9 | 23 | #include "rc.h" |
b622a720 | 24 | #include "ar9003_mac.h" |
f078f209 | 25 | |
cbe61d8a | 26 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); |
f078f209 | 27 | |
7322fd19 LR |
28 | MODULE_AUTHOR("Atheros Communications"); |
29 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
30 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
31 | MODULE_LICENSE("Dual BSD/GPL"); | |
32 | ||
33 | static int __init ath9k_init(void) | |
34 | { | |
35 | return 0; | |
36 | } | |
37 | module_init(ath9k_init); | |
38 | ||
39 | static void __exit ath9k_exit(void) | |
40 | { | |
41 | return; | |
42 | } | |
43 | module_exit(ath9k_exit); | |
44 | ||
d70357d5 LR |
45 | /* Private hardware callbacks */ |
46 | ||
47 | static void ath9k_hw_init_cal_settings(struct ath_hw *ah) | |
48 | { | |
49 | ath9k_hw_private_ops(ah)->init_cal_settings(ah); | |
50 | } | |
51 | ||
52 | static void ath9k_hw_init_mode_regs(struct ath_hw *ah) | |
53 | { | |
54 | ath9k_hw_private_ops(ah)->init_mode_regs(ah); | |
55 | } | |
56 | ||
57 | static bool ath9k_hw_macversion_supported(struct ath_hw *ah) | |
58 | { | |
59 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); | |
60 | ||
61 | return priv_ops->macversion_supported(ah->hw_version.macVersion); | |
62 | } | |
63 | ||
64773964 LR |
64 | static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, |
65 | struct ath9k_channel *chan) | |
66 | { | |
67 | return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); | |
68 | } | |
69 | ||
991312d8 LR |
70 | static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) |
71 | { | |
72 | if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) | |
73 | return; | |
74 | ||
75 | ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); | |
76 | } | |
77 | ||
e36b27af LR |
78 | static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) |
79 | { | |
80 | /* You will not have this callback if using the old ANI */ | |
81 | if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) | |
82 | return; | |
83 | ||
84 | ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); | |
85 | } | |
86 | ||
f1dc5600 S |
87 | /********************/ |
88 | /* Helper Functions */ | |
89 | /********************/ | |
f078f209 | 90 | |
dfdac8ac | 91 | static void ath9k_hw_set_clockrate(struct ath_hw *ah) |
f1dc5600 | 92 | { |
b002a4a9 | 93 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
dfdac8ac FF |
94 | struct ath_common *common = ath9k_hw_common(ah); |
95 | unsigned int clockrate; | |
cbe61d8a | 96 | |
2660b81a | 97 | if (!ah->curchan) /* should really check for CCK instead */ |
dfdac8ac FF |
98 | clockrate = ATH9K_CLOCK_RATE_CCK; |
99 | else if (conf->channel->band == IEEE80211_BAND_2GHZ) | |
100 | clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; | |
101 | else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) | |
102 | clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; | |
e5553724 | 103 | else |
dfdac8ac FF |
104 | clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; |
105 | ||
106 | if (conf_is_ht40(conf)) | |
107 | clockrate *= 2; | |
108 | ||
109 | common->clockrate = clockrate; | |
f1dc5600 S |
110 | } |
111 | ||
cbe61d8a | 112 | static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) |
f1dc5600 | 113 | { |
dfdac8ac | 114 | struct ath_common *common = ath9k_hw_common(ah); |
cbe61d8a | 115 | |
dfdac8ac | 116 | return usecs * common->clockrate; |
f1dc5600 | 117 | } |
f078f209 | 118 | |
0caa7b14 | 119 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) |
f078f209 LR |
120 | { |
121 | int i; | |
122 | ||
0caa7b14 S |
123 | BUG_ON(timeout < AH_TIME_QUANTUM); |
124 | ||
125 | for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { | |
f078f209 LR |
126 | if ((REG_READ(ah, reg) & mask) == val) |
127 | return true; | |
128 | ||
129 | udelay(AH_TIME_QUANTUM); | |
130 | } | |
04bd4638 | 131 | |
226afe68 JP |
132 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY, |
133 | "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", | |
134 | timeout, reg, REG_READ(ah, reg), mask, val); | |
f078f209 | 135 | |
f1dc5600 | 136 | return false; |
f078f209 | 137 | } |
7322fd19 | 138 | EXPORT_SYMBOL(ath9k_hw_wait); |
f078f209 LR |
139 | |
140 | u32 ath9k_hw_reverse_bits(u32 val, u32 n) | |
141 | { | |
142 | u32 retval; | |
143 | int i; | |
144 | ||
145 | for (i = 0, retval = 0; i < n; i++) { | |
146 | retval = (retval << 1) | (val & 1); | |
147 | val >>= 1; | |
148 | } | |
149 | return retval; | |
150 | } | |
151 | ||
cbe61d8a | 152 | bool ath9k_get_channel_edges(struct ath_hw *ah, |
f1dc5600 S |
153 | u16 flags, u16 *low, |
154 | u16 *high) | |
f078f209 | 155 | { |
2660b81a | 156 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
f078f209 | 157 | |
f1dc5600 S |
158 | if (flags & CHANNEL_5GHZ) { |
159 | *low = pCap->low_5ghz_chan; | |
160 | *high = pCap->high_5ghz_chan; | |
161 | return true; | |
f078f209 | 162 | } |
f1dc5600 S |
163 | if ((flags & CHANNEL_2GHZ)) { |
164 | *low = pCap->low_2ghz_chan; | |
165 | *high = pCap->high_2ghz_chan; | |
166 | return true; | |
167 | } | |
168 | return false; | |
f078f209 LR |
169 | } |
170 | ||
cbe61d8a | 171 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
545750d3 | 172 | u8 phy, int kbps, |
f1dc5600 S |
173 | u32 frameLen, u16 rateix, |
174 | bool shortPreamble) | |
f078f209 | 175 | { |
f1dc5600 | 176 | u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; |
f078f209 | 177 | |
f1dc5600 S |
178 | if (kbps == 0) |
179 | return 0; | |
f078f209 | 180 | |
545750d3 | 181 | switch (phy) { |
46d14a58 | 182 | case WLAN_RC_PHY_CCK: |
f1dc5600 | 183 | phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; |
545750d3 | 184 | if (shortPreamble) |
f1dc5600 S |
185 | phyTime >>= 1; |
186 | numBits = frameLen << 3; | |
187 | txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); | |
188 | break; | |
46d14a58 | 189 | case WLAN_RC_PHY_OFDM: |
2660b81a | 190 | if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { |
f1dc5600 S |
191 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; |
192 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
193 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
194 | txTime = OFDM_SIFS_TIME_QUARTER | |
195 | + OFDM_PREAMBLE_TIME_QUARTER | |
196 | + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); | |
2660b81a S |
197 | } else if (ah->curchan && |
198 | IS_CHAN_HALF_RATE(ah->curchan)) { | |
f1dc5600 S |
199 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; |
200 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
201 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
202 | txTime = OFDM_SIFS_TIME_HALF + | |
203 | OFDM_PREAMBLE_TIME_HALF | |
204 | + (numSymbols * OFDM_SYMBOL_TIME_HALF); | |
205 | } else { | |
206 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; | |
207 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
208 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
209 | txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME | |
210 | + (numSymbols * OFDM_SYMBOL_TIME); | |
211 | } | |
212 | break; | |
213 | default: | |
3800276a JP |
214 | ath_err(ath9k_hw_common(ah), |
215 | "Unknown phy %u (rate ix %u)\n", phy, rateix); | |
f1dc5600 S |
216 | txTime = 0; |
217 | break; | |
218 | } | |
f078f209 | 219 | |
f1dc5600 S |
220 | return txTime; |
221 | } | |
7322fd19 | 222 | EXPORT_SYMBOL(ath9k_hw_computetxtime); |
f078f209 | 223 | |
cbe61d8a | 224 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
f1dc5600 S |
225 | struct ath9k_channel *chan, |
226 | struct chan_centers *centers) | |
f078f209 | 227 | { |
f1dc5600 | 228 | int8_t extoff; |
f078f209 | 229 | |
f1dc5600 S |
230 | if (!IS_CHAN_HT40(chan)) { |
231 | centers->ctl_center = centers->ext_center = | |
232 | centers->synth_center = chan->channel; | |
233 | return; | |
f078f209 | 234 | } |
f078f209 | 235 | |
f1dc5600 S |
236 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || |
237 | (chan->chanmode == CHANNEL_G_HT40PLUS)) { | |
238 | centers->synth_center = | |
239 | chan->channel + HT40_CHANNEL_CENTER_SHIFT; | |
240 | extoff = 1; | |
241 | } else { | |
242 | centers->synth_center = | |
243 | chan->channel - HT40_CHANNEL_CENTER_SHIFT; | |
244 | extoff = -1; | |
245 | } | |
f078f209 | 246 | |
f1dc5600 S |
247 | centers->ctl_center = |
248 | centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); | |
6420014c | 249 | /* 25 MHz spacing is supported by hw but not on upper layers */ |
f1dc5600 | 250 | centers->ext_center = |
6420014c | 251 | centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); |
f078f209 LR |
252 | } |
253 | ||
f1dc5600 S |
254 | /******************/ |
255 | /* Chip Revisions */ | |
256 | /******************/ | |
257 | ||
cbe61d8a | 258 | static void ath9k_hw_read_revisions(struct ath_hw *ah) |
f078f209 | 259 | { |
f1dc5600 | 260 | u32 val; |
f078f209 | 261 | |
f1dc5600 | 262 | val = REG_READ(ah, AR_SREV) & AR_SREV_ID; |
f078f209 | 263 | |
f1dc5600 S |
264 | if (val == 0xFF) { |
265 | val = REG_READ(ah, AR_SREV); | |
d535a42a S |
266 | ah->hw_version.macVersion = |
267 | (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; | |
268 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); | |
2660b81a | 269 | ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; |
f1dc5600 S |
270 | } else { |
271 | if (!AR_SREV_9100(ah)) | |
d535a42a | 272 | ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); |
f078f209 | 273 | |
d535a42a | 274 | ah->hw_version.macRev = val & AR_SREV_REVISION; |
f078f209 | 275 | |
d535a42a | 276 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) |
2660b81a | 277 | ah->is_pciexpress = true; |
f1dc5600 | 278 | } |
f078f209 LR |
279 | } |
280 | ||
f1dc5600 S |
281 | /************************************/ |
282 | /* HW Attach, Detach, Init Routines */ | |
283 | /************************************/ | |
284 | ||
cbe61d8a | 285 | static void ath9k_hw_disablepcie(struct ath_hw *ah) |
f078f209 | 286 | { |
feed029c | 287 | if (AR_SREV_9100(ah)) |
f1dc5600 | 288 | return; |
f078f209 | 289 | |
7d0d0df0 S |
290 | ENABLE_REGWRITE_BUFFER(ah); |
291 | ||
f1dc5600 S |
292 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); |
293 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | |
294 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); | |
295 | REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); | |
296 | REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); | |
297 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); | |
298 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); | |
299 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | |
300 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); | |
f078f209 | 301 | |
f1dc5600 | 302 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
7d0d0df0 S |
303 | |
304 | REGWRITE_BUFFER_FLUSH(ah); | |
f078f209 LR |
305 | } |
306 | ||
1f3f0618 | 307 | /* This should work for all families including legacy */ |
cbe61d8a | 308 | static bool ath9k_hw_chip_test(struct ath_hw *ah) |
f078f209 | 309 | { |
c46917bb | 310 | struct ath_common *common = ath9k_hw_common(ah); |
1f3f0618 | 311 | u32 regAddr[2] = { AR_STA_ID0 }; |
f1dc5600 | 312 | u32 regHold[2]; |
07b2fa5a JP |
313 | static const u32 patternData[4] = { |
314 | 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 | |
315 | }; | |
1f3f0618 | 316 | int i, j, loop_max; |
f078f209 | 317 | |
1f3f0618 SB |
318 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
319 | loop_max = 2; | |
320 | regAddr[1] = AR_PHY_BASE + (8 << 2); | |
321 | } else | |
322 | loop_max = 1; | |
323 | ||
324 | for (i = 0; i < loop_max; i++) { | |
f1dc5600 S |
325 | u32 addr = regAddr[i]; |
326 | u32 wrData, rdData; | |
f078f209 | 327 | |
f1dc5600 S |
328 | regHold[i] = REG_READ(ah, addr); |
329 | for (j = 0; j < 0x100; j++) { | |
330 | wrData = (j << 16) | j; | |
331 | REG_WRITE(ah, addr, wrData); | |
332 | rdData = REG_READ(ah, addr); | |
333 | if (rdData != wrData) { | |
3800276a JP |
334 | ath_err(common, |
335 | "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", | |
336 | addr, wrData, rdData); | |
f1dc5600 S |
337 | return false; |
338 | } | |
339 | } | |
340 | for (j = 0; j < 4; j++) { | |
341 | wrData = patternData[j]; | |
342 | REG_WRITE(ah, addr, wrData); | |
343 | rdData = REG_READ(ah, addr); | |
344 | if (wrData != rdData) { | |
3800276a JP |
345 | ath_err(common, |
346 | "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", | |
347 | addr, wrData, rdData); | |
f1dc5600 S |
348 | return false; |
349 | } | |
f078f209 | 350 | } |
f1dc5600 | 351 | REG_WRITE(ah, regAddr[i], regHold[i]); |
f078f209 | 352 | } |
f1dc5600 | 353 | udelay(100); |
cbe61d8a | 354 | |
f078f209 LR |
355 | return true; |
356 | } | |
357 | ||
b8b0f377 | 358 | static void ath9k_hw_init_config(struct ath_hw *ah) |
f1dc5600 S |
359 | { |
360 | int i; | |
f078f209 | 361 | |
2660b81a S |
362 | ah->config.dma_beacon_response_time = 2; |
363 | ah->config.sw_beacon_response_time = 10; | |
364 | ah->config.additional_swba_backoff = 0; | |
365 | ah->config.ack_6mb = 0x0; | |
366 | ah->config.cwm_ignore_extcca = 0; | |
367 | ah->config.pcie_powersave_enable = 0; | |
2660b81a | 368 | ah->config.pcie_clock_req = 0; |
2660b81a S |
369 | ah->config.pcie_waen = 0; |
370 | ah->config.analog_shiftreg = 1; | |
03c72518 | 371 | ah->config.enable_ani = true; |
f078f209 | 372 | |
f1dc5600 | 373 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
2660b81a S |
374 | ah->config.spurchans[i][0] = AR_NO_SPUR; |
375 | ah->config.spurchans[i][1] = AR_NO_SPUR; | |
f078f209 LR |
376 | } |
377 | ||
5ffaf8a3 LR |
378 | if (ah->hw_version.devid != AR2427_DEVID_PCIE) |
379 | ah->config.ht_enable = 1; | |
380 | else | |
381 | ah->config.ht_enable = 0; | |
382 | ||
0ce024cb | 383 | ah->config.rx_intr_mitigation = true; |
6a0ec30a | 384 | ah->config.pcieSerDesWrite = true; |
6158425b LR |
385 | |
386 | /* | |
387 | * We need this for PCI devices only (Cardbus, PCI, miniPCI) | |
388 | * _and_ if on non-uniprocessor systems (Multiprocessor/HT). | |
389 | * This means we use it for all AR5416 devices, and the few | |
390 | * minor PCI AR9280 devices out there. | |
391 | * | |
392 | * Serialization is required because these devices do not handle | |
393 | * well the case of two concurrent reads/writes due to the latency | |
394 | * involved. During one read/write another read/write can be issued | |
395 | * on another CPU while the previous read/write may still be working | |
396 | * on our hardware, if we hit this case the hardware poops in a loop. | |
397 | * We prevent this by serializing reads and writes. | |
398 | * | |
399 | * This issue is not present on PCI-Express devices or pre-AR5416 | |
400 | * devices (legacy, 802.11abg). | |
401 | */ | |
402 | if (num_possible_cpus() > 1) | |
2d6a5e95 | 403 | ah->config.serialize_regmode = SER_REG_MODE_AUTO; |
f078f209 LR |
404 | } |
405 | ||
50aca25b | 406 | static void ath9k_hw_init_defaults(struct ath_hw *ah) |
f078f209 | 407 | { |
608b88cb LR |
408 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
409 | ||
410 | regulatory->country_code = CTRY_DEFAULT; | |
411 | regulatory->power_limit = MAX_RATE_POWER; | |
412 | regulatory->tp_scale = ATH9K_TP_SCALE_MAX; | |
413 | ||
d535a42a | 414 | ah->hw_version.magic = AR5416_MAGIC; |
d535a42a | 415 | ah->hw_version.subvendorid = 0; |
f078f209 | 416 | |
2660b81a | 417 | ah->atim_window = 0; |
16f2411f FF |
418 | ah->sta_id1_defaults = |
419 | AR_STA_ID1_CRPT_MIC_ENABLE | | |
420 | AR_STA_ID1_MCAST_KSRCH; | |
2660b81a S |
421 | ah->beacon_interval = 100; |
422 | ah->enable_32kHz_clock = DONT_USE_32KHZ; | |
423 | ah->slottime = (u32) -1; | |
2660b81a | 424 | ah->globaltxtimeout = (u32) -1; |
cbdec975 | 425 | ah->power_mode = ATH9K_PM_UNDEFINED; |
f078f209 LR |
426 | } |
427 | ||
cbe61d8a | 428 | static int ath9k_hw_init_macaddr(struct ath_hw *ah) |
f078f209 | 429 | { |
1510718d | 430 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 LR |
431 | u32 sum; |
432 | int i; | |
433 | u16 eeval; | |
07b2fa5a | 434 | static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; |
f078f209 LR |
435 | |
436 | sum = 0; | |
437 | for (i = 0; i < 3; i++) { | |
49101676 | 438 | eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); |
f078f209 | 439 | sum += eeval; |
1510718d LR |
440 | common->macaddr[2 * i] = eeval >> 8; |
441 | common->macaddr[2 * i + 1] = eeval & 0xff; | |
f078f209 | 442 | } |
d8baa939 | 443 | if (sum == 0 || sum == 0xffff * 3) |
f078f209 | 444 | return -EADDRNOTAVAIL; |
f078f209 LR |
445 | |
446 | return 0; | |
447 | } | |
448 | ||
f637cfd6 | 449 | static int ath9k_hw_post_init(struct ath_hw *ah) |
f078f209 | 450 | { |
f1dc5600 | 451 | int ecode; |
f078f209 | 452 | |
527d485f S |
453 | if (!AR_SREV_9271(ah)) { |
454 | if (!ath9k_hw_chip_test(ah)) | |
455 | return -ENODEV; | |
456 | } | |
f078f209 | 457 | |
ebd5a14a LR |
458 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
459 | ecode = ar9002_hw_rf_claim(ah); | |
460 | if (ecode != 0) | |
461 | return ecode; | |
462 | } | |
f078f209 | 463 | |
f637cfd6 | 464 | ecode = ath9k_hw_eeprom_init(ah); |
f1dc5600 S |
465 | if (ecode != 0) |
466 | return ecode; | |
7d01b221 | 467 | |
226afe68 JP |
468 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG, |
469 | "Eeprom VER: %d, REV: %d\n", | |
470 | ah->eep_ops->get_eeprom_ver(ah), | |
471 | ah->eep_ops->get_eeprom_rev(ah)); | |
7d01b221 | 472 | |
8fe65368 LR |
473 | ecode = ath9k_hw_rf_alloc_ext_banks(ah); |
474 | if (ecode) { | |
3800276a JP |
475 | ath_err(ath9k_hw_common(ah), |
476 | "Failed allocating banks for external radio\n"); | |
48a7c3df | 477 | ath9k_hw_rf_free_ext_banks(ah); |
8fe65368 | 478 | return ecode; |
574d6b12 | 479 | } |
f078f209 | 480 | |
f1dc5600 S |
481 | if (!AR_SREV_9100(ah)) { |
482 | ath9k_hw_ani_setup(ah); | |
f637cfd6 | 483 | ath9k_hw_ani_init(ah); |
f078f209 LR |
484 | } |
485 | ||
f078f209 LR |
486 | return 0; |
487 | } | |
488 | ||
8525f280 | 489 | static void ath9k_hw_attach_ops(struct ath_hw *ah) |
ee2bb460 | 490 | { |
8525f280 LR |
491 | if (AR_SREV_9300_20_OR_LATER(ah)) |
492 | ar9003_hw_attach_ops(ah); | |
493 | else | |
494 | ar9002_hw_attach_ops(ah); | |
aa4058ae LR |
495 | } |
496 | ||
d70357d5 LR |
497 | /* Called for all hardware families */ |
498 | static int __ath9k_hw_init(struct ath_hw *ah) | |
aa4058ae | 499 | { |
c46917bb | 500 | struct ath_common *common = ath9k_hw_common(ah); |
95fafca2 | 501 | int r = 0; |
aa4058ae | 502 | |
bab1f62e LR |
503 | if (ah->hw_version.devid == AR5416_AR9100_DEVID) |
504 | ah->hw_version.macVersion = AR_SREV_VERSION_9100; | |
aa4058ae LR |
505 | |
506 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { | |
3800276a | 507 | ath_err(common, "Couldn't reset chip\n"); |
95fafca2 | 508 | return -EIO; |
aa4058ae LR |
509 | } |
510 | ||
bab1f62e LR |
511 | ath9k_hw_init_defaults(ah); |
512 | ath9k_hw_init_config(ah); | |
513 | ||
8525f280 | 514 | ath9k_hw_attach_ops(ah); |
d70357d5 | 515 | |
9ecdef4b | 516 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { |
3800276a | 517 | ath_err(common, "Couldn't wakeup chip\n"); |
95fafca2 | 518 | return -EIO; |
aa4058ae LR |
519 | } |
520 | ||
521 | if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { | |
522 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || | |
4c85ab11 JL |
523 | ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) && |
524 | !ah->is_pciexpress)) { | |
aa4058ae LR |
525 | ah->config.serialize_regmode = |
526 | SER_REG_MODE_ON; | |
527 | } else { | |
528 | ah->config.serialize_regmode = | |
529 | SER_REG_MODE_OFF; | |
530 | } | |
531 | } | |
532 | ||
226afe68 | 533 | ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n", |
aa4058ae LR |
534 | ah->config.serialize_regmode); |
535 | ||
f4709fdf LR |
536 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
537 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; | |
538 | else | |
539 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; | |
540 | ||
d70357d5 | 541 | if (!ath9k_hw_macversion_supported(ah)) { |
3800276a JP |
542 | ath_err(common, |
543 | "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", | |
544 | ah->hw_version.macVersion, ah->hw_version.macRev); | |
95fafca2 | 545 | return -EOPNOTSUPP; |
aa4058ae LR |
546 | } |
547 | ||
0df13da4 | 548 | if (AR_SREV_9271(ah) || AR_SREV_9100(ah)) |
d7e7d229 LR |
549 | ah->is_pciexpress = false; |
550 | ||
aa4058ae | 551 | ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); |
aa4058ae LR |
552 | ath9k_hw_init_cal_settings(ah); |
553 | ||
554 | ah->ani_function = ATH9K_ANI_ALL; | |
7a37081e | 555 | if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
aa4058ae | 556 | ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; |
e36b27af LR |
557 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
558 | ah->ani_function &= ~ATH9K_ANI_MRC_CCK; | |
aa4058ae LR |
559 | |
560 | ath9k_hw_init_mode_regs(ah); | |
561 | ||
9a658d2b LR |
562 | /* |
563 | * Read back AR_WA into a permanent copy and set bits 14 and 17. | |
564 | * We need to do this to avoid RMW of this register. We cannot | |
565 | * read the reg when chip is asleep. | |
566 | */ | |
567 | ah->WARegVal = REG_READ(ah, AR_WA); | |
568 | ah->WARegVal |= (AR_WA_D3_L1_DISABLE | | |
569 | AR_WA_ASPM_TIMER_BASED_DISABLE); | |
570 | ||
aa4058ae | 571 | if (ah->is_pciexpress) |
93b1b37f | 572 | ath9k_hw_configpcipowersave(ah, 0, 0); |
aa4058ae LR |
573 | else |
574 | ath9k_hw_disablepcie(ah); | |
575 | ||
d8f492b7 LR |
576 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
577 | ar9002_hw_cck_chan14_spread(ah); | |
193cd458 | 578 | |
f637cfd6 | 579 | r = ath9k_hw_post_init(ah); |
aa4058ae | 580 | if (r) |
95fafca2 | 581 | return r; |
aa4058ae LR |
582 | |
583 | ath9k_hw_init_mode_gain_regs(ah); | |
a9a29ce6 GJ |
584 | r = ath9k_hw_fill_cap_info(ah); |
585 | if (r) | |
586 | return r; | |
587 | ||
4f3acf81 LR |
588 | r = ath9k_hw_init_macaddr(ah); |
589 | if (r) { | |
3800276a | 590 | ath_err(common, "Failed to initialize MAC address\n"); |
95fafca2 | 591 | return r; |
f078f209 LR |
592 | } |
593 | ||
d7e7d229 | 594 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
2660b81a | 595 | ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); |
f1dc5600 | 596 | else |
2660b81a | 597 | ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); |
f078f209 | 598 | |
aea702b7 | 599 | ah->bb_watchdog_timeout_ms = 25; |
f078f209 | 600 | |
211f5859 LR |
601 | common->state = ATH_HW_INITIALIZED; |
602 | ||
4f3acf81 | 603 | return 0; |
f078f209 LR |
604 | } |
605 | ||
d70357d5 | 606 | int ath9k_hw_init(struct ath_hw *ah) |
f078f209 | 607 | { |
d70357d5 LR |
608 | int ret; |
609 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 | 610 | |
d70357d5 LR |
611 | /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ |
612 | switch (ah->hw_version.devid) { | |
613 | case AR5416_DEVID_PCI: | |
614 | case AR5416_DEVID_PCIE: | |
615 | case AR5416_AR9100_DEVID: | |
616 | case AR9160_DEVID_PCI: | |
617 | case AR9280_DEVID_PCI: | |
618 | case AR9280_DEVID_PCIE: | |
619 | case AR9285_DEVID_PCIE: | |
db3cc53a SB |
620 | case AR9287_DEVID_PCI: |
621 | case AR9287_DEVID_PCIE: | |
d70357d5 | 622 | case AR2427_DEVID_PCIE: |
db3cc53a | 623 | case AR9300_DEVID_PCIE: |
3050c914 | 624 | case AR9300_DEVID_AR9485_PCIE: |
d70357d5 LR |
625 | break; |
626 | default: | |
627 | if (common->bus_ops->ath_bus_type == ATH_USB) | |
628 | break; | |
3800276a JP |
629 | ath_err(common, "Hardware device ID 0x%04x not supported\n", |
630 | ah->hw_version.devid); | |
d70357d5 LR |
631 | return -EOPNOTSUPP; |
632 | } | |
f078f209 | 633 | |
d70357d5 LR |
634 | ret = __ath9k_hw_init(ah); |
635 | if (ret) { | |
3800276a JP |
636 | ath_err(common, |
637 | "Unable to initialize hardware; initialization status: %d\n", | |
638 | ret); | |
d70357d5 LR |
639 | return ret; |
640 | } | |
f078f209 | 641 | |
d70357d5 | 642 | return 0; |
f078f209 | 643 | } |
d70357d5 | 644 | EXPORT_SYMBOL(ath9k_hw_init); |
f078f209 | 645 | |
cbe61d8a | 646 | static void ath9k_hw_init_qos(struct ath_hw *ah) |
f078f209 | 647 | { |
7d0d0df0 S |
648 | ENABLE_REGWRITE_BUFFER(ah); |
649 | ||
f1dc5600 S |
650 | REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); |
651 | REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); | |
f078f209 | 652 | |
f1dc5600 S |
653 | REG_WRITE(ah, AR_QOS_NO_ACK, |
654 | SM(2, AR_QOS_NO_ACK_TWO_BIT) | | |
655 | SM(5, AR_QOS_NO_ACK_BIT_OFF) | | |
656 | SM(0, AR_QOS_NO_ACK_BYTE_OFF)); | |
657 | ||
658 | REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); | |
659 | REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); | |
660 | REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); | |
661 | REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); | |
662 | REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); | |
7d0d0df0 S |
663 | |
664 | REGWRITE_BUFFER_FLUSH(ah); | |
f078f209 LR |
665 | } |
666 | ||
cbe61d8a | 667 | static void ath9k_hw_init_pll(struct ath_hw *ah, |
f1dc5600 | 668 | struct ath9k_channel *chan) |
f078f209 | 669 | { |
d09b17f7 VT |
670 | u32 pll; |
671 | ||
672 | if (AR_SREV_9485(ah)) | |
673 | REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666); | |
674 | ||
675 | pll = ath9k_hw_compute_pll_control(ah, chan); | |
f078f209 | 676 | |
d03a66c1 | 677 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); |
f078f209 | 678 | |
c75724d1 LR |
679 | /* Switch the core clock for ar9271 to 117Mhz */ |
680 | if (AR_SREV_9271(ah)) { | |
25e2ab17 S |
681 | udelay(500); |
682 | REG_WRITE(ah, 0x50040, 0x304); | |
c75724d1 LR |
683 | } |
684 | ||
f1dc5600 S |
685 | udelay(RTC_PLL_SETTLE_DELAY); |
686 | ||
687 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); | |
f078f209 LR |
688 | } |
689 | ||
cbe61d8a | 690 | static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, |
d97809db | 691 | enum nl80211_iftype opmode) |
f078f209 | 692 | { |
152d530d | 693 | u32 imr_reg = AR_IMR_TXERR | |
f1dc5600 S |
694 | AR_IMR_TXURN | |
695 | AR_IMR_RXERR | | |
696 | AR_IMR_RXORN | | |
697 | AR_IMR_BCNMISC; | |
f078f209 | 698 | |
66860240 VT |
699 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
700 | imr_reg |= AR_IMR_RXOK_HP; | |
701 | if (ah->config.rx_intr_mitigation) | |
702 | imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; | |
703 | else | |
704 | imr_reg |= AR_IMR_RXOK_LP; | |
f078f209 | 705 | |
66860240 VT |
706 | } else { |
707 | if (ah->config.rx_intr_mitigation) | |
708 | imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; | |
709 | else | |
710 | imr_reg |= AR_IMR_RXOK; | |
711 | } | |
f078f209 | 712 | |
66860240 VT |
713 | if (ah->config.tx_intr_mitigation) |
714 | imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; | |
715 | else | |
716 | imr_reg |= AR_IMR_TXOK; | |
f078f209 | 717 | |
d97809db | 718 | if (opmode == NL80211_IFTYPE_AP) |
152d530d | 719 | imr_reg |= AR_IMR_MIB; |
f078f209 | 720 | |
7d0d0df0 S |
721 | ENABLE_REGWRITE_BUFFER(ah); |
722 | ||
152d530d | 723 | REG_WRITE(ah, AR_IMR, imr_reg); |
74bad5cb PR |
724 | ah->imrs2_reg |= AR_IMR_S2_GTT; |
725 | REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); | |
f078f209 | 726 | |
f1dc5600 S |
727 | if (!AR_SREV_9100(ah)) { |
728 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); | |
729 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); | |
730 | REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); | |
731 | } | |
66860240 | 732 | |
7d0d0df0 | 733 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 734 | |
66860240 VT |
735 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
736 | REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); | |
737 | REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); | |
738 | REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); | |
739 | REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); | |
740 | } | |
f078f209 LR |
741 | } |
742 | ||
0005baf4 | 743 | static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) |
f078f209 | 744 | { |
0005baf4 FF |
745 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
746 | val = min(val, (u32) 0xFFFF); | |
747 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); | |
f078f209 LR |
748 | } |
749 | ||
0005baf4 | 750 | static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) |
f078f209 | 751 | { |
0005baf4 FF |
752 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
753 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); | |
754 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); | |
755 | } | |
756 | ||
757 | static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) | |
758 | { | |
759 | u32 val = ath9k_hw_mac_to_clks(ah, us); | |
760 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); | |
761 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); | |
f078f209 | 762 | } |
f1dc5600 | 763 | |
cbe61d8a | 764 | static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) |
f078f209 | 765 | { |
f078f209 | 766 | if (tu > 0xFFFF) { |
226afe68 JP |
767 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT, |
768 | "bad global tx timeout %u\n", tu); | |
2660b81a | 769 | ah->globaltxtimeout = (u32) -1; |
f078f209 LR |
770 | return false; |
771 | } else { | |
772 | REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); | |
2660b81a | 773 | ah->globaltxtimeout = tu; |
f078f209 LR |
774 | return true; |
775 | } | |
776 | } | |
777 | ||
0005baf4 | 778 | void ath9k_hw_init_global_settings(struct ath_hw *ah) |
f078f209 | 779 | { |
0005baf4 FF |
780 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
781 | int acktimeout; | |
e239d859 | 782 | int slottime; |
0005baf4 FF |
783 | int sifstime; |
784 | ||
226afe68 JP |
785 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", |
786 | ah->misc_mode); | |
f078f209 | 787 | |
2660b81a | 788 | if (ah->misc_mode != 0) |
f1dc5600 | 789 | REG_WRITE(ah, AR_PCU_MISC, |
2660b81a | 790 | REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); |
0005baf4 FF |
791 | |
792 | if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ) | |
793 | sifstime = 16; | |
794 | else | |
795 | sifstime = 10; | |
796 | ||
e239d859 FF |
797 | /* As defined by IEEE 802.11-2007 17.3.8.6 */ |
798 | slottime = ah->slottime + 3 * ah->coverage_class; | |
799 | acktimeout = slottime + sifstime; | |
42c4568a FF |
800 | |
801 | /* | |
802 | * Workaround for early ACK timeouts, add an offset to match the | |
803 | * initval's 64us ack timeout value. | |
804 | * This was initially only meant to work around an issue with delayed | |
805 | * BA frames in some implementations, but it has been found to fix ACK | |
806 | * timeout issues in other cases as well. | |
807 | */ | |
808 | if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) | |
809 | acktimeout += 64 - sifstime - ah->slottime; | |
810 | ||
e239d859 | 811 | ath9k_hw_setslottime(ah, slottime); |
0005baf4 FF |
812 | ath9k_hw_set_ack_timeout(ah, acktimeout); |
813 | ath9k_hw_set_cts_timeout(ah, acktimeout); | |
2660b81a S |
814 | if (ah->globaltxtimeout != (u32) -1) |
815 | ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); | |
f1dc5600 | 816 | } |
0005baf4 | 817 | EXPORT_SYMBOL(ath9k_hw_init_global_settings); |
f1dc5600 | 818 | |
285f2dda | 819 | void ath9k_hw_deinit(struct ath_hw *ah) |
f1dc5600 | 820 | { |
211f5859 LR |
821 | struct ath_common *common = ath9k_hw_common(ah); |
822 | ||
736b3a27 | 823 | if (common->state < ATH_HW_INITIALIZED) |
211f5859 LR |
824 | goto free_hw; |
825 | ||
9ecdef4b | 826 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); |
211f5859 LR |
827 | |
828 | free_hw: | |
8fe65368 | 829 | ath9k_hw_rf_free_ext_banks(ah); |
f1dc5600 | 830 | } |
285f2dda | 831 | EXPORT_SYMBOL(ath9k_hw_deinit); |
f1dc5600 | 832 | |
f1dc5600 S |
833 | /*******/ |
834 | /* INI */ | |
835 | /*******/ | |
836 | ||
8fe65368 | 837 | u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) |
3a702e49 BC |
838 | { |
839 | u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); | |
840 | ||
841 | if (IS_CHAN_B(chan)) | |
842 | ctl |= CTL_11B; | |
843 | else if (IS_CHAN_G(chan)) | |
844 | ctl |= CTL_11G; | |
845 | else | |
846 | ctl |= CTL_11A; | |
847 | ||
848 | return ctl; | |
849 | } | |
850 | ||
f1dc5600 S |
851 | /****************************************/ |
852 | /* Reset and Channel Switching Routines */ | |
853 | /****************************************/ | |
f1dc5600 | 854 | |
cbe61d8a | 855 | static inline void ath9k_hw_set_dma(struct ath_hw *ah) |
f1dc5600 | 856 | { |
57b32227 | 857 | struct ath_common *common = ath9k_hw_common(ah); |
f1dc5600 S |
858 | u32 regval; |
859 | ||
7d0d0df0 S |
860 | ENABLE_REGWRITE_BUFFER(ah); |
861 | ||
d7e7d229 LR |
862 | /* |
863 | * set AHB_MODE not to do cacheline prefetches | |
864 | */ | |
57b32227 FF |
865 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
866 | regval = REG_READ(ah, AR_AHB_MODE); | |
867 | REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); | |
868 | } | |
f1dc5600 | 869 | |
d7e7d229 LR |
870 | /* |
871 | * let mac dma reads be in 128 byte chunks | |
872 | */ | |
f1dc5600 S |
873 | regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; |
874 | REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); | |
875 | ||
7d0d0df0 | 876 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 877 | |
d7e7d229 LR |
878 | /* |
879 | * Restore TX Trigger Level to its pre-reset value. | |
880 | * The initial value depends on whether aggregation is enabled, and is | |
881 | * adjusted whenever underruns are detected. | |
882 | */ | |
57b32227 FF |
883 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
884 | REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); | |
f1dc5600 | 885 | |
7d0d0df0 | 886 | ENABLE_REGWRITE_BUFFER(ah); |
f1dc5600 | 887 | |
d7e7d229 LR |
888 | /* |
889 | * let mac dma writes be in 128 byte chunks | |
890 | */ | |
f1dc5600 S |
891 | regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; |
892 | REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); | |
893 | ||
d7e7d229 LR |
894 | /* |
895 | * Setup receive FIFO threshold to hold off TX activities | |
896 | */ | |
f1dc5600 S |
897 | REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); |
898 | ||
57b32227 FF |
899 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
900 | REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); | |
901 | REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); | |
902 | ||
903 | ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - | |
904 | ah->caps.rx_status_len); | |
905 | } | |
906 | ||
d7e7d229 LR |
907 | /* |
908 | * reduce the number of usable entries in PCU TXBUF to avoid | |
909 | * wrap around issues. | |
910 | */ | |
f1dc5600 | 911 | if (AR_SREV_9285(ah)) { |
d7e7d229 LR |
912 | /* For AR9285 the number of Fifos are reduced to half. |
913 | * So set the usable tx buf size also to half to | |
914 | * avoid data/delimiter underruns | |
915 | */ | |
f1dc5600 S |
916 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, |
917 | AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); | |
d7e7d229 | 918 | } else if (!AR_SREV_9271(ah)) { |
f1dc5600 S |
919 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, |
920 | AR_PCU_TXBUF_CTRL_USABLE_SIZE); | |
921 | } | |
744d4025 | 922 | |
7d0d0df0 | 923 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 924 | |
744d4025 VT |
925 | if (AR_SREV_9300_20_OR_LATER(ah)) |
926 | ath9k_hw_reset_txstatus_ring(ah); | |
f1dc5600 S |
927 | } |
928 | ||
cbe61d8a | 929 | static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) |
f1dc5600 S |
930 | { |
931 | u32 val; | |
932 | ||
933 | val = REG_READ(ah, AR_STA_ID1); | |
934 | val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); | |
935 | switch (opmode) { | |
d97809db | 936 | case NL80211_IFTYPE_AP: |
f1dc5600 S |
937 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP |
938 | | AR_STA_ID1_KSRCH_MODE); | |
939 | REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); | |
f078f209 | 940 | break; |
d97809db | 941 | case NL80211_IFTYPE_ADHOC: |
9cb5412b | 942 | case NL80211_IFTYPE_MESH_POINT: |
f1dc5600 S |
943 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC |
944 | | AR_STA_ID1_KSRCH_MODE); | |
945 | REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); | |
f078f209 | 946 | break; |
d97809db | 947 | case NL80211_IFTYPE_STATION: |
f1dc5600 | 948 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); |
f078f209 | 949 | break; |
5f841b41 RM |
950 | default: |
951 | if (ah->is_monitoring) | |
952 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); | |
953 | break; | |
f1dc5600 S |
954 | } |
955 | } | |
956 | ||
8fe65368 LR |
957 | void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, |
958 | u32 *coef_mantissa, u32 *coef_exponent) | |
f1dc5600 S |
959 | { |
960 | u32 coef_exp, coef_man; | |
961 | ||
962 | for (coef_exp = 31; coef_exp > 0; coef_exp--) | |
963 | if ((coef_scaled >> coef_exp) & 0x1) | |
964 | break; | |
965 | ||
966 | coef_exp = 14 - (coef_exp - COEF_SCALE_S); | |
967 | ||
968 | coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); | |
969 | ||
970 | *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); | |
971 | *coef_exponent = coef_exp - 16; | |
972 | } | |
973 | ||
cbe61d8a | 974 | static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) |
f1dc5600 S |
975 | { |
976 | u32 rst_flags; | |
977 | u32 tmpReg; | |
978 | ||
70768496 S |
979 | if (AR_SREV_9100(ah)) { |
980 | u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); | |
981 | val &= ~AR_RTC_DERIVED_CLK_PERIOD; | |
982 | val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); | |
983 | REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); | |
984 | (void)REG_READ(ah, AR_RTC_DERIVED_CLK); | |
985 | } | |
986 | ||
7d0d0df0 S |
987 | ENABLE_REGWRITE_BUFFER(ah); |
988 | ||
9a658d2b LR |
989 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
990 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
991 | udelay(10); | |
992 | } | |
993 | ||
f1dc5600 S |
994 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
995 | AR_RTC_FORCE_WAKE_ON_INT); | |
996 | ||
997 | if (AR_SREV_9100(ah)) { | |
998 | rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | | |
999 | AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; | |
1000 | } else { | |
1001 | tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); | |
1002 | if (tmpReg & | |
1003 | (AR_INTR_SYNC_LOCAL_TIMEOUT | | |
1004 | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { | |
42d5bc3f | 1005 | u32 val; |
f1dc5600 | 1006 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); |
42d5bc3f LR |
1007 | |
1008 | val = AR_RC_HOSTIF; | |
1009 | if (!AR_SREV_9300_20_OR_LATER(ah)) | |
1010 | val |= AR_RC_AHB; | |
1011 | REG_WRITE(ah, AR_RC, val); | |
1012 | ||
1013 | } else if (!AR_SREV_9300_20_OR_LATER(ah)) | |
f1dc5600 | 1014 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
f1dc5600 S |
1015 | |
1016 | rst_flags = AR_RTC_RC_MAC_WARM; | |
1017 | if (type == ATH9K_RESET_COLD) | |
1018 | rst_flags |= AR_RTC_RC_MAC_COLD; | |
1019 | } | |
1020 | ||
d03a66c1 | 1021 | REG_WRITE(ah, AR_RTC_RC, rst_flags); |
7d0d0df0 S |
1022 | |
1023 | REGWRITE_BUFFER_FLUSH(ah); | |
7d0d0df0 | 1024 | |
f1dc5600 S |
1025 | udelay(50); |
1026 | ||
d03a66c1 | 1027 | REG_WRITE(ah, AR_RTC_RC, 0); |
0caa7b14 | 1028 | if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { |
226afe68 JP |
1029 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, |
1030 | "RTC stuck in MAC reset\n"); | |
f1dc5600 S |
1031 | return false; |
1032 | } | |
1033 | ||
1034 | if (!AR_SREV_9100(ah)) | |
1035 | REG_WRITE(ah, AR_RC, 0); | |
1036 | ||
f1dc5600 S |
1037 | if (AR_SREV_9100(ah)) |
1038 | udelay(50); | |
1039 | ||
1040 | return true; | |
1041 | } | |
1042 | ||
cbe61d8a | 1043 | static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) |
f1dc5600 | 1044 | { |
7d0d0df0 S |
1045 | ENABLE_REGWRITE_BUFFER(ah); |
1046 | ||
9a658d2b LR |
1047 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
1048 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
1049 | udelay(10); | |
1050 | } | |
1051 | ||
f1dc5600 S |
1052 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
1053 | AR_RTC_FORCE_WAKE_ON_INT); | |
1054 | ||
42d5bc3f | 1055 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
1c29ce67 VT |
1056 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
1057 | ||
d03a66c1 | 1058 | REG_WRITE(ah, AR_RTC_RESET, 0); |
ee031112 | 1059 | udelay(2); |
1c29ce67 | 1060 | |
7d0d0df0 | 1061 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1062 | |
84e2169b SB |
1063 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
1064 | udelay(2); | |
1065 | ||
1066 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) | |
1c29ce67 VT |
1067 | REG_WRITE(ah, AR_RC, 0); |
1068 | ||
d03a66c1 | 1069 | REG_WRITE(ah, AR_RTC_RESET, 1); |
f1dc5600 S |
1070 | |
1071 | if (!ath9k_hw_wait(ah, | |
1072 | AR_RTC_STATUS, | |
1073 | AR_RTC_STATUS_M, | |
0caa7b14 S |
1074 | AR_RTC_STATUS_ON, |
1075 | AH_WAIT_TIMEOUT)) { | |
226afe68 JP |
1076 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, |
1077 | "RTC not waking up\n"); | |
f1dc5600 | 1078 | return false; |
f078f209 LR |
1079 | } |
1080 | ||
f1dc5600 S |
1081 | ath9k_hw_read_revisions(ah); |
1082 | ||
1083 | return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); | |
1084 | } | |
1085 | ||
cbe61d8a | 1086 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) |
f1dc5600 | 1087 | { |
9a658d2b LR |
1088 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
1089 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
1090 | udelay(10); | |
1091 | } | |
1092 | ||
f1dc5600 S |
1093 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
1094 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); | |
1095 | ||
1096 | switch (type) { | |
1097 | case ATH9K_RESET_POWER_ON: | |
1098 | return ath9k_hw_set_reset_power_on(ah); | |
f1dc5600 S |
1099 | case ATH9K_RESET_WARM: |
1100 | case ATH9K_RESET_COLD: | |
1101 | return ath9k_hw_set_reset(ah, type); | |
f1dc5600 S |
1102 | default: |
1103 | return false; | |
1104 | } | |
f078f209 LR |
1105 | } |
1106 | ||
cbe61d8a | 1107 | static bool ath9k_hw_chip_reset(struct ath_hw *ah, |
f1dc5600 | 1108 | struct ath9k_channel *chan) |
f078f209 | 1109 | { |
42abfbee | 1110 | if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { |
8bd1d07f SB |
1111 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) |
1112 | return false; | |
1113 | } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) | |
f1dc5600 | 1114 | return false; |
f078f209 | 1115 | |
9ecdef4b | 1116 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
f1dc5600 | 1117 | return false; |
f078f209 | 1118 | |
2660b81a | 1119 | ah->chip_fullsleep = false; |
f1dc5600 | 1120 | ath9k_hw_init_pll(ah, chan); |
f1dc5600 | 1121 | ath9k_hw_set_rfmode(ah, chan); |
f078f209 | 1122 | |
f1dc5600 | 1123 | return true; |
f078f209 LR |
1124 | } |
1125 | ||
cbe61d8a | 1126 | static bool ath9k_hw_channel_change(struct ath_hw *ah, |
25c56eec | 1127 | struct ath9k_channel *chan) |
f078f209 | 1128 | { |
608b88cb | 1129 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
c46917bb | 1130 | struct ath_common *common = ath9k_hw_common(ah); |
5f8e077c | 1131 | struct ieee80211_channel *channel = chan->chan; |
8fe65368 | 1132 | u32 qnum; |
0a3b7bac | 1133 | int r; |
f078f209 LR |
1134 | |
1135 | for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { | |
1136 | if (ath9k_hw_numtxpending(ah, qnum)) { | |
226afe68 JP |
1137 | ath_dbg(common, ATH_DBG_QUEUE, |
1138 | "Transmit frames pending on queue %d\n", qnum); | |
f078f209 LR |
1139 | return false; |
1140 | } | |
1141 | } | |
1142 | ||
8fe65368 | 1143 | if (!ath9k_hw_rfbus_req(ah)) { |
3800276a | 1144 | ath_err(common, "Could not kill baseband RX\n"); |
f078f209 LR |
1145 | return false; |
1146 | } | |
1147 | ||
8fe65368 | 1148 | ath9k_hw_set_channel_regs(ah, chan); |
f078f209 | 1149 | |
8fe65368 | 1150 | r = ath9k_hw_rf_set_freq(ah, chan); |
0a3b7bac | 1151 | if (r) { |
3800276a | 1152 | ath_err(common, "Failed to set channel\n"); |
0a3b7bac | 1153 | return false; |
f078f209 | 1154 | } |
dfdac8ac | 1155 | ath9k_hw_set_clockrate(ah); |
f078f209 | 1156 | |
8fbff4b8 | 1157 | ah->eep_ops->set_txpower(ah, chan, |
608b88cb | 1158 | ath9k_regd_get_ctl(regulatory, chan), |
f74df6fb S |
1159 | channel->max_antenna_gain * 2, |
1160 | channel->max_power * 2, | |
1161 | min((u32) MAX_RATE_POWER, | |
de40f316 | 1162 | (u32) regulatory->power_limit), false); |
f078f209 | 1163 | |
8fe65368 | 1164 | ath9k_hw_rfbus_done(ah); |
f078f209 | 1165 | |
f1dc5600 S |
1166 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
1167 | ath9k_hw_set_delta_slope(ah, chan); | |
1168 | ||
8fe65368 | 1169 | ath9k_hw_spur_mitigate_freq(ah, chan); |
f1dc5600 | 1170 | |
f1dc5600 S |
1171 | return true; |
1172 | } | |
1173 | ||
c9c99e5e | 1174 | bool ath9k_hw_check_alive(struct ath_hw *ah) |
3b319aae | 1175 | { |
c9c99e5e FF |
1176 | int count = 50; |
1177 | u32 reg; | |
1178 | ||
e17f83ea | 1179 | if (AR_SREV_9285_12_OR_LATER(ah)) |
c9c99e5e FF |
1180 | return true; |
1181 | ||
1182 | do { | |
1183 | reg = REG_READ(ah, AR_OBS_BUS_1); | |
3b319aae | 1184 | |
c9c99e5e FF |
1185 | if ((reg & 0x7E7FFFEF) == 0x00702400) |
1186 | continue; | |
1187 | ||
1188 | switch (reg & 0x7E000B00) { | |
1189 | case 0x1E000000: | |
1190 | case 0x52000B00: | |
1191 | case 0x18000B00: | |
1192 | continue; | |
1193 | default: | |
1194 | return true; | |
1195 | } | |
1196 | } while (count-- > 0); | |
3b319aae | 1197 | |
c9c99e5e | 1198 | return false; |
3b319aae | 1199 | } |
c9c99e5e | 1200 | EXPORT_SYMBOL(ath9k_hw_check_alive); |
3b319aae | 1201 | |
cbe61d8a | 1202 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
20bd2a09 | 1203 | struct ath9k_hw_cal_data *caldata, bool bChannelChange) |
f078f209 | 1204 | { |
1510718d | 1205 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 1206 | u32 saveLedState; |
2660b81a | 1207 | struct ath9k_channel *curchan = ah->curchan; |
f078f209 LR |
1208 | u32 saveDefAntenna; |
1209 | u32 macStaId1; | |
46fe782c | 1210 | u64 tsf = 0; |
8fe65368 | 1211 | int i, r; |
f078f209 | 1212 | |
43c27613 LR |
1213 | ah->txchainmask = common->tx_chainmask; |
1214 | ah->rxchainmask = common->rx_chainmask; | |
f078f209 | 1215 | |
9b9cc61c VT |
1216 | if (!ah->chip_fullsleep) { |
1217 | ath9k_hw_abortpcurecv(ah); | |
9cc2f3e8 | 1218 | if (!ath9k_hw_stopdmarecv(ah)) { |
226afe68 | 1219 | ath_dbg(common, ATH_DBG_XMIT, |
9b9cc61c | 1220 | "Failed to stop receive dma\n"); |
9cc2f3e8 FF |
1221 | bChannelChange = false; |
1222 | } | |
9b9cc61c VT |
1223 | } |
1224 | ||
9ecdef4b | 1225 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
ae8d2858 | 1226 | return -EIO; |
f078f209 | 1227 | |
d9891c78 | 1228 | if (curchan && !ah->chip_fullsleep) |
f078f209 LR |
1229 | ath9k_hw_getnf(ah, curchan); |
1230 | ||
20bd2a09 FF |
1231 | ah->caldata = caldata; |
1232 | if (caldata && | |
1233 | (chan->channel != caldata->channel || | |
1234 | (chan->channelFlags & ~CHANNEL_CW_INT) != | |
1235 | (caldata->channelFlags & ~CHANNEL_CW_INT))) { | |
1236 | /* Operating channel changed, reset channel calibration data */ | |
1237 | memset(caldata, 0, sizeof(*caldata)); | |
1238 | ath9k_init_nfcal_hist_buffer(ah, chan); | |
1239 | } | |
1240 | ||
f078f209 | 1241 | if (bChannelChange && |
2660b81a S |
1242 | (ah->chip_fullsleep != true) && |
1243 | (ah->curchan != NULL) && | |
1244 | (chan->channel != ah->curchan->channel) && | |
f078f209 | 1245 | ((chan->channelFlags & CHANNEL_ALL) == |
2660b81a | 1246 | (ah->curchan->channelFlags & CHANNEL_ALL)) && |
58d7e0f3 | 1247 | (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) { |
f078f209 | 1248 | |
25c56eec | 1249 | if (ath9k_hw_channel_change(ah, chan)) { |
2660b81a | 1250 | ath9k_hw_loadnf(ah, ah->curchan); |
00c86590 | 1251 | ath9k_hw_start_nfcal(ah, true); |
c2ba3342 RM |
1252 | if (AR_SREV_9271(ah)) |
1253 | ar9002_hw_load_ani_reg(ah, chan); | |
ae8d2858 | 1254 | return 0; |
f078f209 LR |
1255 | } |
1256 | } | |
1257 | ||
1258 | saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); | |
1259 | if (saveDefAntenna == 0) | |
1260 | saveDefAntenna = 1; | |
1261 | ||
1262 | macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; | |
1263 | ||
46fe782c | 1264 | /* For chips on which RTC reset is done, save TSF before it gets cleared */ |
f860d526 FF |
1265 | if (AR_SREV_9100(ah) || |
1266 | (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) | |
46fe782c S |
1267 | tsf = ath9k_hw_gettsf64(ah); |
1268 | ||
f078f209 LR |
1269 | saveLedState = REG_READ(ah, AR_CFG_LED) & |
1270 | (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | | |
1271 | AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); | |
1272 | ||
1273 | ath9k_hw_mark_phy_inactive(ah); | |
1274 | ||
05020d23 | 1275 | /* Only required on the first reset */ |
d7e7d229 LR |
1276 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
1277 | REG_WRITE(ah, | |
1278 | AR9271_RESET_POWER_DOWN_CONTROL, | |
1279 | AR9271_RADIO_RF_RST); | |
1280 | udelay(50); | |
1281 | } | |
1282 | ||
f078f209 | 1283 | if (!ath9k_hw_chip_reset(ah, chan)) { |
3800276a | 1284 | ath_err(common, "Chip reset failed\n"); |
ae8d2858 | 1285 | return -EINVAL; |
f078f209 LR |
1286 | } |
1287 | ||
05020d23 | 1288 | /* Only required on the first reset */ |
d7e7d229 LR |
1289 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
1290 | ah->htc_reset_init = false; | |
1291 | REG_WRITE(ah, | |
1292 | AR9271_RESET_POWER_DOWN_CONTROL, | |
1293 | AR9271_GATE_MAC_CTL); | |
1294 | udelay(50); | |
1295 | } | |
1296 | ||
46fe782c | 1297 | /* Restore TSF */ |
f860d526 | 1298 | if (tsf) |
46fe782c S |
1299 | ath9k_hw_settsf64(ah, tsf); |
1300 | ||
7a37081e | 1301 | if (AR_SREV_9280_20_OR_LATER(ah)) |
369391db | 1302 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); |
f078f209 | 1303 | |
e9141f71 S |
1304 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
1305 | ar9002_hw_enable_async_fifo(ah); | |
1306 | ||
25c56eec | 1307 | r = ath9k_hw_process_ini(ah, chan); |
ae8d2858 LR |
1308 | if (r) |
1309 | return r; | |
f078f209 | 1310 | |
f860d526 FF |
1311 | /* |
1312 | * Some AR91xx SoC devices frequently fail to accept TSF writes | |
1313 | * right after the chip reset. When that happens, write a new | |
1314 | * value after the initvals have been applied, with an offset | |
1315 | * based on measured time difference | |
1316 | */ | |
1317 | if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { | |
1318 | tsf += 1500; | |
1319 | ath9k_hw_settsf64(ah, tsf); | |
1320 | } | |
1321 | ||
0ced0e17 JM |
1322 | /* Setup MFP options for CCMP */ |
1323 | if (AR_SREV_9280_20_OR_LATER(ah)) { | |
1324 | /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt | |
1325 | * frames when constructing CCMP AAD. */ | |
1326 | REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, | |
1327 | 0xc7ff); | |
1328 | ah->sw_mgmt_crypto = false; | |
1329 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { | |
1330 | /* Disable hardware crypto for management frames */ | |
1331 | REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, | |
1332 | AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); | |
1333 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, | |
1334 | AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); | |
1335 | ah->sw_mgmt_crypto = true; | |
1336 | } else | |
1337 | ah->sw_mgmt_crypto = true; | |
1338 | ||
f078f209 LR |
1339 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
1340 | ath9k_hw_set_delta_slope(ah, chan); | |
1341 | ||
8fe65368 | 1342 | ath9k_hw_spur_mitigate_freq(ah, chan); |
d6509151 | 1343 | ah->eep_ops->set_board_values(ah, chan); |
a7765828 | 1344 | |
6819d57f S |
1345 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
1346 | ||
7d0d0df0 S |
1347 | ENABLE_REGWRITE_BUFFER(ah); |
1348 | ||
1510718d LR |
1349 | REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); |
1350 | REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) | |
f078f209 LR |
1351 | | macStaId1 |
1352 | | AR_STA_ID1_RTS_USE_DEF | |
2660b81a | 1353 | | (ah->config. |
60b67f51 | 1354 | ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) |
2660b81a | 1355 | | ah->sta_id1_defaults); |
13b81559 | 1356 | ath_hw_setbssidmask(common); |
f078f209 | 1357 | REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); |
3453ad88 | 1358 | ath9k_hw_write_associd(ah); |
f078f209 | 1359 | REG_WRITE(ah, AR_ISR, ~0); |
f078f209 LR |
1360 | REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); |
1361 | ||
7d0d0df0 | 1362 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1363 | |
8fe65368 | 1364 | r = ath9k_hw_rf_set_freq(ah, chan); |
0a3b7bac LR |
1365 | if (r) |
1366 | return r; | |
f078f209 | 1367 | |
dfdac8ac FF |
1368 | ath9k_hw_set_clockrate(ah); |
1369 | ||
7d0d0df0 S |
1370 | ENABLE_REGWRITE_BUFFER(ah); |
1371 | ||
f078f209 LR |
1372 | for (i = 0; i < AR_NUM_DCU; i++) |
1373 | REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); | |
1374 | ||
7d0d0df0 | 1375 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1376 | |
2660b81a S |
1377 | ah->intr_txqs = 0; |
1378 | for (i = 0; i < ah->caps.total_queues; i++) | |
f078f209 LR |
1379 | ath9k_hw_resettxqueue(ah, i); |
1380 | ||
2660b81a | 1381 | ath9k_hw_init_interrupt_masks(ah, ah->opmode); |
e36b27af | 1382 | ath9k_hw_ani_cache_ini_regs(ah); |
f078f209 LR |
1383 | ath9k_hw_init_qos(ah); |
1384 | ||
2660b81a | 1385 | if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) |
500c064d | 1386 | ath9k_enable_rfkill(ah); |
3b319aae | 1387 | |
0005baf4 | 1388 | ath9k_hw_init_global_settings(ah); |
f078f209 | 1389 | |
6c94fdc9 | 1390 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
e9141f71 | 1391 | ar9002_hw_update_async_fifo(ah); |
6c94fdc9 | 1392 | ar9002_hw_enable_wep_aggregation(ah); |
ac88b6ec VN |
1393 | } |
1394 | ||
f078f209 LR |
1395 | REG_WRITE(ah, AR_STA_ID1, |
1396 | REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); | |
1397 | ||
1398 | ath9k_hw_set_dma(ah); | |
1399 | ||
1400 | REG_WRITE(ah, AR_OBS, 8); | |
1401 | ||
0ce024cb | 1402 | if (ah->config.rx_intr_mitigation) { |
f078f209 LR |
1403 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); |
1404 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); | |
1405 | } | |
1406 | ||
7f62a136 VT |
1407 | if (ah->config.tx_intr_mitigation) { |
1408 | REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); | |
1409 | REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); | |
1410 | } | |
1411 | ||
f078f209 LR |
1412 | ath9k_hw_init_bb(ah, chan); |
1413 | ||
ae8d2858 | 1414 | if (!ath9k_hw_init_cal(ah, chan)) |
6badaaf7 | 1415 | return -EIO; |
f078f209 | 1416 | |
7d0d0df0 | 1417 | ENABLE_REGWRITE_BUFFER(ah); |
f078f209 | 1418 | |
8fe65368 | 1419 | ath9k_hw_restore_chainmask(ah); |
f078f209 LR |
1420 | REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); |
1421 | ||
7d0d0df0 | 1422 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1423 | |
d7e7d229 LR |
1424 | /* |
1425 | * For big endian systems turn on swapping for descriptors | |
1426 | */ | |
f078f209 LR |
1427 | if (AR_SREV_9100(ah)) { |
1428 | u32 mask; | |
1429 | mask = REG_READ(ah, AR_CFG); | |
1430 | if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { | |
226afe68 | 1431 | ath_dbg(common, ATH_DBG_RESET, |
04bd4638 | 1432 | "CFG Byte Swap Set 0x%x\n", mask); |
f078f209 LR |
1433 | } else { |
1434 | mask = | |
1435 | INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; | |
1436 | REG_WRITE(ah, AR_CFG, mask); | |
226afe68 | 1437 | ath_dbg(common, ATH_DBG_RESET, |
04bd4638 | 1438 | "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); |
f078f209 LR |
1439 | } |
1440 | } else { | |
cbba8cd1 S |
1441 | if (common->bus_ops->ath_bus_type == ATH_USB) { |
1442 | /* Configure AR9271 target WLAN */ | |
1443 | if (AR_SREV_9271(ah)) | |
1444 | REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); | |
1445 | else | |
1446 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); | |
1447 | } | |
f078f209 | 1448 | #ifdef __BIG_ENDIAN |
d7e7d229 LR |
1449 | else |
1450 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); | |
f078f209 LR |
1451 | #endif |
1452 | } | |
1453 | ||
766ec4a9 | 1454 | if (ah->btcoex_hw.enabled) |
42cc41ed VT |
1455 | ath9k_hw_btcoex_enable(ah); |
1456 | ||
00c86590 | 1457 | if (AR_SREV_9300_20_OR_LATER(ah)) |
aea702b7 | 1458 | ar9003_hw_bb_watchdog_config(ah); |
d8903a53 | 1459 | |
ae8d2858 | 1460 | return 0; |
f078f209 | 1461 | } |
7322fd19 | 1462 | EXPORT_SYMBOL(ath9k_hw_reset); |
f078f209 | 1463 | |
f1dc5600 S |
1464 | /******************************/ |
1465 | /* Power Management (Chipset) */ | |
1466 | /******************************/ | |
1467 | ||
42d5bc3f LR |
1468 | /* |
1469 | * Notify Power Mgt is disabled in self-generated frames. | |
1470 | * If requested, force chip to sleep. | |
1471 | */ | |
cbe61d8a | 1472 | static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) |
f078f209 | 1473 | { |
f1dc5600 S |
1474 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
1475 | if (setChip) { | |
42d5bc3f LR |
1476 | /* |
1477 | * Clear the RTC force wake bit to allow the | |
1478 | * mac to go to sleep. | |
1479 | */ | |
f1dc5600 S |
1480 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, |
1481 | AR_RTC_FORCE_WAKE_EN); | |
42d5bc3f | 1482 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
f1dc5600 | 1483 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); |
f078f209 | 1484 | |
42d5bc3f | 1485 | /* Shutdown chip. Active low */ |
14b3af38 | 1486 | if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) |
4921be80 S |
1487 | REG_CLR_BIT(ah, (AR_RTC_RESET), |
1488 | AR_RTC_RESET_EN); | |
f1dc5600 | 1489 | } |
9a658d2b LR |
1490 | |
1491 | /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ | |
1492 | if (AR_SREV_9300_20_OR_LATER(ah)) | |
1493 | REG_WRITE(ah, AR_WA, | |
1494 | ah->WARegVal & ~AR_WA_D3_L1_DISABLE); | |
f078f209 LR |
1495 | } |
1496 | ||
bbd79af5 LR |
1497 | /* |
1498 | * Notify Power Management is enabled in self-generating | |
1499 | * frames. If request, set power mode of chip to | |
1500 | * auto/normal. Duration in units of 128us (1/8 TU). | |
1501 | */ | |
cbe61d8a | 1502 | static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) |
f078f209 | 1503 | { |
f1dc5600 S |
1504 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
1505 | if (setChip) { | |
2660b81a | 1506 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
f078f209 | 1507 | |
f1dc5600 | 1508 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
bbd79af5 | 1509 | /* Set WakeOnInterrupt bit; clear ForceWake bit */ |
f1dc5600 S |
1510 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
1511 | AR_RTC_FORCE_WAKE_ON_INT); | |
1512 | } else { | |
bbd79af5 LR |
1513 | /* |
1514 | * Clear the RTC force wake bit to allow the | |
1515 | * mac to go to sleep. | |
1516 | */ | |
f1dc5600 S |
1517 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, |
1518 | AR_RTC_FORCE_WAKE_EN); | |
f078f209 | 1519 | } |
f078f209 | 1520 | } |
9a658d2b LR |
1521 | |
1522 | /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ | |
1523 | if (AR_SREV_9300_20_OR_LATER(ah)) | |
1524 | REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); | |
f078f209 LR |
1525 | } |
1526 | ||
cbe61d8a | 1527 | static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) |
f078f209 | 1528 | { |
f1dc5600 S |
1529 | u32 val; |
1530 | int i; | |
f078f209 | 1531 | |
9a658d2b LR |
1532 | /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ |
1533 | if (AR_SREV_9300_20_OR_LATER(ah)) { | |
1534 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
1535 | udelay(10); | |
1536 | } | |
1537 | ||
f1dc5600 S |
1538 | if (setChip) { |
1539 | if ((REG_READ(ah, AR_RTC_STATUS) & | |
1540 | AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { | |
1541 | if (ath9k_hw_set_reset_reg(ah, | |
1542 | ATH9K_RESET_POWER_ON) != true) { | |
1543 | return false; | |
1544 | } | |
e041228f LR |
1545 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
1546 | ath9k_hw_init_pll(ah, NULL); | |
f1dc5600 S |
1547 | } |
1548 | if (AR_SREV_9100(ah)) | |
1549 | REG_SET_BIT(ah, AR_RTC_RESET, | |
1550 | AR_RTC_RESET_EN); | |
f078f209 | 1551 | |
f1dc5600 S |
1552 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, |
1553 | AR_RTC_FORCE_WAKE_EN); | |
1554 | udelay(50); | |
f078f209 | 1555 | |
f1dc5600 S |
1556 | for (i = POWER_UP_TIME / 50; i > 0; i--) { |
1557 | val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; | |
1558 | if (val == AR_RTC_STATUS_ON) | |
1559 | break; | |
1560 | udelay(50); | |
1561 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, | |
1562 | AR_RTC_FORCE_WAKE_EN); | |
f078f209 | 1563 | } |
f1dc5600 | 1564 | if (i == 0) { |
3800276a JP |
1565 | ath_err(ath9k_hw_common(ah), |
1566 | "Failed to wakeup in %uus\n", | |
1567 | POWER_UP_TIME / 20); | |
f1dc5600 | 1568 | return false; |
f078f209 | 1569 | } |
f078f209 LR |
1570 | } |
1571 | ||
f1dc5600 | 1572 | REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
f078f209 | 1573 | |
f1dc5600 | 1574 | return true; |
f078f209 LR |
1575 | } |
1576 | ||
9ecdef4b | 1577 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) |
f078f209 | 1578 | { |
c46917bb | 1579 | struct ath_common *common = ath9k_hw_common(ah); |
cbe61d8a | 1580 | int status = true, setChip = true; |
f1dc5600 S |
1581 | static const char *modes[] = { |
1582 | "AWAKE", | |
1583 | "FULL-SLEEP", | |
1584 | "NETWORK SLEEP", | |
1585 | "UNDEFINED" | |
1586 | }; | |
f1dc5600 | 1587 | |
cbdec975 GJ |
1588 | if (ah->power_mode == mode) |
1589 | return status; | |
1590 | ||
226afe68 JP |
1591 | ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n", |
1592 | modes[ah->power_mode], modes[mode]); | |
f1dc5600 S |
1593 | |
1594 | switch (mode) { | |
1595 | case ATH9K_PM_AWAKE: | |
1596 | status = ath9k_hw_set_power_awake(ah, setChip); | |
1597 | break; | |
1598 | case ATH9K_PM_FULL_SLEEP: | |
1599 | ath9k_set_power_sleep(ah, setChip); | |
2660b81a | 1600 | ah->chip_fullsleep = true; |
f1dc5600 S |
1601 | break; |
1602 | case ATH9K_PM_NETWORK_SLEEP: | |
1603 | ath9k_set_power_network_sleep(ah, setChip); | |
1604 | break; | |
f078f209 | 1605 | default: |
3800276a | 1606 | ath_err(common, "Unknown power mode %u\n", mode); |
f078f209 LR |
1607 | return false; |
1608 | } | |
2660b81a | 1609 | ah->power_mode = mode; |
f1dc5600 | 1610 | |
69f4aab1 LR |
1611 | /* |
1612 | * XXX: If this warning never comes up after a while then | |
1613 | * simply keep the ATH_DBG_WARN_ON_ONCE() but make | |
1614 | * ath9k_hw_setpower() return type void. | |
1615 | */ | |
1616 | ATH_DBG_WARN_ON_ONCE(!status); | |
1617 | ||
f1dc5600 | 1618 | return status; |
f078f209 | 1619 | } |
7322fd19 | 1620 | EXPORT_SYMBOL(ath9k_hw_setpower); |
f078f209 | 1621 | |
f1dc5600 S |
1622 | /*******************/ |
1623 | /* Beacon Handling */ | |
1624 | /*******************/ | |
1625 | ||
cbe61d8a | 1626 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) |
f078f209 | 1627 | { |
f078f209 LR |
1628 | int flags = 0; |
1629 | ||
2660b81a | 1630 | ah->beacon_interval = beacon_period; |
f078f209 | 1631 | |
7d0d0df0 S |
1632 | ENABLE_REGWRITE_BUFFER(ah); |
1633 | ||
2660b81a | 1634 | switch (ah->opmode) { |
d97809db | 1635 | case NL80211_IFTYPE_ADHOC: |
9cb5412b | 1636 | case NL80211_IFTYPE_MESH_POINT: |
f078f209 LR |
1637 | REG_SET_BIT(ah, AR_TXCFG, |
1638 | AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); | |
1639 | REG_WRITE(ah, AR_NEXT_NDP_TIMER, | |
1640 | TU_TO_USEC(next_beacon + | |
2660b81a S |
1641 | (ah->atim_window ? ah-> |
1642 | atim_window : 1))); | |
f078f209 | 1643 | flags |= AR_NDP_TIMER_EN; |
d97809db | 1644 | case NL80211_IFTYPE_AP: |
f078f209 LR |
1645 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); |
1646 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, | |
1647 | TU_TO_USEC(next_beacon - | |
2660b81a | 1648 | ah->config. |
60b67f51 | 1649 | dma_beacon_response_time)); |
f078f209 LR |
1650 | REG_WRITE(ah, AR_NEXT_SWBA, |
1651 | TU_TO_USEC(next_beacon - | |
2660b81a | 1652 | ah->config. |
60b67f51 | 1653 | sw_beacon_response_time)); |
f078f209 LR |
1654 | flags |= |
1655 | AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; | |
1656 | break; | |
d97809db | 1657 | default: |
226afe68 JP |
1658 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON, |
1659 | "%s: unsupported opmode: %d\n", | |
1660 | __func__, ah->opmode); | |
d97809db CM |
1661 | return; |
1662 | break; | |
f078f209 LR |
1663 | } |
1664 | ||
1665 | REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); | |
1666 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); | |
1667 | REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); | |
1668 | REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); | |
1669 | ||
7d0d0df0 | 1670 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1671 | |
f078f209 LR |
1672 | beacon_period &= ~ATH9K_BEACON_ENA; |
1673 | if (beacon_period & ATH9K_BEACON_RESET_TSF) { | |
f078f209 LR |
1674 | ath9k_hw_reset_tsf(ah); |
1675 | } | |
1676 | ||
1677 | REG_SET_BIT(ah, AR_TIMER_MODE, flags); | |
1678 | } | |
7322fd19 | 1679 | EXPORT_SYMBOL(ath9k_hw_beaconinit); |
f078f209 | 1680 | |
cbe61d8a | 1681 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, |
f1dc5600 | 1682 | const struct ath9k_beacon_state *bs) |
f078f209 LR |
1683 | { |
1684 | u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; | |
2660b81a | 1685 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
c46917bb | 1686 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 1687 | |
7d0d0df0 S |
1688 | ENABLE_REGWRITE_BUFFER(ah); |
1689 | ||
f078f209 LR |
1690 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); |
1691 | ||
1692 | REG_WRITE(ah, AR_BEACON_PERIOD, | |
1693 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); | |
1694 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, | |
1695 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); | |
1696 | ||
7d0d0df0 | 1697 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1698 | |
f078f209 LR |
1699 | REG_RMW_FIELD(ah, AR_RSSI_THR, |
1700 | AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); | |
1701 | ||
1702 | beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; | |
1703 | ||
1704 | if (bs->bs_sleepduration > beaconintval) | |
1705 | beaconintval = bs->bs_sleepduration; | |
1706 | ||
1707 | dtimperiod = bs->bs_dtimperiod; | |
1708 | if (bs->bs_sleepduration > dtimperiod) | |
1709 | dtimperiod = bs->bs_sleepduration; | |
1710 | ||
1711 | if (beaconintval == dtimperiod) | |
1712 | nextTbtt = bs->bs_nextdtim; | |
1713 | else | |
1714 | nextTbtt = bs->bs_nexttbtt; | |
1715 | ||
226afe68 JP |
1716 | ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); |
1717 | ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); | |
1718 | ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); | |
1719 | ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); | |
f078f209 | 1720 | |
7d0d0df0 S |
1721 | ENABLE_REGWRITE_BUFFER(ah); |
1722 | ||
f1dc5600 S |
1723 | REG_WRITE(ah, AR_NEXT_DTIM, |
1724 | TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); | |
1725 | REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); | |
f078f209 | 1726 | |
f1dc5600 S |
1727 | REG_WRITE(ah, AR_SLEEP1, |
1728 | SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) | |
1729 | | AR_SLEEP1_ASSUME_DTIM); | |
f078f209 | 1730 | |
f1dc5600 S |
1731 | if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) |
1732 | beacontimeout = (BEACON_TIMEOUT_VAL << 3); | |
1733 | else | |
1734 | beacontimeout = MIN_BEACON_TIMEOUT_VAL; | |
f078f209 | 1735 | |
f1dc5600 S |
1736 | REG_WRITE(ah, AR_SLEEP2, |
1737 | SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); | |
f078f209 | 1738 | |
f1dc5600 S |
1739 | REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); |
1740 | REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); | |
f078f209 | 1741 | |
7d0d0df0 | 1742 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1743 | |
f1dc5600 S |
1744 | REG_SET_BIT(ah, AR_TIMER_MODE, |
1745 | AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | | |
1746 | AR_DTIM_TIMER_EN); | |
f078f209 | 1747 | |
4af9cf4f S |
1748 | /* TSF Out of Range Threshold */ |
1749 | REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); | |
f078f209 | 1750 | } |
7322fd19 | 1751 | EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); |
f078f209 | 1752 | |
f1dc5600 S |
1753 | /*******************/ |
1754 | /* HW Capabilities */ | |
1755 | /*******************/ | |
1756 | ||
a9a29ce6 | 1757 | int ath9k_hw_fill_cap_info(struct ath_hw *ah) |
f078f209 | 1758 | { |
2660b81a | 1759 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
608b88cb | 1760 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
c46917bb | 1761 | struct ath_common *common = ath9k_hw_common(ah); |
766ec4a9 | 1762 | struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; |
608b88cb | 1763 | |
f1dc5600 | 1764 | u16 capField = 0, eeval; |
47c80de6 | 1765 | u8 ant_div_ctl1, tx_chainmask, rx_chainmask; |
f078f209 | 1766 | |
f74df6fb | 1767 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); |
608b88cb | 1768 | regulatory->current_rd = eeval; |
f078f209 | 1769 | |
f74df6fb | 1770 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); |
e17f83ea | 1771 | if (AR_SREV_9285_12_OR_LATER(ah)) |
fec0de11 | 1772 | eeval |= AR9285_RDEXT_DEFAULT; |
608b88cb | 1773 | regulatory->current_rd_ext = eeval; |
f078f209 | 1774 | |
f74df6fb | 1775 | capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); |
f1dc5600 | 1776 | |
2660b81a | 1777 | if (ah->opmode != NL80211_IFTYPE_AP && |
d535a42a | 1778 | ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { |
608b88cb LR |
1779 | if (regulatory->current_rd == 0x64 || |
1780 | regulatory->current_rd == 0x65) | |
1781 | regulatory->current_rd += 5; | |
1782 | else if (regulatory->current_rd == 0x41) | |
1783 | regulatory->current_rd = 0x43; | |
226afe68 JP |
1784 | ath_dbg(common, ATH_DBG_REGULATORY, |
1785 | "regdomain mapped to 0x%x\n", regulatory->current_rd); | |
f1dc5600 | 1786 | } |
f078f209 | 1787 | |
f74df6fb | 1788 | eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); |
a9a29ce6 | 1789 | if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { |
3800276a JP |
1790 | ath_err(common, |
1791 | "no band has been marked as supported in EEPROM\n"); | |
a9a29ce6 GJ |
1792 | return -EINVAL; |
1793 | } | |
1794 | ||
d4659912 FF |
1795 | if (eeval & AR5416_OPFLAGS_11A) |
1796 | pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; | |
f078f209 | 1797 | |
d4659912 FF |
1798 | if (eeval & AR5416_OPFLAGS_11G) |
1799 | pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; | |
f1dc5600 | 1800 | |
f74df6fb | 1801 | pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); |
d7e7d229 LR |
1802 | /* |
1803 | * For AR9271 we will temporarilly uses the rx chainmax as read from | |
1804 | * the EEPROM. | |
1805 | */ | |
8147f5de | 1806 | if ((ah->hw_version.devid == AR5416_DEVID_PCI) && |
d7e7d229 LR |
1807 | !(eeval & AR5416_OPFLAGS_11A) && |
1808 | !(AR_SREV_9271(ah))) | |
1809 | /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ | |
8147f5de S |
1810 | pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; |
1811 | else | |
d7e7d229 | 1812 | /* Use rx_chainmask from EEPROM. */ |
8147f5de | 1813 | pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); |
f078f209 | 1814 | |
7a37081e | 1815 | ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; |
f078f209 | 1816 | |
02d2ebb2 FF |
1817 | /* enable key search for every frame in an aggregate */ |
1818 | if (AR_SREV_9300_20_OR_LATER(ah)) | |
1819 | ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; | |
1820 | ||
f1dc5600 S |
1821 | pCap->low_2ghz_chan = 2312; |
1822 | pCap->high_2ghz_chan = 2732; | |
f078f209 | 1823 | |
f1dc5600 S |
1824 | pCap->low_5ghz_chan = 4920; |
1825 | pCap->high_5ghz_chan = 6100; | |
f078f209 | 1826 | |
ce2220d1 BR |
1827 | common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; |
1828 | ||
2660b81a | 1829 | if (ah->config.ht_enable) |
f1dc5600 S |
1830 | pCap->hw_caps |= ATH9K_HW_CAP_HT; |
1831 | else | |
1832 | pCap->hw_caps &= ~ATH9K_HW_CAP_HT; | |
f078f209 | 1833 | |
f1dc5600 S |
1834 | if (capField & AR_EEPROM_EEPCAP_MAXQCU) |
1835 | pCap->total_queues = | |
1836 | MS(capField, AR_EEPROM_EEPCAP_MAXQCU); | |
1837 | else | |
1838 | pCap->total_queues = ATH9K_NUM_TX_QUEUES; | |
f078f209 | 1839 | |
f1dc5600 S |
1840 | if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) |
1841 | pCap->keycache_size = | |
1842 | 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); | |
1843 | else | |
1844 | pCap->keycache_size = AR_KEYTABLE_SIZE; | |
f078f209 | 1845 | |
f4709fdf LR |
1846 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
1847 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1; | |
1848 | else | |
1849 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; | |
f078f209 | 1850 | |
5b5fa355 S |
1851 | if (AR_SREV_9271(ah)) |
1852 | pCap->num_gpio_pins = AR9271_NUM_GPIO; | |
88c1f4f6 S |
1853 | else if (AR_DEVID_7010(ah)) |
1854 | pCap->num_gpio_pins = AR7010_NUM_GPIO; | |
e17f83ea | 1855 | else if (AR_SREV_9285_12_OR_LATER(ah)) |
cb33c412 | 1856 | pCap->num_gpio_pins = AR9285_NUM_GPIO; |
7a37081e | 1857 | else if (AR_SREV_9280_20_OR_LATER(ah)) |
f1dc5600 S |
1858 | pCap->num_gpio_pins = AR928X_NUM_GPIO; |
1859 | else | |
1860 | pCap->num_gpio_pins = AR_NUM_GPIO; | |
f078f209 | 1861 | |
f1dc5600 S |
1862 | if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { |
1863 | pCap->hw_caps |= ATH9K_HW_CAP_CST; | |
1864 | pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; | |
1865 | } else { | |
1866 | pCap->rts_aggr_limit = (8 * 1024); | |
f078f209 LR |
1867 | } |
1868 | ||
f1dc5600 S |
1869 | pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; |
1870 | ||
e97275cb | 1871 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
2660b81a S |
1872 | ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); |
1873 | if (ah->rfsilent & EEP_RFSILENT_ENABLED) { | |
1874 | ah->rfkill_gpio = | |
1875 | MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); | |
1876 | ah->rfkill_polarity = | |
1877 | MS(ah->rfsilent, EEP_RFSILENT_POLARITY); | |
f1dc5600 S |
1878 | |
1879 | pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; | |
f078f209 | 1880 | } |
f1dc5600 | 1881 | #endif |
d5d1154f | 1882 | if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) |
bde748a4 VN |
1883 | pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; |
1884 | else | |
1885 | pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; | |
f078f209 | 1886 | |
e7594072 | 1887 | if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) |
f1dc5600 S |
1888 | pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; |
1889 | else | |
1890 | pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; | |
f078f209 | 1891 | |
608b88cb | 1892 | if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { |
f1dc5600 S |
1893 | pCap->reg_cap = |
1894 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | | |
1895 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | | |
1896 | AR_EEPROM_EEREGCAP_EN_KK_U2 | | |
1897 | AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; | |
f078f209 | 1898 | } else { |
f1dc5600 S |
1899 | pCap->reg_cap = |
1900 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | | |
1901 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; | |
f078f209 | 1902 | } |
f078f209 | 1903 | |
ebb90cfc SB |
1904 | /* Advertise midband for AR5416 with FCC midband set in eeprom */ |
1905 | if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) && | |
1906 | AR_SREV_5416(ah)) | |
1907 | pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; | |
f1dc5600 S |
1908 | |
1909 | pCap->num_antcfg_5ghz = | |
f74df6fb | 1910 | ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); |
f1dc5600 | 1911 | pCap->num_antcfg_2ghz = |
f74df6fb | 1912 | ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); |
f078f209 | 1913 | |
8f5dcb1c | 1914 | if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) { |
766ec4a9 LR |
1915 | btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO; |
1916 | btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO; | |
22f25d0d | 1917 | |
8c8f9ba7 | 1918 | if (AR_SREV_9285(ah)) { |
766ec4a9 LR |
1919 | btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; |
1920 | btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO; | |
8c8f9ba7 | 1921 | } else { |
766ec4a9 | 1922 | btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; |
8c8f9ba7 | 1923 | } |
22f25d0d | 1924 | } else { |
766ec4a9 | 1925 | btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; |
c97c92d9 | 1926 | } |
a9a29ce6 | 1927 | |
ceb26445 | 1928 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
784ad503 VT |
1929 | pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; |
1930 | if (!AR_SREV_9485(ah)) | |
1931 | pCap->hw_caps |= ATH9K_HW_CAP_LDPC; | |
1932 | ||
ceb26445 VT |
1933 | pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; |
1934 | pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; | |
1935 | pCap->rx_status_len = sizeof(struct ar9003_rxs); | |
162c3be3 | 1936 | pCap->tx_desc_len = sizeof(struct ar9003_txc); |
5088c2f1 | 1937 | pCap->txs_len = sizeof(struct ar9003_txs); |
4935250a FF |
1938 | if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) |
1939 | pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; | |
162c3be3 VT |
1940 | } else { |
1941 | pCap->tx_desc_len = sizeof(struct ath_desc); | |
6b42e8d0 FF |
1942 | if (AR_SREV_9280_20(ah) && |
1943 | ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <= | |
1944 | AR5416_EEP_MINOR_VER_16) || | |
1945 | ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G))) | |
1946 | pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; | |
ceb26445 | 1947 | } |
1adf02ff | 1948 | |
6c84ce08 VT |
1949 | if (AR_SREV_9300_20_OR_LATER(ah)) |
1950 | pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; | |
1951 | ||
6ee63f55 SB |
1952 | if (AR_SREV_9300_20_OR_LATER(ah)) |
1953 | ah->ent_mode = REG_READ(ah, AR_ENT_OTP); | |
1954 | ||
a42acef0 | 1955 | if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) |
6473d24d VT |
1956 | pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; |
1957 | ||
754dc536 VT |
1958 | if (AR_SREV_9285(ah)) |
1959 | if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { | |
1960 | ant_div_ctl1 = | |
1961 | ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); | |
1962 | if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) | |
1963 | pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; | |
1964 | } | |
ea066d5a MSS |
1965 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
1966 | if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) | |
1967 | pCap->hw_caps |= ATH9K_HW_CAP_APM; | |
1968 | } | |
1969 | ||
1970 | ||
754dc536 | 1971 | |
8060e169 VT |
1972 | if (AR_SREV_9485_10(ah)) { |
1973 | pCap->pcie_lcr_extsync_en = true; | |
1974 | pCap->pcie_lcr_offset = 0x80; | |
1975 | } | |
1976 | ||
47c80de6 VT |
1977 | tx_chainmask = pCap->tx_chainmask; |
1978 | rx_chainmask = pCap->rx_chainmask; | |
1979 | while (tx_chainmask || rx_chainmask) { | |
1980 | if (tx_chainmask & BIT(0)) | |
1981 | pCap->max_txchains++; | |
1982 | if (rx_chainmask & BIT(0)) | |
1983 | pCap->max_rxchains++; | |
1984 | ||
1985 | tx_chainmask >>= 1; | |
1986 | rx_chainmask >>= 1; | |
1987 | } | |
1988 | ||
a9a29ce6 | 1989 | return 0; |
f078f209 LR |
1990 | } |
1991 | ||
f1dc5600 S |
1992 | /****************************/ |
1993 | /* GPIO / RFKILL / Antennae */ | |
1994 | /****************************/ | |
f078f209 | 1995 | |
cbe61d8a | 1996 | static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, |
f1dc5600 S |
1997 | u32 gpio, u32 type) |
1998 | { | |
1999 | int addr; | |
2000 | u32 gpio_shift, tmp; | |
f078f209 | 2001 | |
f1dc5600 S |
2002 | if (gpio > 11) |
2003 | addr = AR_GPIO_OUTPUT_MUX3; | |
2004 | else if (gpio > 5) | |
2005 | addr = AR_GPIO_OUTPUT_MUX2; | |
2006 | else | |
2007 | addr = AR_GPIO_OUTPUT_MUX1; | |
f078f209 | 2008 | |
f1dc5600 | 2009 | gpio_shift = (gpio % 6) * 5; |
f078f209 | 2010 | |
f1dc5600 S |
2011 | if (AR_SREV_9280_20_OR_LATER(ah) |
2012 | || (addr != AR_GPIO_OUTPUT_MUX1)) { | |
2013 | REG_RMW(ah, addr, (type << gpio_shift), | |
2014 | (0x1f << gpio_shift)); | |
f078f209 | 2015 | } else { |
f1dc5600 S |
2016 | tmp = REG_READ(ah, addr); |
2017 | tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); | |
2018 | tmp &= ~(0x1f << gpio_shift); | |
2019 | tmp |= (type << gpio_shift); | |
2020 | REG_WRITE(ah, addr, tmp); | |
f078f209 | 2021 | } |
f078f209 LR |
2022 | } |
2023 | ||
cbe61d8a | 2024 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) |
f078f209 | 2025 | { |
f1dc5600 | 2026 | u32 gpio_shift; |
f078f209 | 2027 | |
9680e8a3 | 2028 | BUG_ON(gpio >= ah->caps.num_gpio_pins); |
f078f209 | 2029 | |
88c1f4f6 S |
2030 | if (AR_DEVID_7010(ah)) { |
2031 | gpio_shift = gpio; | |
2032 | REG_RMW(ah, AR7010_GPIO_OE, | |
2033 | (AR7010_GPIO_OE_AS_INPUT << gpio_shift), | |
2034 | (AR7010_GPIO_OE_MASK << gpio_shift)); | |
2035 | return; | |
2036 | } | |
f078f209 | 2037 | |
88c1f4f6 | 2038 | gpio_shift = gpio << 1; |
f1dc5600 S |
2039 | REG_RMW(ah, |
2040 | AR_GPIO_OE_OUT, | |
2041 | (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), | |
2042 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); | |
f078f209 | 2043 | } |
7322fd19 | 2044 | EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); |
f078f209 | 2045 | |
cbe61d8a | 2046 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) |
f078f209 | 2047 | { |
cb33c412 SB |
2048 | #define MS_REG_READ(x, y) \ |
2049 | (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) | |
2050 | ||
2660b81a | 2051 | if (gpio >= ah->caps.num_gpio_pins) |
f1dc5600 | 2052 | return 0xffffffff; |
f078f209 | 2053 | |
88c1f4f6 S |
2054 | if (AR_DEVID_7010(ah)) { |
2055 | u32 val; | |
2056 | val = REG_READ(ah, AR7010_GPIO_IN); | |
2057 | return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; | |
2058 | } else if (AR_SREV_9300_20_OR_LATER(ah)) | |
9306990a VT |
2059 | return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & |
2060 | AR_GPIO_BIT(gpio)) != 0; | |
783dfca1 | 2061 | else if (AR_SREV_9271(ah)) |
5b5fa355 | 2062 | return MS_REG_READ(AR9271, gpio) != 0; |
a42acef0 | 2063 | else if (AR_SREV_9287_11_OR_LATER(ah)) |
ac88b6ec | 2064 | return MS_REG_READ(AR9287, gpio) != 0; |
e17f83ea | 2065 | else if (AR_SREV_9285_12_OR_LATER(ah)) |
cb33c412 | 2066 | return MS_REG_READ(AR9285, gpio) != 0; |
7a37081e | 2067 | else if (AR_SREV_9280_20_OR_LATER(ah)) |
cb33c412 SB |
2068 | return MS_REG_READ(AR928X, gpio) != 0; |
2069 | else | |
2070 | return MS_REG_READ(AR, gpio) != 0; | |
f078f209 | 2071 | } |
7322fd19 | 2072 | EXPORT_SYMBOL(ath9k_hw_gpio_get); |
f078f209 | 2073 | |
cbe61d8a | 2074 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, |
f1dc5600 | 2075 | u32 ah_signal_type) |
f078f209 | 2076 | { |
f1dc5600 | 2077 | u32 gpio_shift; |
f078f209 | 2078 | |
88c1f4f6 S |
2079 | if (AR_DEVID_7010(ah)) { |
2080 | gpio_shift = gpio; | |
2081 | REG_RMW(ah, AR7010_GPIO_OE, | |
2082 | (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), | |
2083 | (AR7010_GPIO_OE_MASK << gpio_shift)); | |
2084 | return; | |
2085 | } | |
f078f209 | 2086 | |
88c1f4f6 | 2087 | ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); |
f1dc5600 | 2088 | gpio_shift = 2 * gpio; |
f1dc5600 S |
2089 | REG_RMW(ah, |
2090 | AR_GPIO_OE_OUT, | |
2091 | (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), | |
2092 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); | |
f078f209 | 2093 | } |
7322fd19 | 2094 | EXPORT_SYMBOL(ath9k_hw_cfg_output); |
f078f209 | 2095 | |
cbe61d8a | 2096 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) |
f078f209 | 2097 | { |
88c1f4f6 S |
2098 | if (AR_DEVID_7010(ah)) { |
2099 | val = val ? 0 : 1; | |
2100 | REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), | |
2101 | AR_GPIO_BIT(gpio)); | |
2102 | return; | |
2103 | } | |
2104 | ||
5b5fa355 S |
2105 | if (AR_SREV_9271(ah)) |
2106 | val = ~val; | |
2107 | ||
f1dc5600 S |
2108 | REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), |
2109 | AR_GPIO_BIT(gpio)); | |
f078f209 | 2110 | } |
7322fd19 | 2111 | EXPORT_SYMBOL(ath9k_hw_set_gpio); |
f078f209 | 2112 | |
cbe61d8a | 2113 | u32 ath9k_hw_getdefantenna(struct ath_hw *ah) |
f078f209 | 2114 | { |
f1dc5600 | 2115 | return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; |
f078f209 | 2116 | } |
7322fd19 | 2117 | EXPORT_SYMBOL(ath9k_hw_getdefantenna); |
f078f209 | 2118 | |
cbe61d8a | 2119 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) |
f078f209 | 2120 | { |
f1dc5600 | 2121 | REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); |
f078f209 | 2122 | } |
7322fd19 | 2123 | EXPORT_SYMBOL(ath9k_hw_setantenna); |
f078f209 | 2124 | |
f1dc5600 S |
2125 | /*********************/ |
2126 | /* General Operation */ | |
2127 | /*********************/ | |
2128 | ||
cbe61d8a | 2129 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah) |
f078f209 | 2130 | { |
f1dc5600 S |
2131 | u32 bits = REG_READ(ah, AR_RX_FILTER); |
2132 | u32 phybits = REG_READ(ah, AR_PHY_ERR); | |
f078f209 | 2133 | |
f1dc5600 S |
2134 | if (phybits & AR_PHY_ERR_RADAR) |
2135 | bits |= ATH9K_RX_FILTER_PHYRADAR; | |
2136 | if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) | |
2137 | bits |= ATH9K_RX_FILTER_PHYERR; | |
dc2222a8 | 2138 | |
f1dc5600 | 2139 | return bits; |
f078f209 | 2140 | } |
7322fd19 | 2141 | EXPORT_SYMBOL(ath9k_hw_getrxfilter); |
f078f209 | 2142 | |
cbe61d8a | 2143 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) |
f078f209 | 2144 | { |
f1dc5600 | 2145 | u32 phybits; |
f078f209 | 2146 | |
7d0d0df0 S |
2147 | ENABLE_REGWRITE_BUFFER(ah); |
2148 | ||
7ea310be S |
2149 | REG_WRITE(ah, AR_RX_FILTER, bits); |
2150 | ||
f1dc5600 S |
2151 | phybits = 0; |
2152 | if (bits & ATH9K_RX_FILTER_PHYRADAR) | |
2153 | phybits |= AR_PHY_ERR_RADAR; | |
2154 | if (bits & ATH9K_RX_FILTER_PHYERR) | |
2155 | phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; | |
2156 | REG_WRITE(ah, AR_PHY_ERR, phybits); | |
f078f209 | 2157 | |
f1dc5600 S |
2158 | if (phybits) |
2159 | REG_WRITE(ah, AR_RXCFG, | |
2160 | REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); | |
2161 | else | |
2162 | REG_WRITE(ah, AR_RXCFG, | |
2163 | REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); | |
7d0d0df0 S |
2164 | |
2165 | REGWRITE_BUFFER_FLUSH(ah); | |
f1dc5600 | 2166 | } |
7322fd19 | 2167 | EXPORT_SYMBOL(ath9k_hw_setrxfilter); |
f078f209 | 2168 | |
cbe61d8a | 2169 | bool ath9k_hw_phy_disable(struct ath_hw *ah) |
f1dc5600 | 2170 | { |
63a75b91 SB |
2171 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) |
2172 | return false; | |
2173 | ||
2174 | ath9k_hw_init_pll(ah, NULL); | |
2175 | return true; | |
f1dc5600 | 2176 | } |
7322fd19 | 2177 | EXPORT_SYMBOL(ath9k_hw_phy_disable); |
f078f209 | 2178 | |
cbe61d8a | 2179 | bool ath9k_hw_disable(struct ath_hw *ah) |
f1dc5600 | 2180 | { |
9ecdef4b | 2181 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
f1dc5600 | 2182 | return false; |
f078f209 | 2183 | |
63a75b91 SB |
2184 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) |
2185 | return false; | |
2186 | ||
2187 | ath9k_hw_init_pll(ah, NULL); | |
2188 | return true; | |
f078f209 | 2189 | } |
7322fd19 | 2190 | EXPORT_SYMBOL(ath9k_hw_disable); |
f078f209 | 2191 | |
de40f316 | 2192 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) |
f078f209 | 2193 | { |
608b88cb | 2194 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
2660b81a | 2195 | struct ath9k_channel *chan = ah->curchan; |
5f8e077c | 2196 | struct ieee80211_channel *channel = chan->chan; |
f078f209 | 2197 | |
608b88cb | 2198 | regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); |
6f255425 | 2199 | |
8fbff4b8 | 2200 | ah->eep_ops->set_txpower(ah, chan, |
608b88cb | 2201 | ath9k_regd_get_ctl(regulatory, chan), |
8fbff4b8 VT |
2202 | channel->max_antenna_gain * 2, |
2203 | channel->max_power * 2, | |
2204 | min((u32) MAX_RATE_POWER, | |
de40f316 | 2205 | (u32) regulatory->power_limit), test); |
6f255425 | 2206 | } |
7322fd19 | 2207 | EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); |
6f255425 | 2208 | |
cbe61d8a | 2209 | void ath9k_hw_setopmode(struct ath_hw *ah) |
f078f209 | 2210 | { |
2660b81a | 2211 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
f078f209 | 2212 | } |
7322fd19 | 2213 | EXPORT_SYMBOL(ath9k_hw_setopmode); |
f078f209 | 2214 | |
cbe61d8a | 2215 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) |
f078f209 | 2216 | { |
f1dc5600 S |
2217 | REG_WRITE(ah, AR_MCAST_FIL0, filter0); |
2218 | REG_WRITE(ah, AR_MCAST_FIL1, filter1); | |
f078f209 | 2219 | } |
7322fd19 | 2220 | EXPORT_SYMBOL(ath9k_hw_setmcastfilter); |
f078f209 | 2221 | |
f2b2143e | 2222 | void ath9k_hw_write_associd(struct ath_hw *ah) |
f078f209 | 2223 | { |
1510718d LR |
2224 | struct ath_common *common = ath9k_hw_common(ah); |
2225 | ||
2226 | REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); | |
2227 | REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | | |
2228 | ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); | |
f078f209 | 2229 | } |
7322fd19 | 2230 | EXPORT_SYMBOL(ath9k_hw_write_associd); |
f078f209 | 2231 | |
1c0fc65e BP |
2232 | #define ATH9K_MAX_TSF_READ 10 |
2233 | ||
cbe61d8a | 2234 | u64 ath9k_hw_gettsf64(struct ath_hw *ah) |
f078f209 | 2235 | { |
1c0fc65e BP |
2236 | u32 tsf_lower, tsf_upper1, tsf_upper2; |
2237 | int i; | |
2238 | ||
2239 | tsf_upper1 = REG_READ(ah, AR_TSF_U32); | |
2240 | for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { | |
2241 | tsf_lower = REG_READ(ah, AR_TSF_L32); | |
2242 | tsf_upper2 = REG_READ(ah, AR_TSF_U32); | |
2243 | if (tsf_upper2 == tsf_upper1) | |
2244 | break; | |
2245 | tsf_upper1 = tsf_upper2; | |
2246 | } | |
f078f209 | 2247 | |
1c0fc65e | 2248 | WARN_ON( i == ATH9K_MAX_TSF_READ ); |
f078f209 | 2249 | |
1c0fc65e | 2250 | return (((u64)tsf_upper1 << 32) | tsf_lower); |
f1dc5600 | 2251 | } |
7322fd19 | 2252 | EXPORT_SYMBOL(ath9k_hw_gettsf64); |
f078f209 | 2253 | |
cbe61d8a | 2254 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) |
27abe060 | 2255 | { |
27abe060 | 2256 | REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); |
b9a16197 | 2257 | REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); |
27abe060 | 2258 | } |
7322fd19 | 2259 | EXPORT_SYMBOL(ath9k_hw_settsf64); |
27abe060 | 2260 | |
cbe61d8a | 2261 | void ath9k_hw_reset_tsf(struct ath_hw *ah) |
f1dc5600 | 2262 | { |
f9b604f6 GJ |
2263 | if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, |
2264 | AH_TSF_WRITE_TIMEOUT)) | |
226afe68 JP |
2265 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, |
2266 | "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); | |
f9b604f6 | 2267 | |
f1dc5600 S |
2268 | REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); |
2269 | } | |
7322fd19 | 2270 | EXPORT_SYMBOL(ath9k_hw_reset_tsf); |
f078f209 | 2271 | |
54e4cec6 | 2272 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) |
f1dc5600 | 2273 | { |
f1dc5600 | 2274 | if (setting) |
2660b81a | 2275 | ah->misc_mode |= AR_PCU_TX_ADD_TSF; |
f1dc5600 | 2276 | else |
2660b81a | 2277 | ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; |
f1dc5600 | 2278 | } |
7322fd19 | 2279 | EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); |
f078f209 | 2280 | |
25c56eec | 2281 | void ath9k_hw_set11nmac2040(struct ath_hw *ah) |
f1dc5600 | 2282 | { |
25c56eec | 2283 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
f1dc5600 S |
2284 | u32 macmode; |
2285 | ||
25c56eec | 2286 | if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) |
f1dc5600 S |
2287 | macmode = AR_2040_JOINED_RX_CLEAR; |
2288 | else | |
2289 | macmode = 0; | |
f078f209 | 2290 | |
f1dc5600 | 2291 | REG_WRITE(ah, AR_2040_MODE, macmode); |
f078f209 | 2292 | } |
ff155a45 VT |
2293 | |
2294 | /* HW Generic timers configuration */ | |
2295 | ||
2296 | static const struct ath_gen_timer_configuration gen_tmr_configuration[] = | |
2297 | { | |
2298 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2299 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2300 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2301 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2302 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2303 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2304 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2305 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2306 | {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, | |
2307 | {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, | |
2308 | AR_NDP2_TIMER_MODE, 0x0002}, | |
2309 | {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, | |
2310 | AR_NDP2_TIMER_MODE, 0x0004}, | |
2311 | {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, | |
2312 | AR_NDP2_TIMER_MODE, 0x0008}, | |
2313 | {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, | |
2314 | AR_NDP2_TIMER_MODE, 0x0010}, | |
2315 | {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, | |
2316 | AR_NDP2_TIMER_MODE, 0x0020}, | |
2317 | {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, | |
2318 | AR_NDP2_TIMER_MODE, 0x0040}, | |
2319 | {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, | |
2320 | AR_NDP2_TIMER_MODE, 0x0080} | |
2321 | }; | |
2322 | ||
2323 | /* HW generic timer primitives */ | |
2324 | ||
2325 | /* compute and clear index of rightmost 1 */ | |
2326 | static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) | |
2327 | { | |
2328 | u32 b; | |
2329 | ||
2330 | b = *mask; | |
2331 | b &= (0-b); | |
2332 | *mask &= ~b; | |
2333 | b *= debruijn32; | |
2334 | b >>= 27; | |
2335 | ||
2336 | return timer_table->gen_timer_index[b]; | |
2337 | } | |
2338 | ||
744bcb42 | 2339 | static u32 ath9k_hw_gettsf32(struct ath_hw *ah) |
ff155a45 VT |
2340 | { |
2341 | return REG_READ(ah, AR_TSF_L32); | |
2342 | } | |
2343 | ||
2344 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, | |
2345 | void (*trigger)(void *), | |
2346 | void (*overflow)(void *), | |
2347 | void *arg, | |
2348 | u8 timer_index) | |
2349 | { | |
2350 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
2351 | struct ath_gen_timer *timer; | |
2352 | ||
2353 | timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); | |
2354 | ||
2355 | if (timer == NULL) { | |
3800276a JP |
2356 | ath_err(ath9k_hw_common(ah), |
2357 | "Failed to allocate memory for hw timer[%d]\n", | |
2358 | timer_index); | |
ff155a45 VT |
2359 | return NULL; |
2360 | } | |
2361 | ||
2362 | /* allocate a hardware generic timer slot */ | |
2363 | timer_table->timers[timer_index] = timer; | |
2364 | timer->index = timer_index; | |
2365 | timer->trigger = trigger; | |
2366 | timer->overflow = overflow; | |
2367 | timer->arg = arg; | |
2368 | ||
2369 | return timer; | |
2370 | } | |
7322fd19 | 2371 | EXPORT_SYMBOL(ath_gen_timer_alloc); |
ff155a45 | 2372 | |
cd9bf689 LR |
2373 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
2374 | struct ath_gen_timer *timer, | |
2375 | u32 timer_next, | |
2376 | u32 timer_period) | |
ff155a45 VT |
2377 | { |
2378 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
2379 | u32 tsf; | |
2380 | ||
2381 | BUG_ON(!timer_period); | |
2382 | ||
2383 | set_bit(timer->index, &timer_table->timer_mask.timer_bits); | |
2384 | ||
2385 | tsf = ath9k_hw_gettsf32(ah); | |
2386 | ||
226afe68 JP |
2387 | ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER, |
2388 | "current tsf %x period %x timer_next %x\n", | |
2389 | tsf, timer_period, timer_next); | |
ff155a45 VT |
2390 | |
2391 | /* | |
2392 | * Pull timer_next forward if the current TSF already passed it | |
2393 | * because of software latency | |
2394 | */ | |
2395 | if (timer_next < tsf) | |
2396 | timer_next = tsf + timer_period; | |
2397 | ||
2398 | /* | |
2399 | * Program generic timer registers | |
2400 | */ | |
2401 | REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, | |
2402 | timer_next); | |
2403 | REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, | |
2404 | timer_period); | |
2405 | REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, | |
2406 | gen_tmr_configuration[timer->index].mode_mask); | |
2407 | ||
2408 | /* Enable both trigger and thresh interrupt masks */ | |
2409 | REG_SET_BIT(ah, AR_IMR_S5, | |
2410 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | | |
2411 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); | |
ff155a45 | 2412 | } |
7322fd19 | 2413 | EXPORT_SYMBOL(ath9k_hw_gen_timer_start); |
ff155a45 | 2414 | |
cd9bf689 | 2415 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) |
ff155a45 VT |
2416 | { |
2417 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
2418 | ||
2419 | if ((timer->index < AR_FIRST_NDP_TIMER) || | |
2420 | (timer->index >= ATH_MAX_GEN_TIMER)) { | |
2421 | return; | |
2422 | } | |
2423 | ||
2424 | /* Clear generic timer enable bits. */ | |
2425 | REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, | |
2426 | gen_tmr_configuration[timer->index].mode_mask); | |
2427 | ||
2428 | /* Disable both trigger and thresh interrupt masks */ | |
2429 | REG_CLR_BIT(ah, AR_IMR_S5, | |
2430 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | | |
2431 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); | |
2432 | ||
2433 | clear_bit(timer->index, &timer_table->timer_mask.timer_bits); | |
ff155a45 | 2434 | } |
7322fd19 | 2435 | EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); |
ff155a45 VT |
2436 | |
2437 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) | |
2438 | { | |
2439 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
2440 | ||
2441 | /* free the hardware generic timer slot */ | |
2442 | timer_table->timers[timer->index] = NULL; | |
2443 | kfree(timer); | |
2444 | } | |
7322fd19 | 2445 | EXPORT_SYMBOL(ath_gen_timer_free); |
ff155a45 VT |
2446 | |
2447 | /* | |
2448 | * Generic Timer Interrupts handling | |
2449 | */ | |
2450 | void ath_gen_timer_isr(struct ath_hw *ah) | |
2451 | { | |
2452 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
2453 | struct ath_gen_timer *timer; | |
c46917bb | 2454 | struct ath_common *common = ath9k_hw_common(ah); |
ff155a45 VT |
2455 | u32 trigger_mask, thresh_mask, index; |
2456 | ||
2457 | /* get hardware generic timer interrupt status */ | |
2458 | trigger_mask = ah->intr_gen_timer_trigger; | |
2459 | thresh_mask = ah->intr_gen_timer_thresh; | |
2460 | trigger_mask &= timer_table->timer_mask.val; | |
2461 | thresh_mask &= timer_table->timer_mask.val; | |
2462 | ||
2463 | trigger_mask &= ~thresh_mask; | |
2464 | ||
2465 | while (thresh_mask) { | |
2466 | index = rightmost_index(timer_table, &thresh_mask); | |
2467 | timer = timer_table->timers[index]; | |
2468 | BUG_ON(!timer); | |
226afe68 JP |
2469 | ath_dbg(common, ATH_DBG_HWTIMER, |
2470 | "TSF overflow for Gen timer %d\n", index); | |
ff155a45 VT |
2471 | timer->overflow(timer->arg); |
2472 | } | |
2473 | ||
2474 | while (trigger_mask) { | |
2475 | index = rightmost_index(timer_table, &trigger_mask); | |
2476 | timer = timer_table->timers[index]; | |
2477 | BUG_ON(!timer); | |
226afe68 JP |
2478 | ath_dbg(common, ATH_DBG_HWTIMER, |
2479 | "Gen timer[%d] trigger\n", index); | |
ff155a45 VT |
2480 | timer->trigger(timer->arg); |
2481 | } | |
2482 | } | |
7322fd19 | 2483 | EXPORT_SYMBOL(ath_gen_timer_isr); |
2da4f01a | 2484 | |
05020d23 S |
2485 | /********/ |
2486 | /* HTC */ | |
2487 | /********/ | |
2488 | ||
2489 | void ath9k_hw_htc_resetinit(struct ath_hw *ah) | |
2490 | { | |
2491 | ah->htc_reset_init = true; | |
2492 | } | |
2493 | EXPORT_SYMBOL(ath9k_hw_htc_resetinit); | |
2494 | ||
2da4f01a LR |
2495 | static struct { |
2496 | u32 version; | |
2497 | const char * name; | |
2498 | } ath_mac_bb_names[] = { | |
2499 | /* Devices with external radios */ | |
2500 | { AR_SREV_VERSION_5416_PCI, "5416" }, | |
2501 | { AR_SREV_VERSION_5416_PCIE, "5418" }, | |
2502 | { AR_SREV_VERSION_9100, "9100" }, | |
2503 | { AR_SREV_VERSION_9160, "9160" }, | |
2504 | /* Single-chip solutions */ | |
2505 | { AR_SREV_VERSION_9280, "9280" }, | |
2506 | { AR_SREV_VERSION_9285, "9285" }, | |
11158472 LR |
2507 | { AR_SREV_VERSION_9287, "9287" }, |
2508 | { AR_SREV_VERSION_9271, "9271" }, | |
ec83903e | 2509 | { AR_SREV_VERSION_9300, "9300" }, |
2da4f01a LR |
2510 | }; |
2511 | ||
2512 | /* For devices with external radios */ | |
2513 | static struct { | |
2514 | u16 version; | |
2515 | const char * name; | |
2516 | } ath_rf_names[] = { | |
2517 | { 0, "5133" }, | |
2518 | { AR_RAD5133_SREV_MAJOR, "5133" }, | |
2519 | { AR_RAD5122_SREV_MAJOR, "5122" }, | |
2520 | { AR_RAD2133_SREV_MAJOR, "2133" }, | |
2521 | { AR_RAD2122_SREV_MAJOR, "2122" } | |
2522 | }; | |
2523 | ||
2524 | /* | |
2525 | * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. | |
2526 | */ | |
f934c4d9 | 2527 | static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) |
2da4f01a LR |
2528 | { |
2529 | int i; | |
2530 | ||
2531 | for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { | |
2532 | if (ath_mac_bb_names[i].version == mac_bb_version) { | |
2533 | return ath_mac_bb_names[i].name; | |
2534 | } | |
2535 | } | |
2536 | ||
2537 | return "????"; | |
2538 | } | |
2da4f01a LR |
2539 | |
2540 | /* | |
2541 | * Return the RF name. "????" is returned if the RF is unknown. | |
2542 | * Used for devices with external radios. | |
2543 | */ | |
f934c4d9 | 2544 | static const char *ath9k_hw_rf_name(u16 rf_version) |
2da4f01a LR |
2545 | { |
2546 | int i; | |
2547 | ||
2548 | for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { | |
2549 | if (ath_rf_names[i].version == rf_version) { | |
2550 | return ath_rf_names[i].name; | |
2551 | } | |
2552 | } | |
2553 | ||
2554 | return "????"; | |
2555 | } | |
f934c4d9 LR |
2556 | |
2557 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) | |
2558 | { | |
2559 | int used; | |
2560 | ||
2561 | /* chipsets >= AR9280 are single-chip */ | |
7a37081e | 2562 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
f934c4d9 LR |
2563 | used = snprintf(hw_name, len, |
2564 | "Atheros AR%s Rev:%x", | |
2565 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), | |
2566 | ah->hw_version.macRev); | |
2567 | } | |
2568 | else { | |
2569 | used = snprintf(hw_name, len, | |
2570 | "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", | |
2571 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), | |
2572 | ah->hw_version.macRev, | |
2573 | ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & | |
2574 | AR_RADIO_SREV_MAJOR)), | |
2575 | ah->hw_version.phyRev); | |
2576 | } | |
2577 | ||
2578 | hw_name[used] = '\0'; | |
2579 | } | |
2580 | EXPORT_SYMBOL(ath9k_hw_name); |