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ath9k: Fix regulatory compliance
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
09d8e315 20#include <linux/time.h>
c67ce339 21#include <linux/bitops.h>
f078f209
LR		 22#include <asm/unaligned.h>
23
af03abec 24#include "hw.h"
d70357d5 25#include "hw-ops.h"
cfe8cba9 26#include "rc.h"
b622a720 27#include "ar9003_mac.h"
f4701b5a 28#include "ar9003_mci.h"
362cd03f 29#include "ar9003_phy.h"
462e58f2
BG		 30#include "debug.h"
31#include "ath9k.h"
f078f209 32
cbe61d8a 33static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 34
7322fd19
LR		 35MODULE_AUTHOR("Atheros Communications");
36MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
37MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
38MODULE_LICENSE("Dual BSD/GPL");
39
40static int __init ath9k_init(void)
41{
42 return 0;
43}
44module_init(ath9k_init);
45
46static void __exit ath9k_exit(void)
47{
48 return;
49}
50module_exit(ath9k_exit);
51
d70357d5
LR		 52/* Private hardware callbacks */
53
54static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
55{
56 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
57}
58
64773964
LR		 59static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
60 struct ath9k_channel *chan)
61{
62 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
63}
64
991312d8
LR		 65static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
66{
67 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
68 return;
69
70 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
71}
72
e36b27af
LR		 73static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
74{
75 /* You will not have this callback if using the old ANI */
76 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
77 return;
78
79 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
80}
81
f1dc5600
S		 82/********************/
83/* Helper Functions */
84/********************/
f078f209 85
462e58f2
BG		 86#ifdef CONFIG_ATH9K_DEBUGFS
87
88void ath9k_debug_sync_cause(struct ath_common *common, u32 sync_cause)
89{
90 struct ath_softc *sc = common->priv;
91 if (sync_cause)
92 sc->debug.stats.istats.sync_cause_all++;
93 if (sync_cause & AR_INTR_SYNC_RTC_IRQ)
94 sc->debug.stats.istats.sync_rtc_irq++;
95 if (sync_cause & AR_INTR_SYNC_MAC_IRQ)
96 sc->debug.stats.istats.sync_mac_irq++;
97 if (sync_cause & AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS)
98 sc->debug.stats.istats.eeprom_illegal_access++;
99 if (sync_cause & AR_INTR_SYNC_APB_TIMEOUT)
100 sc->debug.stats.istats.apb_timeout++;
101 if (sync_cause & AR_INTR_SYNC_PCI_MODE_CONFLICT)
102 sc->debug.stats.istats.pci_mode_conflict++;
103 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL)
104 sc->debug.stats.istats.host1_fatal++;
105 if (sync_cause & AR_INTR_SYNC_HOST1_PERR)
106 sc->debug.stats.istats.host1_perr++;
107 if (sync_cause & AR_INTR_SYNC_TRCV_FIFO_PERR)
108 sc->debug.stats.istats.trcv_fifo_perr++;
109 if (sync_cause & AR_INTR_SYNC_RADM_CPL_EP)
110 sc->debug.stats.istats.radm_cpl_ep++;
111 if (sync_cause & AR_INTR_SYNC_RADM_CPL_DLLP_ABORT)
112 sc->debug.stats.istats.radm_cpl_dllp_abort++;
113 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TLP_ABORT)
114 sc->debug.stats.istats.radm_cpl_tlp_abort++;
115 if (sync_cause & AR_INTR_SYNC_RADM_CPL_ECRC_ERR)
116 sc->debug.stats.istats.radm_cpl_ecrc_err++;
117 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT)
118 sc->debug.stats.istats.radm_cpl_timeout++;
119 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
120 sc->debug.stats.istats.local_timeout++;
121 if (sync_cause & AR_INTR_SYNC_PM_ACCESS)
122 sc->debug.stats.istats.pm_access++;
123 if (sync_cause & AR_INTR_SYNC_MAC_AWAKE)
124 sc->debug.stats.istats.mac_awake++;
125 if (sync_cause & AR_INTR_SYNC_MAC_ASLEEP)
126 sc->debug.stats.istats.mac_asleep++;
127 if (sync_cause & AR_INTR_SYNC_MAC_SLEEP_ACCESS)
128 sc->debug.stats.istats.mac_sleep_access++;
129}
130#endif
131
132
dfdac8ac 133static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 134{
dfdac8ac 135 struct ath_common *common = ath9k_hw_common(ah);
e4744ec7 136 struct ath9k_channel *chan = ah->curchan;
dfdac8ac 137 unsigned int clockrate;
cbe61d8a 138
087b6ff6
FF		 139 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
140 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
141 clockrate = 117;
e4744ec7 142 else if (!chan) /* should really check for CCK instead */
dfdac8ac 143 clockrate = ATH9K_CLOCK_RATE_CCK;
e4744ec7 144 else if (IS_CHAN_2GHZ(chan))
dfdac8ac
FF		 145 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
146 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
147 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 148 else
dfdac8ac
FF		 149 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
150
beae416b
MN		 151 if (chan) {
152 if (IS_CHAN_HT40(chan))
153 clockrate *= 2;
e4744ec7 154 if (IS_CHAN_HALF_RATE(chan))
906c7205 155 clockrate /= 2;
e4744ec7 156 if (IS_CHAN_QUARTER_RATE(chan))
906c7205
FF		 157 clockrate /= 4;
158 }
159
dfdac8ac 160 common->clockrate = clockrate;
f1dc5600
S		 161}
162
cbe61d8a 163static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 164{
dfdac8ac 165 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 166
dfdac8ac 167 return usecs * common->clockrate;
f1dc5600 168}
f078f209 169
0caa7b14 170bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 171{
172 int i;
173
0caa7b14
S		 174 BUG_ON(timeout < AH_TIME_QUANTUM);
175
176 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 177 if ((REG_READ(ah, reg) & mask) == val)
178 return true;
179
180 udelay(AH_TIME_QUANTUM);
181 }
04bd4638 182
d2182b69 183 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 184 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
185 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 186
f1dc5600 187 return false;
f078f209 188}
7322fd19 189EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 190
7c5adc8d
FF		 191void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
192 int hw_delay)
193{
1a5e6326 194 hw_delay /= 10;
7c5adc8d
FF		 195
196 if (IS_CHAN_HALF_RATE(chan))
197 hw_delay *= 2;
198 else if (IS_CHAN_QUARTER_RATE(chan))
199 hw_delay *= 4;
200
201 udelay(hw_delay + BASE_ACTIVATE_DELAY);
202}
203
0166b4be 204void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
a9b6b256
FF		 205 int column, unsigned int *writecnt)
206{
207 int r;
208
209 ENABLE_REGWRITE_BUFFER(ah);
210 for (r = 0; r < array->ia_rows; r++) {
211 REG_WRITE(ah, INI_RA(array, r, 0),
212 INI_RA(array, r, column));
213 DO_DELAY(*writecnt);
214 }
215 REGWRITE_BUFFER_FLUSH(ah);
216}
217
f078f209
LR		 218u32 ath9k_hw_reverse_bits(u32 val, u32 n)
219{
220 u32 retval;
221 int i;
222
223 for (i = 0, retval = 0; i < n; i++) {
224 retval = (retval << 1) | (val & 1);
225 val >>= 1;
226 }
227 return retval;
228}
229
cbe61d8a 230u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 231 u8 phy, int kbps,
f1dc5600
S		 232 u32 frameLen, u16 rateix,
233 bool shortPreamble)
f078f209 234{
f1dc5600 235 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 236
f1dc5600
S		 237 if (kbps == 0)
238 return 0;
f078f209 239
545750d3 240 switch (phy) {
46d14a58 241 case WLAN_RC_PHY_CCK:
f1dc5600 242 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 243 if (shortPreamble)
f1dc5600
S		 244 phyTime >>= 1;
245 numBits = frameLen << 3;
246 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
247 break;
46d14a58 248 case WLAN_RC_PHY_OFDM:
2660b81a 249 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 250 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
251 numBits = OFDM_PLCP_BITS + (frameLen << 3);
252 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
253 txTime = OFDM_SIFS_TIME_QUARTER
254 + OFDM_PREAMBLE_TIME_QUARTER
255 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 256 } else if (ah->curchan &&
257 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 258 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
259 numBits = OFDM_PLCP_BITS + (frameLen << 3);
260 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
261 txTime = OFDM_SIFS_TIME_HALF +
262 OFDM_PREAMBLE_TIME_HALF
263 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
264 } else {
265 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
266 numBits = OFDM_PLCP_BITS + (frameLen << 3);
267 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
268 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
269 + (numSymbols * OFDM_SYMBOL_TIME);
270 }
271 break;
272 default:
3800276a
JP		 273 ath_err(ath9k_hw_common(ah),
274 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 275 txTime = 0;
276 break;
277 }
f078f209 278
f1dc5600
S		 279 return txTime;
280}
7322fd19 281EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 282
cbe61d8a 283void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 284 struct ath9k_channel *chan,
285 struct chan_centers *centers)
f078f209 286{
f1dc5600 287 int8_t extoff;
f078f209 288
f1dc5600
S		 289 if (!IS_CHAN_HT40(chan)) {
290 centers->ctl_center = centers->ext_center =
291 centers->synth_center = chan->channel;
292 return;
f078f209 293 }
f078f209 294
8896934c 295 if (IS_CHAN_HT40PLUS(chan)) {
f1dc5600
S		 296 centers->synth_center =
297 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
298 extoff = 1;
299 } else {
300 centers->synth_center =
301 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
302 extoff = -1;
303 }
f078f209 304
f1dc5600
S		 305 centers->ctl_center =
306 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 307 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 308 centers->ext_center =
6420014c 309 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 310}
311
f1dc5600
S		 312/******************/
313/* Chip Revisions */
314/******************/
315
cbe61d8a 316static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 317{
f1dc5600 318 u32 val;
f078f209 319
ecb1d385
VT		 320 switch (ah->hw_version.devid) {
321 case AR5416_AR9100_DEVID:
322 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
323 break;
3762561a
GJ		 324 case AR9300_DEVID_AR9330:
325 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
326 if (ah->get_mac_revision) {
327 ah->hw_version.macRev = ah->get_mac_revision();
328 } else {
329 val = REG_READ(ah, AR_SREV);
330 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
331 }
332 return;
ecb1d385
VT		 333 case AR9300_DEVID_AR9340:
334 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
335 val = REG_READ(ah, AR_SREV);
336 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
337 return;
813831dc
GJ		 338 case AR9300_DEVID_QCA955X:
339 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
340 return;
ecb1d385
VT		 341 }
342
f1dc5600 343 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 344
f1dc5600
S		 345 if (val == 0xFF) {
346 val = REG_READ(ah, AR_SREV);
d535a42a
S		 347 ah->hw_version.macVersion =
348 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
349 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 350
77fac465 351 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
76ed94be
MSS		 352 ah->is_pciexpress = true;
353 else
354 ah->is_pciexpress = (val &
355 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 356 } else {
357 if (!AR_SREV_9100(ah))
d535a42a 358 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 359
d535a42a 360 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 361
d535a42a 362 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 363 ah->is_pciexpress = true;
f1dc5600 364 }
f078f209
LR		 365}
366
f1dc5600
S		 367/************************************/
368/* HW Attach, Detach, Init Routines */
369/************************************/
370
cbe61d8a 371static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 372{
040b74f7 373 if (!AR_SREV_5416(ah))
f1dc5600 374 return;
f078f209 375
f1dc5600
S		 376 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
377 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
378 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
379 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
380 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
381 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
382 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
383 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
384 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 385
f1dc5600 386 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 387}
388
1f3f0618 389/* This should work for all families including legacy */
cbe61d8a 390static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 391{
c46917bb 392 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 393 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 394 u32 regHold[2];
07b2fa5a
JP		 395 static const u32 patternData[4] = {
396 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
397 };
1f3f0618 398 int i, j, loop_max;
f078f209 399
1f3f0618
SB		 400 if (!AR_SREV_9300_20_OR_LATER(ah)) {
401 loop_max = 2;
402 regAddr[1] = AR_PHY_BASE + (8 << 2);
403 } else
404 loop_max = 1;
405
406 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 407 u32 addr = regAddr[i];
408 u32 wrData, rdData;
f078f209 409
f1dc5600
S		 410 regHold[i] = REG_READ(ah, addr);
411 for (j = 0; j < 0x100; j++) {
412 wrData = (j << 16) | j;
413 REG_WRITE(ah, addr, wrData);
414 rdData = REG_READ(ah, addr);
415 if (rdData != wrData) {
3800276a
JP		 416 ath_err(common,
417 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
418 addr, wrData, rdData);
f1dc5600
S		 419 return false;
420 }
421 }
422 for (j = 0; j < 4; j++) {
423 wrData = patternData[j];
424 REG_WRITE(ah, addr, wrData);
425 rdData = REG_READ(ah, addr);
426 if (wrData != rdData) {
3800276a
JP		 427 ath_err(common,
428 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
429 addr, wrData, rdData);
f1dc5600
S		 430 return false;
431 }
f078f209 432 }
f1dc5600 433 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 434 }
f1dc5600 435 udelay(100);
cbe61d8a 436
f078f209
LR		 437 return true;
438}
439
b8b0f377 440static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600 441{
689e756f
FF		 442 ah->config.dma_beacon_response_time = 1;
443 ah->config.sw_beacon_response_time = 6;
2660b81a
S		 444 ah->config.ack_6mb = 0x0;
445 ah->config.cwm_ignore_extcca = 0;
2660b81a 446 ah->config.analog_shiftreg = 1;
f078f209 447
0ce024cb 448 ah->config.rx_intr_mitigation = true;
6158425b
LR		 449
450 /*
451 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
452 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
453 * This means we use it for all AR5416 devices, and the few
454 * minor PCI AR9280 devices out there.
455 *
456 * Serialization is required because these devices do not handle
457 * well the case of two concurrent reads/writes due to the latency
458 * involved. During one read/write another read/write can be issued
459 * on another CPU while the previous read/write may still be working
460 * on our hardware, if we hit this case the hardware poops in a loop.
461 * We prevent this by serializing reads and writes.
462 *
463 * This issue is not present on PCI-Express devices or pre-AR5416
464 * devices (legacy, 802.11abg).
465 */
466 if (num_possible_cpus() > 1)
2d6a5e95 467 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 468}
469
50aca25b 470static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 471{
608b88cb
LR		 472 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
473
474 regulatory->country_code = CTRY_DEFAULT;
475 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 476
d535a42a 477 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 478 ah->hw_version.subvendorid = 0;
f078f209 479
16f2411f
FF		 480 ah->sta_id1_defaults =
481 AR_STA_ID1_CRPT_MIC_ENABLE |
482 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 483 if (AR_SREV_9100(ah))
484 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
e3f2acc7 485 ah->slottime = ATH9K_SLOT_TIME_9;
2660b81a 486 ah->globaltxtimeout = (u32) -1;
cbdec975 487 ah->power_mode = ATH9K_PM_UNDEFINED;
8efa7a81 488 ah->htc_reset_init = true;
f078f209
LR		 489}
490
cbe61d8a 491static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 492{
1510718d 493 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 494 u32 sum;
495 int i;
496 u16 eeval;
07b2fa5a 497 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 498
499 sum = 0;
500 for (i = 0; i < 3; i++) {
49101676 501 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 502 sum += eeval;
1510718d
LR		 503 common->macaddr[2 * i] = eeval >> 8;
504 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 505 }
d8baa939 506 if (sum == 0 || sum == 0xffff * 3)
f078f209 507 return -EADDRNOTAVAIL;
f078f209
LR		 508
509 return 0;
510}
511
f637cfd6 512static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 513{
6cae913d 514 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 515 int ecode;
f078f209 516
6cae913d 517 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 518 if (!ath9k_hw_chip_test(ah))
519 return -ENODEV;
520 }
f078f209 521
ebd5a14a
LR		 522 if (!AR_SREV_9300_20_OR_LATER(ah)) {
523 ecode = ar9002_hw_rf_claim(ah);
524 if (ecode != 0)
525 return ecode;
526 }
f078f209 527
f637cfd6 528 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 529 if (ecode != 0)
530 return ecode;
7d01b221 531
d2182b69 532 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 533 ah->eep_ops->get_eeprom_ver(ah),
534 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 535
e323300d 536 ath9k_hw_ani_init(ah);
f078f209 537
d3b371cb
SM		 538 /*
539 * EEPROM needs to be initialized before we do this.
540 * This is required for regulatory compliance.
541 */
0c7c2bb4 542 if (AR_SREV_9300_20_OR_LATER(ah)) {
d3b371cb
SM		 543 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
544 if ((regdmn & 0xF0) == CTL_FCC) {
0c7c2bb4
SM		 545 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
546 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
d3b371cb
SM		 547 }
548 }
549
f078f209
LR		 550 return 0;
551}
552
c1b976d2 553static int ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 554{
c1b976d2
FF		 555 if (!AR_SREV_9300_20_OR_LATER(ah))
556 return ar9002_hw_attach_ops(ah);
557
558 ar9003_hw_attach_ops(ah);
559 return 0;
aa4058ae
LR		 560}
561
d70357d5
LR		 562/* Called for all hardware families */
563static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 564{
c46917bb 565 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 566 int r = 0;
aa4058ae 567
ac45c12d
SB		 568 ath9k_hw_read_revisions(ah);
569
0a8d7cb0
SB		 570 /*
571 * Read back AR_WA into a permanent copy and set bits 14 and 17.
572 * We need to do this to avoid RMW of this register. We cannot
573 * read the reg when chip is asleep.
574 */
27251e00
SM		 575 if (AR_SREV_9300_20_OR_LATER(ah)) {
576 ah->WARegVal = REG_READ(ah, AR_WA);
577 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
578 AR_WA_ASPM_TIMER_BASED_DISABLE);
579 }
0a8d7cb0 580
aa4058ae 581 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 582 ath_err(common, "Couldn't reset chip\n");
95fafca2 583 return -EIO;
aa4058ae
LR		 584 }
585
a4a2954f
SM		 586 if (AR_SREV_9565(ah)) {
587 ah->WARegVal |= AR_WA_BIT22;
588 REG_WRITE(ah, AR_WA, ah->WARegVal);
589 }
590
bab1f62e
LR		 591 ath9k_hw_init_defaults(ah);
592 ath9k_hw_init_config(ah);
593
c1b976d2
FF		 594 r = ath9k_hw_attach_ops(ah);
595 if (r)
596 return r;
d70357d5 597
9ecdef4b 598 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 599 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 600 return -EIO;
aa4058ae
LR		 601 }
602
f3eef645 603 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
aa4058ae 604 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
7508b657 605 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
4c85ab11 606 !ah->is_pciexpress)) {
aa4058ae
LR		 607 ah->config.serialize_regmode =
608 SER_REG_MODE_ON;
609 } else {
610 ah->config.serialize_regmode =
611 SER_REG_MODE_OFF;
612 }
613 }
614
d2182b69 615 ath_dbg(common, RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 616 ah->config.serialize_regmode);
617
f4709fdf
LR		 618 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
619 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
620 else
621 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
622
6da5a720
FF		 623 switch (ah->hw_version.macVersion) {
624 case AR_SREV_VERSION_5416_PCI:
625 case AR_SREV_VERSION_5416_PCIE:
626 case AR_SREV_VERSION_9160:
627 case AR_SREV_VERSION_9100:
628 case AR_SREV_VERSION_9280:
629 case AR_SREV_VERSION_9285:
630 case AR_SREV_VERSION_9287:
631 case AR_SREV_VERSION_9271:
632 case AR_SREV_VERSION_9300:
2c8e5937 633 case AR_SREV_VERSION_9330:
6da5a720 634 case AR_SREV_VERSION_9485:
bca04689 635 case AR_SREV_VERSION_9340:
423e38e8 636 case AR_SREV_VERSION_9462:
2b943a33 637 case AR_SREV_VERSION_9550:
77fac465 638 case AR_SREV_VERSION_9565:
6da5a720
FF		 639 break;
640 default:
3800276a
JP		 641 ath_err(common,
642 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
643 ah->hw_version.macVersion, ah->hw_version.macRev);
95fafca2 644 return -EOPNOTSUPP;
aa4058ae
LR		 645 }
646
2c8e5937 647 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
c95b584b 648 AR_SREV_9330(ah) || AR_SREV_9550(ah))
d7e7d229
LR		 649 ah->is_pciexpress = false;
650
aa4058ae 651 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 652 ath9k_hw_init_cal_settings(ah);
653
654 ah->ani_function = ATH9K_ANI_ALL;
e36b27af
LR		 655 if (!AR_SREV_9300_20_OR_LATER(ah))
656 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
aa4058ae 657
69ce674b 658 if (!ah->is_pciexpress)
aa4058ae
LR		 659 ath9k_hw_disablepcie(ah);
660
f637cfd6 661 r = ath9k_hw_post_init(ah);
aa4058ae 662 if (r)
95fafca2 663 return r;
aa4058ae
LR		 664
665 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 666 r = ath9k_hw_fill_cap_info(ah);
667 if (r)
668 return r;
669
4f3acf81
LR		 670 r = ath9k_hw_init_macaddr(ah);
671 if (r) {
3800276a 672 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 673 return r;
f078f209
LR		 674 }
675
d7e7d229 676 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 677 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 678 else
2660b81a 679 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 680
88e641df
GJ		 681 if (AR_SREV_9330(ah))
682 ah->bb_watchdog_timeout_ms = 85;
683 else
684 ah->bb_watchdog_timeout_ms = 25;
f078f209 685
211f5859
LR		 686 common->state = ATH_HW_INITIALIZED;
687
4f3acf81 688 return 0;
f078f209
LR		 689}
690
d70357d5 691int ath9k_hw_init(struct ath_hw *ah)
f078f209 692{
d70357d5
LR		 693 int ret;
694 struct ath_common *common = ath9k_hw_common(ah);
f078f209 695
77fac465 696 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
d70357d5
LR		 697 switch (ah->hw_version.devid) {
698 case AR5416_DEVID_PCI:
699 case AR5416_DEVID_PCIE:
700 case AR5416_AR9100_DEVID:
701 case AR9160_DEVID_PCI:
702 case AR9280_DEVID_PCI:
703 case AR9280_DEVID_PCIE:
704 case AR9285_DEVID_PCIE:
db3cc53a
SB		 705 case AR9287_DEVID_PCI:
706 case AR9287_DEVID_PCIE:
d70357d5 707 case AR2427_DEVID_PCIE:
db3cc53a 708 case AR9300_DEVID_PCIE:
3050c914 709 case AR9300_DEVID_AR9485_PCIE:
999a7a88 710 case AR9300_DEVID_AR9330:
bca04689 711 case AR9300_DEVID_AR9340:
2b943a33 712 case AR9300_DEVID_QCA955X:
5a63ef0f 713 case AR9300_DEVID_AR9580:
423e38e8 714 case AR9300_DEVID_AR9462:
d4e5979c 715 case AR9485_DEVID_AR1111:
77fac465 716 case AR9300_DEVID_AR9565:
d70357d5
LR		 717 break;
718 default:
719 if (common->bus_ops->ath_bus_type == ATH_USB)
720 break;
3800276a
JP		 721 ath_err(common, "Hardware device ID 0x%04x not supported\n",
722 ah->hw_version.devid);
d70357d5
LR		 723 return -EOPNOTSUPP;
724 }
f078f209 725
d70357d5
LR		 726 ret = __ath9k_hw_init(ah);
727 if (ret) {
3800276a
JP		 728 ath_err(common,
729 "Unable to initialize hardware; initialization status: %d\n",
730 ret);
d70357d5
LR		 731 return ret;
732 }
f078f209 733
d70357d5 734 return 0;
f078f209 735}
d70357d5 736EXPORT_SYMBOL(ath9k_hw_init);
f078f209 737
cbe61d8a 738static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 739{
7d0d0df0
S		 740 ENABLE_REGWRITE_BUFFER(ah);
741
f1dc5600
S		 742 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
743 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 744
f1dc5600
S		 745 REG_WRITE(ah, AR_QOS_NO_ACK,
746 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
747 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
748 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
749
750 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
751 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
752 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
753 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
754 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 755
756 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 757}
758
b84628eb 759u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 760{
f18e3c6b
MSS		 761 struct ath_common *common = ath9k_hw_common(ah);
762 int i = 0;
763
ca7a4deb
FF		 764 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
765 udelay(100);
766 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 767
f18e3c6b
MSS		 768 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
769
ca7a4deb 770 udelay(100);
b1415819 771
f18e3c6b
MSS		 772 if (WARN_ON_ONCE(i >= 100)) {
773 ath_err(common, "PLL4 meaurement not done\n");
774 break;
775 }
776
777 i++;
778 }
779
ca7a4deb 780 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 781}
782EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
783
cbe61d8a 784static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 785 struct ath9k_channel *chan)
f078f209 786{
d09b17f7
VT		 787 u32 pll;
788
a4a2954f 789 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3dfd7f60
VT		 790 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
791 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
792 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
793 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
794 AR_CH0_DPLL2_KD, 0x40);
795 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
796 AR_CH0_DPLL2_KI, 0x4);
22983c30 797
3dfd7f60
VT		 798 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
799 AR_CH0_BB_DPLL1_REFDIV, 0x5);
800 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
801 AR_CH0_BB_DPLL1_NINI, 0x58);
802 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
803 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 804
805 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 806 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
807 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
808 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 809 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 810 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 811
3dfd7f60 812 /* program BB PLL phase_shift to 0x6 */
22983c30 813 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 814 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
815
816 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
817 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 818 udelay(1000);
a5415d62
GJ		 819 } else if (AR_SREV_9330(ah)) {
820 u32 ddr_dpll2, pll_control2, kd;
821
822 if (ah->is_clk_25mhz) {
823 ddr_dpll2 = 0x18e82f01;
824 pll_control2 = 0xe04a3d;
825 kd = 0x1d;
826 } else {
827 ddr_dpll2 = 0x19e82f01;
828 pll_control2 = 0x886666;
829 kd = 0x3d;
830 }
831
832 /* program DDR PLL ki and kd value */
833 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
834
835 /* program DDR PLL phase_shift */
836 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
837 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
838
839 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
840 udelay(1000);
841
842 /* program refdiv, nint, frac to RTC register */
843 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
844
845 /* program BB PLL kd and ki value */
846 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
847 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
848
849 /* program BB PLL phase_shift */
850 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
851 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
fc05a317 852 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
0b488ac6
VT		 853 u32 regval, pll2_divint, pll2_divfrac, refdiv;
854
855 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
856 udelay(1000);
857
858 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
859 udelay(100);
860
861 if (ah->is_clk_25mhz) {
862 pll2_divint = 0x54;
863 pll2_divfrac = 0x1eb85;
864 refdiv = 3;
865 } else {
fc05a317
GJ		 866 if (AR_SREV_9340(ah)) {
867 pll2_divint = 88;
868 pll2_divfrac = 0;
869 refdiv = 5;
870 } else {
871 pll2_divint = 0x11;
872 pll2_divfrac = 0x26666;
873 refdiv = 1;
874 }
0b488ac6
VT		 875 }
876
877 regval = REG_READ(ah, AR_PHY_PLL_MODE);
878 regval |= (0x1 << 16);
879 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
880 udelay(100);
881
882 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
883 (pll2_divint << 18) | pll2_divfrac);
884 udelay(100);
885
886 regval = REG_READ(ah, AR_PHY_PLL_MODE);
fc05a317
GJ		 887 if (AR_SREV_9340(ah))
888 regval = (regval & 0x80071fff) | (0x1 << 30) |
889 (0x1 << 13) | (0x4 << 26) | (0x18 << 19);
890 else
891 regval = (regval & 0x80071fff) | (0x3 << 30) |
892 (0x1 << 13) | (0x4 << 26) | (0x60 << 19);
0b488ac6
VT		 893 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
894 REG_WRITE(ah, AR_PHY_PLL_MODE,
895 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
896 udelay(1000);
22983c30 897 }
d09b17f7
VT		 898
899 pll = ath9k_hw_compute_pll_control(ah, chan);
8565f8bf
SM		 900 if (AR_SREV_9565(ah))
901 pll |= 0x40000;
d03a66c1 902 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 903
fc05a317
GJ		 904 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
905 AR_SREV_9550(ah))
3dfd7f60
VT		 906 udelay(1000);
907
c75724d1
LR		 908 /* Switch the core clock for ar9271 to 117Mhz */
909 if (AR_SREV_9271(ah)) {
25e2ab17
S		 910 udelay(500);
911 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 912 }
913
f1dc5600
S		 914 udelay(RTC_PLL_SETTLE_DELAY);
915
916 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
0b488ac6 917
fc05a317 918 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
0b488ac6
VT		 919 if (ah->is_clk_25mhz) {
920 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
921 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
922 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
923 } else {
924 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
925 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
926 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
927 }
928 udelay(100);
929 }
f078f209
LR		 930}
931
cbe61d8a 932static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 933 enum nl80211_iftype opmode)
f078f209 934{
79d1d2b8 935 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 936 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 937 AR_IMR_TXURN |
938 AR_IMR_RXERR |
939 AR_IMR_RXORN |
940 AR_IMR_BCNMISC;
f078f209 941
3b8a0577 942 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
79d1d2b8
VT		 943 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
944
66860240
VT		 945 if (AR_SREV_9300_20_OR_LATER(ah)) {
946 imr_reg |= AR_IMR_RXOK_HP;
947 if (ah->config.rx_intr_mitigation)
948 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
949 else
950 imr_reg |= AR_IMR_RXOK_LP;
f078f209 951
66860240
VT		 952 } else {
953 if (ah->config.rx_intr_mitigation)
954 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
955 else
956 imr_reg |= AR_IMR_RXOK;
957 }
f078f209 958
66860240
VT		 959 if (ah->config.tx_intr_mitigation)
960 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
961 else
962 imr_reg |= AR_IMR_TXOK;
f078f209 963
7d0d0df0
S		 964 ENABLE_REGWRITE_BUFFER(ah);
965
152d530d 966 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 967 ah->imrs2_reg |= AR_IMR_S2_GTT;
968 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 969
f1dc5600
S		 970 if (!AR_SREV_9100(ah)) {
971 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 972 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 973 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
974 }
66860240 975
7d0d0df0 976 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 977
66860240
VT		 978 if (AR_SREV_9300_20_OR_LATER(ah)) {
979 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
980 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
981 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
982 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
983 }
f078f209
LR		 984}
985
b6ba41bb
FF		 986static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
987{
988 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
989 val = min(val, (u32) 0xFFFF);
990 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
991}
992
0005baf4 993static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 994{
0005baf4
FF		 995 u32 val = ath9k_hw_mac_to_clks(ah, us);
996 val = min(val, (u32) 0xFFFF);
997 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 998}
999
0005baf4 1000static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 1001{
0005baf4
FF		 1002 u32 val = ath9k_hw_mac_to_clks(ah, us);
1003 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1004 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1005}
1006
1007static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1008{
1009 u32 val = ath9k_hw_mac_to_clks(ah, us);
1010 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1011 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 1012}
f1dc5600 1013
cbe61d8a 1014static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1015{
f078f209 1016 if (tu > 0xFFFF) {
d2182b69
JP		 1017 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1018 tu);
2660b81a 1019 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1020 return false;
1021 } else {
1022 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1023 ah->globaltxtimeout = tu;
f078f209
LR		 1024 return true;
1025 }
1026}
1027
0005baf4 1028void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 1029{
b6ba41bb 1030 struct ath_common *common = ath9k_hw_common(ah);
b6ba41bb 1031 const struct ath9k_channel *chan = ah->curchan;
e115b7ec 1032 int acktimeout, ctstimeout, ack_offset = 0;
e239d859 1033 int slottime;
0005baf4 1034 int sifstime;
b6ba41bb
FF		 1035 int rx_lat = 0, tx_lat = 0, eifs = 0;
1036 u32 reg;
0005baf4 1037
d2182b69 1038 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 1039 ah->misc_mode);
f078f209 1040
b6ba41bb
FF		 1041 if (!chan)
1042 return;
1043
2660b81a 1044 if (ah->misc_mode != 0)
ca7a4deb 1045 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 1046
81a91d57
RM		 1047 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1048 rx_lat = 41;
1049 else
1050 rx_lat = 37;
b6ba41bb
FF		 1051 tx_lat = 54;
1052
e88e4861
FF		 1053 if (IS_CHAN_5GHZ(chan))
1054 sifstime = 16;
1055 else
1056 sifstime = 10;
1057
b6ba41bb
FF		 1058 if (IS_CHAN_HALF_RATE(chan)) {
1059 eifs = 175;
1060 rx_lat *= 2;
1061 tx_lat *= 2;
1062 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1063 tx_lat += 11;
1064
92367fe7 1065 sifstime = 32;
e115b7ec 1066 ack_offset = 16;
b6ba41bb 1067 slottime = 13;
b6ba41bb
FF		 1068 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1069 eifs = 340;
81a91d57 1070 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 1071 tx_lat *= 4;
1072 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1073 tx_lat += 22;
1074
92367fe7 1075 sifstime = 64;
e115b7ec 1076 ack_offset = 32;
b6ba41bb 1077 slottime = 21;
b6ba41bb 1078 } else {
a7be039d
RM		 1079 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1080 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1081 reg = AR_USEC_ASYNC_FIFO;
1082 } else {
1083 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1084 common->clockrate;
1085 reg = REG_READ(ah, AR_USEC);
1086 }
b6ba41bb
FF		 1087 rx_lat = MS(reg, AR_USEC_RX_LAT);
1088 tx_lat = MS(reg, AR_USEC_TX_LAT);
1089
1090 slottime = ah->slottime;
b6ba41bb 1091 }
0005baf4 1092
e239d859 1093 /* As defined by IEEE 802.11-2007 17.3.8.6 */
f77f8234
MK		 1094 slottime += 3 * ah->coverage_class;
1095 acktimeout = slottime + sifstime + ack_offset;
adb5066a 1096 ctstimeout = acktimeout;
42c4568a
FF		 1097
1098 /*
1099 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1100 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1101 * This was initially only meant to work around an issue with delayed
1102 * BA frames in some implementations, but it has been found to fix ACK
1103 * timeout issues in other cases as well.
1104 */
e4744ec7 1105 if (IS_CHAN_2GHZ(chan) &&
e115b7ec 1106 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
42c4568a 1107 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1108 ctstimeout += 48 - sifstime - ah->slottime;
1109 }
1110
b6ba41bb
FF		 1111 ath9k_hw_set_sifs_time(ah, sifstime);
1112 ath9k_hw_setslottime(ah, slottime);
0005baf4 1113 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1114 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1115 if (ah->globaltxtimeout != (u32) -1)
1116 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1117
1118 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1119 REG_RMW(ah, AR_USEC,
1120 (common->clockrate - 1) |
1121 SM(rx_lat, AR_USEC_RX_LAT) |
1122 SM(tx_lat, AR_USEC_TX_LAT),
1123 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1124
f1dc5600 1125}
0005baf4 1126EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1127
285f2dda 1128void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1129{
211f5859
LR		 1130 struct ath_common *common = ath9k_hw_common(ah);
1131
736b3a27 1132 if (common->state < ATH_HW_INITIALIZED)
c1b976d2 1133 return;
211f5859 1134
9ecdef4b 1135 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
f1dc5600 1136}
285f2dda 1137EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1138
f1dc5600
S		 1139/*******/
1140/* INI */
1141/*******/
1142
8fe65368 1143u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1144{
1145 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1146
6b21fd20 1147 if (IS_CHAN_2GHZ(chan))
3a702e49
BC		 1148 ctl |= CTL_11G;
1149 else
1150 ctl |= CTL_11A;
1151
1152 return ctl;
1153}
1154
f1dc5600
S		 1155/****************************************/
1156/* Reset and Channel Switching Routines */
1157/****************************************/
f1dc5600 1158
cbe61d8a 1159static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1160{
57b32227 1161 struct ath_common *common = ath9k_hw_common(ah);
86c157b3 1162 int txbuf_size;
f1dc5600 1163
7d0d0df0
S		 1164 ENABLE_REGWRITE_BUFFER(ah);
1165
d7e7d229
LR		 1166 /*
1167 * set AHB_MODE not to do cacheline prefetches
1168 */
ca7a4deb
FF		 1169 if (!AR_SREV_9300_20_OR_LATER(ah))
1170 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1171
d7e7d229
LR		 1172 /*
1173 * let mac dma reads be in 128 byte chunks
1174 */
ca7a4deb 1175 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1176
7d0d0df0 1177 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1178
d7e7d229
LR		 1179 /*
1180 * Restore TX Trigger Level to its pre-reset value.
1181 * The initial value depends on whether aggregation is enabled, and is
1182 * adjusted whenever underruns are detected.
1183 */
57b32227
FF		 1184 if (!AR_SREV_9300_20_OR_LATER(ah))
1185 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1186
7d0d0df0 1187 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1188
d7e7d229
LR		 1189 /*
1190 * let mac dma writes be in 128 byte chunks
1191 */
ca7a4deb 1192 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1193
d7e7d229
LR		 1194 /*
1195 * Setup receive FIFO threshold to hold off TX activities
1196 */
f1dc5600
S		 1197 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1198
57b32227
FF		 1199 if (AR_SREV_9300_20_OR_LATER(ah)) {
1200 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1201 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1202
1203 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1204 ah->caps.rx_status_len);
1205 }
1206
d7e7d229
LR		 1207 /*
1208 * reduce the number of usable entries in PCU TXBUF to avoid
1209 * wrap around issues.
1210 */
f1dc5600 1211 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1212 /* For AR9285 the number of Fifos are reduced to half.
1213 * So set the usable tx buf size also to half to
1214 * avoid data/delimiter underruns
1215 */
86c157b3
FF		 1216 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1217 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1218 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1219 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1220 } else {
1221 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
f1dc5600 1222 }
744d4025 1223
86c157b3
FF		 1224 if (!AR_SREV_9271(ah))
1225 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1226
7d0d0df0 1227 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1228
744d4025
VT		 1229 if (AR_SREV_9300_20_OR_LATER(ah))
1230 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1231}
1232
cbe61d8a 1233static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1234{
ca7a4deb
FF		 1235 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1236 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1237
f1dc5600 1238 switch (opmode) {
d97809db 1239 case NL80211_IFTYPE_ADHOC:
ca7a4deb 1240 set |= AR_STA_ID1_ADHOC;
f1dc5600 1241 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1242 break;
2664d666 1243 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb
FF		 1244 case NL80211_IFTYPE_AP:
1245 set |= AR_STA_ID1_STA_AP;
1246 /* fall through */
d97809db 1247 case NL80211_IFTYPE_STATION:
ca7a4deb 1248 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1249 break;
5f841b41 1250 default:
ca7a4deb
FF		 1251 if (!ah->is_monitoring)
1252 set = 0;
5f841b41 1253 break;
f1dc5600 1254 }
ca7a4deb 1255 REG_RMW(ah, AR_STA_ID1, set, mask);
f1dc5600
S		 1256}
1257
8fe65368
LR		 1258void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1259 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1260{
1261 u32 coef_exp, coef_man;
1262
1263 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1264 if ((coef_scaled >> coef_exp) & 0x1)
1265 break;
1266
1267 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1268
1269 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1270
1271 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1272 *coef_exponent = coef_exp - 16;
1273}
1274
cbe61d8a 1275static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1276{
1277 u32 rst_flags;
1278 u32 tmpReg;
1279
70768496 1280 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1281 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1282 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1283 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1284 }
1285
7d0d0df0
S		 1286 ENABLE_REGWRITE_BUFFER(ah);
1287
9a658d2b
LR		 1288 if (AR_SREV_9300_20_OR_LATER(ah)) {
1289 REG_WRITE(ah, AR_WA, ah->WARegVal);
1290 udelay(10);
1291 }
1292
f1dc5600
S		 1293 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1294 AR_RTC_FORCE_WAKE_ON_INT);
1295
1296 if (AR_SREV_9100(ah)) {
1297 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1298 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1299 } else {
1300 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
a37a9910
FF		 1301 if (AR_SREV_9340(ah))
1302 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1303 else
1304 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1305 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1306
1307 if (tmpReg) {
42d5bc3f 1308 u32 val;
f1dc5600 1309 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1310
1311 val = AR_RC_HOSTIF;
1312 if (!AR_SREV_9300_20_OR_LATER(ah))
1313 val |= AR_RC_AHB;
1314 REG_WRITE(ah, AR_RC, val);
1315
1316 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1317 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1318
1319 rst_flags = AR_RTC_RC_MAC_WARM;
1320 if (type == ATH9K_RESET_COLD)
1321 rst_flags |= AR_RTC_RC_MAC_COLD;
1322 }
1323
7d95847c
GJ		 1324 if (AR_SREV_9330(ah)) {
1325 int npend = 0;
1326 int i;
1327
1328 /* AR9330 WAR:
1329 * call external reset function to reset WMAC if:
1330 * - doing a cold reset
1331 * - we have pending frames in the TX queues
1332 */
1333
1334 for (i = 0; i < AR_NUM_QCU; i++) {
1335 npend = ath9k_hw_numtxpending(ah, i);
1336 if (npend)
1337 break;
1338 }
1339
1340 if (ah->external_reset &&
1341 (npend || type == ATH9K_RESET_COLD)) {
1342 int reset_err = 0;
1343
d2182b69 1344 ath_dbg(ath9k_hw_common(ah), RESET,
7d95847c
GJ		 1345 "reset MAC via external reset\n");
1346
1347 reset_err = ah->external_reset();
1348 if (reset_err) {
1349 ath_err(ath9k_hw_common(ah),
1350 "External reset failed, err=%d\n",
1351 reset_err);
1352 return false;
1353 }
1354
1355 REG_WRITE(ah, AR_RTC_RESET, 1);
1356 }
1357 }
1358
3863495b 1359 if (ath9k_hw_mci_is_enabled(ah))
506847ad 1360 ar9003_mci_check_gpm_offset(ah);
3863495b 1361
d03a66c1 1362 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1363
1364 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1365
f1dc5600
S		 1366 udelay(50);
1367
d03a66c1 1368 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1369 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1370 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1371 return false;
1372 }
1373
1374 if (!AR_SREV_9100(ah))
1375 REG_WRITE(ah, AR_RC, 0);
1376
f1dc5600
S		 1377 if (AR_SREV_9100(ah))
1378 udelay(50);
1379
1380 return true;
1381}
1382
cbe61d8a 1383static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1384{
7d0d0df0
S		 1385 ENABLE_REGWRITE_BUFFER(ah);
1386
9a658d2b
LR		 1387 if (AR_SREV_9300_20_OR_LATER(ah)) {
1388 REG_WRITE(ah, AR_WA, ah->WARegVal);
1389 udelay(10);
1390 }
1391
f1dc5600
S		 1392 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1393 AR_RTC_FORCE_WAKE_ON_INT);
1394
42d5bc3f 1395 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1396 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1397
d03a66c1 1398 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1399
7d0d0df0 1400 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1401
84e2169b
SB		 1402 if (!AR_SREV_9300_20_OR_LATER(ah))
1403 udelay(2);
1404
1405 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1406 REG_WRITE(ah, AR_RC, 0);
1407
d03a66c1 1408 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1409
1410 if (!ath9k_hw_wait(ah,
1411 AR_RTC_STATUS,
1412 AR_RTC_STATUS_M,
0caa7b14
S		 1413 AR_RTC_STATUS_ON,
1414 AH_WAIT_TIMEOUT)) {
d2182b69 1415 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1416 return false;
f078f209
LR		 1417 }
1418
f1dc5600
S		 1419 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1420}
1421
cbe61d8a 1422static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1423{
7a9233ff 1424 bool ret = false;
2577c6e8 1425
9a658d2b
LR		 1426 if (AR_SREV_9300_20_OR_LATER(ah)) {
1427 REG_WRITE(ah, AR_WA, ah->WARegVal);
1428 udelay(10);
1429 }
1430
f1dc5600
S		 1431 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1432 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1433
ceb26a60
FF		 1434 if (!ah->reset_power_on)
1435 type = ATH9K_RESET_POWER_ON;
1436
f1dc5600
S		 1437 switch (type) {
1438 case ATH9K_RESET_POWER_ON:
7a9233ff 1439 ret = ath9k_hw_set_reset_power_on(ah);
da8fb123 1440 if (ret)
ceb26a60 1441 ah->reset_power_on = true;
7a9233ff 1442 break;
f1dc5600
S		 1443 case ATH9K_RESET_WARM:
1444 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1445 ret = ath9k_hw_set_reset(ah, type);
1446 break;
f1dc5600 1447 default:
7a9233ff 1448 break;
f1dc5600 1449 }
7a9233ff 1450
7a9233ff 1451 return ret;
f078f209
LR		 1452}
1453
cbe61d8a 1454static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1455 struct ath9k_channel *chan)
f078f209 1456{
9c083af8
FF		 1457 int reset_type = ATH9K_RESET_WARM;
1458
1459 if (AR_SREV_9280(ah)) {
1460 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1461 reset_type = ATH9K_RESET_POWER_ON;
1462 else
1463 reset_type = ATH9K_RESET_COLD;
3412f2f0
FF		 1464 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1465 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1466 reset_type = ATH9K_RESET_COLD;
9c083af8
FF		 1467
1468 if (!ath9k_hw_set_reset_reg(ah, reset_type))
f1dc5600 1469 return false;
f078f209 1470
9ecdef4b 1471 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1472 return false;
f078f209 1473
2660b81a 1474 ah->chip_fullsleep = false;
bfc441a4
FF		 1475
1476 if (AR_SREV_9330(ah))
1477 ar9003_hw_internal_regulator_apply(ah);
f1dc5600 1478 ath9k_hw_init_pll(ah, chan);
f078f209 1479
f1dc5600 1480 return true;
f078f209
LR		 1481}
1482
cbe61d8a 1483static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1484 struct ath9k_channel *chan)
f078f209 1485{
c46917bb 1486 struct ath_common *common = ath9k_hw_common(ah);
b840cffe
SM		 1487 struct ath9k_hw_capabilities *pCap = &ah->caps;
1488 bool band_switch = false, mode_diff = false;
70e89a71 1489 u8 ini_reloaded = 0;
8fe65368 1490 u32 qnum;
0a3b7bac 1491 int r;
5f0c04ea 1492
b840cffe 1493 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
af02efb3
FF		 1494 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1495 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1496 mode_diff = !!(flags_diff & ~CHANNEL_HT);
b840cffe 1497 }
f078f209
LR		 1498
1499 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1500 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1501 ath_dbg(common, QUEUE,
226afe68 1502 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1503 return false;
1504 }
1505 }
1506
8fe65368 1507 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1508 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1509 return false;
1510 }
1511
b840cffe 1512 if (band_switch || mode_diff) {
5f0c04ea
RM		 1513 ath9k_hw_mark_phy_inactive(ah);
1514 udelay(5);
1515
5f35c0fa
SM		 1516 if (band_switch)
1517 ath9k_hw_init_pll(ah, chan);
5f0c04ea
RM		 1518
1519 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1520 ath_err(common, "Failed to do fast channel change\n");
1521 return false;
1522 }
1523 }
1524
8fe65368 1525 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1526
8fe65368 1527 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1528 if (r) {
3800276a 1529 ath_err(common, "Failed to set channel\n");
0a3b7bac 1530 return false;
f078f209 1531 }
dfdac8ac 1532 ath9k_hw_set_clockrate(ah);
64ea57d0 1533 ath9k_hw_apply_txpower(ah, chan, false);
f078f209 1534
81c507a8 1535 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1536 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1537
70e89a71
SM		 1538 if (band_switch || ini_reloaded)
1539 ah->eep_ops->set_board_values(ah, chan);
5f0c04ea 1540
70e89a71
SM		 1541 ath9k_hw_init_bb(ah, chan);
1542 ath9k_hw_rfbus_done(ah);
5f0c04ea 1543
70e89a71
SM		 1544 if (band_switch || ini_reloaded) {
1545 ah->ah_flags |= AH_FASTCC;
1546 ath9k_hw_init_cal(ah, chan);
a126ff51 1547 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1548 }
1549
f1dc5600
S		 1550 return true;
1551}
1552
691680b8
FF		 1553static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1554{
1555 u32 gpio_mask = ah->gpio_mask;
1556 int i;
1557
1558 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1559 if (!(gpio_mask & 1))
1560 continue;
1561
1562 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1563 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1564 }
1565}
1566
01e18918
RM		 1567static bool ath9k_hw_check_dcs(u32 dma_dbg, u32 num_dcu_states,
1568 int *hang_state, int *hang_pos)
1569{
1570 static u32 dcu_chain_state[] = {5, 6, 9}; /* DCU chain stuck states */
1571 u32 chain_state, dcs_pos, i;
1572
1573 for (dcs_pos = 0; dcs_pos < num_dcu_states; dcs_pos++) {
1574 chain_state = (dma_dbg >> (5 * dcs_pos)) & 0x1f;
1575 for (i = 0; i < 3; i++) {
1576 if (chain_state == dcu_chain_state[i]) {
1577 *hang_state = chain_state;
1578 *hang_pos = dcs_pos;
1579 return true;
1580 }
1581 }
1582 }
1583 return false;
1584}
1585
1586#define DCU_COMPLETE_STATE 1
1587#define DCU_COMPLETE_STATE_MASK 0x3
1588#define NUM_STATUS_READS 50
1589static bool ath9k_hw_detect_mac_hang(struct ath_hw *ah)
1590{
1591 u32 chain_state, comp_state, dcs_reg = AR_DMADBG_4;
1592 u32 i, hang_pos, hang_state, num_state = 6;
1593
1594 comp_state = REG_READ(ah, AR_DMADBG_6);
1595
1596 if ((comp_state & DCU_COMPLETE_STATE_MASK) != DCU_COMPLETE_STATE) {
1597 ath_dbg(ath9k_hw_common(ah), RESET,
1598 "MAC Hang signature not found at DCU complete\n");
1599 return false;
1600 }
1601
1602 chain_state = REG_READ(ah, dcs_reg);
1603 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1604 goto hang_check_iter;
1605
1606 dcs_reg = AR_DMADBG_5;
1607 num_state = 4;
1608 chain_state = REG_READ(ah, dcs_reg);
1609 if (ath9k_hw_check_dcs(chain_state, num_state, &hang_state, &hang_pos))
1610 goto hang_check_iter;
1611
1612 ath_dbg(ath9k_hw_common(ah), RESET,
1613 "MAC Hang signature 1 not found\n");
1614 return false;
1615
1616hang_check_iter:
1617 ath_dbg(ath9k_hw_common(ah), RESET,
1618 "DCU registers: chain %08x complete %08x Hang: state %d pos %d\n",
1619 chain_state, comp_state, hang_state, hang_pos);
1620
1621 for (i = 0; i < NUM_STATUS_READS; i++) {
1622 chain_state = REG_READ(ah, dcs_reg);
1623 chain_state = (chain_state >> (5 * hang_pos)) & 0x1f;
1624 comp_state = REG_READ(ah, AR_DMADBG_6);
1625
1626 if (((comp_state & DCU_COMPLETE_STATE_MASK) !=
1627 DCU_COMPLETE_STATE) ||
1628 (chain_state != hang_state))
1629 return false;
1630 }
1631
1632 ath_dbg(ath9k_hw_common(ah), RESET, "MAC Hang signature 1 found\n");
1633
1634 return true;
1635}
1636
1e516ca7
SM		 1637void ath9k_hw_check_nav(struct ath_hw *ah)
1638{
1639 struct ath_common *common = ath9k_hw_common(ah);
1640 u32 val;
1641
1642 val = REG_READ(ah, AR_NAV);
1643 if (val != 0xdeadbeef && val > 0x7fff) {
1644 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1645 REG_WRITE(ah, AR_NAV, 0);
1646 }
1647}
1648EXPORT_SYMBOL(ath9k_hw_check_nav);
1649
c9c99e5e 1650bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1651{
c9c99e5e
FF		 1652 int count = 50;
1653 u32 reg;
1654
01e18918
RM		 1655 if (AR_SREV_9300(ah))
1656 return !ath9k_hw_detect_mac_hang(ah);
1657
e17f83ea 1658 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1659 return true;
1660
1661 do {
1662 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1663
c9c99e5e
FF		 1664 if ((reg & 0x7E7FFFEF) == 0x00702400)
1665 continue;
1666
1667 switch (reg & 0x7E000B00) {
1668 case 0x1E000000:
1669 case 0x52000B00:
1670 case 0x18000B00:
1671 continue;
1672 default:
1673 return true;
1674 }
1675 } while (count-- > 0);
3b319aae 1676
c9c99e5e 1677 return false;
3b319aae 1678}
c9c99e5e 1679EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1680
15d2b585
SM		 1681static void ath9k_hw_init_mfp(struct ath_hw *ah)
1682{
1683 /* Setup MFP options for CCMP */
1684 if (AR_SREV_9280_20_OR_LATER(ah)) {
1685 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1686 * frames when constructing CCMP AAD. */
1687 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1688 0xc7ff);
1689 ah->sw_mgmt_crypto = false;
1690 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1691 /* Disable hardware crypto for management frames */
1692 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1693 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1694 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1695 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1696 ah->sw_mgmt_crypto = true;
1697 } else {
1698 ah->sw_mgmt_crypto = true;
1699 }
1700}
1701
1702static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1703 u32 macStaId1, u32 saveDefAntenna)
1704{
1705 struct ath_common *common = ath9k_hw_common(ah);
1706
1707 ENABLE_REGWRITE_BUFFER(ah);
1708
ecbbed32 1709 REG_RMW(ah, AR_STA_ID1, macStaId1
15d2b585
SM		 1710 | AR_STA_ID1_RTS_USE_DEF
1711 | (ah->config.ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
ecbbed32
FF		 1712 | ah->sta_id1_defaults,
1713 ~AR_STA_ID1_SADH_MASK);
15d2b585
SM		 1714 ath_hw_setbssidmask(common);
1715 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1716 ath9k_hw_write_associd(ah);
1717 REG_WRITE(ah, AR_ISR, ~0);
1718 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1719
1720 REGWRITE_BUFFER_FLUSH(ah);
1721
1722 ath9k_hw_set_operating_mode(ah, ah->opmode);
1723}
1724
1725static void ath9k_hw_init_queues(struct ath_hw *ah)
1726{
1727 int i;
1728
1729 ENABLE_REGWRITE_BUFFER(ah);
1730
1731 for (i = 0; i < AR_NUM_DCU; i++)
1732 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1733
1734 REGWRITE_BUFFER_FLUSH(ah);
1735
1736 ah->intr_txqs = 0;
1737 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1738 ath9k_hw_resettxqueue(ah, i);
1739}
1740
1741/*
1742 * For big endian systems turn on swapping for descriptors
1743 */
1744static void ath9k_hw_init_desc(struct ath_hw *ah)
1745{
1746 struct ath_common *common = ath9k_hw_common(ah);
1747
1748 if (AR_SREV_9100(ah)) {
1749 u32 mask;
1750 mask = REG_READ(ah, AR_CFG);
1751 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1752 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1753 mask);
1754 } else {
1755 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1756 REG_WRITE(ah, AR_CFG, mask);
1757 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1758 REG_READ(ah, AR_CFG));
1759 }
1760 } else {
1761 if (common->bus_ops->ath_bus_type == ATH_USB) {
1762 /* Configure AR9271 target WLAN */
1763 if (AR_SREV_9271(ah))
1764 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1765 else
1766 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1767 }
1768#ifdef __BIG_ENDIAN
1769 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1770 AR_SREV_9550(ah))
1771 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1772 else
1773 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1774#endif
1775 }
1776}
1777
caed6579
SM		 1778/*
1779 * Fast channel change:
1780 * (Change synthesizer based on channel freq without resetting chip)
caed6579
SM		 1781 */
1782static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1783{
1784 struct ath_common *common = ath9k_hw_common(ah);
b840cffe 1785 struct ath9k_hw_capabilities *pCap = &ah->caps;
caed6579
SM		 1786 int ret;
1787
1788 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1789 goto fail;
1790
1791 if (ah->chip_fullsleep)
1792 goto fail;
1793
1794 if (!ah->curchan)
1795 goto fail;
1796
1797 if (chan->channel == ah->curchan->channel)
1798 goto fail;
1799
feb7bc99
FF		 1800 if ((ah->curchan->channelFlags | chan->channelFlags) &
1801 (CHANNEL_HALF | CHANNEL_QUARTER))
1802 goto fail;
1803
b840cffe 1804 /*
6b21fd20 1805 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
b840cffe 1806 */
6b21fd20 1807 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
af02efb3 1808 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
6b21fd20 1809 goto fail;
caed6579
SM		 1810
1811 if (!ath9k_hw_check_alive(ah))
1812 goto fail;
1813
1814 /*
1815 * For AR9462, make sure that calibration data for
1816 * re-using are present.
1817 */
8a90555f 1818 if (AR_SREV_9462(ah) && (ah->caldata &&
4b9b42bf
SM		 1819 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1820 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1821 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
caed6579
SM		 1822 goto fail;
1823
1824 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1825 ah->curchan->channel, chan->channel);
1826
1827 ret = ath9k_hw_channel_change(ah, chan);
1828 if (!ret)
1829 goto fail;
1830
5955b2b0 1831 if (ath9k_hw_mci_is_enabled(ah))
1bde95fa 1832 ar9003_mci_2g5g_switch(ah, false);
caed6579 1833
88033318
RM		 1834 ath9k_hw_loadnf(ah, ah->curchan);
1835 ath9k_hw_start_nfcal(ah, true);
1836
caed6579
SM		 1837 if (AR_SREV_9271(ah))
1838 ar9002_hw_load_ani_reg(ah, chan);
1839
1840 return 0;
1841fail:
1842 return -EINVAL;
1843}
1844
cbe61d8a 1845int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 1846 struct ath9k_hw_cal_data *caldata, bool fastcc)
f078f209 1847{
1510718d 1848 struct ath_common *common = ath9k_hw_common(ah);
09d8e315 1849 struct timespec ts;
f078f209 1850 u32 saveLedState;
f078f209
LR		 1851 u32 saveDefAntenna;
1852 u32 macStaId1;
46fe782c 1853 u64 tsf = 0;
09d8e315 1854 s64 usec = 0;
15d2b585 1855 int r;
caed6579 1856 bool start_mci_reset = false;
63d32967
MSS		 1857 bool save_fullsleep = ah->chip_fullsleep;
1858
5955b2b0 1859 if (ath9k_hw_mci_is_enabled(ah)) {
528e5d36
SM		 1860 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1861 if (start_mci_reset)
1862 return 0;
63d32967
MSS		 1863 }
1864
9ecdef4b 1865 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1866 return -EIO;
f078f209 1867
caed6579
SM		 1868 if (ah->curchan && !ah->chip_fullsleep)
1869 ath9k_hw_getnf(ah, ah->curchan);
f078f209 1870
20bd2a09 1871 ah->caldata = caldata;
fcb9a3de 1872 if (caldata && (chan->channel != caldata->channel ||
6b21fd20 1873 chan->channelFlags != caldata->channelFlags)) {
20bd2a09
FF		 1874 /* Operating channel changed, reset channel calibration data */
1875 memset(caldata, 0, sizeof(*caldata));
1876 ath9k_init_nfcal_hist_buffer(ah, chan);
51dea9be 1877 } else if (caldata) {
4b9b42bf 1878 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
20bd2a09 1879 }
5bc225ac 1880 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
20bd2a09 1881
caed6579
SM		 1882 if (fastcc) {
1883 r = ath9k_hw_do_fastcc(ah, chan);
1884 if (!r)
1885 return r;
f078f209
LR		 1886 }
1887
5955b2b0 1888 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1889 ar9003_mci_stop_bt(ah, save_fullsleep);
63d32967 1890
f078f209
LR		 1891 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1892 if (saveDefAntenna == 0)
1893 saveDefAntenna = 1;
1894
1895 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1896
09d8e315
FF		 1897 /* Save TSF before chip reset, a cold reset clears it */
1898 tsf = ath9k_hw_gettsf64(ah);
1899 getrawmonotonic(&ts);
1900 usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000;
46fe782c 1901
f078f209
LR		 1902 saveLedState = REG_READ(ah, AR_CFG_LED) &
1903 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1904 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1905
1906 ath9k_hw_mark_phy_inactive(ah);
1907
45ef6a0b
VT		 1908 ah->paprd_table_write_done = false;
1909
05020d23 1910 /* Only required on the first reset */
d7e7d229
LR		 1911 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1912 REG_WRITE(ah,
1913 AR9271_RESET_POWER_DOWN_CONTROL,
1914 AR9271_RADIO_RF_RST);
1915 udelay(50);
1916 }
1917
f078f209 1918 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1919 ath_err(common, "Chip reset failed\n");
ae8d2858 1920 return -EINVAL;
f078f209
LR		 1921 }
1922
05020d23 1923 /* Only required on the first reset */
d7e7d229
LR		 1924 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1925 ah->htc_reset_init = false;
1926 REG_WRITE(ah,
1927 AR9271_RESET_POWER_DOWN_CONTROL,
1928 AR9271_GATE_MAC_CTL);
1929 udelay(50);
1930 }
1931
46fe782c 1932 /* Restore TSF */
09d8e315
FF		 1933 getrawmonotonic(&ts);
1934 usec = ts.tv_sec * 1000 + ts.tv_nsec / 1000 - usec;
1935 ath9k_hw_settsf64(ah, tsf + usec);
46fe782c 1936
7a37081e 1937 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1938 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1939
e9141f71
S		 1940 if (!AR_SREV_9300_20_OR_LATER(ah))
1941 ar9002_hw_enable_async_fifo(ah);
1942
25c56eec 1943 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1944 if (r)
1945 return r;
f078f209 1946
935d00cc
LB		 1947 ath9k_hw_set_rfmode(ah, chan);
1948
5955b2b0 1949 if (ath9k_hw_mci_is_enabled(ah))
63d32967
MSS		 1950 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1951
f860d526
FF		 1952 /*
1953 * Some AR91xx SoC devices frequently fail to accept TSF writes
1954 * right after the chip reset. When that happens, write a new
1955 * value after the initvals have been applied, with an offset
1956 * based on measured time difference
1957 */
1958 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1959 tsf += 1500;
1960 ath9k_hw_settsf64(ah, tsf);
1961 }
1962
15d2b585 1963 ath9k_hw_init_mfp(ah);
0ced0e17 1964
81c507a8 1965 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1966 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1967 ah->eep_ops->set_board_values(ah, chan);
a7765828 1968
15d2b585 1969 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
00e0003e 1970
8fe65368 1971 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1972 if (r)
1973 return r;
f078f209 1974
dfdac8ac
FF		 1975 ath9k_hw_set_clockrate(ah);
1976
15d2b585 1977 ath9k_hw_init_queues(ah);
2660b81a 1978 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1979 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1980 ath9k_hw_init_qos(ah);
1981
2660b81a 1982 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
55821324 1983 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3b319aae 1984
0005baf4 1985 ath9k_hw_init_global_settings(ah);
f078f209 1986
fe2b6afb
FF		 1987 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1988 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1989 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1990 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1991 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1992 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1993 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 1994 }
1995
ca7a4deb 1996 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1997
1998 ath9k_hw_set_dma(ah);
1999
ed6ebd8b
RM		 2000 if (!ath9k_hw_mci_is_enabled(ah))
2001 REG_WRITE(ah, AR_OBS, 8);
f078f209 2002
0ce024cb 2003 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 2004 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2005 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2006 }
2007
7f62a136
VT		 2008 if (ah->config.tx_intr_mitigation) {
2009 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
2010 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
2011 }
2012
f078f209
LR		 2013 ath9k_hw_init_bb(ah, chan);
2014
77a5a664 2015 if (caldata) {
4b9b42bf
SM		 2016 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
2017 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
77a5a664 2018 }
ae8d2858 2019 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 2020 return -EIO;
f078f209 2021
5955b2b0 2022 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
528e5d36 2023 return -EIO;
63d32967 2024
7d0d0df0 2025 ENABLE_REGWRITE_BUFFER(ah);
f078f209 2026
8fe65368 2027 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 2028 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2029
7d0d0df0 2030 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2031
15d2b585 2032 ath9k_hw_init_desc(ah);
f078f209 2033
dbccdd1d 2034 if (ath9k_hw_btcoex_is_enabled(ah))
42cc41ed
VT		 2035 ath9k_hw_btcoex_enable(ah);
2036
5955b2b0 2037 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 2038 ar9003_mci_check_bt(ah);
63d32967 2039
1fe860ed
RM		 2040 ath9k_hw_loadnf(ah, chan);
2041 ath9k_hw_start_nfcal(ah, true);
2042
51ac8cbb 2043 if (AR_SREV_9300_20_OR_LATER(ah)) {
aea702b7 2044 ar9003_hw_bb_watchdog_config(ah);
51ac8cbb
RM		 2045 ar9003_hw_disable_phy_restart(ah);
2046 }
2047
691680b8
FF		 2048 ath9k_hw_apply_gpio_override(ah);
2049
7bdea96a 2050 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
362cd03f
SM		 2051 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2052
ae8d2858 2053 return 0;
f078f209 2054}
7322fd19 2055EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 2056
f1dc5600
S		 2057/******************************/
2058/* Power Management (Chipset) */
2059/******************************/
2060
42d5bc3f
LR		 2061/*
2062 * Notify Power Mgt is disabled in self-generated frames.
2063 * If requested, force chip to sleep.
2064 */
31604cf0 2065static void ath9k_set_power_sleep(struct ath_hw *ah)
f078f209 2066{
f1dc5600 2067 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2577c6e8 2068
a4a2954f 2069 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
153dccd4
RM		 2070 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2071 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2072 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
31604cf0
SM		 2073 /* xxx Required for WLAN only case ? */
2074 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2075 udelay(100);
2076 }
2577c6e8 2077
31604cf0
SM		 2078 /*
2079 * Clear the RTC force wake bit to allow the
2080 * mac to go to sleep.
2081 */
2082 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2083
153dccd4 2084 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2085 udelay(100);
2577c6e8 2086
31604cf0
SM		 2087 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2088 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2089
31604cf0
SM		 2090 /* Shutdown chip. Active low */
2091 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2092 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2093 udelay(2);
f1dc5600 2094 }
9a658d2b
LR		 2095
2096 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 2097 if (AR_SREV_9300_20_OR_LATER(ah))
2098 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2099}
2100
bbd79af5
LR		 2101/*
2102 * Notify Power Management is enabled in self-generating
2103 * frames. If request, set power mode of chip to
2104 * auto/normal. Duration in units of 128us (1/8 TU).
2105 */
31604cf0 2106static void ath9k_set_power_network_sleep(struct ath_hw *ah)
f078f209 2107{
31604cf0 2108 struct ath9k_hw_capabilities *pCap = &ah->caps;
2577c6e8 2109
f1dc5600 2110 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2111
31604cf0
SM		 2112 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2113 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2114 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2115 AR_RTC_FORCE_WAKE_ON_INT);
2116 } else {
2577c6e8 2117
31604cf0
SM		 2118 /* When chip goes into network sleep, it could be waken
2119 * up by MCI_INT interrupt caused by BT's HW messages
2120 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2121 * rate (~100us). This will cause chip to leave and
2122 * re-enter network sleep mode frequently, which in
2123 * consequence will have WLAN MCI HW to generate lots of
2124 * SYS_WAKING and SYS_SLEEPING messages which will make
2125 * BT CPU to busy to process.
2126 */
153dccd4
RM		 2127 if (ath9k_hw_mci_is_enabled(ah))
2128 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2129 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
31604cf0
SM		 2130 /*
2131 * Clear the RTC force wake bit to allow the
2132 * mac to go to sleep.
2133 */
153dccd4 2134 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
31604cf0 2135
153dccd4 2136 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2137 udelay(30);
f078f209 2138 }
9a658d2b
LR		 2139
2140 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2141 if (AR_SREV_9300_20_OR_LATER(ah))
2142 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2143}
2144
31604cf0 2145static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
f078f209 2146{
f1dc5600
S		 2147 u32 val;
2148 int i;
f078f209 2149
9a658d2b
LR		 2150 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2151 if (AR_SREV_9300_20_OR_LATER(ah)) {
2152 REG_WRITE(ah, AR_WA, ah->WARegVal);
2153 udelay(10);
2154 }
2155
31604cf0
SM		 2156 if ((REG_READ(ah, AR_RTC_STATUS) &
2157 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2158 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2159 return false;
f1dc5600 2160 }
31604cf0
SM		 2161 if (!AR_SREV_9300_20_OR_LATER(ah))
2162 ath9k_hw_init_pll(ah, NULL);
2163 }
2164 if (AR_SREV_9100(ah))
2165 REG_SET_BIT(ah, AR_RTC_RESET,
2166 AR_RTC_RESET_EN);
2167
2168 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2169 AR_RTC_FORCE_WAKE_EN);
2170 udelay(50);
f078f209 2171
31604cf0
SM		 2172 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2173 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2174 if (val == AR_RTC_STATUS_ON)
2175 break;
2176 udelay(50);
f1dc5600
S		 2177 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2178 AR_RTC_FORCE_WAKE_EN);
31604cf0
SM		 2179 }
2180 if (i == 0) {
2181 ath_err(ath9k_hw_common(ah),
2182 "Failed to wakeup in %uus\n",
2183 POWER_UP_TIME / 20);
2184 return false;
f078f209
LR		 2185 }
2186
cdbe408d
RM		 2187 if (ath9k_hw_mci_is_enabled(ah))
2188 ar9003_mci_set_power_awake(ah);
2189
f1dc5600 2190 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2191
f1dc5600 2192 return true;
f078f209
LR		 2193}
2194
9ecdef4b 2195bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2196{
c46917bb 2197 struct ath_common *common = ath9k_hw_common(ah);
31604cf0 2198 int status = true;
f1dc5600
S		 2199 static const char *modes[] = {
2200 "AWAKE",
2201 "FULL-SLEEP",
2202 "NETWORK SLEEP",
2203 "UNDEFINED"
2204 };
f1dc5600 2205
cbdec975
GJ		 2206 if (ah->power_mode == mode)
2207 return status;
2208
d2182b69 2209 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2210 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2211
2212 switch (mode) {
2213 case ATH9K_PM_AWAKE:
31604cf0 2214 status = ath9k_hw_set_power_awake(ah);
f1dc5600
S		 2215 break;
2216 case ATH9K_PM_FULL_SLEEP:
5955b2b0 2217 if (ath9k_hw_mci_is_enabled(ah))
d1ca8b8e 2218 ar9003_mci_set_full_sleep(ah);
1010911e 2219
31604cf0 2220 ath9k_set_power_sleep(ah);
2660b81a 2221 ah->chip_fullsleep = true;
f1dc5600
S		 2222 break;
2223 case ATH9K_PM_NETWORK_SLEEP:
31604cf0 2224 ath9k_set_power_network_sleep(ah);
f1dc5600 2225 break;
f078f209 2226 default:
3800276a 2227 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2228 return false;
2229 }
2660b81a 2230 ah->power_mode = mode;
f1dc5600 2231
69f4aab1
LR		 2232 /*
2233 * XXX: If this warning never comes up after a while then
2234 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2235 * ath9k_hw_setpower() return type void.
2236 */
97dcec57
SM		 2237
2238 if (!(ah->ah_flags & AH_UNPLUGGED))
2239 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2240
f1dc5600 2241 return status;
f078f209 2242}
7322fd19 2243EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2244
f1dc5600
S		 2245/*******************/
2246/* Beacon Handling */
2247/*******************/
2248
cbe61d8a 2249void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2250{
f078f209
LR		 2251 int flags = 0;
2252
7d0d0df0
S		 2253 ENABLE_REGWRITE_BUFFER(ah);
2254
2660b81a 2255 switch (ah->opmode) {
d97809db 2256 case NL80211_IFTYPE_ADHOC:
f078f209
LR		 2257 REG_SET_BIT(ah, AR_TXCFG,
2258 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2664d666 2259 case NL80211_IFTYPE_MESH_POINT:
d97809db 2260 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2261 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2262 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2263 TU_TO_USEC(ah->config.dma_beacon_response_time));
2264 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2265 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2266 flags |=
2267 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2268 break;
d97809db 2269 default:
d2182b69
JP		 2270 ath_dbg(ath9k_hw_common(ah), BEACON,
2271 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2272 return;
2273 break;
f078f209
LR		 2274 }
2275
dd347f2f
FF		 2276 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2277 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2278 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
f078f209 2279
7d0d0df0 2280 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2281
f078f209
LR		 2282 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2283}
7322fd19 2284EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2285
cbe61d8a 2286void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2287 const struct ath9k_beacon_state *bs)
f078f209
LR		 2288{
2289 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2290 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2291 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2292
7d0d0df0
S		 2293 ENABLE_REGWRITE_BUFFER(ah);
2294
4ed15762
FF		 2295 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2296 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2297 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
f078f209 2298
7d0d0df0 2299 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2300
f078f209
LR		 2301 REG_RMW_FIELD(ah, AR_RSSI_THR,
2302 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2303
f29f5c08 2304 beaconintval = bs->bs_intval;
f078f209
LR		 2305
2306 if (bs->bs_sleepduration > beaconintval)
2307 beaconintval = bs->bs_sleepduration;
2308
2309 dtimperiod = bs->bs_dtimperiod;
2310 if (bs->bs_sleepduration > dtimperiod)
2311 dtimperiod = bs->bs_sleepduration;
2312
2313 if (beaconintval == dtimperiod)
2314 nextTbtt = bs->bs_nextdtim;
2315 else
2316 nextTbtt = bs->bs_nexttbtt;
2317
d2182b69
JP		 2318 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2319 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2320 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2321 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2322
7d0d0df0
S		 2323 ENABLE_REGWRITE_BUFFER(ah);
2324
4ed15762
FF		 2325 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2326 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
f078f209 2327
f1dc5600
S		 2328 REG_WRITE(ah, AR_SLEEP1,
2329 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2330 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2331
f1dc5600
S		 2332 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2333 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2334 else
2335 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2336
f1dc5600
S		 2337 REG_WRITE(ah, AR_SLEEP2,
2338 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2339
4ed15762
FF		 2340 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2341 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
f078f209 2342
7d0d0df0 2343 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2344
f1dc5600
S		 2345 REG_SET_BIT(ah, AR_TIMER_MODE,
2346 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2347 AR_DTIM_TIMER_EN);
f078f209 2348
4af9cf4f
S		 2349 /* TSF Out of Range Threshold */
2350 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2351}
7322fd19 2352EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2353
f1dc5600
S		 2354/*******************/
2355/* HW Capabilities */
2356/*******************/
2357
6054069a
FF		 2358static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2359{
2360 eeprom_chainmask &= chip_chainmask;
2361 if (eeprom_chainmask)
2362 return eeprom_chainmask;
2363 else
2364 return chip_chainmask;
2365}
2366
9a66af33
ZK		 2367/**
2368 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2369 * @ah: the atheros hardware data structure
2370 *
2371 * We enable DFS support upstream on chipsets which have passed a series
2372 * of tests. The testing requirements are going to be documented. Desired
2373 * test requirements are documented at:
2374 *
2375 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2376 *
2377 * Once a new chipset gets properly tested an individual commit can be used
2378 * to document the testing for DFS for that chipset.
2379 */
2380static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2381{
2382
2383 switch (ah->hw_version.macVersion) {
73e4937d
ZK		 2384 /* for temporary testing DFS with 9280 */
2385 case AR_SREV_VERSION_9280:
9a66af33
ZK		 2386 /* AR9580 will likely be our first target to get testing on */
2387 case AR_SREV_VERSION_9580:
73e4937d 2388 return true;
9a66af33
ZK		 2389 default:
2390 return false;
2391 }
2392}
2393
a9a29ce6 2394int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2395{
2660b81a 2396 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2397 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2398 struct ath_common *common = ath9k_hw_common(ah);
6054069a 2399 unsigned int chip_chainmask;
608b88cb 2400
0ff2b5c0 2401 u16 eeval;
47c80de6 2402 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2403
f74df6fb 2404 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2405 regulatory->current_rd = eeval;
f078f209 2406
2660b81a 2407 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2408 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2409 if (regulatory->current_rd == 0x64 ||
2410 regulatory->current_rd == 0x65)
2411 regulatory->current_rd += 5;
2412 else if (regulatory->current_rd == 0x41)
2413 regulatory->current_rd = 0x43;
d2182b69
JP		 2414 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2415 regulatory->current_rd);
f1dc5600 2416 }
f078f209 2417
f74df6fb 2418 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6 2419 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3800276a
JP		 2420 ath_err(common,
2421 "no band has been marked as supported in EEPROM\n");
a9a29ce6
GJ		 2422 return -EINVAL;
2423 }
2424
d4659912
FF		 2425 if (eeval & AR5416_OPFLAGS_11A)
2426 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 2427
d4659912
FF		 2428 if (eeval & AR5416_OPFLAGS_11G)
2429 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 2430
e41db61d
SM		 2431 if (AR_SREV_9485(ah) ||
2432 AR_SREV_9285(ah) ||
2433 AR_SREV_9330(ah) ||
2434 AR_SREV_9565(ah))
6054069a 2435 chip_chainmask = 1;
ba5736a5
MSS		 2436 else if (AR_SREV_9462(ah))
2437 chip_chainmask = 3;
6054069a
FF		 2438 else if (!AR_SREV_9280_20_OR_LATER(ah))
2439 chip_chainmask = 7;
2440 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2441 chip_chainmask = 3;
2442 else
2443 chip_chainmask = 7;
2444
f74df6fb 2445 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2446 /*
2447 * For AR9271 we will temporarilly uses the rx chainmax as read from
2448 * the EEPROM.
2449 */
8147f5de 2450 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2451 !(eeval & AR5416_OPFLAGS_11A) &&
2452 !(AR_SREV_9271(ah)))
2453 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2454 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2455 else if (AR_SREV_9100(ah))
2456 pCap->rx_chainmask = 0x7;
8147f5de 2457 else
d7e7d229 2458 /* Use rx_chainmask from EEPROM. */
8147f5de 2459 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2460
6054069a
FF		 2461 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2462 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2463 ah->txchainmask = pCap->tx_chainmask;
2464 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2465
7a37081e 2466 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2467
02d2ebb2
FF		 2468 /* enable key search for every frame in an aggregate */
2469 if (AR_SREV_9300_20_OR_LATER(ah))
2470 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2471
ce2220d1
BR		 2472 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2473
0db156e9 2474 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2475 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2476 else
2477 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2478
5b5fa355
S		 2479 if (AR_SREV_9271(ah))
2480 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 2481 else if (AR_DEVID_7010(ah))
2482 pCap->num_gpio_pins = AR7010_NUM_GPIO;
6321eb09
MSS		 2483 else if (AR_SREV_9300_20_OR_LATER(ah))
2484 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2485 else if (AR_SREV_9287_11_OR_LATER(ah))
2486 pCap->num_gpio_pins = AR9287_NUM_GPIO;
e17f83ea 2487 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2488 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 2489 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 2490 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2491 else
2492 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2493
1b2538b2 2494 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2495 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2496 else
f1dc5600 2497 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2498
74e13060 2499#ifdef CONFIG_ATH9K_RFKILL
2660b81a
S		 2500 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2501 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2502 ah->rfkill_gpio =
2503 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2504 ah->rfkill_polarity =
2505 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2506
2507 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2508 }
f1dc5600 2509#endif
d5d1154f 2510 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2511 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2512 else
2513 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2514
e7594072 2515 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2516 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2517 else
2518 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2519
ceb26445 2520 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2521 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
a4a2954f 2522 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
784ad503
VT		 2523 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2524
ceb26445
VT		 2525 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2526 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2527 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2528 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2529 pCap->txs_len = sizeof(struct ar9003_txs);
162c3be3
VT		 2530 } else {
2531 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2532 if (AR_SREV_9280_20(ah))
6b42e8d0 2533 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2534 }
1adf02ff 2535
6c84ce08
VT		 2536 if (AR_SREV_9300_20_OR_LATER(ah))
2537 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2538
6ee63f55
SB		 2539 if (AR_SREV_9300_20_OR_LATER(ah))
2540 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2541
a42acef0 2542 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2543 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2544
f85c3371 2545 if (AR_SREV_9285(ah)) {
754dc536
VT		 2546 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2547 ant_div_ctl1 =
2548 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2549 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
754dc536 2550 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2551 ath_info(common, "Enable LNA combining\n");
2552 }
754dc536 2553 }
f85c3371
SM		 2554 }
2555
ea066d5a
MSS		 2556 if (AR_SREV_9300_20_OR_LATER(ah)) {
2557 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2558 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2559 }
2560
06236e53 2561 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
21d2c63a 2562 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2563 if ((ant_div_ctl1 >> 0x6) == 0x3) {
21d2c63a 2564 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2565 ath_info(common, "Enable LNA combining\n");
2566 }
21d2c63a 2567 }
754dc536 2568
9a66af33
ZK		 2569 if (ath9k_hw_dfs_tested(ah))
2570 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2571
47c80de6
VT		 2572 tx_chainmask = pCap->tx_chainmask;
2573 rx_chainmask = pCap->rx_chainmask;
2574 while (tx_chainmask || rx_chainmask) {
2575 if (tx_chainmask & BIT(0))
2576 pCap->max_txchains++;
2577 if (rx_chainmask & BIT(0))
2578 pCap->max_rxchains++;
2579
2580 tx_chainmask >>= 1;
2581 rx_chainmask >>= 1;
2582 }
2583
a4a2954f 2584 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3789d59c
MSS		 2585 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2586 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2587
2b5e54e2 2588 if (AR_SREV_9462_20_OR_LATER(ah))
3789d59c 2589 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
3789d59c
MSS		 2590 }
2591
846e438f
SM		 2592 if (AR_SREV_9462(ah))
2593 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE;
d687809b 2594
0f21ee8d
SM		 2595 if (AR_SREV_9300_20_OR_LATER(ah) &&
2596 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2597 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2598
81dc75b5
SM		 2599 /*
2600 * Fast channel change across bands is available
2601 * only for AR9462 and AR9565.
2602 */
2603 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2604 pCap->hw_caps |= ATH9K_HW_CAP_FCC_BAND_SWITCH;
2605
a9a29ce6 2606 return 0;
f078f209
LR		 2607}
2608
f1dc5600
S		 2609/****************************/
2610/* GPIO / RFKILL / Antennae */
2611/****************************/
f078f209 2612
cbe61d8a 2613static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2614 u32 gpio, u32 type)
2615{
2616 int addr;
2617 u32 gpio_shift, tmp;
f078f209 2618
f1dc5600
S		 2619 if (gpio > 11)
2620 addr = AR_GPIO_OUTPUT_MUX3;
2621 else if (gpio > 5)
2622 addr = AR_GPIO_OUTPUT_MUX2;
2623 else
2624 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2625
f1dc5600 2626 gpio_shift = (gpio % 6) * 5;
f078f209 2627
f1dc5600
S		 2628 if (AR_SREV_9280_20_OR_LATER(ah)
2629 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2630 REG_RMW(ah, addr, (type << gpio_shift),
2631 (0x1f << gpio_shift));
f078f209 2632 } else {
f1dc5600
S		 2633 tmp = REG_READ(ah, addr);
2634 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2635 tmp &= ~(0x1f << gpio_shift);
2636 tmp |= (type << gpio_shift);
2637 REG_WRITE(ah, addr, tmp);
f078f209 2638 }
f078f209
LR		 2639}
2640
cbe61d8a 2641void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2642{
f1dc5600 2643 u32 gpio_shift;
f078f209 2644
9680e8a3 2645 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2646
88c1f4f6
S		 2647 if (AR_DEVID_7010(ah)) {
2648 gpio_shift = gpio;
2649 REG_RMW(ah, AR7010_GPIO_OE,
2650 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2651 (AR7010_GPIO_OE_MASK << gpio_shift));
2652 return;
2653 }
f078f209 2654
88c1f4f6 2655 gpio_shift = gpio << 1;
f1dc5600
S		 2656 REG_RMW(ah,
2657 AR_GPIO_OE_OUT,
2658 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2659 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2660}
7322fd19 2661EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2662
cbe61d8a 2663u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2664{
cb33c412
SB		 2665#define MS_REG_READ(x, y) \
2666 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2667
2660b81a 2668 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2669 return 0xffffffff;
f078f209 2670
88c1f4f6
S		 2671 if (AR_DEVID_7010(ah)) {
2672 u32 val;
2673 val = REG_READ(ah, AR7010_GPIO_IN);
2674 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2675 } else if (AR_SREV_9300_20_OR_LATER(ah))
9306990a
VT		 2676 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2677 AR_GPIO_BIT(gpio)) != 0;
783dfca1 2678 else if (AR_SREV_9271(ah))
5b5fa355 2679 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2680 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2681 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2682 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2683 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2684 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2685 return MS_REG_READ(AR928X, gpio) != 0;
2686 else
2687 return MS_REG_READ(AR, gpio) != 0;
f078f209 2688}
7322fd19 2689EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2690
cbe61d8a 2691void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2692 u32 ah_signal_type)
f078f209 2693{
f1dc5600 2694 u32 gpio_shift;
f078f209 2695
88c1f4f6
S		 2696 if (AR_DEVID_7010(ah)) {
2697 gpio_shift = gpio;
2698 REG_RMW(ah, AR7010_GPIO_OE,
2699 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2700 (AR7010_GPIO_OE_MASK << gpio_shift));
2701 return;
2702 }
f078f209 2703
88c1f4f6 2704 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2705 gpio_shift = 2 * gpio;
f1dc5600
S		 2706 REG_RMW(ah,
2707 AR_GPIO_OE_OUT,
2708 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2709 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2710}
7322fd19 2711EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2712
cbe61d8a 2713void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2714{
88c1f4f6
S		 2715 if (AR_DEVID_7010(ah)) {
2716 val = val ? 0 : 1;
2717 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2718 AR_GPIO_BIT(gpio));
2719 return;
2720 }
2721
5b5fa355
S		 2722 if (AR_SREV_9271(ah))
2723 val = ~val;
2724
f1dc5600
S		 2725 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2726 AR_GPIO_BIT(gpio));
f078f209 2727}
7322fd19 2728EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2729
cbe61d8a 2730void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2731{
f1dc5600 2732 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2733}
7322fd19 2734EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2735
f1dc5600
S		 2736/*********************/
2737/* General Operation */
2738/*********************/
2739
cbe61d8a 2740u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2741{
f1dc5600
S		 2742 u32 bits = REG_READ(ah, AR_RX_FILTER);
2743 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2744
f1dc5600
S		 2745 if (phybits & AR_PHY_ERR_RADAR)
2746 bits |= ATH9K_RX_FILTER_PHYRADAR;
2747 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2748 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2749
f1dc5600 2750 return bits;
f078f209 2751}
7322fd19 2752EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2753
cbe61d8a 2754void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2755{
f1dc5600 2756 u32 phybits;
f078f209 2757
7d0d0df0
S		 2758 ENABLE_REGWRITE_BUFFER(ah);
2759
a4a2954f 2760 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2577c6e8
SB		 2761 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2762
7ea310be
S		 2763 REG_WRITE(ah, AR_RX_FILTER, bits);
2764
f1dc5600
S		 2765 phybits = 0;
2766 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2767 phybits |= AR_PHY_ERR_RADAR;
2768 if (bits & ATH9K_RX_FILTER_PHYERR)
2769 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2770 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2771
f1dc5600 2772 if (phybits)
ca7a4deb 2773 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2774 else
ca7a4deb 2775 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2776
2777 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2778}
7322fd19 2779EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2780
cbe61d8a 2781bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2782{
99922a45
RM		 2783 if (ath9k_hw_mci_is_enabled(ah))
2784 ar9003_mci_bt_gain_ctrl(ah);
2785
63a75b91
SB		 2786 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2787 return false;
2788
2789 ath9k_hw_init_pll(ah, NULL);
8efa7a81 2790 ah->htc_reset_init = true;
63a75b91 2791 return true;
f1dc5600 2792}
7322fd19 2793EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2794
cbe61d8a 2795bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2796{
9ecdef4b 2797 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2798 return false;
f078f209 2799
63a75b91
SB		 2800 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2801 return false;
2802
2803 ath9k_hw_init_pll(ah, NULL);
2804 return true;
f078f209 2805}
7322fd19 2806EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2807
ca2c68cc
FF		 2808static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2809{
2810 enum eeprom_param gain_param;
2811
2812 if (IS_CHAN_2GHZ(chan))
2813 gain_param = EEP_ANTENNA_GAIN_2G;
2814 else
2815 gain_param = EEP_ANTENNA_GAIN_5G;
2816
2817 return ah->eep_ops->get_eeprom(ah, gain_param);
2818}
2819
64ea57d0
GJ		 2820void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2821 bool test)
ca2c68cc
FF		 2822{
2823 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2824 struct ieee80211_channel *channel;
2825 int chan_pwr, new_pwr, max_gain;
2826 int ant_gain, ant_reduction = 0;
2827
2828 if (!chan)
2829 return;
2830
2831 channel = chan->chan;
2832 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2833 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2834 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2835
2836 ant_gain = get_antenna_gain(ah, chan);
2837 if (ant_gain > max_gain)
2838 ant_reduction = ant_gain - max_gain;
2839
2840 ah->eep_ops->set_txpower(ah, chan,
2841 ath9k_regd_get_ctl(reg, chan),
64ea57d0 2842 ant_reduction, new_pwr, test);
ca2c68cc
FF		 2843}
2844
de40f316 2845void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2846{
ca2c68cc 2847 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2848 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2849 struct ieee80211_channel *channel = chan->chan;
9c204b46 2850
48ef5c42 2851 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2852 if (test)
ca2c68cc 2853 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2854
64ea57d0 2855 ath9k_hw_apply_txpower(ah, chan, test);
6f255425 2856
ca2c68cc
FF		 2857 if (test)
2858 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2859}
7322fd19 2860EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2861
cbe61d8a 2862void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2863{
2660b81a 2864 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2865}
7322fd19 2866EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2867
cbe61d8a 2868void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2869{
f1dc5600
S		 2870 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2871 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2872}
7322fd19 2873EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2874
f2b2143e 2875void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2876{
1510718d
LR		 2877 struct ath_common *common = ath9k_hw_common(ah);
2878
2879 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2880 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2881 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2882}
7322fd19 2883EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2884
1c0fc65e
BP		 2885#define ATH9K_MAX_TSF_READ 10
2886
cbe61d8a 2887u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2888{
1c0fc65e
BP		 2889 u32 tsf_lower, tsf_upper1, tsf_upper2;
2890 int i;
2891
2892 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2893 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2894 tsf_lower = REG_READ(ah, AR_TSF_L32);
2895 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2896 if (tsf_upper2 == tsf_upper1)
2897 break;
2898 tsf_upper1 = tsf_upper2;
2899 }
f078f209 2900
1c0fc65e 2901 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2902
1c0fc65e 2903 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2904}
7322fd19 2905EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2906
cbe61d8a 2907void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2908{
27abe060 2909 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2910 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2911}
7322fd19 2912EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2913
cbe61d8a 2914void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2915{
f9b604f6
GJ		 2916 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2917 AH_TSF_WRITE_TIMEOUT))
d2182b69 2918 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 2919 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2920
f1dc5600
S		 2921 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2922}
7322fd19 2923EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2924
60ca9f87 2925void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
f1dc5600 2926{
60ca9f87 2927 if (set)
2660b81a 2928 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2929 else
2660b81a 2930 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2931}
7322fd19 2932EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2933
e4744ec7 2934void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 2935{
2936 u32 macmode;
2937
e4744ec7 2938 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2939 macmode = AR_2040_JOINED_RX_CLEAR;
2940 else
2941 macmode = 0;
f078f209 2942
f1dc5600 2943 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2944}
ff155a45
VT		 2945
2946/* HW Generic timers configuration */
2947
2948static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2949{
2950 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2951 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2952 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2953 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2954 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2955 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2956 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2957 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2958 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2959 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2960 AR_NDP2_TIMER_MODE, 0x0002},
2961 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2962 AR_NDP2_TIMER_MODE, 0x0004},
2963 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2964 AR_NDP2_TIMER_MODE, 0x0008},
2965 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2966 AR_NDP2_TIMER_MODE, 0x0010},
2967 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2968 AR_NDP2_TIMER_MODE, 0x0020},
2969 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2970 AR_NDP2_TIMER_MODE, 0x0040},
2971 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2972 AR_NDP2_TIMER_MODE, 0x0080}
2973};
2974
2975/* HW generic timer primitives */
2976
dd347f2f 2977u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2978{
2979 return REG_READ(ah, AR_TSF_L32);
2980}
dd347f2f 2981EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2982
2983struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2984 void (*trigger)(void *),
2985 void (*overflow)(void *),
2986 void *arg,
2987 u8 timer_index)
2988{
2989 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2990 struct ath_gen_timer *timer;
2991
c67ce339
FF		 2992 if ((timer_index < AR_FIRST_NDP_TIMER) ||
2993 (timer_index >= ATH_MAX_GEN_TIMER))
2994 return NULL;
2995
ff155a45 2996 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
14f8dc49 2997 if (timer == NULL)
ff155a45 2998 return NULL;
ff155a45
VT		 2999
3000 /* allocate a hardware generic timer slot */
3001 timer_table->timers[timer_index] = timer;
3002 timer->index = timer_index;
3003 timer->trigger = trigger;
3004 timer->overflow = overflow;
3005 timer->arg = arg;
3006
3007 return timer;
3008}
7322fd19 3009EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 3010
cd9bf689
LR		 3011void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3012 struct ath_gen_timer *timer,
c67ce339 3013 u32 timer_next,
cd9bf689 3014 u32 timer_period)
ff155a45
VT		 3015{
3016 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
c67ce339 3017 u32 mask = 0;
788f6875 3018
c67ce339 3019 timer_table->timer_mask |= BIT(timer->index);
ff155a45 3020
ff155a45
VT		 3021 /*
3022 * Program generic timer registers
3023 */
3024 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3025 timer_next);
3026 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3027 timer_period);
3028 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3029 gen_tmr_configuration[timer->index].mode_mask);
3030
a4a2954f 3031 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2577c6e8 3032 /*
423e38e8 3033 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 3034 * to use. But we still follow the old rule, 0 - 7 use tsf and
3035 * 8 - 15 use tsf2.
3036 */
3037 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3038 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3039 (1 << timer->index));
3040 else
3041 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3042 (1 << timer->index));
3043 }
3044
c67ce339
FF		 3045 if (timer->trigger)
3046 mask |= SM(AR_GENTMR_BIT(timer->index),
3047 AR_IMR_S5_GENTIMER_TRIG);
3048 if (timer->overflow)
3049 mask |= SM(AR_GENTMR_BIT(timer->index),
3050 AR_IMR_S5_GENTIMER_THRESH);
3051
3052 REG_SET_BIT(ah, AR_IMR_S5, mask);
3053
3054 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
3055 ah->imask |= ATH9K_INT_GENTIMER;
3056 ath9k_hw_set_interrupts(ah);
3057 }
ff155a45 3058}
7322fd19 3059EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 3060
cd9bf689 3061void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 3062{
3063 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3064
ff155a45
VT		 3065 /* Clear generic timer enable bits. */
3066 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3067 gen_tmr_configuration[timer->index].mode_mask);
3068
b7f59766
SM		 3069 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3070 /*
3071 * Need to switch back to TSF if it was using TSF2.
3072 */
3073 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3074 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3075 (1 << timer->index));
3076 }
3077 }
3078
ff155a45
VT		 3079 /* Disable both trigger and thresh interrupt masks */
3080 REG_CLR_BIT(ah, AR_IMR_S5,
3081 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3082 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3083
c67ce339
FF		 3084 timer_table->timer_mask &= ~BIT(timer->index);
3085
3086 if (timer_table->timer_mask == 0) {
3087 ah->imask &= ~ATH9K_INT_GENTIMER;
3088 ath9k_hw_set_interrupts(ah);
3089 }
ff155a45 3090}
7322fd19 3091EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3092
3093void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3094{
3095 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3096
3097 /* free the hardware generic timer slot */
3098 timer_table->timers[timer->index] = NULL;
3099 kfree(timer);
3100}
7322fd19 3101EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3102
3103/*
3104 * Generic Timer Interrupts handling
3105 */
3106void ath_gen_timer_isr(struct ath_hw *ah)
3107{
3108 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3109 struct ath_gen_timer *timer;
c67ce339
FF		 3110 unsigned long trigger_mask, thresh_mask;
3111 unsigned int index;
ff155a45
VT		 3112
3113 /* get hardware generic timer interrupt status */
3114 trigger_mask = ah->intr_gen_timer_trigger;
3115 thresh_mask = ah->intr_gen_timer_thresh;
c67ce339
FF		 3116 trigger_mask &= timer_table->timer_mask;
3117 thresh_mask &= timer_table->timer_mask;
ff155a45
VT		 3118
3119 trigger_mask &= ~thresh_mask;
3120
c67ce339 3121 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3122 timer = timer_table->timers[index];
c67ce339
FF		 3123 if (!timer)
3124 continue;
3125 if (!timer->overflow)
3126 continue;
ff155a45
VT		 3127 timer->overflow(timer->arg);
3128 }
3129
c67ce339 3130 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3131 timer = timer_table->timers[index];
c67ce339
FF		 3132 if (!timer)
3133 continue;
3134 if (!timer->trigger)
3135 continue;
ff155a45
VT		 3136 timer->trigger(timer->arg);
3137 }
3138}
7322fd19 3139EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3140
05020d23
S		 3141/********/
3142/* HTC */
3143/********/
3144
2da4f01a
LR		 3145static struct {
3146 u32 version;
3147 const char * name;
3148} ath_mac_bb_names[] = {
3149 /* Devices with external radios */
3150 { AR_SREV_VERSION_5416_PCI, "5416" },
3151 { AR_SREV_VERSION_5416_PCIE, "5418" },
3152 { AR_SREV_VERSION_9100, "9100" },
3153 { AR_SREV_VERSION_9160, "9160" },
3154 /* Single-chip solutions */
3155 { AR_SREV_VERSION_9280, "9280" },
3156 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3157 { AR_SREV_VERSION_9287, "9287" },
3158 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3159 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3160 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3161 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3162 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3163 { AR_SREV_VERSION_9462, "9462" },
485124cb 3164 { AR_SREV_VERSION_9550, "9550" },
77fac465 3165 { AR_SREV_VERSION_9565, "9565" },
2da4f01a
LR		 3166};
3167
3168/* For devices with external radios */
3169static struct {
3170 u16 version;
3171 const char * name;
3172} ath_rf_names[] = {
3173 { 0, "5133" },
3174 { AR_RAD5133_SREV_MAJOR, "5133" },
3175 { AR_RAD5122_SREV_MAJOR, "5122" },
3176 { AR_RAD2133_SREV_MAJOR, "2133" },
3177 { AR_RAD2122_SREV_MAJOR, "2122" }
3178};
3179
3180/*
3181 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3182 */
f934c4d9 3183static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3184{
3185 int i;
3186
3187 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3188 if (ath_mac_bb_names[i].version == mac_bb_version) {
3189 return ath_mac_bb_names[i].name;
3190 }
3191 }
3192
3193 return "????";
3194}
2da4f01a
LR		 3195
3196/*
3197 * Return the RF name. "????" is returned if the RF is unknown.
3198 * Used for devices with external radios.
3199 */
f934c4d9 3200static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3201{
3202 int i;
3203
3204 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3205 if (ath_rf_names[i].version == rf_version) {
3206 return ath_rf_names[i].name;
3207 }
3208 }
3209
3210 return "????";
3211}
f934c4d9
LR		 3212
3213void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3214{
3215 int used;
3216
3217 /* chipsets >= AR9280 are single-chip */
7a37081e 3218 if (AR_SREV_9280_20_OR_LATER(ah)) {
5e88ba62
ZK		 3219 used = scnprintf(hw_name, len,
3220 "Atheros AR%s Rev:%x",
3221 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3222 ah->hw_version.macRev);
f934c4d9
LR		 3223 }
3224 else {
5e88ba62
ZK		 3225 used = scnprintf(hw_name, len,
3226 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3227 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3228 ah->hw_version.macRev,
3229 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3230 & AR_RADIO_SREV_MAJOR)),
3231 ah->hw_version.phyRev);
f934c4d9
LR		 3232 }
3233
3234 hw_name[used] = '\0';
3235}
3236EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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