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ath9k: Setup appropriate tx desc for regular dma and edma
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
b3950e6a 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
19
af03abec 20#include "hw.h"
d70357d5 21#include "hw-ops.h"
cfe8cba9 22#include "rc.h"
b622a720 23#include "ar9003_mac.h"
f078f209 24
4febf7b8
LR		 25#define ATH9K_CLOCK_RATE_CCK 22
26#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
27#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
f078f209 28
cbe61d8a 29static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 30
7322fd19
LR		 31MODULE_AUTHOR("Atheros Communications");
32MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
33MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
34MODULE_LICENSE("Dual BSD/GPL");
35
36static int __init ath9k_init(void)
37{
38 return 0;
39}
40module_init(ath9k_init);
41
42static void __exit ath9k_exit(void)
43{
44 return;
45}
46module_exit(ath9k_exit);
47
d70357d5
LR		 48/* Private hardware callbacks */
49
50static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
51{
52 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
53}
54
55static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
56{
57 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
58}
59
60static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
61{
62 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
63
64 return priv_ops->macversion_supported(ah->hw_version.macVersion);
65}
66
64773964
LR		 67static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
68 struct ath9k_channel *chan)
69{
70 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
71}
72
991312d8
LR		 73static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
74{
75 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
76 return;
77
78 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
79}
80
f1dc5600
S		 81/********************/
82/* Helper Functions */
83/********************/
f078f209 84
cbe61d8a 85static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 86{
b002a4a9 87 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 88
2660b81a 89 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 90 return usecs *ATH9K_CLOCK_RATE_CCK;
91 if (conf->channel->band == IEEE80211_BAND_2GHZ)
92 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
93 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 94}
95
cbe61d8a 96static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 97{
b002a4a9 98 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 99
4febf7b8 100 if (conf_is_ht40(conf))
f1dc5600
S		 101 return ath9k_hw_mac_clks(ah, usecs) * 2;
102 else
103 return ath9k_hw_mac_clks(ah, usecs);
104}
f078f209 105
0caa7b14 106bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 107{
108 int i;
109
0caa7b14
S		 110 BUG_ON(timeout < AH_TIME_QUANTUM);
111
112 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 113 if ((REG_READ(ah, reg) & mask) == val)
114 return true;
115
116 udelay(AH_TIME_QUANTUM);
117 }
04bd4638 118
c46917bb
LR		 119 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
120 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
121 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 122
f1dc5600 123 return false;
f078f209 124}
7322fd19 125EXPORT_SYMBOL(ath9k_hw_wait);
f078f209
LR		 126
127u32 ath9k_hw_reverse_bits(u32 val, u32 n)
128{
129 u32 retval;
130 int i;
131
132 for (i = 0, retval = 0; i < n; i++) {
133 retval = (retval << 1) | (val & 1);
134 val >>= 1;
135 }
136 return retval;
137}
138
cbe61d8a 139bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 140 u16 flags, u16 *low,
141 u16 *high)
f078f209 142{
2660b81a 143 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 144
f1dc5600
S		 145 if (flags & CHANNEL_5GHZ) {
146 *low = pCap->low_5ghz_chan;
147 *high = pCap->high_5ghz_chan;
148 return true;
f078f209 149 }
f1dc5600
S		 150 if ((flags & CHANNEL_2GHZ)) {
151 *low = pCap->low_2ghz_chan;
152 *high = pCap->high_2ghz_chan;
153 return true;
154 }
155 return false;
f078f209
LR		 156}
157
cbe61d8a 158u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 159 u8 phy, int kbps,
f1dc5600
S		 160 u32 frameLen, u16 rateix,
161 bool shortPreamble)
f078f209 162{
f1dc5600 163 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 164
f1dc5600
S		 165 if (kbps == 0)
166 return 0;
f078f209 167
545750d3 168 switch (phy) {
46d14a58 169 case WLAN_RC_PHY_CCK:
f1dc5600 170 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 171 if (shortPreamble)
f1dc5600
S		 172 phyTime >>= 1;
173 numBits = frameLen << 3;
174 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
175 break;
46d14a58 176 case WLAN_RC_PHY_OFDM:
2660b81a 177 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 178 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
179 numBits = OFDM_PLCP_BITS + (frameLen << 3);
180 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
181 txTime = OFDM_SIFS_TIME_QUARTER
182 + OFDM_PREAMBLE_TIME_QUARTER
183 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 184 } else if (ah->curchan &&
185 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 186 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
187 numBits = OFDM_PLCP_BITS + (frameLen << 3);
188 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
189 txTime = OFDM_SIFS_TIME_HALF +
190 OFDM_PREAMBLE_TIME_HALF
191 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
192 } else {
193 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
194 numBits = OFDM_PLCP_BITS + (frameLen << 3);
195 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
196 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
197 + (numSymbols * OFDM_SYMBOL_TIME);
198 }
199 break;
200 default:
c46917bb 201 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
545750d3 202 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 203 txTime = 0;
204 break;
205 }
f078f209 206
f1dc5600
S		 207 return txTime;
208}
7322fd19 209EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 210
cbe61d8a 211void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 212 struct ath9k_channel *chan,
213 struct chan_centers *centers)
f078f209 214{
f1dc5600 215 int8_t extoff;
f078f209 216
f1dc5600
S		 217 if (!IS_CHAN_HT40(chan)) {
218 centers->ctl_center = centers->ext_center =
219 centers->synth_center = chan->channel;
220 return;
f078f209 221 }
f078f209 222
f1dc5600
S		 223 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
224 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
225 centers->synth_center =
226 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
227 extoff = 1;
228 } else {
229 centers->synth_center =
230 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
231 extoff = -1;
232 }
f078f209 233
f1dc5600
S		 234 centers->ctl_center =
235 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 236 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 237 centers->ext_center =
6420014c 238 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 239}
240
f1dc5600
S		 241/******************/
242/* Chip Revisions */
243/******************/
244
cbe61d8a 245static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 246{
f1dc5600 247 u32 val;
f078f209 248
f1dc5600 249 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 250
f1dc5600
S		 251 if (val == 0xFF) {
252 val = REG_READ(ah, AR_SREV);
d535a42a
S		 253 ah->hw_version.macVersion =
254 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
255 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 256 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 257 } else {
258 if (!AR_SREV_9100(ah))
d535a42a 259 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 260
d535a42a 261 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 262
d535a42a 263 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 264 ah->is_pciexpress = true;
f1dc5600 265 }
f078f209
LR		 266}
267
f1dc5600
S		 268/************************************/
269/* HW Attach, Detach, Init Routines */
270/************************************/
271
cbe61d8a 272static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 273{
feed029c 274 if (AR_SREV_9100(ah))
f1dc5600 275 return;
f078f209 276
f1dc5600
S		 277 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
278 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
279 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
280 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
281 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
282 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
283 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 286
f1dc5600 287 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 288}
289
1f3f0618 290/* This should work for all families including legacy */
cbe61d8a 291static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 292{
c46917bb 293 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 294 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600
S		 295 u32 regHold[2];
296 u32 patternData[4] = { 0x55555555,
297 0xaaaaaaaa,
298 0x66666666,
299 0x99999999 };
1f3f0618 300 int i, j, loop_max;
f078f209 301
1f3f0618
SB		 302 if (!AR_SREV_9300_20_OR_LATER(ah)) {
303 loop_max = 2;
304 regAddr[1] = AR_PHY_BASE + (8 << 2);
305 } else
306 loop_max = 1;
307
308 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 309 u32 addr = regAddr[i];
310 u32 wrData, rdData;
f078f209 311
f1dc5600
S		 312 regHold[i] = REG_READ(ah, addr);
313 for (j = 0; j < 0x100; j++) {
314 wrData = (j << 16) | j;
315 REG_WRITE(ah, addr, wrData);
316 rdData = REG_READ(ah, addr);
317 if (rdData != wrData) {
c46917bb
LR		 318 ath_print(common, ATH_DBG_FATAL,
319 "address test failed "
320 "addr: 0x%08x - wr:0x%08x != "
321 "rd:0x%08x\n",
322 addr, wrData, rdData);
f1dc5600
S		 323 return false;
324 }
325 }
326 for (j = 0; j < 4; j++) {
327 wrData = patternData[j];
328 REG_WRITE(ah, addr, wrData);
329 rdData = REG_READ(ah, addr);
330 if (wrData != rdData) {
c46917bb
LR		 331 ath_print(common, ATH_DBG_FATAL,
332 "address test failed "
333 "addr: 0x%08x - wr:0x%08x != "
334 "rd:0x%08x\n",
335 addr, wrData, rdData);
f1dc5600
S		 336 return false;
337 }
f078f209 338 }
f1dc5600 339 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 340 }
f1dc5600 341 udelay(100);
cbe61d8a 342
f078f209
LR		 343 return true;
344}
345
b8b0f377 346static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 347{
348 int i;
f078f209 349
2660b81a
S		 350 ah->config.dma_beacon_response_time = 2;
351 ah->config.sw_beacon_response_time = 10;
352 ah->config.additional_swba_backoff = 0;
353 ah->config.ack_6mb = 0x0;
354 ah->config.cwm_ignore_extcca = 0;
355 ah->config.pcie_powersave_enable = 0;
2660b81a 356 ah->config.pcie_clock_req = 0;
2660b81a
S		 357 ah->config.pcie_waen = 0;
358 ah->config.analog_shiftreg = 1;
2660b81a
S		 359 ah->config.ofdm_trig_low = 200;
360 ah->config.ofdm_trig_high = 500;
361 ah->config.cck_trig_high = 200;
362 ah->config.cck_trig_low = 100;
31a0bd3c
LR		 363
364 /*
365 * For now ANI is disabled for AR9003, it is still
366 * being tested.
367 */
368 if (!AR_SREV_9300_20_OR_LATER(ah))
369 ah->config.enable_ani = 1;
f078f209 370
f1dc5600 371 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 372 ah->config.spurchans[i][0] = AR_NO_SPUR;
373 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 374 }
375
5ffaf8a3
LR		 376 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
377 ah->config.ht_enable = 1;
378 else
379 ah->config.ht_enable = 0;
380
0ce024cb 381 ah->config.rx_intr_mitigation = true;
6158425b
LR		 382
383 /*
384 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
385 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
386 * This means we use it for all AR5416 devices, and the few
387 * minor PCI AR9280 devices out there.
388 *
389 * Serialization is required because these devices do not handle
390 * well the case of two concurrent reads/writes due to the latency
391 * involved. During one read/write another read/write can be issued
392 * on another CPU while the previous read/write may still be working
393 * on our hardware, if we hit this case the hardware poops in a loop.
394 * We prevent this by serializing reads and writes.
395 *
396 * This issue is not present on PCI-Express devices or pre-AR5416
397 * devices (legacy, 802.11abg).
398 */
399 if (num_possible_cpus() > 1)
2d6a5e95 400 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 401}
402
50aca25b 403static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 404{
608b88cb
LR		 405 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
406
407 regulatory->country_code = CTRY_DEFAULT;
408 regulatory->power_limit = MAX_RATE_POWER;
409 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
410
d535a42a 411 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 412 ah->hw_version.subvendorid = 0;
f078f209
LR		 413
414 ah->ah_flags = 0;
f078f209
LR		 415 if (!AR_SREV_9100(ah))
416 ah->ah_flags = AH_USE_EEPROM;
417
2660b81a 418 ah->atim_window = 0;
2660b81a
S		 419 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
420 ah->beacon_interval = 100;
421 ah->enable_32kHz_clock = DONT_USE_32KHZ;
422 ah->slottime = (u32) -1;
2660b81a 423 ah->globaltxtimeout = (u32) -1;
cbdec975 424 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 425}
426
cbe61d8a 427static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 428{
1510718d 429 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 430 u32 sum;
431 int i;
432 u16 eeval;
49101676 433 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 434
435 sum = 0;
436 for (i = 0; i < 3; i++) {
49101676 437 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 438 sum += eeval;
1510718d
LR		 439 common->macaddr[2 * i] = eeval >> 8;
440 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 441 }
d8baa939 442 if (sum == 0 || sum == 0xffff * 3)
f078f209 443 return -EADDRNOTAVAIL;
f078f209
LR		 444
445 return 0;
446}
447
f637cfd6 448static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 449{
f1dc5600 450 int ecode;
f078f209 451
527d485f
S		 452 if (!AR_SREV_9271(ah)) {
453 if (!ath9k_hw_chip_test(ah))
454 return -ENODEV;
455 }
f078f209 456
ebd5a14a
LR		 457 if (!AR_SREV_9300_20_OR_LATER(ah)) {
458 ecode = ar9002_hw_rf_claim(ah);
459 if (ecode != 0)
460 return ecode;
461 }
f078f209 462
f637cfd6 463 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 464 if (ecode != 0)
465 return ecode;
7d01b221 466
c46917bb
LR		 467 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
468 "Eeprom VER: %d, REV: %d\n",
469 ah->eep_ops->get_eeprom_ver(ah),
470 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 471
8fe65368
LR		 472 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
473 if (ecode) {
474 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
475 "Failed allocating banks for "
476 "external radio\n");
477 return ecode;
574d6b12 478 }
f078f209 479
f1dc5600
S		 480 if (!AR_SREV_9100(ah)) {
481 ath9k_hw_ani_setup(ah);
f637cfd6 482 ath9k_hw_ani_init(ah);
f078f209
LR		 483 }
484
f078f209
LR		 485 return 0;
486}
487
8525f280
LR		 488static void ath9k_hw_attach_ops(struct ath_hw *ah)
489{
490 if (AR_SREV_9300_20_OR_LATER(ah))
491 ar9003_hw_attach_ops(ah);
492 else
493 ar9002_hw_attach_ops(ah);
494}
495
d70357d5
LR		 496/* Called for all hardware families */
497static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 498{
c46917bb 499 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 500 int r = 0;
aa4058ae 501
bab1f62e
LR		 502 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
503 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
aa4058ae
LR		 504
505 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
c46917bb
LR		 506 ath_print(common, ATH_DBG_FATAL,
507 "Couldn't reset chip\n");
95fafca2 508 return -EIO;
aa4058ae
LR		 509 }
510
bab1f62e
LR		 511 ath9k_hw_init_defaults(ah);
512 ath9k_hw_init_config(ah);
513
8525f280 514 ath9k_hw_attach_ops(ah);
d70357d5 515
9ecdef4b 516 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
c46917bb 517 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
95fafca2 518 return -EIO;
aa4058ae
LR		 519 }
520
521 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
522 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
523 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
524 ah->config.serialize_regmode =
525 SER_REG_MODE_ON;
526 } else {
527 ah->config.serialize_regmode =
528 SER_REG_MODE_OFF;
529 }
530 }
531
c46917bb 532 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 533 ah->config.serialize_regmode);
534
f4709fdf
LR		 535 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
536 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
537 else
538 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
539
d70357d5 540 if (!ath9k_hw_macversion_supported(ah)) {
c46917bb
LR		 541 ath_print(common, ATH_DBG_FATAL,
542 "Mac Chip Rev 0x%02x.%x is not supported by "
543 "this driver\n", ah->hw_version.macVersion,
544 ah->hw_version.macRev);
95fafca2 545 return -EOPNOTSUPP;
aa4058ae
LR		 546 }
547
0df13da4 548 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
d7e7d229
LR		 549 ah->is_pciexpress = false;
550
aa4058ae 551 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 552 ath9k_hw_init_cal_settings(ah);
553
554 ah->ani_function = ATH9K_ANI_ALL;
31a0bd3c 555 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae
LR		 556 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
557
558 ath9k_hw_init_mode_regs(ah);
559
560 if (ah->is_pciexpress)
93b1b37f 561 ath9k_hw_configpcipowersave(ah, 0, 0);
aa4058ae
LR		 562 else
563 ath9k_hw_disablepcie(ah);
564
d8f492b7
LR		 565 if (!AR_SREV_9300_20_OR_LATER(ah))
566 ar9002_hw_cck_chan14_spread(ah);
193cd458 567
f637cfd6 568 r = ath9k_hw_post_init(ah);
aa4058ae 569 if (r)
95fafca2 570 return r;
aa4058ae
LR		 571
572 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 573 r = ath9k_hw_fill_cap_info(ah);
574 if (r)
575 return r;
576
4f3acf81
LR		 577 r = ath9k_hw_init_macaddr(ah);
578 if (r) {
c46917bb
LR		 579 ath_print(common, ATH_DBG_FATAL,
580 "Failed to initialize MAC address\n");
95fafca2 581 return r;
f078f209
LR		 582 }
583
d7e7d229 584 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 585 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 586 else
2660b81a 587 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 588
641d9921
FF		 589 if (AR_SREV_9300_20_OR_LATER(ah))
590 ar9003_hw_set_nf_limits(ah);
591
f1dc5600 592 ath9k_init_nfcal_hist_buffer(ah);
f078f209 593
211f5859
LR		 594 common->state = ATH_HW_INITIALIZED;
595
4f3acf81 596 return 0;
f078f209
LR		 597}
598
d70357d5
LR		 599int ath9k_hw_init(struct ath_hw *ah)
600{
601 int ret;
602 struct ath_common *common = ath9k_hw_common(ah);
603
604 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
605 switch (ah->hw_version.devid) {
606 case AR5416_DEVID_PCI:
607 case AR5416_DEVID_PCIE:
608 case AR5416_AR9100_DEVID:
609 case AR9160_DEVID_PCI:
610 case AR9280_DEVID_PCI:
611 case AR9280_DEVID_PCIE:
612 case AR9285_DEVID_PCIE:
db3cc53a
SB		 613 case AR9287_DEVID_PCI:
614 case AR9287_DEVID_PCIE:
d70357d5 615 case AR2427_DEVID_PCIE:
db3cc53a 616 case AR9300_DEVID_PCIE:
d70357d5
LR		 617 break;
618 default:
619 if (common->bus_ops->ath_bus_type == ATH_USB)
620 break;
621 ath_print(common, ATH_DBG_FATAL,
622 "Hardware device ID 0x%04x not supported\n",
623 ah->hw_version.devid);
624 return -EOPNOTSUPP;
625 }
626
627 ret = __ath9k_hw_init(ah);
628 if (ret) {
629 ath_print(common, ATH_DBG_FATAL,
630 "Unable to initialize hardware; "
631 "initialization status: %d\n", ret);
632 return ret;
633 }
634
635 return 0;
636}
637EXPORT_SYMBOL(ath9k_hw_init);
638
cbe61d8a 639static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 640{
f1dc5600
S		 641 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
642 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 643
f1dc5600
S		 644 REG_WRITE(ah, AR_QOS_NO_ACK,
645 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
646 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
647 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
648
649 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
650 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
651 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
652 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
653 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
f078f209
LR		 654}
655
cbe61d8a 656static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 657 struct ath9k_channel *chan)
f078f209 658{
64773964 659 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
f078f209 660
d03a66c1 661 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 662
c75724d1
LR		 663 /* Switch the core clock for ar9271 to 117Mhz */
664 if (AR_SREV_9271(ah)) {
25e2ab17
S		 665 udelay(500);
666 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 667 }
668
f1dc5600
S		 669 udelay(RTC_PLL_SETTLE_DELAY);
670
671 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 672}
673
cbe61d8a 674static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 675 enum nl80211_iftype opmode)
f078f209 676{
152d530d 677 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 678 AR_IMR_TXURN |
679 AR_IMR_RXERR |
680 AR_IMR_RXORN |
681 AR_IMR_BCNMISC;
f078f209 682
66860240
VT		 683 if (AR_SREV_9300_20_OR_LATER(ah)) {
684 imr_reg |= AR_IMR_RXOK_HP;
685 if (ah->config.rx_intr_mitigation)
686 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
687 else
688 imr_reg |= AR_IMR_RXOK_LP;
f078f209 689
66860240
VT		 690 } else {
691 if (ah->config.rx_intr_mitigation)
692 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
693 else
694 imr_reg |= AR_IMR_RXOK;
695 }
696
697 if (ah->config.tx_intr_mitigation)
698 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
699 else
700 imr_reg |= AR_IMR_TXOK;
f078f209 701
d97809db 702 if (opmode == NL80211_IFTYPE_AP)
152d530d 703 imr_reg |= AR_IMR_MIB;
f078f209 704
152d530d 705 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 706 ah->imrs2_reg |= AR_IMR_S2_GTT;
707 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 708
f1dc5600
S		 709 if (!AR_SREV_9100(ah)) {
710 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
711 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
712 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
713 }
66860240
VT		 714
715 if (AR_SREV_9300_20_OR_LATER(ah)) {
716 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
717 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
718 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
719 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
720 }
f078f209
LR		 721}
722
0005baf4 723static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 724{
0005baf4
FF		 725 u32 val = ath9k_hw_mac_to_clks(ah, us);
726 val = min(val, (u32) 0xFFFF);
727 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 728}
729
0005baf4 730static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 731{
0005baf4
FF		 732 u32 val = ath9k_hw_mac_to_clks(ah, us);
733 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
734 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
735}
736
737static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
738{
739 u32 val = ath9k_hw_mac_to_clks(ah, us);
740 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
741 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 742}
f1dc5600 743
cbe61d8a 744static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 745{
f078f209 746 if (tu > 0xFFFF) {
c46917bb
LR		 747 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
748 "bad global tx timeout %u\n", tu);
2660b81a 749 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 750 return false;
751 } else {
752 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 753 ah->globaltxtimeout = tu;
f078f209
LR		 754 return true;
755 }
756}
757
0005baf4 758void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 759{
0005baf4
FF		 760 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
761 int acktimeout;
e239d859 762 int slottime;
0005baf4
FF		 763 int sifstime;
764
c46917bb
LR		 765 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
766 ah->misc_mode);
f078f209 767
2660b81a 768 if (ah->misc_mode != 0)
f1dc5600 769 REG_WRITE(ah, AR_PCU_MISC,
2660b81a 770 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
0005baf4
FF		 771
772 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
773 sifstime = 16;
774 else
775 sifstime = 10;
776
e239d859
FF		 777 /* As defined by IEEE 802.11-2007 17.3.8.6 */
778 slottime = ah->slottime + 3 * ah->coverage_class;
779 acktimeout = slottime + sifstime;
42c4568a
FF		 780
781 /*
782 * Workaround for early ACK timeouts, add an offset to match the
783 * initval's 64us ack timeout value.
784 * This was initially only meant to work around an issue with delayed
785 * BA frames in some implementations, but it has been found to fix ACK
786 * timeout issues in other cases as well.
787 */
788 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
789 acktimeout += 64 - sifstime - ah->slottime;
790
e239d859 791 ath9k_hw_setslottime(ah, slottime);
0005baf4
FF		 792 ath9k_hw_set_ack_timeout(ah, acktimeout);
793 ath9k_hw_set_cts_timeout(ah, acktimeout);
2660b81a
S		 794 if (ah->globaltxtimeout != (u32) -1)
795 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600 796}
0005baf4 797EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 798
285f2dda 799void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 800{
211f5859
LR		 801 struct ath_common *common = ath9k_hw_common(ah);
802
736b3a27 803 if (common->state < ATH_HW_INITIALIZED)
211f5859
LR		 804 goto free_hw;
805
f1dc5600 806 if (!AR_SREV_9100(ah))
e70c0cfd 807 ath9k_hw_ani_disable(ah);
f1dc5600 808
9ecdef4b 809 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 810
811free_hw:
8fe65368 812 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 813}
285f2dda 814EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 815
f1dc5600
S		 816/*******/
817/* INI */
818/*******/
819
8fe65368 820u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 821{
822 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
823
824 if (IS_CHAN_B(chan))
825 ctl |= CTL_11B;
826 else if (IS_CHAN_G(chan))
827 ctl |= CTL_11G;
828 else
829 ctl |= CTL_11A;
830
831 return ctl;
832}
833
f1dc5600
S		 834/****************************************/
835/* Reset and Channel Switching Routines */
836/****************************************/
837
cbe61d8a 838static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 839{
57b32227 840 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 841 u32 regval;
842
d7e7d229
LR		 843 /*
844 * set AHB_MODE not to do cacheline prefetches
845 */
57b32227
FF		 846 if (!AR_SREV_9300_20_OR_LATER(ah)) {
847 regval = REG_READ(ah, AR_AHB_MODE);
848 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
849 }
f1dc5600 850
d7e7d229
LR		 851 /*
852 * let mac dma reads be in 128 byte chunks
853 */
f1dc5600
S		 854 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
855 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
856
d7e7d229
LR		 857 /*
858 * Restore TX Trigger Level to its pre-reset value.
859 * The initial value depends on whether aggregation is enabled, and is
860 * adjusted whenever underruns are detected.
861 */
57b32227
FF		 862 if (!AR_SREV_9300_20_OR_LATER(ah))
863 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 864
d7e7d229
LR		 865 /*
866 * let mac dma writes be in 128 byte chunks
867 */
f1dc5600
S		 868 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
869 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
870
d7e7d229
LR		 871 /*
872 * Setup receive FIFO threshold to hold off TX activities
873 */
f1dc5600
S		 874 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
875
57b32227
FF		 876 if (AR_SREV_9300_20_OR_LATER(ah)) {
877 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
878 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
879
880 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
881 ah->caps.rx_status_len);
882 }
883
d7e7d229
LR		 884 /*
885 * reduce the number of usable entries in PCU TXBUF to avoid
886 * wrap around issues.
887 */
f1dc5600 888 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 889 /* For AR9285 the number of Fifos are reduced to half.
890 * So set the usable tx buf size also to half to
891 * avoid data/delimiter underruns
892 */
f1dc5600
S		 893 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
894 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 895 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 896 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
897 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
898 }
744d4025
VT		 899
900 if (AR_SREV_9300_20_OR_LATER(ah))
901 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 902}
903
cbe61d8a 904static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 905{
906 u32 val;
907
908 val = REG_READ(ah, AR_STA_ID1);
909 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
910 switch (opmode) {
d97809db 911 case NL80211_IFTYPE_AP:
f1dc5600
S		 912 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
913 | AR_STA_ID1_KSRCH_MODE);
914 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 915 break;
d97809db 916 case NL80211_IFTYPE_ADHOC:
9cb5412b 917 case NL80211_IFTYPE_MESH_POINT:
f1dc5600
S		 918 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
919 | AR_STA_ID1_KSRCH_MODE);
920 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 921 break;
d97809db
CM		 922 case NL80211_IFTYPE_STATION:
923 case NL80211_IFTYPE_MONITOR:
f1dc5600 924 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 925 break;
f1dc5600
S		 926 }
927}
928
8fe65368
LR		 929void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
930 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 931{
932 u32 coef_exp, coef_man;
933
934 for (coef_exp = 31; coef_exp > 0; coef_exp--)
935 if ((coef_scaled >> coef_exp) & 0x1)
936 break;
937
938 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
939
940 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
941
942 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
943 *coef_exponent = coef_exp - 16;
944}
945
cbe61d8a 946static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 947{
948 u32 rst_flags;
949 u32 tmpReg;
950
70768496
S		 951 if (AR_SREV_9100(ah)) {
952 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
953 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
954 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
955 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
956 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
957 }
958
f1dc5600
S		 959 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
960 AR_RTC_FORCE_WAKE_ON_INT);
961
962 if (AR_SREV_9100(ah)) {
963 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
964 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
965 } else {
966 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
967 if (tmpReg &
968 (AR_INTR_SYNC_LOCAL_TIMEOUT |
969 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 970 u32 val;
f1dc5600 971 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 972
973 val = AR_RC_HOSTIF;
974 if (!AR_SREV_9300_20_OR_LATER(ah))
975 val |= AR_RC_AHB;
976 REG_WRITE(ah, AR_RC, val);
977
978 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 979 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 980
981 rst_flags = AR_RTC_RC_MAC_WARM;
982 if (type == ATH9K_RESET_COLD)
983 rst_flags |= AR_RTC_RC_MAC_COLD;
984 }
985
d03a66c1 986 REG_WRITE(ah, AR_RTC_RC, rst_flags);
f1dc5600
S		 987 udelay(50);
988
d03a66c1 989 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 990 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 991 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
992 "RTC stuck in MAC reset\n");
f1dc5600
S		 993 return false;
994 }
995
996 if (!AR_SREV_9100(ah))
997 REG_WRITE(ah, AR_RC, 0);
998
f1dc5600
S		 999 if (AR_SREV_9100(ah))
1000 udelay(50);
1001
1002 return true;
1003}
1004
cbe61d8a 1005static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600
S		 1006{
1007 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1008 AR_RTC_FORCE_WAKE_ON_INT);
1009
42d5bc3f 1010 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1011 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1012
d03a66c1 1013 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1014
84e2169b
SB		 1015 if (!AR_SREV_9300_20_OR_LATER(ah))
1016 udelay(2);
1017
1018 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1019 REG_WRITE(ah, AR_RC, 0);
1020
d03a66c1 1021 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1022
1023 if (!ath9k_hw_wait(ah,
1024 AR_RTC_STATUS,
1025 AR_RTC_STATUS_M,
0caa7b14
S		 1026 AR_RTC_STATUS_ON,
1027 AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1028 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1029 "RTC not waking up\n");
f1dc5600 1030 return false;
f078f209
LR		 1031 }
1032
f1dc5600
S		 1033 ath9k_hw_read_revisions(ah);
1034
1035 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1036}
1037
cbe61d8a 1038static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600
S		 1039{
1040 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1041 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1042
1043 switch (type) {
1044 case ATH9K_RESET_POWER_ON:
1045 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1046 case ATH9K_RESET_WARM:
1047 case ATH9K_RESET_COLD:
1048 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1049 default:
1050 return false;
1051 }
f078f209
LR		 1052}
1053
cbe61d8a 1054static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1055 struct ath9k_channel *chan)
f078f209 1056{
42abfbee 1057 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1058 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1059 return false;
1060 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1061 return false;
f078f209 1062
9ecdef4b 1063 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1064 return false;
f078f209 1065
2660b81a 1066 ah->chip_fullsleep = false;
f1dc5600 1067 ath9k_hw_init_pll(ah, chan);
f1dc5600 1068 ath9k_hw_set_rfmode(ah, chan);
f078f209 1069
f1dc5600 1070 return true;
f078f209
LR		 1071}
1072
cbe61d8a 1073static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1074 struct ath9k_channel *chan)
f078f209 1075{
608b88cb 1076 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1077 struct ath_common *common = ath9k_hw_common(ah);
5f8e077c 1078 struct ieee80211_channel *channel = chan->chan;
8fe65368 1079 u32 qnum;
0a3b7bac 1080 int r;
f078f209
LR		 1081
1082 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1083 if (ath9k_hw_numtxpending(ah, qnum)) {
c46917bb
LR		 1084 ath_print(common, ATH_DBG_QUEUE,
1085 "Transmit frames pending on "
1086 "queue %d\n", qnum);
f078f209
LR		 1087 return false;
1088 }
1089 }
1090
8fe65368 1091 if (!ath9k_hw_rfbus_req(ah)) {
c46917bb
LR		 1092 ath_print(common, ATH_DBG_FATAL,
1093 "Could not kill baseband RX\n");
f078f209
LR		 1094 return false;
1095 }
1096
8fe65368 1097 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1098
8fe65368 1099 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1100 if (r) {
1101 ath_print(common, ATH_DBG_FATAL,
1102 "Failed to set channel\n");
1103 return false;
f078f209
LR		 1104 }
1105
8fbff4b8 1106 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1107 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1108 channel->max_antenna_gain * 2,
1109 channel->max_power * 2,
1110 min((u32) MAX_RATE_POWER,
608b88cb 1111 (u32) regulatory->power_limit));
f078f209 1112
8fe65368 1113 ath9k_hw_rfbus_done(ah);
f078f209 1114
f1dc5600
S		 1115 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1116 ath9k_hw_set_delta_slope(ah, chan);
1117
8fe65368 1118 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600
S		 1119
1120 if (!chan->oneTimeCalsDone)
1121 chan->oneTimeCalsDone = true;
1122
1123 return true;
1124}
1125
cbe61d8a 1126int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ae8d2858 1127 bool bChannelChange)
f078f209 1128{
1510718d 1129 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1130 u32 saveLedState;
2660b81a 1131 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 1132 u32 saveDefAntenna;
1133 u32 macStaId1;
46fe782c 1134 u64 tsf = 0;
8fe65368 1135 int i, r;
f078f209 1136
43c27613
LR		 1137 ah->txchainmask = common->tx_chainmask;
1138 ah->rxchainmask = common->rx_chainmask;
f078f209 1139
9ecdef4b 1140 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1141 return -EIO;
f078f209 1142
9ebef799 1143 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 1144 ath9k_hw_getnf(ah, curchan);
1145
1146 if (bChannelChange &&
2660b81a
S		 1147 (ah->chip_fullsleep != true) &&
1148 (ah->curchan != NULL) &&
1149 (chan->channel != ah->curchan->channel) &&
f078f209 1150 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 1151 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
0a475cc6
VT		 1152 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1153 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
f078f209 1154
25c56eec 1155 if (ath9k_hw_channel_change(ah, chan)) {
2660b81a 1156 ath9k_hw_loadnf(ah, ah->curchan);
f078f209 1157 ath9k_hw_start_nfcal(ah);
ae8d2858 1158 return 0;
f078f209
LR		 1159 }
1160 }
1161
1162 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1163 if (saveDefAntenna == 0)
1164 saveDefAntenna = 1;
1165
1166 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1167
46fe782c
S		 1168 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1169 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1170 tsf = ath9k_hw_gettsf64(ah);
1171
f078f209
LR		 1172 saveLedState = REG_READ(ah, AR_CFG_LED) &
1173 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1174 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1175
1176 ath9k_hw_mark_phy_inactive(ah);
1177
05020d23 1178 /* Only required on the first reset */
d7e7d229
LR		 1179 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1180 REG_WRITE(ah,
1181 AR9271_RESET_POWER_DOWN_CONTROL,
1182 AR9271_RADIO_RF_RST);
1183 udelay(50);
1184 }
1185
f078f209 1186 if (!ath9k_hw_chip_reset(ah, chan)) {
c46917bb 1187 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
ae8d2858 1188 return -EINVAL;
f078f209
LR		 1189 }
1190
05020d23 1191 /* Only required on the first reset */
d7e7d229
LR		 1192 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1193 ah->htc_reset_init = false;
1194 REG_WRITE(ah,
1195 AR9271_RESET_POWER_DOWN_CONTROL,
1196 AR9271_GATE_MAC_CTL);
1197 udelay(50);
1198 }
1199
46fe782c
S		 1200 /* Restore TSF */
1201 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1202 ath9k_hw_settsf64(ah, tsf);
1203
369391db
VT		 1204 if (AR_SREV_9280_10_OR_LATER(ah))
1205 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1206
25c56eec 1207 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1208 if (r)
1209 return r;
f078f209 1210
0ced0e17
JM		 1211 /* Setup MFP options for CCMP */
1212 if (AR_SREV_9280_20_OR_LATER(ah)) {
1213 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1214 * frames when constructing CCMP AAD. */
1215 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1216 0xc7ff);
1217 ah->sw_mgmt_crypto = false;
1218 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1219 /* Disable hardware crypto for management frames */
1220 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1221 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1222 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1223 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1224 ah->sw_mgmt_crypto = true;
1225 } else
1226 ah->sw_mgmt_crypto = true;
1227
f078f209
LR		 1228 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1229 ath9k_hw_set_delta_slope(ah, chan);
1230
8fe65368 1231 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1232 ah->eep_ops->set_board_values(ah, chan);
a7765828 1233
1510718d
LR		 1234 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1235 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 1236 | macStaId1
1237 | AR_STA_ID1_RTS_USE_DEF
2660b81a 1238 | (ah->config.
60b67f51 1239 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a
S		 1240 | ah->sta_id1_defaults);
1241 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 1242
13b81559 1243 ath_hw_setbssidmask(common);
f078f209
LR		 1244
1245 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1246
3453ad88 1247 ath9k_hw_write_associd(ah);
f078f209
LR		 1248
1249 REG_WRITE(ah, AR_ISR, ~0);
1250
1251 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1252
8fe65368 1253 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1254 if (r)
1255 return r;
f078f209
LR		 1256
1257 for (i = 0; i < AR_NUM_DCU; i++)
1258 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1259
2660b81a
S		 1260 ah->intr_txqs = 0;
1261 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 1262 ath9k_hw_resettxqueue(ah, i);
1263
2660b81a 1264 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
f078f209
LR		 1265 ath9k_hw_init_qos(ah);
1266
2660b81a 1267 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d 1268 ath9k_enable_rfkill(ah);
3b319aae 1269
0005baf4 1270 ath9k_hw_init_global_settings(ah);
f078f209 1271
6c94fdc9 1272 if (!AR_SREV_9300_20_OR_LATER(ah)) {
78ec2677 1273 ar9002_hw_enable_async_fifo(ah);
6c94fdc9 1274 ar9002_hw_enable_wep_aggregation(ah);
ac88b6ec
VN		 1275 }
1276
f078f209
LR		 1277 REG_WRITE(ah, AR_STA_ID1,
1278 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1279
1280 ath9k_hw_set_dma(ah);
1281
1282 REG_WRITE(ah, AR_OBS, 8);
1283
0ce024cb 1284 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1285 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1286 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1287 }
1288
7f62a136
VT		 1289 if (ah->config.tx_intr_mitigation) {
1290 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1291 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1292 }
1293
f078f209
LR		 1294 ath9k_hw_init_bb(ah, chan);
1295
ae8d2858 1296 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1297 return -EIO;
f078f209 1298
8fe65368 1299 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1300 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1301
d7e7d229
LR		 1302 /*
1303 * For big endian systems turn on swapping for descriptors
1304 */
f078f209
LR		 1305 if (AR_SREV_9100(ah)) {
1306 u32 mask;
1307 mask = REG_READ(ah, AR_CFG);
1308 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
c46917bb 1309 ath_print(common, ATH_DBG_RESET,
04bd4638 1310 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 1311 } else {
1312 mask =
1313 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1314 REG_WRITE(ah, AR_CFG, mask);
c46917bb 1315 ath_print(common, ATH_DBG_RESET,
04bd4638 1316 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 1317 }
1318 } else {
d7e7d229
LR		 1319 /* Configure AR9271 target WLAN */
1320 if (AR_SREV_9271(ah))
1321 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
f078f209 1322#ifdef __BIG_ENDIAN
d7e7d229
LR		 1323 else
1324 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 1325#endif
1326 }
1327
766ec4a9 1328 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 1329 ath9k_hw_btcoex_enable(ah);
1330
d8903a53
VT		 1331 if (AR_SREV_9300_20_OR_LATER(ah)) {
1332 ath9k_hw_loadnf(ah, curchan);
1333 ath9k_hw_start_nfcal(ah);
1334 }
1335
ae8d2858 1336 return 0;
f078f209 1337}
7322fd19 1338EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1339
f1dc5600
S		 1340/************************/
1341/* Key Cache Management */
1342/************************/
f078f209 1343
cbe61d8a 1344bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
f078f209 1345{
f1dc5600 1346 u32 keyType;
f078f209 1347
2660b81a 1348 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 1349 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1350 "keychache entry %u out of range\n", entry);
f078f209
LR		 1351 return false;
1352 }
1353
f1dc5600 1354 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 1355
f1dc5600
S		 1356 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1357 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1358 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1359 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1360 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1361 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1362 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1363 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 1364
f1dc5600
S		 1365 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1366 u16 micentry = entry + 64;
f078f209 1367
f1dc5600
S		 1368 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1369 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1370 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1371 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 1372
f078f209
LR		 1373 }
1374
f078f209
LR		 1375 return true;
1376}
7322fd19 1377EXPORT_SYMBOL(ath9k_hw_keyreset);
f078f209 1378
cbe61d8a 1379bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
f078f209 1380{
f1dc5600 1381 u32 macHi, macLo;
f078f209 1382
2660b81a 1383 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 1384 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1385 "keychache entry %u out of range\n", entry);
f1dc5600 1386 return false;
f078f209
LR		 1387 }
1388
f1dc5600
S		 1389 if (mac != NULL) {
1390 macHi = (mac[5] << 8) | mac[4];
1391 macLo = (mac[3] << 24) |
1392 (mac[2] << 16) |
1393 (mac[1] << 8) |
1394 mac[0];
1395 macLo >>= 1;
1396 macLo |= (macHi & 1) << 31;
1397 macHi >>= 1;
f078f209 1398 } else {
f1dc5600 1399 macLo = macHi = 0;
f078f209 1400 }
f1dc5600
S		 1401 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1402 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
f078f209 1403
f1dc5600 1404 return true;
f078f209 1405}
7322fd19 1406EXPORT_SYMBOL(ath9k_hw_keysetmac);
f078f209 1407
cbe61d8a 1408bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
f1dc5600 1409 const struct ath9k_keyval *k,
e0caf9ea 1410 const u8 *mac)
f078f209 1411{
2660b81a 1412 const struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1413 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 1414 u32 key0, key1, key2, key3, key4;
1415 u32 keyType;
f078f209 1416
f1dc5600 1417 if (entry >= pCap->keycache_size) {
c46917bb
LR		 1418 ath_print(common, ATH_DBG_FATAL,
1419 "keycache entry %u out of range\n", entry);
f1dc5600 1420 return false;
f078f209
LR		 1421 }
1422
f1dc5600
S		 1423 switch (k->kv_type) {
1424 case ATH9K_CIPHER_AES_OCB:
1425 keyType = AR_KEYTABLE_TYPE_AES;
1426 break;
1427 case ATH9K_CIPHER_AES_CCM:
1428 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
c46917bb
LR		 1429 ath_print(common, ATH_DBG_ANY,
1430 "AES-CCM not supported by mac rev 0x%x\n",
1431 ah->hw_version.macRev);
f1dc5600
S		 1432 return false;
1433 }
1434 keyType = AR_KEYTABLE_TYPE_CCM;
1435 break;
1436 case ATH9K_CIPHER_TKIP:
1437 keyType = AR_KEYTABLE_TYPE_TKIP;
1438 if (ATH9K_IS_MIC_ENABLED(ah)
1439 && entry + 64 >= pCap->keycache_size) {
c46917bb
LR		 1440 ath_print(common, ATH_DBG_ANY,
1441 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 1442 return false;
1443 }
1444 break;
1445 case ATH9K_CIPHER_WEP:
e31a16d6 1446 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
c46917bb
LR		 1447 ath_print(common, ATH_DBG_ANY,
1448 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 1449 return false;
1450 }
e31a16d6 1451 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
f1dc5600 1452 keyType = AR_KEYTABLE_TYPE_40;
e31a16d6 1453 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600
S		 1454 keyType = AR_KEYTABLE_TYPE_104;
1455 else
1456 keyType = AR_KEYTABLE_TYPE_128;
1457 break;
1458 case ATH9K_CIPHER_CLR:
1459 keyType = AR_KEYTABLE_TYPE_CLR;
1460 break;
1461 default:
c46917bb
LR		 1462 ath_print(common, ATH_DBG_FATAL,
1463 "cipher %u not supported\n", k->kv_type);
f1dc5600 1464 return false;
f078f209
LR		 1465 }
1466
e0caf9ea
JM		 1467 key0 = get_unaligned_le32(k->kv_val + 0);
1468 key1 = get_unaligned_le16(k->kv_val + 4);
1469 key2 = get_unaligned_le32(k->kv_val + 6);
1470 key3 = get_unaligned_le16(k->kv_val + 10);
1471 key4 = get_unaligned_le32(k->kv_val + 12);
e31a16d6 1472 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600 1473 key4 &= 0xff;
f078f209 1474
672903b3
JM		 1475 /*
1476 * Note: Key cache registers access special memory area that requires
1477 * two 32-bit writes to actually update the values in the internal
1478 * memory. Consequently, the exact order and pairs used here must be
1479 * maintained.
1480 */
1481
f1dc5600
S		 1482 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1483 u16 micentry = entry + 64;
f078f209 1484
672903b3
JM		 1485 /*
1486 * Write inverted key[47:0] first to avoid Michael MIC errors
1487 * on frames that could be sent or received at the same time.
1488 * The correct key will be written in the end once everything
1489 * else is ready.
1490 */
f1dc5600
S		 1491 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1492 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
672903b3
JM		 1493
1494 /* Write key[95:48] */
f1dc5600
S		 1495 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1496 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 1497
1498 /* Write key[127:96] and key type */
f1dc5600
S		 1499 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1500 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
672903b3
JM		 1501
1502 /* Write MAC address for the entry */
f1dc5600 1503 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 1504
2660b81a 1505 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
672903b3
JM		 1506 /*
1507 * TKIP uses two key cache entries:
1508 * Michael MIC TX/RX keys in the same key cache entry
1509 * (idx = main index + 64):
1510 * key0 [31:0] = RX key [31:0]
1511 * key1 [15:0] = TX key [31:16]
1512 * key1 [31:16] = reserved
1513 * key2 [31:0] = RX key [63:32]
1514 * key3 [15:0] = TX key [15:0]
1515 * key3 [31:16] = reserved
1516 * key4 [31:0] = TX key [63:32]
1517 */
f1dc5600 1518 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 1519
f1dc5600
S		 1520 mic0 = get_unaligned_le32(k->kv_mic + 0);
1521 mic2 = get_unaligned_le32(k->kv_mic + 4);
1522 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1523 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1524 mic4 = get_unaligned_le32(k->kv_txmic + 4);
672903b3
JM		 1525
1526 /* Write RX[31:0] and TX[31:16] */
f1dc5600
S		 1527 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1528 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
672903b3
JM		 1529
1530 /* Write RX[63:32] and TX[15:0] */
f1dc5600
S		 1531 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1532 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
672903b3
JM		 1533
1534 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 1535 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1536 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1537 AR_KEYTABLE_TYPE_CLR);
f078f209 1538
f1dc5600 1539 } else {
672903b3
JM		 1540 /*
1541 * TKIP uses four key cache entries (two for group
1542 * keys):
1543 * Michael MIC TX/RX keys are in different key cache
1544 * entries (idx = main index + 64 for TX and
1545 * main index + 32 + 96 for RX):
1546 * key0 [31:0] = TX/RX MIC key [31:0]
1547 * key1 [31:0] = reserved
1548 * key2 [31:0] = TX/RX MIC key [63:32]
1549 * key3 [31:0] = reserved
1550 * key4 [31:0] = reserved
1551 *
1552 * Upper layer code will call this function separately
1553 * for TX and RX keys when these registers offsets are
1554 * used.
1555 */
f1dc5600 1556 u32 mic0, mic2;
f078f209 1557
f1dc5600
S		 1558 mic0 = get_unaligned_le32(k->kv_mic + 0);
1559 mic2 = get_unaligned_le32(k->kv_mic + 4);
672903b3
JM		 1560
1561 /* Write MIC key[31:0] */
f1dc5600
S		 1562 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1563 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
672903b3
JM		 1564
1565 /* Write MIC key[63:32] */
f1dc5600
S		 1566 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1567 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
672903b3
JM		 1568
1569 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 1570 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1571 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1572 AR_KEYTABLE_TYPE_CLR);
1573 }
672903b3
JM		 1574
1575 /* MAC address registers are reserved for the MIC entry */
f1dc5600
S		 1576 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1577 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
672903b3
JM		 1578
1579 /*
1580 * Write the correct (un-inverted) key[47:0] last to enable
1581 * TKIP now that all other registers are set with correct
1582 * values.
1583 */
f1dc5600
S		 1584 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1585 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1586 } else {
672903b3 1587 /* Write key[47:0] */
f1dc5600
S		 1588 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1589 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
672903b3
JM		 1590
1591 /* Write key[95:48] */
f1dc5600
S		 1592 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1593 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 1594
1595 /* Write key[127:96] and key type */
f1dc5600
S		 1596 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1597 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 1598
672903b3 1599 /* Write MAC address for the entry */
f1dc5600
S		 1600 (void) ath9k_hw_keysetmac(ah, entry, mac);
1601 }
f078f209 1602
f078f209
LR		 1603 return true;
1604}
7322fd19 1605EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
f078f209 1606
cbe61d8a 1607bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
f078f209 1608{
2660b81a 1609 if (entry < ah->caps.keycache_size) {
f1dc5600
S		 1610 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1611 if (val & AR_KEYTABLE_VALID)
1612 return true;
1613 }
1614 return false;
f078f209 1615}
7322fd19 1616EXPORT_SYMBOL(ath9k_hw_keyisvalid);
f078f209 1617
f1dc5600
S		 1618/******************************/
1619/* Power Management (Chipset) */
1620/******************************/
1621
42d5bc3f
LR		 1622/*
1623 * Notify Power Mgt is disabled in self-generated frames.
1624 * If requested, force chip to sleep.
1625 */
cbe61d8a 1626static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 1627{
f1dc5600
S		 1628 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1629 if (setChip) {
42d5bc3f
LR		 1630 /*
1631 * Clear the RTC force wake bit to allow the
1632 * mac to go to sleep.
1633 */
f1dc5600
S		 1634 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1635 AR_RTC_FORCE_WAKE_EN);
42d5bc3f 1636 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1637 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 1638
42d5bc3f 1639 /* Shutdown chip. Active low */
14b3af38 1640 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
4921be80
S		 1641 REG_CLR_BIT(ah, (AR_RTC_RESET),
1642 AR_RTC_RESET_EN);
f1dc5600 1643 }
f078f209
LR		 1644}
1645
bbd79af5
LR		 1646/*
1647 * Notify Power Management is enabled in self-generating
1648 * frames. If request, set power mode of chip to
1649 * auto/normal. Duration in units of 128us (1/8 TU).
1650 */
cbe61d8a 1651static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 1652{
f1dc5600
S		 1653 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1654 if (setChip) {
2660b81a 1655 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 1656
f1dc5600 1657 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
bbd79af5 1658 /* Set WakeOnInterrupt bit; clear ForceWake bit */
f1dc5600
S		 1659 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1660 AR_RTC_FORCE_WAKE_ON_INT);
1661 } else {
bbd79af5
LR		 1662 /*
1663 * Clear the RTC force wake bit to allow the
1664 * mac to go to sleep.
1665 */
f1dc5600
S		 1666 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1667 AR_RTC_FORCE_WAKE_EN);
f078f209 1668 }
f078f209 1669 }
f078f209
LR		 1670}
1671
cbe61d8a 1672static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 1673{
f1dc5600
S		 1674 u32 val;
1675 int i;
f078f209 1676
f1dc5600
S		 1677 if (setChip) {
1678 if ((REG_READ(ah, AR_RTC_STATUS) &
1679 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1680 if (ath9k_hw_set_reset_reg(ah,
1681 ATH9K_RESET_POWER_ON) != true) {
1682 return false;
1683 }
e041228f
LR		 1684 if (!AR_SREV_9300_20_OR_LATER(ah))
1685 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 1686 }
1687 if (AR_SREV_9100(ah))
1688 REG_SET_BIT(ah, AR_RTC_RESET,
1689 AR_RTC_RESET_EN);
f078f209 1690
f1dc5600
S		 1691 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1692 AR_RTC_FORCE_WAKE_EN);
1693 udelay(50);
f078f209 1694
f1dc5600
S		 1695 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1696 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1697 if (val == AR_RTC_STATUS_ON)
1698 break;
1699 udelay(50);
1700 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1701 AR_RTC_FORCE_WAKE_EN);
f078f209 1702 }
f1dc5600 1703 if (i == 0) {
c46917bb
LR		 1704 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1705 "Failed to wakeup in %uus\n",
1706 POWER_UP_TIME / 20);
f1dc5600 1707 return false;
f078f209 1708 }
f078f209
LR		 1709 }
1710
f1dc5600 1711 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 1712
f1dc5600 1713 return true;
f078f209
LR		 1714}
1715
9ecdef4b 1716bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 1717{
c46917bb 1718 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 1719 int status = true, setChip = true;
f1dc5600
S		 1720 static const char *modes[] = {
1721 "AWAKE",
1722 "FULL-SLEEP",
1723 "NETWORK SLEEP",
1724 "UNDEFINED"
1725 };
f1dc5600 1726
cbdec975
GJ		 1727 if (ah->power_mode == mode)
1728 return status;
1729
c46917bb
LR		 1730 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1731 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 1732
1733 switch (mode) {
1734 case ATH9K_PM_AWAKE:
1735 status = ath9k_hw_set_power_awake(ah, setChip);
1736 break;
1737 case ATH9K_PM_FULL_SLEEP:
1738 ath9k_set_power_sleep(ah, setChip);
2660b81a 1739 ah->chip_fullsleep = true;
f1dc5600
S		 1740 break;
1741 case ATH9K_PM_NETWORK_SLEEP:
1742 ath9k_set_power_network_sleep(ah, setChip);
1743 break;
f078f209 1744 default:
c46917bb
LR		 1745 ath_print(common, ATH_DBG_FATAL,
1746 "Unknown power mode %u\n", mode);
f078f209
LR		 1747 return false;
1748 }
2660b81a 1749 ah->power_mode = mode;
f1dc5600
S		 1750
1751 return status;
f078f209 1752}
7322fd19 1753EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 1754
f1dc5600
S		 1755/*******************/
1756/* Beacon Handling */
1757/*******************/
1758
cbe61d8a 1759void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 1760{
f078f209
LR		 1761 int flags = 0;
1762
2660b81a 1763 ah->beacon_interval = beacon_period;
f078f209 1764
2660b81a 1765 switch (ah->opmode) {
d97809db
CM		 1766 case NL80211_IFTYPE_STATION:
1767 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 1768 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1769 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1770 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1771 flags |= AR_TBTT_TIMER_EN;
1772 break;
d97809db 1773 case NL80211_IFTYPE_ADHOC:
9cb5412b 1774 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 1775 REG_SET_BIT(ah, AR_TXCFG,
1776 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1777 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1778 TU_TO_USEC(next_beacon +
2660b81a
S		 1779 (ah->atim_window ? ah->
1780 atim_window : 1)));
f078f209 1781 flags |= AR_NDP_TIMER_EN;
d97809db 1782 case NL80211_IFTYPE_AP:
f078f209
LR		 1783 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1784 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1785 TU_TO_USEC(next_beacon -
2660b81a 1786 ah->config.
60b67f51 1787 dma_beacon_response_time));
f078f209
LR		 1788 REG_WRITE(ah, AR_NEXT_SWBA,
1789 TU_TO_USEC(next_beacon -
2660b81a 1790 ah->config.
60b67f51 1791 sw_beacon_response_time));
f078f209
LR		 1792 flags |=
1793 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1794 break;
d97809db 1795 default:
c46917bb
LR		 1796 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1797 "%s: unsupported opmode: %d\n",
1798 __func__, ah->opmode);
d97809db
CM		 1799 return;
1800 break;
f078f209
LR		 1801 }
1802
1803 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1804 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1805 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1806 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1807
1808 beacon_period &= ~ATH9K_BEACON_ENA;
1809 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
f078f209
LR		 1810 ath9k_hw_reset_tsf(ah);
1811 }
1812
1813 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1814}
7322fd19 1815EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 1816
cbe61d8a 1817void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 1818 const struct ath9k_beacon_state *bs)
f078f209
LR		 1819{
1820 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 1821 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1822 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 1823
1824 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1825
1826 REG_WRITE(ah, AR_BEACON_PERIOD,
1827 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1828 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1829 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1830
1831 REG_RMW_FIELD(ah, AR_RSSI_THR,
1832 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1833
1834 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1835
1836 if (bs->bs_sleepduration > beaconintval)
1837 beaconintval = bs->bs_sleepduration;
1838
1839 dtimperiod = bs->bs_dtimperiod;
1840 if (bs->bs_sleepduration > dtimperiod)
1841 dtimperiod = bs->bs_sleepduration;
1842
1843 if (beaconintval == dtimperiod)
1844 nextTbtt = bs->bs_nextdtim;
1845 else
1846 nextTbtt = bs->bs_nexttbtt;
1847
c46917bb
LR		 1848 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1849 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1850 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1851 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 1852
f1dc5600
S		 1853 REG_WRITE(ah, AR_NEXT_DTIM,
1854 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1855 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 1856
f1dc5600
S		 1857 REG_WRITE(ah, AR_SLEEP1,
1858 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1859 | AR_SLEEP1_ASSUME_DTIM);
f078f209 1860
f1dc5600
S		 1861 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1862 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1863 else
1864 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 1865
f1dc5600
S		 1866 REG_WRITE(ah, AR_SLEEP2,
1867 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 1868
f1dc5600
S		 1869 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1870 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 1871
f1dc5600
S		 1872 REG_SET_BIT(ah, AR_TIMER_MODE,
1873 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1874 AR_DTIM_TIMER_EN);
f078f209 1875
4af9cf4f
S		 1876 /* TSF Out of Range Threshold */
1877 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 1878}
7322fd19 1879EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 1880
f1dc5600
S		 1881/*******************/
1882/* HW Capabilities */
1883/*******************/
1884
a9a29ce6 1885int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 1886{
2660b81a 1887 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 1888 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1889 struct ath_common *common = ath9k_hw_common(ah);
766ec4a9 1890 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
608b88cb 1891
f1dc5600 1892 u16 capField = 0, eeval;
f078f209 1893
f74df6fb 1894 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 1895 regulatory->current_rd = eeval;
f078f209 1896
f74df6fb 1897 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
fec0de11
S		 1898 if (AR_SREV_9285_10_OR_LATER(ah))
1899 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 1900 regulatory->current_rd_ext = eeval;
f078f209 1901
f74df6fb 1902 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 1903
2660b81a 1904 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 1905 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 1906 if (regulatory->current_rd == 0x64 ||
1907 regulatory->current_rd == 0x65)
1908 regulatory->current_rd += 5;
1909 else if (regulatory->current_rd == 0x41)
1910 regulatory->current_rd = 0x43;
c46917bb
LR		 1911 ath_print(common, ATH_DBG_REGULATORY,
1912 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 1913 }
f078f209 1914
f74df6fb 1915 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6
GJ		 1916 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1917 ath_print(common, ATH_DBG_FATAL,
1918 "no band has been marked as supported in EEPROM.\n");
1919 return -EINVAL;
1920 }
1921
f1dc5600 1922 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 1923
f1dc5600
S		 1924 if (eeval & AR5416_OPFLAGS_11A) {
1925 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2660b81a 1926 if (ah->config.ht_enable) {
f1dc5600
S		 1927 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
1928 set_bit(ATH9K_MODE_11NA_HT20,
1929 pCap->wireless_modes);
1930 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
1931 set_bit(ATH9K_MODE_11NA_HT40PLUS,
1932 pCap->wireless_modes);
1933 set_bit(ATH9K_MODE_11NA_HT40MINUS,
1934 pCap->wireless_modes);
1935 }
f078f209 1936 }
f078f209
LR		 1937 }
1938
f1dc5600 1939 if (eeval & AR5416_OPFLAGS_11G) {
f1dc5600 1940 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2660b81a 1941 if (ah->config.ht_enable) {
f1dc5600
S		 1942 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
1943 set_bit(ATH9K_MODE_11NG_HT20,
1944 pCap->wireless_modes);
1945 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
1946 set_bit(ATH9K_MODE_11NG_HT40PLUS,
1947 pCap->wireless_modes);
1948 set_bit(ATH9K_MODE_11NG_HT40MINUS,
1949 pCap->wireless_modes);
1950 }
1951 }
f078f209 1952 }
f1dc5600 1953
f74df6fb 1954 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 1955 /*
1956 * For AR9271 we will temporarilly uses the rx chainmax as read from
1957 * the EEPROM.
1958 */
8147f5de 1959 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 1960 !(eeval & AR5416_OPFLAGS_11A) &&
1961 !(AR_SREV_9271(ah)))
1962 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de
S		 1963 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
1964 else
d7e7d229 1965 /* Use rx_chainmask from EEPROM. */
8147f5de 1966 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 1967
d535a42a 1968 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2660b81a 1969 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 1970
f1dc5600
S		 1971 pCap->low_2ghz_chan = 2312;
1972 pCap->high_2ghz_chan = 2732;
f078f209 1973
f1dc5600
S		 1974 pCap->low_5ghz_chan = 4920;
1975 pCap->high_5ghz_chan = 6100;
f078f209 1976
f1dc5600
S		 1977 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
1978 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
1979 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 1980
f1dc5600
S		 1981 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
1982 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
1983 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 1984
2660b81a 1985 if (ah->config.ht_enable)
f1dc5600
S		 1986 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1987 else
1988 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 1989
f1dc5600
S		 1990 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
1991 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
1992 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
1993 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 1994
f1dc5600
S		 1995 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
1996 pCap->total_queues =
1997 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
1998 else
1999 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 2000
f1dc5600
S		 2001 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2002 pCap->keycache_size =
2003 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2004 else
2005 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 2006
f1dc5600 2007 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
f4709fdf
LR		 2008
2009 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2010 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2011 else
2012 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 2013
5b5fa355
S		 2014 if (AR_SREV_9271(ah))
2015 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2016 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 2017 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2018 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 2019 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2020 else
2021 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2022
f1dc5600
S		 2023 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2024 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2025 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2026 } else {
2027 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 2028 }
2029
f1dc5600
S		 2030 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2031
e97275cb 2032#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 2033 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2034 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2035 ah->rfkill_gpio =
2036 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2037 ah->rfkill_polarity =
2038 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2039
2040 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2041 }
f1dc5600 2042#endif
bde748a4
VN		 2043 if (AR_SREV_9271(ah))
2044 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2045 else
2046 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2047
e7594072 2048 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2049 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2050 else
2051 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2052
608b88cb 2053 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 2054 pCap->reg_cap =
2055 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2056 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2057 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2058 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 2059 } else {
f1dc5600
S		 2060 pCap->reg_cap =
2061 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2062 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 2063 }
f078f209 2064
ebb90cfc
SB		 2065 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2066 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2067 AR_SREV_5416(ah))
2068 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
f1dc5600
S		 2069
2070 pCap->num_antcfg_5ghz =
f74df6fb 2071 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 2072 pCap->num_antcfg_2ghz =
f74df6fb 2073 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 2074
fe12946e 2075 if (AR_SREV_9280_10_OR_LATER(ah) &&
a36cfbca 2076 ath9k_hw_btcoex_supported(ah)) {
766ec4a9
LR		 2077 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2078 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
22f25d0d 2079
8c8f9ba7 2080 if (AR_SREV_9285(ah)) {
766ec4a9
LR		 2081 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2082 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
8c8f9ba7 2083 } else {
766ec4a9 2084 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
8c8f9ba7 2085 }
22f25d0d 2086 } else {
766ec4a9 2087 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 2088 }
a9a29ce6 2089
ceb26445 2090 if (AR_SREV_9300_20_OR_LATER(ah)) {
1adf02ff 2091 pCap->hw_caps |= ATH9K_HW_CAP_EDMA;
ceb26445
VT		 2092 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2093 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2094 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3
VT		 2095 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2096 } else {
2097 pCap->tx_desc_len = sizeof(struct ath_desc);
ceb26445 2098 }
1adf02ff 2099
6c84ce08
VT		 2100 if (AR_SREV_9300_20_OR_LATER(ah))
2101 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2102
a9a29ce6 2103 return 0;
f078f209
LR		 2104}
2105
cbe61d8a 2106bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 2107 u32 capability, u32 *result)
f078f209 2108{
608b88cb 2109 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f1dc5600
S		 2110 switch (type) {
2111 case ATH9K_CAP_CIPHER:
2112 switch (capability) {
2113 case ATH9K_CIPHER_AES_CCM:
2114 case ATH9K_CIPHER_AES_OCB:
2115 case ATH9K_CIPHER_TKIP:
2116 case ATH9K_CIPHER_WEP:
2117 case ATH9K_CIPHER_MIC:
2118 case ATH9K_CIPHER_CLR:
2119 return true;
2120 default:
2121 return false;
2122 }
2123 case ATH9K_CAP_TKIP_MIC:
2124 switch (capability) {
2125 case 0:
2126 return true;
2127 case 1:
2660b81a 2128 return (ah->sta_id1_defaults &
f1dc5600
S		 2129 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2130 false;
2131 }
2132 case ATH9K_CAP_TKIP_SPLIT:
2660b81a 2133 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
f1dc5600 2134 false : true;
f1dc5600
S		 2135 case ATH9K_CAP_MCAST_KEYSRCH:
2136 switch (capability) {
2137 case 0:
2138 return true;
2139 case 1:
2140 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2141 return false;
2142 } else {
2660b81a 2143 return (ah->sta_id1_defaults &
f1dc5600
S		 2144 AR_STA_ID1_MCAST_KSRCH) ? true :
2145 false;
2146 }
2147 }
2148 return false;
f1dc5600
S		 2149 case ATH9K_CAP_TXPOW:
2150 switch (capability) {
2151 case 0:
2152 return 0;
2153 case 1:
608b88cb 2154 *result = regulatory->power_limit;
f1dc5600
S		 2155 return 0;
2156 case 2:
608b88cb 2157 *result = regulatory->max_power_level;
f1dc5600
S		 2158 return 0;
2159 case 3:
608b88cb 2160 *result = regulatory->tp_scale;
f1dc5600
S		 2161 return 0;
2162 }
2163 return false;
8bd1d07f
SB		 2164 case ATH9K_CAP_DS:
2165 return (AR_SREV_9280_20_OR_LATER(ah) &&
2166 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2167 ? false : true;
f1dc5600
S		 2168 default:
2169 return false;
f078f209 2170 }
f078f209 2171}
7322fd19 2172EXPORT_SYMBOL(ath9k_hw_getcapability);
f078f209 2173
cbe61d8a 2174bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 2175 u32 capability, u32 setting, int *status)
f078f209 2176{
f1dc5600
S		 2177 switch (type) {
2178 case ATH9K_CAP_TKIP_MIC:
2179 if (setting)
2660b81a 2180 ah->sta_id1_defaults |=
f1dc5600
S		 2181 AR_STA_ID1_CRPT_MIC_ENABLE;
2182 else
2660b81a 2183 ah->sta_id1_defaults &=
f1dc5600
S		 2184 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2185 return true;
f1dc5600
S		 2186 case ATH9K_CAP_MCAST_KEYSRCH:
2187 if (setting)
2660b81a 2188 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
f1dc5600 2189 else
2660b81a 2190 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
f1dc5600 2191 return true;
f1dc5600
S		 2192 default:
2193 return false;
f078f209
LR		 2194 }
2195}
7322fd19 2196EXPORT_SYMBOL(ath9k_hw_setcapability);
f078f209 2197
f1dc5600
S		 2198/****************************/
2199/* GPIO / RFKILL / Antennae */
2200/****************************/
f078f209 2201
cbe61d8a 2202static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2203 u32 gpio, u32 type)
2204{
2205 int addr;
2206 u32 gpio_shift, tmp;
f078f209 2207
f1dc5600
S		 2208 if (gpio > 11)
2209 addr = AR_GPIO_OUTPUT_MUX3;
2210 else if (gpio > 5)
2211 addr = AR_GPIO_OUTPUT_MUX2;
2212 else
2213 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2214
f1dc5600 2215 gpio_shift = (gpio % 6) * 5;
f078f209 2216
f1dc5600
S		 2217 if (AR_SREV_9280_20_OR_LATER(ah)
2218 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2219 REG_RMW(ah, addr, (type << gpio_shift),
2220 (0x1f << gpio_shift));
f078f209 2221 } else {
f1dc5600
S		 2222 tmp = REG_READ(ah, addr);
2223 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2224 tmp &= ~(0x1f << gpio_shift);
2225 tmp |= (type << gpio_shift);
2226 REG_WRITE(ah, addr, tmp);
f078f209 2227 }
f078f209
LR		 2228}
2229
cbe61d8a 2230void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2231{
f1dc5600 2232 u32 gpio_shift;
f078f209 2233
9680e8a3 2234 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2235
f1dc5600 2236 gpio_shift = gpio << 1;
f078f209 2237
f1dc5600
S		 2238 REG_RMW(ah,
2239 AR_GPIO_OE_OUT,
2240 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2241 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2242}
7322fd19 2243EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2244
cbe61d8a 2245u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2246{
cb33c412
SB		 2247#define MS_REG_READ(x, y) \
2248 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2249
2660b81a 2250 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2251 return 0xffffffff;
f078f209 2252
783dfca1
FF		 2253 if (AR_SREV_9300_20_OR_LATER(ah))
2254 return MS_REG_READ(AR9300, gpio) != 0;
2255 else if (AR_SREV_9271(ah))
5b5fa355
S		 2256 return MS_REG_READ(AR9271, gpio) != 0;
2257 else if (AR_SREV_9287_10_OR_LATER(ah))
ac88b6ec
VN		 2258 return MS_REG_READ(AR9287, gpio) != 0;
2259 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 2260 return MS_REG_READ(AR9285, gpio) != 0;
2261 else if (AR_SREV_9280_10_OR_LATER(ah))
2262 return MS_REG_READ(AR928X, gpio) != 0;
2263 else
2264 return MS_REG_READ(AR, gpio) != 0;
f078f209 2265}
7322fd19 2266EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2267
cbe61d8a 2268void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2269 u32 ah_signal_type)
f078f209 2270{
f1dc5600 2271 u32 gpio_shift;
f078f209 2272
f1dc5600 2273 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 2274
f1dc5600 2275 gpio_shift = 2 * gpio;
f078f209 2276
f1dc5600
S		 2277 REG_RMW(ah,
2278 AR_GPIO_OE_OUT,
2279 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2280 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2281}
7322fd19 2282EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2283
cbe61d8a 2284void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2285{
5b5fa355
S		 2286 if (AR_SREV_9271(ah))
2287 val = ~val;
2288
f1dc5600
S		 2289 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2290 AR_GPIO_BIT(gpio));
f078f209 2291}
7322fd19 2292EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2293
cbe61d8a 2294u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 2295{
f1dc5600 2296 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209 2297}
7322fd19 2298EXPORT_SYMBOL(ath9k_hw_getdefantenna);
f078f209 2299
cbe61d8a 2300void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2301{
f1dc5600 2302 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2303}
7322fd19 2304EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2305
f1dc5600
S		 2306/*********************/
2307/* General Operation */
2308/*********************/
2309
cbe61d8a 2310u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2311{
f1dc5600
S		 2312 u32 bits = REG_READ(ah, AR_RX_FILTER);
2313 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2314
f1dc5600
S		 2315 if (phybits & AR_PHY_ERR_RADAR)
2316 bits |= ATH9K_RX_FILTER_PHYRADAR;
2317 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2318 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2319
f1dc5600 2320 return bits;
f078f209 2321}
7322fd19 2322EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2323
cbe61d8a 2324void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2325{
f1dc5600 2326 u32 phybits;
f078f209 2327
7ea310be
S		 2328 REG_WRITE(ah, AR_RX_FILTER, bits);
2329
f1dc5600
S		 2330 phybits = 0;
2331 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2332 phybits |= AR_PHY_ERR_RADAR;
2333 if (bits & ATH9K_RX_FILTER_PHYERR)
2334 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2335 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2336
f1dc5600
S		 2337 if (phybits)
2338 REG_WRITE(ah, AR_RXCFG,
2339 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2340 else
2341 REG_WRITE(ah, AR_RXCFG,
2342 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2343}
7322fd19 2344EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2345
cbe61d8a 2346bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2347{
63a75b91
SB		 2348 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2349 return false;
2350
2351 ath9k_hw_init_pll(ah, NULL);
2352 return true;
f1dc5600 2353}
7322fd19 2354EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2355
cbe61d8a 2356bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2357{
9ecdef4b 2358 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2359 return false;
f078f209 2360
63a75b91
SB		 2361 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2362 return false;
2363
2364 ath9k_hw_init_pll(ah, NULL);
2365 return true;
f078f209 2366}
7322fd19 2367EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2368
8fbff4b8 2369void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 2370{
608b88cb 2371 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 2372 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2373 struct ieee80211_channel *channel = chan->chan;
f078f209 2374
608b88cb 2375 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 2376
8fbff4b8 2377 ah->eep_ops->set_txpower(ah, chan,
608b88cb 2378 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 2379 channel->max_antenna_gain * 2,
2380 channel->max_power * 2,
2381 min((u32) MAX_RATE_POWER,
608b88cb 2382 (u32) regulatory->power_limit));
6f255425 2383}
7322fd19 2384EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2385
cbe61d8a 2386void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
f078f209 2387{
1510718d 2388 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
f078f209 2389}
7322fd19 2390EXPORT_SYMBOL(ath9k_hw_setmac);
f078f209 2391
cbe61d8a 2392void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2393{
2660b81a 2394 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2395}
7322fd19 2396EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2397
cbe61d8a 2398void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2399{
f1dc5600
S		 2400 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2401 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2402}
7322fd19 2403EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2404
f2b2143e 2405void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2406{
1510718d
LR		 2407 struct ath_common *common = ath9k_hw_common(ah);
2408
2409 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2410 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2411 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2412}
7322fd19 2413EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2414
cbe61d8a 2415u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2416{
f1dc5600 2417 u64 tsf;
f078f209 2418
f1dc5600
S		 2419 tsf = REG_READ(ah, AR_TSF_U32);
2420 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
f078f209 2421
f1dc5600
S		 2422 return tsf;
2423}
7322fd19 2424EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2425
cbe61d8a 2426void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2427{
27abe060 2428 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2429 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2430}
7322fd19 2431EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2432
cbe61d8a 2433void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2434{
f9b604f6
GJ		 2435 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2436 AH_TSF_WRITE_TIMEOUT))
c46917bb
LR		 2437 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2438 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2439
f1dc5600
S		 2440 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2441}
7322fd19 2442EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2443
54e4cec6 2444void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 2445{
f1dc5600 2446 if (setting)
2660b81a 2447 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2448 else
2660b81a 2449 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2450}
7322fd19 2451EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2452
30cbd422
LR		 2453/*
2454 * Extend 15-bit time stamp from rx descriptor to
2455 * a full 64-bit TSF using the current h/w TSF.
2456*/
2457u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2458{
2459 u64 tsf;
2460
2461 tsf = ath9k_hw_gettsf64(ah);
2462 if ((tsf & 0x7fff) < rstamp)
2463 tsf -= 0x8000;
2464 return (tsf & ~0x7fff) | rstamp;
2465}
2466EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2467
25c56eec 2468void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2469{
25c56eec 2470 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2471 u32 macmode;
2472
25c56eec 2473 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2474 macmode = AR_2040_JOINED_RX_CLEAR;
2475 else
2476 macmode = 0;
f078f209 2477
f1dc5600 2478 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2479}
ff155a45
VT		 2480
2481/* HW Generic timers configuration */
2482
2483static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2484{
2485 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2486 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2487 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2488 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2489 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2490 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2491 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2492 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2493 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2494 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2495 AR_NDP2_TIMER_MODE, 0x0002},
2496 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2497 AR_NDP2_TIMER_MODE, 0x0004},
2498 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2499 AR_NDP2_TIMER_MODE, 0x0008},
2500 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2501 AR_NDP2_TIMER_MODE, 0x0010},
2502 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2503 AR_NDP2_TIMER_MODE, 0x0020},
2504 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2505 AR_NDP2_TIMER_MODE, 0x0040},
2506 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2507 AR_NDP2_TIMER_MODE, 0x0080}
2508};
2509
2510/* HW generic timer primitives */
2511
2512/* compute and clear index of rightmost 1 */
2513static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2514{
2515 u32 b;
2516
2517 b = *mask;
2518 b &= (0-b);
2519 *mask &= ~b;
2520 b *= debruijn32;
2521 b >>= 27;
2522
2523 return timer_table->gen_timer_index[b];
2524}
2525
1773912b 2526u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2527{
2528 return REG_READ(ah, AR_TSF_L32);
2529}
7322fd19 2530EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2531
2532struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2533 void (*trigger)(void *),
2534 void (*overflow)(void *),
2535 void *arg,
2536 u8 timer_index)
2537{
2538 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2539 struct ath_gen_timer *timer;
2540
2541 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2542
2543 if (timer == NULL) {
c46917bb
LR		 2544 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2545 "Failed to allocate memory"
2546 "for hw timer[%d]\n", timer_index);
ff155a45
VT		 2547 return NULL;
2548 }
2549
2550 /* allocate a hardware generic timer slot */
2551 timer_table->timers[timer_index] = timer;
2552 timer->index = timer_index;
2553 timer->trigger = trigger;
2554 timer->overflow = overflow;
2555 timer->arg = arg;
2556
2557 return timer;
2558}
7322fd19 2559EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2560
cd9bf689
LR		 2561void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2562 struct ath_gen_timer *timer,
2563 u32 timer_next,
2564 u32 timer_period)
ff155a45
VT		 2565{
2566 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2567 u32 tsf;
2568
2569 BUG_ON(!timer_period);
2570
2571 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2572
2573 tsf = ath9k_hw_gettsf32(ah);
2574
c46917bb
LR		 2575 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2576 "curent tsf %x period %x"
2577 "timer_next %x\n", tsf, timer_period, timer_next);
ff155a45
VT		 2578
2579 /*
2580 * Pull timer_next forward if the current TSF already passed it
2581 * because of software latency
2582 */
2583 if (timer_next < tsf)
2584 timer_next = tsf + timer_period;
2585
2586 /*
2587 * Program generic timer registers
2588 */
2589 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2590 timer_next);
2591 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2592 timer_period);
2593 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2594 gen_tmr_configuration[timer->index].mode_mask);
2595
2596 /* Enable both trigger and thresh interrupt masks */
2597 REG_SET_BIT(ah, AR_IMR_S5,
2598 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2599 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 2600}
7322fd19 2601EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 2602
cd9bf689 2603void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 2604{
2605 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2606
2607 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2608 (timer->index >= ATH_MAX_GEN_TIMER)) {
2609 return;
2610 }
2611
2612 /* Clear generic timer enable bits. */
2613 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2614 gen_tmr_configuration[timer->index].mode_mask);
2615
2616 /* Disable both trigger and thresh interrupt masks */
2617 REG_CLR_BIT(ah, AR_IMR_S5,
2618 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2619 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2620
2621 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 2622}
7322fd19 2623EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 2624
2625void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2626{
2627 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2628
2629 /* free the hardware generic timer slot */
2630 timer_table->timers[timer->index] = NULL;
2631 kfree(timer);
2632}
7322fd19 2633EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 2634
2635/*
2636 * Generic Timer Interrupts handling
2637 */
2638void ath_gen_timer_isr(struct ath_hw *ah)
2639{
2640 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2641 struct ath_gen_timer *timer;
c46917bb 2642 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 2643 u32 trigger_mask, thresh_mask, index;
2644
2645 /* get hardware generic timer interrupt status */
2646 trigger_mask = ah->intr_gen_timer_trigger;
2647 thresh_mask = ah->intr_gen_timer_thresh;
2648 trigger_mask &= timer_table->timer_mask.val;
2649 thresh_mask &= timer_table->timer_mask.val;
2650
2651 trigger_mask &= ~thresh_mask;
2652
2653 while (thresh_mask) {
2654 index = rightmost_index(timer_table, &thresh_mask);
2655 timer = timer_table->timers[index];
2656 BUG_ON(!timer);
c46917bb
LR		 2657 ath_print(common, ATH_DBG_HWTIMER,
2658 "TSF overflow for Gen timer %d\n", index);
ff155a45
VT		 2659 timer->overflow(timer->arg);
2660 }
2661
2662 while (trigger_mask) {
2663 index = rightmost_index(timer_table, &trigger_mask);
2664 timer = timer_table->timers[index];
2665 BUG_ON(!timer);
c46917bb
LR		 2666 ath_print(common, ATH_DBG_HWTIMER,
2667 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 2668 timer->trigger(timer->arg);
2669 }
2670}
7322fd19 2671EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 2672
05020d23
S		 2673/********/
2674/* HTC */
2675/********/
2676
2677void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2678{
2679 ah->htc_reset_init = true;
2680}
2681EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2682
2da4f01a
LR		 2683static struct {
2684 u32 version;
2685 const char * name;
2686} ath_mac_bb_names[] = {
2687 /* Devices with external radios */
2688 { AR_SREV_VERSION_5416_PCI, "5416" },
2689 { AR_SREV_VERSION_5416_PCIE, "5418" },
2690 { AR_SREV_VERSION_9100, "9100" },
2691 { AR_SREV_VERSION_9160, "9160" },
2692 /* Single-chip solutions */
2693 { AR_SREV_VERSION_9280, "9280" },
2694 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 2695 { AR_SREV_VERSION_9287, "9287" },
2696 { AR_SREV_VERSION_9271, "9271" },
ec83903e 2697 { AR_SREV_VERSION_9300, "9300" },
2da4f01a
LR		 2698};
2699
2700/* For devices with external radios */
2701static struct {
2702 u16 version;
2703 const char * name;
2704} ath_rf_names[] = {
2705 { 0, "5133" },
2706 { AR_RAD5133_SREV_MAJOR, "5133" },
2707 { AR_RAD5122_SREV_MAJOR, "5122" },
2708 { AR_RAD2133_SREV_MAJOR, "2133" },
2709 { AR_RAD2122_SREV_MAJOR, "2122" }
2710};
2711
2712/*
2713 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2714 */
f934c4d9 2715static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 2716{
2717 int i;
2718
2719 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2720 if (ath_mac_bb_names[i].version == mac_bb_version) {
2721 return ath_mac_bb_names[i].name;
2722 }
2723 }
2724
2725 return "????";
2726}
2da4f01a
LR		 2727
2728/*
2729 * Return the RF name. "????" is returned if the RF is unknown.
2730 * Used for devices with external radios.
2731 */
f934c4d9 2732static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 2733{
2734 int i;
2735
2736 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2737 if (ath_rf_names[i].version == rf_version) {
2738 return ath_rf_names[i].name;
2739 }
2740 }
2741
2742 return "????";
2743}
f934c4d9
LR		 2744
2745void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2746{
2747 int used;
2748
2749 /* chipsets >= AR9280 are single-chip */
2750 if (AR_SREV_9280_10_OR_LATER(ah)) {
2751 used = snprintf(hw_name, len,
2752 "Atheros AR%s Rev:%x",
2753 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2754 ah->hw_version.macRev);
2755 }
2756 else {
2757 used = snprintf(hw_name, len,
2758 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2759 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2760 ah->hw_version.macRev,
2761 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2762 AR_RADIO_SREV_MAJOR)),
2763 ah->hw_version.phyRev);
2764 }
2765
2766 hw_name[used] = '\0';
2767}
2768EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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