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ath9k: move ath9k_hw_setpower() to main.c
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
7b6840ab 19#include <linux/pci.h>
f078f209 20
af03abec 21#include "hw.h"
394cf0a1 22#include "ath9k.h"
f078f209
LR		 23#include "initvals.h"
24
4febf7b8
LR		 25#define ATH9K_CLOCK_RATE_CCK 22
26#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
27#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
f078f209 28
cbe61d8a
S		 29static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
30static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
f1dc5600 31 enum ath9k_ht_macmode macmode);
cbe61d8a 32static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072 33 struct ar5416_eeprom_def *pEepData,
f1dc5600 34 u32 reg, u32 value);
cbe61d8a
S		 35static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
36static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
f078f209 37
f1dc5600
S		 38/********************/
39/* Helper Functions */
40/********************/
f078f209 41
cbe61d8a 42static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
f1dc5600 43{
4febf7b8 44 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
cbe61d8a 45
2660b81a 46 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 47 return clks / ATH9K_CLOCK_RATE_CCK;
48 if (conf->channel->band == IEEE80211_BAND_2GHZ)
49 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
cbe61d8a 50
4febf7b8 51 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600 52}
f078f209 53
cbe61d8a 54static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
f1dc5600 55{
4febf7b8 56 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
cbe61d8a 57
4febf7b8 58 if (conf_is_ht40(conf))
f1dc5600
S		 59 return ath9k_hw_mac_usec(ah, clks) / 2;
60 else
61 return ath9k_hw_mac_usec(ah, clks);
62}
f078f209 63
cbe61d8a 64static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 65{
4febf7b8 66 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
cbe61d8a 67
2660b81a 68 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 69 return usecs *ATH9K_CLOCK_RATE_CCK;
70 if (conf->channel->band == IEEE80211_BAND_2GHZ)
71 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
72 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 73}
74
cbe61d8a 75static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 76{
4febf7b8 77 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
cbe61d8a 78
4febf7b8 79 if (conf_is_ht40(conf))
f1dc5600
S		 80 return ath9k_hw_mac_clks(ah, usecs) * 2;
81 else
82 return ath9k_hw_mac_clks(ah, usecs);
83}
f078f209 84
fb4a3d35
GJ		 85/*
86 * Read and write, they both share the same lock. We do this to serialize
87 * reads and writes on Atheros 802.11n PCI devices only. This is required
88 * as the FIFO on these devices can only accept sanely 2 requests. After
89 * that the device goes bananas. Serializing the reads/writes prevents this
90 * from happening.
91 */
92
93void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
94{
95 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
96 unsigned long flags;
97 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
98 iowrite32(val, ah->ah_sc->mem + reg_offset);
99 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
100 } else
101 iowrite32(val, ah->ah_sc->mem + reg_offset);
102}
103
104unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
105{
106 u32 val;
107 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
108 unsigned long flags;
109 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
110 val = ioread32(ah->ah_sc->mem + reg_offset);
111 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
112 } else
113 val = ioread32(ah->ah_sc->mem + reg_offset);
114 return val;
115}
116
0caa7b14 117bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 118{
119 int i;
120
0caa7b14
S		 121 BUG_ON(timeout < AH_TIME_QUANTUM);
122
123 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 124 if ((REG_READ(ah, reg) & mask) == val)
125 return true;
126
127 udelay(AH_TIME_QUANTUM);
128 }
04bd4638 129
4d6b228d 130 DPRINTF(ah, ATH_DBG_ANY,
0caa7b14
S		 131 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
132 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 133
f1dc5600 134 return false;
f078f209
LR		 135}
136
137u32 ath9k_hw_reverse_bits(u32 val, u32 n)
138{
139 u32 retval;
140 int i;
141
142 for (i = 0, retval = 0; i < n; i++) {
143 retval = (retval << 1) | (val & 1);
144 val >>= 1;
145 }
146 return retval;
147}
148
cbe61d8a 149bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 150 u16 flags, u16 *low,
151 u16 *high)
f078f209 152{
2660b81a 153 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 154
f1dc5600
S		 155 if (flags & CHANNEL_5GHZ) {
156 *low = pCap->low_5ghz_chan;
157 *high = pCap->high_5ghz_chan;
158 return true;
f078f209 159 }
f1dc5600
S		 160 if ((flags & CHANNEL_2GHZ)) {
161 *low = pCap->low_2ghz_chan;
162 *high = pCap->high_2ghz_chan;
163 return true;
164 }
165 return false;
f078f209
LR		 166}
167
cbe61d8a 168u16 ath9k_hw_computetxtime(struct ath_hw *ah,
4f0fc7c3 169 const struct ath_rate_table *rates,
f1dc5600
S		 170 u32 frameLen, u16 rateix,
171 bool shortPreamble)
f078f209 172{
f1dc5600
S		 173 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
174 u32 kbps;
f078f209 175
e63835b0 176 kbps = rates->info[rateix].ratekbps;
f078f209 177
f1dc5600
S		 178 if (kbps == 0)
179 return 0;
f078f209 180
f1dc5600 181 switch (rates->info[rateix].phy) {
46d14a58 182 case WLAN_RC_PHY_CCK:
f1dc5600 183 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
e63835b0 184 if (shortPreamble && rates->info[rateix].short_preamble)
f1dc5600
S		 185 phyTime >>= 1;
186 numBits = frameLen << 3;
187 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
188 break;
46d14a58 189 case WLAN_RC_PHY_OFDM:
2660b81a 190 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 191 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
192 numBits = OFDM_PLCP_BITS + (frameLen << 3);
193 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
194 txTime = OFDM_SIFS_TIME_QUARTER
195 + OFDM_PREAMBLE_TIME_QUARTER
196 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 197 } else if (ah->curchan &&
198 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 199 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
200 numBits = OFDM_PLCP_BITS + (frameLen << 3);
201 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
202 txTime = OFDM_SIFS_TIME_HALF +
203 OFDM_PREAMBLE_TIME_HALF
204 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
205 } else {
206 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
207 numBits = OFDM_PLCP_BITS + (frameLen << 3);
208 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
209 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
210 + (numSymbols * OFDM_SYMBOL_TIME);
211 }
212 break;
213 default:
4d6b228d 214 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 215 "Unknown phy %u (rate ix %u)\n",
f1dc5600
S		 216 rates->info[rateix].phy, rateix);
217 txTime = 0;
218 break;
219 }
f078f209 220
f1dc5600
S		 221 return txTime;
222}
f078f209 223
cbe61d8a 224void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 225 struct ath9k_channel *chan,
226 struct chan_centers *centers)
f078f209 227{
f1dc5600 228 int8_t extoff;
f078f209 229
f1dc5600
S		 230 if (!IS_CHAN_HT40(chan)) {
231 centers->ctl_center = centers->ext_center =
232 centers->synth_center = chan->channel;
233 return;
f078f209 234 }
f078f209 235
f1dc5600
S		 236 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
237 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
238 centers->synth_center =
239 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
240 extoff = 1;
241 } else {
242 centers->synth_center =
243 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
244 extoff = -1;
245 }
f078f209 246
f1dc5600
S		 247 centers->ctl_center =
248 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
249 centers->ext_center =
250 centers->synth_center + (extoff *
2660b81a 251 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
f1dc5600 252 HT40_CHANNEL_CENTER_SHIFT : 15));
f078f209
LR		 253}
254
f1dc5600
S		 255/******************/
256/* Chip Revisions */
257/******************/
258
cbe61d8a 259static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 260{
f1dc5600 261 u32 val;
f078f209 262
f1dc5600 263 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 264
f1dc5600
S		 265 if (val == 0xFF) {
266 val = REG_READ(ah, AR_SREV);
d535a42a
S		 267 ah->hw_version.macVersion =
268 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
269 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 270 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 271 } else {
272 if (!AR_SREV_9100(ah))
d535a42a 273 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 274
d535a42a 275 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 276
d535a42a 277 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 278 ah->is_pciexpress = true;
f1dc5600 279 }
f078f209
LR		 280}
281
cbe61d8a 282static int ath9k_hw_get_radiorev(struct ath_hw *ah)
f078f209 283{
f1dc5600
S		 284 u32 val;
285 int i;
f078f209 286
f1dc5600 287 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
f078f209 288
f1dc5600
S		 289 for (i = 0; i < 8; i++)
290 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
291 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
292 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
f078f209 293
f1dc5600 294 return ath9k_hw_reverse_bits(val, 8);
f078f209
LR		 295}
296
f1dc5600
S		 297/************************************/
298/* HW Attach, Detach, Init Routines */
299/************************************/
300
cbe61d8a 301static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 302{
feed029c 303 if (AR_SREV_9100(ah))
f1dc5600 304 return;
f078f209 305
f1dc5600
S		 306 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
307 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
308 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
309 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
310 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
311 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
312 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
313 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 315
f1dc5600 316 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 317}
318
cbe61d8a 319static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 320{
f1dc5600
S		 321 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
322 u32 regHold[2];
323 u32 patternData[4] = { 0x55555555,
324 0xaaaaaaaa,
325 0x66666666,
326 0x99999999 };
327 int i, j;
f078f209 328
f1dc5600
S		 329 for (i = 0; i < 2; i++) {
330 u32 addr = regAddr[i];
331 u32 wrData, rdData;
f078f209 332
f1dc5600
S		 333 regHold[i] = REG_READ(ah, addr);
334 for (j = 0; j < 0x100; j++) {
335 wrData = (j << 16) | j;
336 REG_WRITE(ah, addr, wrData);
337 rdData = REG_READ(ah, addr);
338 if (rdData != wrData) {
4d6b228d 339 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 340 "address test failed "
f1dc5600 341 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
04bd4638 342 addr, wrData, rdData);
f1dc5600
S		 343 return false;
344 }
345 }
346 for (j = 0; j < 4; j++) {
347 wrData = patternData[j];
348 REG_WRITE(ah, addr, wrData);
349 rdData = REG_READ(ah, addr);
350 if (wrData != rdData) {
4d6b228d 351 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 352 "address test failed "
f1dc5600 353 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
04bd4638 354 addr, wrData, rdData);
f1dc5600
S		 355 return false;
356 }
f078f209 357 }
f1dc5600 358 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 359 }
f1dc5600 360 udelay(100);
cbe61d8a 361
f078f209
LR		 362 return true;
363}
364
f1dc5600 365static const char *ath9k_hw_devname(u16 devid)
f078f209 366{
f1dc5600
S		 367 switch (devid) {
368 case AR5416_DEVID_PCI:
f1dc5600 369 return "Atheros 5416";
392dff83
BP		 370 case AR5416_DEVID_PCIE:
371 return "Atheros 5418";
f1dc5600
S		 372 case AR9160_DEVID_PCI:
373 return "Atheros 9160";
0c1aa495
GJ		 374 case AR5416_AR9100_DEVID:
375 return "Atheros 9100";
f1dc5600
S		 376 case AR9280_DEVID_PCI:
377 case AR9280_DEVID_PCIE:
378 return "Atheros 9280";
e7594072
SB		 379 case AR9285_DEVID_PCIE:
380 return "Atheros 9285";
ac88b6ec
VN		 381 case AR5416_DEVID_AR9287_PCI:
382 case AR5416_DEVID_AR9287_PCIE:
383 return "Atheros 9287";
f078f209
LR		 384 }
385
f1dc5600
S		 386 return NULL;
387}
f078f209 388
b8b0f377 389static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 390{
391 int i;
f078f209 392
2660b81a
S		 393 ah->config.dma_beacon_response_time = 2;
394 ah->config.sw_beacon_response_time = 10;
395 ah->config.additional_swba_backoff = 0;
396 ah->config.ack_6mb = 0x0;
397 ah->config.cwm_ignore_extcca = 0;
398 ah->config.pcie_powersave_enable = 0;
2660b81a 399 ah->config.pcie_clock_req = 0;
2660b81a
S		 400 ah->config.pcie_waen = 0;
401 ah->config.analog_shiftreg = 1;
402 ah->config.ht_enable = 1;
403 ah->config.ofdm_trig_low = 200;
404 ah->config.ofdm_trig_high = 500;
405 ah->config.cck_trig_high = 200;
406 ah->config.cck_trig_low = 100;
407 ah->config.enable_ani = 1;
1cf6873a 408 ah->config.diversity_control = ATH9K_ANT_VARIABLE;
2660b81a 409 ah->config.antenna_switch_swap = 0;
f078f209 410
f1dc5600 411 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 412 ah->config.spurchans[i][0] = AR_NO_SPUR;
413 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 414 }
415
0ef1f168 416 ah->config.intr_mitigation = true;
6158425b
LR		 417
418 /*
419 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
420 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
421 * This means we use it for all AR5416 devices, and the few
422 * minor PCI AR9280 devices out there.
423 *
424 * Serialization is required because these devices do not handle
425 * well the case of two concurrent reads/writes due to the latency
426 * involved. During one read/write another read/write can be issued
427 * on another CPU while the previous read/write may still be working
428 * on our hardware, if we hit this case the hardware poops in a loop.
429 * We prevent this by serializing reads and writes.
430 *
431 * This issue is not present on PCI-Express devices or pre-AR5416
432 * devices (legacy, 802.11abg).
433 */
434 if (num_possible_cpus() > 1)
2d6a5e95 435 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 436}
437
50aca25b 438static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 439{
608b88cb
LR		 440 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
441
442 regulatory->country_code = CTRY_DEFAULT;
443 regulatory->power_limit = MAX_RATE_POWER;
444 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
445
d535a42a 446 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 447 ah->hw_version.subvendorid = 0;
f078f209
LR		 448
449 ah->ah_flags = 0;
8df5d1b7 450 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
d535a42a 451 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
f078f209
LR		 452 if (!AR_SREV_9100(ah))
453 ah->ah_flags = AH_USE_EEPROM;
454
2660b81a 455 ah->atim_window = 0;
2660b81a
S		 456 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
457 ah->beacon_interval = 100;
458 ah->enable_32kHz_clock = DONT_USE_32KHZ;
459 ah->slottime = (u32) -1;
460 ah->acktimeout = (u32) -1;
461 ah->ctstimeout = (u32) -1;
462 ah->globaltxtimeout = (u32) -1;
463
464 ah->gbeacon_rate = 0;
f078f209 465
cbdec975 466 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 467}
468
cbe61d8a 469static int ath9k_hw_rfattach(struct ath_hw *ah)
f078f209 470{
f1dc5600
S		 471 bool rfStatus = false;
472 int ecode = 0;
f078f209 473
f1dc5600
S		 474 rfStatus = ath9k_hw_init_rf(ah, &ecode);
475 if (!rfStatus) {
4d6b228d 476 DPRINTF(ah, ATH_DBG_FATAL,
d8baa939 477 "RF setup failed, status: %u\n", ecode);
f1dc5600
S		 478 return ecode;
479 }
f078f209 480
f1dc5600 481 return 0;
f078f209
LR		 482}
483
cbe61d8a 484static int ath9k_hw_rf_claim(struct ath_hw *ah)
f078f209 485{
f1dc5600
S		 486 u32 val;
487
488 REG_WRITE(ah, AR_PHY(0), 0x00000007);
489
490 val = ath9k_hw_get_radiorev(ah);
491 switch (val & AR_RADIO_SREV_MAJOR) {
492 case 0:
493 val = AR_RAD5133_SREV_MAJOR;
494 break;
495 case AR_RAD5133_SREV_MAJOR:
496 case AR_RAD5122_SREV_MAJOR:
497 case AR_RAD2133_SREV_MAJOR:
498 case AR_RAD2122_SREV_MAJOR:
499 break;
f078f209 500 default:
4d6b228d 501 DPRINTF(ah, ATH_DBG_FATAL,
d8baa939
S		 502 "Radio Chip Rev 0x%02X not supported\n",
503 val & AR_RADIO_SREV_MAJOR);
f1dc5600 504 return -EOPNOTSUPP;
f078f209 505 }
f078f209 506
d535a42a 507 ah->hw_version.analog5GhzRev = val;
f078f209 508
f1dc5600 509 return 0;
f078f209
LR		 510}
511
cbe61d8a 512static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209
LR		 513{
514 u32 sum;
515 int i;
516 u16 eeval;
f078f209
LR		 517
518 sum = 0;
519 for (i = 0; i < 3; i++) {
f74df6fb 520 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
f078f209 521 sum += eeval;
ba52da58
S		 522 ah->macaddr[2 * i] = eeval >> 8;
523 ah->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 524 }
d8baa939 525 if (sum == 0 || sum == 0xffff * 3)
f078f209 526 return -EADDRNOTAVAIL;
f078f209
LR		 527
528 return 0;
529}
530
cbe61d8a 531static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
9f804202
SB		 532{
533 u32 rxgain_type;
9f804202 534
f74df6fb
S		 535 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
536 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
9f804202
SB		 537
538 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
2660b81a 539 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 540 ar9280Modes_backoff_13db_rxgain_9280_2,
541 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
542 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
2660b81a 543 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 544 ar9280Modes_backoff_23db_rxgain_9280_2,
545 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
546 else
2660b81a 547 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 548 ar9280Modes_original_rxgain_9280_2,
549 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 550 } else {
2660b81a 551 INIT_INI_ARRAY(&ah->iniModesRxGain,
9f804202
SB		 552 ar9280Modes_original_rxgain_9280_2,
553 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
cbe61d8a 554 }
9f804202
SB		 555}
556
cbe61d8a 557static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
9f804202
SB		 558{
559 u32 txgain_type;
9f804202 560
f74df6fb
S		 561 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
562 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
9f804202
SB		 563
564 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
2660b81a 565 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 566 ar9280Modes_high_power_tx_gain_9280_2,
567 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
568 else
2660b81a 569 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 570 ar9280Modes_original_tx_gain_9280_2,
571 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 572 } else {
2660b81a 573 INIT_INI_ARRAY(&ah->iniModesTxGain,
9f804202
SB		 574 ar9280Modes_original_tx_gain_9280_2,
575 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
cbe61d8a 576 }
9f804202
SB		 577}
578
f637cfd6 579static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 580{
f1dc5600 581 int ecode;
f078f209 582
d8baa939 583 if (!ath9k_hw_chip_test(ah))
f1dc5600 584 return -ENODEV;
f078f209 585
f1dc5600
S		 586 ecode = ath9k_hw_rf_claim(ah);
587 if (ecode != 0)
f078f209 588 return ecode;
f078f209 589
f637cfd6 590 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 591 if (ecode != 0)
592 return ecode;
7d01b221 593
4d6b228d 594 DPRINTF(ah, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
7d01b221
S		 595 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
596
f1dc5600
S		 597 ecode = ath9k_hw_rfattach(ah);
598 if (ecode != 0)
599 return ecode;
f078f209 600
f1dc5600
S		 601 if (!AR_SREV_9100(ah)) {
602 ath9k_hw_ani_setup(ah);
f637cfd6 603 ath9k_hw_ani_init(ah);
f078f209
LR		 604 }
605
f078f209
LR		 606 return 0;
607}
608
ee2bb460
LR		 609static bool ath9k_hw_devid_supported(u16 devid)
610{
611 switch (devid) {
612 case AR5416_DEVID_PCI:
613 case AR5416_DEVID_PCIE:
614 case AR5416_AR9100_DEVID:
615 case AR9160_DEVID_PCI:
616 case AR9280_DEVID_PCI:
617 case AR9280_DEVID_PCIE:
618 case AR9285_DEVID_PCIE:
619 case AR5416_DEVID_AR9287_PCI:
620 case AR5416_DEVID_AR9287_PCIE:
621 return true;
622 default:
623 break;
624 }
625 return false;
626}
627
f9d4a668
LR		 628static bool ath9k_hw_macversion_supported(u32 macversion)
629{
630 switch (macversion) {
631 case AR_SREV_VERSION_5416_PCI:
632 case AR_SREV_VERSION_5416_PCIE:
633 case AR_SREV_VERSION_9160:
634 case AR_SREV_VERSION_9100:
635 case AR_SREV_VERSION_9280:
636 case AR_SREV_VERSION_9285:
637 case AR_SREV_VERSION_9287:
638 return true;
d7e7d229
LR		 639 /* Not yet */
640 case AR_SREV_VERSION_9271:
f9d4a668
LR		 641 default:
642 break;
643 }
644 return false;
645}
646
aa4058ae 647static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
f078f209 648{
f1dc5600
S		 649 if (AR_SREV_9160_10_OR_LATER(ah)) {
650 if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a
S		 651 ah->iq_caldata.calData = &iq_cal_single_sample;
652 ah->adcgain_caldata.calData =
f1dc5600 653 &adc_gain_cal_single_sample;
2660b81a 654 ah->adcdc_caldata.calData =
f1dc5600 655 &adc_dc_cal_single_sample;
2660b81a 656 ah->adcdc_calinitdata.calData =
f1dc5600
S		 657 &adc_init_dc_cal;
658 } else {
2660b81a
S		 659 ah->iq_caldata.calData = &iq_cal_multi_sample;
660 ah->adcgain_caldata.calData =
f1dc5600 661 &adc_gain_cal_multi_sample;
2660b81a 662 ah->adcdc_caldata.calData =
f1dc5600 663 &adc_dc_cal_multi_sample;
2660b81a 664 ah->adcdc_calinitdata.calData =
f1dc5600
S		 665 &adc_init_dc_cal;
666 }
2660b81a 667 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
f1dc5600 668 }
aa4058ae 669}
f078f209 670
aa4058ae
LR		 671static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
672{
d7e7d229
LR		 673 if (AR_SREV_9271(ah)) {
674 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271_1_0,
675 ARRAY_SIZE(ar9271Modes_9271_1_0), 6);
676 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271_1_0,
677 ARRAY_SIZE(ar9271Common_9271_1_0), 2);
678 return;
679 }
680
ac88b6ec
VN		 681 if (AR_SREV_9287_11_OR_LATER(ah)) {
682 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
683 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
684 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
685 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
686 if (ah->config.pcie_clock_req)
687 INIT_INI_ARRAY(&ah->iniPcieSerdes,
688 ar9287PciePhy_clkreq_off_L1_9287_1_1,
689 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
690 else
691 INIT_INI_ARRAY(&ah->iniPcieSerdes,
692 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
693 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
694 2);
695 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
696 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
697 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
698 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
699 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
700
701 if (ah->config.pcie_clock_req)
702 INIT_INI_ARRAY(&ah->iniPcieSerdes,
703 ar9287PciePhy_clkreq_off_L1_9287_1_0,
704 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
705 else
706 INIT_INI_ARRAY(&ah->iniPcieSerdes,
707 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
708 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
709 2);
710 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
f078f209 711
4e845168 712
2660b81a 713 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
e7594072 714 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
2660b81a 715 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
e7594072
SB		 716 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
717
2660b81a
S		 718 if (ah->config.pcie_clock_req) {
719 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 720 ar9285PciePhy_clkreq_off_L1_9285_1_2,
721 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
722 } else {
2660b81a 723 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 724 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
725 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
726 2);
727 }
728 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
2660b81a 729 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
e7594072 730 ARRAY_SIZE(ar9285Modes_9285), 6);
2660b81a 731 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
e7594072
SB		 732 ARRAY_SIZE(ar9285Common_9285), 2);
733
2660b81a
S		 734 if (ah->config.pcie_clock_req) {
735 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 736 ar9285PciePhy_clkreq_off_L1_9285,
737 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
738 } else {
2660b81a 739 INIT_INI_ARRAY(&ah->iniPcieSerdes,
e7594072
SB		 740 ar9285PciePhy_clkreq_always_on_L1_9285,
741 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
742 }
743 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2660b81a 744 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
f1dc5600 745 ARRAY_SIZE(ar9280Modes_9280_2), 6);
2660b81a 746 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
f1dc5600 747 ARRAY_SIZE(ar9280Common_9280_2), 2);
f078f209 748
2660b81a
S		 749 if (ah->config.pcie_clock_req) {
750 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 751 ar9280PciePhy_clkreq_off_L1_9280,
752 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
753 } else {
2660b81a 754 INIT_INI_ARRAY(&ah->iniPcieSerdes,
f1dc5600
S		 755 ar9280PciePhy_clkreq_always_on_L1_9280,
756 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
757 }
2660b81a 758 INIT_INI_ARRAY(&ah->iniModesAdditional,
f1dc5600
S		 759 ar9280Modes_fast_clock_9280_2,
760 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
761 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
2660b81a 762 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
f1dc5600 763 ARRAY_SIZE(ar9280Modes_9280), 6);
2660b81a 764 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
f1dc5600
S		 765 ARRAY_SIZE(ar9280Common_9280), 2);
766 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2660b81a 767 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
f1dc5600 768 ARRAY_SIZE(ar5416Modes_9160), 6);
2660b81a 769 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
f1dc5600 770 ARRAY_SIZE(ar5416Common_9160), 2);
2660b81a 771 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
f1dc5600 772 ARRAY_SIZE(ar5416Bank0_9160), 2);
2660b81a 773 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
f1dc5600 774 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
2660b81a 775 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
f1dc5600 776 ARRAY_SIZE(ar5416Bank1_9160), 2);
2660b81a 777 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
f1dc5600 778 ARRAY_SIZE(ar5416Bank2_9160), 2);
2660b81a 779 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
f1dc5600 780 ARRAY_SIZE(ar5416Bank3_9160), 3);
2660b81a 781 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
f1dc5600 782 ARRAY_SIZE(ar5416Bank6_9160), 3);
2660b81a 783 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
f1dc5600 784 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
2660b81a 785 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
f1dc5600
S		 786 ARRAY_SIZE(ar5416Bank7_9160), 2);
787 if (AR_SREV_9160_11(ah)) {
2660b81a 788 INIT_INI_ARRAY(&ah->iniAddac,
f1dc5600
S		 789 ar5416Addac_91601_1,
790 ARRAY_SIZE(ar5416Addac_91601_1), 2);
791 } else {
2660b81a 792 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
f1dc5600
S		 793 ARRAY_SIZE(ar5416Addac_9160), 2);
794 }
795 } else if (AR_SREV_9100_OR_LATER(ah)) {
2660b81a 796 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
f1dc5600 797 ARRAY_SIZE(ar5416Modes_9100), 6);
2660b81a 798 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
f1dc5600 799 ARRAY_SIZE(ar5416Common_9100), 2);
2660b81a 800 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
f1dc5600 801 ARRAY_SIZE(ar5416Bank0_9100), 2);
2660b81a 802 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
f1dc5600 803 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
2660b81a 804 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
f1dc5600 805 ARRAY_SIZE(ar5416Bank1_9100), 2);
2660b81a 806 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
f1dc5600 807 ARRAY_SIZE(ar5416Bank2_9100), 2);
2660b81a 808 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
f1dc5600 809 ARRAY_SIZE(ar5416Bank3_9100), 3);
2660b81a 810 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
f1dc5600 811 ARRAY_SIZE(ar5416Bank6_9100), 3);
2660b81a 812 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
f1dc5600 813 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
2660b81a 814 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
f1dc5600 815 ARRAY_SIZE(ar5416Bank7_9100), 2);
2660b81a 816 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
f1dc5600
S		 817 ARRAY_SIZE(ar5416Addac_9100), 2);
818 } else {
2660b81a 819 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
f1dc5600 820 ARRAY_SIZE(ar5416Modes), 6);
2660b81a 821 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
f1dc5600 822 ARRAY_SIZE(ar5416Common), 2);
2660b81a 823 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
f1dc5600 824 ARRAY_SIZE(ar5416Bank0), 2);
2660b81a 825 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
f1dc5600 826 ARRAY_SIZE(ar5416BB_RfGain), 3);
2660b81a 827 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
f1dc5600 828 ARRAY_SIZE(ar5416Bank1), 2);
2660b81a 829 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
f1dc5600 830 ARRAY_SIZE(ar5416Bank2), 2);
2660b81a 831 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
f1dc5600 832 ARRAY_SIZE(ar5416Bank3), 3);
2660b81a 833 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
f1dc5600 834 ARRAY_SIZE(ar5416Bank6), 3);
2660b81a 835 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
f1dc5600 836 ARRAY_SIZE(ar5416Bank6TPC), 3);
2660b81a 837 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
f1dc5600 838 ARRAY_SIZE(ar5416Bank7), 2);
2660b81a 839 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
f1dc5600 840 ARRAY_SIZE(ar5416Addac), 2);
f078f209 841 }
aa4058ae 842}
f078f209 843
aa4058ae
LR		 844static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
845{
b37fa870 846 if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec
VN		 847 INIT_INI_ARRAY(&ah->iniModesRxGain,
848 ar9287Modes_rx_gain_9287_1_1,
849 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
850 else if (AR_SREV_9287_10(ah))
851 INIT_INI_ARRAY(&ah->iniModesRxGain,
852 ar9287Modes_rx_gain_9287_1_0,
853 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
854 else if (AR_SREV_9280_20(ah))
855 ath9k_hw_init_rxgain_ini(ah);
856
b37fa870 857 if (AR_SREV_9287_11_OR_LATER(ah)) {
ac88b6ec
VN		 858 INIT_INI_ARRAY(&ah->iniModesTxGain,
859 ar9287Modes_tx_gain_9287_1_1,
860 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
861 } else if (AR_SREV_9287_10(ah)) {
862 INIT_INI_ARRAY(&ah->iniModesTxGain,
863 ar9287Modes_tx_gain_9287_1_0,
864 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
865 } else if (AR_SREV_9280_20(ah)) {
866 ath9k_hw_init_txgain_ini(ah);
867 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
4e845168
SB		 868 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
869
870 /* txgain table */
871 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
872 INIT_INI_ARRAY(&ah->iniModesTxGain,
873 ar9285Modes_high_power_tx_gain_9285_1_2,
874 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
875 } else {
876 INIT_INI_ARRAY(&ah->iniModesTxGain,
877 ar9285Modes_original_tx_gain_9285_1_2,
878 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
879 }
880
881 }
aa4058ae 882}
4e845168 883
aa4058ae
LR		 884static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
885{
886 u32 i, j;
06d0f066
S		 887
888 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
889 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
890
891 /* EEPROM Fixup */
2660b81a
S		 892 for (i = 0; i < ah->iniModes.ia_rows; i++) {
893 u32 reg = INI_RA(&ah->iniModes, i, 0);
f078f209 894
2660b81a
S		 895 for (j = 1; j < ah->iniModes.ia_columns; j++) {
896 u32 val = INI_RA(&ah->iniModes, i, j);
f078f209 897
2660b81a 898 INI_RA(&ah->iniModes, i, j) =
e7594072 899 ath9k_hw_ini_fixup(ah,
2660b81a 900 &ah->eeprom.def,
f1dc5600
S		 901 reg, val);
902 }
f078f209 903 }
f1dc5600 904 }
aa4058ae
LR		 905}
906
f637cfd6 907int ath9k_hw_init(struct ath_hw *ah)
aa4058ae 908{
95fafca2 909 int r = 0;
aa4058ae 910
95fafca2
LR		 911 if (!ath9k_hw_devid_supported(ah->hw_version.devid))
912 return -EOPNOTSUPP;
aa4058ae
LR		 913
914 ath9k_hw_init_defaults(ah);
915 ath9k_hw_init_config(ah);
916
917 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
4d6b228d 918 DPRINTF(ah, ATH_DBG_FATAL, "Couldn't reset chip\n");
95fafca2 919 return -EIO;
aa4058ae
LR		 920 }
921
1adc93c8 922 if (!ath9k_hw_setpower_nolock(ah, ATH9K_PM_AWAKE)) {
4d6b228d 923 DPRINTF(ah, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
95fafca2 924 return -EIO;
aa4058ae
LR		 925 }
926
927 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
928 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
929 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
930 ah->config.serialize_regmode =
931 SER_REG_MODE_ON;
932 } else {
933 ah->config.serialize_regmode =
934 SER_REG_MODE_OFF;
935 }
936 }
937
4d6b228d 938 DPRINTF(ah, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 939 ah->config.serialize_regmode);
940
941 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
4d6b228d 942 DPRINTF(ah, ATH_DBG_FATAL,
aa4058ae
LR		 943 "Mac Chip Rev 0x%02x.%x is not supported by "
944 "this driver\n", ah->hw_version.macVersion,
945 ah->hw_version.macRev);
95fafca2 946 return -EOPNOTSUPP;
aa4058ae
LR		 947 }
948
949 if (AR_SREV_9100(ah)) {
950 ah->iq_caldata.calData = &iq_cal_multi_sample;
951 ah->supp_cals = IQ_MISMATCH_CAL;
952 ah->is_pciexpress = false;
953 }
d7e7d229
LR		 954
955 if (AR_SREV_9271(ah))
956 ah->is_pciexpress = false;
957
aa4058ae
LR		 958 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
959
960 ath9k_hw_init_cal_settings(ah);
961
962 ah->ani_function = ATH9K_ANI_ALL;
963 if (AR_SREV_9280_10_OR_LATER(ah))
964 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
965
966 ath9k_hw_init_mode_regs(ah);
967
968 if (ah->is_pciexpress)
93b1b37f 969 ath9k_hw_configpcipowersave(ah, 0, 0);
aa4058ae
LR		 970 else
971 ath9k_hw_disablepcie(ah);
972
f637cfd6 973 r = ath9k_hw_post_init(ah);
aa4058ae 974 if (r)
95fafca2 975 return r;
aa4058ae
LR		 976
977 ath9k_hw_init_mode_gain_regs(ah);
978 ath9k_hw_fill_cap_info(ah);
979 ath9k_hw_init_11a_eeprom_fix(ah);
f6688cd8 980
4f3acf81
LR		 981 r = ath9k_hw_init_macaddr(ah);
982 if (r) {
4d6b228d 983 DPRINTF(ah, ATH_DBG_FATAL,
d8baa939 984 "Failed to initialize MAC address\n");
95fafca2 985 return r;
f078f209
LR		 986 }
987
d7e7d229 988 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 989 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 990 else
2660b81a 991 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 992
f1dc5600 993 ath9k_init_nfcal_hist_buffer(ah);
f078f209 994
4f3acf81 995 return 0;
f078f209
LR		 996}
997
cbe61d8a 998static void ath9k_hw_init_bb(struct ath_hw *ah,
f1dc5600 999 struct ath9k_channel *chan)
f078f209 1000{
f1dc5600 1001 u32 synthDelay;
f078f209 1002
f1dc5600 1003 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 1004 if (IS_CHAN_B(chan))
f1dc5600
S		 1005 synthDelay = (4 * synthDelay) / 22;
1006 else
1007 synthDelay /= 10;
f078f209 1008
f1dc5600 1009 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
f078f209 1010
f1dc5600 1011 udelay(synthDelay + BASE_ACTIVATE_DELAY);
f078f209
LR		 1012}
1013
cbe61d8a 1014static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 1015{
f1dc5600
S		 1016 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1017 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 1018
f1dc5600
S		 1019 REG_WRITE(ah, AR_QOS_NO_ACK,
1020 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1021 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1022 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1023
1024 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1025 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1026 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1027 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1028 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
f078f209
LR		 1029}
1030
cbe61d8a 1031static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 1032 struct ath9k_channel *chan)
f078f209 1033{
f1dc5600 1034 u32 pll;
f078f209 1035
f1dc5600
S		 1036 if (AR_SREV_9100(ah)) {
1037 if (chan && IS_CHAN_5GHZ(chan))
1038 pll = 0x1450;
f078f209 1039 else
f1dc5600
S		 1040 pll = 0x1458;
1041 } else {
1042 if (AR_SREV_9280_10_OR_LATER(ah)) {
1043 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 1044
f1dc5600
S		 1045 if (chan && IS_CHAN_HALF_RATE(chan))
1046 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1047 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1048 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 1049
f1dc5600
S		 1050 if (chan && IS_CHAN_5GHZ(chan)) {
1051 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
f078f209 1052
f078f209 1053
f1dc5600
S		 1054 if (AR_SREV_9280_20(ah)) {
1055 if (((chan->channel % 20) == 0)
1056 || ((chan->channel % 10) == 0))
1057 pll = 0x2850;
1058 else
1059 pll = 0x142c;
1060 }
1061 } else {
1062 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1063 }
f078f209 1064
f1dc5600 1065 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
f078f209 1066
f1dc5600 1067 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
f078f209 1068
f1dc5600
S		 1069 if (chan && IS_CHAN_HALF_RATE(chan))
1070 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1071 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1072 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
f078f209 1073
f1dc5600
S		 1074 if (chan && IS_CHAN_5GHZ(chan))
1075 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1076 else
1077 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1078 } else {
1079 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
f078f209 1080
f1dc5600
S		 1081 if (chan && IS_CHAN_HALF_RATE(chan))
1082 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1083 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1084 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
f078f209 1085
f1dc5600
S		 1086 if (chan && IS_CHAN_5GHZ(chan))
1087 pll |= SM(0xa, AR_RTC_PLL_DIV);
1088 else
1089 pll |= SM(0xb, AR_RTC_PLL_DIV);
1090 }
1091 }
d03a66c1 1092 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 1093
f1dc5600
S		 1094 udelay(RTC_PLL_SETTLE_DELAY);
1095
1096 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 1097}
1098
cbe61d8a 1099static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
f078f209 1100{
f078f209
LR		 1101 int rx_chainmask, tx_chainmask;
1102
2660b81a
S		 1103 rx_chainmask = ah->rxchainmask;
1104 tx_chainmask = ah->txchainmask;
f078f209
LR		 1105
1106 switch (rx_chainmask) {
1107 case 0x5:
1108 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1109 AR_PHY_SWAP_ALT_CHAIN);
1110 case 0x3:
d535a42a 1111 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
f078f209
LR		 1112 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1113 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1114 break;
1115 }
1116 case 0x1:
1117 case 0x2:
f078f209
LR		 1118 case 0x7:
1119 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1120 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1121 break;
1122 default:
1123 break;
1124 }
1125
1126 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1127 if (tx_chainmask == 0x5) {
1128 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1129 AR_PHY_SWAP_ALT_CHAIN);
1130 }
1131 if (AR_SREV_9100(ah))
1132 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1133 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1134}
1135
cbe61d8a 1136static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 1137 enum nl80211_iftype opmode)
f078f209 1138{
2660b81a 1139 ah->mask_reg = AR_IMR_TXERR |
f1dc5600
S		 1140 AR_IMR_TXURN |
1141 AR_IMR_RXERR |
1142 AR_IMR_RXORN |
1143 AR_IMR_BCNMISC;
f078f209 1144
0ef1f168 1145 if (ah->config.intr_mitigation)
2660b81a 1146 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
f078f209 1147 else
2660b81a 1148 ah->mask_reg |= AR_IMR_RXOK;
f078f209 1149
2660b81a 1150 ah->mask_reg |= AR_IMR_TXOK;
f078f209 1151
d97809db 1152 if (opmode == NL80211_IFTYPE_AP)
2660b81a 1153 ah->mask_reg |= AR_IMR_MIB;
f078f209 1154
2660b81a 1155 REG_WRITE(ah, AR_IMR, ah->mask_reg);
f1dc5600 1156 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
f078f209 1157
f1dc5600
S		 1158 if (!AR_SREV_9100(ah)) {
1159 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1160 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1161 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1162 }
f078f209
LR		 1163}
1164
cbe61d8a 1165static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 1166{
f078f209 1167 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
4d6b228d 1168 DPRINTF(ah, ATH_DBG_RESET, "bad ack timeout %u\n", us);
2660b81a 1169 ah->acktimeout = (u32) -1;
f078f209
LR		 1170 return false;
1171 } else {
1172 REG_RMW_FIELD(ah, AR_TIME_OUT,
1173 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1174 ah->acktimeout = us;
f078f209
LR		 1175 return true;
1176 }
1177}
1178
cbe61d8a 1179static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
f078f209 1180{
f078f209 1181 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
4d6b228d 1182 DPRINTF(ah, ATH_DBG_RESET, "bad cts timeout %u\n", us);
2660b81a 1183 ah->ctstimeout = (u32) -1;
f078f209
LR		 1184 return false;
1185 } else {
1186 REG_RMW_FIELD(ah, AR_TIME_OUT,
1187 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
2660b81a 1188 ah->ctstimeout = us;
f078f209
LR		 1189 return true;
1190 }
1191}
f1dc5600 1192
cbe61d8a 1193static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 1194{
f078f209 1195 if (tu > 0xFFFF) {
4d6b228d 1196 DPRINTF(ah, ATH_DBG_XMIT,
04bd4638 1197 "bad global tx timeout %u\n", tu);
2660b81a 1198 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 1199 return false;
1200 } else {
1201 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 1202 ah->globaltxtimeout = tu;
f078f209
LR		 1203 return true;
1204 }
1205}
1206
cbe61d8a 1207static void ath9k_hw_init_user_settings(struct ath_hw *ah)
f078f209 1208{
4d6b228d 1209 DPRINTF(ah, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
2660b81a 1210 ah->misc_mode);
f078f209 1211
2660b81a 1212 if (ah->misc_mode != 0)
f1dc5600 1213 REG_WRITE(ah, AR_PCU_MISC,
2660b81a
S		 1214 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1215 if (ah->slottime != (u32) -1)
1216 ath9k_hw_setslottime(ah, ah->slottime);
1217 if (ah->acktimeout != (u32) -1)
1218 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1219 if (ah->ctstimeout != (u32) -1)
1220 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1221 if (ah->globaltxtimeout != (u32) -1)
1222 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600
S		 1223}
1224
1225const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1226{
1227 return vendorid == ATHEROS_VENDOR_ID ?
1228 ath9k_hw_devname(devid) : NULL;
1229}
1230
cbe61d8a 1231void ath9k_hw_detach(struct ath_hw *ah)
f1dc5600
S		 1232{
1233 if (!AR_SREV_9100(ah))
e70c0cfd 1234 ath9k_hw_ani_disable(ah);
f1dc5600 1235
081b35ab 1236 ath9k_hw_rf_free(ah);
1adc93c8 1237 ath9k_hw_setpower_nolock(ah, ATH9K_PM_FULL_SLEEP);
f1dc5600 1238 kfree(ah);
9db6b6a2 1239 ah = NULL;
f1dc5600
S		 1240}
1241
f1dc5600
S		 1242/*******/
1243/* INI */
1244/*******/
1245
cbe61d8a 1246static void ath9k_hw_override_ini(struct ath_hw *ah,
f1dc5600
S		 1247 struct ath9k_channel *chan)
1248{
d7e7d229
LR		 1249 u32 val;
1250
1251 if (AR_SREV_9271(ah)) {
1252 /*
1253 * Enable spectral scan to solution for issues with stuck
1254 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1255 * AR9271 1.1
1256 */
1257 if (AR_SREV_9271_10(ah)) {
1258 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | AR_PHY_SPECTRAL_SCAN_ENABLE;
1259 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1260 }
1261 else if (AR_SREV_9271_11(ah))
1262 /*
1263 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1264 * present on AR9271 1.1
1265 */
1266 REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1267 return;
1268 }
1269
8aa15e15
SB		 1270 /*
1271 * Set the RX_ABORT and RX_DIS and clear if off only after
1272 * RXE is set for MAC. This prevents frames with corrupted
1273 * descriptor status.
1274 */
1275 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1276
204d7940
VT		 1277 if (AR_SREV_9280_10_OR_LATER(ah)) {
1278 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1279 (~AR_PCU_MISC_MODE2_HWWAR1);
1280
1281 if (AR_SREV_9287_10_OR_LATER(ah))
1282 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1283
1284 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1285 }
8aa15e15 1286
a8c96d3b 1287 if (!AR_SREV_5416_20_OR_LATER(ah) ||
f1dc5600
S		 1288 AR_SREV_9280_10_OR_LATER(ah))
1289 return;
d7e7d229
LR		 1290 /*
1291 * Disable BB clock gating
1292 * Necessary to avoid issues on AR5416 2.0
1293 */
f1dc5600 1294 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
f078f209
LR		 1295}
1296
cbe61d8a 1297static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
e7594072 1298 struct ar5416_eeprom_def *pEepData,
f1dc5600 1299 u32 reg, u32 value)
f078f209 1300{
f1dc5600 1301 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
f078f209 1302
d535a42a 1303 switch (ah->hw_version.devid) {
f1dc5600
S		 1304 case AR9280_DEVID_PCI:
1305 if (reg == 0x7894) {
4d6b228d 1306 DPRINTF(ah, ATH_DBG_EEPROM,
f1dc5600
S		 1307 "ini VAL: %x EEPROM: %x\n", value,
1308 (pBase->version & 0xff));
1309
1310 if ((pBase->version & 0xff) > 0x0a) {
4d6b228d 1311 DPRINTF(ah, ATH_DBG_EEPROM,
f1dc5600
S		 1312 "PWDCLKIND: %d\n",
1313 pBase->pwdclkind);
1314 value &= ~AR_AN_TOP2_PWDCLKIND;
1315 value |= AR_AN_TOP2_PWDCLKIND &
1316 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1317 } else {
4d6b228d 1318 DPRINTF(ah, ATH_DBG_EEPROM,
f1dc5600
S		 1319 "PWDCLKIND Earlier Rev\n");
1320 }
1321
4d6b228d 1322 DPRINTF(ah, ATH_DBG_EEPROM,
f1dc5600
S		 1323 "final ini VAL: %x\n", value);
1324 }
1325 break;
1326 }
1327
1328 return value;
f078f209
LR		 1329}
1330
cbe61d8a 1331static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
e7594072
SB		 1332 struct ar5416_eeprom_def *pEepData,
1333 u32 reg, u32 value)
1334{
2660b81a 1335 if (ah->eep_map == EEP_MAP_4KBITS)
e7594072
SB		 1336 return value;
1337 else
1338 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1339}
1340
8bd1d07f
SB		 1341static void ath9k_olc_init(struct ath_hw *ah)
1342{
1343 u32 i;
1344
db91f2e4
VN		 1345 if (OLC_FOR_AR9287_10_LATER) {
1346 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1347 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1348 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1349 AR9287_AN_TXPC0_TXPCMODE,
1350 AR9287_AN_TXPC0_TXPCMODE_S,
1351 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1352 udelay(100);
1353 } else {
1354 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1355 ah->originalGain[i] =
1356 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1357 AR_PHY_TX_GAIN);
1358 ah->PDADCdelta = 0;
1359 }
8bd1d07f
SB		 1360}
1361
3a702e49
BC		 1362static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1363 struct ath9k_channel *chan)
1364{
1365 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1366
1367 if (IS_CHAN_B(chan))
1368 ctl |= CTL_11B;
1369 else if (IS_CHAN_G(chan))
1370 ctl |= CTL_11G;
1371 else
1372 ctl |= CTL_11A;
1373
1374 return ctl;
1375}
1376
cbe61d8a 1377static int ath9k_hw_process_ini(struct ath_hw *ah,
f1dc5600
S		 1378 struct ath9k_channel *chan,
1379 enum ath9k_ht_macmode macmode)
f078f209 1380{
608b88cb 1381 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f078f209 1382 int i, regWrites = 0;
5f8e077c 1383 struct ieee80211_channel *channel = chan->chan;
f078f209 1384 u32 modesIndex, freqIndex;
f078f209
LR		 1385
1386 switch (chan->chanmode) {
1387 case CHANNEL_A:
1388 case CHANNEL_A_HT20:
1389 modesIndex = 1;
1390 freqIndex = 1;
1391 break;
1392 case CHANNEL_A_HT40PLUS:
1393 case CHANNEL_A_HT40MINUS:
1394 modesIndex = 2;
1395 freqIndex = 1;
1396 break;
1397 case CHANNEL_G:
1398 case CHANNEL_G_HT20:
1399 case CHANNEL_B:
1400 modesIndex = 4;
1401 freqIndex = 2;
1402 break;
1403 case CHANNEL_G_HT40PLUS:
1404 case CHANNEL_G_HT40MINUS:
1405 modesIndex = 3;
1406 freqIndex = 2;
1407 break;
1408
1409 default:
1410 return -EINVAL;
1411 }
1412
1413 REG_WRITE(ah, AR_PHY(0), 0x00000007);
f078f209 1414 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
f74df6fb 1415 ah->eep_ops->set_addac(ah, chan);
f078f209 1416
a8c96d3b 1417 if (AR_SREV_5416_22_OR_LATER(ah)) {
2660b81a 1418 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
f078f209
LR		 1419 } else {
1420 struct ar5416IniArray temp;
1421 u32 addacSize =
2660b81a
S		 1422 sizeof(u32) * ah->iniAddac.ia_rows *
1423 ah->iniAddac.ia_columns;
f078f209 1424
2660b81a
S		 1425 memcpy(ah->addac5416_21,
1426 ah->iniAddac.ia_array, addacSize);
f078f209 1427
2660b81a 1428 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
f078f209 1429
2660b81a
S		 1430 temp.ia_array = ah->addac5416_21;
1431 temp.ia_columns = ah->iniAddac.ia_columns;
1432 temp.ia_rows = ah->iniAddac.ia_rows;
f078f209
LR		 1433 REG_WRITE_ARRAY(&temp, 1, regWrites);
1434 }
f1dc5600 1435
f078f209
LR		 1436 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1437
2660b81a
S		 1438 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1439 u32 reg = INI_RA(&ah->iniModes, i, 0);
1440 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
f078f209 1441
f078f209
LR		 1442 REG_WRITE(ah, reg, val);
1443
1444 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1445 && ah->config.analog_shiftreg) {
f078f209
LR		 1446 udelay(100);
1447 }
1448
1449 DO_DELAY(regWrites);
1450 }
1451
ac88b6ec 1452 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
2660b81a 1453 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
9f804202 1454
ac88b6ec
VN		 1455 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1456 AR_SREV_9287_10_OR_LATER(ah))
2660b81a 1457 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
9f804202 1458
2660b81a
S		 1459 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1460 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1461 u32 val = INI_RA(&ah->iniCommon, i, 1);
f078f209
LR		 1462
1463 REG_WRITE(ah, reg, val);
1464
1465 if (reg >= 0x7800 && reg < 0x78a0
2660b81a 1466 && ah->config.analog_shiftreg) {
f078f209
LR		 1467 udelay(100);
1468 }
1469
1470 DO_DELAY(regWrites);
1471 }
1472
1473 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1474
1475 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
2660b81a 1476 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
f078f209
LR		 1477 regWrites);
1478 }
1479
1480 ath9k_hw_override_ini(ah, chan);
1481 ath9k_hw_set_regs(ah, chan, macmode);
1482 ath9k_hw_init_chain_masks(ah);
1483
8bd1d07f
SB		 1484 if (OLC_FOR_AR9280_20_LATER)
1485 ath9k_olc_init(ah);
1486
8fbff4b8 1487 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1488 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 1489 channel->max_antenna_gain * 2,
1490 channel->max_power * 2,
1491 min((u32) MAX_RATE_POWER,
608b88cb 1492 (u32) regulatory->power_limit));
f078f209
LR		 1493
1494 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
4d6b228d 1495 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1496 "ar5416SetRfRegs failed\n");
f078f209
LR		 1497 return -EIO;
1498 }
1499
1500 return 0;
1501}
1502
f1dc5600
S		 1503/****************************************/
1504/* Reset and Channel Switching Routines */
1505/****************************************/
1506
cbe61d8a 1507static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 1508{
f1dc5600
S		 1509 u32 rfMode = 0;
1510
1511 if (chan == NULL)
1512 return;
1513
1514 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1515 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1516
1517 if (!AR_SREV_9280_10_OR_LATER(ah))
1518 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1519 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1520
1521 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1522 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1523
1524 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1525}
1526
cbe61d8a 1527static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
f1dc5600
S		 1528{
1529 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1530}
1531
cbe61d8a 1532static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600
S		 1533{
1534 u32 regval;
1535
d7e7d229
LR		 1536 /*
1537 * set AHB_MODE not to do cacheline prefetches
1538 */
f1dc5600
S		 1539 regval = REG_READ(ah, AR_AHB_MODE);
1540 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1541
d7e7d229
LR		 1542 /*
1543 * let mac dma reads be in 128 byte chunks
1544 */
f1dc5600
S		 1545 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1546 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1547
d7e7d229
LR		 1548 /*
1549 * Restore TX Trigger Level to its pre-reset value.
1550 * The initial value depends on whether aggregation is enabled, and is
1551 * adjusted whenever underruns are detected.
1552 */
2660b81a 1553 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1554
d7e7d229
LR		 1555 /*
1556 * let mac dma writes be in 128 byte chunks
1557 */
f1dc5600
S		 1558 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1559 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1560
d7e7d229
LR		 1561 /*
1562 * Setup receive FIFO threshold to hold off TX activities
1563 */
f1dc5600
S		 1564 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1565
d7e7d229
LR		 1566 /*
1567 * reduce the number of usable entries in PCU TXBUF to avoid
1568 * wrap around issues.
1569 */
f1dc5600 1570 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1571 /* For AR9285 the number of Fifos are reduced to half.
1572 * So set the usable tx buf size also to half to
1573 * avoid data/delimiter underruns
1574 */
f1dc5600
S		 1575 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1576 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1577 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1578 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1579 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1580 }
1581}
1582
cbe61d8a 1583static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 1584{
1585 u32 val;
1586
1587 val = REG_READ(ah, AR_STA_ID1);
1588 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1589 switch (opmode) {
d97809db 1590 case NL80211_IFTYPE_AP:
f1dc5600
S		 1591 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1592 | AR_STA_ID1_KSRCH_MODE);
1593 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1594 break;
d97809db 1595 case NL80211_IFTYPE_ADHOC:
9cb5412b 1596 case NL80211_IFTYPE_MESH_POINT:
f1dc5600
S		 1597 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1598 | AR_STA_ID1_KSRCH_MODE);
1599 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1600 break;
d97809db
CM		 1601 case NL80211_IFTYPE_STATION:
1602 case NL80211_IFTYPE_MONITOR:
f1dc5600 1603 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 1604 break;
f1dc5600
S		 1605 }
1606}
1607
cbe61d8a 1608static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
f1dc5600
S		 1609 u32 coef_scaled,
1610 u32 *coef_mantissa,
1611 u32 *coef_exponent)
1612{
1613 u32 coef_exp, coef_man;
1614
1615 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1616 if ((coef_scaled >> coef_exp) & 0x1)
1617 break;
1618
1619 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1620
1621 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1622
1623 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1624 *coef_exponent = coef_exp - 16;
1625}
1626
cbe61d8a 1627static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
f1dc5600
S		 1628 struct ath9k_channel *chan)
1629{
1630 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1631 u32 clockMhzScaled = 0x64000000;
1632 struct chan_centers centers;
1633
1634 if (IS_CHAN_HALF_RATE(chan))
1635 clockMhzScaled = clockMhzScaled >> 1;
1636 else if (IS_CHAN_QUARTER_RATE(chan))
1637 clockMhzScaled = clockMhzScaled >> 2;
1638
1639 ath9k_hw_get_channel_centers(ah, chan, &centers);
1640 coef_scaled = clockMhzScaled / centers.synth_center;
1641
1642 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1643 &ds_coef_exp);
1644
1645 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1646 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1647 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1648 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1649
1650 coef_scaled = (9 * coef_scaled) / 10;
1651
1652 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1653 &ds_coef_exp);
1654
1655 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1656 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1657 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1658 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1659}
1660
cbe61d8a 1661static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1662{
1663 u32 rst_flags;
1664 u32 tmpReg;
1665
70768496
S		 1666 if (AR_SREV_9100(ah)) {
1667 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1668 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1669 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1670 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1671 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1672 }
1673
f1dc5600
S		 1674 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1675 AR_RTC_FORCE_WAKE_ON_INT);
1676
1677 if (AR_SREV_9100(ah)) {
1678 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1679 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1680 } else {
1681 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1682 if (tmpReg &
1683 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1684 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1685 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1686 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1687 } else {
1688 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1689 }
1690
1691 rst_flags = AR_RTC_RC_MAC_WARM;
1692 if (type == ATH9K_RESET_COLD)
1693 rst_flags |= AR_RTC_RC_MAC_COLD;
1694 }
1695
d03a66c1 1696 REG_WRITE(ah, AR_RTC_RC, rst_flags);
f1dc5600
S		 1697 udelay(50);
1698
d03a66c1 1699 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1700 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
4d6b228d 1701 DPRINTF(ah, ATH_DBG_RESET,
04bd4638 1702 "RTC stuck in MAC reset\n");
f1dc5600
S		 1703 return false;
1704 }
1705
1706 if (!AR_SREV_9100(ah))
1707 REG_WRITE(ah, AR_RC, 0);
1708
1709 ath9k_hw_init_pll(ah, NULL);
1710
1711 if (AR_SREV_9100(ah))
1712 udelay(50);
1713
1714 return true;
1715}
1716
cbe61d8a 1717static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600
S		 1718{
1719 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1720 AR_RTC_FORCE_WAKE_ON_INT);
1721
1c29ce67
VT		 1722 if (!AR_SREV_9100(ah))
1723 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1724
d03a66c1 1725 REG_WRITE(ah, AR_RTC_RESET, 0);
8bd1d07f 1726 udelay(2);
1c29ce67
VT		 1727
1728 if (!AR_SREV_9100(ah))
1729 REG_WRITE(ah, AR_RC, 0);
1730
d03a66c1 1731 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1732
1733 if (!ath9k_hw_wait(ah,
1734 AR_RTC_STATUS,
1735 AR_RTC_STATUS_M,
0caa7b14
S		 1736 AR_RTC_STATUS_ON,
1737 AH_WAIT_TIMEOUT)) {
4d6b228d 1738 DPRINTF(ah, ATH_DBG_RESET, "RTC not waking up\n");
f1dc5600 1739 return false;
f078f209
LR		 1740 }
1741
f1dc5600
S		 1742 ath9k_hw_read_revisions(ah);
1743
1744 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1745}
1746
cbe61d8a 1747static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600
S		 1748{
1749 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1750 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1751
1752 switch (type) {
1753 case ATH9K_RESET_POWER_ON:
1754 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1755 case ATH9K_RESET_WARM:
1756 case ATH9K_RESET_COLD:
1757 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1758 default:
1759 return false;
1760 }
f078f209
LR		 1761}
1762
cbe61d8a 1763static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
f1dc5600 1764 enum ath9k_ht_macmode macmode)
f078f209 1765{
f1dc5600 1766 u32 phymode;
e7594072 1767 u32 enableDacFifo = 0;
f078f209 1768
e7594072
SB		 1769 if (AR_SREV_9285_10_OR_LATER(ah))
1770 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1771 AR_PHY_FC_ENABLE_DAC_FIFO);
1772
f1dc5600 1773 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
e7594072 1774 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
f1dc5600
S		 1775
1776 if (IS_CHAN_HT40(chan)) {
1777 phymode |= AR_PHY_FC_DYN2040_EN;
f078f209 1778
f1dc5600
S		 1779 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1780 (chan->chanmode == CHANNEL_G_HT40PLUS))
1781 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
f078f209 1782
2660b81a 1783 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
f1dc5600 1784 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
f078f209 1785 }
f1dc5600
S		 1786 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1787
1788 ath9k_hw_set11nmac2040(ah, macmode);
f078f209 1789
f1dc5600
S		 1790 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1791 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
f078f209
LR		 1792}
1793
cbe61d8a 1794static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1795 struct ath9k_channel *chan)
f078f209 1796{
42abfbee 1797 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1798 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1799 return false;
1800 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1801 return false;
f078f209 1802
1adc93c8 1803 if (!ath9k_hw_setpower_nolock(ah, ATH9K_PM_AWAKE))
f1dc5600 1804 return false;
f078f209 1805
2660b81a 1806 ah->chip_fullsleep = false;
f1dc5600 1807 ath9k_hw_init_pll(ah, chan);
f1dc5600 1808 ath9k_hw_set_rfmode(ah, chan);
f078f209 1809
f1dc5600 1810 return true;
f078f209
LR		 1811}
1812
cbe61d8a 1813static bool ath9k_hw_channel_change(struct ath_hw *ah,
f1dc5600
S		 1814 struct ath9k_channel *chan,
1815 enum ath9k_ht_macmode macmode)
f078f209 1816{
608b88cb 1817 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
5f8e077c 1818 struct ieee80211_channel *channel = chan->chan;
f078f209 1819 u32 synthDelay, qnum;
f078f209
LR		 1820
1821 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1822 if (ath9k_hw_numtxpending(ah, qnum)) {
4d6b228d 1823 DPRINTF(ah, ATH_DBG_QUEUE,
04bd4638 1824 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1825 return false;
1826 }
1827 }
1828
1829 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1830 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
0caa7b14 1831 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
4d6b228d 1832 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1833 "Could not kill baseband RX\n");
f078f209
LR		 1834 return false;
1835 }
1836
1837 ath9k_hw_set_regs(ah, chan, macmode);
1838
1839 if (AR_SREV_9280_10_OR_LATER(ah)) {
8fbff4b8 1840 ath9k_hw_ar9280_set_channel(ah, chan);
f078f209
LR		 1841 } else {
1842 if (!(ath9k_hw_set_channel(ah, chan))) {
4d6b228d 1843 DPRINTF(ah, ATH_DBG_FATAL,
d8baa939 1844 "Failed to set channel\n");
f078f209
LR		 1845 return false;
1846 }
1847 }
1848
8fbff4b8 1849 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1850 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1851 channel->max_antenna_gain * 2,
1852 channel->max_power * 2,
1853 min((u32) MAX_RATE_POWER,
608b88cb 1854 (u32) regulatory->power_limit));
f078f209
LR		 1855
1856 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
788a3d6f 1857 if (IS_CHAN_B(chan))
f078f209
LR		 1858 synthDelay = (4 * synthDelay) / 22;
1859 else
1860 synthDelay /= 10;
1861
1862 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1863
1864 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1865
f1dc5600
S		 1866 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1867 ath9k_hw_set_delta_slope(ah, chan);
1868
1869 if (AR_SREV_9280_10_OR_LATER(ah))
1870 ath9k_hw_9280_spur_mitigate(ah, chan);
1871 else
1872 ath9k_hw_spur_mitigate(ah, chan);
1873
1874 if (!chan->oneTimeCalsDone)
1875 chan->oneTimeCalsDone = true;
1876
1877 return true;
1878}
1879
cbe61d8a 1880static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 1881{
1882 int bb_spur = AR_NO_SPUR;
1883 int freq;
1884 int bin, cur_bin;
1885 int bb_spur_off, spur_subchannel_sd;
1886 int spur_freq_sd;
1887 int spur_delta_phase;
1888 int denominator;
1889 int upper, lower, cur_vit_mask;
1890 int tmp, newVal;
1891 int i;
1892 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1893 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1894 };
1895 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1896 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1897 };
1898 int inc[4] = { 0, 100, 0, 0 };
1899 struct chan_centers centers;
1900
1901 int8_t mask_m[123];
1902 int8_t mask_p[123];
1903 int8_t mask_amt;
1904 int tmp_mask;
1905 int cur_bb_spur;
1906 bool is2GHz = IS_CHAN_2GHZ(chan);
1907
1908 memset(&mask_m, 0, sizeof(int8_t) * 123);
1909 memset(&mask_p, 0, sizeof(int8_t) * 123);
1910
1911 ath9k_hw_get_channel_centers(ah, chan, &centers);
1912 freq = centers.synth_center;
1913
2660b81a 1914 ah->config.spurmode = SPUR_ENABLE_EEPROM;
f1dc5600 1915 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
f74df6fb 1916 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
f1dc5600
S		 1917
1918 if (is2GHz)
1919 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1920 else
1921 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1922
1923 if (AR_NO_SPUR == cur_bb_spur)
1924 break;
1925 cur_bb_spur = cur_bb_spur - freq;
1926
1927 if (IS_CHAN_HT40(chan)) {
1928 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1929 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1930 bb_spur = cur_bb_spur;
1931 break;
1932 }
1933 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1934 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1935 bb_spur = cur_bb_spur;
1936 break;
1937 }
1938 }
1939
1940 if (AR_NO_SPUR == bb_spur) {
1941 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1942 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1943 return;
1944 } else {
1945 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1946 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1947 }
1948
1949 bin = bb_spur * 320;
1950
1951 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1952
1953 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1954 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1955 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1956 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1957 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1958
1959 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1960 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1961 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1962 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1963 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1964 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1965
1966 if (IS_CHAN_HT40(chan)) {
1967 if (bb_spur < 0) {
1968 spur_subchannel_sd = 1;
1969 bb_spur_off = bb_spur + 10;
1970 } else {
1971 spur_subchannel_sd = 0;
1972 bb_spur_off = bb_spur - 10;
1973 }
1974 } else {
1975 spur_subchannel_sd = 0;
1976 bb_spur_off = bb_spur;
1977 }
1978
1979 if (IS_CHAN_HT40(chan))
1980 spur_delta_phase =
1981 ((bb_spur * 262144) /
1982 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1983 else
1984 spur_delta_phase =
1985 ((bb_spur * 524288) /
1986 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1987
1988 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1989 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1990
1991 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1992 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1993 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1994 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1995
1996 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1997 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1998
1999 cur_bin = -6000;
2000 upper = bin + 100;
2001 lower = bin - 100;
2002
2003 for (i = 0; i < 4; i++) {
2004 int pilot_mask = 0;
2005 int chan_mask = 0;
2006 int bp = 0;
2007 for (bp = 0; bp < 30; bp++) {
2008 if ((cur_bin > lower) && (cur_bin < upper)) {
2009 pilot_mask = pilot_mask | 0x1 << bp;
2010 chan_mask = chan_mask | 0x1 << bp;
2011 }
2012 cur_bin += 100;
2013 }
2014 cur_bin += inc[i];
2015 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2016 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2017 }
2018
2019 cur_vit_mask = 6100;
2020 upper = bin + 120;
2021 lower = bin - 120;
2022
2023 for (i = 0; i < 123; i++) {
2024 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2025
2026 /* workaround for gcc bug #37014 */
a085ff71 2027 volatile int tmp_v = abs(cur_vit_mask - bin);
f1dc5600 2028
a085ff71 2029 if (tmp_v < 75)
f1dc5600
S		 2030 mask_amt = 1;
2031 else
2032 mask_amt = 0;
2033 if (cur_vit_mask < 0)
2034 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2035 else
2036 mask_p[cur_vit_mask / 100] = mask_amt;
2037 }
2038 cur_vit_mask -= 100;
2039 }
2040
2041 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2042 | (mask_m[48] << 26) | (mask_m[49] << 24)
2043 | (mask_m[50] << 22) | (mask_m[51] << 20)
2044 | (mask_m[52] << 18) | (mask_m[53] << 16)
2045 | (mask_m[54] << 14) | (mask_m[55] << 12)
2046 | (mask_m[56] << 10) | (mask_m[57] << 8)
2047 | (mask_m[58] << 6) | (mask_m[59] << 4)
2048 | (mask_m[60] << 2) | (mask_m[61] << 0);
2049 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2050 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2051
2052 tmp_mask = (mask_m[31] << 28)
2053 | (mask_m[32] << 26) | (mask_m[33] << 24)
2054 | (mask_m[34] << 22) | (mask_m[35] << 20)
2055 | (mask_m[36] << 18) | (mask_m[37] << 16)
2056 | (mask_m[48] << 14) | (mask_m[39] << 12)
2057 | (mask_m[40] << 10) | (mask_m[41] << 8)
2058 | (mask_m[42] << 6) | (mask_m[43] << 4)
2059 | (mask_m[44] << 2) | (mask_m[45] << 0);
2060 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2061 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2062
2063 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2064 | (mask_m[18] << 26) | (mask_m[18] << 24)
2065 | (mask_m[20] << 22) | (mask_m[20] << 20)
2066 | (mask_m[22] << 18) | (mask_m[22] << 16)
2067 | (mask_m[24] << 14) | (mask_m[24] << 12)
2068 | (mask_m[25] << 10) | (mask_m[26] << 8)
2069 | (mask_m[27] << 6) | (mask_m[28] << 4)
2070 | (mask_m[29] << 2) | (mask_m[30] << 0);
2071 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2072 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2073
2074 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2075 | (mask_m[2] << 26) | (mask_m[3] << 24)
2076 | (mask_m[4] << 22) | (mask_m[5] << 20)
2077 | (mask_m[6] << 18) | (mask_m[7] << 16)
2078 | (mask_m[8] << 14) | (mask_m[9] << 12)
2079 | (mask_m[10] << 10) | (mask_m[11] << 8)
2080 | (mask_m[12] << 6) | (mask_m[13] << 4)
2081 | (mask_m[14] << 2) | (mask_m[15] << 0);
2082 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2083 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2084
2085 tmp_mask = (mask_p[15] << 28)
2086 | (mask_p[14] << 26) | (mask_p[13] << 24)
2087 | (mask_p[12] << 22) | (mask_p[11] << 20)
2088 | (mask_p[10] << 18) | (mask_p[9] << 16)
2089 | (mask_p[8] << 14) | (mask_p[7] << 12)
2090 | (mask_p[6] << 10) | (mask_p[5] << 8)
2091 | (mask_p[4] << 6) | (mask_p[3] << 4)
2092 | (mask_p[2] << 2) | (mask_p[1] << 0);
2093 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2094 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 2095
f1dc5600
S		 2096 tmp_mask = (mask_p[30] << 28)
2097 | (mask_p[29] << 26) | (mask_p[28] << 24)
2098 | (mask_p[27] << 22) | (mask_p[26] << 20)
2099 | (mask_p[25] << 18) | (mask_p[24] << 16)
2100 | (mask_p[23] << 14) | (mask_p[22] << 12)
2101 | (mask_p[21] << 10) | (mask_p[20] << 8)
2102 | (mask_p[19] << 6) | (mask_p[18] << 4)
2103 | (mask_p[17] << 2) | (mask_p[16] << 0);
2104 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2105 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 2106
f1dc5600
S		 2107 tmp_mask = (mask_p[45] << 28)
2108 | (mask_p[44] << 26) | (mask_p[43] << 24)
2109 | (mask_p[42] << 22) | (mask_p[41] << 20)
2110 | (mask_p[40] << 18) | (mask_p[39] << 16)
2111 | (mask_p[38] << 14) | (mask_p[37] << 12)
2112 | (mask_p[36] << 10) | (mask_p[35] << 8)
2113 | (mask_p[34] << 6) | (mask_p[33] << 4)
2114 | (mask_p[32] << 2) | (mask_p[31] << 0);
2115 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2116 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 2117
f1dc5600
S		 2118 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2119 | (mask_p[59] << 26) | (mask_p[58] << 24)
2120 | (mask_p[57] << 22) | (mask_p[56] << 20)
2121 | (mask_p[55] << 18) | (mask_p[54] << 16)
2122 | (mask_p[53] << 14) | (mask_p[52] << 12)
2123 | (mask_p[51] << 10) | (mask_p[50] << 8)
2124 | (mask_p[49] << 6) | (mask_p[48] << 4)
2125 | (mask_p[47] << 2) | (mask_p[46] << 0);
2126 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2127 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 2128}
2129
cbe61d8a 2130static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
f078f209 2131{
f1dc5600
S		 2132 int bb_spur = AR_NO_SPUR;
2133 int bin, cur_bin;
2134 int spur_freq_sd;
2135 int spur_delta_phase;
2136 int denominator;
2137 int upper, lower, cur_vit_mask;
2138 int tmp, new;
2139 int i;
2140 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2141 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2142 };
2143 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2144 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2145 };
2146 int inc[4] = { 0, 100, 0, 0 };
f078f209 2147
f1dc5600
S		 2148 int8_t mask_m[123];
2149 int8_t mask_p[123];
2150 int8_t mask_amt;
2151 int tmp_mask;
2152 int cur_bb_spur;
2153 bool is2GHz = IS_CHAN_2GHZ(chan);
f078f209 2154
f1dc5600
S		 2155 memset(&mask_m, 0, sizeof(int8_t) * 123);
2156 memset(&mask_p, 0, sizeof(int8_t) * 123);
f078f209 2157
f1dc5600 2158 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
f74df6fb 2159 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
f1dc5600
S		 2160 if (AR_NO_SPUR == cur_bb_spur)
2161 break;
2162 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2163 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2164 bb_spur = cur_bb_spur;
2165 break;
2166 }
2167 }
f078f209 2168
f1dc5600
S		 2169 if (AR_NO_SPUR == bb_spur)
2170 return;
f078f209 2171
f1dc5600 2172 bin = bb_spur * 32;
f078f209 2173
f1dc5600
S		 2174 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2175 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2176 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2177 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2178 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
f078f209 2179
f1dc5600 2180 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
f078f209 2181
f1dc5600
S		 2182 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2183 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2184 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2185 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2186 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2187 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
f078f209 2188
f1dc5600
S		 2189 spur_delta_phase = ((bb_spur * 524288) / 100) &
2190 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
f078f209 2191
f1dc5600
S		 2192 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2193 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
f078f209 2194
f1dc5600
S		 2195 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2196 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2197 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2198 REG_WRITE(ah, AR_PHY_TIMING11, new);
f078f209 2199
f1dc5600
S		 2200 cur_bin = -6000;
2201 upper = bin + 100;
2202 lower = bin - 100;
f078f209 2203
f1dc5600
S		 2204 for (i = 0; i < 4; i++) {
2205 int pilot_mask = 0;
2206 int chan_mask = 0;
2207 int bp = 0;
2208 for (bp = 0; bp < 30; bp++) {
2209 if ((cur_bin > lower) && (cur_bin < upper)) {
2210 pilot_mask = pilot_mask | 0x1 << bp;
2211 chan_mask = chan_mask | 0x1 << bp;
2212 }
2213 cur_bin += 100;
2214 }
2215 cur_bin += inc[i];
2216 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2217 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
f078f209 2218 }
f078f209 2219
f1dc5600
S		 2220 cur_vit_mask = 6100;
2221 upper = bin + 120;
2222 lower = bin - 120;
f078f209 2223
f1dc5600
S		 2224 for (i = 0; i < 123; i++) {
2225 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
f078f209 2226
f1dc5600 2227 /* workaround for gcc bug #37014 */
a085ff71 2228 volatile int tmp_v = abs(cur_vit_mask - bin);
f078f209 2229
a085ff71 2230 if (tmp_v < 75)
f1dc5600
S		 2231 mask_amt = 1;
2232 else
2233 mask_amt = 0;
2234 if (cur_vit_mask < 0)
2235 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2236 else
2237 mask_p[cur_vit_mask / 100] = mask_amt;
2238 }
2239 cur_vit_mask -= 100;
f078f209
LR		 2240 }
2241
f1dc5600
S		 2242 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2243 | (mask_m[48] << 26) | (mask_m[49] << 24)
2244 | (mask_m[50] << 22) | (mask_m[51] << 20)
2245 | (mask_m[52] << 18) | (mask_m[53] << 16)
2246 | (mask_m[54] << 14) | (mask_m[55] << 12)
2247 | (mask_m[56] << 10) | (mask_m[57] << 8)
2248 | (mask_m[58] << 6) | (mask_m[59] << 4)
2249 | (mask_m[60] << 2) | (mask_m[61] << 0);
2250 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2251 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
f078f209 2252
f1dc5600
S		 2253 tmp_mask = (mask_m[31] << 28)
2254 | (mask_m[32] << 26) | (mask_m[33] << 24)
2255 | (mask_m[34] << 22) | (mask_m[35] << 20)
2256 | (mask_m[36] << 18) | (mask_m[37] << 16)
2257 | (mask_m[48] << 14) | (mask_m[39] << 12)
2258 | (mask_m[40] << 10) | (mask_m[41] << 8)
2259 | (mask_m[42] << 6) | (mask_m[43] << 4)
2260 | (mask_m[44] << 2) | (mask_m[45] << 0);
2261 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2262 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
f078f209 2263
f1dc5600
S		 2264 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2265 | (mask_m[18] << 26) | (mask_m[18] << 24)
2266 | (mask_m[20] << 22) | (mask_m[20] << 20)
2267 | (mask_m[22] << 18) | (mask_m[22] << 16)
2268 | (mask_m[24] << 14) | (mask_m[24] << 12)
2269 | (mask_m[25] << 10) | (mask_m[26] << 8)
2270 | (mask_m[27] << 6) | (mask_m[28] << 4)
2271 | (mask_m[29] << 2) | (mask_m[30] << 0);
2272 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2273 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
f078f209 2274
f1dc5600
S		 2275 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2276 | (mask_m[2] << 26) | (mask_m[3] << 24)
2277 | (mask_m[4] << 22) | (mask_m[5] << 20)
2278 | (mask_m[6] << 18) | (mask_m[7] << 16)
2279 | (mask_m[8] << 14) | (mask_m[9] << 12)
2280 | (mask_m[10] << 10) | (mask_m[11] << 8)
2281 | (mask_m[12] << 6) | (mask_m[13] << 4)
2282 | (mask_m[14] << 2) | (mask_m[15] << 0);
2283 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2284 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
f078f209 2285
f1dc5600
S		 2286 tmp_mask = (mask_p[15] << 28)
2287 | (mask_p[14] << 26) | (mask_p[13] << 24)
2288 | (mask_p[12] << 22) | (mask_p[11] << 20)
2289 | (mask_p[10] << 18) | (mask_p[9] << 16)
2290 | (mask_p[8] << 14) | (mask_p[7] << 12)
2291 | (mask_p[6] << 10) | (mask_p[5] << 8)
2292 | (mask_p[4] << 6) | (mask_p[3] << 4)
2293 | (mask_p[2] << 2) | (mask_p[1] << 0);
2294 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2295 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
f078f209 2296
f1dc5600
S		 2297 tmp_mask = (mask_p[30] << 28)
2298 | (mask_p[29] << 26) | (mask_p[28] << 24)
2299 | (mask_p[27] << 22) | (mask_p[26] << 20)
2300 | (mask_p[25] << 18) | (mask_p[24] << 16)
2301 | (mask_p[23] << 14) | (mask_p[22] << 12)
2302 | (mask_p[21] << 10) | (mask_p[20] << 8)
2303 | (mask_p[19] << 6) | (mask_p[18] << 4)
2304 | (mask_p[17] << 2) | (mask_p[16] << 0);
2305 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2306 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
f078f209 2307
f1dc5600
S		 2308 tmp_mask = (mask_p[45] << 28)
2309 | (mask_p[44] << 26) | (mask_p[43] << 24)
2310 | (mask_p[42] << 22) | (mask_p[41] << 20)
2311 | (mask_p[40] << 18) | (mask_p[39] << 16)
2312 | (mask_p[38] << 14) | (mask_p[37] << 12)
2313 | (mask_p[36] << 10) | (mask_p[35] << 8)
2314 | (mask_p[34] << 6) | (mask_p[33] << 4)
2315 | (mask_p[32] << 2) | (mask_p[31] << 0);
2316 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2317 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
f078f209 2318
f1dc5600
S		 2319 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2320 | (mask_p[59] << 26) | (mask_p[58] << 24)
2321 | (mask_p[57] << 22) | (mask_p[56] << 20)
2322 | (mask_p[55] << 18) | (mask_p[54] << 16)
2323 | (mask_p[53] << 14) | (mask_p[52] << 12)
2324 | (mask_p[51] << 10) | (mask_p[50] << 8)
2325 | (mask_p[49] << 6) | (mask_p[48] << 4)
2326 | (mask_p[47] << 2) | (mask_p[46] << 0);
2327 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2328 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
f078f209
LR		 2329}
2330
3b319aae
JB		 2331static void ath9k_enable_rfkill(struct ath_hw *ah)
2332{
2333 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2334 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2335
2336 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2337 AR_GPIO_INPUT_MUX2_RFSILENT);
2338
2339 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2340 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2341}
2342
cbe61d8a 2343int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ae8d2858 2344 bool bChannelChange)
f078f209 2345{
f078f209 2346 u32 saveLedState;
ae8d2858 2347 struct ath_softc *sc = ah->ah_sc;
2660b81a 2348 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 2349 u32 saveDefAntenna;
2350 u32 macStaId1;
46fe782c 2351 u64 tsf = 0;
ae8d2858 2352 int i, rx_chainmask, r;
f078f209 2353
2660b81a
S		 2354 ah->extprotspacing = sc->ht_extprotspacing;
2355 ah->txchainmask = sc->tx_chainmask;
2356 ah->rxchainmask = sc->rx_chainmask;
f078f209 2357
1adc93c8 2358 if (!ath9k_hw_setpower_nolock(ah, ATH9K_PM_AWAKE))
ae8d2858 2359 return -EIO;
f078f209 2360
9ebef799 2361 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 2362 ath9k_hw_getnf(ah, curchan);
2363
2364 if (bChannelChange &&
2660b81a
S		 2365 (ah->chip_fullsleep != true) &&
2366 (ah->curchan != NULL) &&
2367 (chan->channel != ah->curchan->channel) &&
f078f209 2368 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 2369 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
0a475cc6
VT		 2370 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
2371 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
f078f209 2372
ae8d2858 2373 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2660b81a 2374 ath9k_hw_loadnf(ah, ah->curchan);
f078f209 2375 ath9k_hw_start_nfcal(ah);
ae8d2858 2376 return 0;
f078f209
LR		 2377 }
2378 }
2379
2380 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2381 if (saveDefAntenna == 0)
2382 saveDefAntenna = 1;
2383
2384 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2385
46fe782c
S		 2386 /* For chips on which RTC reset is done, save TSF before it gets cleared */
2387 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2388 tsf = ath9k_hw_gettsf64(ah);
2389
f078f209
LR		 2390 saveLedState = REG_READ(ah, AR_CFG_LED) &
2391 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2392 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2393
2394 ath9k_hw_mark_phy_inactive(ah);
2395
d7e7d229
LR		 2396 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2397 REG_WRITE(ah,
2398 AR9271_RESET_POWER_DOWN_CONTROL,
2399 AR9271_RADIO_RF_RST);
2400 udelay(50);
2401 }
2402
f078f209 2403 if (!ath9k_hw_chip_reset(ah, chan)) {
4d6b228d 2404 DPRINTF(ah, ATH_DBG_FATAL, "Chip reset failed\n");
ae8d2858 2405 return -EINVAL;
f078f209
LR		 2406 }
2407
d7e7d229
LR		 2408 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2409 ah->htc_reset_init = false;
2410 REG_WRITE(ah,
2411 AR9271_RESET_POWER_DOWN_CONTROL,
2412 AR9271_GATE_MAC_CTL);
2413 udelay(50);
2414 }
2415
46fe782c
S		 2416 /* Restore TSF */
2417 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2418 ath9k_hw_settsf64(ah, tsf);
2419
369391db
VT		 2420 if (AR_SREV_9280_10_OR_LATER(ah))
2421 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 2422
326bebbc 2423 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2424 /* Enable ASYNC FIFO */
2425 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2426 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2427 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2428 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2429 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2430 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2431 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2432 }
ae8d2858
LR		 2433 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2434 if (r)
2435 return r;
f078f209 2436
0ced0e17
JM		 2437 /* Setup MFP options for CCMP */
2438 if (AR_SREV_9280_20_OR_LATER(ah)) {
2439 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2440 * frames when constructing CCMP AAD. */
2441 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2442 0xc7ff);
2443 ah->sw_mgmt_crypto = false;
2444 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2445 /* Disable hardware crypto for management frames */
2446 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2447 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2448 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2449 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2450 ah->sw_mgmt_crypto = true;
2451 } else
2452 ah->sw_mgmt_crypto = true;
2453
f078f209
LR		 2454 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2455 ath9k_hw_set_delta_slope(ah, chan);
2456
2457 if (AR_SREV_9280_10_OR_LATER(ah))
2458 ath9k_hw_9280_spur_mitigate(ah, chan);
2459 else
2460 ath9k_hw_spur_mitigate(ah, chan);
2461
d6509151 2462 ah->eep_ops->set_board_values(ah, chan);
f078f209
LR		 2463
2464 ath9k_hw_decrease_chain_power(ah, chan);
2465
ba52da58
S		 2466 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2467 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
f078f209
LR		 2468 | macStaId1
2469 | AR_STA_ID1_RTS_USE_DEF
2660b81a 2470 | (ah->config.
60b67f51 2471 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a
S		 2472 | ah->sta_id1_defaults);
2473 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2474
ba52da58
S		 2475 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2476 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
f078f209
LR		 2477
2478 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2479
ba52da58
S		 2480 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2481 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2482 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209
LR		 2483
2484 REG_WRITE(ah, AR_ISR, ~0);
2485
2486 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2487
8fbff4b8
VT		 2488 if (AR_SREV_9280_10_OR_LATER(ah))
2489 ath9k_hw_ar9280_set_channel(ah, chan);
2490 else
ae8d2858
LR		 2491 if (!(ath9k_hw_set_channel(ah, chan)))
2492 return -EIO;
f078f209
LR		 2493
2494 for (i = 0; i < AR_NUM_DCU; i++)
2495 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2496
2660b81a
S		 2497 ah->intr_txqs = 0;
2498 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 2499 ath9k_hw_resettxqueue(ah, i);
2500
2660b81a 2501 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
f078f209
LR		 2502 ath9k_hw_init_qos(ah);
2503
2660b81a 2504 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d 2505 ath9k_enable_rfkill(ah);
3b319aae 2506
f078f209
LR		 2507 ath9k_hw_init_user_settings(ah);
2508
326bebbc 2509 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2510 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2511 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2512 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2513 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2514 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2515 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2516
2517 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2518 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2519
2520 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2521 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2522 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2523 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2524 }
326bebbc 2525 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 2526 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2527 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2528 }
2529
f078f209
LR		 2530 REG_WRITE(ah, AR_STA_ID1,
2531 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2532
2533 ath9k_hw_set_dma(ah);
2534
2535 REG_WRITE(ah, AR_OBS, 8);
2536
0ef1f168 2537 if (ah->config.intr_mitigation) {
f078f209
LR		 2538 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2539 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2540 }
2541
2542 ath9k_hw_init_bb(ah, chan);
2543
ae8d2858 2544 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 2545 return -EIO;
f078f209 2546
2660b81a 2547 rx_chainmask = ah->rxchainmask;
f078f209
LR		 2548 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2549 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2550 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2551 }
2552
2553 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2554
d7e7d229
LR		 2555 /*
2556 * For big endian systems turn on swapping for descriptors
2557 */
f078f209
LR		 2558 if (AR_SREV_9100(ah)) {
2559 u32 mask;
2560 mask = REG_READ(ah, AR_CFG);
2561 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
4d6b228d 2562 DPRINTF(ah, ATH_DBG_RESET,
04bd4638 2563 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 2564 } else {
2565 mask =
2566 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2567 REG_WRITE(ah, AR_CFG, mask);
4d6b228d 2568 DPRINTF(ah, ATH_DBG_RESET,
04bd4638 2569 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 2570 }
2571 } else {
d7e7d229
LR		 2572 /* Configure AR9271 target WLAN */
2573 if (AR_SREV_9271(ah))
2574 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
f078f209 2575#ifdef __BIG_ENDIAN
d7e7d229
LR		 2576 else
2577 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 2578#endif
2579 }
2580
766ec4a9 2581 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 2582 ath9k_hw_btcoex_enable(ah);
2583
ae8d2858 2584 return 0;
f078f209
LR		 2585}
2586
f1dc5600
S		 2587/************************/
2588/* Key Cache Management */
2589/************************/
f078f209 2590
cbe61d8a 2591bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
f078f209 2592{
f1dc5600 2593 u32 keyType;
f078f209 2594
2660b81a 2595 if (entry >= ah->caps.keycache_size) {
4d6b228d 2596 DPRINTF(ah, ATH_DBG_FATAL,
d8baa939 2597 "keychache entry %u out of range\n", entry);
f078f209
LR		 2598 return false;
2599 }
2600
f1dc5600 2601 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 2602
f1dc5600
S		 2603 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2604 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2605 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2606 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2607 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2608 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2609 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2610 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 2611
f1dc5600
S		 2612 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2613 u16 micentry = entry + 64;
f078f209 2614
f1dc5600
S		 2615 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2616 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2617 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2618 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 2619
f078f209
LR		 2620 }
2621
f078f209
LR		 2622 return true;
2623}
2624
cbe61d8a 2625bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
f078f209 2626{
f1dc5600 2627 u32 macHi, macLo;
f078f209 2628
2660b81a 2629 if (entry >= ah->caps.keycache_size) {
4d6b228d 2630 DPRINTF(ah, ATH_DBG_FATAL,
d8baa939 2631 "keychache entry %u out of range\n", entry);
f1dc5600 2632 return false;
f078f209
LR		 2633 }
2634
f1dc5600
S		 2635 if (mac != NULL) {
2636 macHi = (mac[5] << 8) | mac[4];
2637 macLo = (mac[3] << 24) |
2638 (mac[2] << 16) |
2639 (mac[1] << 8) |
2640 mac[0];
2641 macLo >>= 1;
2642 macLo |= (macHi & 1) << 31;
2643 macHi >>= 1;
f078f209 2644 } else {
f1dc5600 2645 macLo = macHi = 0;
f078f209 2646 }
f1dc5600
S		 2647 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2648 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
f078f209 2649
f1dc5600 2650 return true;
f078f209
LR		 2651}
2652
cbe61d8a 2653bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
f1dc5600 2654 const struct ath9k_keyval *k,
e0caf9ea 2655 const u8 *mac)
f078f209 2656{
2660b81a 2657 const struct ath9k_hw_capabilities *pCap = &ah->caps;
f1dc5600
S		 2658 u32 key0, key1, key2, key3, key4;
2659 u32 keyType;
f078f209 2660
f1dc5600 2661 if (entry >= pCap->keycache_size) {
4d6b228d 2662 DPRINTF(ah, ATH_DBG_FATAL,
d8baa939 2663 "keycache entry %u out of range\n", entry);
f1dc5600 2664 return false;
f078f209
LR		 2665 }
2666
f1dc5600
S		 2667 switch (k->kv_type) {
2668 case ATH9K_CIPHER_AES_OCB:
2669 keyType = AR_KEYTABLE_TYPE_AES;
2670 break;
2671 case ATH9K_CIPHER_AES_CCM:
2672 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
4d6b228d 2673 DPRINTF(ah, ATH_DBG_ANY,
04bd4638 2674 "AES-CCM not supported by mac rev 0x%x\n",
d535a42a 2675 ah->hw_version.macRev);
f1dc5600
S		 2676 return false;
2677 }
2678 keyType = AR_KEYTABLE_TYPE_CCM;
2679 break;
2680 case ATH9K_CIPHER_TKIP:
2681 keyType = AR_KEYTABLE_TYPE_TKIP;
2682 if (ATH9K_IS_MIC_ENABLED(ah)
2683 && entry + 64 >= pCap->keycache_size) {
4d6b228d 2684 DPRINTF(ah, ATH_DBG_ANY,
04bd4638 2685 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 2686 return false;
2687 }
2688 break;
2689 case ATH9K_CIPHER_WEP:
e31a16d6 2690 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
4d6b228d 2691 DPRINTF(ah, ATH_DBG_ANY,
04bd4638 2692 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 2693 return false;
2694 }
e31a16d6 2695 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
f1dc5600 2696 keyType = AR_KEYTABLE_TYPE_40;
e31a16d6 2697 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600
S		 2698 keyType = AR_KEYTABLE_TYPE_104;
2699 else
2700 keyType = AR_KEYTABLE_TYPE_128;
2701 break;
2702 case ATH9K_CIPHER_CLR:
2703 keyType = AR_KEYTABLE_TYPE_CLR;
2704 break;
2705 default:
4d6b228d 2706 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 2707 "cipher %u not supported\n", k->kv_type);
f1dc5600 2708 return false;
f078f209
LR		 2709 }
2710
e0caf9ea
JM		 2711 key0 = get_unaligned_le32(k->kv_val + 0);
2712 key1 = get_unaligned_le16(k->kv_val + 4);
2713 key2 = get_unaligned_le32(k->kv_val + 6);
2714 key3 = get_unaligned_le16(k->kv_val + 10);
2715 key4 = get_unaligned_le32(k->kv_val + 12);
e31a16d6 2716 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600 2717 key4 &= 0xff;
f078f209 2718
672903b3
JM		 2719 /*
2720 * Note: Key cache registers access special memory area that requires
2721 * two 32-bit writes to actually update the values in the internal
2722 * memory. Consequently, the exact order and pairs used here must be
2723 * maintained.
2724 */
2725
f1dc5600
S		 2726 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2727 u16 micentry = entry + 64;
f078f209 2728
672903b3
JM		 2729 /*
2730 * Write inverted key[47:0] first to avoid Michael MIC errors
2731 * on frames that could be sent or received at the same time.
2732 * The correct key will be written in the end once everything
2733 * else is ready.
2734 */
f1dc5600
S		 2735 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2736 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
672903b3
JM		 2737
2738 /* Write key[95:48] */
f1dc5600
S		 2739 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2740 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 2741
2742 /* Write key[127:96] and key type */
f1dc5600
S		 2743 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2744 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
672903b3
JM		 2745
2746 /* Write MAC address for the entry */
f1dc5600 2747 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 2748
2660b81a 2749 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
672903b3
JM		 2750 /*
2751 * TKIP uses two key cache entries:
2752 * Michael MIC TX/RX keys in the same key cache entry
2753 * (idx = main index + 64):
2754 * key0 [31:0] = RX key [31:0]
2755 * key1 [15:0] = TX key [31:16]
2756 * key1 [31:16] = reserved
2757 * key2 [31:0] = RX key [63:32]
2758 * key3 [15:0] = TX key [15:0]
2759 * key3 [31:16] = reserved
2760 * key4 [31:0] = TX key [63:32]
2761 */
f1dc5600 2762 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 2763
f1dc5600
S		 2764 mic0 = get_unaligned_le32(k->kv_mic + 0);
2765 mic2 = get_unaligned_le32(k->kv_mic + 4);
2766 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2767 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2768 mic4 = get_unaligned_le32(k->kv_txmic + 4);
672903b3
JM		 2769
2770 /* Write RX[31:0] and TX[31:16] */
f1dc5600
S		 2771 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2772 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
672903b3
JM		 2773
2774 /* Write RX[63:32] and TX[15:0] */
f1dc5600
S		 2775 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2776 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
672903b3
JM		 2777
2778 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 2779 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2780 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2781 AR_KEYTABLE_TYPE_CLR);
f078f209 2782
f1dc5600 2783 } else {
672903b3
JM		 2784 /*
2785 * TKIP uses four key cache entries (two for group
2786 * keys):
2787 * Michael MIC TX/RX keys are in different key cache
2788 * entries (idx = main index + 64 for TX and
2789 * main index + 32 + 96 for RX):
2790 * key0 [31:0] = TX/RX MIC key [31:0]
2791 * key1 [31:0] = reserved
2792 * key2 [31:0] = TX/RX MIC key [63:32]
2793 * key3 [31:0] = reserved
2794 * key4 [31:0] = reserved
2795 *
2796 * Upper layer code will call this function separately
2797 * for TX and RX keys when these registers offsets are
2798 * used.
2799 */
f1dc5600 2800 u32 mic0, mic2;
f078f209 2801
f1dc5600
S		 2802 mic0 = get_unaligned_le32(k->kv_mic + 0);
2803 mic2 = get_unaligned_le32(k->kv_mic + 4);
672903b3
JM		 2804
2805 /* Write MIC key[31:0] */
f1dc5600
S		 2806 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2807 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
672903b3
JM		 2808
2809 /* Write MIC key[63:32] */
f1dc5600
S		 2810 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2811 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
672903b3
JM		 2812
2813 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 2814 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2815 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2816 AR_KEYTABLE_TYPE_CLR);
2817 }
672903b3
JM		 2818
2819 /* MAC address registers are reserved for the MIC entry */
f1dc5600
S		 2820 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2821 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
672903b3
JM		 2822
2823 /*
2824 * Write the correct (un-inverted) key[47:0] last to enable
2825 * TKIP now that all other registers are set with correct
2826 * values.
2827 */
f1dc5600
S		 2828 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2829 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2830 } else {
672903b3 2831 /* Write key[47:0] */
f1dc5600
S		 2832 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2833 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
672903b3
JM		 2834
2835 /* Write key[95:48] */
f1dc5600
S		 2836 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2837 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 2838
2839 /* Write key[127:96] and key type */
f1dc5600
S		 2840 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2841 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 2842
672903b3 2843 /* Write MAC address for the entry */
f1dc5600
S		 2844 (void) ath9k_hw_keysetmac(ah, entry, mac);
2845 }
f078f209 2846
f078f209
LR		 2847 return true;
2848}
2849
cbe61d8a 2850bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
f078f209 2851{
2660b81a 2852 if (entry < ah->caps.keycache_size) {
f1dc5600
S		 2853 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2854 if (val & AR_KEYTABLE_VALID)
2855 return true;
2856 }
2857 return false;
f078f209
LR		 2858}
2859
f1dc5600
S		 2860/******************************/
2861/* Power Management (Chipset) */
2862/******************************/
2863
cbe61d8a 2864static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 2865{
f1dc5600
S		 2866 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2867 if (setChip) {
2868 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2869 AR_RTC_FORCE_WAKE_EN);
2870 if (!AR_SREV_9100(ah))
2871 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2872
d03a66c1 2873 REG_CLR_BIT(ah, (AR_RTC_RESET),
f1dc5600
S		 2874 AR_RTC_RESET_EN);
2875 }
f078f209
LR		 2876}
2877
cbe61d8a 2878static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 2879{
f1dc5600
S		 2880 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2881 if (setChip) {
2660b81a 2882 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 2883
f1dc5600
S		 2884 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2885 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2886 AR_RTC_FORCE_WAKE_ON_INT);
2887 } else {
2888 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2889 AR_RTC_FORCE_WAKE_EN);
f078f209 2890 }
f078f209 2891 }
f078f209
LR		 2892}
2893
cbe61d8a 2894static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 2895{
f1dc5600
S		 2896 u32 val;
2897 int i;
f078f209 2898
f1dc5600
S		 2899 if (setChip) {
2900 if ((REG_READ(ah, AR_RTC_STATUS) &
2901 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2902 if (ath9k_hw_set_reset_reg(ah,
2903 ATH9K_RESET_POWER_ON) != true) {
2904 return false;
2905 }
2906 }
2907 if (AR_SREV_9100(ah))
2908 REG_SET_BIT(ah, AR_RTC_RESET,
2909 AR_RTC_RESET_EN);
f078f209 2910
f1dc5600
S		 2911 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2912 AR_RTC_FORCE_WAKE_EN);
2913 udelay(50);
f078f209 2914
f1dc5600
S		 2915 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2916 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2917 if (val == AR_RTC_STATUS_ON)
2918 break;
2919 udelay(50);
2920 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2921 AR_RTC_FORCE_WAKE_EN);
f078f209 2922 }
f1dc5600 2923 if (i == 0) {
4d6b228d 2924 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 2925 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
f1dc5600 2926 return false;
f078f209 2927 }
f078f209
LR		 2928 }
2929
f1dc5600 2930 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2931
f1dc5600 2932 return true;
f078f209
LR		 2933}
2934
a91d75ae 2935bool ath9k_hw_setpower_nolock(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2936{
cbe61d8a 2937 int status = true, setChip = true;
f1dc5600
S		 2938 static const char *modes[] = {
2939 "AWAKE",
2940 "FULL-SLEEP",
2941 "NETWORK SLEEP",
2942 "UNDEFINED"
2943 };
f1dc5600 2944
cbdec975
GJ		 2945 if (ah->power_mode == mode)
2946 return status;
2947
4d6b228d 2948 DPRINTF(ah, ATH_DBG_RESET, "%s -> %s\n",
d8baa939 2949 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2950
2951 switch (mode) {
2952 case ATH9K_PM_AWAKE:
2953 status = ath9k_hw_set_power_awake(ah, setChip);
2954 break;
2955 case ATH9K_PM_FULL_SLEEP:
2956 ath9k_set_power_sleep(ah, setChip);
2660b81a 2957 ah->chip_fullsleep = true;
f1dc5600
S		 2958 break;
2959 case ATH9K_PM_NETWORK_SLEEP:
2960 ath9k_set_power_network_sleep(ah, setChip);
2961 break;
f078f209 2962 default:
4d6b228d 2963 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 2964 "Unknown power mode %u\n", mode);
f078f209
LR		 2965 return false;
2966 }
2660b81a 2967 ah->power_mode = mode;
f1dc5600
S		 2968
2969 return status;
f078f209
LR		 2970}
2971
24c1a280
LR		 2972/*
2973 * Helper for ASPM support.
2974 *
2975 * Disable PLL when in L0s as well as receiver clock when in L1.
2976 * This power saving option must be enabled through the SerDes.
2977 *
2978 * Programming the SerDes must go through the same 288 bit serial shift
2979 * register as the other analog registers. Hence the 9 writes.
2980 */
93b1b37f 2981void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
f078f209 2982{
f1dc5600 2983 u8 i;
93b1b37f 2984 u32 val;
f078f209 2985
2660b81a 2986 if (ah->is_pciexpress != true)
f1dc5600 2987 return;
f078f209 2988
24c1a280 2989 /* Do not touch SerDes registers */
2660b81a 2990 if (ah->config.pcie_powersave_enable == 2)
f1dc5600
S		 2991 return;
2992
24c1a280 2993 /* Nothing to do on restore for 11N */
93b1b37f
VN		 2994 if (!restore) {
2995 if (AR_SREV_9280_20_OR_LATER(ah)) {
2996 /*
2997 * AR9280 2.0 or later chips use SerDes values from the
2998 * initvals.h initialized depending on chipset during
2999 * ath9k_hw_init()
3000 */
3001 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
3002 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
3003 INI_RA(&ah->iniPcieSerdes, i, 1));
3004 }
3005 } else if (AR_SREV_9280(ah) &&
3006 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
3007 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
3008 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3009
3010 /* RX shut off when elecidle is asserted */
3011 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
3012 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
3013 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
3014
3015 /* Shut off CLKREQ active in L1 */
3016 if (ah->config.pcie_clock_req)
3017 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3018 else
3019 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
f1dc5600 3020
93b1b37f
VN		 3021 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3022 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3023 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
f1dc5600 3024
93b1b37f
VN		 3025 /* Load the new settings */
3026 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f1dc5600 3027
93b1b37f
VN		 3028 } else {
3029 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3030 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
f1dc5600 3031
93b1b37f
VN		 3032 /* RX shut off when elecidle is asserted */
3033 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3034 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3035 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
f1dc5600 3036
93b1b37f
VN		 3037 /*
3038 * Ignore ah->ah_config.pcie_clock_req setting for
3039 * pre-AR9280 11n
3040 */
3041 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
24c1a280 3042
93b1b37f
VN		 3043 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3044 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3045 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
24c1a280 3046
93b1b37f
VN		 3047 /* Load the new settings */
3048 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3049 }
24c1a280 3050
93b1b37f 3051 udelay(1000);
24c1a280 3052
93b1b37f
VN		 3053 /* set bit 19 to allow forcing of pcie core into L1 state */
3054 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
f078f209 3055
93b1b37f
VN		 3056 /* Several PCIe massages to ensure proper behaviour */
3057 if (ah->config.pcie_waen) {
3058 val = ah->config.pcie_waen;
3059 if (!power_off)
3060 val &= (~AR_WA_D3_L1_DISABLE);
3061 } else {
3062 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3063 AR_SREV_9287(ah)) {
3064 val = AR9285_WA_DEFAULT;
3065 if (!power_off)
3066 val &= (~AR_WA_D3_L1_DISABLE);
3067 } else if (AR_SREV_9280(ah)) {
3068 /*
3069 * On AR9280 chips bit 22 of 0x4004 needs to be
3070 * set otherwise card may disappear.
3071 */
3072 val = AR9280_WA_DEFAULT;
3073 if (!power_off)
3074 val &= (~AR_WA_D3_L1_DISABLE);
3075 } else
3076 val = AR_WA_DEFAULT;
3077 }
6d08b9b9 3078
93b1b37f
VN		 3079 REG_WRITE(ah, AR_WA, val);
3080 }
f1dc5600 3081
93b1b37f 3082 if (power_off) {
24c1a280 3083 /*
93b1b37f
VN		 3084 * Set PCIe workaround bits
3085 * bit 14 in WA register (disable L1) should only
3086 * be set when device enters D3 and be cleared
3087 * when device comes back to D0.
24c1a280 3088 */
93b1b37f
VN		 3089 if (ah->config.pcie_waen) {
3090 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
3091 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3092 } else {
3093 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3094 AR_SREV_9287(ah)) &&
3095 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
3096 (AR_SREV_9280(ah) &&
3097 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
3098 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3099 }
3100 }
f1dc5600 3101 }
f078f209
LR		 3102}
3103
f1dc5600
S		 3104/**********************/
3105/* Interrupt Handling */
3106/**********************/
3107
cbe61d8a 3108bool ath9k_hw_intrpend(struct ath_hw *ah)
f078f209
LR		 3109{
3110 u32 host_isr;
3111
3112 if (AR_SREV_9100(ah))
3113 return true;
3114
3115 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3116 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3117 return true;
3118
3119 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3120 if ((host_isr & AR_INTR_SYNC_DEFAULT)
3121 && (host_isr != AR_INTR_SPURIOUS))
3122 return true;
3123
3124 return false;
3125}
3126
cbe61d8a 3127bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
f078f209
LR		 3128{
3129 u32 isr = 0;
3130 u32 mask2 = 0;
2660b81a 3131 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209
LR		 3132 u32 sync_cause = 0;
3133 bool fatal_int = false;
3134
3135 if (!AR_SREV_9100(ah)) {
3136 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3137 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3138 == AR_RTC_STATUS_ON) {
3139 isr = REG_READ(ah, AR_ISR);
3140 }
3141 }
3142
f1dc5600
S		 3143 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3144 AR_INTR_SYNC_DEFAULT;
f078f209
LR		 3145
3146 *masked = 0;
3147
3148 if (!isr && !sync_cause)
3149 return false;
3150 } else {
3151 *masked = 0;
3152 isr = REG_READ(ah, AR_ISR);
3153 }
3154
3155 if (isr) {
f078f209
LR		 3156 if (isr & AR_ISR_BCNMISC) {
3157 u32 isr2;
3158 isr2 = REG_READ(ah, AR_ISR_S2);
3159 if (isr2 & AR_ISR_S2_TIM)
3160 mask2 |= ATH9K_INT_TIM;
3161 if (isr2 & AR_ISR_S2_DTIM)
3162 mask2 |= ATH9K_INT_DTIM;
3163 if (isr2 & AR_ISR_S2_DTIMSYNC)
3164 mask2 |= ATH9K_INT_DTIMSYNC;
3165 if (isr2 & (AR_ISR_S2_CABEND))
3166 mask2 |= ATH9K_INT_CABEND;
3167 if (isr2 & AR_ISR_S2_GTT)
3168 mask2 |= ATH9K_INT_GTT;
3169 if (isr2 & AR_ISR_S2_CST)
3170 mask2 |= ATH9K_INT_CST;
4af9cf4f
S		 3171 if (isr2 & AR_ISR_S2_TSFOOR)
3172 mask2 |= ATH9K_INT_TSFOOR;
f078f209
LR		 3173 }
3174
3175 isr = REG_READ(ah, AR_ISR_RAC);
3176 if (isr == 0xffffffff) {
3177 *masked = 0;
3178 return false;
3179 }
3180
3181 *masked = isr & ATH9K_INT_COMMON;
3182
0ef1f168 3183 if (ah->config.intr_mitigation) {
f078f209
LR		 3184 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3185 *masked |= ATH9K_INT_RX;
3186 }
3187
3188 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3189 *masked |= ATH9K_INT_RX;
3190 if (isr &
3191 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3192 AR_ISR_TXEOL)) {
3193 u32 s0_s, s1_s;
3194
3195 *masked |= ATH9K_INT_TX;
3196
3197 s0_s = REG_READ(ah, AR_ISR_S0_S);
2660b81a
S		 3198 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3199 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
f078f209
LR		 3200
3201 s1_s = REG_READ(ah, AR_ISR_S1_S);
2660b81a
S		 3202 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3203 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
f078f209
LR		 3204 }
3205
3206 if (isr & AR_ISR_RXORN) {
4d6b228d 3207 DPRINTF(ah, ATH_DBG_INTERRUPT,
04bd4638 3208 "receive FIFO overrun interrupt\n");
f078f209
LR		 3209 }
3210
3211 if (!AR_SREV_9100(ah)) {
60b67f51 3212 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 3213 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3214 if (isr5 & AR_ISR_S5_TIM_TIMER)
3215 *masked |= ATH9K_INT_TIM_TIMER;
3216 }
3217 }
3218
3219 *masked |= mask2;
3220 }
f1dc5600 3221
f078f209
LR		 3222 if (AR_SREV_9100(ah))
3223 return true;
f1dc5600 3224
ff155a45
VT		 3225 if (isr & AR_ISR_GENTMR) {
3226 u32 s5_s;
3227
3228 s5_s = REG_READ(ah, AR_ISR_S5_S);
3229 if (isr & AR_ISR_GENTMR) {
3230 ah->intr_gen_timer_trigger =
3231 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
3232
3233 ah->intr_gen_timer_thresh =
3234 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
3235
3236 if (ah->intr_gen_timer_trigger)
3237 *masked |= ATH9K_INT_GENTIMER;
3238
3239 }
3240 }
3241
f078f209
LR		 3242 if (sync_cause) {
3243 fatal_int =
3244 (sync_cause &
3245 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3246 ? true : false;
3247
3248 if (fatal_int) {
3249 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
4d6b228d 3250 DPRINTF(ah, ATH_DBG_ANY,
04bd4638 3251 "received PCI FATAL interrupt\n");
f078f209
LR		 3252 }
3253 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
4d6b228d 3254 DPRINTF(ah, ATH_DBG_ANY,
04bd4638 3255 "received PCI PERR interrupt\n");
f078f209 3256 }
a89bff9a 3257 *masked |= ATH9K_INT_FATAL;
f078f209
LR		 3258 }
3259 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
4d6b228d 3260 DPRINTF(ah, ATH_DBG_INTERRUPT,
04bd4638 3261 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
f078f209
LR		 3262 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3263 REG_WRITE(ah, AR_RC, 0);
3264 *masked |= ATH9K_INT_FATAL;
3265 }
3266 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
4d6b228d 3267 DPRINTF(ah, ATH_DBG_INTERRUPT,
04bd4638 3268 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
f078f209
LR		 3269 }
3270
3271 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3272 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3273 }
f1dc5600 3274
f078f209
LR		 3275 return true;
3276}
3277
cbe61d8a 3278enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
f078f209 3279{
2660b81a 3280 u32 omask = ah->mask_reg;
f078f209 3281 u32 mask, mask2;
2660b81a 3282 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 3283
4d6b228d 3284 DPRINTF(ah, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
f078f209
LR		 3285
3286 if (omask & ATH9K_INT_GLOBAL) {
4d6b228d 3287 DPRINTF(ah, ATH_DBG_INTERRUPT, "disable IER\n");
f078f209
LR		 3288 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3289 (void) REG_READ(ah, AR_IER);
3290 if (!AR_SREV_9100(ah)) {
3291 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3292 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3293
3294 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3295 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3296 }
3297 }
3298
3299 mask = ints & ATH9K_INT_COMMON;
3300 mask2 = 0;
3301
3302 if (ints & ATH9K_INT_TX) {
2660b81a 3303 if (ah->txok_interrupt_mask)
f078f209 3304 mask |= AR_IMR_TXOK;
2660b81a 3305 if (ah->txdesc_interrupt_mask)
f078f209 3306 mask |= AR_IMR_TXDESC;
2660b81a 3307 if (ah->txerr_interrupt_mask)
f078f209 3308 mask |= AR_IMR_TXERR;
2660b81a 3309 if (ah->txeol_interrupt_mask)
f078f209
LR		 3310 mask |= AR_IMR_TXEOL;
3311 }
3312 if (ints & ATH9K_INT_RX) {
3313 mask |= AR_IMR_RXERR;
0ef1f168 3314 if (ah->config.intr_mitigation)
f078f209
LR		 3315 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3316 else
3317 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
60b67f51 3318 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
f078f209
LR		 3319 mask |= AR_IMR_GENTMR;
3320 }
3321
3322 if (ints & (ATH9K_INT_BMISC)) {
3323 mask |= AR_IMR_BCNMISC;
3324 if (ints & ATH9K_INT_TIM)
3325 mask2 |= AR_IMR_S2_TIM;
3326 if (ints & ATH9K_INT_DTIM)
3327 mask2 |= AR_IMR_S2_DTIM;
3328 if (ints & ATH9K_INT_DTIMSYNC)
3329 mask2 |= AR_IMR_S2_DTIMSYNC;
3330 if (ints & ATH9K_INT_CABEND)
4af9cf4f
S		 3331 mask2 |= AR_IMR_S2_CABEND;
3332 if (ints & ATH9K_INT_TSFOOR)
3333 mask2 |= AR_IMR_S2_TSFOOR;
f078f209
LR		 3334 }
3335
3336 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3337 mask |= AR_IMR_BCNMISC;
3338 if (ints & ATH9K_INT_GTT)
3339 mask2 |= AR_IMR_S2_GTT;
3340 if (ints & ATH9K_INT_CST)
3341 mask2 |= AR_IMR_S2_CST;
3342 }
3343
4d6b228d 3344 DPRINTF(ah, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
f078f209
LR		 3345 REG_WRITE(ah, AR_IMR, mask);
3346 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3347 AR_IMR_S2_DTIM |
3348 AR_IMR_S2_DTIMSYNC |
3349 AR_IMR_S2_CABEND |
3350 AR_IMR_S2_CABTO |
3351 AR_IMR_S2_TSFOOR |
3352 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3353 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2660b81a 3354 ah->mask_reg = ints;
f078f209 3355
60b67f51 3356 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
f078f209
LR		 3357 if (ints & ATH9K_INT_TIM_TIMER)
3358 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3359 else
3360 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3361 }
3362
3363 if (ints & ATH9K_INT_GLOBAL) {
4d6b228d 3364 DPRINTF(ah, ATH_DBG_INTERRUPT, "enable IER\n");
f078f209
LR		 3365 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3366 if (!AR_SREV_9100(ah)) {
3367 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3368 AR_INTR_MAC_IRQ);
3369 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3370
3371
3372 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3373 AR_INTR_SYNC_DEFAULT);
3374 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3375 AR_INTR_SYNC_DEFAULT);
3376 }
4d6b228d 3377 DPRINTF(ah, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
f078f209
LR		 3378 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3379 }
3380
3381 return omask;
3382}
3383
f1dc5600
S		 3384/*******************/
3385/* Beacon Handling */
3386/*******************/
3387
cbe61d8a 3388void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 3389{
f078f209
LR		 3390 int flags = 0;
3391
2660b81a 3392 ah->beacon_interval = beacon_period;
f078f209 3393
2660b81a 3394 switch (ah->opmode) {
d97809db
CM		 3395 case NL80211_IFTYPE_STATION:
3396 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 3397 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3398 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3399 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3400 flags |= AR_TBTT_TIMER_EN;
3401 break;
d97809db 3402 case NL80211_IFTYPE_ADHOC:
9cb5412b 3403 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 3404 REG_SET_BIT(ah, AR_TXCFG,
3405 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3406 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3407 TU_TO_USEC(next_beacon +
2660b81a
S		 3408 (ah->atim_window ? ah->
3409 atim_window : 1)));
f078f209 3410 flags |= AR_NDP_TIMER_EN;
d97809db 3411 case NL80211_IFTYPE_AP:
f078f209
LR		 3412 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3413 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3414 TU_TO_USEC(next_beacon -
2660b81a 3415 ah->config.
60b67f51 3416 dma_beacon_response_time));
f078f209
LR		 3417 REG_WRITE(ah, AR_NEXT_SWBA,
3418 TU_TO_USEC(next_beacon -
2660b81a 3419 ah->config.
60b67f51 3420 sw_beacon_response_time));
f078f209
LR		 3421 flags |=
3422 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3423 break;
d97809db 3424 default:
4d6b228d 3425 DPRINTF(ah, ATH_DBG_BEACON,
d97809db 3426 "%s: unsupported opmode: %d\n",
2660b81a 3427 __func__, ah->opmode);
d97809db
CM		 3428 return;
3429 break;
f078f209
LR		 3430 }
3431
3432 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3433 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3434 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3435 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3436
3437 beacon_period &= ~ATH9K_BEACON_ENA;
3438 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3439 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3440 ath9k_hw_reset_tsf(ah);
3441 }
3442
3443 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3444}
3445
cbe61d8a 3446void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 3447 const struct ath9k_beacon_state *bs)
f078f209
LR		 3448{
3449 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 3450 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209
LR		 3451
3452 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3453
3454 REG_WRITE(ah, AR_BEACON_PERIOD,
3455 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3456 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3457 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3458
3459 REG_RMW_FIELD(ah, AR_RSSI_THR,
3460 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3461
3462 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3463
3464 if (bs->bs_sleepduration > beaconintval)
3465 beaconintval = bs->bs_sleepduration;
3466
3467 dtimperiod = bs->bs_dtimperiod;
3468 if (bs->bs_sleepduration > dtimperiod)
3469 dtimperiod = bs->bs_sleepduration;
3470
3471 if (beaconintval == dtimperiod)
3472 nextTbtt = bs->bs_nextdtim;
3473 else
3474 nextTbtt = bs->bs_nexttbtt;
3475
4d6b228d
LR		 3476 DPRINTF(ah, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3477 DPRINTF(ah, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3478 DPRINTF(ah, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3479 DPRINTF(ah, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 3480
f1dc5600
S		 3481 REG_WRITE(ah, AR_NEXT_DTIM,
3482 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3483 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 3484
f1dc5600
S		 3485 REG_WRITE(ah, AR_SLEEP1,
3486 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3487 | AR_SLEEP1_ASSUME_DTIM);
f078f209 3488
f1dc5600
S		 3489 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3490 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3491 else
3492 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 3493
f1dc5600
S		 3494 REG_WRITE(ah, AR_SLEEP2,
3495 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 3496
f1dc5600
S		 3497 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3498 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 3499
f1dc5600
S		 3500 REG_SET_BIT(ah, AR_TIMER_MODE,
3501 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3502 AR_DTIM_TIMER_EN);
f078f209 3503
4af9cf4f
S		 3504 /* TSF Out of Range Threshold */
3505 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209
LR		 3506}
3507
f1dc5600
S		 3508/*******************/
3509/* HW Capabilities */
3510/*******************/
3511
eef7a574 3512void ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 3513{
2660b81a 3514 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 3515 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
766ec4a9 3516 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
608b88cb 3517
f1dc5600 3518 u16 capField = 0, eeval;
f078f209 3519
f74df6fb 3520 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 3521 regulatory->current_rd = eeval;
f078f209 3522
f74df6fb 3523 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
fec0de11
S		 3524 if (AR_SREV_9285_10_OR_LATER(ah))
3525 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 3526 regulatory->current_rd_ext = eeval;
f078f209 3527
f74df6fb 3528 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 3529
2660b81a 3530 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 3531 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 3532 if (regulatory->current_rd == 0x64 ||
3533 regulatory->current_rd == 0x65)
3534 regulatory->current_rd += 5;
3535 else if (regulatory->current_rd == 0x41)
3536 regulatory->current_rd = 0x43;
4d6b228d 3537 DPRINTF(ah, ATH_DBG_REGULATORY,
608b88cb 3538 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 3539 }
f078f209 3540
f74df6fb 3541 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
f1dc5600 3542 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 3543
f1dc5600
S		 3544 if (eeval & AR5416_OPFLAGS_11A) {
3545 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2660b81a 3546 if (ah->config.ht_enable) {
f1dc5600
S		 3547 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3548 set_bit(ATH9K_MODE_11NA_HT20,
3549 pCap->wireless_modes);
3550 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3551 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3552 pCap->wireless_modes);
3553 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3554 pCap->wireless_modes);
3555 }
f078f209 3556 }
f078f209
LR		 3557 }
3558
f1dc5600 3559 if (eeval & AR5416_OPFLAGS_11G) {
f1dc5600 3560 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2660b81a 3561 if (ah->config.ht_enable) {
f1dc5600
S		 3562 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3563 set_bit(ATH9K_MODE_11NG_HT20,
3564 pCap->wireless_modes);
3565 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3566 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3567 pCap->wireless_modes);
3568 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3569 pCap->wireless_modes);
3570 }
3571 }
f078f209 3572 }
f1dc5600 3573
f74df6fb 3574 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 3575 /*
3576 * For AR9271 we will temporarilly uses the rx chainmax as read from
3577 * the EEPROM.
3578 */
8147f5de 3579 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 3580 !(eeval & AR5416_OPFLAGS_11A) &&
3581 !(AR_SREV_9271(ah)))
3582 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de
S		 3583 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3584 else
d7e7d229 3585 /* Use rx_chainmask from EEPROM. */
8147f5de 3586 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 3587
d535a42a 3588 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2660b81a 3589 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 3590
f1dc5600
S		 3591 pCap->low_2ghz_chan = 2312;
3592 pCap->high_2ghz_chan = 2732;
f078f209 3593
f1dc5600
S		 3594 pCap->low_5ghz_chan = 4920;
3595 pCap->high_5ghz_chan = 6100;
f078f209 3596
f1dc5600
S		 3597 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3598 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3599 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 3600
f1dc5600
S		 3601 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3602 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3603 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 3604
2660b81a 3605 if (ah->config.ht_enable)
f1dc5600
S		 3606 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3607 else
3608 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 3609
f1dc5600
S		 3610 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3611 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3612 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3613 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 3614
f1dc5600
S		 3615 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3616 pCap->total_queues =
3617 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3618 else
3619 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 3620
f1dc5600
S		 3621 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3622 pCap->keycache_size =
3623 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3624 else
3625 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 3626
f1dc5600 3627 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
f1dc5600 3628 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 3629
cb33c412
SB		 3630 if (AR_SREV_9285_10_OR_LATER(ah))
3631 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3632 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 3633 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3634 else
3635 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 3636
f1dc5600
S		 3637 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3638 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3639 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3640 } else {
3641 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 3642 }
3643
f1dc5600
S		 3644 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3645
e97275cb 3646#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 3647 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3648 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3649 ah->rfkill_gpio =
3650 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3651 ah->rfkill_polarity =
3652 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 3653
3654 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 3655 }
f1dc5600 3656#endif
f078f209 3657
a3ca95fb 3658 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 3659
e7594072 3660 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 3661 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3662 else
3663 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 3664
608b88cb 3665 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 3666 pCap->reg_cap =
3667 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3668 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3669 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3670 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 3671 } else {
f1dc5600
S		 3672 pCap->reg_cap =
3673 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3674 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 3675 }
f078f209 3676
f1dc5600
S		 3677 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3678
3679 pCap->num_antcfg_5ghz =
f74df6fb 3680 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 3681 pCap->num_antcfg_2ghz =
f74df6fb 3682 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 3683
fe12946e 3684 if (AR_SREV_9280_10_OR_LATER(ah) &&
a36cfbca 3685 ath9k_hw_btcoex_supported(ah)) {
766ec4a9
LR		 3686 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3687 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
22f25d0d 3688
8c8f9ba7 3689 if (AR_SREV_9285(ah)) {
766ec4a9
LR		 3690 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3691 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
8c8f9ba7 3692 } else {
766ec4a9 3693 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
8c8f9ba7 3694 }
22f25d0d 3695 } else {
766ec4a9 3696 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 3697 }
f078f209
LR		 3698}
3699
cbe61d8a 3700bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3701 u32 capability, u32 *result)
f078f209 3702{
608b88cb 3703 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f1dc5600
S		 3704 switch (type) {
3705 case ATH9K_CAP_CIPHER:
3706 switch (capability) {
3707 case ATH9K_CIPHER_AES_CCM:
3708 case ATH9K_CIPHER_AES_OCB:
3709 case ATH9K_CIPHER_TKIP:
3710 case ATH9K_CIPHER_WEP:
3711 case ATH9K_CIPHER_MIC:
3712 case ATH9K_CIPHER_CLR:
3713 return true;
3714 default:
3715 return false;
3716 }
3717 case ATH9K_CAP_TKIP_MIC:
3718 switch (capability) {
3719 case 0:
3720 return true;
3721 case 1:
2660b81a 3722 return (ah->sta_id1_defaults &
f1dc5600
S		 3723 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3724 false;
3725 }
3726 case ATH9K_CAP_TKIP_SPLIT:
2660b81a 3727 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
f1dc5600 3728 false : true;
f1dc5600
S		 3729 case ATH9K_CAP_DIVERSITY:
3730 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3731 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3732 true : false;
f1dc5600
S		 3733 case ATH9K_CAP_MCAST_KEYSRCH:
3734 switch (capability) {
3735 case 0:
3736 return true;
3737 case 1:
3738 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3739 return false;
3740 } else {
2660b81a 3741 return (ah->sta_id1_defaults &
f1dc5600
S		 3742 AR_STA_ID1_MCAST_KSRCH) ? true :
3743 false;
3744 }
3745 }
3746 return false;
f1dc5600
S		 3747 case ATH9K_CAP_TXPOW:
3748 switch (capability) {
3749 case 0:
3750 return 0;
3751 case 1:
608b88cb 3752 *result = regulatory->power_limit;
f1dc5600
S		 3753 return 0;
3754 case 2:
608b88cb 3755 *result = regulatory->max_power_level;
f1dc5600
S		 3756 return 0;
3757 case 3:
608b88cb 3758 *result = regulatory->tp_scale;
f1dc5600
S		 3759 return 0;
3760 }
3761 return false;
8bd1d07f
SB		 3762 case ATH9K_CAP_DS:
3763 return (AR_SREV_9280_20_OR_LATER(ah) &&
3764 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3765 ? false : true;
f1dc5600
S		 3766 default:
3767 return false;
f078f209 3768 }
f078f209
LR		 3769}
3770
cbe61d8a 3771bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 3772 u32 capability, u32 setting, int *status)
f078f209 3773{
f1dc5600 3774 u32 v;
f078f209 3775
f1dc5600
S		 3776 switch (type) {
3777 case ATH9K_CAP_TKIP_MIC:
3778 if (setting)
2660b81a 3779 ah->sta_id1_defaults |=
f1dc5600
S		 3780 AR_STA_ID1_CRPT_MIC_ENABLE;
3781 else
2660b81a 3782 ah->sta_id1_defaults &=
f1dc5600
S		 3783 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3784 return true;
3785 case ATH9K_CAP_DIVERSITY:
3786 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3787 if (setting)
3788 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3789 else
3790 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3791 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3792 return true;
3793 case ATH9K_CAP_MCAST_KEYSRCH:
3794 if (setting)
2660b81a 3795 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3796 else
2660b81a 3797 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
f1dc5600 3798 return true;
f1dc5600
S		 3799 default:
3800 return false;
f078f209
LR		 3801 }
3802}
3803
f1dc5600
S		 3804/****************************/
3805/* GPIO / RFKILL / Antennae */
3806/****************************/
f078f209 3807
cbe61d8a 3808static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 3809 u32 gpio, u32 type)
3810{
3811 int addr;
3812 u32 gpio_shift, tmp;
f078f209 3813
f1dc5600
S		 3814 if (gpio > 11)
3815 addr = AR_GPIO_OUTPUT_MUX3;
3816 else if (gpio > 5)
3817 addr = AR_GPIO_OUTPUT_MUX2;
3818 else
3819 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 3820
f1dc5600 3821 gpio_shift = (gpio % 6) * 5;
f078f209 3822
f1dc5600
S		 3823 if (AR_SREV_9280_20_OR_LATER(ah)
3824 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3825 REG_RMW(ah, addr, (type << gpio_shift),
3826 (0x1f << gpio_shift));
f078f209 3827 } else {
f1dc5600
S		 3828 tmp = REG_READ(ah, addr);
3829 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3830 tmp &= ~(0x1f << gpio_shift);
3831 tmp |= (type << gpio_shift);
3832 REG_WRITE(ah, addr, tmp);
f078f209 3833 }
f078f209
LR		 3834}
3835
cbe61d8a 3836void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 3837{
f1dc5600 3838 u32 gpio_shift;
f078f209 3839
2660b81a 3840 ASSERT(gpio < ah->caps.num_gpio_pins);
f078f209 3841
f1dc5600 3842 gpio_shift = gpio << 1;
f078f209 3843
f1dc5600
S		 3844 REG_RMW(ah,
3845 AR_GPIO_OE_OUT,
3846 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3847 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209
LR		 3848}
3849
cbe61d8a 3850u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 3851{
cb33c412
SB		 3852#define MS_REG_READ(x, y) \
3853 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3854
2660b81a 3855 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 3856 return 0xffffffff;
f078f209 3857
ac88b6ec
VN		 3858 if (AR_SREV_9287_10_OR_LATER(ah))
3859 return MS_REG_READ(AR9287, gpio) != 0;
3860 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 3861 return MS_REG_READ(AR9285, gpio) != 0;
3862 else if (AR_SREV_9280_10_OR_LATER(ah))
3863 return MS_REG_READ(AR928X, gpio) != 0;
3864 else
3865 return MS_REG_READ(AR, gpio) != 0;
f078f209
LR		 3866}
3867
cbe61d8a 3868void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 3869 u32 ah_signal_type)
f078f209 3870{
f1dc5600 3871 u32 gpio_shift;
f078f209 3872
f1dc5600 3873 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 3874
f1dc5600 3875 gpio_shift = 2 * gpio;
f078f209 3876
f1dc5600
S		 3877 REG_RMW(ah,
3878 AR_GPIO_OE_OUT,
3879 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3880 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209
LR		 3881}
3882
cbe61d8a 3883void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 3884{
f1dc5600
S		 3885 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3886 AR_GPIO_BIT(gpio));
f078f209
LR		 3887}
3888
cbe61d8a 3889u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 3890{
f1dc5600 3891 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209
LR		 3892}
3893
cbe61d8a 3894void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 3895{
f1dc5600 3896 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209
LR		 3897}
3898
cbe61d8a 3899bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
f1dc5600
S		 3900 enum ath9k_ant_setting settings,
3901 struct ath9k_channel *chan,
3902 u8 *tx_chainmask,
3903 u8 *rx_chainmask,
3904 u8 *antenna_cfgd)
f078f209 3905{
f1dc5600 3906 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
f078f209 3907
f1dc5600
S		 3908 if (AR_SREV_9280(ah)) {
3909 if (!tx_chainmask_cfg) {
f078f209 3910
f1dc5600
S		 3911 tx_chainmask_cfg = *tx_chainmask;
3912 rx_chainmask_cfg = *rx_chainmask;
3913 }
f078f209 3914
f1dc5600
S		 3915 switch (settings) {
3916 case ATH9K_ANT_FIXED_A:
3917 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3918 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3919 *antenna_cfgd = true;
3920 break;
3921 case ATH9K_ANT_FIXED_B:
2660b81a 3922 if (ah->caps.tx_chainmask >
f1dc5600
S		 3923 ATH9K_ANTENNA1_CHAINMASK) {
3924 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3925 }
3926 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3927 *antenna_cfgd = true;
3928 break;
3929 case ATH9K_ANT_VARIABLE:
3930 *tx_chainmask = tx_chainmask_cfg;
3931 *rx_chainmask = rx_chainmask_cfg;
3932 *antenna_cfgd = true;
3933 break;
3934 default:
3935 break;
3936 }
3937 } else {
1cf6873a 3938 ah->config.diversity_control = settings;
f078f209 3939 }
f078f209 3940
f1dc5600 3941 return true;
f078f209
LR		 3942}
3943
f1dc5600
S		 3944/*********************/
3945/* General Operation */
3946/*********************/
3947
cbe61d8a 3948u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 3949{
f1dc5600
S		 3950 u32 bits = REG_READ(ah, AR_RX_FILTER);
3951 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 3952
f1dc5600
S		 3953 if (phybits & AR_PHY_ERR_RADAR)
3954 bits |= ATH9K_RX_FILTER_PHYRADAR;
3955 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3956 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 3957
f1dc5600 3958 return bits;
f078f209
LR		 3959}
3960
cbe61d8a 3961void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 3962{
f1dc5600 3963 u32 phybits;
f078f209 3964
7ea310be
S		 3965 REG_WRITE(ah, AR_RX_FILTER, bits);
3966
f1dc5600
S		 3967 phybits = 0;
3968 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3969 phybits |= AR_PHY_ERR_RADAR;
3970 if (bits & ATH9K_RX_FILTER_PHYERR)
3971 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3972 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 3973
f1dc5600
S		 3974 if (phybits)
3975 REG_WRITE(ah, AR_RXCFG,
3976 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3977 else
3978 REG_WRITE(ah, AR_RXCFG,
3979 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3980}
f078f209 3981
cbe61d8a 3982bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600
S		 3983{
3984 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3985}
f078f209 3986
cbe61d8a 3987bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 3988{
1adc93c8 3989 if (!ath9k_hw_setpower_nolock(ah, ATH9K_PM_AWAKE))
f1dc5600 3990 return false;
f078f209 3991
f1dc5600 3992 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
f078f209
LR		 3993}
3994
8fbff4b8 3995void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 3996{
608b88cb 3997 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 3998 struct ath9k_channel *chan = ah->curchan;
5f8e077c 3999 struct ieee80211_channel *channel = chan->chan;
f078f209 4000
608b88cb 4001 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 4002
8fbff4b8 4003 ah->eep_ops->set_txpower(ah, chan,
608b88cb 4004 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 4005 channel->max_antenna_gain * 2,
4006 channel->max_power * 2,
4007 min((u32) MAX_RATE_POWER,
608b88cb 4008 (u32) regulatory->power_limit));
6f255425
LR		 4009}
4010
cbe61d8a 4011void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
f078f209 4012{
ba52da58 4013 memcpy(ah->macaddr, mac, ETH_ALEN);
f078f209
LR		 4014}
4015
cbe61d8a 4016void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 4017{
2660b81a 4018 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209
LR		 4019}
4020
cbe61d8a 4021void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 4022{
f1dc5600
S		 4023 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
4024 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209
LR		 4025}
4026
ba52da58 4027void ath9k_hw_setbssidmask(struct ath_softc *sc)
f078f209 4028{
ba52da58
S		 4029 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
4030 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
f078f209
LR		 4031}
4032
ba52da58 4033void ath9k_hw_write_associd(struct ath_softc *sc)
f078f209 4034{
ba52da58
S		 4035 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
4036 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
4037 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209
LR		 4038}
4039
cbe61d8a 4040u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 4041{
f1dc5600 4042 u64 tsf;
f078f209 4043
f1dc5600
S		 4044 tsf = REG_READ(ah, AR_TSF_U32);
4045 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
f078f209 4046
f1dc5600
S		 4047 return tsf;
4048}
f078f209 4049
cbe61d8a 4050void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 4051{
27abe060 4052 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 4053 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060
AF		 4054}
4055
cbe61d8a 4056void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 4057{
f9b604f6
GJ		 4058 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
4059 AH_TSF_WRITE_TIMEOUT))
4d6b228d 4060 DPRINTF(ah, ATH_DBG_RESET,
f9b604f6
GJ		 4061 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
4062
f1dc5600
S		 4063 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
4064}
f078f209 4065
54e4cec6 4066void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 4067{
f1dc5600 4068 if (setting)
2660b81a 4069 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 4070 else
2660b81a 4071 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 4072}
f078f209 4073
cbe61d8a 4074bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f1dc5600 4075{
f1dc5600 4076 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
4d6b228d 4077 DPRINTF(ah, ATH_DBG_RESET, "bad slot time %u\n", us);
2660b81a 4078 ah->slottime = (u32) -1;
f1dc5600
S		 4079 return false;
4080 } else {
4081 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
2660b81a 4082 ah->slottime = us;
f1dc5600 4083 return true;
f078f209 4084 }
f1dc5600
S		 4085}
4086
cbe61d8a 4087void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
f1dc5600
S		 4088{
4089 u32 macmode;
4090
4091 if (mode == ATH9K_HT_MACMODE_2040 &&
2660b81a 4092 !ah->config.cwm_ignore_extcca)
f1dc5600
S		 4093 macmode = AR_2040_JOINED_RX_CLEAR;
4094 else
4095 macmode = 0;
f078f209 4096
f1dc5600 4097 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 4098}
ff155a45
VT		 4099
4100/* HW Generic timers configuration */
4101
4102static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
4103{
4104 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4105 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4106 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4107 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4108 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4109 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4110 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4111 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4112 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
4113 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
4114 AR_NDP2_TIMER_MODE, 0x0002},
4115 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
4116 AR_NDP2_TIMER_MODE, 0x0004},
4117 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
4118 AR_NDP2_TIMER_MODE, 0x0008},
4119 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
4120 AR_NDP2_TIMER_MODE, 0x0010},
4121 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
4122 AR_NDP2_TIMER_MODE, 0x0020},
4123 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
4124 AR_NDP2_TIMER_MODE, 0x0040},
4125 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
4126 AR_NDP2_TIMER_MODE, 0x0080}
4127};
4128
4129/* HW generic timer primitives */
4130
4131/* compute and clear index of rightmost 1 */
4132static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
4133{
4134 u32 b;
4135
4136 b = *mask;
4137 b &= (0-b);
4138 *mask &= ~b;
4139 b *= debruijn32;
4140 b >>= 27;
4141
4142 return timer_table->gen_timer_index[b];
4143}
4144
1773912b 4145u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 4146{
4147 return REG_READ(ah, AR_TSF_L32);
4148}
4149
4150struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
4151 void (*trigger)(void *),
4152 void (*overflow)(void *),
4153 void *arg,
4154 u8 timer_index)
4155{
4156 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4157 struct ath_gen_timer *timer;
4158
4159 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
4160
4161 if (timer == NULL) {
4162 printk(KERN_DEBUG "Failed to allocate memory"
4163 "for hw timer[%d]\n", timer_index);
4164 return NULL;
4165 }
4166
4167 /* allocate a hardware generic timer slot */
4168 timer_table->timers[timer_index] = timer;
4169 timer->index = timer_index;
4170 timer->trigger = trigger;
4171 timer->overflow = overflow;
4172 timer->arg = arg;
4173
4174 return timer;
4175}
4176
4177void ath_gen_timer_start(struct ath_hw *ah,
4178 struct ath_gen_timer *timer,
4179 u32 timer_next, u32 timer_period)
4180{
4181 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4182 u32 tsf;
4183
4184 BUG_ON(!timer_period);
4185
4186 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
4187
4188 tsf = ath9k_hw_gettsf32(ah);
4189
4d6b228d 4190 DPRINTF(ah, ATH_DBG_HWTIMER, "curent tsf %x period %x"
ff155a45
VT		 4191 "timer_next %x\n", tsf, timer_period, timer_next);
4192
4193 /*
4194 * Pull timer_next forward if the current TSF already passed it
4195 * because of software latency
4196 */
4197 if (timer_next < tsf)
4198 timer_next = tsf + timer_period;
4199
4200 /*
4201 * Program generic timer registers
4202 */
4203 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
4204 timer_next);
4205 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
4206 timer_period);
4207 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4208 gen_tmr_configuration[timer->index].mode_mask);
4209
4210 /* Enable both trigger and thresh interrupt masks */
4211 REG_SET_BIT(ah, AR_IMR_S5,
4212 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4213 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4214
4215 if ((ah->ah_sc->imask & ATH9K_INT_GENTIMER) == 0) {
4216 ath9k_hw_set_interrupts(ah, 0);
4217 ah->ah_sc->imask |= ATH9K_INT_GENTIMER;
4218 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
4219 }
4220}
4221
4222void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
4223{
4224 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4225
4226 if ((timer->index < AR_FIRST_NDP_TIMER) ||
4227 (timer->index >= ATH_MAX_GEN_TIMER)) {
4228 return;
4229 }
4230
4231 /* Clear generic timer enable bits. */
4232 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4233 gen_tmr_configuration[timer->index].mode_mask);
4234
4235 /* Disable both trigger and thresh interrupt masks */
4236 REG_CLR_BIT(ah, AR_IMR_S5,
4237 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4238 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4239
4240 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
4241
4242 /* if no timer is enabled, turn off interrupt mask */
4243 if (timer_table->timer_mask.val == 0) {
4244 ath9k_hw_set_interrupts(ah, 0);
4245 ah->ah_sc->imask &= ~ATH9K_INT_GENTIMER;
4246 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
4247 }
4248}
4249
4250void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
4251{
4252 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4253
4254 /* free the hardware generic timer slot */
4255 timer_table->timers[timer->index] = NULL;
4256 kfree(timer);
4257}
4258
4259/*
4260 * Generic Timer Interrupts handling
4261 */
4262void ath_gen_timer_isr(struct ath_hw *ah)
4263{
4264 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4265 struct ath_gen_timer *timer;
4266 u32 trigger_mask, thresh_mask, index;
4267
4268 /* get hardware generic timer interrupt status */
4269 trigger_mask = ah->intr_gen_timer_trigger;
4270 thresh_mask = ah->intr_gen_timer_thresh;
4271 trigger_mask &= timer_table->timer_mask.val;
4272 thresh_mask &= timer_table->timer_mask.val;
4273
4274 trigger_mask &= ~thresh_mask;
4275
4276 while (thresh_mask) {
4277 index = rightmost_index(timer_table, &thresh_mask);
4278 timer = timer_table->timers[index];
4279 BUG_ON(!timer);
4d6b228d 4280 DPRINTF(ah, ATH_DBG_HWTIMER,
ff155a45
VT		 4281 "TSF overflow for Gen timer %d\n", index);
4282 timer->overflow(timer->arg);
4283 }
4284
4285 while (trigger_mask) {
4286 index = rightmost_index(timer_table, &trigger_mask);
4287 timer = timer_table->timers[index];
4288 BUG_ON(!timer);
4d6b228d 4289 DPRINTF(ah, ATH_DBG_HWTIMER,
ff155a45
VT		 4290 "Gen timer[%d] trigger\n", index);
4291 timer->trigger(timer->arg);
4292 }
4293}
7b6840ab
VT		 4294
4295/*
4296 * Primitive to disable ASPM
4297 */
4298void ath_pcie_aspm_disable(struct ath_softc *sc)
4299{
4300 struct pci_dev *pdev = to_pci_dev(sc->dev);
4301 u8 aspm;
4302
4303 pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
4304 aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
4305 pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
4306}
Linux kernel - Deliverables
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