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ath9k: add support for endian swap of eeprom from platform data
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
09d8e315 20#include <linux/time.h>
c67ce339 21#include <linux/bitops.h>
f078f209
LR		 22#include <asm/unaligned.h>
23
af03abec 24#include "hw.h"
d70357d5 25#include "hw-ops.h"
b622a720 26#include "ar9003_mac.h"
f4701b5a 27#include "ar9003_mci.h"
362cd03f 28#include "ar9003_phy.h"
462e58f2 29#include "ath9k.h"
f078f209 30
cbe61d8a 31static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 32
7322fd19
LR		 33MODULE_AUTHOR("Atheros Communications");
34MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
35MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
36MODULE_LICENSE("Dual BSD/GPL");
37
dfdac8ac 38static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 39{
dfdac8ac 40 struct ath_common *common = ath9k_hw_common(ah);
e4744ec7 41 struct ath9k_channel *chan = ah->curchan;
dfdac8ac 42 unsigned int clockrate;
cbe61d8a 43
087b6ff6
FF		 44 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
45 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
46 clockrate = 117;
e4744ec7 47 else if (!chan) /* should really check for CCK instead */
dfdac8ac 48 clockrate = ATH9K_CLOCK_RATE_CCK;
e4744ec7 49 else if (IS_CHAN_2GHZ(chan))
dfdac8ac
FF		 50 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
51 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
52 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 53 else
dfdac8ac
FF		 54 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
55
beae416b
MN		 56 if (chan) {
57 if (IS_CHAN_HT40(chan))
58 clockrate *= 2;
e4744ec7 59 if (IS_CHAN_HALF_RATE(chan))
906c7205 60 clockrate /= 2;
e4744ec7 61 if (IS_CHAN_QUARTER_RATE(chan))
906c7205
FF		 62 clockrate /= 4;
63 }
64
dfdac8ac 65 common->clockrate = clockrate;
f1dc5600
S		 66}
67
cbe61d8a 68static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 69{
dfdac8ac 70 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 71
dfdac8ac 72 return usecs * common->clockrate;
f1dc5600 73}
f078f209 74
0caa7b14 75bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 76{
77 int i;
78
0caa7b14
S		 79 BUG_ON(timeout < AH_TIME_QUANTUM);
80
81 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 82 if ((REG_READ(ah, reg) & mask) == val)
83 return true;
84
85 udelay(AH_TIME_QUANTUM);
86 }
04bd4638 87
d2182b69 88 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 89 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
90 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 91
f1dc5600 92 return false;
f078f209 93}
7322fd19 94EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 95
7c5adc8d
FF		 96void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
97 int hw_delay)
98{
1a5e6326 99 hw_delay /= 10;
7c5adc8d
FF		 100
101 if (IS_CHAN_HALF_RATE(chan))
102 hw_delay *= 2;
103 else if (IS_CHAN_QUARTER_RATE(chan))
104 hw_delay *= 4;
105
106 udelay(hw_delay + BASE_ACTIVATE_DELAY);
107}
108
0166b4be 109void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
a9b6b256
FF		 110 int column, unsigned int *writecnt)
111{
112 int r;
113
114 ENABLE_REGWRITE_BUFFER(ah);
115 for (r = 0; r < array->ia_rows; r++) {
116 REG_WRITE(ah, INI_RA(array, r, 0),
117 INI_RA(array, r, column));
118 DO_DELAY(*writecnt);
119 }
120 REGWRITE_BUFFER_FLUSH(ah);
121}
122
f078f209
LR		 123u32 ath9k_hw_reverse_bits(u32 val, u32 n)
124{
125 u32 retval;
126 int i;
127
128 for (i = 0, retval = 0; i < n; i++) {
129 retval = (retval << 1) | (val & 1);
130 val >>= 1;
131 }
132 return retval;
133}
134
cbe61d8a 135u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 136 u8 phy, int kbps,
f1dc5600
S		 137 u32 frameLen, u16 rateix,
138 bool shortPreamble)
f078f209 139{
f1dc5600 140 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 141
f1dc5600
S		 142 if (kbps == 0)
143 return 0;
f078f209 144
545750d3 145 switch (phy) {
46d14a58 146 case WLAN_RC_PHY_CCK:
f1dc5600 147 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 148 if (shortPreamble)
f1dc5600
S		 149 phyTime >>= 1;
150 numBits = frameLen << 3;
151 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
152 break;
46d14a58 153 case WLAN_RC_PHY_OFDM:
2660b81a 154 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 155 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
156 numBits = OFDM_PLCP_BITS + (frameLen << 3);
157 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
158 txTime = OFDM_SIFS_TIME_QUARTER
159 + OFDM_PREAMBLE_TIME_QUARTER
160 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 161 } else if (ah->curchan &&
162 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 163 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
164 numBits = OFDM_PLCP_BITS + (frameLen << 3);
165 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
166 txTime = OFDM_SIFS_TIME_HALF +
167 OFDM_PREAMBLE_TIME_HALF
168 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
169 } else {
170 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
171 numBits = OFDM_PLCP_BITS + (frameLen << 3);
172 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
173 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
174 + (numSymbols * OFDM_SYMBOL_TIME);
175 }
176 break;
177 default:
3800276a
JP		 178 ath_err(ath9k_hw_common(ah),
179 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 180 txTime = 0;
181 break;
182 }
f078f209 183
f1dc5600
S		 184 return txTime;
185}
7322fd19 186EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 187
cbe61d8a 188void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 189 struct ath9k_channel *chan,
190 struct chan_centers *centers)
f078f209 191{
f1dc5600 192 int8_t extoff;
f078f209 193
f1dc5600
S		 194 if (!IS_CHAN_HT40(chan)) {
195 centers->ctl_center = centers->ext_center =
196 centers->synth_center = chan->channel;
197 return;
f078f209 198 }
f078f209 199
8896934c 200 if (IS_CHAN_HT40PLUS(chan)) {
f1dc5600
S		 201 centers->synth_center =
202 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
203 extoff = 1;
204 } else {
205 centers->synth_center =
206 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
207 extoff = -1;
208 }
f078f209 209
f1dc5600
S		 210 centers->ctl_center =
211 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 212 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 213 centers->ext_center =
6420014c 214 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 215}
216
f1dc5600
S		 217/******************/
218/* Chip Revisions */
219/******************/
220
cbe61d8a 221static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 222{
f1dc5600 223 u32 val;
f078f209 224
09c74f7b
FF		 225 if (ah->get_mac_revision)
226 ah->hw_version.macRev = ah->get_mac_revision();
227
ecb1d385
VT		 228 switch (ah->hw_version.devid) {
229 case AR5416_AR9100_DEVID:
230 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
231 break;
3762561a
GJ		 232 case AR9300_DEVID_AR9330:
233 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
09c74f7b 234 if (!ah->get_mac_revision) {
3762561a
GJ		 235 val = REG_READ(ah, AR_SREV);
236 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
237 }
238 return;
ecb1d385
VT		 239 case AR9300_DEVID_AR9340:
240 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
ecb1d385 241 return;
813831dc
GJ		 242 case AR9300_DEVID_QCA955X:
243 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
244 return;
e6b1e46e
SM		 245 case AR9300_DEVID_AR953X:
246 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
247 return;
ecb1d385
VT		 248 }
249
f1dc5600 250 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 251
f1dc5600
S		 252 if (val == 0xFF) {
253 val = REG_READ(ah, AR_SREV);
d535a42a
S		 254 ah->hw_version.macVersion =
255 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
256 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 257
77fac465 258 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
76ed94be
MSS		 259 ah->is_pciexpress = true;
260 else
261 ah->is_pciexpress = (val &
262 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 263 } else {
264 if (!AR_SREV_9100(ah))
d535a42a 265 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 266
d535a42a 267 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 268
d535a42a 269 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 270 ah->is_pciexpress = true;
f1dc5600 271 }
f078f209
LR		 272}
273
f1dc5600
S		 274/************************************/
275/* HW Attach, Detach, Init Routines */
276/************************************/
277
cbe61d8a 278static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 279{
040b74f7 280 if (!AR_SREV_5416(ah))
f1dc5600 281 return;
f078f209 282
f1dc5600
S		 283 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 292
f1dc5600 293 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 294}
295
1f3f0618 296/* This should work for all families including legacy */
cbe61d8a 297static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 298{
c46917bb 299 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 300 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 301 u32 regHold[2];
07b2fa5a
JP		 302 static const u32 patternData[4] = {
303 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
304 };
1f3f0618 305 int i, j, loop_max;
f078f209 306
1f3f0618
SB		 307 if (!AR_SREV_9300_20_OR_LATER(ah)) {
308 loop_max = 2;
309 regAddr[1] = AR_PHY_BASE + (8 << 2);
310 } else
311 loop_max = 1;
312
313 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 314 u32 addr = regAddr[i];
315 u32 wrData, rdData;
f078f209 316
f1dc5600
S		 317 regHold[i] = REG_READ(ah, addr);
318 for (j = 0; j < 0x100; j++) {
319 wrData = (j << 16) | j;
320 REG_WRITE(ah, addr, wrData);
321 rdData = REG_READ(ah, addr);
322 if (rdData != wrData) {
3800276a
JP		 323 ath_err(common,
324 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
325 addr, wrData, rdData);
f1dc5600
S		 326 return false;
327 }
328 }
329 for (j = 0; j < 4; j++) {
330 wrData = patternData[j];
331 REG_WRITE(ah, addr, wrData);
332 rdData = REG_READ(ah, addr);
333 if (wrData != rdData) {
3800276a
JP		 334 ath_err(common,
335 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
336 addr, wrData, rdData);
f1dc5600
S		 337 return false;
338 }
f078f209 339 }
f1dc5600 340 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 341 }
f1dc5600 342 udelay(100);
cbe61d8a 343
f078f209
LR		 344 return true;
345}
346
b8b0f377 347static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600 348{
f57cf939
SM		 349 struct ath_common *common = ath9k_hw_common(ah);
350
689e756f
FF		 351 ah->config.dma_beacon_response_time = 1;
352 ah->config.sw_beacon_response_time = 6;
2660b81a 353 ah->config.cwm_ignore_extcca = 0;
2660b81a 354 ah->config.analog_shiftreg = 1;
f078f209 355
0ce024cb 356 ah->config.rx_intr_mitigation = true;
6158425b 357
a64e1a45
SM		 358 if (AR_SREV_9300_20_OR_LATER(ah)) {
359 ah->config.rimt_last = 500;
360 ah->config.rimt_first = 2000;
361 } else {
362 ah->config.rimt_last = 250;
363 ah->config.rimt_first = 700;
364 }
365
6158425b
LR		 366 /*
367 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
368 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
369 * This means we use it for all AR5416 devices, and the few
370 * minor PCI AR9280 devices out there.
371 *
372 * Serialization is required because these devices do not handle
373 * well the case of two concurrent reads/writes due to the latency
374 * involved. During one read/write another read/write can be issued
375 * on another CPU while the previous read/write may still be working
376 * on our hardware, if we hit this case the hardware poops in a loop.
377 * We prevent this by serializing reads and writes.
378 *
379 * This issue is not present on PCI-Express devices or pre-AR5416
380 * devices (legacy, 802.11abg).
381 */
382 if (num_possible_cpus() > 1)
2d6a5e95 383 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f57cf939
SM		 384
385 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
386 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
387 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
388 !ah->is_pciexpress)) {
389 ah->config.serialize_regmode = SER_REG_MODE_ON;
390 } else {
391 ah->config.serialize_regmode = SER_REG_MODE_OFF;
392 }
393 }
394
395 ath_dbg(common, RESET, "serialize_regmode is %d\n",
396 ah->config.serialize_regmode);
397
398 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
399 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
400 else
401 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
f078f209
LR		 402}
403
50aca25b 404static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 405{
608b88cb
LR		 406 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
407
408 regulatory->country_code = CTRY_DEFAULT;
409 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 410
d535a42a 411 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 412 ah->hw_version.subvendorid = 0;
f078f209 413
f57cf939
SM		 414 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
415 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 416 if (AR_SREV_9100(ah))
417 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
f57cf939 418
e3f2acc7 419 ah->slottime = ATH9K_SLOT_TIME_9;
2660b81a 420 ah->globaltxtimeout = (u32) -1;
cbdec975 421 ah->power_mode = ATH9K_PM_UNDEFINED;
8efa7a81 422 ah->htc_reset_init = true;
f57cf939
SM		 423
424 ah->ani_function = ATH9K_ANI_ALL;
425 if (!AR_SREV_9300_20_OR_LATER(ah))
426 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
427
428 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
429 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
430 else
431 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209
LR		 432}
433
cbe61d8a 434static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 435{
1510718d 436 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 437 u32 sum;
438 int i;
439 u16 eeval;
07b2fa5a 440 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 441
442 sum = 0;
443 for (i = 0; i < 3; i++) {
49101676 444 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 445 sum += eeval;
1510718d
LR		 446 common->macaddr[2 * i] = eeval >> 8;
447 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 448 }
d8baa939 449 if (sum == 0 || sum == 0xffff * 3)
f078f209 450 return -EADDRNOTAVAIL;
f078f209
LR		 451
452 return 0;
453}
454
f637cfd6 455static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 456{
6cae913d 457 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 458 int ecode;
f078f209 459
6cae913d 460 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 461 if (!ath9k_hw_chip_test(ah))
462 return -ENODEV;
463 }
f078f209 464
ebd5a14a
LR		 465 if (!AR_SREV_9300_20_OR_LATER(ah)) {
466 ecode = ar9002_hw_rf_claim(ah);
467 if (ecode != 0)
468 return ecode;
469 }
f078f209 470
f637cfd6 471 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 472 if (ecode != 0)
473 return ecode;
7d01b221 474
d2182b69 475 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 476 ah->eep_ops->get_eeprom_ver(ah),
477 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 478
e323300d 479 ath9k_hw_ani_init(ah);
f078f209 480
d3b371cb
SM		 481 /*
482 * EEPROM needs to be initialized before we do this.
483 * This is required for regulatory compliance.
484 */
0c7c2bb4 485 if (AR_SREV_9300_20_OR_LATER(ah)) {
d3b371cb
SM		 486 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
487 if ((regdmn & 0xF0) == CTL_FCC) {
0c7c2bb4
SM		 488 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
489 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
d3b371cb
SM		 490 }
491 }
492
f078f209
LR		 493 return 0;
494}
495
c1b976d2 496static int ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 497{
c1b976d2
FF		 498 if (!AR_SREV_9300_20_OR_LATER(ah))
499 return ar9002_hw_attach_ops(ah);
500
501 ar9003_hw_attach_ops(ah);
502 return 0;
aa4058ae
LR		 503}
504
d70357d5
LR		 505/* Called for all hardware families */
506static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 507{
c46917bb 508 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 509 int r = 0;
aa4058ae 510
ac45c12d
SB		 511 ath9k_hw_read_revisions(ah);
512
de82582b
SM		 513 switch (ah->hw_version.macVersion) {
514 case AR_SREV_VERSION_5416_PCI:
515 case AR_SREV_VERSION_5416_PCIE:
516 case AR_SREV_VERSION_9160:
517 case AR_SREV_VERSION_9100:
518 case AR_SREV_VERSION_9280:
519 case AR_SREV_VERSION_9285:
520 case AR_SREV_VERSION_9287:
521 case AR_SREV_VERSION_9271:
522 case AR_SREV_VERSION_9300:
523 case AR_SREV_VERSION_9330:
524 case AR_SREV_VERSION_9485:
525 case AR_SREV_VERSION_9340:
526 case AR_SREV_VERSION_9462:
527 case AR_SREV_VERSION_9550:
528 case AR_SREV_VERSION_9565:
e6b1e46e 529 case AR_SREV_VERSION_9531:
de82582b
SM		 530 break;
531 default:
532 ath_err(common,
533 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
534 ah->hw_version.macVersion, ah->hw_version.macRev);
535 return -EOPNOTSUPP;
536 }
537
0a8d7cb0
SB		 538 /*
539 * Read back AR_WA into a permanent copy and set bits 14 and 17.
540 * We need to do this to avoid RMW of this register. We cannot
541 * read the reg when chip is asleep.
542 */
27251e00
SM		 543 if (AR_SREV_9300_20_OR_LATER(ah)) {
544 ah->WARegVal = REG_READ(ah, AR_WA);
545 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
546 AR_WA_ASPM_TIMER_BASED_DISABLE);
547 }
0a8d7cb0 548
aa4058ae 549 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 550 ath_err(common, "Couldn't reset chip\n");
95fafca2 551 return -EIO;
aa4058ae
LR		 552 }
553
a4a2954f
SM		 554 if (AR_SREV_9565(ah)) {
555 ah->WARegVal |= AR_WA_BIT22;
556 REG_WRITE(ah, AR_WA, ah->WARegVal);
557 }
558
bab1f62e
LR		 559 ath9k_hw_init_defaults(ah);
560 ath9k_hw_init_config(ah);
561
c1b976d2
FF		 562 r = ath9k_hw_attach_ops(ah);
563 if (r)
564 return r;
d70357d5 565
9ecdef4b 566 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 567 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 568 return -EIO;
aa4058ae
LR		 569 }
570
2c8e5937 571 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
c95b584b 572 AR_SREV_9330(ah) || AR_SREV_9550(ah))
d7e7d229
LR		 573 ah->is_pciexpress = false;
574
aa4058ae 575 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 576 ath9k_hw_init_cal_settings(ah);
577
69ce674b 578 if (!ah->is_pciexpress)
aa4058ae
LR		 579 ath9k_hw_disablepcie(ah);
580
f637cfd6 581 r = ath9k_hw_post_init(ah);
aa4058ae 582 if (r)
95fafca2 583 return r;
aa4058ae
LR		 584
585 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 586 r = ath9k_hw_fill_cap_info(ah);
587 if (r)
588 return r;
589
4f3acf81
LR		 590 r = ath9k_hw_init_macaddr(ah);
591 if (r) {
3800276a 592 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 593 return r;
f078f209
LR		 594 }
595
4598702d 596 ath9k_hw_init_hang_checks(ah);
f078f209 597
211f5859
LR		 598 common->state = ATH_HW_INITIALIZED;
599
4f3acf81 600 return 0;
f078f209
LR		 601}
602
d70357d5 603int ath9k_hw_init(struct ath_hw *ah)
f078f209 604{
d70357d5
LR		 605 int ret;
606 struct ath_common *common = ath9k_hw_common(ah);
f078f209 607
77fac465 608 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
d70357d5
LR		 609 switch (ah->hw_version.devid) {
610 case AR5416_DEVID_PCI:
611 case AR5416_DEVID_PCIE:
612 case AR5416_AR9100_DEVID:
613 case AR9160_DEVID_PCI:
614 case AR9280_DEVID_PCI:
615 case AR9280_DEVID_PCIE:
616 case AR9285_DEVID_PCIE:
db3cc53a
SB		 617 case AR9287_DEVID_PCI:
618 case AR9287_DEVID_PCIE:
d70357d5 619 case AR2427_DEVID_PCIE:
db3cc53a 620 case AR9300_DEVID_PCIE:
3050c914 621 case AR9300_DEVID_AR9485_PCIE:
999a7a88 622 case AR9300_DEVID_AR9330:
bca04689 623 case AR9300_DEVID_AR9340:
2b943a33 624 case AR9300_DEVID_QCA955X:
5a63ef0f 625 case AR9300_DEVID_AR9580:
423e38e8 626 case AR9300_DEVID_AR9462:
d4e5979c 627 case AR9485_DEVID_AR1111:
77fac465 628 case AR9300_DEVID_AR9565:
e6b1e46e 629 case AR9300_DEVID_AR953X:
d70357d5
LR		 630 break;
631 default:
632 if (common->bus_ops->ath_bus_type == ATH_USB)
633 break;
3800276a
JP		 634 ath_err(common, "Hardware device ID 0x%04x not supported\n",
635 ah->hw_version.devid);
d70357d5
LR		 636 return -EOPNOTSUPP;
637 }
f078f209 638
d70357d5
LR		 639 ret = __ath9k_hw_init(ah);
640 if (ret) {
3800276a
JP		 641 ath_err(common,
642 "Unable to initialize hardware; initialization status: %d\n",
643 ret);
d70357d5
LR		 644 return ret;
645 }
f078f209 646
c774d57f
LB		 647 ath_dynack_init(ah);
648
d70357d5 649 return 0;
f078f209 650}
d70357d5 651EXPORT_SYMBOL(ath9k_hw_init);
f078f209 652
cbe61d8a 653static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 654{
7d0d0df0
S		 655 ENABLE_REGWRITE_BUFFER(ah);
656
f1dc5600
S		 657 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
658 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 659
f1dc5600
S		 660 REG_WRITE(ah, AR_QOS_NO_ACK,
661 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
662 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
663 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
664
665 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
666 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
667 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
668 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
669 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 670
671 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 672}
673
b84628eb 674u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 675{
f18e3c6b
MSS		 676 struct ath_common *common = ath9k_hw_common(ah);
677 int i = 0;
678
ca7a4deb
FF		 679 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
680 udelay(100);
681 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 682
f18e3c6b
MSS		 683 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
684
ca7a4deb 685 udelay(100);
b1415819 686
f18e3c6b
MSS		 687 if (WARN_ON_ONCE(i >= 100)) {
688 ath_err(common, "PLL4 meaurement not done\n");
689 break;
690 }
691
692 i++;
693 }
694
ca7a4deb 695 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 696}
697EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
698
cbe61d8a 699static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 700 struct ath9k_channel *chan)
f078f209 701{
d09b17f7
VT		 702 u32 pll;
703
5fb9b1b9
FF		 704 pll = ath9k_hw_compute_pll_control(ah, chan);
705
a4a2954f 706 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3dfd7f60
VT		 707 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
708 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
709 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
710 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
711 AR_CH0_DPLL2_KD, 0x40);
712 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
713 AR_CH0_DPLL2_KI, 0x4);
22983c30 714
3dfd7f60
VT		 715 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
716 AR_CH0_BB_DPLL1_REFDIV, 0x5);
717 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
718 AR_CH0_BB_DPLL1_NINI, 0x58);
719 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
720 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 721
722 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 723 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
724 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
725 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 726 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 727 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 728
3dfd7f60 729 /* program BB PLL phase_shift to 0x6 */
22983c30 730 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 731 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
732
733 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
734 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 735 udelay(1000);
a5415d62
GJ		 736 } else if (AR_SREV_9330(ah)) {
737 u32 ddr_dpll2, pll_control2, kd;
738
739 if (ah->is_clk_25mhz) {
740 ddr_dpll2 = 0x18e82f01;
741 pll_control2 = 0xe04a3d;
742 kd = 0x1d;
743 } else {
744 ddr_dpll2 = 0x19e82f01;
745 pll_control2 = 0x886666;
746 kd = 0x3d;
747 }
748
749 /* program DDR PLL ki and kd value */
750 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
751
752 /* program DDR PLL phase_shift */
753 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
754 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
755
5fb9b1b9
FF		 756 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
757 pll | AR_RTC_9300_PLL_BYPASS);
a5415d62
GJ		 758 udelay(1000);
759
760 /* program refdiv, nint, frac to RTC register */
761 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
762
763 /* program BB PLL kd and ki value */
764 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
765 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
766
767 /* program BB PLL phase_shift */
768 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
769 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
2c323058 770 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
0b488ac6
VT		 771 u32 regval, pll2_divint, pll2_divfrac, refdiv;
772
5fb9b1b9
FF		 773 REG_WRITE(ah, AR_RTC_PLL_CONTROL,
774 pll | AR_RTC_9300_SOC_PLL_BYPASS);
0b488ac6
VT		 775 udelay(1000);
776
777 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
778 udelay(100);
779
780 if (ah->is_clk_25mhz) {
2c323058
SM		 781 if (AR_SREV_9531(ah)) {
782 pll2_divint = 0x1c;
783 pll2_divfrac = 0xa3d2;
784 refdiv = 1;
785 } else {
786 pll2_divint = 0x54;
787 pll2_divfrac = 0x1eb85;
788 refdiv = 3;
789 }
0b488ac6 790 } else {
fc05a317
GJ		 791 if (AR_SREV_9340(ah)) {
792 pll2_divint = 88;
793 pll2_divfrac = 0;
794 refdiv = 5;
795 } else {
796 pll2_divint = 0x11;
76ac9ed6
RM		 797 pll2_divfrac =
798 AR_SREV_9531(ah) ? 0x26665 : 0x26666;
fc05a317
GJ		 799 refdiv = 1;
800 }
0b488ac6
VT		 801 }
802
803 regval = REG_READ(ah, AR_PHY_PLL_MODE);
2c323058
SM		 804 if (AR_SREV_9531(ah))
805 regval |= (0x1 << 22);
806 else
807 regval |= (0x1 << 16);
0b488ac6
VT		 808 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
809 udelay(100);
810
811 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
812 (pll2_divint << 18) | pll2_divfrac);
813 udelay(100);
814
815 regval = REG_READ(ah, AR_PHY_PLL_MODE);
fc05a317 816 if (AR_SREV_9340(ah))
2c323058
SM		 817 regval = (regval & 0x80071fff) |
818 (0x1 << 30) |
819 (0x1 << 13) |
820 (0x4 << 26) |
821 (0x18 << 19);
822 else if (AR_SREV_9531(ah))
823 regval = (regval & 0x01c00fff) |
824 (0x1 << 31) |
825 (0x2 << 29) |
826 (0xa << 25) |
827 (0x1 << 19) |
828 (0x6 << 12);
fc05a317 829 else
2c323058
SM		 830 regval = (regval & 0x80071fff) |
831 (0x3 << 30) |
832 (0x1 << 13) |
833 (0x4 << 26) |
834 (0x60 << 19);
0b488ac6 835 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
2c323058
SM		 836
837 if (AR_SREV_9531(ah))
838 REG_WRITE(ah, AR_PHY_PLL_MODE,
839 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
840 else
841 REG_WRITE(ah, AR_PHY_PLL_MODE,
842 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
843
0b488ac6 844 udelay(1000);
22983c30 845 }
d09b17f7 846
8565f8bf
SM		 847 if (AR_SREV_9565(ah))
848 pll |= 0x40000;
d03a66c1 849 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 850
fc05a317
GJ		 851 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
852 AR_SREV_9550(ah))
3dfd7f60
VT		 853 udelay(1000);
854
c75724d1
LR		 855 /* Switch the core clock for ar9271 to 117Mhz */
856 if (AR_SREV_9271(ah)) {
25e2ab17
S		 857 udelay(500);
858 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 859 }
860
f1dc5600
S		 861 udelay(RTC_PLL_SETTLE_DELAY);
862
863 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
0b488ac6 864
fc05a317 865 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
0b488ac6
VT		 866 if (ah->is_clk_25mhz) {
867 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
868 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
869 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
870 } else {
871 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
872 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
873 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
874 }
875 udelay(100);
876 }
f078f209
LR		 877}
878
cbe61d8a 879static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 880 enum nl80211_iftype opmode)
f078f209 881{
79d1d2b8 882 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 883 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 884 AR_IMR_TXURN |
885 AR_IMR_RXERR |
886 AR_IMR_RXORN |
887 AR_IMR_BCNMISC;
f078f209 888
c90d4f7b 889 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah))
79d1d2b8
VT		 890 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
891
66860240
VT		 892 if (AR_SREV_9300_20_OR_LATER(ah)) {
893 imr_reg |= AR_IMR_RXOK_HP;
894 if (ah->config.rx_intr_mitigation)
895 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
896 else
897 imr_reg |= AR_IMR_RXOK_LP;
f078f209 898
66860240
VT		 899 } else {
900 if (ah->config.rx_intr_mitigation)
901 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
902 else
903 imr_reg |= AR_IMR_RXOK;
904 }
f078f209 905
66860240
VT		 906 if (ah->config.tx_intr_mitigation)
907 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
908 else
909 imr_reg |= AR_IMR_TXOK;
f078f209 910
7d0d0df0
S		 911 ENABLE_REGWRITE_BUFFER(ah);
912
152d530d 913 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 914 ah->imrs2_reg |= AR_IMR_S2_GTT;
915 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 916
f1dc5600
S		 917 if (!AR_SREV_9100(ah)) {
918 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 919 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 920 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
921 }
66860240 922
7d0d0df0 923 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 924
66860240
VT		 925 if (AR_SREV_9300_20_OR_LATER(ah)) {
926 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
927 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
928 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
929 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
930 }
f078f209
LR		 931}
932
b6ba41bb
FF		 933static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
934{
935 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
936 val = min(val, (u32) 0xFFFF);
937 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
938}
939
8e15e094 940void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 941{
0005baf4
FF		 942 u32 val = ath9k_hw_mac_to_clks(ah, us);
943 val = min(val, (u32) 0xFFFF);
944 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 945}
946
8e15e094 947void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 948{
0005baf4
FF		 949 u32 val = ath9k_hw_mac_to_clks(ah, us);
950 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
951 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
952}
953
8e15e094 954void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
0005baf4
FF		 955{
956 u32 val = ath9k_hw_mac_to_clks(ah, us);
957 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
958 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 959}
f1dc5600 960
cbe61d8a 961static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 962{
f078f209 963 if (tu > 0xFFFF) {
d2182b69
JP		 964 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
965 tu);
2660b81a 966 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 967 return false;
968 } else {
969 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 970 ah->globaltxtimeout = tu;
f078f209
LR		 971 return true;
972 }
973}
974
0005baf4 975void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 976{
b6ba41bb 977 struct ath_common *common = ath9k_hw_common(ah);
b6ba41bb 978 const struct ath9k_channel *chan = ah->curchan;
e115b7ec 979 int acktimeout, ctstimeout, ack_offset = 0;
e239d859 980 int slottime;
0005baf4 981 int sifstime;
b6ba41bb
FF		 982 int rx_lat = 0, tx_lat = 0, eifs = 0;
983 u32 reg;
0005baf4 984
d2182b69 985 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 986 ah->misc_mode);
f078f209 987
b6ba41bb
FF		 988 if (!chan)
989 return;
990
2660b81a 991 if (ah->misc_mode != 0)
ca7a4deb 992 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 993
81a91d57
RM		 994 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
995 rx_lat = 41;
996 else
997 rx_lat = 37;
b6ba41bb
FF		 998 tx_lat = 54;
999
e88e4861
FF		 1000 if (IS_CHAN_5GHZ(chan))
1001 sifstime = 16;
1002 else
1003 sifstime = 10;
1004
b6ba41bb
FF		 1005 if (IS_CHAN_HALF_RATE(chan)) {
1006 eifs = 175;
1007 rx_lat *= 2;
1008 tx_lat *= 2;
1009 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1010 tx_lat += 11;
1011
92367fe7 1012 sifstime = 32;
e115b7ec 1013 ack_offset = 16;
b6ba41bb 1014 slottime = 13;
b6ba41bb
FF		 1015 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1016 eifs = 340;
81a91d57 1017 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 1018 tx_lat *= 4;
1019 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1020 tx_lat += 22;
1021
92367fe7 1022 sifstime = 64;
e115b7ec 1023 ack_offset = 32;
b6ba41bb 1024 slottime = 21;
b6ba41bb 1025 } else {
a7be039d
RM		 1026 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1027 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1028 reg = AR_USEC_ASYNC_FIFO;
1029 } else {
1030 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1031 common->clockrate;
1032 reg = REG_READ(ah, AR_USEC);
1033 }
b6ba41bb
FF		 1034 rx_lat = MS(reg, AR_USEC_RX_LAT);
1035 tx_lat = MS(reg, AR_USEC_TX_LAT);
1036
1037 slottime = ah->slottime;
b6ba41bb 1038 }
0005baf4 1039
e239d859 1040 /* As defined by IEEE 802.11-2007 17.3.8.6 */
f77f8234
MK		 1041 slottime += 3 * ah->coverage_class;
1042 acktimeout = slottime + sifstime + ack_offset;
adb5066a 1043 ctstimeout = acktimeout;
42c4568a
FF		 1044
1045 /*
1046 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1047 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1048 * This was initially only meant to work around an issue with delayed
1049 * BA frames in some implementations, but it has been found to fix ACK
1050 * timeout issues in other cases as well.
1051 */
e4744ec7 1052 if (IS_CHAN_2GHZ(chan) &&
e115b7ec 1053 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
42c4568a 1054 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1055 ctstimeout += 48 - sifstime - ah->slottime;
1056 }
1057
7aefa8aa
LB		 1058 if (ah->dynack.enabled) {
1059 acktimeout = ah->dynack.ackto;
1060 ctstimeout = acktimeout;
1061 slottime = (acktimeout - 3) / 2;
1062 } else {
1063 ah->dynack.ackto = acktimeout;
1064 }
1065
b6ba41bb
FF		 1066 ath9k_hw_set_sifs_time(ah, sifstime);
1067 ath9k_hw_setslottime(ah, slottime);
0005baf4 1068 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1069 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1070 if (ah->globaltxtimeout != (u32) -1)
1071 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1072
1073 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1074 REG_RMW(ah, AR_USEC,
1075 (common->clockrate - 1) |
1076 SM(rx_lat, AR_USEC_RX_LAT) |
1077 SM(tx_lat, AR_USEC_TX_LAT),
1078 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1079
f1dc5600 1080}
0005baf4 1081EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1082
285f2dda 1083void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1084{
211f5859
LR		 1085 struct ath_common *common = ath9k_hw_common(ah);
1086
736b3a27 1087 if (common->state < ATH_HW_INITIALIZED)
c1b976d2 1088 return;
211f5859 1089
9ecdef4b 1090 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
f1dc5600 1091}
285f2dda 1092EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1093
f1dc5600
S		 1094/*******/
1095/* INI */
1096/*******/
1097
8fe65368 1098u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1099{
1100 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1101
6b21fd20 1102 if (IS_CHAN_2GHZ(chan))
3a702e49
BC		 1103 ctl |= CTL_11G;
1104 else
1105 ctl |= CTL_11A;
1106
1107 return ctl;
1108}
1109
f1dc5600
S		 1110/****************************************/
1111/* Reset and Channel Switching Routines */
1112/****************************************/
f1dc5600 1113
cbe61d8a 1114static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1115{
57b32227 1116 struct ath_common *common = ath9k_hw_common(ah);
86c157b3 1117 int txbuf_size;
f1dc5600 1118
7d0d0df0
S		 1119 ENABLE_REGWRITE_BUFFER(ah);
1120
d7e7d229
LR		 1121 /*
1122 * set AHB_MODE not to do cacheline prefetches
1123 */
ca7a4deb
FF		 1124 if (!AR_SREV_9300_20_OR_LATER(ah))
1125 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1126
d7e7d229
LR		 1127 /*
1128 * let mac dma reads be in 128 byte chunks
1129 */
ca7a4deb 1130 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1131
7d0d0df0 1132 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1133
d7e7d229
LR		 1134 /*
1135 * Restore TX Trigger Level to its pre-reset value.
1136 * The initial value depends on whether aggregation is enabled, and is
1137 * adjusted whenever underruns are detected.
1138 */
57b32227
FF		 1139 if (!AR_SREV_9300_20_OR_LATER(ah))
1140 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1141
7d0d0df0 1142 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1143
d7e7d229
LR		 1144 /*
1145 * let mac dma writes be in 128 byte chunks
1146 */
ca7a4deb 1147 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1148
d7e7d229
LR		 1149 /*
1150 * Setup receive FIFO threshold to hold off TX activities
1151 */
f1dc5600
S		 1152 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1153
57b32227
FF		 1154 if (AR_SREV_9300_20_OR_LATER(ah)) {
1155 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1156 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1157
1158 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1159 ah->caps.rx_status_len);
1160 }
1161
d7e7d229
LR		 1162 /*
1163 * reduce the number of usable entries in PCU TXBUF to avoid
1164 * wrap around issues.
1165 */
f1dc5600 1166 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1167 /* For AR9285 the number of Fifos are reduced to half.
1168 * So set the usable tx buf size also to half to
1169 * avoid data/delimiter underruns
1170 */
86c157b3
FF		 1171 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1172 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1173 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1174 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1175 } else {
1176 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
f1dc5600 1177 }
744d4025 1178
86c157b3
FF		 1179 if (!AR_SREV_9271(ah))
1180 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1181
7d0d0df0 1182 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1183
744d4025
VT		 1184 if (AR_SREV_9300_20_OR_LATER(ah))
1185 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1186}
1187
cbe61d8a 1188static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1189{
ca7a4deb
FF		 1190 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1191 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1192
f1dc5600 1193 switch (opmode) {
d97809db 1194 case NL80211_IFTYPE_ADHOC:
83322eb8
FF		 1195 if (!AR_SREV_9340_13(ah)) {
1196 set |= AR_STA_ID1_ADHOC;
1197 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1198 break;
1199 }
1200 /* fall through */
2664d666 1201 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb
FF		 1202 case NL80211_IFTYPE_AP:
1203 set |= AR_STA_ID1_STA_AP;
1204 /* fall through */
d97809db 1205 case NL80211_IFTYPE_STATION:
ca7a4deb 1206 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1207 break;
5f841b41 1208 default:
ca7a4deb
FF		 1209 if (!ah->is_monitoring)
1210 set = 0;
5f841b41 1211 break;
f1dc5600 1212 }
ca7a4deb 1213 REG_RMW(ah, AR_STA_ID1, set, mask);
f1dc5600
S		 1214}
1215
8fe65368
LR		 1216void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1217 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1218{
1219 u32 coef_exp, coef_man;
1220
1221 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1222 if ((coef_scaled >> coef_exp) & 0x1)
1223 break;
1224
1225 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1226
1227 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1228
1229 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1230 *coef_exponent = coef_exp - 16;
1231}
1232
d7df7a55
SM		 1233/* AR9330 WAR:
1234 * call external reset function to reset WMAC if:
1235 * - doing a cold reset
1236 * - we have pending frames in the TX queues.
1237 */
1238static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1239{
1240 int i, npend = 0;
1241
1242 for (i = 0; i < AR_NUM_QCU; i++) {
1243 npend = ath9k_hw_numtxpending(ah, i);
1244 if (npend)
1245 break;
1246 }
1247
1248 if (ah->external_reset &&
1249 (npend || type == ATH9K_RESET_COLD)) {
1250 int reset_err = 0;
1251
1252 ath_dbg(ath9k_hw_common(ah), RESET,
1253 "reset MAC via external reset\n");
1254
1255 reset_err = ah->external_reset();
1256 if (reset_err) {
1257 ath_err(ath9k_hw_common(ah),
1258 "External reset failed, err=%d\n",
1259 reset_err);
1260 return false;
1261 }
1262
1263 REG_WRITE(ah, AR_RTC_RESET, 1);
1264 }
1265
1266 return true;
1267}
1268
cbe61d8a 1269static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1270{
1271 u32 rst_flags;
1272 u32 tmpReg;
1273
70768496 1274 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1275 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1276 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1277 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1278 }
1279
7d0d0df0
S		 1280 ENABLE_REGWRITE_BUFFER(ah);
1281
9a658d2b
LR		 1282 if (AR_SREV_9300_20_OR_LATER(ah)) {
1283 REG_WRITE(ah, AR_WA, ah->WARegVal);
1284 udelay(10);
1285 }
1286
f1dc5600
S		 1287 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1288 AR_RTC_FORCE_WAKE_ON_INT);
1289
1290 if (AR_SREV_9100(ah)) {
1291 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1292 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1293 } else {
1294 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
a37a9910
FF		 1295 if (AR_SREV_9340(ah))
1296 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1297 else
1298 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1299 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1300
1301 if (tmpReg) {
42d5bc3f 1302 u32 val;
f1dc5600 1303 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1304
1305 val = AR_RC_HOSTIF;
1306 if (!AR_SREV_9300_20_OR_LATER(ah))
1307 val |= AR_RC_AHB;
1308 REG_WRITE(ah, AR_RC, val);
1309
1310 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1311 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1312
1313 rst_flags = AR_RTC_RC_MAC_WARM;
1314 if (type == ATH9K_RESET_COLD)
1315 rst_flags |= AR_RTC_RC_MAC_COLD;
1316 }
1317
7d95847c 1318 if (AR_SREV_9330(ah)) {
d7df7a55
SM		 1319 if (!ath9k_hw_ar9330_reset_war(ah, type))
1320 return false;
7d95847c
GJ		 1321 }
1322
3863495b 1323 if (ath9k_hw_mci_is_enabled(ah))
506847ad 1324 ar9003_mci_check_gpm_offset(ah);
3863495b 1325
d03a66c1 1326 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1327
1328 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1329
4dc78c43
SM		 1330 if (AR_SREV_9300_20_OR_LATER(ah))
1331 udelay(50);
1332 else if (AR_SREV_9100(ah))
3683a07b 1333 mdelay(10);
4dc78c43
SM		 1334 else
1335 udelay(100);
f1dc5600 1336
d03a66c1 1337 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1338 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1339 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1340 return false;
1341 }
1342
1343 if (!AR_SREV_9100(ah))
1344 REG_WRITE(ah, AR_RC, 0);
1345
f1dc5600
S		 1346 if (AR_SREV_9100(ah))
1347 udelay(50);
1348
1349 return true;
1350}
1351
cbe61d8a 1352static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1353{
7d0d0df0
S		 1354 ENABLE_REGWRITE_BUFFER(ah);
1355
9a658d2b
LR		 1356 if (AR_SREV_9300_20_OR_LATER(ah)) {
1357 REG_WRITE(ah, AR_WA, ah->WARegVal);
1358 udelay(10);
1359 }
1360
f1dc5600
S		 1361 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1362 AR_RTC_FORCE_WAKE_ON_INT);
1363
42d5bc3f 1364 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1365 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1366
d03a66c1 1367 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1368
7d0d0df0 1369 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1370
afe36533 1371 udelay(2);
84e2169b
SB		 1372
1373 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1374 REG_WRITE(ah, AR_RC, 0);
1375
d03a66c1 1376 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1377
1378 if (!ath9k_hw_wait(ah,
1379 AR_RTC_STATUS,
1380 AR_RTC_STATUS_M,
0caa7b14
S		 1381 AR_RTC_STATUS_ON,
1382 AH_WAIT_TIMEOUT)) {
d2182b69 1383 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1384 return false;
f078f209
LR		 1385 }
1386
f1dc5600
S		 1387 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1388}
1389
cbe61d8a 1390static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1391{
7a9233ff 1392 bool ret = false;
2577c6e8 1393
9a658d2b
LR		 1394 if (AR_SREV_9300_20_OR_LATER(ah)) {
1395 REG_WRITE(ah, AR_WA, ah->WARegVal);
1396 udelay(10);
1397 }
1398
f1dc5600
S		 1399 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1400 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1401
ceb26a60
FF		 1402 if (!ah->reset_power_on)
1403 type = ATH9K_RESET_POWER_ON;
1404
f1dc5600
S		 1405 switch (type) {
1406 case ATH9K_RESET_POWER_ON:
7a9233ff 1407 ret = ath9k_hw_set_reset_power_on(ah);
da8fb123 1408 if (ret)
ceb26a60 1409 ah->reset_power_on = true;
7a9233ff 1410 break;
f1dc5600
S		 1411 case ATH9K_RESET_WARM:
1412 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1413 ret = ath9k_hw_set_reset(ah, type);
1414 break;
f1dc5600 1415 default:
7a9233ff 1416 break;
f1dc5600 1417 }
7a9233ff 1418
7a9233ff 1419 return ret;
f078f209
LR		 1420}
1421
cbe61d8a 1422static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1423 struct ath9k_channel *chan)
f078f209 1424{
9c083af8
FF		 1425 int reset_type = ATH9K_RESET_WARM;
1426
1427 if (AR_SREV_9280(ah)) {
1428 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1429 reset_type = ATH9K_RESET_POWER_ON;
1430 else
1431 reset_type = ATH9K_RESET_COLD;
3412f2f0
FF		 1432 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1433 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1434 reset_type = ATH9K_RESET_COLD;
9c083af8
FF		 1435
1436 if (!ath9k_hw_set_reset_reg(ah, reset_type))
f1dc5600 1437 return false;
f078f209 1438
9ecdef4b 1439 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1440 return false;
f078f209 1441
2660b81a 1442 ah->chip_fullsleep = false;
bfc441a4
FF		 1443
1444 if (AR_SREV_9330(ah))
1445 ar9003_hw_internal_regulator_apply(ah);
f1dc5600 1446 ath9k_hw_init_pll(ah, chan);
f078f209 1447
f1dc5600 1448 return true;
f078f209
LR		 1449}
1450
cbe61d8a 1451static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1452 struct ath9k_channel *chan)
f078f209 1453{
c46917bb 1454 struct ath_common *common = ath9k_hw_common(ah);
b840cffe
SM		 1455 struct ath9k_hw_capabilities *pCap = &ah->caps;
1456 bool band_switch = false, mode_diff = false;
70e89a71 1457 u8 ini_reloaded = 0;
8fe65368 1458 u32 qnum;
0a3b7bac 1459 int r;
5f0c04ea 1460
b840cffe 1461 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
af02efb3
FF		 1462 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1463 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1464 mode_diff = !!(flags_diff & ~CHANNEL_HT);
b840cffe 1465 }
f078f209
LR		 1466
1467 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1468 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1469 ath_dbg(common, QUEUE,
226afe68 1470 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1471 return false;
1472 }
1473 }
1474
8fe65368 1475 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1476 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1477 return false;
1478 }
1479
b840cffe 1480 if (band_switch || mode_diff) {
5f0c04ea
RM		 1481 ath9k_hw_mark_phy_inactive(ah);
1482 udelay(5);
1483
5f35c0fa
SM		 1484 if (band_switch)
1485 ath9k_hw_init_pll(ah, chan);
5f0c04ea
RM		 1486
1487 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1488 ath_err(common, "Failed to do fast channel change\n");
1489 return false;
1490 }
1491 }
1492
8fe65368 1493 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1494
8fe65368 1495 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1496 if (r) {
3800276a 1497 ath_err(common, "Failed to set channel\n");
0a3b7bac 1498 return false;
f078f209 1499 }
dfdac8ac 1500 ath9k_hw_set_clockrate(ah);
64ea57d0 1501 ath9k_hw_apply_txpower(ah, chan, false);
f078f209 1502
81c507a8 1503 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1504 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1505
70e89a71
SM		 1506 if (band_switch || ini_reloaded)
1507 ah->eep_ops->set_board_values(ah, chan);
5f0c04ea 1508
70e89a71
SM		 1509 ath9k_hw_init_bb(ah, chan);
1510 ath9k_hw_rfbus_done(ah);
5f0c04ea 1511
70e89a71
SM		 1512 if (band_switch || ini_reloaded) {
1513 ah->ah_flags |= AH_FASTCC;
1514 ath9k_hw_init_cal(ah, chan);
a126ff51 1515 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1516 }
1517
f1dc5600
S		 1518 return true;
1519}
1520
691680b8
FF		 1521static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1522{
1523 u32 gpio_mask = ah->gpio_mask;
1524 int i;
1525
1526 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1527 if (!(gpio_mask & 1))
1528 continue;
1529
1530 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1531 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1532 }
1533}
1534
1e516ca7
SM		 1535void ath9k_hw_check_nav(struct ath_hw *ah)
1536{
1537 struct ath_common *common = ath9k_hw_common(ah);
1538 u32 val;
1539
1540 val = REG_READ(ah, AR_NAV);
1541 if (val != 0xdeadbeef && val > 0x7fff) {
1542 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1543 REG_WRITE(ah, AR_NAV, 0);
1544 }
1545}
1546EXPORT_SYMBOL(ath9k_hw_check_nav);
1547
c9c99e5e 1548bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1549{
c9c99e5e 1550 int count = 50;
d31a36a6 1551 u32 reg, last_val;
c9c99e5e 1552
01e18918
RM		 1553 if (AR_SREV_9300(ah))
1554 return !ath9k_hw_detect_mac_hang(ah);
1555
e17f83ea 1556 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1557 return true;
1558
d31a36a6 1559 last_val = REG_READ(ah, AR_OBS_BUS_1);
c9c99e5e
FF		 1560 do {
1561 reg = REG_READ(ah, AR_OBS_BUS_1);
d31a36a6
FF		 1562 if (reg != last_val)
1563 return true;
3b319aae 1564
105ff411 1565 udelay(1);
d31a36a6 1566 last_val = reg;
c9c99e5e
FF		 1567 if ((reg & 0x7E7FFFEF) == 0x00702400)
1568 continue;
1569
1570 switch (reg & 0x7E000B00) {
1571 case 0x1E000000:
1572 case 0x52000B00:
1573 case 0x18000B00:
1574 continue;
1575 default:
1576 return true;
1577 }
1578 } while (count-- > 0);
3b319aae 1579
c9c99e5e 1580 return false;
3b319aae 1581}
c9c99e5e 1582EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1583
15d2b585
SM		 1584static void ath9k_hw_init_mfp(struct ath_hw *ah)
1585{
1586 /* Setup MFP options for CCMP */
1587 if (AR_SREV_9280_20_OR_LATER(ah)) {
1588 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1589 * frames when constructing CCMP AAD. */
1590 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1591 0xc7ff);
1592 ah->sw_mgmt_crypto = false;
1593 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1594 /* Disable hardware crypto for management frames */
1595 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1596 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1597 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1598 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1599 ah->sw_mgmt_crypto = true;
1600 } else {
1601 ah->sw_mgmt_crypto = true;
1602 }
1603}
1604
1605static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1606 u32 macStaId1, u32 saveDefAntenna)
1607{
1608 struct ath_common *common = ath9k_hw_common(ah);
1609
1610 ENABLE_REGWRITE_BUFFER(ah);
1611
ecbbed32 1612 REG_RMW(ah, AR_STA_ID1, macStaId1
15d2b585 1613 | AR_STA_ID1_RTS_USE_DEF
ecbbed32
FF		 1614 | ah->sta_id1_defaults,
1615 ~AR_STA_ID1_SADH_MASK);
15d2b585
SM		 1616 ath_hw_setbssidmask(common);
1617 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1618 ath9k_hw_write_associd(ah);
1619 REG_WRITE(ah, AR_ISR, ~0);
1620 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1621
1622 REGWRITE_BUFFER_FLUSH(ah);
1623
1624 ath9k_hw_set_operating_mode(ah, ah->opmode);
1625}
1626
1627static void ath9k_hw_init_queues(struct ath_hw *ah)
1628{
1629 int i;
1630
1631 ENABLE_REGWRITE_BUFFER(ah);
1632
1633 for (i = 0; i < AR_NUM_DCU; i++)
1634 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1635
1636 REGWRITE_BUFFER_FLUSH(ah);
1637
1638 ah->intr_txqs = 0;
1639 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1640 ath9k_hw_resettxqueue(ah, i);
1641}
1642
1643/*
1644 * For big endian systems turn on swapping for descriptors
1645 */
1646static void ath9k_hw_init_desc(struct ath_hw *ah)
1647{
1648 struct ath_common *common = ath9k_hw_common(ah);
1649
1650 if (AR_SREV_9100(ah)) {
1651 u32 mask;
1652 mask = REG_READ(ah, AR_CFG);
1653 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1654 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1655 mask);
1656 } else {
1657 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1658 REG_WRITE(ah, AR_CFG, mask);
1659 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1660 REG_READ(ah, AR_CFG));
1661 }
1662 } else {
1663 if (common->bus_ops->ath_bus_type == ATH_USB) {
1664 /* Configure AR9271 target WLAN */
1665 if (AR_SREV_9271(ah))
1666 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1667 else
1668 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1669 }
1670#ifdef __BIG_ENDIAN
1671 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
2c323058 1672 AR_SREV_9550(ah) || AR_SREV_9531(ah))
15d2b585
SM		 1673 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1674 else
1675 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1676#endif
1677 }
1678}
1679
caed6579
SM		 1680/*
1681 * Fast channel change:
1682 * (Change synthesizer based on channel freq without resetting chip)
caed6579
SM		 1683 */
1684static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1685{
1686 struct ath_common *common = ath9k_hw_common(ah);
b840cffe 1687 struct ath9k_hw_capabilities *pCap = &ah->caps;
caed6579
SM		 1688 int ret;
1689
1690 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1691 goto fail;
1692
1693 if (ah->chip_fullsleep)
1694 goto fail;
1695
1696 if (!ah->curchan)
1697 goto fail;
1698
1699 if (chan->channel == ah->curchan->channel)
1700 goto fail;
1701
feb7bc99
FF		 1702 if ((ah->curchan->channelFlags | chan->channelFlags) &
1703 (CHANNEL_HALF | CHANNEL_QUARTER))
1704 goto fail;
1705
b840cffe 1706 /*
6b21fd20 1707 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
b840cffe 1708 */
6b21fd20 1709 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
af02efb3 1710 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
6b21fd20 1711 goto fail;
caed6579
SM		 1712
1713 if (!ath9k_hw_check_alive(ah))
1714 goto fail;
1715
1716 /*
1717 * For AR9462, make sure that calibration data for
1718 * re-using are present.
1719 */
8a90555f 1720 if (AR_SREV_9462(ah) && (ah->caldata &&
4b9b42bf
SM		 1721 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1722 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1723 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
caed6579
SM		 1724 goto fail;
1725
1726 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1727 ah->curchan->channel, chan->channel);
1728
1729 ret = ath9k_hw_channel_change(ah, chan);
1730 if (!ret)
1731 goto fail;
1732
5955b2b0 1733 if (ath9k_hw_mci_is_enabled(ah))
1bde95fa 1734 ar9003_mci_2g5g_switch(ah, false);
caed6579 1735
88033318
RM		 1736 ath9k_hw_loadnf(ah, ah->curchan);
1737 ath9k_hw_start_nfcal(ah, true);
1738
caed6579
SM		 1739 if (AR_SREV_9271(ah))
1740 ar9002_hw_load_ani_reg(ah, chan);
1741
1742 return 0;
1743fail:
1744 return -EINVAL;
1745}
1746
8d7e09dd
FF		 1747u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur)
1748{
1749 struct timespec ts;
1750 s64 usec;
1751
1752 if (!cur) {
1753 getrawmonotonic(&ts);
1754 cur = &ts;
1755 }
1756
1757 usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000;
1758 usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000;
1759
1760 return (u32) usec;
1761}
1762EXPORT_SYMBOL(ath9k_hw_get_tsf_offset);
1763
cbe61d8a 1764int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 1765 struct ath9k_hw_cal_data *caldata, bool fastcc)
f078f209 1766{
1510718d 1767 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1768 u32 saveLedState;
f078f209
LR		 1769 u32 saveDefAntenna;
1770 u32 macStaId1;
46fe782c 1771 u64 tsf = 0;
09d8e315 1772 s64 usec = 0;
15d2b585 1773 int r;
caed6579 1774 bool start_mci_reset = false;
63d32967
MSS		 1775 bool save_fullsleep = ah->chip_fullsleep;
1776
5955b2b0 1777 if (ath9k_hw_mci_is_enabled(ah)) {
528e5d36
SM		 1778 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1779 if (start_mci_reset)
1780 return 0;
63d32967
MSS		 1781 }
1782
9ecdef4b 1783 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1784 return -EIO;
f078f209 1785
caed6579
SM		 1786 if (ah->curchan && !ah->chip_fullsleep)
1787 ath9k_hw_getnf(ah, ah->curchan);
f078f209 1788
20bd2a09 1789 ah->caldata = caldata;
fcb9a3de 1790 if (caldata && (chan->channel != caldata->channel ||
6b21fd20 1791 chan->channelFlags != caldata->channelFlags)) {
20bd2a09
FF		 1792 /* Operating channel changed, reset channel calibration data */
1793 memset(caldata, 0, sizeof(*caldata));
1794 ath9k_init_nfcal_hist_buffer(ah, chan);
51dea9be 1795 } else if (caldata) {
4b9b42bf 1796 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
20bd2a09 1797 }
5bc225ac 1798 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
20bd2a09 1799
caed6579
SM		 1800 if (fastcc) {
1801 r = ath9k_hw_do_fastcc(ah, chan);
1802 if (!r)
1803 return r;
f078f209
LR		 1804 }
1805
5955b2b0 1806 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1807 ar9003_mci_stop_bt(ah, save_fullsleep);
63d32967 1808
f078f209
LR		 1809 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1810 if (saveDefAntenna == 0)
1811 saveDefAntenna = 1;
1812
1813 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1814
09d8e315
FF		 1815 /* Save TSF before chip reset, a cold reset clears it */
1816 tsf = ath9k_hw_gettsf64(ah);
6438e0dd 1817 usec = ktime_to_us(ktime_get_raw());
46fe782c 1818
f078f209
LR		 1819 saveLedState = REG_READ(ah, AR_CFG_LED) &
1820 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1821 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1822
1823 ath9k_hw_mark_phy_inactive(ah);
1824
45ef6a0b
VT		 1825 ah->paprd_table_write_done = false;
1826
05020d23 1827 /* Only required on the first reset */
d7e7d229
LR		 1828 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1829 REG_WRITE(ah,
1830 AR9271_RESET_POWER_DOWN_CONTROL,
1831 AR9271_RADIO_RF_RST);
1832 udelay(50);
1833 }
1834
f078f209 1835 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1836 ath_err(common, "Chip reset failed\n");
ae8d2858 1837 return -EINVAL;
f078f209
LR		 1838 }
1839
05020d23 1840 /* Only required on the first reset */
d7e7d229
LR		 1841 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1842 ah->htc_reset_init = false;
1843 REG_WRITE(ah,
1844 AR9271_RESET_POWER_DOWN_CONTROL,
1845 AR9271_GATE_MAC_CTL);
1846 udelay(50);
1847 }
1848
46fe782c 1849 /* Restore TSF */
6438e0dd 1850 usec = ktime_to_us(ktime_get_raw()) - usec;
09d8e315 1851 ath9k_hw_settsf64(ah, tsf + usec);
46fe782c 1852
7a37081e 1853 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1854 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1855
e9141f71
S		 1856 if (!AR_SREV_9300_20_OR_LATER(ah))
1857 ar9002_hw_enable_async_fifo(ah);
1858
25c56eec 1859 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1860 if (r)
1861 return r;
f078f209 1862
935d00cc
LB		 1863 ath9k_hw_set_rfmode(ah, chan);
1864
5955b2b0 1865 if (ath9k_hw_mci_is_enabled(ah))
63d32967
MSS		 1866 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1867
f860d526
FF		 1868 /*
1869 * Some AR91xx SoC devices frequently fail to accept TSF writes
1870 * right after the chip reset. When that happens, write a new
1871 * value after the initvals have been applied, with an offset
1872 * based on measured time difference
1873 */
1874 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1875 tsf += 1500;
1876 ath9k_hw_settsf64(ah, tsf);
1877 }
1878
15d2b585 1879 ath9k_hw_init_mfp(ah);
0ced0e17 1880
81c507a8 1881 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1882 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1883 ah->eep_ops->set_board_values(ah, chan);
a7765828 1884
15d2b585 1885 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
00e0003e 1886
8fe65368 1887 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1888 if (r)
1889 return r;
f078f209 1890
dfdac8ac
FF		 1891 ath9k_hw_set_clockrate(ah);
1892
15d2b585 1893 ath9k_hw_init_queues(ah);
2660b81a 1894 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1895 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1896 ath9k_hw_init_qos(ah);
1897
2660b81a 1898 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
55821324 1899 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3b319aae 1900
0005baf4 1901 ath9k_hw_init_global_settings(ah);
f078f209 1902
fe2b6afb
FF		 1903 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1904 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1905 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1906 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1907 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1908 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1909 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 1910 }
1911
ca7a4deb 1912 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1913
1914 ath9k_hw_set_dma(ah);
1915
ed6ebd8b
RM		 1916 if (!ath9k_hw_mci_is_enabled(ah))
1917 REG_WRITE(ah, AR_OBS, 8);
f078f209 1918
0ce024cb 1919 if (ah->config.rx_intr_mitigation) {
a64e1a45
SM		 1920 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
1921 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
f078f209
LR		 1922 }
1923
7f62a136
VT		 1924 if (ah->config.tx_intr_mitigation) {
1925 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1926 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1927 }
1928
f078f209
LR		 1929 ath9k_hw_init_bb(ah, chan);
1930
77a5a664 1931 if (caldata) {
4b9b42bf
SM		 1932 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
1933 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
77a5a664 1934 }
ae8d2858 1935 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1936 return -EIO;
f078f209 1937
5955b2b0 1938 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
528e5d36 1939 return -EIO;
63d32967 1940
7d0d0df0 1941 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1942
8fe65368 1943 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1944 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1945
7d0d0df0 1946 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1947
15d2b585 1948 ath9k_hw_init_desc(ah);
f078f209 1949
dbccdd1d 1950 if (ath9k_hw_btcoex_is_enabled(ah))
42cc41ed
VT		 1951 ath9k_hw_btcoex_enable(ah);
1952
5955b2b0 1953 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1954 ar9003_mci_check_bt(ah);
63d32967 1955
7b89fccf
FF		 1956 if (AR_SREV_9300_20_OR_LATER(ah)) {
1957 ath9k_hw_loadnf(ah, chan);
1958 ath9k_hw_start_nfcal(ah, true);
1959 }
1fe860ed 1960
a7abaf7d 1961 if (AR_SREV_9300_20_OR_LATER(ah))
aea702b7 1962 ar9003_hw_bb_watchdog_config(ah);
a7abaf7d
SM		 1963
1964 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
51ac8cbb 1965 ar9003_hw_disable_phy_restart(ah);
51ac8cbb 1966
691680b8
FF		 1967 ath9k_hw_apply_gpio_override(ah);
1968
7bdea96a 1969 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
362cd03f
SM		 1970 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
1971
4307b0fe
LB		 1972 if (ah->hw->conf.radar_enabled) {
1973 /* set HW specific DFS configuration */
7a0a260a 1974 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan);
4307b0fe
LB		 1975 ath9k_hw_set_radar_params(ah);
1976 }
1977
ae8d2858 1978 return 0;
f078f209 1979}
7322fd19 1980EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1981
f1dc5600
S		 1982/******************************/
1983/* Power Management (Chipset) */
1984/******************************/
1985
42d5bc3f
LR		 1986/*
1987 * Notify Power Mgt is disabled in self-generated frames.
1988 * If requested, force chip to sleep.
1989 */
31604cf0 1990static void ath9k_set_power_sleep(struct ath_hw *ah)
f078f209 1991{
f1dc5600 1992 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2577c6e8 1993
a4a2954f 1994 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
153dccd4
RM		 1995 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
1996 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
1997 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
31604cf0
SM		 1998 /* xxx Required for WLAN only case ? */
1999 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2000 udelay(100);
2001 }
2577c6e8 2002
31604cf0
SM		 2003 /*
2004 * Clear the RTC force wake bit to allow the
2005 * mac to go to sleep.
2006 */
2007 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
2008
153dccd4 2009 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2010 udelay(100);
2577c6e8 2011
31604cf0
SM		 2012 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2013 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 2014
31604cf0
SM		 2015 /* Shutdown chip. Active low */
2016 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2017 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
2018 udelay(2);
f1dc5600 2019 }
9a658d2b
LR		 2020
2021 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 2022 if (AR_SREV_9300_20_OR_LATER(ah))
2023 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2024}
2025
bbd79af5
LR		 2026/*
2027 * Notify Power Management is enabled in self-generating
2028 * frames. If request, set power mode of chip to
2029 * auto/normal. Duration in units of 128us (1/8 TU).
2030 */
31604cf0 2031static void ath9k_set_power_network_sleep(struct ath_hw *ah)
f078f209 2032{
31604cf0 2033 struct ath9k_hw_capabilities *pCap = &ah->caps;
2577c6e8 2034
f1dc5600 2035 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2036
31604cf0
SM		 2037 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2038 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2039 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2040 AR_RTC_FORCE_WAKE_ON_INT);
2041 } else {
2577c6e8 2042
31604cf0
SM		 2043 /* When chip goes into network sleep, it could be waken
2044 * up by MCI_INT interrupt caused by BT's HW messages
2045 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2046 * rate (~100us). This will cause chip to leave and
2047 * re-enter network sleep mode frequently, which in
2048 * consequence will have WLAN MCI HW to generate lots of
2049 * SYS_WAKING and SYS_SLEEPING messages which will make
2050 * BT CPU to busy to process.
2051 */
153dccd4
RM		 2052 if (ath9k_hw_mci_is_enabled(ah))
2053 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2054 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
31604cf0
SM		 2055 /*
2056 * Clear the RTC force wake bit to allow the
2057 * mac to go to sleep.
2058 */
153dccd4 2059 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
31604cf0 2060
153dccd4 2061 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2062 udelay(30);
f078f209 2063 }
9a658d2b
LR		 2064
2065 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2066 if (AR_SREV_9300_20_OR_LATER(ah))
2067 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2068}
2069
31604cf0 2070static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
f078f209 2071{
f1dc5600
S		 2072 u32 val;
2073 int i;
f078f209 2074
9a658d2b
LR		 2075 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2076 if (AR_SREV_9300_20_OR_LATER(ah)) {
2077 REG_WRITE(ah, AR_WA, ah->WARegVal);
2078 udelay(10);
2079 }
2080
31604cf0
SM		 2081 if ((REG_READ(ah, AR_RTC_STATUS) &
2082 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2083 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2084 return false;
f1dc5600 2085 }
31604cf0
SM		 2086 if (!AR_SREV_9300_20_OR_LATER(ah))
2087 ath9k_hw_init_pll(ah, NULL);
2088 }
2089 if (AR_SREV_9100(ah))
2090 REG_SET_BIT(ah, AR_RTC_RESET,
2091 AR_RTC_RESET_EN);
2092
2093 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2094 AR_RTC_FORCE_WAKE_EN);
04575f21 2095 if (AR_SREV_9100(ah))
3683a07b 2096 mdelay(10);
04575f21
SM		 2097 else
2098 udelay(50);
f078f209 2099
31604cf0
SM		 2100 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2101 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2102 if (val == AR_RTC_STATUS_ON)
2103 break;
2104 udelay(50);
f1dc5600
S		 2105 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2106 AR_RTC_FORCE_WAKE_EN);
31604cf0
SM		 2107 }
2108 if (i == 0) {
2109 ath_err(ath9k_hw_common(ah),
2110 "Failed to wakeup in %uus\n",
2111 POWER_UP_TIME / 20);
2112 return false;
f078f209
LR		 2113 }
2114
cdbe408d
RM		 2115 if (ath9k_hw_mci_is_enabled(ah))
2116 ar9003_mci_set_power_awake(ah);
2117
f1dc5600 2118 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2119
f1dc5600 2120 return true;
f078f209
LR		 2121}
2122
9ecdef4b 2123bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2124{
c46917bb 2125 struct ath_common *common = ath9k_hw_common(ah);
31604cf0 2126 int status = true;
f1dc5600
S		 2127 static const char *modes[] = {
2128 "AWAKE",
2129 "FULL-SLEEP",
2130 "NETWORK SLEEP",
2131 "UNDEFINED"
2132 };
f1dc5600 2133
cbdec975
GJ		 2134 if (ah->power_mode == mode)
2135 return status;
2136
d2182b69 2137 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2138 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2139
2140 switch (mode) {
2141 case ATH9K_PM_AWAKE:
31604cf0 2142 status = ath9k_hw_set_power_awake(ah);
f1dc5600
S		 2143 break;
2144 case ATH9K_PM_FULL_SLEEP:
5955b2b0 2145 if (ath9k_hw_mci_is_enabled(ah))
d1ca8b8e 2146 ar9003_mci_set_full_sleep(ah);
1010911e 2147
31604cf0 2148 ath9k_set_power_sleep(ah);
2660b81a 2149 ah->chip_fullsleep = true;
f1dc5600
S		 2150 break;
2151 case ATH9K_PM_NETWORK_SLEEP:
31604cf0 2152 ath9k_set_power_network_sleep(ah);
f1dc5600 2153 break;
f078f209 2154 default:
3800276a 2155 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2156 return false;
2157 }
2660b81a 2158 ah->power_mode = mode;
f1dc5600 2159
69f4aab1
LR		 2160 /*
2161 * XXX: If this warning never comes up after a while then
2162 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2163 * ath9k_hw_setpower() return type void.
2164 */
97dcec57
SM		 2165
2166 if (!(ah->ah_flags & AH_UNPLUGGED))
2167 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2168
f1dc5600 2169 return status;
f078f209 2170}
7322fd19 2171EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2172
f1dc5600
S		 2173/*******************/
2174/* Beacon Handling */
2175/*******************/
2176
cbe61d8a 2177void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2178{
f078f209
LR		 2179 int flags = 0;
2180
7d0d0df0
S		 2181 ENABLE_REGWRITE_BUFFER(ah);
2182
2660b81a 2183 switch (ah->opmode) {
d97809db 2184 case NL80211_IFTYPE_ADHOC:
f078f209
LR		 2185 REG_SET_BIT(ah, AR_TXCFG,
2186 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2664d666 2187 case NL80211_IFTYPE_MESH_POINT:
d97809db 2188 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2189 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2190 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2191 TU_TO_USEC(ah->config.dma_beacon_response_time));
2192 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2193 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2194 flags |=
2195 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2196 break;
d97809db 2197 default:
d2182b69
JP		 2198 ath_dbg(ath9k_hw_common(ah), BEACON,
2199 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2200 return;
2201 break;
f078f209
LR		 2202 }
2203
dd347f2f
FF		 2204 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2205 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2206 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
f078f209 2207
7d0d0df0 2208 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2209
f078f209
LR		 2210 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2211}
7322fd19 2212EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2213
cbe61d8a 2214void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2215 const struct ath9k_beacon_state *bs)
f078f209
LR		 2216{
2217 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2218 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2219 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2220
7d0d0df0
S		 2221 ENABLE_REGWRITE_BUFFER(ah);
2222
4ed15762
FF		 2223 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2224 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2225 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
f078f209 2226
7d0d0df0 2227 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2228
f078f209
LR		 2229 REG_RMW_FIELD(ah, AR_RSSI_THR,
2230 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2231
f29f5c08 2232 beaconintval = bs->bs_intval;
f078f209
LR		 2233
2234 if (bs->bs_sleepduration > beaconintval)
2235 beaconintval = bs->bs_sleepduration;
2236
2237 dtimperiod = bs->bs_dtimperiod;
2238 if (bs->bs_sleepduration > dtimperiod)
2239 dtimperiod = bs->bs_sleepduration;
2240
2241 if (beaconintval == dtimperiod)
2242 nextTbtt = bs->bs_nextdtim;
2243 else
2244 nextTbtt = bs->bs_nexttbtt;
2245
d2182b69
JP		 2246 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2247 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2248 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2249 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2250
7d0d0df0
S		 2251 ENABLE_REGWRITE_BUFFER(ah);
2252
4ed15762
FF		 2253 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2254 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
f078f209 2255
f1dc5600
S		 2256 REG_WRITE(ah, AR_SLEEP1,
2257 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2258 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2259
f1dc5600
S		 2260 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2261 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2262 else
2263 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2264
f1dc5600
S		 2265 REG_WRITE(ah, AR_SLEEP2,
2266 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2267
4ed15762
FF		 2268 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2269 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
f078f209 2270
7d0d0df0 2271 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2272
f1dc5600
S		 2273 REG_SET_BIT(ah, AR_TIMER_MODE,
2274 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2275 AR_DTIM_TIMER_EN);
f078f209 2276
4af9cf4f
S		 2277 /* TSF Out of Range Threshold */
2278 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2279}
7322fd19 2280EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2281
f1dc5600
S		 2282/*******************/
2283/* HW Capabilities */
2284/*******************/
2285
6054069a
FF		 2286static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2287{
2288 eeprom_chainmask &= chip_chainmask;
2289 if (eeprom_chainmask)
2290 return eeprom_chainmask;
2291 else
2292 return chip_chainmask;
2293}
2294
9a66af33
ZK		 2295/**
2296 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2297 * @ah: the atheros hardware data structure
2298 *
2299 * We enable DFS support upstream on chipsets which have passed a series
2300 * of tests. The testing requirements are going to be documented. Desired
2301 * test requirements are documented at:
2302 *
2303 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2304 *
2305 * Once a new chipset gets properly tested an individual commit can be used
2306 * to document the testing for DFS for that chipset.
2307 */
2308static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2309{
2310
2311 switch (ah->hw_version.macVersion) {
73e4937d
ZK		 2312 /* for temporary testing DFS with 9280 */
2313 case AR_SREV_VERSION_9280:
9a66af33
ZK		 2314 /* AR9580 will likely be our first target to get testing on */
2315 case AR_SREV_VERSION_9580:
73e4937d 2316 return true;
9a66af33
ZK		 2317 default:
2318 return false;
2319 }
2320}
2321
a9a29ce6 2322int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2323{
2660b81a 2324 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2325 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2326 struct ath_common *common = ath9k_hw_common(ah);
6054069a 2327 unsigned int chip_chainmask;
608b88cb 2328
0ff2b5c0 2329 u16 eeval;
47c80de6 2330 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2331
f74df6fb 2332 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2333 regulatory->current_rd = eeval;
f078f209 2334
2660b81a 2335 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2336 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2337 if (regulatory->current_rd == 0x64 ||
2338 regulatory->current_rd == 0x65)
2339 regulatory->current_rd += 5;
2340 else if (regulatory->current_rd == 0x41)
2341 regulatory->current_rd = 0x43;
d2182b69
JP		 2342 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2343 regulatory->current_rd);
f1dc5600 2344 }
f078f209 2345
f74df6fb 2346 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6 2347 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3800276a
JP		 2348 ath_err(common,
2349 "no band has been marked as supported in EEPROM\n");
a9a29ce6
GJ		 2350 return -EINVAL;
2351 }
2352
d4659912
FF		 2353 if (eeval & AR5416_OPFLAGS_11A)
2354 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 2355
d4659912
FF		 2356 if (eeval & AR5416_OPFLAGS_11G)
2357 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 2358
e41db61d
SM		 2359 if (AR_SREV_9485(ah) ||
2360 AR_SREV_9285(ah) ||
2361 AR_SREV_9330(ah) ||
2362 AR_SREV_9565(ah))
6054069a 2363 chip_chainmask = 1;
ba5736a5
MSS		 2364 else if (AR_SREV_9462(ah))
2365 chip_chainmask = 3;
6054069a
FF		 2366 else if (!AR_SREV_9280_20_OR_LATER(ah))
2367 chip_chainmask = 7;
2368 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2369 chip_chainmask = 3;
2370 else
2371 chip_chainmask = 7;
2372
f74df6fb 2373 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2374 /*
2375 * For AR9271 we will temporarilly uses the rx chainmax as read from
2376 * the EEPROM.
2377 */
8147f5de 2378 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2379 !(eeval & AR5416_OPFLAGS_11A) &&
2380 !(AR_SREV_9271(ah)))
2381 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2382 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2383 else if (AR_SREV_9100(ah))
2384 pCap->rx_chainmask = 0x7;
8147f5de 2385 else
d7e7d229 2386 /* Use rx_chainmask from EEPROM. */
8147f5de 2387 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2388
6054069a
FF		 2389 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2390 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2391 ah->txchainmask = pCap->tx_chainmask;
2392 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2393
7a37081e 2394 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2395
02d2ebb2
FF		 2396 /* enable key search for every frame in an aggregate */
2397 if (AR_SREV_9300_20_OR_LATER(ah))
2398 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2399
ce2220d1
BR		 2400 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2401
0db156e9 2402 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2403 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2404 else
2405 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2406
5b5fa355
S		 2407 if (AR_SREV_9271(ah))
2408 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 2409 else if (AR_DEVID_7010(ah))
2410 pCap->num_gpio_pins = AR7010_NUM_GPIO;
6321eb09
MSS		 2411 else if (AR_SREV_9300_20_OR_LATER(ah))
2412 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2413 else if (AR_SREV_9287_11_OR_LATER(ah))
2414 pCap->num_gpio_pins = AR9287_NUM_GPIO;
e17f83ea 2415 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2416 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 2417 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 2418 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2419 else
2420 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2421
1b2538b2 2422 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2423 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2424 else
f1dc5600 2425 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2426
74e13060 2427#ifdef CONFIG_ATH9K_RFKILL
2660b81a
S		 2428 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2429 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2430 ah->rfkill_gpio =
2431 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2432 ah->rfkill_polarity =
2433 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2434
2435 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2436 }
f1dc5600 2437#endif
d5d1154f 2438 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2439 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2440 else
2441 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2442
e7594072 2443 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2444 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2445 else
2446 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2447
ceb26445 2448 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2449 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
a4a2954f 2450 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
784ad503
VT		 2451 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2452
ceb26445
VT		 2453 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2454 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2455 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2456 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2457 pCap->txs_len = sizeof(struct ar9003_txs);
162c3be3
VT		 2458 } else {
2459 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2460 if (AR_SREV_9280_20(ah))
6b42e8d0 2461 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2462 }
1adf02ff 2463
6c84ce08
VT		 2464 if (AR_SREV_9300_20_OR_LATER(ah))
2465 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2466
6ee63f55
SB		 2467 if (AR_SREV_9300_20_OR_LATER(ah))
2468 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2469
a42acef0 2470 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2471 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2472
f85c3371 2473 if (AR_SREV_9285(ah)) {
754dc536
VT		 2474 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2475 ant_div_ctl1 =
2476 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2477 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
754dc536 2478 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2479 ath_info(common, "Enable LNA combining\n");
2480 }
754dc536 2481 }
f85c3371
SM		 2482 }
2483
ea066d5a
MSS		 2484 if (AR_SREV_9300_20_OR_LATER(ah)) {
2485 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2486 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2487 }
2488
06236e53 2489 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
21d2c63a 2490 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2491 if ((ant_div_ctl1 >> 0x6) == 0x3) {
21d2c63a 2492 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2493 ath_info(common, "Enable LNA combining\n");
2494 }
21d2c63a 2495 }
754dc536 2496
9a66af33
ZK		 2497 if (ath9k_hw_dfs_tested(ah))
2498 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2499
47c80de6
VT		 2500 tx_chainmask = pCap->tx_chainmask;
2501 rx_chainmask = pCap->rx_chainmask;
2502 while (tx_chainmask || rx_chainmask) {
2503 if (tx_chainmask & BIT(0))
2504 pCap->max_txchains++;
2505 if (rx_chainmask & BIT(0))
2506 pCap->max_rxchains++;
2507
2508 tx_chainmask >>= 1;
2509 rx_chainmask >>= 1;
2510 }
2511
a4a2954f 2512 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3789d59c
MSS		 2513 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2514 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2515
2b5e54e2 2516 if (AR_SREV_9462_20_OR_LATER(ah))
3789d59c 2517 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
3789d59c
MSS		 2518 }
2519
846e438f
SM		 2520 if (AR_SREV_9462(ah))
2521 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE;
d687809b 2522
0f21ee8d
SM		 2523 if (AR_SREV_9300_20_OR_LATER(ah) &&
2524 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2525 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2526
a9a29ce6 2527 return 0;
f078f209
LR		 2528}
2529
f1dc5600
S		 2530/****************************/
2531/* GPIO / RFKILL / Antennae */
2532/****************************/
f078f209 2533
cbe61d8a 2534static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2535 u32 gpio, u32 type)
2536{
2537 int addr;
2538 u32 gpio_shift, tmp;
f078f209 2539
f1dc5600
S		 2540 if (gpio > 11)
2541 addr = AR_GPIO_OUTPUT_MUX3;
2542 else if (gpio > 5)
2543 addr = AR_GPIO_OUTPUT_MUX2;
2544 else
2545 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2546
f1dc5600 2547 gpio_shift = (gpio % 6) * 5;
f078f209 2548
f1dc5600
S		 2549 if (AR_SREV_9280_20_OR_LATER(ah)
2550 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2551 REG_RMW(ah, addr, (type << gpio_shift),
2552 (0x1f << gpio_shift));
f078f209 2553 } else {
f1dc5600
S		 2554 tmp = REG_READ(ah, addr);
2555 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2556 tmp &= ~(0x1f << gpio_shift);
2557 tmp |= (type << gpio_shift);
2558 REG_WRITE(ah, addr, tmp);
f078f209 2559 }
f078f209
LR		 2560}
2561
cbe61d8a 2562void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2563{
f1dc5600 2564 u32 gpio_shift;
f078f209 2565
9680e8a3 2566 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2567
88c1f4f6
S		 2568 if (AR_DEVID_7010(ah)) {
2569 gpio_shift = gpio;
2570 REG_RMW(ah, AR7010_GPIO_OE,
2571 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2572 (AR7010_GPIO_OE_MASK << gpio_shift));
2573 return;
2574 }
f078f209 2575
88c1f4f6 2576 gpio_shift = gpio << 1;
f1dc5600
S		 2577 REG_RMW(ah,
2578 AR_GPIO_OE_OUT,
2579 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2580 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2581}
7322fd19 2582EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2583
cbe61d8a 2584u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2585{
cb33c412
SB		 2586#define MS_REG_READ(x, y) \
2587 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2588
2660b81a 2589 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2590 return 0xffffffff;
f078f209 2591
88c1f4f6
S		 2592 if (AR_DEVID_7010(ah)) {
2593 u32 val;
2594 val = REG_READ(ah, AR7010_GPIO_IN);
2595 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2596 } else if (AR_SREV_9300_20_OR_LATER(ah))
9306990a
VT		 2597 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2598 AR_GPIO_BIT(gpio)) != 0;
783dfca1 2599 else if (AR_SREV_9271(ah))
5b5fa355 2600 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2601 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2602 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2603 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2604 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2605 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2606 return MS_REG_READ(AR928X, gpio) != 0;
2607 else
2608 return MS_REG_READ(AR, gpio) != 0;
f078f209 2609}
7322fd19 2610EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2611
cbe61d8a 2612void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2613 u32 ah_signal_type)
f078f209 2614{
f1dc5600 2615 u32 gpio_shift;
f078f209 2616
88c1f4f6
S		 2617 if (AR_DEVID_7010(ah)) {
2618 gpio_shift = gpio;
2619 REG_RMW(ah, AR7010_GPIO_OE,
2620 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2621 (AR7010_GPIO_OE_MASK << gpio_shift));
2622 return;
2623 }
f078f209 2624
88c1f4f6 2625 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2626 gpio_shift = 2 * gpio;
f1dc5600
S		 2627 REG_RMW(ah,
2628 AR_GPIO_OE_OUT,
2629 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2630 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2631}
7322fd19 2632EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2633
cbe61d8a 2634void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2635{
88c1f4f6
S		 2636 if (AR_DEVID_7010(ah)) {
2637 val = val ? 0 : 1;
2638 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2639 AR_GPIO_BIT(gpio));
2640 return;
2641 }
2642
5b5fa355
S		 2643 if (AR_SREV_9271(ah))
2644 val = ~val;
2645
f1dc5600
S		 2646 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2647 AR_GPIO_BIT(gpio));
f078f209 2648}
7322fd19 2649EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2650
cbe61d8a 2651void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2652{
f1dc5600 2653 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2654}
7322fd19 2655EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2656
f1dc5600
S		 2657/*********************/
2658/* General Operation */
2659/*********************/
2660
cbe61d8a 2661u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2662{
f1dc5600
S		 2663 u32 bits = REG_READ(ah, AR_RX_FILTER);
2664 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2665
f1dc5600
S		 2666 if (phybits & AR_PHY_ERR_RADAR)
2667 bits |= ATH9K_RX_FILTER_PHYRADAR;
2668 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2669 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2670
f1dc5600 2671 return bits;
f078f209 2672}
7322fd19 2673EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2674
cbe61d8a 2675void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2676{
f1dc5600 2677 u32 phybits;
f078f209 2678
7d0d0df0
S		 2679 ENABLE_REGWRITE_BUFFER(ah);
2680
a4a2954f 2681 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2577c6e8
SB		 2682 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2683
7ea310be
S		 2684 REG_WRITE(ah, AR_RX_FILTER, bits);
2685
f1dc5600
S		 2686 phybits = 0;
2687 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2688 phybits |= AR_PHY_ERR_RADAR;
2689 if (bits & ATH9K_RX_FILTER_PHYERR)
2690 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2691 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2692
f1dc5600 2693 if (phybits)
ca7a4deb 2694 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2695 else
ca7a4deb 2696 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2697
2698 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2699}
7322fd19 2700EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2701
cbe61d8a 2702bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2703{
99922a45
RM		 2704 if (ath9k_hw_mci_is_enabled(ah))
2705 ar9003_mci_bt_gain_ctrl(ah);
2706
63a75b91
SB		 2707 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2708 return false;
2709
2710 ath9k_hw_init_pll(ah, NULL);
8efa7a81 2711 ah->htc_reset_init = true;
63a75b91 2712 return true;
f1dc5600 2713}
7322fd19 2714EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2715
cbe61d8a 2716bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2717{
9ecdef4b 2718 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2719 return false;
f078f209 2720
63a75b91
SB		 2721 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2722 return false;
2723
2724 ath9k_hw_init_pll(ah, NULL);
2725 return true;
f078f209 2726}
7322fd19 2727EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2728
ca2c68cc
FF		 2729static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2730{
2731 enum eeprom_param gain_param;
2732
2733 if (IS_CHAN_2GHZ(chan))
2734 gain_param = EEP_ANTENNA_GAIN_2G;
2735 else
2736 gain_param = EEP_ANTENNA_GAIN_5G;
2737
2738 return ah->eep_ops->get_eeprom(ah, gain_param);
2739}
2740
64ea57d0
GJ		 2741void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2742 bool test)
ca2c68cc
FF		 2743{
2744 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2745 struct ieee80211_channel *channel;
2746 int chan_pwr, new_pwr, max_gain;
2747 int ant_gain, ant_reduction = 0;
2748
2749 if (!chan)
2750 return;
2751
2752 channel = chan->chan;
2753 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2754 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2755 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2756
2757 ant_gain = get_antenna_gain(ah, chan);
2758 if (ant_gain > max_gain)
2759 ant_reduction = ant_gain - max_gain;
2760
2761 ah->eep_ops->set_txpower(ah, chan,
2762 ath9k_regd_get_ctl(reg, chan),
64ea57d0 2763 ant_reduction, new_pwr, test);
ca2c68cc
FF		 2764}
2765
de40f316 2766void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2767{
ca2c68cc 2768 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2769 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2770 struct ieee80211_channel *channel = chan->chan;
9c204b46 2771
48ef5c42 2772 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2773 if (test)
ca2c68cc 2774 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2775
64ea57d0 2776 ath9k_hw_apply_txpower(ah, chan, test);
6f255425 2777
ca2c68cc
FF		 2778 if (test)
2779 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2780}
7322fd19 2781EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2782
cbe61d8a 2783void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2784{
2660b81a 2785 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2786}
7322fd19 2787EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2788
cbe61d8a 2789void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2790{
f1dc5600
S		 2791 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2792 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2793}
7322fd19 2794EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2795
f2b2143e 2796void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2797{
1510718d
LR		 2798 struct ath_common *common = ath9k_hw_common(ah);
2799
2800 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2801 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2802 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2803}
7322fd19 2804EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2805
1c0fc65e
BP		 2806#define ATH9K_MAX_TSF_READ 10
2807
cbe61d8a 2808u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2809{
1c0fc65e
BP		 2810 u32 tsf_lower, tsf_upper1, tsf_upper2;
2811 int i;
2812
2813 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2814 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2815 tsf_lower = REG_READ(ah, AR_TSF_L32);
2816 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2817 if (tsf_upper2 == tsf_upper1)
2818 break;
2819 tsf_upper1 = tsf_upper2;
2820 }
f078f209 2821
1c0fc65e 2822 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2823
1c0fc65e 2824 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2825}
7322fd19 2826EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2827
cbe61d8a 2828void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2829{
27abe060 2830 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2831 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2832}
7322fd19 2833EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2834
cbe61d8a 2835void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2836{
f9b604f6
GJ		 2837 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2838 AH_TSF_WRITE_TIMEOUT))
d2182b69 2839 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 2840 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2841
f1dc5600
S		 2842 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2843}
7322fd19 2844EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2845
60ca9f87 2846void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
f1dc5600 2847{
60ca9f87 2848 if (set)
2660b81a 2849 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2850 else
2660b81a 2851 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2852}
7322fd19 2853EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2854
e4744ec7 2855void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 2856{
2857 u32 macmode;
2858
e4744ec7 2859 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2860 macmode = AR_2040_JOINED_RX_CLEAR;
2861 else
2862 macmode = 0;
f078f209 2863
f1dc5600 2864 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2865}
ff155a45
VT		 2866
2867/* HW Generic timers configuration */
2868
2869static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2870{
2871 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2872 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2873 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2874 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2875 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2876 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2877 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2878 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2879 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2880 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2881 AR_NDP2_TIMER_MODE, 0x0002},
2882 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2883 AR_NDP2_TIMER_MODE, 0x0004},
2884 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2885 AR_NDP2_TIMER_MODE, 0x0008},
2886 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2887 AR_NDP2_TIMER_MODE, 0x0010},
2888 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2889 AR_NDP2_TIMER_MODE, 0x0020},
2890 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2891 AR_NDP2_TIMER_MODE, 0x0040},
2892 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2893 AR_NDP2_TIMER_MODE, 0x0080}
2894};
2895
2896/* HW generic timer primitives */
2897
dd347f2f 2898u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2899{
2900 return REG_READ(ah, AR_TSF_L32);
2901}
dd347f2f 2902EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2903
2904struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2905 void (*trigger)(void *),
2906 void (*overflow)(void *),
2907 void *arg,
2908 u8 timer_index)
2909{
2910 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2911 struct ath_gen_timer *timer;
2912
c67ce339
FF		 2913 if ((timer_index < AR_FIRST_NDP_TIMER) ||
2914 (timer_index >= ATH_MAX_GEN_TIMER))
2915 return NULL;
2916
ff155a45 2917 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
14f8dc49 2918 if (timer == NULL)
ff155a45 2919 return NULL;
ff155a45
VT		 2920
2921 /* allocate a hardware generic timer slot */
2922 timer_table->timers[timer_index] = timer;
2923 timer->index = timer_index;
2924 timer->trigger = trigger;
2925 timer->overflow = overflow;
2926 timer->arg = arg;
2927
2928 return timer;
2929}
7322fd19 2930EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2931
cd9bf689
LR		 2932void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2933 struct ath_gen_timer *timer,
c67ce339 2934 u32 timer_next,
cd9bf689 2935 u32 timer_period)
ff155a45
VT		 2936{
2937 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
c67ce339 2938 u32 mask = 0;
788f6875 2939
c67ce339 2940 timer_table->timer_mask |= BIT(timer->index);
ff155a45 2941
ff155a45
VT		 2942 /*
2943 * Program generic timer registers
2944 */
2945 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2946 timer_next);
2947 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2948 timer_period);
2949 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2950 gen_tmr_configuration[timer->index].mode_mask);
2951
a4a2954f 2952 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2577c6e8 2953 /*
423e38e8 2954 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 2955 * to use. But we still follow the old rule, 0 - 7 use tsf and
2956 * 8 - 15 use tsf2.
2957 */
2958 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
2959 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2960 (1 << timer->index));
2961 else
2962 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2963 (1 << timer->index));
2964 }
2965
c67ce339
FF		 2966 if (timer->trigger)
2967 mask |= SM(AR_GENTMR_BIT(timer->index),
2968 AR_IMR_S5_GENTIMER_TRIG);
2969 if (timer->overflow)
2970 mask |= SM(AR_GENTMR_BIT(timer->index),
2971 AR_IMR_S5_GENTIMER_THRESH);
2972
2973 REG_SET_BIT(ah, AR_IMR_S5, mask);
2974
2975 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
2976 ah->imask |= ATH9K_INT_GENTIMER;
2977 ath9k_hw_set_interrupts(ah);
2978 }
ff155a45 2979}
7322fd19 2980EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 2981
cd9bf689 2982void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 2983{
2984 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2985
ff155a45
VT		 2986 /* Clear generic timer enable bits. */
2987 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2988 gen_tmr_configuration[timer->index].mode_mask);
2989
b7f59766
SM		 2990 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2991 /*
2992 * Need to switch back to TSF if it was using TSF2.
2993 */
2994 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
2995 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2996 (1 << timer->index));
2997 }
2998 }
2999
ff155a45
VT		 3000 /* Disable both trigger and thresh interrupt masks */
3001 REG_CLR_BIT(ah, AR_IMR_S5,
3002 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3003 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3004
c67ce339
FF		 3005 timer_table->timer_mask &= ~BIT(timer->index);
3006
3007 if (timer_table->timer_mask == 0) {
3008 ah->imask &= ~ATH9K_INT_GENTIMER;
3009 ath9k_hw_set_interrupts(ah);
3010 }
ff155a45 3011}
7322fd19 3012EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 3013
3014void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3015{
3016 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3017
3018 /* free the hardware generic timer slot */
3019 timer_table->timers[timer->index] = NULL;
3020 kfree(timer);
3021}
7322fd19 3022EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 3023
3024/*
3025 * Generic Timer Interrupts handling
3026 */
3027void ath_gen_timer_isr(struct ath_hw *ah)
3028{
3029 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3030 struct ath_gen_timer *timer;
c67ce339
FF		 3031 unsigned long trigger_mask, thresh_mask;
3032 unsigned int index;
ff155a45
VT		 3033
3034 /* get hardware generic timer interrupt status */
3035 trigger_mask = ah->intr_gen_timer_trigger;
3036 thresh_mask = ah->intr_gen_timer_thresh;
c67ce339
FF		 3037 trigger_mask &= timer_table->timer_mask;
3038 thresh_mask &= timer_table->timer_mask;
ff155a45 3039
c67ce339 3040 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3041 timer = timer_table->timers[index];
c67ce339
FF		 3042 if (!timer)
3043 continue;
3044 if (!timer->overflow)
3045 continue;
a6a172b2
FF		 3046
3047 trigger_mask &= ~BIT(index);
ff155a45
VT		 3048 timer->overflow(timer->arg);
3049 }
3050
c67ce339 3051 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3052 timer = timer_table->timers[index];
c67ce339
FF		 3053 if (!timer)
3054 continue;
3055 if (!timer->trigger)
3056 continue;
ff155a45
VT		 3057 timer->trigger(timer->arg);
3058 }
3059}
7322fd19 3060EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3061
05020d23
S		 3062/********/
3063/* HTC */
3064/********/
3065
2da4f01a
LR		 3066static struct {
3067 u32 version;
3068 const char * name;
3069} ath_mac_bb_names[] = {
3070 /* Devices with external radios */
3071 { AR_SREV_VERSION_5416_PCI, "5416" },
3072 { AR_SREV_VERSION_5416_PCIE, "5418" },
3073 { AR_SREV_VERSION_9100, "9100" },
3074 { AR_SREV_VERSION_9160, "9160" },
3075 /* Single-chip solutions */
3076 { AR_SREV_VERSION_9280, "9280" },
3077 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3078 { AR_SREV_VERSION_9287, "9287" },
3079 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3080 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3081 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3082 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3083 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3084 { AR_SREV_VERSION_9462, "9462" },
485124cb 3085 { AR_SREV_VERSION_9550, "9550" },
77fac465 3086 { AR_SREV_VERSION_9565, "9565" },
c08148bb 3087 { AR_SREV_VERSION_9531, "9531" },
2da4f01a
LR		 3088};
3089
3090/* For devices with external radios */
3091static struct {
3092 u16 version;
3093 const char * name;
3094} ath_rf_names[] = {
3095 { 0, "5133" },
3096 { AR_RAD5133_SREV_MAJOR, "5133" },
3097 { AR_RAD5122_SREV_MAJOR, "5122" },
3098 { AR_RAD2133_SREV_MAJOR, "2133" },
3099 { AR_RAD2122_SREV_MAJOR, "2122" }
3100};
3101
3102/*
3103 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3104 */
f934c4d9 3105static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3106{
3107 int i;
3108
3109 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3110 if (ath_mac_bb_names[i].version == mac_bb_version) {
3111 return ath_mac_bb_names[i].name;
3112 }
3113 }
3114
3115 return "????";
3116}
2da4f01a
LR		 3117
3118/*
3119 * Return the RF name. "????" is returned if the RF is unknown.
3120 * Used for devices with external radios.
3121 */
f934c4d9 3122static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3123{
3124 int i;
3125
3126 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3127 if (ath_rf_names[i].version == rf_version) {
3128 return ath_rf_names[i].name;
3129 }
3130 }
3131
3132 return "????";
3133}
f934c4d9
LR		 3134
3135void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3136{
3137 int used;
3138
3139 /* chipsets >= AR9280 are single-chip */
7a37081e 3140 if (AR_SREV_9280_20_OR_LATER(ah)) {
5e88ba62
ZK		 3141 used = scnprintf(hw_name, len,
3142 "Atheros AR%s Rev:%x",
3143 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3144 ah->hw_version.macRev);
f934c4d9
LR		 3145 }
3146 else {
5e88ba62
ZK		 3147 used = scnprintf(hw_name, len,
3148 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3149 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3150 ah->hw_version.macRev,
3151 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3152 & AR_RADIO_SREV_MAJOR)),
3153 ah->hw_version.phyRev);
f934c4d9
LR		 3154 }
3155
3156 hw_name[used] = '\0';
3157}
3158EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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