Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/io.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
9d9779e7 | 19 | #include <linux/module.h> |
09d8e315 | 20 | #include <linux/time.h> |
c67ce339 | 21 | #include <linux/bitops.h> |
5ca06ebe | 22 | #include <linux/etherdevice.h> |
61b559de | 23 | #include <linux/gpio.h> |
f078f209 LR |
24 | #include <asm/unaligned.h> |
25 | ||
af03abec | 26 | #include "hw.h" |
d70357d5 | 27 | #include "hw-ops.h" |
b622a720 | 28 | #include "ar9003_mac.h" |
f4701b5a | 29 | #include "ar9003_mci.h" |
362cd03f | 30 | #include "ar9003_phy.h" |
462e58f2 | 31 | #include "ath9k.h" |
f078f209 | 32 | |
cbe61d8a | 33 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); |
f078f209 | 34 | |
7322fd19 LR |
35 | MODULE_AUTHOR("Atheros Communications"); |
36 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
37 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
38 | MODULE_LICENSE("Dual BSD/GPL"); | |
39 | ||
dfdac8ac | 40 | static void ath9k_hw_set_clockrate(struct ath_hw *ah) |
f1dc5600 | 41 | { |
dfdac8ac | 42 | struct ath_common *common = ath9k_hw_common(ah); |
e4744ec7 | 43 | struct ath9k_channel *chan = ah->curchan; |
dfdac8ac | 44 | unsigned int clockrate; |
cbe61d8a | 45 | |
087b6ff6 FF |
46 | /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ |
47 | if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) | |
48 | clockrate = 117; | |
e4744ec7 | 49 | else if (!chan) /* should really check for CCK instead */ |
dfdac8ac | 50 | clockrate = ATH9K_CLOCK_RATE_CCK; |
e4744ec7 | 51 | else if (IS_CHAN_2GHZ(chan)) |
dfdac8ac FF |
52 | clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; |
53 | else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) | |
54 | clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; | |
e5553724 | 55 | else |
dfdac8ac FF |
56 | clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; |
57 | ||
beae416b MN |
58 | if (chan) { |
59 | if (IS_CHAN_HT40(chan)) | |
60 | clockrate *= 2; | |
e4744ec7 | 61 | if (IS_CHAN_HALF_RATE(chan)) |
906c7205 | 62 | clockrate /= 2; |
e4744ec7 | 63 | if (IS_CHAN_QUARTER_RATE(chan)) |
906c7205 FF |
64 | clockrate /= 4; |
65 | } | |
66 | ||
dfdac8ac | 67 | common->clockrate = clockrate; |
f1dc5600 S |
68 | } |
69 | ||
cbe61d8a | 70 | static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) |
f1dc5600 | 71 | { |
dfdac8ac | 72 | struct ath_common *common = ath9k_hw_common(ah); |
cbe61d8a | 73 | |
dfdac8ac | 74 | return usecs * common->clockrate; |
f1dc5600 | 75 | } |
f078f209 | 76 | |
0caa7b14 | 77 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) |
f078f209 LR |
78 | { |
79 | int i; | |
80 | ||
0caa7b14 S |
81 | BUG_ON(timeout < AH_TIME_QUANTUM); |
82 | ||
83 | for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { | |
f078f209 LR |
84 | if ((REG_READ(ah, reg) & mask) == val) |
85 | return true; | |
86 | ||
87 | udelay(AH_TIME_QUANTUM); | |
88 | } | |
04bd4638 | 89 | |
d2182b69 | 90 | ath_dbg(ath9k_hw_common(ah), ANY, |
226afe68 JP |
91 | "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", |
92 | timeout, reg, REG_READ(ah, reg), mask, val); | |
f078f209 | 93 | |
f1dc5600 | 94 | return false; |
f078f209 | 95 | } |
7322fd19 | 96 | EXPORT_SYMBOL(ath9k_hw_wait); |
f078f209 | 97 | |
7c5adc8d FF |
98 | void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, |
99 | int hw_delay) | |
100 | { | |
1a5e6326 | 101 | hw_delay /= 10; |
7c5adc8d FF |
102 | |
103 | if (IS_CHAN_HALF_RATE(chan)) | |
104 | hw_delay *= 2; | |
105 | else if (IS_CHAN_QUARTER_RATE(chan)) | |
106 | hw_delay *= 4; | |
107 | ||
108 | udelay(hw_delay + BASE_ACTIVATE_DELAY); | |
109 | } | |
110 | ||
0166b4be | 111 | void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, |
a9b6b256 FF |
112 | int column, unsigned int *writecnt) |
113 | { | |
114 | int r; | |
115 | ||
116 | ENABLE_REGWRITE_BUFFER(ah); | |
117 | for (r = 0; r < array->ia_rows; r++) { | |
118 | REG_WRITE(ah, INI_RA(array, r, 0), | |
119 | INI_RA(array, r, column)); | |
120 | DO_DELAY(*writecnt); | |
121 | } | |
122 | REGWRITE_BUFFER_FLUSH(ah); | |
123 | } | |
124 | ||
a57cb45a OR |
125 | void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size) |
126 | { | |
127 | u32 *tmp_reg_list, *tmp_data; | |
128 | int i; | |
129 | ||
130 | tmp_reg_list = kmalloc(size * sizeof(u32), GFP_KERNEL); | |
131 | if (!tmp_reg_list) { | |
132 | dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__); | |
133 | return; | |
134 | } | |
135 | ||
136 | tmp_data = kmalloc(size * sizeof(u32), GFP_KERNEL); | |
137 | if (!tmp_data) { | |
138 | dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__); | |
139 | goto error_tmp_data; | |
140 | } | |
141 | ||
142 | for (i = 0; i < size; i++) | |
143 | tmp_reg_list[i] = array[i][0]; | |
144 | ||
145 | REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size); | |
146 | ||
147 | for (i = 0; i < size; i++) | |
148 | array[i][1] = tmp_data[i]; | |
149 | ||
150 | kfree(tmp_data); | |
151 | error_tmp_data: | |
152 | kfree(tmp_reg_list); | |
153 | } | |
154 | ||
f078f209 LR |
155 | u32 ath9k_hw_reverse_bits(u32 val, u32 n) |
156 | { | |
157 | u32 retval; | |
158 | int i; | |
159 | ||
160 | for (i = 0, retval = 0; i < n; i++) { | |
161 | retval = (retval << 1) | (val & 1); | |
162 | val >>= 1; | |
163 | } | |
164 | return retval; | |
165 | } | |
166 | ||
cbe61d8a | 167 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
545750d3 | 168 | u8 phy, int kbps, |
f1dc5600 S |
169 | u32 frameLen, u16 rateix, |
170 | bool shortPreamble) | |
f078f209 | 171 | { |
f1dc5600 | 172 | u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; |
f078f209 | 173 | |
f1dc5600 S |
174 | if (kbps == 0) |
175 | return 0; | |
f078f209 | 176 | |
545750d3 | 177 | switch (phy) { |
46d14a58 | 178 | case WLAN_RC_PHY_CCK: |
f1dc5600 | 179 | phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; |
545750d3 | 180 | if (shortPreamble) |
f1dc5600 S |
181 | phyTime >>= 1; |
182 | numBits = frameLen << 3; | |
183 | txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); | |
184 | break; | |
46d14a58 | 185 | case WLAN_RC_PHY_OFDM: |
2660b81a | 186 | if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { |
f1dc5600 S |
187 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; |
188 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
189 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
190 | txTime = OFDM_SIFS_TIME_QUARTER | |
191 | + OFDM_PREAMBLE_TIME_QUARTER | |
192 | + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); | |
2660b81a S |
193 | } else if (ah->curchan && |
194 | IS_CHAN_HALF_RATE(ah->curchan)) { | |
f1dc5600 S |
195 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; |
196 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
197 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
198 | txTime = OFDM_SIFS_TIME_HALF + | |
199 | OFDM_PREAMBLE_TIME_HALF | |
200 | + (numSymbols * OFDM_SYMBOL_TIME_HALF); | |
201 | } else { | |
202 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; | |
203 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
204 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
205 | txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME | |
206 | + (numSymbols * OFDM_SYMBOL_TIME); | |
207 | } | |
208 | break; | |
209 | default: | |
3800276a JP |
210 | ath_err(ath9k_hw_common(ah), |
211 | "Unknown phy %u (rate ix %u)\n", phy, rateix); | |
f1dc5600 S |
212 | txTime = 0; |
213 | break; | |
214 | } | |
f078f209 | 215 | |
f1dc5600 S |
216 | return txTime; |
217 | } | |
7322fd19 | 218 | EXPORT_SYMBOL(ath9k_hw_computetxtime); |
f078f209 | 219 | |
cbe61d8a | 220 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
f1dc5600 S |
221 | struct ath9k_channel *chan, |
222 | struct chan_centers *centers) | |
f078f209 | 223 | { |
f1dc5600 | 224 | int8_t extoff; |
f078f209 | 225 | |
f1dc5600 S |
226 | if (!IS_CHAN_HT40(chan)) { |
227 | centers->ctl_center = centers->ext_center = | |
228 | centers->synth_center = chan->channel; | |
229 | return; | |
f078f209 | 230 | } |
f078f209 | 231 | |
8896934c | 232 | if (IS_CHAN_HT40PLUS(chan)) { |
f1dc5600 S |
233 | centers->synth_center = |
234 | chan->channel + HT40_CHANNEL_CENTER_SHIFT; | |
235 | extoff = 1; | |
236 | } else { | |
237 | centers->synth_center = | |
238 | chan->channel - HT40_CHANNEL_CENTER_SHIFT; | |
239 | extoff = -1; | |
240 | } | |
f078f209 | 241 | |
f1dc5600 S |
242 | centers->ctl_center = |
243 | centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); | |
6420014c | 244 | /* 25 MHz spacing is supported by hw but not on upper layers */ |
f1dc5600 | 245 | centers->ext_center = |
6420014c | 246 | centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); |
f078f209 LR |
247 | } |
248 | ||
f1dc5600 S |
249 | /******************/ |
250 | /* Chip Revisions */ | |
251 | /******************/ | |
252 | ||
cbe61d8a | 253 | static void ath9k_hw_read_revisions(struct ath_hw *ah) |
f078f209 | 254 | { |
f1dc5600 | 255 | u32 val; |
f078f209 | 256 | |
09c74f7b FF |
257 | if (ah->get_mac_revision) |
258 | ah->hw_version.macRev = ah->get_mac_revision(); | |
259 | ||
ecb1d385 VT |
260 | switch (ah->hw_version.devid) { |
261 | case AR5416_AR9100_DEVID: | |
262 | ah->hw_version.macVersion = AR_SREV_VERSION_9100; | |
263 | break; | |
3762561a GJ |
264 | case AR9300_DEVID_AR9330: |
265 | ah->hw_version.macVersion = AR_SREV_VERSION_9330; | |
09c74f7b | 266 | if (!ah->get_mac_revision) { |
3762561a GJ |
267 | val = REG_READ(ah, AR_SREV); |
268 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); | |
269 | } | |
270 | return; | |
ecb1d385 VT |
271 | case AR9300_DEVID_AR9340: |
272 | ah->hw_version.macVersion = AR_SREV_VERSION_9340; | |
ecb1d385 | 273 | return; |
813831dc GJ |
274 | case AR9300_DEVID_QCA955X: |
275 | ah->hw_version.macVersion = AR_SREV_VERSION_9550; | |
276 | return; | |
e6b1e46e SM |
277 | case AR9300_DEVID_AR953X: |
278 | ah->hw_version.macVersion = AR_SREV_VERSION_9531; | |
279 | return; | |
2131fabb MP |
280 | case AR9300_DEVID_QCA956X: |
281 | ah->hw_version.macVersion = AR_SREV_VERSION_9561; | |
7865598e | 282 | return; |
ecb1d385 VT |
283 | } |
284 | ||
f1dc5600 | 285 | val = REG_READ(ah, AR_SREV) & AR_SREV_ID; |
f078f209 | 286 | |
f1dc5600 S |
287 | if (val == 0xFF) { |
288 | val = REG_READ(ah, AR_SREV); | |
d535a42a S |
289 | ah->hw_version.macVersion = |
290 | (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; | |
291 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); | |
76ed94be | 292 | |
77fac465 | 293 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) |
76ed94be MSS |
294 | ah->is_pciexpress = true; |
295 | else | |
296 | ah->is_pciexpress = (val & | |
297 | AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; | |
f1dc5600 S |
298 | } else { |
299 | if (!AR_SREV_9100(ah)) | |
d535a42a | 300 | ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); |
f078f209 | 301 | |
d535a42a | 302 | ah->hw_version.macRev = val & AR_SREV_REVISION; |
f078f209 | 303 | |
d535a42a | 304 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) |
2660b81a | 305 | ah->is_pciexpress = true; |
f1dc5600 | 306 | } |
f078f209 LR |
307 | } |
308 | ||
f1dc5600 S |
309 | /************************************/ |
310 | /* HW Attach, Detach, Init Routines */ | |
311 | /************************************/ | |
312 | ||
cbe61d8a | 313 | static void ath9k_hw_disablepcie(struct ath_hw *ah) |
f078f209 | 314 | { |
040b74f7 | 315 | if (!AR_SREV_5416(ah)) |
f1dc5600 | 316 | return; |
f078f209 | 317 | |
f1dc5600 S |
318 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); |
319 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | |
320 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); | |
321 | REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); | |
322 | REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); | |
323 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); | |
324 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); | |
325 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | |
326 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); | |
f078f209 | 327 | |
f1dc5600 | 328 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
f078f209 LR |
329 | } |
330 | ||
1f3f0618 | 331 | /* This should work for all families including legacy */ |
cbe61d8a | 332 | static bool ath9k_hw_chip_test(struct ath_hw *ah) |
f078f209 | 333 | { |
c46917bb | 334 | struct ath_common *common = ath9k_hw_common(ah); |
1f3f0618 | 335 | u32 regAddr[2] = { AR_STA_ID0 }; |
f1dc5600 | 336 | u32 regHold[2]; |
07b2fa5a JP |
337 | static const u32 patternData[4] = { |
338 | 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 | |
339 | }; | |
1f3f0618 | 340 | int i, j, loop_max; |
f078f209 | 341 | |
1f3f0618 SB |
342 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
343 | loop_max = 2; | |
344 | regAddr[1] = AR_PHY_BASE + (8 << 2); | |
345 | } else | |
346 | loop_max = 1; | |
347 | ||
348 | for (i = 0; i < loop_max; i++) { | |
f1dc5600 S |
349 | u32 addr = regAddr[i]; |
350 | u32 wrData, rdData; | |
f078f209 | 351 | |
f1dc5600 S |
352 | regHold[i] = REG_READ(ah, addr); |
353 | for (j = 0; j < 0x100; j++) { | |
354 | wrData = (j << 16) | j; | |
355 | REG_WRITE(ah, addr, wrData); | |
356 | rdData = REG_READ(ah, addr); | |
357 | if (rdData != wrData) { | |
3800276a JP |
358 | ath_err(common, |
359 | "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", | |
360 | addr, wrData, rdData); | |
f1dc5600 S |
361 | return false; |
362 | } | |
363 | } | |
364 | for (j = 0; j < 4; j++) { | |
365 | wrData = patternData[j]; | |
366 | REG_WRITE(ah, addr, wrData); | |
367 | rdData = REG_READ(ah, addr); | |
368 | if (wrData != rdData) { | |
3800276a JP |
369 | ath_err(common, |
370 | "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", | |
371 | addr, wrData, rdData); | |
f1dc5600 S |
372 | return false; |
373 | } | |
f078f209 | 374 | } |
f1dc5600 | 375 | REG_WRITE(ah, regAddr[i], regHold[i]); |
f078f209 | 376 | } |
f1dc5600 | 377 | udelay(100); |
cbe61d8a | 378 | |
f078f209 LR |
379 | return true; |
380 | } | |
381 | ||
b8b0f377 | 382 | static void ath9k_hw_init_config(struct ath_hw *ah) |
f1dc5600 | 383 | { |
f57cf939 SM |
384 | struct ath_common *common = ath9k_hw_common(ah); |
385 | ||
689e756f FF |
386 | ah->config.dma_beacon_response_time = 1; |
387 | ah->config.sw_beacon_response_time = 6; | |
621a5f7a | 388 | ah->config.cwm_ignore_extcca = false; |
2660b81a | 389 | ah->config.analog_shiftreg = 1; |
f078f209 | 390 | |
0ce024cb | 391 | ah->config.rx_intr_mitigation = true; |
6158425b | 392 | |
a64e1a45 SM |
393 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
394 | ah->config.rimt_last = 500; | |
395 | ah->config.rimt_first = 2000; | |
396 | } else { | |
397 | ah->config.rimt_last = 250; | |
398 | ah->config.rimt_first = 700; | |
399 | } | |
400 | ||
656cd75c SM |
401 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) |
402 | ah->config.pll_pwrsave = 7; | |
403 | ||
6158425b LR |
404 | /* |
405 | * We need this for PCI devices only (Cardbus, PCI, miniPCI) | |
406 | * _and_ if on non-uniprocessor systems (Multiprocessor/HT). | |
407 | * This means we use it for all AR5416 devices, and the few | |
408 | * minor PCI AR9280 devices out there. | |
409 | * | |
410 | * Serialization is required because these devices do not handle | |
411 | * well the case of two concurrent reads/writes due to the latency | |
412 | * involved. During one read/write another read/write can be issued | |
413 | * on another CPU while the previous read/write may still be working | |
414 | * on our hardware, if we hit this case the hardware poops in a loop. | |
415 | * We prevent this by serializing reads and writes. | |
416 | * | |
417 | * This issue is not present on PCI-Express devices or pre-AR5416 | |
418 | * devices (legacy, 802.11abg). | |
419 | */ | |
420 | if (num_possible_cpus() > 1) | |
2d6a5e95 | 421 | ah->config.serialize_regmode = SER_REG_MODE_AUTO; |
f57cf939 SM |
422 | |
423 | if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { | |
424 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || | |
425 | ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && | |
426 | !ah->is_pciexpress)) { | |
427 | ah->config.serialize_regmode = SER_REG_MODE_ON; | |
428 | } else { | |
429 | ah->config.serialize_regmode = SER_REG_MODE_OFF; | |
430 | } | |
431 | } | |
432 | ||
433 | ath_dbg(common, RESET, "serialize_regmode is %d\n", | |
434 | ah->config.serialize_regmode); | |
435 | ||
436 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) | |
437 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; | |
438 | else | |
439 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; | |
f078f209 LR |
440 | } |
441 | ||
50aca25b | 442 | static void ath9k_hw_init_defaults(struct ath_hw *ah) |
f078f209 | 443 | { |
608b88cb LR |
444 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
445 | ||
446 | regulatory->country_code = CTRY_DEFAULT; | |
447 | regulatory->power_limit = MAX_RATE_POWER; | |
608b88cb | 448 | |
d535a42a | 449 | ah->hw_version.magic = AR5416_MAGIC; |
d535a42a | 450 | ah->hw_version.subvendorid = 0; |
f078f209 | 451 | |
f57cf939 SM |
452 | ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE | |
453 | AR_STA_ID1_MCAST_KSRCH; | |
f171760c FF |
454 | if (AR_SREV_9100(ah)) |
455 | ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; | |
f57cf939 | 456 | |
e3f2acc7 | 457 | ah->slottime = ATH9K_SLOT_TIME_9; |
2660b81a | 458 | ah->globaltxtimeout = (u32) -1; |
cbdec975 | 459 | ah->power_mode = ATH9K_PM_UNDEFINED; |
8efa7a81 | 460 | ah->htc_reset_init = true; |
f57cf939 | 461 | |
c09396eb | 462 | ah->tpc_enabled = false; |
a9abe302 | 463 | |
f57cf939 SM |
464 | ah->ani_function = ATH9K_ANI_ALL; |
465 | if (!AR_SREV_9300_20_OR_LATER(ah)) | |
466 | ah->ani_function &= ~ATH9K_ANI_MRC_CCK; | |
467 | ||
468 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) | |
469 | ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); | |
470 | else | |
471 | ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); | |
f078f209 LR |
472 | } |
473 | ||
cbe61d8a | 474 | static int ath9k_hw_init_macaddr(struct ath_hw *ah) |
f078f209 | 475 | { |
1510718d | 476 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 LR |
477 | u32 sum; |
478 | int i; | |
479 | u16 eeval; | |
07b2fa5a | 480 | static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; |
f078f209 LR |
481 | |
482 | sum = 0; | |
483 | for (i = 0; i < 3; i++) { | |
49101676 | 484 | eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); |
f078f209 | 485 | sum += eeval; |
1510718d LR |
486 | common->macaddr[2 * i] = eeval >> 8; |
487 | common->macaddr[2 * i + 1] = eeval & 0xff; | |
f078f209 | 488 | } |
5ca06ebe FF |
489 | if (!is_valid_ether_addr(common->macaddr)) { |
490 | ath_err(common, | |
491 | "eeprom contains invalid mac address: %pM\n", | |
492 | common->macaddr); | |
493 | ||
494 | random_ether_addr(common->macaddr); | |
495 | ath_err(common, | |
496 | "random mac address will be used: %pM\n", | |
497 | common->macaddr); | |
498 | } | |
f078f209 LR |
499 | |
500 | return 0; | |
501 | } | |
502 | ||
f637cfd6 | 503 | static int ath9k_hw_post_init(struct ath_hw *ah) |
f078f209 | 504 | { |
6cae913d | 505 | struct ath_common *common = ath9k_hw_common(ah); |
f1dc5600 | 506 | int ecode; |
f078f209 | 507 | |
6cae913d | 508 | if (common->bus_ops->ath_bus_type != ATH_USB) { |
527d485f S |
509 | if (!ath9k_hw_chip_test(ah)) |
510 | return -ENODEV; | |
511 | } | |
f078f209 | 512 | |
ebd5a14a LR |
513 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
514 | ecode = ar9002_hw_rf_claim(ah); | |
515 | if (ecode != 0) | |
516 | return ecode; | |
517 | } | |
f078f209 | 518 | |
f637cfd6 | 519 | ecode = ath9k_hw_eeprom_init(ah); |
f1dc5600 S |
520 | if (ecode != 0) |
521 | return ecode; | |
7d01b221 | 522 | |
d2182b69 | 523 | ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", |
226afe68 JP |
524 | ah->eep_ops->get_eeprom_ver(ah), |
525 | ah->eep_ops->get_eeprom_rev(ah)); | |
7d01b221 | 526 | |
e323300d | 527 | ath9k_hw_ani_init(ah); |
f078f209 | 528 | |
d3b371cb SM |
529 | /* |
530 | * EEPROM needs to be initialized before we do this. | |
531 | * This is required for regulatory compliance. | |
532 | */ | |
0c7c2bb4 | 533 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
d3b371cb SM |
534 | u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); |
535 | if ((regdmn & 0xF0) == CTL_FCC) { | |
0c7c2bb4 SM |
536 | ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ; |
537 | ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ; | |
d3b371cb SM |
538 | } |
539 | } | |
540 | ||
f078f209 LR |
541 | return 0; |
542 | } | |
543 | ||
c1b976d2 | 544 | static int ath9k_hw_attach_ops(struct ath_hw *ah) |
ee2bb460 | 545 | { |
c1b976d2 FF |
546 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
547 | return ar9002_hw_attach_ops(ah); | |
548 | ||
549 | ar9003_hw_attach_ops(ah); | |
550 | return 0; | |
aa4058ae LR |
551 | } |
552 | ||
d70357d5 LR |
553 | /* Called for all hardware families */ |
554 | static int __ath9k_hw_init(struct ath_hw *ah) | |
aa4058ae | 555 | { |
c46917bb | 556 | struct ath_common *common = ath9k_hw_common(ah); |
95fafca2 | 557 | int r = 0; |
aa4058ae | 558 | |
ac45c12d SB |
559 | ath9k_hw_read_revisions(ah); |
560 | ||
de82582b SM |
561 | switch (ah->hw_version.macVersion) { |
562 | case AR_SREV_VERSION_5416_PCI: | |
563 | case AR_SREV_VERSION_5416_PCIE: | |
564 | case AR_SREV_VERSION_9160: | |
565 | case AR_SREV_VERSION_9100: | |
566 | case AR_SREV_VERSION_9280: | |
567 | case AR_SREV_VERSION_9285: | |
568 | case AR_SREV_VERSION_9287: | |
569 | case AR_SREV_VERSION_9271: | |
570 | case AR_SREV_VERSION_9300: | |
571 | case AR_SREV_VERSION_9330: | |
572 | case AR_SREV_VERSION_9485: | |
573 | case AR_SREV_VERSION_9340: | |
574 | case AR_SREV_VERSION_9462: | |
575 | case AR_SREV_VERSION_9550: | |
576 | case AR_SREV_VERSION_9565: | |
e6b1e46e | 577 | case AR_SREV_VERSION_9531: |
2131fabb | 578 | case AR_SREV_VERSION_9561: |
de82582b SM |
579 | break; |
580 | default: | |
581 | ath_err(common, | |
582 | "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", | |
583 | ah->hw_version.macVersion, ah->hw_version.macRev); | |
584 | return -EOPNOTSUPP; | |
585 | } | |
586 | ||
0a8d7cb0 SB |
587 | /* |
588 | * Read back AR_WA into a permanent copy and set bits 14 and 17. | |
589 | * We need to do this to avoid RMW of this register. We cannot | |
590 | * read the reg when chip is asleep. | |
591 | */ | |
27251e00 SM |
592 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
593 | ah->WARegVal = REG_READ(ah, AR_WA); | |
594 | ah->WARegVal |= (AR_WA_D3_L1_DISABLE | | |
595 | AR_WA_ASPM_TIMER_BASED_DISABLE); | |
596 | } | |
0a8d7cb0 | 597 | |
aa4058ae | 598 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { |
3800276a | 599 | ath_err(common, "Couldn't reset chip\n"); |
95fafca2 | 600 | return -EIO; |
aa4058ae LR |
601 | } |
602 | ||
a4a2954f SM |
603 | if (AR_SREV_9565(ah)) { |
604 | ah->WARegVal |= AR_WA_BIT22; | |
605 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
606 | } | |
607 | ||
bab1f62e LR |
608 | ath9k_hw_init_defaults(ah); |
609 | ath9k_hw_init_config(ah); | |
610 | ||
c1b976d2 FF |
611 | r = ath9k_hw_attach_ops(ah); |
612 | if (r) | |
613 | return r; | |
d70357d5 | 614 | |
9ecdef4b | 615 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { |
3800276a | 616 | ath_err(common, "Couldn't wakeup chip\n"); |
95fafca2 | 617 | return -EIO; |
aa4058ae LR |
618 | } |
619 | ||
2c8e5937 | 620 | if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || |
c95b584b | 621 | AR_SREV_9330(ah) || AR_SREV_9550(ah)) |
d7e7d229 LR |
622 | ah->is_pciexpress = false; |
623 | ||
aa4058ae | 624 | ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); |
aa4058ae LR |
625 | ath9k_hw_init_cal_settings(ah); |
626 | ||
69ce674b | 627 | if (!ah->is_pciexpress) |
aa4058ae LR |
628 | ath9k_hw_disablepcie(ah); |
629 | ||
f637cfd6 | 630 | r = ath9k_hw_post_init(ah); |
aa4058ae | 631 | if (r) |
95fafca2 | 632 | return r; |
aa4058ae LR |
633 | |
634 | ath9k_hw_init_mode_gain_regs(ah); | |
a9a29ce6 GJ |
635 | r = ath9k_hw_fill_cap_info(ah); |
636 | if (r) | |
637 | return r; | |
638 | ||
4f3acf81 LR |
639 | r = ath9k_hw_init_macaddr(ah); |
640 | if (r) { | |
3800276a | 641 | ath_err(common, "Failed to initialize MAC address\n"); |
95fafca2 | 642 | return r; |
f078f209 LR |
643 | } |
644 | ||
4598702d | 645 | ath9k_hw_init_hang_checks(ah); |
f078f209 | 646 | |
211f5859 LR |
647 | common->state = ATH_HW_INITIALIZED; |
648 | ||
4f3acf81 | 649 | return 0; |
f078f209 LR |
650 | } |
651 | ||
d70357d5 | 652 | int ath9k_hw_init(struct ath_hw *ah) |
f078f209 | 653 | { |
d70357d5 LR |
654 | int ret; |
655 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 | 656 | |
77fac465 | 657 | /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */ |
d70357d5 LR |
658 | switch (ah->hw_version.devid) { |
659 | case AR5416_DEVID_PCI: | |
660 | case AR5416_DEVID_PCIE: | |
661 | case AR5416_AR9100_DEVID: | |
662 | case AR9160_DEVID_PCI: | |
663 | case AR9280_DEVID_PCI: | |
664 | case AR9280_DEVID_PCIE: | |
665 | case AR9285_DEVID_PCIE: | |
db3cc53a SB |
666 | case AR9287_DEVID_PCI: |
667 | case AR9287_DEVID_PCIE: | |
d70357d5 | 668 | case AR2427_DEVID_PCIE: |
db3cc53a | 669 | case AR9300_DEVID_PCIE: |
3050c914 | 670 | case AR9300_DEVID_AR9485_PCIE: |
999a7a88 | 671 | case AR9300_DEVID_AR9330: |
bca04689 | 672 | case AR9300_DEVID_AR9340: |
2b943a33 | 673 | case AR9300_DEVID_QCA955X: |
5a63ef0f | 674 | case AR9300_DEVID_AR9580: |
423e38e8 | 675 | case AR9300_DEVID_AR9462: |
d4e5979c | 676 | case AR9485_DEVID_AR1111: |
77fac465 | 677 | case AR9300_DEVID_AR9565: |
e6b1e46e | 678 | case AR9300_DEVID_AR953X: |
2131fabb | 679 | case AR9300_DEVID_QCA956X: |
d70357d5 LR |
680 | break; |
681 | default: | |
682 | if (common->bus_ops->ath_bus_type == ATH_USB) | |
683 | break; | |
3800276a JP |
684 | ath_err(common, "Hardware device ID 0x%04x not supported\n", |
685 | ah->hw_version.devid); | |
d70357d5 LR |
686 | return -EOPNOTSUPP; |
687 | } | |
f078f209 | 688 | |
d70357d5 LR |
689 | ret = __ath9k_hw_init(ah); |
690 | if (ret) { | |
3800276a JP |
691 | ath_err(common, |
692 | "Unable to initialize hardware; initialization status: %d\n", | |
693 | ret); | |
d70357d5 LR |
694 | return ret; |
695 | } | |
f078f209 | 696 | |
c774d57f LB |
697 | ath_dynack_init(ah); |
698 | ||
d70357d5 | 699 | return 0; |
f078f209 | 700 | } |
d70357d5 | 701 | EXPORT_SYMBOL(ath9k_hw_init); |
f078f209 | 702 | |
cbe61d8a | 703 | static void ath9k_hw_init_qos(struct ath_hw *ah) |
f078f209 | 704 | { |
7d0d0df0 S |
705 | ENABLE_REGWRITE_BUFFER(ah); |
706 | ||
f1dc5600 S |
707 | REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); |
708 | REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); | |
f078f209 | 709 | |
f1dc5600 S |
710 | REG_WRITE(ah, AR_QOS_NO_ACK, |
711 | SM(2, AR_QOS_NO_ACK_TWO_BIT) | | |
712 | SM(5, AR_QOS_NO_ACK_BIT_OFF) | | |
713 | SM(0, AR_QOS_NO_ACK_BYTE_OFF)); | |
714 | ||
715 | REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); | |
716 | REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); | |
717 | REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); | |
718 | REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); | |
719 | REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); | |
7d0d0df0 S |
720 | |
721 | REGWRITE_BUFFER_FLUSH(ah); | |
f078f209 LR |
722 | } |
723 | ||
b84628eb | 724 | u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) |
b1415819 | 725 | { |
f18e3c6b MSS |
726 | struct ath_common *common = ath9k_hw_common(ah); |
727 | int i = 0; | |
728 | ||
ca7a4deb FF |
729 | REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); |
730 | udelay(100); | |
731 | REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); | |
b1415819 | 732 | |
f18e3c6b MSS |
733 | while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { |
734 | ||
ca7a4deb | 735 | udelay(100); |
b1415819 | 736 | |
f18e3c6b MSS |
737 | if (WARN_ON_ONCE(i >= 100)) { |
738 | ath_err(common, "PLL4 meaurement not done\n"); | |
739 | break; | |
740 | } | |
741 | ||
742 | i++; | |
743 | } | |
744 | ||
ca7a4deb | 745 | return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; |
b1415819 VN |
746 | } |
747 | EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); | |
748 | ||
cbe61d8a | 749 | static void ath9k_hw_init_pll(struct ath_hw *ah, |
f1dc5600 | 750 | struct ath9k_channel *chan) |
f078f209 | 751 | { |
d09b17f7 VT |
752 | u32 pll; |
753 | ||
5fb9b1b9 FF |
754 | pll = ath9k_hw_compute_pll_control(ah, chan); |
755 | ||
a4a2954f | 756 | if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { |
3dfd7f60 VT |
757 | /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ |
758 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | |
759 | AR_CH0_BB_DPLL2_PLL_PWD, 0x1); | |
760 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | |
761 | AR_CH0_DPLL2_KD, 0x40); | |
762 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | |
763 | AR_CH0_DPLL2_KI, 0x4); | |
22983c30 | 764 | |
3dfd7f60 VT |
765 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, |
766 | AR_CH0_BB_DPLL1_REFDIV, 0x5); | |
767 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, | |
768 | AR_CH0_BB_DPLL1_NINI, 0x58); | |
769 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, | |
770 | AR_CH0_BB_DPLL1_NFRAC, 0x0); | |
22983c30 VN |
771 | |
772 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | |
3dfd7f60 VT |
773 | AR_CH0_BB_DPLL2_OUTDIV, 0x1); |
774 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | |
775 | AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); | |
22983c30 | 776 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, |
3dfd7f60 | 777 | AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); |
22983c30 | 778 | |
3dfd7f60 | 779 | /* program BB PLL phase_shift to 0x6 */ |
22983c30 | 780 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, |
3dfd7f60 VT |
781 | AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); |
782 | ||
783 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | |
784 | AR_CH0_BB_DPLL2_PLL_PWD, 0x0); | |
75e03512 | 785 | udelay(1000); |
a5415d62 GJ |
786 | } else if (AR_SREV_9330(ah)) { |
787 | u32 ddr_dpll2, pll_control2, kd; | |
788 | ||
789 | if (ah->is_clk_25mhz) { | |
790 | ddr_dpll2 = 0x18e82f01; | |
791 | pll_control2 = 0xe04a3d; | |
792 | kd = 0x1d; | |
793 | } else { | |
794 | ddr_dpll2 = 0x19e82f01; | |
795 | pll_control2 = 0x886666; | |
796 | kd = 0x3d; | |
797 | } | |
798 | ||
799 | /* program DDR PLL ki and kd value */ | |
800 | REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); | |
801 | ||
802 | /* program DDR PLL phase_shift */ | |
803 | REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, | |
804 | AR_CH0_DPLL3_PHASE_SHIFT, 0x1); | |
805 | ||
5fb9b1b9 FF |
806 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, |
807 | pll | AR_RTC_9300_PLL_BYPASS); | |
a5415d62 GJ |
808 | udelay(1000); |
809 | ||
810 | /* program refdiv, nint, frac to RTC register */ | |
811 | REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); | |
812 | ||
813 | /* program BB PLL kd and ki value */ | |
814 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); | |
815 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); | |
816 | ||
817 | /* program BB PLL phase_shift */ | |
818 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, | |
819 | AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); | |
ede6a5e7 MP |
820 | } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || |
821 | AR_SREV_9561(ah)) { | |
0b488ac6 VT |
822 | u32 regval, pll2_divint, pll2_divfrac, refdiv; |
823 | ||
5fb9b1b9 FF |
824 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, |
825 | pll | AR_RTC_9300_SOC_PLL_BYPASS); | |
0b488ac6 VT |
826 | udelay(1000); |
827 | ||
828 | REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); | |
829 | udelay(100); | |
830 | ||
831 | if (ah->is_clk_25mhz) { | |
ede6a5e7 | 832 | if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { |
2c323058 SM |
833 | pll2_divint = 0x1c; |
834 | pll2_divfrac = 0xa3d2; | |
835 | refdiv = 1; | |
836 | } else { | |
837 | pll2_divint = 0x54; | |
838 | pll2_divfrac = 0x1eb85; | |
839 | refdiv = 3; | |
840 | } | |
0b488ac6 | 841 | } else { |
fc05a317 GJ |
842 | if (AR_SREV_9340(ah)) { |
843 | pll2_divint = 88; | |
844 | pll2_divfrac = 0; | |
845 | refdiv = 5; | |
846 | } else { | |
847 | pll2_divint = 0x11; | |
ede6a5e7 MP |
848 | pll2_divfrac = (AR_SREV_9531(ah) || |
849 | AR_SREV_9561(ah)) ? | |
850 | 0x26665 : 0x26666; | |
fc05a317 GJ |
851 | refdiv = 1; |
852 | } | |
0b488ac6 VT |
853 | } |
854 | ||
855 | regval = REG_READ(ah, AR_PHY_PLL_MODE); | |
ede6a5e7 | 856 | if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) |
2c323058 SM |
857 | regval |= (0x1 << 22); |
858 | else | |
859 | regval |= (0x1 << 16); | |
0b488ac6 VT |
860 | REG_WRITE(ah, AR_PHY_PLL_MODE, regval); |
861 | udelay(100); | |
862 | ||
863 | REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | | |
864 | (pll2_divint << 18) | pll2_divfrac); | |
865 | udelay(100); | |
866 | ||
867 | regval = REG_READ(ah, AR_PHY_PLL_MODE); | |
fc05a317 | 868 | if (AR_SREV_9340(ah)) |
2c323058 SM |
869 | regval = (regval & 0x80071fff) | |
870 | (0x1 << 30) | | |
871 | (0x1 << 13) | | |
872 | (0x4 << 26) | | |
873 | (0x18 << 19); | |
ede6a5e7 | 874 | else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { |
2c323058 SM |
875 | regval = (regval & 0x01c00fff) | |
876 | (0x1 << 31) | | |
877 | (0x2 << 29) | | |
878 | (0xa << 25) | | |
ede6a5e7 MP |
879 | (0x1 << 19); |
880 | ||
881 | if (AR_SREV_9531(ah)) | |
882 | regval |= (0x6 << 12); | |
883 | } else | |
2c323058 SM |
884 | regval = (regval & 0x80071fff) | |
885 | (0x3 << 30) | | |
886 | (0x1 << 13) | | |
887 | (0x4 << 26) | | |
888 | (0x60 << 19); | |
0b488ac6 | 889 | REG_WRITE(ah, AR_PHY_PLL_MODE, regval); |
2c323058 | 890 | |
ede6a5e7 | 891 | if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) |
2c323058 SM |
892 | REG_WRITE(ah, AR_PHY_PLL_MODE, |
893 | REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); | |
894 | else | |
895 | REG_WRITE(ah, AR_PHY_PLL_MODE, | |
896 | REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); | |
897 | ||
0b488ac6 | 898 | udelay(1000); |
22983c30 | 899 | } |
d09b17f7 | 900 | |
8565f8bf SM |
901 | if (AR_SREV_9565(ah)) |
902 | pll |= 0x40000; | |
d03a66c1 | 903 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); |
f078f209 | 904 | |
fc05a317 GJ |
905 | if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || |
906 | AR_SREV_9550(ah)) | |
3dfd7f60 VT |
907 | udelay(1000); |
908 | ||
c75724d1 LR |
909 | /* Switch the core clock for ar9271 to 117Mhz */ |
910 | if (AR_SREV_9271(ah)) { | |
25e2ab17 S |
911 | udelay(500); |
912 | REG_WRITE(ah, 0x50040, 0x304); | |
c75724d1 LR |
913 | } |
914 | ||
f1dc5600 S |
915 | udelay(RTC_PLL_SETTLE_DELAY); |
916 | ||
917 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); | |
f078f209 LR |
918 | } |
919 | ||
cbe61d8a | 920 | static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, |
d97809db | 921 | enum nl80211_iftype opmode) |
f078f209 | 922 | { |
79d1d2b8 | 923 | u32 sync_default = AR_INTR_SYNC_DEFAULT; |
152d530d | 924 | u32 imr_reg = AR_IMR_TXERR | |
f1dc5600 S |
925 | AR_IMR_TXURN | |
926 | AR_IMR_RXERR | | |
927 | AR_IMR_RXORN | | |
928 | AR_IMR_BCNMISC; | |
f078f209 | 929 | |
ede6a5e7 MP |
930 | if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || |
931 | AR_SREV_9561(ah)) | |
79d1d2b8 VT |
932 | sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; |
933 | ||
66860240 VT |
934 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
935 | imr_reg |= AR_IMR_RXOK_HP; | |
936 | if (ah->config.rx_intr_mitigation) | |
937 | imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; | |
938 | else | |
939 | imr_reg |= AR_IMR_RXOK_LP; | |
f078f209 | 940 | |
66860240 VT |
941 | } else { |
942 | if (ah->config.rx_intr_mitigation) | |
943 | imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; | |
944 | else | |
945 | imr_reg |= AR_IMR_RXOK; | |
946 | } | |
f078f209 | 947 | |
66860240 VT |
948 | if (ah->config.tx_intr_mitigation) |
949 | imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; | |
950 | else | |
951 | imr_reg |= AR_IMR_TXOK; | |
f078f209 | 952 | |
7d0d0df0 S |
953 | ENABLE_REGWRITE_BUFFER(ah); |
954 | ||
152d530d | 955 | REG_WRITE(ah, AR_IMR, imr_reg); |
74bad5cb PR |
956 | ah->imrs2_reg |= AR_IMR_S2_GTT; |
957 | REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); | |
f078f209 | 958 | |
f1dc5600 S |
959 | if (!AR_SREV_9100(ah)) { |
960 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); | |
79d1d2b8 | 961 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); |
f1dc5600 S |
962 | REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); |
963 | } | |
66860240 | 964 | |
7d0d0df0 | 965 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 966 | |
66860240 VT |
967 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
968 | REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); | |
969 | REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); | |
970 | REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); | |
971 | REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); | |
972 | } | |
f078f209 LR |
973 | } |
974 | ||
b6ba41bb FF |
975 | static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) |
976 | { | |
977 | u32 val = ath9k_hw_mac_to_clks(ah, us - 2); | |
978 | val = min(val, (u32) 0xFFFF); | |
979 | REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); | |
980 | } | |
981 | ||
8e15e094 | 982 | void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) |
f078f209 | 983 | { |
0005baf4 FF |
984 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
985 | val = min(val, (u32) 0xFFFF); | |
986 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); | |
f078f209 LR |
987 | } |
988 | ||
8e15e094 | 989 | void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) |
f078f209 | 990 | { |
0005baf4 FF |
991 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
992 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); | |
993 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); | |
994 | } | |
995 | ||
8e15e094 | 996 | void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) |
0005baf4 FF |
997 | { |
998 | u32 val = ath9k_hw_mac_to_clks(ah, us); | |
999 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); | |
1000 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); | |
f078f209 | 1001 | } |
f1dc5600 | 1002 | |
cbe61d8a | 1003 | static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) |
f078f209 | 1004 | { |
f078f209 | 1005 | if (tu > 0xFFFF) { |
d2182b69 JP |
1006 | ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", |
1007 | tu); | |
2660b81a | 1008 | ah->globaltxtimeout = (u32) -1; |
f078f209 LR |
1009 | return false; |
1010 | } else { | |
1011 | REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); | |
2660b81a | 1012 | ah->globaltxtimeout = tu; |
f078f209 LR |
1013 | return true; |
1014 | } | |
1015 | } | |
1016 | ||
0005baf4 | 1017 | void ath9k_hw_init_global_settings(struct ath_hw *ah) |
f078f209 | 1018 | { |
b6ba41bb | 1019 | struct ath_common *common = ath9k_hw_common(ah); |
b6ba41bb | 1020 | const struct ath9k_channel *chan = ah->curchan; |
e115b7ec | 1021 | int acktimeout, ctstimeout, ack_offset = 0; |
e239d859 | 1022 | int slottime; |
0005baf4 | 1023 | int sifstime; |
b6ba41bb FF |
1024 | int rx_lat = 0, tx_lat = 0, eifs = 0; |
1025 | u32 reg; | |
0005baf4 | 1026 | |
d2182b69 | 1027 | ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", |
226afe68 | 1028 | ah->misc_mode); |
f078f209 | 1029 | |
b6ba41bb FF |
1030 | if (!chan) |
1031 | return; | |
1032 | ||
2660b81a | 1033 | if (ah->misc_mode != 0) |
ca7a4deb | 1034 | REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); |
0005baf4 | 1035 | |
81a91d57 RM |
1036 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) |
1037 | rx_lat = 41; | |
1038 | else | |
1039 | rx_lat = 37; | |
b6ba41bb FF |
1040 | tx_lat = 54; |
1041 | ||
e88e4861 FF |
1042 | if (IS_CHAN_5GHZ(chan)) |
1043 | sifstime = 16; | |
1044 | else | |
1045 | sifstime = 10; | |
1046 | ||
b6ba41bb FF |
1047 | if (IS_CHAN_HALF_RATE(chan)) { |
1048 | eifs = 175; | |
1049 | rx_lat *= 2; | |
1050 | tx_lat *= 2; | |
1051 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) | |
1052 | tx_lat += 11; | |
1053 | ||
92367fe7 | 1054 | sifstime = 32; |
e115b7ec | 1055 | ack_offset = 16; |
b6ba41bb | 1056 | slottime = 13; |
b6ba41bb FF |
1057 | } else if (IS_CHAN_QUARTER_RATE(chan)) { |
1058 | eifs = 340; | |
81a91d57 | 1059 | rx_lat = (rx_lat * 4) - 1; |
b6ba41bb FF |
1060 | tx_lat *= 4; |
1061 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) | |
1062 | tx_lat += 22; | |
1063 | ||
92367fe7 | 1064 | sifstime = 64; |
e115b7ec | 1065 | ack_offset = 32; |
b6ba41bb | 1066 | slottime = 21; |
b6ba41bb | 1067 | } else { |
a7be039d RM |
1068 | if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { |
1069 | eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; | |
1070 | reg = AR_USEC_ASYNC_FIFO; | |
1071 | } else { | |
1072 | eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ | |
1073 | common->clockrate; | |
1074 | reg = REG_READ(ah, AR_USEC); | |
1075 | } | |
b6ba41bb FF |
1076 | rx_lat = MS(reg, AR_USEC_RX_LAT); |
1077 | tx_lat = MS(reg, AR_USEC_TX_LAT); | |
1078 | ||
1079 | slottime = ah->slottime; | |
b6ba41bb | 1080 | } |
0005baf4 | 1081 | |
e239d859 | 1082 | /* As defined by IEEE 802.11-2007 17.3.8.6 */ |
f77f8234 MK |
1083 | slottime += 3 * ah->coverage_class; |
1084 | acktimeout = slottime + sifstime + ack_offset; | |
adb5066a | 1085 | ctstimeout = acktimeout; |
42c4568a FF |
1086 | |
1087 | /* | |
1088 | * Workaround for early ACK timeouts, add an offset to match the | |
55a2bb4a | 1089 | * initval's 64us ack timeout value. Use 48us for the CTS timeout. |
42c4568a FF |
1090 | * This was initially only meant to work around an issue with delayed |
1091 | * BA frames in some implementations, but it has been found to fix ACK | |
1092 | * timeout issues in other cases as well. | |
1093 | */ | |
e4744ec7 | 1094 | if (IS_CHAN_2GHZ(chan) && |
e115b7ec | 1095 | !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) { |
42c4568a | 1096 | acktimeout += 64 - sifstime - ah->slottime; |
55a2bb4a FF |
1097 | ctstimeout += 48 - sifstime - ah->slottime; |
1098 | } | |
1099 | ||
7aefa8aa LB |
1100 | if (ah->dynack.enabled) { |
1101 | acktimeout = ah->dynack.ackto; | |
1102 | ctstimeout = acktimeout; | |
1103 | slottime = (acktimeout - 3) / 2; | |
1104 | } else { | |
1105 | ah->dynack.ackto = acktimeout; | |
1106 | } | |
1107 | ||
b6ba41bb FF |
1108 | ath9k_hw_set_sifs_time(ah, sifstime); |
1109 | ath9k_hw_setslottime(ah, slottime); | |
0005baf4 | 1110 | ath9k_hw_set_ack_timeout(ah, acktimeout); |
adb5066a | 1111 | ath9k_hw_set_cts_timeout(ah, ctstimeout); |
2660b81a S |
1112 | if (ah->globaltxtimeout != (u32) -1) |
1113 | ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); | |
b6ba41bb FF |
1114 | |
1115 | REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); | |
1116 | REG_RMW(ah, AR_USEC, | |
1117 | (common->clockrate - 1) | | |
1118 | SM(rx_lat, AR_USEC_RX_LAT) | | |
1119 | SM(tx_lat, AR_USEC_TX_LAT), | |
1120 | AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); | |
1121 | ||
f1dc5600 | 1122 | } |
0005baf4 | 1123 | EXPORT_SYMBOL(ath9k_hw_init_global_settings); |
f1dc5600 | 1124 | |
285f2dda | 1125 | void ath9k_hw_deinit(struct ath_hw *ah) |
f1dc5600 | 1126 | { |
211f5859 LR |
1127 | struct ath_common *common = ath9k_hw_common(ah); |
1128 | ||
736b3a27 | 1129 | if (common->state < ATH_HW_INITIALIZED) |
c1b976d2 | 1130 | return; |
211f5859 | 1131 | |
9ecdef4b | 1132 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); |
f1dc5600 | 1133 | } |
285f2dda | 1134 | EXPORT_SYMBOL(ath9k_hw_deinit); |
f1dc5600 | 1135 | |
f1dc5600 S |
1136 | /*******/ |
1137 | /* INI */ | |
1138 | /*******/ | |
1139 | ||
8fe65368 | 1140 | u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) |
3a702e49 BC |
1141 | { |
1142 | u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); | |
1143 | ||
6b21fd20 | 1144 | if (IS_CHAN_2GHZ(chan)) |
3a702e49 BC |
1145 | ctl |= CTL_11G; |
1146 | else | |
1147 | ctl |= CTL_11A; | |
1148 | ||
1149 | return ctl; | |
1150 | } | |
1151 | ||
f1dc5600 S |
1152 | /****************************************/ |
1153 | /* Reset and Channel Switching Routines */ | |
1154 | /****************************************/ | |
f1dc5600 | 1155 | |
cbe61d8a | 1156 | static inline void ath9k_hw_set_dma(struct ath_hw *ah) |
f1dc5600 | 1157 | { |
57b32227 | 1158 | struct ath_common *common = ath9k_hw_common(ah); |
86c157b3 | 1159 | int txbuf_size; |
f1dc5600 | 1160 | |
7d0d0df0 S |
1161 | ENABLE_REGWRITE_BUFFER(ah); |
1162 | ||
d7e7d229 LR |
1163 | /* |
1164 | * set AHB_MODE not to do cacheline prefetches | |
1165 | */ | |
ca7a4deb FF |
1166 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
1167 | REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); | |
f1dc5600 | 1168 | |
d7e7d229 LR |
1169 | /* |
1170 | * let mac dma reads be in 128 byte chunks | |
1171 | */ | |
ca7a4deb | 1172 | REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); |
f1dc5600 | 1173 | |
7d0d0df0 | 1174 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1175 | |
d7e7d229 LR |
1176 | /* |
1177 | * Restore TX Trigger Level to its pre-reset value. | |
1178 | * The initial value depends on whether aggregation is enabled, and is | |
1179 | * adjusted whenever underruns are detected. | |
1180 | */ | |
57b32227 FF |
1181 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
1182 | REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); | |
f1dc5600 | 1183 | |
7d0d0df0 | 1184 | ENABLE_REGWRITE_BUFFER(ah); |
f1dc5600 | 1185 | |
d7e7d229 LR |
1186 | /* |
1187 | * let mac dma writes be in 128 byte chunks | |
1188 | */ | |
ca7a4deb | 1189 | REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); |
f1dc5600 | 1190 | |
d7e7d229 LR |
1191 | /* |
1192 | * Setup receive FIFO threshold to hold off TX activities | |
1193 | */ | |
f1dc5600 S |
1194 | REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); |
1195 | ||
57b32227 FF |
1196 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
1197 | REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); | |
1198 | REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); | |
1199 | ||
1200 | ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - | |
1201 | ah->caps.rx_status_len); | |
1202 | } | |
1203 | ||
d7e7d229 LR |
1204 | /* |
1205 | * reduce the number of usable entries in PCU TXBUF to avoid | |
1206 | * wrap around issues. | |
1207 | */ | |
f1dc5600 | 1208 | if (AR_SREV_9285(ah)) { |
d7e7d229 LR |
1209 | /* For AR9285 the number of Fifos are reduced to half. |
1210 | * So set the usable tx buf size also to half to | |
1211 | * avoid data/delimiter underruns | |
1212 | */ | |
86c157b3 FF |
1213 | txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE; |
1214 | } else if (AR_SREV_9340_13_OR_LATER(ah)) { | |
1215 | /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */ | |
1216 | txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE; | |
1217 | } else { | |
1218 | txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE; | |
f1dc5600 | 1219 | } |
744d4025 | 1220 | |
86c157b3 FF |
1221 | if (!AR_SREV_9271(ah)) |
1222 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); | |
1223 | ||
7d0d0df0 | 1224 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1225 | |
744d4025 VT |
1226 | if (AR_SREV_9300_20_OR_LATER(ah)) |
1227 | ath9k_hw_reset_txstatus_ring(ah); | |
f1dc5600 S |
1228 | } |
1229 | ||
cbe61d8a | 1230 | static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) |
f1dc5600 | 1231 | { |
ca7a4deb FF |
1232 | u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; |
1233 | u32 set = AR_STA_ID1_KSRCH_MODE; | |
f1dc5600 | 1234 | |
7b37e0d4 | 1235 | ENABLE_REG_RMW_BUFFER(ah); |
f1dc5600 | 1236 | switch (opmode) { |
d97809db | 1237 | case NL80211_IFTYPE_ADHOC: |
83322eb8 FF |
1238 | if (!AR_SREV_9340_13(ah)) { |
1239 | set |= AR_STA_ID1_ADHOC; | |
1240 | REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); | |
1241 | break; | |
1242 | } | |
1243 | /* fall through */ | |
862a336c | 1244 | case NL80211_IFTYPE_OCB: |
2664d666 | 1245 | case NL80211_IFTYPE_MESH_POINT: |
ca7a4deb FF |
1246 | case NL80211_IFTYPE_AP: |
1247 | set |= AR_STA_ID1_STA_AP; | |
1248 | /* fall through */ | |
d97809db | 1249 | case NL80211_IFTYPE_STATION: |
ca7a4deb | 1250 | REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); |
f078f209 | 1251 | break; |
5f841b41 | 1252 | default: |
ca7a4deb FF |
1253 | if (!ah->is_monitoring) |
1254 | set = 0; | |
5f841b41 | 1255 | break; |
f1dc5600 | 1256 | } |
ca7a4deb | 1257 | REG_RMW(ah, AR_STA_ID1, set, mask); |
7b37e0d4 | 1258 | REG_RMW_BUFFER_FLUSH(ah); |
f1dc5600 S |
1259 | } |
1260 | ||
8fe65368 LR |
1261 | void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, |
1262 | u32 *coef_mantissa, u32 *coef_exponent) | |
f1dc5600 S |
1263 | { |
1264 | u32 coef_exp, coef_man; | |
1265 | ||
1266 | for (coef_exp = 31; coef_exp > 0; coef_exp--) | |
1267 | if ((coef_scaled >> coef_exp) & 0x1) | |
1268 | break; | |
1269 | ||
1270 | coef_exp = 14 - (coef_exp - COEF_SCALE_S); | |
1271 | ||
1272 | coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); | |
1273 | ||
1274 | *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); | |
1275 | *coef_exponent = coef_exp - 16; | |
1276 | } | |
1277 | ||
d7df7a55 SM |
1278 | /* AR9330 WAR: |
1279 | * call external reset function to reset WMAC if: | |
1280 | * - doing a cold reset | |
1281 | * - we have pending frames in the TX queues. | |
1282 | */ | |
1283 | static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type) | |
1284 | { | |
1285 | int i, npend = 0; | |
1286 | ||
1287 | for (i = 0; i < AR_NUM_QCU; i++) { | |
1288 | npend = ath9k_hw_numtxpending(ah, i); | |
1289 | if (npend) | |
1290 | break; | |
1291 | } | |
1292 | ||
1293 | if (ah->external_reset && | |
1294 | (npend || type == ATH9K_RESET_COLD)) { | |
1295 | int reset_err = 0; | |
1296 | ||
1297 | ath_dbg(ath9k_hw_common(ah), RESET, | |
1298 | "reset MAC via external reset\n"); | |
1299 | ||
1300 | reset_err = ah->external_reset(); | |
1301 | if (reset_err) { | |
1302 | ath_err(ath9k_hw_common(ah), | |
1303 | "External reset failed, err=%d\n", | |
1304 | reset_err); | |
1305 | return false; | |
1306 | } | |
1307 | ||
1308 | REG_WRITE(ah, AR_RTC_RESET, 1); | |
1309 | } | |
1310 | ||
1311 | return true; | |
1312 | } | |
1313 | ||
cbe61d8a | 1314 | static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) |
f1dc5600 S |
1315 | { |
1316 | u32 rst_flags; | |
1317 | u32 tmpReg; | |
1318 | ||
70768496 | 1319 | if (AR_SREV_9100(ah)) { |
ca7a4deb FF |
1320 | REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, |
1321 | AR_RTC_DERIVED_CLK_PERIOD, 1); | |
70768496 S |
1322 | (void)REG_READ(ah, AR_RTC_DERIVED_CLK); |
1323 | } | |
1324 | ||
7d0d0df0 S |
1325 | ENABLE_REGWRITE_BUFFER(ah); |
1326 | ||
9a658d2b LR |
1327 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
1328 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
1329 | udelay(10); | |
1330 | } | |
1331 | ||
f1dc5600 S |
1332 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
1333 | AR_RTC_FORCE_WAKE_ON_INT); | |
1334 | ||
1335 | if (AR_SREV_9100(ah)) { | |
1336 | rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | | |
1337 | AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; | |
1338 | } else { | |
1339 | tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); | |
a37a9910 FF |
1340 | if (AR_SREV_9340(ah)) |
1341 | tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT; | |
1342 | else | |
1343 | tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT | | |
1344 | AR_INTR_SYNC_RADM_CPL_TIMEOUT; | |
1345 | ||
1346 | if (tmpReg) { | |
42d5bc3f | 1347 | u32 val; |
f1dc5600 | 1348 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); |
42d5bc3f LR |
1349 | |
1350 | val = AR_RC_HOSTIF; | |
1351 | if (!AR_SREV_9300_20_OR_LATER(ah)) | |
1352 | val |= AR_RC_AHB; | |
1353 | REG_WRITE(ah, AR_RC, val); | |
1354 | ||
1355 | } else if (!AR_SREV_9300_20_OR_LATER(ah)) | |
f1dc5600 | 1356 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
f1dc5600 S |
1357 | |
1358 | rst_flags = AR_RTC_RC_MAC_WARM; | |
1359 | if (type == ATH9K_RESET_COLD) | |
1360 | rst_flags |= AR_RTC_RC_MAC_COLD; | |
1361 | } | |
1362 | ||
7d95847c | 1363 | if (AR_SREV_9330(ah)) { |
d7df7a55 SM |
1364 | if (!ath9k_hw_ar9330_reset_war(ah, type)) |
1365 | return false; | |
7d95847c GJ |
1366 | } |
1367 | ||
3863495b | 1368 | if (ath9k_hw_mci_is_enabled(ah)) |
506847ad | 1369 | ar9003_mci_check_gpm_offset(ah); |
3863495b | 1370 | |
466b0f02 MP |
1371 | /* DMA HALT added to resolve ar9300 and ar9580 bus error during |
1372 | * RTC_RC reg read | |
1373 | */ | |
1374 | if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) { | |
1375 | REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); | |
1376 | ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK, | |
1377 | 20 * AH_WAIT_TIMEOUT); | |
1378 | REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ); | |
1379 | } | |
1380 | ||
d03a66c1 | 1381 | REG_WRITE(ah, AR_RTC_RC, rst_flags); |
7d0d0df0 S |
1382 | |
1383 | REGWRITE_BUFFER_FLUSH(ah); | |
7d0d0df0 | 1384 | |
4dc78c43 SM |
1385 | if (AR_SREV_9300_20_OR_LATER(ah)) |
1386 | udelay(50); | |
1387 | else if (AR_SREV_9100(ah)) | |
3683a07b | 1388 | mdelay(10); |
4dc78c43 SM |
1389 | else |
1390 | udelay(100); | |
f1dc5600 | 1391 | |
d03a66c1 | 1392 | REG_WRITE(ah, AR_RTC_RC, 0); |
0caa7b14 | 1393 | if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { |
d2182b69 | 1394 | ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); |
f1dc5600 S |
1395 | return false; |
1396 | } | |
1397 | ||
1398 | if (!AR_SREV_9100(ah)) | |
1399 | REG_WRITE(ah, AR_RC, 0); | |
1400 | ||
f1dc5600 S |
1401 | if (AR_SREV_9100(ah)) |
1402 | udelay(50); | |
1403 | ||
1404 | return true; | |
1405 | } | |
1406 | ||
cbe61d8a | 1407 | static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) |
f1dc5600 | 1408 | { |
7d0d0df0 S |
1409 | ENABLE_REGWRITE_BUFFER(ah); |
1410 | ||
9a658d2b LR |
1411 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
1412 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
1413 | udelay(10); | |
1414 | } | |
1415 | ||
f1dc5600 S |
1416 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
1417 | AR_RTC_FORCE_WAKE_ON_INT); | |
1418 | ||
42d5bc3f | 1419 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
1c29ce67 VT |
1420 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
1421 | ||
d03a66c1 | 1422 | REG_WRITE(ah, AR_RTC_RESET, 0); |
1c29ce67 | 1423 | |
7d0d0df0 | 1424 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1425 | |
afe36533 | 1426 | udelay(2); |
84e2169b SB |
1427 | |
1428 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) | |
1c29ce67 VT |
1429 | REG_WRITE(ah, AR_RC, 0); |
1430 | ||
d03a66c1 | 1431 | REG_WRITE(ah, AR_RTC_RESET, 1); |
f1dc5600 S |
1432 | |
1433 | if (!ath9k_hw_wait(ah, | |
1434 | AR_RTC_STATUS, | |
1435 | AR_RTC_STATUS_M, | |
0caa7b14 S |
1436 | AR_RTC_STATUS_ON, |
1437 | AH_WAIT_TIMEOUT)) { | |
d2182b69 | 1438 | ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); |
f1dc5600 | 1439 | return false; |
f078f209 LR |
1440 | } |
1441 | ||
f1dc5600 S |
1442 | return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); |
1443 | } | |
1444 | ||
cbe61d8a | 1445 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) |
f1dc5600 | 1446 | { |
7a9233ff | 1447 | bool ret = false; |
2577c6e8 | 1448 | |
9a658d2b LR |
1449 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
1450 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
1451 | udelay(10); | |
1452 | } | |
1453 | ||
f1dc5600 S |
1454 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
1455 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); | |
1456 | ||
ceb26a60 FF |
1457 | if (!ah->reset_power_on) |
1458 | type = ATH9K_RESET_POWER_ON; | |
1459 | ||
f1dc5600 S |
1460 | switch (type) { |
1461 | case ATH9K_RESET_POWER_ON: | |
7a9233ff | 1462 | ret = ath9k_hw_set_reset_power_on(ah); |
da8fb123 | 1463 | if (ret) |
ceb26a60 | 1464 | ah->reset_power_on = true; |
7a9233ff | 1465 | break; |
f1dc5600 S |
1466 | case ATH9K_RESET_WARM: |
1467 | case ATH9K_RESET_COLD: | |
7a9233ff MSS |
1468 | ret = ath9k_hw_set_reset(ah, type); |
1469 | break; | |
f1dc5600 | 1470 | default: |
7a9233ff | 1471 | break; |
f1dc5600 | 1472 | } |
7a9233ff | 1473 | |
7a9233ff | 1474 | return ret; |
f078f209 LR |
1475 | } |
1476 | ||
cbe61d8a | 1477 | static bool ath9k_hw_chip_reset(struct ath_hw *ah, |
f1dc5600 | 1478 | struct ath9k_channel *chan) |
f078f209 | 1479 | { |
9c083af8 FF |
1480 | int reset_type = ATH9K_RESET_WARM; |
1481 | ||
1482 | if (AR_SREV_9280(ah)) { | |
1483 | if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) | |
1484 | reset_type = ATH9K_RESET_POWER_ON; | |
1485 | else | |
1486 | reset_type = ATH9K_RESET_COLD; | |
3412f2f0 FF |
1487 | } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || |
1488 | (REG_READ(ah, AR_CR) & AR_CR_RXE)) | |
1489 | reset_type = ATH9K_RESET_COLD; | |
9c083af8 FF |
1490 | |
1491 | if (!ath9k_hw_set_reset_reg(ah, reset_type)) | |
f1dc5600 | 1492 | return false; |
f078f209 | 1493 | |
9ecdef4b | 1494 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
f1dc5600 | 1495 | return false; |
f078f209 | 1496 | |
2660b81a | 1497 | ah->chip_fullsleep = false; |
bfc441a4 FF |
1498 | |
1499 | if (AR_SREV_9330(ah)) | |
1500 | ar9003_hw_internal_regulator_apply(ah); | |
f1dc5600 | 1501 | ath9k_hw_init_pll(ah, chan); |
f078f209 | 1502 | |
f1dc5600 | 1503 | return true; |
f078f209 LR |
1504 | } |
1505 | ||
cbe61d8a | 1506 | static bool ath9k_hw_channel_change(struct ath_hw *ah, |
25c56eec | 1507 | struct ath9k_channel *chan) |
f078f209 | 1508 | { |
c46917bb | 1509 | struct ath_common *common = ath9k_hw_common(ah); |
b840cffe SM |
1510 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
1511 | bool band_switch = false, mode_diff = false; | |
70e89a71 | 1512 | u8 ini_reloaded = 0; |
8fe65368 | 1513 | u32 qnum; |
0a3b7bac | 1514 | int r; |
5f0c04ea | 1515 | |
b840cffe | 1516 | if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) { |
af02efb3 FF |
1517 | u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; |
1518 | band_switch = !!(flags_diff & CHANNEL_5GHZ); | |
1519 | mode_diff = !!(flags_diff & ~CHANNEL_HT); | |
b840cffe | 1520 | } |
f078f209 LR |
1521 | |
1522 | for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { | |
1523 | if (ath9k_hw_numtxpending(ah, qnum)) { | |
d2182b69 | 1524 | ath_dbg(common, QUEUE, |
226afe68 | 1525 | "Transmit frames pending on queue %d\n", qnum); |
f078f209 LR |
1526 | return false; |
1527 | } | |
1528 | } | |
1529 | ||
8fe65368 | 1530 | if (!ath9k_hw_rfbus_req(ah)) { |
3800276a | 1531 | ath_err(common, "Could not kill baseband RX\n"); |
f078f209 LR |
1532 | return false; |
1533 | } | |
1534 | ||
b840cffe | 1535 | if (band_switch || mode_diff) { |
5f0c04ea RM |
1536 | ath9k_hw_mark_phy_inactive(ah); |
1537 | udelay(5); | |
1538 | ||
5f35c0fa SM |
1539 | if (band_switch) |
1540 | ath9k_hw_init_pll(ah, chan); | |
5f0c04ea RM |
1541 | |
1542 | if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { | |
1543 | ath_err(common, "Failed to do fast channel change\n"); | |
1544 | return false; | |
1545 | } | |
1546 | } | |
1547 | ||
8fe65368 | 1548 | ath9k_hw_set_channel_regs(ah, chan); |
f078f209 | 1549 | |
8fe65368 | 1550 | r = ath9k_hw_rf_set_freq(ah, chan); |
0a3b7bac | 1551 | if (r) { |
3800276a | 1552 | ath_err(common, "Failed to set channel\n"); |
0a3b7bac | 1553 | return false; |
f078f209 | 1554 | } |
dfdac8ac | 1555 | ath9k_hw_set_clockrate(ah); |
64ea57d0 | 1556 | ath9k_hw_apply_txpower(ah, chan, false); |
f078f209 | 1557 | |
81c507a8 | 1558 | ath9k_hw_set_delta_slope(ah, chan); |
8fe65368 | 1559 | ath9k_hw_spur_mitigate_freq(ah, chan); |
f1dc5600 | 1560 | |
70e89a71 SM |
1561 | if (band_switch || ini_reloaded) |
1562 | ah->eep_ops->set_board_values(ah, chan); | |
5f0c04ea | 1563 | |
70e89a71 SM |
1564 | ath9k_hw_init_bb(ah, chan); |
1565 | ath9k_hw_rfbus_done(ah); | |
5f0c04ea | 1566 | |
70e89a71 SM |
1567 | if (band_switch || ini_reloaded) { |
1568 | ah->ah_flags |= AH_FASTCC; | |
1569 | ath9k_hw_init_cal(ah, chan); | |
a126ff51 | 1570 | ah->ah_flags &= ~AH_FASTCC; |
5f0c04ea RM |
1571 | } |
1572 | ||
f1dc5600 S |
1573 | return true; |
1574 | } | |
1575 | ||
691680b8 FF |
1576 | static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) |
1577 | { | |
1578 | u32 gpio_mask = ah->gpio_mask; | |
1579 | int i; | |
1580 | ||
1581 | for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { | |
1582 | if (!(gpio_mask & 1)) | |
1583 | continue; | |
1584 | ||
b2d70d49 MP |
1585 | ath9k_hw_gpio_request_out(ah, i, NULL, |
1586 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
691680b8 FF |
1587 | ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); |
1588 | } | |
1589 | } | |
1590 | ||
1e516ca7 SM |
1591 | void ath9k_hw_check_nav(struct ath_hw *ah) |
1592 | { | |
1593 | struct ath_common *common = ath9k_hw_common(ah); | |
1594 | u32 val; | |
1595 | ||
1596 | val = REG_READ(ah, AR_NAV); | |
1597 | if (val != 0xdeadbeef && val > 0x7fff) { | |
1598 | ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val); | |
1599 | REG_WRITE(ah, AR_NAV, 0); | |
1600 | } | |
1601 | } | |
1602 | EXPORT_SYMBOL(ath9k_hw_check_nav); | |
1603 | ||
c9c99e5e | 1604 | bool ath9k_hw_check_alive(struct ath_hw *ah) |
3b319aae | 1605 | { |
c9c99e5e | 1606 | int count = 50; |
d31a36a6 | 1607 | u32 reg, last_val; |
c9c99e5e | 1608 | |
01e18918 RM |
1609 | if (AR_SREV_9300(ah)) |
1610 | return !ath9k_hw_detect_mac_hang(ah); | |
1611 | ||
e17f83ea | 1612 | if (AR_SREV_9285_12_OR_LATER(ah)) |
c9c99e5e FF |
1613 | return true; |
1614 | ||
d31a36a6 | 1615 | last_val = REG_READ(ah, AR_OBS_BUS_1); |
c9c99e5e FF |
1616 | do { |
1617 | reg = REG_READ(ah, AR_OBS_BUS_1); | |
d31a36a6 FF |
1618 | if (reg != last_val) |
1619 | return true; | |
3b319aae | 1620 | |
105ff411 | 1621 | udelay(1); |
d31a36a6 | 1622 | last_val = reg; |
c9c99e5e FF |
1623 | if ((reg & 0x7E7FFFEF) == 0x00702400) |
1624 | continue; | |
1625 | ||
1626 | switch (reg & 0x7E000B00) { | |
1627 | case 0x1E000000: | |
1628 | case 0x52000B00: | |
1629 | case 0x18000B00: | |
1630 | continue; | |
1631 | default: | |
1632 | return true; | |
1633 | } | |
1634 | } while (count-- > 0); | |
3b319aae | 1635 | |
c9c99e5e | 1636 | return false; |
3b319aae | 1637 | } |
c9c99e5e | 1638 | EXPORT_SYMBOL(ath9k_hw_check_alive); |
3b319aae | 1639 | |
15d2b585 SM |
1640 | static void ath9k_hw_init_mfp(struct ath_hw *ah) |
1641 | { | |
1642 | /* Setup MFP options for CCMP */ | |
1643 | if (AR_SREV_9280_20_OR_LATER(ah)) { | |
1644 | /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt | |
1645 | * frames when constructing CCMP AAD. */ | |
1646 | REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, | |
1647 | 0xc7ff); | |
60fc4962 CYY |
1648 | if (AR_SREV_9271(ah) || AR_DEVID_7010(ah)) |
1649 | ah->sw_mgmt_crypto_tx = true; | |
1650 | else | |
1651 | ah->sw_mgmt_crypto_tx = false; | |
e6510b11 | 1652 | ah->sw_mgmt_crypto_rx = false; |
15d2b585 SM |
1653 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { |
1654 | /* Disable hardware crypto for management frames */ | |
1655 | REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, | |
1656 | AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); | |
1657 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, | |
1658 | AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); | |
e6510b11 CYY |
1659 | ah->sw_mgmt_crypto_tx = true; |
1660 | ah->sw_mgmt_crypto_rx = true; | |
15d2b585 | 1661 | } else { |
e6510b11 CYY |
1662 | ah->sw_mgmt_crypto_tx = true; |
1663 | ah->sw_mgmt_crypto_rx = true; | |
15d2b585 SM |
1664 | } |
1665 | } | |
1666 | ||
1667 | static void ath9k_hw_reset_opmode(struct ath_hw *ah, | |
1668 | u32 macStaId1, u32 saveDefAntenna) | |
1669 | { | |
1670 | struct ath_common *common = ath9k_hw_common(ah); | |
1671 | ||
1672 | ENABLE_REGWRITE_BUFFER(ah); | |
1673 | ||
ecbbed32 | 1674 | REG_RMW(ah, AR_STA_ID1, macStaId1 |
15d2b585 | 1675 | | AR_STA_ID1_RTS_USE_DEF |
ecbbed32 FF |
1676 | | ah->sta_id1_defaults, |
1677 | ~AR_STA_ID1_SADH_MASK); | |
15d2b585 SM |
1678 | ath_hw_setbssidmask(common); |
1679 | REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); | |
1680 | ath9k_hw_write_associd(ah); | |
1681 | REG_WRITE(ah, AR_ISR, ~0); | |
1682 | REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); | |
1683 | ||
1684 | REGWRITE_BUFFER_FLUSH(ah); | |
1685 | ||
1686 | ath9k_hw_set_operating_mode(ah, ah->opmode); | |
1687 | } | |
1688 | ||
1689 | static void ath9k_hw_init_queues(struct ath_hw *ah) | |
1690 | { | |
1691 | int i; | |
1692 | ||
1693 | ENABLE_REGWRITE_BUFFER(ah); | |
1694 | ||
1695 | for (i = 0; i < AR_NUM_DCU; i++) | |
1696 | REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); | |
1697 | ||
1698 | REGWRITE_BUFFER_FLUSH(ah); | |
1699 | ||
1700 | ah->intr_txqs = 0; | |
1701 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
1702 | ath9k_hw_resettxqueue(ah, i); | |
1703 | } | |
1704 | ||
1705 | /* | |
1706 | * For big endian systems turn on swapping for descriptors | |
1707 | */ | |
1708 | static void ath9k_hw_init_desc(struct ath_hw *ah) | |
1709 | { | |
1710 | struct ath_common *common = ath9k_hw_common(ah); | |
1711 | ||
1712 | if (AR_SREV_9100(ah)) { | |
1713 | u32 mask; | |
1714 | mask = REG_READ(ah, AR_CFG); | |
1715 | if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { | |
1716 | ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", | |
1717 | mask); | |
1718 | } else { | |
1719 | mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; | |
1720 | REG_WRITE(ah, AR_CFG, mask); | |
1721 | ath_dbg(common, RESET, "Setting CFG 0x%x\n", | |
1722 | REG_READ(ah, AR_CFG)); | |
1723 | } | |
1724 | } else { | |
1725 | if (common->bus_ops->ath_bus_type == ATH_USB) { | |
1726 | /* Configure AR9271 target WLAN */ | |
1727 | if (AR_SREV_9271(ah)) | |
1728 | REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); | |
1729 | else | |
1730 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); | |
1731 | } | |
1732 | #ifdef __BIG_ENDIAN | |
1733 | else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || | |
ede6a5e7 MP |
1734 | AR_SREV_9550(ah) || AR_SREV_9531(ah) || |
1735 | AR_SREV_9561(ah)) | |
15d2b585 SM |
1736 | REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); |
1737 | else | |
1738 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); | |
1739 | #endif | |
1740 | } | |
1741 | } | |
1742 | ||
caed6579 SM |
1743 | /* |
1744 | * Fast channel change: | |
1745 | * (Change synthesizer based on channel freq without resetting chip) | |
caed6579 SM |
1746 | */ |
1747 | static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) | |
1748 | { | |
1749 | struct ath_common *common = ath9k_hw_common(ah); | |
b840cffe | 1750 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
caed6579 SM |
1751 | int ret; |
1752 | ||
1753 | if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) | |
1754 | goto fail; | |
1755 | ||
1756 | if (ah->chip_fullsleep) | |
1757 | goto fail; | |
1758 | ||
1759 | if (!ah->curchan) | |
1760 | goto fail; | |
1761 | ||
1762 | if (chan->channel == ah->curchan->channel) | |
1763 | goto fail; | |
1764 | ||
feb7bc99 FF |
1765 | if ((ah->curchan->channelFlags | chan->channelFlags) & |
1766 | (CHANNEL_HALF | CHANNEL_QUARTER)) | |
1767 | goto fail; | |
1768 | ||
b840cffe | 1769 | /* |
6b21fd20 | 1770 | * If cross-band fcc is not supoprted, bail out if channelFlags differ. |
b840cffe | 1771 | */ |
6b21fd20 | 1772 | if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) && |
af02efb3 | 1773 | ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) |
6b21fd20 | 1774 | goto fail; |
caed6579 SM |
1775 | |
1776 | if (!ath9k_hw_check_alive(ah)) | |
1777 | goto fail; | |
1778 | ||
1779 | /* | |
1780 | * For AR9462, make sure that calibration data for | |
1781 | * re-using are present. | |
1782 | */ | |
8a90555f | 1783 | if (AR_SREV_9462(ah) && (ah->caldata && |
4b9b42bf SM |
1784 | (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) || |
1785 | !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) || | |
1786 | !test_bit(RTT_DONE, &ah->caldata->cal_flags)))) | |
caed6579 SM |
1787 | goto fail; |
1788 | ||
1789 | ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", | |
1790 | ah->curchan->channel, chan->channel); | |
1791 | ||
1792 | ret = ath9k_hw_channel_change(ah, chan); | |
1793 | if (!ret) | |
1794 | goto fail; | |
1795 | ||
5955b2b0 | 1796 | if (ath9k_hw_mci_is_enabled(ah)) |
1bde95fa | 1797 | ar9003_mci_2g5g_switch(ah, false); |
caed6579 | 1798 | |
88033318 RM |
1799 | ath9k_hw_loadnf(ah, ah->curchan); |
1800 | ath9k_hw_start_nfcal(ah, true); | |
1801 | ||
caed6579 SM |
1802 | if (AR_SREV_9271(ah)) |
1803 | ar9002_hw_load_ani_reg(ah, chan); | |
1804 | ||
1805 | return 0; | |
1806 | fail: | |
1807 | return -EINVAL; | |
1808 | } | |
1809 | ||
8d7e09dd FF |
1810 | u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur) |
1811 | { | |
1812 | struct timespec ts; | |
1813 | s64 usec; | |
1814 | ||
1815 | if (!cur) { | |
1816 | getrawmonotonic(&ts); | |
1817 | cur = &ts; | |
1818 | } | |
1819 | ||
1820 | usec = cur->tv_sec * 1000000ULL + cur->tv_nsec / 1000; | |
1821 | usec -= last->tv_sec * 1000000ULL + last->tv_nsec / 1000; | |
1822 | ||
1823 | return (u32) usec; | |
1824 | } | |
1825 | EXPORT_SYMBOL(ath9k_hw_get_tsf_offset); | |
1826 | ||
cbe61d8a | 1827 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
caed6579 | 1828 | struct ath9k_hw_cal_data *caldata, bool fastcc) |
f078f209 | 1829 | { |
1510718d | 1830 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 1831 | u32 saveLedState; |
f078f209 LR |
1832 | u32 saveDefAntenna; |
1833 | u32 macStaId1; | |
46fe782c | 1834 | u64 tsf = 0; |
09d8e315 | 1835 | s64 usec = 0; |
15d2b585 | 1836 | int r; |
caed6579 | 1837 | bool start_mci_reset = false; |
63d32967 MSS |
1838 | bool save_fullsleep = ah->chip_fullsleep; |
1839 | ||
5955b2b0 | 1840 | if (ath9k_hw_mci_is_enabled(ah)) { |
528e5d36 SM |
1841 | start_mci_reset = ar9003_mci_start_reset(ah, chan); |
1842 | if (start_mci_reset) | |
1843 | return 0; | |
63d32967 MSS |
1844 | } |
1845 | ||
9ecdef4b | 1846 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
ae8d2858 | 1847 | return -EIO; |
f078f209 | 1848 | |
caed6579 SM |
1849 | if (ah->curchan && !ah->chip_fullsleep) |
1850 | ath9k_hw_getnf(ah, ah->curchan); | |
f078f209 | 1851 | |
20bd2a09 | 1852 | ah->caldata = caldata; |
fcb9a3de | 1853 | if (caldata && (chan->channel != caldata->channel || |
6b21fd20 | 1854 | chan->channelFlags != caldata->channelFlags)) { |
20bd2a09 FF |
1855 | /* Operating channel changed, reset channel calibration data */ |
1856 | memset(caldata, 0, sizeof(*caldata)); | |
1857 | ath9k_init_nfcal_hist_buffer(ah, chan); | |
51dea9be | 1858 | } else if (caldata) { |
4b9b42bf | 1859 | clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags); |
20bd2a09 | 1860 | } |
5bc225ac | 1861 | ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor); |
20bd2a09 | 1862 | |
caed6579 SM |
1863 | if (fastcc) { |
1864 | r = ath9k_hw_do_fastcc(ah, chan); | |
1865 | if (!r) | |
1866 | return r; | |
f078f209 LR |
1867 | } |
1868 | ||
5955b2b0 | 1869 | if (ath9k_hw_mci_is_enabled(ah)) |
528e5d36 | 1870 | ar9003_mci_stop_bt(ah, save_fullsleep); |
63d32967 | 1871 | |
f078f209 LR |
1872 | saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); |
1873 | if (saveDefAntenna == 0) | |
1874 | saveDefAntenna = 1; | |
1875 | ||
1876 | macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; | |
1877 | ||
09d8e315 FF |
1878 | /* Save TSF before chip reset, a cold reset clears it */ |
1879 | tsf = ath9k_hw_gettsf64(ah); | |
6438e0dd | 1880 | usec = ktime_to_us(ktime_get_raw()); |
46fe782c | 1881 | |
f078f209 LR |
1882 | saveLedState = REG_READ(ah, AR_CFG_LED) & |
1883 | (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | | |
1884 | AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); | |
1885 | ||
1886 | ath9k_hw_mark_phy_inactive(ah); | |
1887 | ||
45ef6a0b VT |
1888 | ah->paprd_table_write_done = false; |
1889 | ||
05020d23 | 1890 | /* Only required on the first reset */ |
d7e7d229 LR |
1891 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
1892 | REG_WRITE(ah, | |
1893 | AR9271_RESET_POWER_DOWN_CONTROL, | |
1894 | AR9271_RADIO_RF_RST); | |
1895 | udelay(50); | |
1896 | } | |
1897 | ||
f078f209 | 1898 | if (!ath9k_hw_chip_reset(ah, chan)) { |
3800276a | 1899 | ath_err(common, "Chip reset failed\n"); |
ae8d2858 | 1900 | return -EINVAL; |
f078f209 LR |
1901 | } |
1902 | ||
05020d23 | 1903 | /* Only required on the first reset */ |
d7e7d229 LR |
1904 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
1905 | ah->htc_reset_init = false; | |
1906 | REG_WRITE(ah, | |
1907 | AR9271_RESET_POWER_DOWN_CONTROL, | |
1908 | AR9271_GATE_MAC_CTL); | |
1909 | udelay(50); | |
1910 | } | |
1911 | ||
46fe782c | 1912 | /* Restore TSF */ |
6438e0dd | 1913 | usec = ktime_to_us(ktime_get_raw()) - usec; |
09d8e315 | 1914 | ath9k_hw_settsf64(ah, tsf + usec); |
46fe782c | 1915 | |
7a37081e | 1916 | if (AR_SREV_9280_20_OR_LATER(ah)) |
369391db | 1917 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); |
f078f209 | 1918 | |
e9141f71 S |
1919 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
1920 | ar9002_hw_enable_async_fifo(ah); | |
1921 | ||
25c56eec | 1922 | r = ath9k_hw_process_ini(ah, chan); |
ae8d2858 LR |
1923 | if (r) |
1924 | return r; | |
f078f209 | 1925 | |
935d00cc LB |
1926 | ath9k_hw_set_rfmode(ah, chan); |
1927 | ||
5955b2b0 | 1928 | if (ath9k_hw_mci_is_enabled(ah)) |
63d32967 MSS |
1929 | ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); |
1930 | ||
f860d526 FF |
1931 | /* |
1932 | * Some AR91xx SoC devices frequently fail to accept TSF writes | |
1933 | * right after the chip reset. When that happens, write a new | |
1934 | * value after the initvals have been applied, with an offset | |
1935 | * based on measured time difference | |
1936 | */ | |
1937 | if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { | |
1938 | tsf += 1500; | |
1939 | ath9k_hw_settsf64(ah, tsf); | |
1940 | } | |
1941 | ||
15d2b585 | 1942 | ath9k_hw_init_mfp(ah); |
0ced0e17 | 1943 | |
81c507a8 | 1944 | ath9k_hw_set_delta_slope(ah, chan); |
8fe65368 | 1945 | ath9k_hw_spur_mitigate_freq(ah, chan); |
d6509151 | 1946 | ah->eep_ops->set_board_values(ah, chan); |
a7765828 | 1947 | |
15d2b585 | 1948 | ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); |
00e0003e | 1949 | |
8fe65368 | 1950 | r = ath9k_hw_rf_set_freq(ah, chan); |
0a3b7bac LR |
1951 | if (r) |
1952 | return r; | |
f078f209 | 1953 | |
dfdac8ac FF |
1954 | ath9k_hw_set_clockrate(ah); |
1955 | ||
15d2b585 | 1956 | ath9k_hw_init_queues(ah); |
2660b81a | 1957 | ath9k_hw_init_interrupt_masks(ah, ah->opmode); |
e36b27af | 1958 | ath9k_hw_ani_cache_ini_regs(ah); |
f078f209 LR |
1959 | ath9k_hw_init_qos(ah); |
1960 | ||
2660b81a | 1961 | if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) |
b2d70d49 | 1962 | ath9k_hw_gpio_request_in(ah, ah->rfkill_gpio, "ath9k-rfkill"); |
3b319aae | 1963 | |
0005baf4 | 1964 | ath9k_hw_init_global_settings(ah); |
f078f209 | 1965 | |
fe2b6afb FF |
1966 | if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { |
1967 | REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, | |
1968 | AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); | |
1969 | REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, | |
1970 | AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); | |
1971 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, | |
1972 | AR_PCU_MISC_MODE2_ENABLE_AGGWEP); | |
ac88b6ec VN |
1973 | } |
1974 | ||
ca7a4deb | 1975 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); |
f078f209 LR |
1976 | |
1977 | ath9k_hw_set_dma(ah); | |
1978 | ||
ed6ebd8b RM |
1979 | if (!ath9k_hw_mci_is_enabled(ah)) |
1980 | REG_WRITE(ah, AR_OBS, 8); | |
f078f209 | 1981 | |
7b37e0d4 | 1982 | ENABLE_REG_RMW_BUFFER(ah); |
0ce024cb | 1983 | if (ah->config.rx_intr_mitigation) { |
a64e1a45 SM |
1984 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last); |
1985 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first); | |
f078f209 LR |
1986 | } |
1987 | ||
7f62a136 VT |
1988 | if (ah->config.tx_intr_mitigation) { |
1989 | REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); | |
1990 | REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); | |
1991 | } | |
7b37e0d4 | 1992 | REG_RMW_BUFFER_FLUSH(ah); |
7f62a136 | 1993 | |
f078f209 LR |
1994 | ath9k_hw_init_bb(ah, chan); |
1995 | ||
77a5a664 | 1996 | if (caldata) { |
4b9b42bf SM |
1997 | clear_bit(TXIQCAL_DONE, &caldata->cal_flags); |
1998 | clear_bit(TXCLCAL_DONE, &caldata->cal_flags); | |
77a5a664 | 1999 | } |
ae8d2858 | 2000 | if (!ath9k_hw_init_cal(ah, chan)) |
6badaaf7 | 2001 | return -EIO; |
f078f209 | 2002 | |
5955b2b0 | 2003 | if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) |
528e5d36 | 2004 | return -EIO; |
63d32967 | 2005 | |
7d0d0df0 | 2006 | ENABLE_REGWRITE_BUFFER(ah); |
f078f209 | 2007 | |
8fe65368 | 2008 | ath9k_hw_restore_chainmask(ah); |
f078f209 LR |
2009 | REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); |
2010 | ||
7d0d0df0 | 2011 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 2012 | |
f4c34af4 SM |
2013 | ath9k_hw_gen_timer_start_tsf2(ah); |
2014 | ||
15d2b585 | 2015 | ath9k_hw_init_desc(ah); |
f078f209 | 2016 | |
dbccdd1d | 2017 | if (ath9k_hw_btcoex_is_enabled(ah)) |
42cc41ed VT |
2018 | ath9k_hw_btcoex_enable(ah); |
2019 | ||
5955b2b0 | 2020 | if (ath9k_hw_mci_is_enabled(ah)) |
528e5d36 | 2021 | ar9003_mci_check_bt(ah); |
63d32967 | 2022 | |
7b89fccf FF |
2023 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
2024 | ath9k_hw_loadnf(ah, chan); | |
2025 | ath9k_hw_start_nfcal(ah, true); | |
2026 | } | |
1fe860ed | 2027 | |
a7abaf7d | 2028 | if (AR_SREV_9300_20_OR_LATER(ah)) |
aea702b7 | 2029 | ar9003_hw_bb_watchdog_config(ah); |
a7abaf7d SM |
2030 | |
2031 | if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR) | |
51ac8cbb | 2032 | ar9003_hw_disable_phy_restart(ah); |
51ac8cbb | 2033 | |
691680b8 FF |
2034 | ath9k_hw_apply_gpio_override(ah); |
2035 | ||
7bdea96a | 2036 | if (AR_SREV_9565(ah) && common->bt_ant_diversity) |
362cd03f SM |
2037 | REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); |
2038 | ||
4307b0fe LB |
2039 | if (ah->hw->conf.radar_enabled) { |
2040 | /* set HW specific DFS configuration */ | |
7a0a260a | 2041 | ah->radar_conf.ext_channel = IS_CHAN_HT40(chan); |
4307b0fe LB |
2042 | ath9k_hw_set_radar_params(ah); |
2043 | } | |
2044 | ||
ae8d2858 | 2045 | return 0; |
f078f209 | 2046 | } |
7322fd19 | 2047 | EXPORT_SYMBOL(ath9k_hw_reset); |
f078f209 | 2048 | |
f1dc5600 S |
2049 | /******************************/ |
2050 | /* Power Management (Chipset) */ | |
2051 | /******************************/ | |
2052 | ||
42d5bc3f LR |
2053 | /* |
2054 | * Notify Power Mgt is disabled in self-generated frames. | |
2055 | * If requested, force chip to sleep. | |
2056 | */ | |
31604cf0 | 2057 | static void ath9k_set_power_sleep(struct ath_hw *ah) |
f078f209 | 2058 | { |
f1dc5600 | 2059 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
2577c6e8 | 2060 | |
a4a2954f | 2061 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { |
153dccd4 RM |
2062 | REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); |
2063 | REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); | |
2064 | REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); | |
31604cf0 SM |
2065 | /* xxx Required for WLAN only case ? */ |
2066 | REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); | |
2067 | udelay(100); | |
2068 | } | |
2577c6e8 | 2069 | |
31604cf0 SM |
2070 | /* |
2071 | * Clear the RTC force wake bit to allow the | |
2072 | * mac to go to sleep. | |
2073 | */ | |
2074 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); | |
2075 | ||
153dccd4 | 2076 | if (ath9k_hw_mci_is_enabled(ah)) |
31604cf0 | 2077 | udelay(100); |
2577c6e8 | 2078 | |
31604cf0 SM |
2079 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
2080 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); | |
f078f209 | 2081 | |
31604cf0 SM |
2082 | /* Shutdown chip. Active low */ |
2083 | if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { | |
2084 | REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); | |
2085 | udelay(2); | |
f1dc5600 | 2086 | } |
9a658d2b LR |
2087 | |
2088 | /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ | |
a7322812 RW |
2089 | if (AR_SREV_9300_20_OR_LATER(ah)) |
2090 | REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); | |
f078f209 LR |
2091 | } |
2092 | ||
bbd79af5 LR |
2093 | /* |
2094 | * Notify Power Management is enabled in self-generating | |
2095 | * frames. If request, set power mode of chip to | |
2096 | * auto/normal. Duration in units of 128us (1/8 TU). | |
2097 | */ | |
31604cf0 | 2098 | static void ath9k_set_power_network_sleep(struct ath_hw *ah) |
f078f209 | 2099 | { |
31604cf0 | 2100 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
2577c6e8 | 2101 | |
f1dc5600 | 2102 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
f078f209 | 2103 | |
31604cf0 SM |
2104 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
2105 | /* Set WakeOnInterrupt bit; clear ForceWake bit */ | |
2106 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, | |
2107 | AR_RTC_FORCE_WAKE_ON_INT); | |
2108 | } else { | |
2577c6e8 | 2109 | |
31604cf0 SM |
2110 | /* When chip goes into network sleep, it could be waken |
2111 | * up by MCI_INT interrupt caused by BT's HW messages | |
2112 | * (LNA_xxx, CONT_xxx) which chould be in a very fast | |
2113 | * rate (~100us). This will cause chip to leave and | |
2114 | * re-enter network sleep mode frequently, which in | |
2115 | * consequence will have WLAN MCI HW to generate lots of | |
2116 | * SYS_WAKING and SYS_SLEEPING messages which will make | |
2117 | * BT CPU to busy to process. | |
2118 | */ | |
153dccd4 RM |
2119 | if (ath9k_hw_mci_is_enabled(ah)) |
2120 | REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, | |
2121 | AR_MCI_INTERRUPT_RX_HW_MSG_MASK); | |
31604cf0 SM |
2122 | /* |
2123 | * Clear the RTC force wake bit to allow the | |
2124 | * mac to go to sleep. | |
2125 | */ | |
153dccd4 | 2126 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); |
31604cf0 | 2127 | |
153dccd4 | 2128 | if (ath9k_hw_mci_is_enabled(ah)) |
31604cf0 | 2129 | udelay(30); |
f078f209 | 2130 | } |
9a658d2b LR |
2131 | |
2132 | /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ | |
2133 | if (AR_SREV_9300_20_OR_LATER(ah)) | |
2134 | REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); | |
f078f209 LR |
2135 | } |
2136 | ||
31604cf0 | 2137 | static bool ath9k_hw_set_power_awake(struct ath_hw *ah) |
f078f209 | 2138 | { |
f1dc5600 S |
2139 | u32 val; |
2140 | int i; | |
f078f209 | 2141 | |
9a658d2b LR |
2142 | /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ |
2143 | if (AR_SREV_9300_20_OR_LATER(ah)) { | |
2144 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
2145 | udelay(10); | |
2146 | } | |
2147 | ||
31604cf0 SM |
2148 | if ((REG_READ(ah, AR_RTC_STATUS) & |
2149 | AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { | |
2150 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { | |
2151 | return false; | |
f1dc5600 | 2152 | } |
31604cf0 SM |
2153 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
2154 | ath9k_hw_init_pll(ah, NULL); | |
2155 | } | |
2156 | if (AR_SREV_9100(ah)) | |
2157 | REG_SET_BIT(ah, AR_RTC_RESET, | |
2158 | AR_RTC_RESET_EN); | |
2159 | ||
2160 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, | |
2161 | AR_RTC_FORCE_WAKE_EN); | |
04575f21 | 2162 | if (AR_SREV_9100(ah)) |
3683a07b | 2163 | mdelay(10); |
04575f21 SM |
2164 | else |
2165 | udelay(50); | |
f078f209 | 2166 | |
31604cf0 SM |
2167 | for (i = POWER_UP_TIME / 50; i > 0; i--) { |
2168 | val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; | |
2169 | if (val == AR_RTC_STATUS_ON) | |
2170 | break; | |
2171 | udelay(50); | |
f1dc5600 S |
2172 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, |
2173 | AR_RTC_FORCE_WAKE_EN); | |
31604cf0 SM |
2174 | } |
2175 | if (i == 0) { | |
2176 | ath_err(ath9k_hw_common(ah), | |
2177 | "Failed to wakeup in %uus\n", | |
2178 | POWER_UP_TIME / 20); | |
2179 | return false; | |
f078f209 LR |
2180 | } |
2181 | ||
cdbe408d RM |
2182 | if (ath9k_hw_mci_is_enabled(ah)) |
2183 | ar9003_mci_set_power_awake(ah); | |
2184 | ||
f1dc5600 | 2185 | REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
f078f209 | 2186 | |
f1dc5600 | 2187 | return true; |
f078f209 LR |
2188 | } |
2189 | ||
9ecdef4b | 2190 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) |
f078f209 | 2191 | { |
c46917bb | 2192 | struct ath_common *common = ath9k_hw_common(ah); |
31604cf0 | 2193 | int status = true; |
f1dc5600 S |
2194 | static const char *modes[] = { |
2195 | "AWAKE", | |
2196 | "FULL-SLEEP", | |
2197 | "NETWORK SLEEP", | |
2198 | "UNDEFINED" | |
2199 | }; | |
f1dc5600 | 2200 | |
cbdec975 GJ |
2201 | if (ah->power_mode == mode) |
2202 | return status; | |
2203 | ||
d2182b69 | 2204 | ath_dbg(common, RESET, "%s -> %s\n", |
226afe68 | 2205 | modes[ah->power_mode], modes[mode]); |
f1dc5600 S |
2206 | |
2207 | switch (mode) { | |
2208 | case ATH9K_PM_AWAKE: | |
31604cf0 | 2209 | status = ath9k_hw_set_power_awake(ah); |
f1dc5600 S |
2210 | break; |
2211 | case ATH9K_PM_FULL_SLEEP: | |
5955b2b0 | 2212 | if (ath9k_hw_mci_is_enabled(ah)) |
d1ca8b8e | 2213 | ar9003_mci_set_full_sleep(ah); |
1010911e | 2214 | |
31604cf0 | 2215 | ath9k_set_power_sleep(ah); |
2660b81a | 2216 | ah->chip_fullsleep = true; |
f1dc5600 S |
2217 | break; |
2218 | case ATH9K_PM_NETWORK_SLEEP: | |
31604cf0 | 2219 | ath9k_set_power_network_sleep(ah); |
f1dc5600 | 2220 | break; |
f078f209 | 2221 | default: |
3800276a | 2222 | ath_err(common, "Unknown power mode %u\n", mode); |
f078f209 LR |
2223 | return false; |
2224 | } | |
2660b81a | 2225 | ah->power_mode = mode; |
f1dc5600 | 2226 | |
69f4aab1 LR |
2227 | /* |
2228 | * XXX: If this warning never comes up after a while then | |
2229 | * simply keep the ATH_DBG_WARN_ON_ONCE() but make | |
2230 | * ath9k_hw_setpower() return type void. | |
2231 | */ | |
97dcec57 SM |
2232 | |
2233 | if (!(ah->ah_flags & AH_UNPLUGGED)) | |
2234 | ATH_DBG_WARN_ON_ONCE(!status); | |
69f4aab1 | 2235 | |
f1dc5600 | 2236 | return status; |
f078f209 | 2237 | } |
7322fd19 | 2238 | EXPORT_SYMBOL(ath9k_hw_setpower); |
f078f209 | 2239 | |
f1dc5600 S |
2240 | /*******************/ |
2241 | /* Beacon Handling */ | |
2242 | /*******************/ | |
2243 | ||
cbe61d8a | 2244 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) |
f078f209 | 2245 | { |
f078f209 LR |
2246 | int flags = 0; |
2247 | ||
7d0d0df0 S |
2248 | ENABLE_REGWRITE_BUFFER(ah); |
2249 | ||
2660b81a | 2250 | switch (ah->opmode) { |
d97809db | 2251 | case NL80211_IFTYPE_ADHOC: |
f078f209 LR |
2252 | REG_SET_BIT(ah, AR_TXCFG, |
2253 | AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); | |
2664d666 | 2254 | case NL80211_IFTYPE_MESH_POINT: |
d97809db | 2255 | case NL80211_IFTYPE_AP: |
dd347f2f FF |
2256 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); |
2257 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - | |
2258 | TU_TO_USEC(ah->config.dma_beacon_response_time)); | |
2259 | REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - | |
2260 | TU_TO_USEC(ah->config.sw_beacon_response_time)); | |
f078f209 LR |
2261 | flags |= |
2262 | AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; | |
2263 | break; | |
d97809db | 2264 | default: |
d2182b69 JP |
2265 | ath_dbg(ath9k_hw_common(ah), BEACON, |
2266 | "%s: unsupported opmode: %d\n", __func__, ah->opmode); | |
d97809db CM |
2267 | return; |
2268 | break; | |
f078f209 LR |
2269 | } |
2270 | ||
dd347f2f FF |
2271 | REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); |
2272 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); | |
2273 | REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); | |
f078f209 | 2274 | |
7d0d0df0 | 2275 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 2276 | |
f078f209 LR |
2277 | REG_SET_BIT(ah, AR_TIMER_MODE, flags); |
2278 | } | |
7322fd19 | 2279 | EXPORT_SYMBOL(ath9k_hw_beaconinit); |
f078f209 | 2280 | |
cbe61d8a | 2281 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, |
f1dc5600 | 2282 | const struct ath9k_beacon_state *bs) |
f078f209 LR |
2283 | { |
2284 | u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; | |
2660b81a | 2285 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
c46917bb | 2286 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 2287 | |
7d0d0df0 S |
2288 | ENABLE_REGWRITE_BUFFER(ah); |
2289 | ||
4ed15762 FF |
2290 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); |
2291 | REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); | |
2292 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); | |
f078f209 | 2293 | |
7d0d0df0 | 2294 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 2295 | |
f078f209 LR |
2296 | REG_RMW_FIELD(ah, AR_RSSI_THR, |
2297 | AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); | |
2298 | ||
f29f5c08 | 2299 | beaconintval = bs->bs_intval; |
f078f209 LR |
2300 | |
2301 | if (bs->bs_sleepduration > beaconintval) | |
2302 | beaconintval = bs->bs_sleepduration; | |
2303 | ||
2304 | dtimperiod = bs->bs_dtimperiod; | |
2305 | if (bs->bs_sleepduration > dtimperiod) | |
2306 | dtimperiod = bs->bs_sleepduration; | |
2307 | ||
2308 | if (beaconintval == dtimperiod) | |
2309 | nextTbtt = bs->bs_nextdtim; | |
2310 | else | |
2311 | nextTbtt = bs->bs_nexttbtt; | |
2312 | ||
58bb9ca8 JD |
2313 | ath_dbg(common, BEACON, "next DTIM %u\n", bs->bs_nextdtim); |
2314 | ath_dbg(common, BEACON, "next beacon %u\n", nextTbtt); | |
2315 | ath_dbg(common, BEACON, "beacon period %u\n", beaconintval); | |
2316 | ath_dbg(common, BEACON, "DTIM period %u\n", dtimperiod); | |
f078f209 | 2317 | |
7d0d0df0 S |
2318 | ENABLE_REGWRITE_BUFFER(ah); |
2319 | ||
4ed15762 FF |
2320 | REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); |
2321 | REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); | |
f078f209 | 2322 | |
f1dc5600 S |
2323 | REG_WRITE(ah, AR_SLEEP1, |
2324 | SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) | |
2325 | | AR_SLEEP1_ASSUME_DTIM); | |
f078f209 | 2326 | |
f1dc5600 S |
2327 | if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) |
2328 | beacontimeout = (BEACON_TIMEOUT_VAL << 3); | |
2329 | else | |
2330 | beacontimeout = MIN_BEACON_TIMEOUT_VAL; | |
f078f209 | 2331 | |
f1dc5600 S |
2332 | REG_WRITE(ah, AR_SLEEP2, |
2333 | SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); | |
f078f209 | 2334 | |
4ed15762 FF |
2335 | REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); |
2336 | REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); | |
f078f209 | 2337 | |
7d0d0df0 | 2338 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 2339 | |
f1dc5600 S |
2340 | REG_SET_BIT(ah, AR_TIMER_MODE, |
2341 | AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | | |
2342 | AR_DTIM_TIMER_EN); | |
f078f209 | 2343 | |
4af9cf4f S |
2344 | /* TSF Out of Range Threshold */ |
2345 | REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); | |
f078f209 | 2346 | } |
7322fd19 | 2347 | EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); |
f078f209 | 2348 | |
f1dc5600 S |
2349 | /*******************/ |
2350 | /* HW Capabilities */ | |
2351 | /*******************/ | |
2352 | ||
6054069a FF |
2353 | static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) |
2354 | { | |
2355 | eeprom_chainmask &= chip_chainmask; | |
2356 | if (eeprom_chainmask) | |
2357 | return eeprom_chainmask; | |
2358 | else | |
2359 | return chip_chainmask; | |
2360 | } | |
2361 | ||
9a66af33 ZK |
2362 | /** |
2363 | * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset | |
2364 | * @ah: the atheros hardware data structure | |
2365 | * | |
2366 | * We enable DFS support upstream on chipsets which have passed a series | |
2367 | * of tests. The testing requirements are going to be documented. Desired | |
2368 | * test requirements are documented at: | |
2369 | * | |
2370 | * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs | |
2371 | * | |
2372 | * Once a new chipset gets properly tested an individual commit can be used | |
2373 | * to document the testing for DFS for that chipset. | |
2374 | */ | |
2375 | static bool ath9k_hw_dfs_tested(struct ath_hw *ah) | |
2376 | { | |
2377 | ||
2378 | switch (ah->hw_version.macVersion) { | |
73e4937d ZK |
2379 | /* for temporary testing DFS with 9280 */ |
2380 | case AR_SREV_VERSION_9280: | |
9a66af33 ZK |
2381 | /* AR9580 will likely be our first target to get testing on */ |
2382 | case AR_SREV_VERSION_9580: | |
73e4937d | 2383 | return true; |
9a66af33 ZK |
2384 | default: |
2385 | return false; | |
2386 | } | |
2387 | } | |
2388 | ||
a01ab81b MP |
2389 | static void ath9k_gpio_cap_init(struct ath_hw *ah) |
2390 | { | |
2391 | struct ath9k_hw_capabilities *pCap = &ah->caps; | |
2392 | ||
2393 | if (AR_SREV_9271(ah)) { | |
2394 | pCap->num_gpio_pins = AR9271_NUM_GPIO; | |
2395 | pCap->gpio_mask = AR9271_GPIO_MASK; | |
2396 | } else if (AR_DEVID_7010(ah)) { | |
2397 | pCap->num_gpio_pins = AR7010_NUM_GPIO; | |
2398 | pCap->gpio_mask = AR7010_GPIO_MASK; | |
2399 | } else if (AR_SREV_9287(ah)) { | |
2400 | pCap->num_gpio_pins = AR9287_NUM_GPIO; | |
2401 | pCap->gpio_mask = AR9287_GPIO_MASK; | |
2402 | } else if (AR_SREV_9285(ah)) { | |
2403 | pCap->num_gpio_pins = AR9285_NUM_GPIO; | |
2404 | pCap->gpio_mask = AR9285_GPIO_MASK; | |
2405 | } else if (AR_SREV_9280(ah)) { | |
2406 | pCap->num_gpio_pins = AR9280_NUM_GPIO; | |
2407 | pCap->gpio_mask = AR9280_GPIO_MASK; | |
2408 | } else if (AR_SREV_9300(ah)) { | |
2409 | pCap->num_gpio_pins = AR9300_NUM_GPIO; | |
2410 | pCap->gpio_mask = AR9300_GPIO_MASK; | |
2411 | } else if (AR_SREV_9330(ah)) { | |
2412 | pCap->num_gpio_pins = AR9330_NUM_GPIO; | |
2413 | pCap->gpio_mask = AR9330_GPIO_MASK; | |
2414 | } else if (AR_SREV_9340(ah)) { | |
2415 | pCap->num_gpio_pins = AR9340_NUM_GPIO; | |
2416 | pCap->gpio_mask = AR9340_GPIO_MASK; | |
2417 | } else if (AR_SREV_9462(ah)) { | |
2418 | pCap->num_gpio_pins = AR9462_NUM_GPIO; | |
2419 | pCap->gpio_mask = AR9462_GPIO_MASK; | |
2420 | } else if (AR_SREV_9485(ah)) { | |
2421 | pCap->num_gpio_pins = AR9485_NUM_GPIO; | |
2422 | pCap->gpio_mask = AR9485_GPIO_MASK; | |
2423 | } else if (AR_SREV_9531(ah)) { | |
2424 | pCap->num_gpio_pins = AR9531_NUM_GPIO; | |
2425 | pCap->gpio_mask = AR9531_GPIO_MASK; | |
2426 | } else if (AR_SREV_9550(ah)) { | |
2427 | pCap->num_gpio_pins = AR9550_NUM_GPIO; | |
2428 | pCap->gpio_mask = AR9550_GPIO_MASK; | |
2429 | } else if (AR_SREV_9561(ah)) { | |
2430 | pCap->num_gpio_pins = AR9561_NUM_GPIO; | |
2431 | pCap->gpio_mask = AR9561_GPIO_MASK; | |
2432 | } else if (AR_SREV_9565(ah)) { | |
2433 | pCap->num_gpio_pins = AR9565_NUM_GPIO; | |
2434 | pCap->gpio_mask = AR9565_GPIO_MASK; | |
2435 | } else if (AR_SREV_9580(ah)) { | |
2436 | pCap->num_gpio_pins = AR9580_NUM_GPIO; | |
2437 | pCap->gpio_mask = AR9580_GPIO_MASK; | |
2438 | } else { | |
2439 | pCap->num_gpio_pins = AR_NUM_GPIO; | |
2440 | pCap->gpio_mask = AR_GPIO_MASK; | |
2441 | } | |
2442 | } | |
2443 | ||
a9a29ce6 | 2444 | int ath9k_hw_fill_cap_info(struct ath_hw *ah) |
f078f209 | 2445 | { |
2660b81a | 2446 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
608b88cb | 2447 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
c46917bb | 2448 | struct ath_common *common = ath9k_hw_common(ah); |
608b88cb | 2449 | |
0ff2b5c0 | 2450 | u16 eeval; |
47c80de6 | 2451 | u8 ant_div_ctl1, tx_chainmask, rx_chainmask; |
f078f209 | 2452 | |
f74df6fb | 2453 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); |
608b88cb | 2454 | regulatory->current_rd = eeval; |
f078f209 | 2455 | |
2660b81a | 2456 | if (ah->opmode != NL80211_IFTYPE_AP && |
d535a42a | 2457 | ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { |
608b88cb LR |
2458 | if (regulatory->current_rd == 0x64 || |
2459 | regulatory->current_rd == 0x65) | |
2460 | regulatory->current_rd += 5; | |
2461 | else if (regulatory->current_rd == 0x41) | |
2462 | regulatory->current_rd = 0x43; | |
d2182b69 JP |
2463 | ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", |
2464 | regulatory->current_rd); | |
f1dc5600 | 2465 | } |
f078f209 | 2466 | |
f74df6fb | 2467 | eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); |
3468968e FF |
2468 | |
2469 | if (eeval & AR5416_OPFLAGS_11A) { | |
2470 | if (ah->disable_5ghz) | |
2471 | ath_warn(common, "disabling 5GHz band\n"); | |
2472 | else | |
2473 | pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; | |
a9a29ce6 GJ |
2474 | } |
2475 | ||
3468968e FF |
2476 | if (eeval & AR5416_OPFLAGS_11G) { |
2477 | if (ah->disable_2ghz) | |
2478 | ath_warn(common, "disabling 2GHz band\n"); | |
2479 | else | |
2480 | pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; | |
2481 | } | |
f078f209 | 2482 | |
3468968e FF |
2483 | if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) { |
2484 | ath_err(common, "both bands are disabled\n"); | |
2485 | return -EINVAL; | |
2486 | } | |
f1dc5600 | 2487 | |
e41db61d SM |
2488 | if (AR_SREV_9485(ah) || |
2489 | AR_SREV_9285(ah) || | |
2490 | AR_SREV_9330(ah) || | |
2491 | AR_SREV_9565(ah)) | |
ee79ccd9 | 2492 | pCap->chip_chainmask = 1; |
6054069a | 2493 | else if (!AR_SREV_9280_20_OR_LATER(ah)) |
ee79ccd9 SM |
2494 | pCap->chip_chainmask = 7; |
2495 | else if (!AR_SREV_9300_20_OR_LATER(ah) || | |
2496 | AR_SREV_9340(ah) || | |
2497 | AR_SREV_9462(ah) || | |
2498 | AR_SREV_9531(ah)) | |
2499 | pCap->chip_chainmask = 3; | |
6054069a | 2500 | else |
ee79ccd9 | 2501 | pCap->chip_chainmask = 7; |
6054069a | 2502 | |
f74df6fb | 2503 | pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); |
d7e7d229 LR |
2504 | /* |
2505 | * For AR9271 we will temporarilly uses the rx chainmax as read from | |
2506 | * the EEPROM. | |
2507 | */ | |
8147f5de | 2508 | if ((ah->hw_version.devid == AR5416_DEVID_PCI) && |
d7e7d229 LR |
2509 | !(eeval & AR5416_OPFLAGS_11A) && |
2510 | !(AR_SREV_9271(ah))) | |
2511 | /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ | |
8147f5de | 2512 | pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; |
598cdd52 FF |
2513 | else if (AR_SREV_9100(ah)) |
2514 | pCap->rx_chainmask = 0x7; | |
8147f5de | 2515 | else |
d7e7d229 | 2516 | /* Use rx_chainmask from EEPROM. */ |
8147f5de | 2517 | pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); |
f078f209 | 2518 | |
ee79ccd9 SM |
2519 | pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask); |
2520 | pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask); | |
82b2d334 FF |
2521 | ah->txchainmask = pCap->tx_chainmask; |
2522 | ah->rxchainmask = pCap->rx_chainmask; | |
6054069a | 2523 | |
7a37081e | 2524 | ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; |
f078f209 | 2525 | |
02d2ebb2 FF |
2526 | /* enable key search for every frame in an aggregate */ |
2527 | if (AR_SREV_9300_20_OR_LATER(ah)) | |
2528 | ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; | |
2529 | ||
ce2220d1 BR |
2530 | common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; |
2531 | ||
0db156e9 | 2532 | if (ah->hw_version.devid != AR2427_DEVID_PCIE) |
f1dc5600 S |
2533 | pCap->hw_caps |= ATH9K_HW_CAP_HT; |
2534 | else | |
2535 | pCap->hw_caps &= ~ATH9K_HW_CAP_HT; | |
f078f209 | 2536 | |
a01ab81b | 2537 | ath9k_gpio_cap_init(ah); |
f078f209 | 2538 | |
1b2538b2 | 2539 | if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) |
f1dc5600 | 2540 | pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; |
1b2538b2 | 2541 | else |
f1dc5600 | 2542 | pCap->rts_aggr_limit = (8 * 1024); |
f078f209 | 2543 | |
74e13060 | 2544 | #ifdef CONFIG_ATH9K_RFKILL |
2660b81a S |
2545 | ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); |
2546 | if (ah->rfsilent & EEP_RFSILENT_ENABLED) { | |
2547 | ah->rfkill_gpio = | |
2548 | MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); | |
2549 | ah->rfkill_polarity = | |
2550 | MS(ah->rfsilent, EEP_RFSILENT_POLARITY); | |
f1dc5600 S |
2551 | |
2552 | pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; | |
f078f209 | 2553 | } |
f1dc5600 | 2554 | #endif |
d5d1154f | 2555 | if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) |
bde748a4 VN |
2556 | pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; |
2557 | else | |
2558 | pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; | |
f078f209 | 2559 | |
e7594072 | 2560 | if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) |
f1dc5600 S |
2561 | pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; |
2562 | else | |
2563 | pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; | |
f078f209 | 2564 | |
ceb26445 | 2565 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
784ad503 | 2566 | pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; |
ede6a5e7 MP |
2567 | if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && |
2568 | !AR_SREV_9561(ah) && !AR_SREV_9565(ah)) | |
784ad503 VT |
2569 | pCap->hw_caps |= ATH9K_HW_CAP_LDPC; |
2570 | ||
ceb26445 VT |
2571 | pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; |
2572 | pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; | |
2573 | pCap->rx_status_len = sizeof(struct ar9003_rxs); | |
162c3be3 | 2574 | pCap->tx_desc_len = sizeof(struct ar9003_txc); |
5088c2f1 | 2575 | pCap->txs_len = sizeof(struct ar9003_txs); |
162c3be3 VT |
2576 | } else { |
2577 | pCap->tx_desc_len = sizeof(struct ath_desc); | |
a949b172 | 2578 | if (AR_SREV_9280_20(ah)) |
6b42e8d0 | 2579 | pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; |
ceb26445 | 2580 | } |
1adf02ff | 2581 | |
6c84ce08 VT |
2582 | if (AR_SREV_9300_20_OR_LATER(ah)) |
2583 | pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; | |
2584 | ||
ede6a5e7 MP |
2585 | if (AR_SREV_9561(ah)) |
2586 | ah->ent_mode = 0x3BDA000; | |
2587 | else if (AR_SREV_9300_20_OR_LATER(ah)) | |
6ee63f55 SB |
2588 | ah->ent_mode = REG_READ(ah, AR_ENT_OTP); |
2589 | ||
a42acef0 | 2590 | if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) |
6473d24d VT |
2591 | pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; |
2592 | ||
f85c3371 | 2593 | if (AR_SREV_9285(ah)) { |
754dc536 VT |
2594 | if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { |
2595 | ant_div_ctl1 = | |
2596 | ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); | |
f85c3371 | 2597 | if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) { |
754dc536 | 2598 | pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; |
f85c3371 SM |
2599 | ath_info(common, "Enable LNA combining\n"); |
2600 | } | |
754dc536 | 2601 | } |
f85c3371 SM |
2602 | } |
2603 | ||
ea066d5a MSS |
2604 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
2605 | if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) | |
2606 | pCap->hw_caps |= ATH9K_HW_CAP_APM; | |
2607 | } | |
2608 | ||
06236e53 | 2609 | if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { |
21d2c63a | 2610 | ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); |
f85c3371 | 2611 | if ((ant_div_ctl1 >> 0x6) == 0x3) { |
21d2c63a | 2612 | pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; |
f85c3371 SM |
2613 | ath_info(common, "Enable LNA combining\n"); |
2614 | } | |
21d2c63a | 2615 | } |
754dc536 | 2616 | |
9a66af33 ZK |
2617 | if (ath9k_hw_dfs_tested(ah)) |
2618 | pCap->hw_caps |= ATH9K_HW_CAP_DFS; | |
2619 | ||
47c80de6 VT |
2620 | tx_chainmask = pCap->tx_chainmask; |
2621 | rx_chainmask = pCap->rx_chainmask; | |
2622 | while (tx_chainmask || rx_chainmask) { | |
2623 | if (tx_chainmask & BIT(0)) | |
2624 | pCap->max_txchains++; | |
2625 | if (rx_chainmask & BIT(0)) | |
2626 | pCap->max_rxchains++; | |
2627 | ||
2628 | tx_chainmask >>= 1; | |
2629 | rx_chainmask >>= 1; | |
2630 | } | |
2631 | ||
a4a2954f | 2632 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { |
3789d59c MSS |
2633 | if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) |
2634 | pCap->hw_caps |= ATH9K_HW_CAP_MCI; | |
2635 | ||
2b5e54e2 | 2636 | if (AR_SREV_9462_20_OR_LATER(ah)) |
3789d59c | 2637 | pCap->hw_caps |= ATH9K_HW_CAP_RTT; |
3789d59c MSS |
2638 | } |
2639 | ||
0f21ee8d SM |
2640 | if (AR_SREV_9300_20_OR_LATER(ah) && |
2641 | ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) | |
2642 | pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; | |
2643 | ||
12a44422 SM |
2644 | #ifdef CONFIG_ATH9K_WOW |
2645 | if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah)) | |
2646 | ah->wow.max_patterns = MAX_NUM_PATTERN; | |
2647 | else | |
2648 | ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY; | |
2649 | #endif | |
2650 | ||
a9a29ce6 | 2651 | return 0; |
f078f209 LR |
2652 | } |
2653 | ||
f1dc5600 S |
2654 | /****************************/ |
2655 | /* GPIO / RFKILL / Antennae */ | |
2656 | /****************************/ | |
f078f209 | 2657 | |
b2d70d49 | 2658 | static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type) |
f1dc5600 S |
2659 | { |
2660 | int addr; | |
2661 | u32 gpio_shift, tmp; | |
f078f209 | 2662 | |
f1dc5600 S |
2663 | if (gpio > 11) |
2664 | addr = AR_GPIO_OUTPUT_MUX3; | |
2665 | else if (gpio > 5) | |
2666 | addr = AR_GPIO_OUTPUT_MUX2; | |
2667 | else | |
2668 | addr = AR_GPIO_OUTPUT_MUX1; | |
f078f209 | 2669 | |
f1dc5600 | 2670 | gpio_shift = (gpio % 6) * 5; |
f078f209 | 2671 | |
b2d70d49 MP |
2672 | if (AR_SREV_9280_20_OR_LATER(ah) || |
2673 | (addr != AR_GPIO_OUTPUT_MUX1)) { | |
f1dc5600 S |
2674 | REG_RMW(ah, addr, (type << gpio_shift), |
2675 | (0x1f << gpio_shift)); | |
f078f209 | 2676 | } else { |
f1dc5600 S |
2677 | tmp = REG_READ(ah, addr); |
2678 | tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); | |
2679 | tmp &= ~(0x1f << gpio_shift); | |
2680 | tmp |= (type << gpio_shift); | |
2681 | REG_WRITE(ah, addr, tmp); | |
f078f209 | 2682 | } |
f078f209 LR |
2683 | } |
2684 | ||
b2d70d49 MP |
2685 | /* BSP should set the corresponding MUX register correctly. |
2686 | */ | |
2687 | static void ath9k_hw_gpio_cfg_soc(struct ath_hw *ah, u32 gpio, bool out, | |
2688 | const char *label) | |
f078f209 | 2689 | { |
b2d70d49 MP |
2690 | if (ah->caps.gpio_requested & BIT(gpio)) |
2691 | return; | |
f078f209 | 2692 | |
b2d70d49 MP |
2693 | /* may be requested by BSP, free anyway */ |
2694 | gpio_free(gpio); | |
f078f209 | 2695 | |
b2d70d49 | 2696 | if (gpio_request_one(gpio, out ? GPIOF_OUT_INIT_LOW : GPIOF_IN, label)) |
88c1f4f6 | 2697 | return; |
f078f209 | 2698 | |
b2d70d49 | 2699 | ah->caps.gpio_requested |= BIT(gpio); |
f078f209 LR |
2700 | } |
2701 | ||
b2d70d49 MP |
2702 | static void ath9k_hw_gpio_cfg_wmac(struct ath_hw *ah, u32 gpio, bool out, |
2703 | u32 ah_signal_type) | |
f078f209 | 2704 | { |
b2d70d49 | 2705 | u32 gpio_set, gpio_shift = gpio; |
f078f209 | 2706 | |
88c1f4f6 | 2707 | if (AR_DEVID_7010(ah)) { |
b2d70d49 MP |
2708 | gpio_set = out ? |
2709 | AR7010_GPIO_OE_AS_OUTPUT : AR7010_GPIO_OE_AS_INPUT; | |
2710 | REG_RMW(ah, AR7010_GPIO_OE, gpio_set << gpio_shift, | |
2711 | AR7010_GPIO_OE_MASK << gpio_shift); | |
2712 | } else if (AR_SREV_SOC(ah)) { | |
2713 | gpio_set = out ? 1 : 0; | |
2714 | REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift, | |
2715 | gpio_set << gpio_shift); | |
2716 | } else { | |
2717 | gpio_shift = gpio << 1; | |
2718 | gpio_set = out ? | |
2719 | AR_GPIO_OE_OUT_DRV_ALL : AR_GPIO_OE_OUT_DRV_NO; | |
2720 | REG_RMW(ah, AR_GPIO_OE_OUT, gpio_set << gpio_shift, | |
2721 | AR_GPIO_OE_OUT_DRV << gpio_shift); | |
2722 | ||
2723 | if (out) | |
2724 | ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); | |
2725 | } | |
f078f209 LR |
2726 | } |
2727 | ||
b2d70d49 MP |
2728 | static void ath9k_hw_gpio_request(struct ath_hw *ah, u32 gpio, bool out, |
2729 | const char *label, u32 ah_signal_type) | |
f078f209 | 2730 | { |
b2d70d49 | 2731 | WARN_ON(gpio >= ah->caps.num_gpio_pins); |
f078f209 | 2732 | |
b2d70d49 MP |
2733 | if (BIT(gpio) & ah->caps.gpio_mask) |
2734 | ath9k_hw_gpio_cfg_wmac(ah, gpio, out, ah_signal_type); | |
2735 | else if (AR_SREV_SOC(ah)) | |
2736 | ath9k_hw_gpio_cfg_soc(ah, gpio, out, label); | |
2737 | else | |
2738 | WARN_ON(1); | |
2739 | } | |
f078f209 | 2740 | |
b2d70d49 MP |
2741 | void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label) |
2742 | { | |
2743 | ath9k_hw_gpio_request(ah, gpio, false, label, 0); | |
f078f209 | 2744 | } |
b2d70d49 | 2745 | EXPORT_SYMBOL(ath9k_hw_gpio_request_in); |
f078f209 | 2746 | |
b2d70d49 MP |
2747 | void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label, |
2748 | u32 ah_signal_type) | |
f078f209 | 2749 | { |
b2d70d49 MP |
2750 | ath9k_hw_gpio_request(ah, gpio, true, label, ah_signal_type); |
2751 | } | |
2752 | EXPORT_SYMBOL(ath9k_hw_gpio_request_out); | |
2753 | ||
2754 | void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio) | |
2755 | { | |
2756 | if (!AR_SREV_SOC(ah)) | |
88c1f4f6 | 2757 | return; |
b2d70d49 MP |
2758 | |
2759 | WARN_ON(gpio >= ah->caps.num_gpio_pins); | |
2760 | ||
2761 | if (ah->caps.gpio_requested & BIT(gpio)) { | |
2762 | gpio_free(gpio); | |
2763 | ah->caps.gpio_requested &= ~BIT(gpio); | |
88c1f4f6 | 2764 | } |
b2d70d49 MP |
2765 | } |
2766 | EXPORT_SYMBOL(ath9k_hw_gpio_free); | |
88c1f4f6 | 2767 | |
b2d70d49 MP |
2768 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) |
2769 | { | |
2770 | u32 val = 0xffffffff; | |
5b5fa355 | 2771 | |
b2d70d49 MP |
2772 | #define MS_REG_READ(x, y) \ |
2773 | (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & BIT(y)) | |
2774 | ||
2775 | WARN_ON(gpio >= ah->caps.num_gpio_pins); | |
2776 | ||
2777 | if (BIT(gpio) & ah->caps.gpio_mask) { | |
2778 | if (AR_SREV_9271(ah)) | |
2779 | val = MS_REG_READ(AR9271, gpio); | |
2780 | else if (AR_SREV_9287(ah)) | |
2781 | val = MS_REG_READ(AR9287, gpio); | |
2782 | else if (AR_SREV_9285(ah)) | |
2783 | val = MS_REG_READ(AR9285, gpio); | |
2784 | else if (AR_SREV_9280(ah)) | |
2785 | val = MS_REG_READ(AR928X, gpio); | |
2786 | else if (AR_DEVID_7010(ah)) | |
2787 | val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio); | |
2788 | else if (AR_SREV_9300_20_OR_LATER(ah)) | |
2789 | val = REG_READ(ah, AR_GPIO_IN) & BIT(gpio); | |
2790 | else | |
2791 | val = MS_REG_READ(AR, gpio); | |
2792 | } else if (BIT(gpio) & ah->caps.gpio_requested) { | |
2793 | val = gpio_get_value(gpio) & BIT(gpio); | |
2794 | } else { | |
2795 | WARN_ON(1); | |
2796 | } | |
2797 | ||
2798 | return val; | |
f078f209 | 2799 | } |
b2d70d49 | 2800 | EXPORT_SYMBOL(ath9k_hw_gpio_get); |
f078f209 | 2801 | |
b2d70d49 | 2802 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) |
61b559de | 2803 | { |
b2d70d49 | 2804 | WARN_ON(gpio >= ah->caps.num_gpio_pins); |
61b559de | 2805 | |
b2d70d49 MP |
2806 | if (AR_DEVID_7010(ah) || AR_SREV_9271(ah)) |
2807 | val = !val; | |
2808 | else | |
2809 | val = !!val; | |
2810 | ||
2811 | if (BIT(gpio) & ah->caps.gpio_mask) { | |
2812 | u32 out_addr = AR_DEVID_7010(ah) ? | |
2813 | AR7010_GPIO_OUT : AR_GPIO_IN_OUT; | |
2814 | ||
2815 | REG_RMW(ah, out_addr, val << gpio, BIT(gpio)); | |
2816 | } else if (BIT(gpio) & ah->caps.gpio_requested) { | |
2817 | gpio_set_value(gpio, val); | |
2818 | } else { | |
2819 | WARN_ON(1); | |
2820 | } | |
61b559de | 2821 | } |
b2d70d49 | 2822 | EXPORT_SYMBOL(ath9k_hw_set_gpio); |
61b559de | 2823 | |
cbe61d8a | 2824 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) |
f078f209 | 2825 | { |
f1dc5600 | 2826 | REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); |
f078f209 | 2827 | } |
7322fd19 | 2828 | EXPORT_SYMBOL(ath9k_hw_setantenna); |
f078f209 | 2829 | |
f1dc5600 S |
2830 | /*********************/ |
2831 | /* General Operation */ | |
2832 | /*********************/ | |
2833 | ||
cbe61d8a | 2834 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah) |
f078f209 | 2835 | { |
f1dc5600 S |
2836 | u32 bits = REG_READ(ah, AR_RX_FILTER); |
2837 | u32 phybits = REG_READ(ah, AR_PHY_ERR); | |
f078f209 | 2838 | |
f1dc5600 S |
2839 | if (phybits & AR_PHY_ERR_RADAR) |
2840 | bits |= ATH9K_RX_FILTER_PHYRADAR; | |
2841 | if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) | |
2842 | bits |= ATH9K_RX_FILTER_PHYERR; | |
dc2222a8 | 2843 | |
f1dc5600 | 2844 | return bits; |
f078f209 | 2845 | } |
7322fd19 | 2846 | EXPORT_SYMBOL(ath9k_hw_getrxfilter); |
f078f209 | 2847 | |
cbe61d8a | 2848 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) |
f078f209 | 2849 | { |
f1dc5600 | 2850 | u32 phybits; |
f078f209 | 2851 | |
7d0d0df0 S |
2852 | ENABLE_REGWRITE_BUFFER(ah); |
2853 | ||
7ea310be S |
2854 | REG_WRITE(ah, AR_RX_FILTER, bits); |
2855 | ||
f1dc5600 S |
2856 | phybits = 0; |
2857 | if (bits & ATH9K_RX_FILTER_PHYRADAR) | |
2858 | phybits |= AR_PHY_ERR_RADAR; | |
2859 | if (bits & ATH9K_RX_FILTER_PHYERR) | |
2860 | phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; | |
2861 | REG_WRITE(ah, AR_PHY_ERR, phybits); | |
f078f209 | 2862 | |
f1dc5600 | 2863 | if (phybits) |
ca7a4deb | 2864 | REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); |
f1dc5600 | 2865 | else |
ca7a4deb | 2866 | REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); |
7d0d0df0 S |
2867 | |
2868 | REGWRITE_BUFFER_FLUSH(ah); | |
f1dc5600 | 2869 | } |
7322fd19 | 2870 | EXPORT_SYMBOL(ath9k_hw_setrxfilter); |
f078f209 | 2871 | |
cbe61d8a | 2872 | bool ath9k_hw_phy_disable(struct ath_hw *ah) |
f1dc5600 | 2873 | { |
99922a45 RM |
2874 | if (ath9k_hw_mci_is_enabled(ah)) |
2875 | ar9003_mci_bt_gain_ctrl(ah); | |
2876 | ||
63a75b91 SB |
2877 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) |
2878 | return false; | |
2879 | ||
2880 | ath9k_hw_init_pll(ah, NULL); | |
8efa7a81 | 2881 | ah->htc_reset_init = true; |
63a75b91 | 2882 | return true; |
f1dc5600 | 2883 | } |
7322fd19 | 2884 | EXPORT_SYMBOL(ath9k_hw_phy_disable); |
f078f209 | 2885 | |
cbe61d8a | 2886 | bool ath9k_hw_disable(struct ath_hw *ah) |
f1dc5600 | 2887 | { |
9ecdef4b | 2888 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
f1dc5600 | 2889 | return false; |
f078f209 | 2890 | |
63a75b91 SB |
2891 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) |
2892 | return false; | |
2893 | ||
2894 | ath9k_hw_init_pll(ah, NULL); | |
2895 | return true; | |
f078f209 | 2896 | } |
7322fd19 | 2897 | EXPORT_SYMBOL(ath9k_hw_disable); |
f078f209 | 2898 | |
ca2c68cc FF |
2899 | static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) |
2900 | { | |
2901 | enum eeprom_param gain_param; | |
2902 | ||
2903 | if (IS_CHAN_2GHZ(chan)) | |
2904 | gain_param = EEP_ANTENNA_GAIN_2G; | |
2905 | else | |
2906 | gain_param = EEP_ANTENNA_GAIN_5G; | |
2907 | ||
2908 | return ah->eep_ops->get_eeprom(ah, gain_param); | |
2909 | } | |
2910 | ||
64ea57d0 GJ |
2911 | void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, |
2912 | bool test) | |
ca2c68cc FF |
2913 | { |
2914 | struct ath_regulatory *reg = ath9k_hw_regulatory(ah); | |
2915 | struct ieee80211_channel *channel; | |
2916 | int chan_pwr, new_pwr, max_gain; | |
2917 | int ant_gain, ant_reduction = 0; | |
2918 | ||
2919 | if (!chan) | |
2920 | return; | |
2921 | ||
2922 | channel = chan->chan; | |
2923 | chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); | |
2924 | new_pwr = min_t(int, chan_pwr, reg->power_limit); | |
2925 | max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; | |
2926 | ||
2927 | ant_gain = get_antenna_gain(ah, chan); | |
2928 | if (ant_gain > max_gain) | |
2929 | ant_reduction = ant_gain - max_gain; | |
2930 | ||
2931 | ah->eep_ops->set_txpower(ah, chan, | |
2932 | ath9k_regd_get_ctl(reg, chan), | |
64ea57d0 | 2933 | ant_reduction, new_pwr, test); |
ca2c68cc FF |
2934 | } |
2935 | ||
de40f316 | 2936 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) |
f078f209 | 2937 | { |
ca2c68cc | 2938 | struct ath_regulatory *reg = ath9k_hw_regulatory(ah); |
2660b81a | 2939 | struct ath9k_channel *chan = ah->curchan; |
5f8e077c | 2940 | struct ieee80211_channel *channel = chan->chan; |
9c204b46 | 2941 | |
48ef5c42 | 2942 | reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); |
9c204b46 | 2943 | if (test) |
ca2c68cc | 2944 | channel->max_power = MAX_RATE_POWER / 2; |
f078f209 | 2945 | |
64ea57d0 | 2946 | ath9k_hw_apply_txpower(ah, chan, test); |
6f255425 | 2947 | |
ca2c68cc FF |
2948 | if (test) |
2949 | channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); | |
6f255425 | 2950 | } |
7322fd19 | 2951 | EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); |
6f255425 | 2952 | |
cbe61d8a | 2953 | void ath9k_hw_setopmode(struct ath_hw *ah) |
f078f209 | 2954 | { |
2660b81a | 2955 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
f078f209 | 2956 | } |
7322fd19 | 2957 | EXPORT_SYMBOL(ath9k_hw_setopmode); |
f078f209 | 2958 | |
cbe61d8a | 2959 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) |
f078f209 | 2960 | { |
f1dc5600 S |
2961 | REG_WRITE(ah, AR_MCAST_FIL0, filter0); |
2962 | REG_WRITE(ah, AR_MCAST_FIL1, filter1); | |
f078f209 | 2963 | } |
7322fd19 | 2964 | EXPORT_SYMBOL(ath9k_hw_setmcastfilter); |
f078f209 | 2965 | |
f2b2143e | 2966 | void ath9k_hw_write_associd(struct ath_hw *ah) |
f078f209 | 2967 | { |
1510718d LR |
2968 | struct ath_common *common = ath9k_hw_common(ah); |
2969 | ||
2970 | REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); | |
2971 | REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | | |
2972 | ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); | |
f078f209 | 2973 | } |
7322fd19 | 2974 | EXPORT_SYMBOL(ath9k_hw_write_associd); |
f078f209 | 2975 | |
1c0fc65e BP |
2976 | #define ATH9K_MAX_TSF_READ 10 |
2977 | ||
cbe61d8a | 2978 | u64 ath9k_hw_gettsf64(struct ath_hw *ah) |
f078f209 | 2979 | { |
1c0fc65e BP |
2980 | u32 tsf_lower, tsf_upper1, tsf_upper2; |
2981 | int i; | |
2982 | ||
2983 | tsf_upper1 = REG_READ(ah, AR_TSF_U32); | |
2984 | for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { | |
2985 | tsf_lower = REG_READ(ah, AR_TSF_L32); | |
2986 | tsf_upper2 = REG_READ(ah, AR_TSF_U32); | |
2987 | if (tsf_upper2 == tsf_upper1) | |
2988 | break; | |
2989 | tsf_upper1 = tsf_upper2; | |
2990 | } | |
f078f209 | 2991 | |
1c0fc65e | 2992 | WARN_ON( i == ATH9K_MAX_TSF_READ ); |
f078f209 | 2993 | |
1c0fc65e | 2994 | return (((u64)tsf_upper1 << 32) | tsf_lower); |
f1dc5600 | 2995 | } |
7322fd19 | 2996 | EXPORT_SYMBOL(ath9k_hw_gettsf64); |
f078f209 | 2997 | |
cbe61d8a | 2998 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) |
27abe060 | 2999 | { |
27abe060 | 3000 | REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); |
b9a16197 | 3001 | REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); |
27abe060 | 3002 | } |
7322fd19 | 3003 | EXPORT_SYMBOL(ath9k_hw_settsf64); |
27abe060 | 3004 | |
cbe61d8a | 3005 | void ath9k_hw_reset_tsf(struct ath_hw *ah) |
f1dc5600 | 3006 | { |
f9b604f6 GJ |
3007 | if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, |
3008 | AH_TSF_WRITE_TIMEOUT)) | |
d2182b69 | 3009 | ath_dbg(ath9k_hw_common(ah), RESET, |
226afe68 | 3010 | "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); |
f9b604f6 | 3011 | |
f1dc5600 S |
3012 | REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); |
3013 | } | |
7322fd19 | 3014 | EXPORT_SYMBOL(ath9k_hw_reset_tsf); |
f078f209 | 3015 | |
60ca9f87 | 3016 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) |
f1dc5600 | 3017 | { |
60ca9f87 | 3018 | if (set) |
2660b81a | 3019 | ah->misc_mode |= AR_PCU_TX_ADD_TSF; |
f1dc5600 | 3020 | else |
2660b81a | 3021 | ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; |
f1dc5600 | 3022 | } |
7322fd19 | 3023 | EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); |
f078f209 | 3024 | |
e4744ec7 | 3025 | void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan) |
f1dc5600 S |
3026 | { |
3027 | u32 macmode; | |
3028 | ||
e4744ec7 | 3029 | if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca) |
f1dc5600 S |
3030 | macmode = AR_2040_JOINED_RX_CLEAR; |
3031 | else | |
3032 | macmode = 0; | |
f078f209 | 3033 | |
f1dc5600 | 3034 | REG_WRITE(ah, AR_2040_MODE, macmode); |
f078f209 | 3035 | } |
ff155a45 VT |
3036 | |
3037 | /* HW Generic timers configuration */ | |
3038 | ||
3039 | static const struct ath_gen_timer_configuration gen_tmr_configuration[] = | |
3040 | { | |
3041 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3042 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3043 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3044 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3045 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3046 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3047 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3048 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
3049 | {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, | |
3050 | {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, | |
3051 | AR_NDP2_TIMER_MODE, 0x0002}, | |
3052 | {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, | |
3053 | AR_NDP2_TIMER_MODE, 0x0004}, | |
3054 | {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, | |
3055 | AR_NDP2_TIMER_MODE, 0x0008}, | |
3056 | {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, | |
3057 | AR_NDP2_TIMER_MODE, 0x0010}, | |
3058 | {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, | |
3059 | AR_NDP2_TIMER_MODE, 0x0020}, | |
3060 | {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, | |
3061 | AR_NDP2_TIMER_MODE, 0x0040}, | |
3062 | {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, | |
3063 | AR_NDP2_TIMER_MODE, 0x0080} | |
3064 | }; | |
3065 | ||
3066 | /* HW generic timer primitives */ | |
3067 | ||
dd347f2f | 3068 | u32 ath9k_hw_gettsf32(struct ath_hw *ah) |
ff155a45 VT |
3069 | { |
3070 | return REG_READ(ah, AR_TSF_L32); | |
3071 | } | |
dd347f2f | 3072 | EXPORT_SYMBOL(ath9k_hw_gettsf32); |
ff155a45 | 3073 | |
f4c34af4 SM |
3074 | void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah) |
3075 | { | |
3076 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
3077 | ||
3078 | if (timer_table->tsf2_enabled) { | |
3079 | REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN); | |
3080 | REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE); | |
3081 | } | |
3082 | } | |
3083 | ||
ff155a45 VT |
3084 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, |
3085 | void (*trigger)(void *), | |
3086 | void (*overflow)(void *), | |
3087 | void *arg, | |
3088 | u8 timer_index) | |
3089 | { | |
3090 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
3091 | struct ath_gen_timer *timer; | |
3092 | ||
c67ce339 | 3093 | if ((timer_index < AR_FIRST_NDP_TIMER) || |
f4c34af4 SM |
3094 | (timer_index >= ATH_MAX_GEN_TIMER)) |
3095 | return NULL; | |
3096 | ||
3097 | if ((timer_index > AR_FIRST_NDP_TIMER) && | |
3098 | !AR_SREV_9300_20_OR_LATER(ah)) | |
c67ce339 FF |
3099 | return NULL; |
3100 | ||
ff155a45 | 3101 | timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); |
14f8dc49 | 3102 | if (timer == NULL) |
ff155a45 | 3103 | return NULL; |
ff155a45 VT |
3104 | |
3105 | /* allocate a hardware generic timer slot */ | |
3106 | timer_table->timers[timer_index] = timer; | |
3107 | timer->index = timer_index; | |
3108 | timer->trigger = trigger; | |
3109 | timer->overflow = overflow; | |
3110 | timer->arg = arg; | |
3111 | ||
f4c34af4 SM |
3112 | if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) { |
3113 | timer_table->tsf2_enabled = true; | |
3114 | ath9k_hw_gen_timer_start_tsf2(ah); | |
3115 | } | |
3116 | ||
ff155a45 VT |
3117 | return timer; |
3118 | } | |
7322fd19 | 3119 | EXPORT_SYMBOL(ath_gen_timer_alloc); |
ff155a45 | 3120 | |
cd9bf689 LR |
3121 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
3122 | struct ath_gen_timer *timer, | |
c67ce339 | 3123 | u32 timer_next, |
cd9bf689 | 3124 | u32 timer_period) |
ff155a45 VT |
3125 | { |
3126 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
c67ce339 | 3127 | u32 mask = 0; |
788f6875 | 3128 | |
c67ce339 | 3129 | timer_table->timer_mask |= BIT(timer->index); |
ff155a45 | 3130 | |
ff155a45 VT |
3131 | /* |
3132 | * Program generic timer registers | |
3133 | */ | |
3134 | REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, | |
3135 | timer_next); | |
3136 | REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, | |
3137 | timer_period); | |
3138 | REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, | |
3139 | gen_tmr_configuration[timer->index].mode_mask); | |
3140 | ||
a4a2954f | 3141 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { |
2577c6e8 | 3142 | /* |
423e38e8 | 3143 | * Starting from AR9462, each generic timer can select which tsf |
2577c6e8 SB |
3144 | * to use. But we still follow the old rule, 0 - 7 use tsf and |
3145 | * 8 - 15 use tsf2. | |
3146 | */ | |
3147 | if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) | |
3148 | REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, | |
3149 | (1 << timer->index)); | |
3150 | else | |
3151 | REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, | |
3152 | (1 << timer->index)); | |
3153 | } | |
3154 | ||
c67ce339 FF |
3155 | if (timer->trigger) |
3156 | mask |= SM(AR_GENTMR_BIT(timer->index), | |
3157 | AR_IMR_S5_GENTIMER_TRIG); | |
3158 | if (timer->overflow) | |
3159 | mask |= SM(AR_GENTMR_BIT(timer->index), | |
3160 | AR_IMR_S5_GENTIMER_THRESH); | |
3161 | ||
3162 | REG_SET_BIT(ah, AR_IMR_S5, mask); | |
3163 | ||
3164 | if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { | |
3165 | ah->imask |= ATH9K_INT_GENTIMER; | |
3166 | ath9k_hw_set_interrupts(ah); | |
3167 | } | |
ff155a45 | 3168 | } |
7322fd19 | 3169 | EXPORT_SYMBOL(ath9k_hw_gen_timer_start); |
ff155a45 | 3170 | |
cd9bf689 | 3171 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) |
ff155a45 VT |
3172 | { |
3173 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
3174 | ||
ff155a45 VT |
3175 | /* Clear generic timer enable bits. */ |
3176 | REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, | |
3177 | gen_tmr_configuration[timer->index].mode_mask); | |
3178 | ||
b7f59766 SM |
3179 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { |
3180 | /* | |
3181 | * Need to switch back to TSF if it was using TSF2. | |
3182 | */ | |
3183 | if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) { | |
3184 | REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, | |
3185 | (1 << timer->index)); | |
3186 | } | |
3187 | } | |
3188 | ||
ff155a45 VT |
3189 | /* Disable both trigger and thresh interrupt masks */ |
3190 | REG_CLR_BIT(ah, AR_IMR_S5, | |
3191 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | | |
3192 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); | |
3193 | ||
c67ce339 FF |
3194 | timer_table->timer_mask &= ~BIT(timer->index); |
3195 | ||
3196 | if (timer_table->timer_mask == 0) { | |
3197 | ah->imask &= ~ATH9K_INT_GENTIMER; | |
3198 | ath9k_hw_set_interrupts(ah); | |
3199 | } | |
ff155a45 | 3200 | } |
7322fd19 | 3201 | EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); |
ff155a45 VT |
3202 | |
3203 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) | |
3204 | { | |
3205 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
3206 | ||
3207 | /* free the hardware generic timer slot */ | |
3208 | timer_table->timers[timer->index] = NULL; | |
3209 | kfree(timer); | |
3210 | } | |
7322fd19 | 3211 | EXPORT_SYMBOL(ath_gen_timer_free); |
ff155a45 VT |
3212 | |
3213 | /* | |
3214 | * Generic Timer Interrupts handling | |
3215 | */ | |
3216 | void ath_gen_timer_isr(struct ath_hw *ah) | |
3217 | { | |
3218 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
3219 | struct ath_gen_timer *timer; | |
c67ce339 FF |
3220 | unsigned long trigger_mask, thresh_mask; |
3221 | unsigned int index; | |
ff155a45 VT |
3222 | |
3223 | /* get hardware generic timer interrupt status */ | |
3224 | trigger_mask = ah->intr_gen_timer_trigger; | |
3225 | thresh_mask = ah->intr_gen_timer_thresh; | |
c67ce339 FF |
3226 | trigger_mask &= timer_table->timer_mask; |
3227 | thresh_mask &= timer_table->timer_mask; | |
ff155a45 | 3228 | |
c67ce339 | 3229 | for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) { |
ff155a45 | 3230 | timer = timer_table->timers[index]; |
c67ce339 FF |
3231 | if (!timer) |
3232 | continue; | |
3233 | if (!timer->overflow) | |
3234 | continue; | |
a6a172b2 FF |
3235 | |
3236 | trigger_mask &= ~BIT(index); | |
ff155a45 VT |
3237 | timer->overflow(timer->arg); |
3238 | } | |
3239 | ||
c67ce339 | 3240 | for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) { |
ff155a45 | 3241 | timer = timer_table->timers[index]; |
c67ce339 FF |
3242 | if (!timer) |
3243 | continue; | |
3244 | if (!timer->trigger) | |
3245 | continue; | |
ff155a45 VT |
3246 | timer->trigger(timer->arg); |
3247 | } | |
3248 | } | |
7322fd19 | 3249 | EXPORT_SYMBOL(ath_gen_timer_isr); |
2da4f01a | 3250 | |
05020d23 S |
3251 | /********/ |
3252 | /* HTC */ | |
3253 | /********/ | |
3254 | ||
2da4f01a LR |
3255 | static struct { |
3256 | u32 version; | |
3257 | const char * name; | |
3258 | } ath_mac_bb_names[] = { | |
3259 | /* Devices with external radios */ | |
3260 | { AR_SREV_VERSION_5416_PCI, "5416" }, | |
3261 | { AR_SREV_VERSION_5416_PCIE, "5418" }, | |
3262 | { AR_SREV_VERSION_9100, "9100" }, | |
3263 | { AR_SREV_VERSION_9160, "9160" }, | |
3264 | /* Single-chip solutions */ | |
3265 | { AR_SREV_VERSION_9280, "9280" }, | |
3266 | { AR_SREV_VERSION_9285, "9285" }, | |
11158472 LR |
3267 | { AR_SREV_VERSION_9287, "9287" }, |
3268 | { AR_SREV_VERSION_9271, "9271" }, | |
ec83903e | 3269 | { AR_SREV_VERSION_9300, "9300" }, |
2c8e5937 | 3270 | { AR_SREV_VERSION_9330, "9330" }, |
397e5d5b | 3271 | { AR_SREV_VERSION_9340, "9340" }, |
8f06ca2c | 3272 | { AR_SREV_VERSION_9485, "9485" }, |
423e38e8 | 3273 | { AR_SREV_VERSION_9462, "9462" }, |
485124cb | 3274 | { AR_SREV_VERSION_9550, "9550" }, |
77fac465 | 3275 | { AR_SREV_VERSION_9565, "9565" }, |
c08148bb | 3276 | { AR_SREV_VERSION_9531, "9531" }, |
1165dd90 | 3277 | { AR_SREV_VERSION_9561, "9561" }, |
2da4f01a LR |
3278 | }; |
3279 | ||
3280 | /* For devices with external radios */ | |
3281 | static struct { | |
3282 | u16 version; | |
3283 | const char * name; | |
3284 | } ath_rf_names[] = { | |
3285 | { 0, "5133" }, | |
3286 | { AR_RAD5133_SREV_MAJOR, "5133" }, | |
3287 | { AR_RAD5122_SREV_MAJOR, "5122" }, | |
3288 | { AR_RAD2133_SREV_MAJOR, "2133" }, | |
3289 | { AR_RAD2122_SREV_MAJOR, "2122" } | |
3290 | }; | |
3291 | ||
3292 | /* | |
3293 | * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. | |
3294 | */ | |
f934c4d9 | 3295 | static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) |
2da4f01a LR |
3296 | { |
3297 | int i; | |
3298 | ||
3299 | for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { | |
3300 | if (ath_mac_bb_names[i].version == mac_bb_version) { | |
3301 | return ath_mac_bb_names[i].name; | |
3302 | } | |
3303 | } | |
3304 | ||
3305 | return "????"; | |
3306 | } | |
2da4f01a LR |
3307 | |
3308 | /* | |
3309 | * Return the RF name. "????" is returned if the RF is unknown. | |
3310 | * Used for devices with external radios. | |
3311 | */ | |
f934c4d9 | 3312 | static const char *ath9k_hw_rf_name(u16 rf_version) |
2da4f01a LR |
3313 | { |
3314 | int i; | |
3315 | ||
3316 | for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { | |
3317 | if (ath_rf_names[i].version == rf_version) { | |
3318 | return ath_rf_names[i].name; | |
3319 | } | |
3320 | } | |
3321 | ||
3322 | return "????"; | |
3323 | } | |
f934c4d9 LR |
3324 | |
3325 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) | |
3326 | { | |
3327 | int used; | |
3328 | ||
3329 | /* chipsets >= AR9280 are single-chip */ | |
7a37081e | 3330 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
5e88ba62 ZK |
3331 | used = scnprintf(hw_name, len, |
3332 | "Atheros AR%s Rev:%x", | |
3333 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), | |
3334 | ah->hw_version.macRev); | |
f934c4d9 LR |
3335 | } |
3336 | else { | |
5e88ba62 ZK |
3337 | used = scnprintf(hw_name, len, |
3338 | "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", | |
3339 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), | |
3340 | ah->hw_version.macRev, | |
3341 | ath9k_hw_rf_name((ah->hw_version.analog5GhzRev | |
3342 | & AR_RADIO_SREV_MAJOR)), | |
3343 | ah->hw_version.phyRev); | |
f934c4d9 LR |
3344 | } |
3345 | ||
3346 | hw_name[used] = '\0'; | |
3347 | } | |
3348 | EXPORT_SYMBOL(ath9k_hw_name); |