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ath9k_hw: Enable AR9340 support
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
b3950e6a 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
f078f209
LR		 19#include <asm/unaligned.h>
20
af03abec 21#include "hw.h"
d70357d5 22#include "hw-ops.h"
cfe8cba9 23#include "rc.h"
b622a720 24#include "ar9003_mac.h"
f078f209 25
cbe61d8a 26static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 27
7322fd19
LR		 28MODULE_AUTHOR("Atheros Communications");
29MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31MODULE_LICENSE("Dual BSD/GPL");
32
33static int __init ath9k_init(void)
34{
35 return 0;
36}
37module_init(ath9k_init);
38
39static void __exit ath9k_exit(void)
40{
41 return;
42}
43module_exit(ath9k_exit);
44
d70357d5
LR		 45/* Private hardware callbacks */
46
47static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48{
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50}
51
52static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53{
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55}
56
64773964
LR		 57static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
59{
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
61}
62
991312d8
LR		 63static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
64{
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
66 return;
67
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
69}
70
e36b27af
LR		 71static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
72{
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
78}
79
f1dc5600
S		 80/********************/
81/* Helper Functions */
82/********************/
f078f209 83
dfdac8ac 84static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 85{
b002a4a9 86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
dfdac8ac
FF		 87 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate;
cbe61d8a 89
2660b81a 90 if (!ah->curchan) /* should really check for CCK instead */
dfdac8ac
FF		 91 clockrate = ATH9K_CLOCK_RATE_CCK;
92 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
93 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
94 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
95 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 96 else
dfdac8ac
FF		 97 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
98
99 if (conf_is_ht40(conf))
100 clockrate *= 2;
101
102 common->clockrate = clockrate;
f1dc5600
S		 103}
104
cbe61d8a 105static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 106{
dfdac8ac 107 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 108
dfdac8ac 109 return usecs * common->clockrate;
f1dc5600 110}
f078f209 111
0caa7b14 112bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 113{
114 int i;
115
0caa7b14
S		 116 BUG_ON(timeout < AH_TIME_QUANTUM);
117
118 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 119 if ((REG_READ(ah, reg) & mask) == val)
120 return true;
121
122 udelay(AH_TIME_QUANTUM);
123 }
04bd4638 124
226afe68
JP		 125 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
126 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
127 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 128
f1dc5600 129 return false;
f078f209 130}
7322fd19 131EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 132
a9b6b256
FF		 133void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
134 int column, unsigned int *writecnt)
135{
136 int r;
137
138 ENABLE_REGWRITE_BUFFER(ah);
139 for (r = 0; r < array->ia_rows; r++) {
140 REG_WRITE(ah, INI_RA(array, r, 0),
141 INI_RA(array, r, column));
142 DO_DELAY(*writecnt);
143 }
144 REGWRITE_BUFFER_FLUSH(ah);
145}
146
f078f209
LR		 147u32 ath9k_hw_reverse_bits(u32 val, u32 n)
148{
149 u32 retval;
150 int i;
151
152 for (i = 0, retval = 0; i < n; i++) {
153 retval = (retval << 1) | (val & 1);
154 val >>= 1;
155 }
156 return retval;
157}
158
cbe61d8a 159u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 160 u8 phy, int kbps,
f1dc5600
S		 161 u32 frameLen, u16 rateix,
162 bool shortPreamble)
f078f209 163{
f1dc5600 164 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 165
f1dc5600
S		 166 if (kbps == 0)
167 return 0;
f078f209 168
545750d3 169 switch (phy) {
46d14a58 170 case WLAN_RC_PHY_CCK:
f1dc5600 171 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 172 if (shortPreamble)
f1dc5600
S		 173 phyTime >>= 1;
174 numBits = frameLen << 3;
175 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
176 break;
46d14a58 177 case WLAN_RC_PHY_OFDM:
2660b81a 178 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 179 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
180 numBits = OFDM_PLCP_BITS + (frameLen << 3);
181 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
182 txTime = OFDM_SIFS_TIME_QUARTER
183 + OFDM_PREAMBLE_TIME_QUARTER
184 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 185 } else if (ah->curchan &&
186 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 187 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
188 numBits = OFDM_PLCP_BITS + (frameLen << 3);
189 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
190 txTime = OFDM_SIFS_TIME_HALF +
191 OFDM_PREAMBLE_TIME_HALF
192 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
193 } else {
194 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
195 numBits = OFDM_PLCP_BITS + (frameLen << 3);
196 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
197 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
198 + (numSymbols * OFDM_SYMBOL_TIME);
199 }
200 break;
201 default:
3800276a
JP		 202 ath_err(ath9k_hw_common(ah),
203 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 204 txTime = 0;
205 break;
206 }
f078f209 207
f1dc5600
S		 208 return txTime;
209}
7322fd19 210EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 211
cbe61d8a 212void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 213 struct ath9k_channel *chan,
214 struct chan_centers *centers)
f078f209 215{
f1dc5600 216 int8_t extoff;
f078f209 217
f1dc5600
S		 218 if (!IS_CHAN_HT40(chan)) {
219 centers->ctl_center = centers->ext_center =
220 centers->synth_center = chan->channel;
221 return;
f078f209 222 }
f078f209 223
f1dc5600
S		 224 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
225 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
226 centers->synth_center =
227 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
228 extoff = 1;
229 } else {
230 centers->synth_center =
231 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
232 extoff = -1;
233 }
f078f209 234
f1dc5600
S		 235 centers->ctl_center =
236 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 237 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 238 centers->ext_center =
6420014c 239 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 240}
241
f1dc5600
S		 242/******************/
243/* Chip Revisions */
244/******************/
245
cbe61d8a 246static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 247{
f1dc5600 248 u32 val;
f078f209 249
ecb1d385
VT		 250 switch (ah->hw_version.devid) {
251 case AR5416_AR9100_DEVID:
252 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
253 break;
254 case AR9300_DEVID_AR9340:
255 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
256 val = REG_READ(ah, AR_SREV);
257 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
258 return;
259 }
260
f1dc5600 261 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 262
f1dc5600
S		 263 if (val == 0xFF) {
264 val = REG_READ(ah, AR_SREV);
d535a42a
S		 265 ah->hw_version.macVersion =
266 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
267 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 268 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 269 } else {
270 if (!AR_SREV_9100(ah))
d535a42a 271 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 272
d535a42a 273 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 274
d535a42a 275 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 276 ah->is_pciexpress = true;
f1dc5600 277 }
f078f209
LR		 278}
279
f1dc5600
S		 280/************************************/
281/* HW Attach, Detach, Init Routines */
282/************************************/
283
cbe61d8a 284static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 285{
040b74f7 286 if (!AR_SREV_5416(ah))
f1dc5600 287 return;
f078f209 288
f1dc5600
S		 289 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
296 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
297 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 298
f1dc5600 299 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 300}
301
1f3f0618 302/* This should work for all families including legacy */
cbe61d8a 303static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 304{
c46917bb 305 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 306 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 307 u32 regHold[2];
07b2fa5a
JP		 308 static const u32 patternData[4] = {
309 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
310 };
1f3f0618 311 int i, j, loop_max;
f078f209 312
1f3f0618
SB		 313 if (!AR_SREV_9300_20_OR_LATER(ah)) {
314 loop_max = 2;
315 regAddr[1] = AR_PHY_BASE + (8 << 2);
316 } else
317 loop_max = 1;
318
319 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 320 u32 addr = regAddr[i];
321 u32 wrData, rdData;
f078f209 322
f1dc5600
S		 323 regHold[i] = REG_READ(ah, addr);
324 for (j = 0; j < 0x100; j++) {
325 wrData = (j << 16) | j;
326 REG_WRITE(ah, addr, wrData);
327 rdData = REG_READ(ah, addr);
328 if (rdData != wrData) {
3800276a
JP		 329 ath_err(common,
330 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
331 addr, wrData, rdData);
f1dc5600
S		 332 return false;
333 }
334 }
335 for (j = 0; j < 4; j++) {
336 wrData = patternData[j];
337 REG_WRITE(ah, addr, wrData);
338 rdData = REG_READ(ah, addr);
339 if (wrData != rdData) {
3800276a
JP		 340 ath_err(common,
341 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
342 addr, wrData, rdData);
f1dc5600
S		 343 return false;
344 }
f078f209 345 }
f1dc5600 346 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 347 }
f1dc5600 348 udelay(100);
cbe61d8a 349
f078f209
LR		 350 return true;
351}
352
b8b0f377 353static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 354{
355 int i;
f078f209 356
2660b81a
S		 357 ah->config.dma_beacon_response_time = 2;
358 ah->config.sw_beacon_response_time = 10;
359 ah->config.additional_swba_backoff = 0;
360 ah->config.ack_6mb = 0x0;
361 ah->config.cwm_ignore_extcca = 0;
362 ah->config.pcie_powersave_enable = 0;
2660b81a 363 ah->config.pcie_clock_req = 0;
2660b81a
S		 364 ah->config.pcie_waen = 0;
365 ah->config.analog_shiftreg = 1;
03c72518 366 ah->config.enable_ani = true;
f078f209 367
f1dc5600 368 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 369 ah->config.spurchans[i][0] = AR_NO_SPUR;
370 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 371 }
372
6f481010
LR		 373 /* PAPRD needs some more work to be enabled */
374 ah->config.paprd_disable = 1;
375
0ce024cb 376 ah->config.rx_intr_mitigation = true;
6a0ec30a 377 ah->config.pcieSerDesWrite = true;
6158425b
LR		 378
379 /*
380 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
381 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
382 * This means we use it for all AR5416 devices, and the few
383 * minor PCI AR9280 devices out there.
384 *
385 * Serialization is required because these devices do not handle
386 * well the case of two concurrent reads/writes due to the latency
387 * involved. During one read/write another read/write can be issued
388 * on another CPU while the previous read/write may still be working
389 * on our hardware, if we hit this case the hardware poops in a loop.
390 * We prevent this by serializing reads and writes.
391 *
392 * This issue is not present on PCI-Express devices or pre-AR5416
393 * devices (legacy, 802.11abg).
394 */
395 if (num_possible_cpus() > 1)
2d6a5e95 396 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 397}
398
50aca25b 399static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 400{
608b88cb
LR		 401 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
402
403 regulatory->country_code = CTRY_DEFAULT;
404 regulatory->power_limit = MAX_RATE_POWER;
405 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
406
d535a42a 407 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 408 ah->hw_version.subvendorid = 0;
f078f209 409
2660b81a 410 ah->atim_window = 0;
16f2411f
FF		 411 ah->sta_id1_defaults =
412 AR_STA_ID1_CRPT_MIC_ENABLE |
413 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 414 if (AR_SREV_9100(ah))
415 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
2660b81a 416 ah->enable_32kHz_clock = DONT_USE_32KHZ;
4357c6bf 417 ah->slottime = 20;
2660b81a 418 ah->globaltxtimeout = (u32) -1;
cbdec975 419 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 420}
421
cbe61d8a 422static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 423{
1510718d 424 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 425 u32 sum;
426 int i;
427 u16 eeval;
07b2fa5a 428 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 429
430 sum = 0;
431 for (i = 0; i < 3; i++) {
49101676 432 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 433 sum += eeval;
1510718d
LR		 434 common->macaddr[2 * i] = eeval >> 8;
435 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 436 }
d8baa939 437 if (sum == 0 || sum == 0xffff * 3)
f078f209 438 return -EADDRNOTAVAIL;
f078f209
LR		 439
440 return 0;
441}
442
f637cfd6 443static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 444{
6cae913d 445 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 446 int ecode;
f078f209 447
6cae913d 448 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 449 if (!ath9k_hw_chip_test(ah))
450 return -ENODEV;
451 }
f078f209 452
ebd5a14a
LR		 453 if (!AR_SREV_9300_20_OR_LATER(ah)) {
454 ecode = ar9002_hw_rf_claim(ah);
455 if (ecode != 0)
456 return ecode;
457 }
f078f209 458
f637cfd6 459 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 460 if (ecode != 0)
461 return ecode;
7d01b221 462
226afe68
JP		 463 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
464 "Eeprom VER: %d, REV: %d\n",
465 ah->eep_ops->get_eeprom_ver(ah),
466 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 467
8fe65368
LR		 468 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
469 if (ecode) {
3800276a
JP		 470 ath_err(ath9k_hw_common(ah),
471 "Failed allocating banks for external radio\n");
48a7c3df 472 ath9k_hw_rf_free_ext_banks(ah);
8fe65368 473 return ecode;
574d6b12 474 }
f078f209 475
070c4d50 476 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
f1dc5600 477 ath9k_hw_ani_setup(ah);
f637cfd6 478 ath9k_hw_ani_init(ah);
f078f209
LR		 479 }
480
f078f209
LR		 481 return 0;
482}
483
8525f280 484static void ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 485{
8525f280
LR		 486 if (AR_SREV_9300_20_OR_LATER(ah))
487 ar9003_hw_attach_ops(ah);
488 else
489 ar9002_hw_attach_ops(ah);
aa4058ae
LR		 490}
491
d70357d5
LR		 492/* Called for all hardware families */
493static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 494{
c46917bb 495 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 496 int r = 0;
aa4058ae 497
ac45c12d
SB		 498 ath9k_hw_read_revisions(ah);
499
0a8d7cb0
SB		 500 /*
501 * Read back AR_WA into a permanent copy and set bits 14 and 17.
502 * We need to do this to avoid RMW of this register. We cannot
503 * read the reg when chip is asleep.
504 */
505 ah->WARegVal = REG_READ(ah, AR_WA);
506 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
507 AR_WA_ASPM_TIMER_BASED_DISABLE);
508
aa4058ae 509 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 510 ath_err(common, "Couldn't reset chip\n");
95fafca2 511 return -EIO;
aa4058ae
LR		 512 }
513
bab1f62e
LR		 514 ath9k_hw_init_defaults(ah);
515 ath9k_hw_init_config(ah);
516
8525f280 517 ath9k_hw_attach_ops(ah);
d70357d5 518
9ecdef4b 519 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 520 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 521 return -EIO;
aa4058ae
LR		 522 }
523
524 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
525 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
4c85ab11
JL		 526 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
527 !ah->is_pciexpress)) {
aa4058ae
LR		 528 ah->config.serialize_regmode =
529 SER_REG_MODE_ON;
530 } else {
531 ah->config.serialize_regmode =
532 SER_REG_MODE_OFF;
533 }
534 }
535
226afe68 536 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 537 ah->config.serialize_regmode);
538
f4709fdf
LR		 539 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
540 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
541 else
542 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
543
6da5a720
FF		 544 switch (ah->hw_version.macVersion) {
545 case AR_SREV_VERSION_5416_PCI:
546 case AR_SREV_VERSION_5416_PCIE:
547 case AR_SREV_VERSION_9160:
548 case AR_SREV_VERSION_9100:
549 case AR_SREV_VERSION_9280:
550 case AR_SREV_VERSION_9285:
551 case AR_SREV_VERSION_9287:
552 case AR_SREV_VERSION_9271:
553 case AR_SREV_VERSION_9300:
554 case AR_SREV_VERSION_9485:
bca04689 555 case AR_SREV_VERSION_9340:
6da5a720
FF		 556 break;
557 default:
3800276a
JP		 558 ath_err(common,
559 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
560 ah->hw_version.macVersion, ah->hw_version.macRev);
95fafca2 561 return -EOPNOTSUPP;
aa4058ae
LR		 562 }
563
b99a7be4 564 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah))
d7e7d229
LR		 565 ah->is_pciexpress = false;
566
aa4058ae 567 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 568 ath9k_hw_init_cal_settings(ah);
569
570 ah->ani_function = ATH9K_ANI_ALL;
7a37081e 571 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae 572 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
e36b27af
LR		 573 if (!AR_SREV_9300_20_OR_LATER(ah))
574 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
aa4058ae
LR		 575
576 ath9k_hw_init_mode_regs(ah);
577
9a658d2b 578
aa4058ae 579 if (ah->is_pciexpress)
93b1b37f 580 ath9k_hw_configpcipowersave(ah, 0, 0);
aa4058ae
LR		 581 else
582 ath9k_hw_disablepcie(ah);
583
d8f492b7
LR		 584 if (!AR_SREV_9300_20_OR_LATER(ah))
585 ar9002_hw_cck_chan14_spread(ah);
193cd458 586
f637cfd6 587 r = ath9k_hw_post_init(ah);
aa4058ae 588 if (r)
95fafca2 589 return r;
aa4058ae
LR		 590
591 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 592 r = ath9k_hw_fill_cap_info(ah);
593 if (r)
594 return r;
595
4f3acf81
LR		 596 r = ath9k_hw_init_macaddr(ah);
597 if (r) {
3800276a 598 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 599 return r;
f078f209
LR		 600 }
601
d7e7d229 602 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 603 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 604 else
2660b81a 605 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 606
aea702b7 607 ah->bb_watchdog_timeout_ms = 25;
f078f209 608
211f5859
LR		 609 common->state = ATH_HW_INITIALIZED;
610
4f3acf81 611 return 0;
f078f209
LR		 612}
613
d70357d5 614int ath9k_hw_init(struct ath_hw *ah)
f078f209 615{
d70357d5
LR		 616 int ret;
617 struct ath_common *common = ath9k_hw_common(ah);
f078f209 618
d70357d5
LR		 619 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
620 switch (ah->hw_version.devid) {
621 case AR5416_DEVID_PCI:
622 case AR5416_DEVID_PCIE:
623 case AR5416_AR9100_DEVID:
624 case AR9160_DEVID_PCI:
625 case AR9280_DEVID_PCI:
626 case AR9280_DEVID_PCIE:
627 case AR9285_DEVID_PCIE:
db3cc53a
SB		 628 case AR9287_DEVID_PCI:
629 case AR9287_DEVID_PCIE:
d70357d5 630 case AR2427_DEVID_PCIE:
db3cc53a 631 case AR9300_DEVID_PCIE:
3050c914 632 case AR9300_DEVID_AR9485_PCIE:
bca04689 633 case AR9300_DEVID_AR9340:
d70357d5
LR		 634 break;
635 default:
636 if (common->bus_ops->ath_bus_type == ATH_USB)
637 break;
3800276a
JP		 638 ath_err(common, "Hardware device ID 0x%04x not supported\n",
639 ah->hw_version.devid);
d70357d5
LR		 640 return -EOPNOTSUPP;
641 }
f078f209 642
d70357d5
LR		 643 ret = __ath9k_hw_init(ah);
644 if (ret) {
3800276a
JP		 645 ath_err(common,
646 "Unable to initialize hardware; initialization status: %d\n",
647 ret);
d70357d5
LR		 648 return ret;
649 }
f078f209 650
d70357d5 651 return 0;
f078f209 652}
d70357d5 653EXPORT_SYMBOL(ath9k_hw_init);
f078f209 654
cbe61d8a 655static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 656{
7d0d0df0
S		 657 ENABLE_REGWRITE_BUFFER(ah);
658
f1dc5600
S		 659 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
660 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 661
f1dc5600
S		 662 REG_WRITE(ah, AR_QOS_NO_ACK,
663 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
664 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
665 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
666
667 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
668 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
669 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
670 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
671 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 672
673 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 674}
675
b1415819
VN		 676unsigned long ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
677{
ca7a4deb
FF		 678 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
679 udelay(100);
680 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 681
ca7a4deb
FF		 682 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
683 udelay(100);
b1415819 684
ca7a4deb 685 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 686}
687EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
688
3dfd7f60 689#define DPLL3_PHASE_SHIFT_VAL 0x1
cbe61d8a 690static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 691 struct ath9k_channel *chan)
f078f209 692{
d09b17f7
VT		 693 u32 pll;
694
22983c30 695 if (AR_SREV_9485(ah)) {
22983c30 696
3dfd7f60
VT		 697 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
698 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
699 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
700 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
701 AR_CH0_DPLL2_KD, 0x40);
702 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
703 AR_CH0_DPLL2_KI, 0x4);
22983c30 704
3dfd7f60
VT		 705 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
706 AR_CH0_BB_DPLL1_REFDIV, 0x5);
707 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
708 AR_CH0_BB_DPLL1_NINI, 0x58);
709 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
710 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 711
712 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 713 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
714 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
715 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 716 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 717 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 718
3dfd7f60 719 /* program BB PLL phase_shift to 0x6 */
22983c30 720 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 721 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
722
723 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
724 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 725 udelay(1000);
3dfd7f60
VT		 726
727 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
728 AR_CH0_DPLL3_PHASE_SHIFT, DPLL3_PHASE_SHIFT_VAL);
0b488ac6
VT		 729 } else if (AR_SREV_9340(ah)) {
730 u32 regval, pll2_divint, pll2_divfrac, refdiv;
731
732 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
733 udelay(1000);
734
735 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
736 udelay(100);
737
738 if (ah->is_clk_25mhz) {
739 pll2_divint = 0x54;
740 pll2_divfrac = 0x1eb85;
741 refdiv = 3;
742 } else {
743 pll2_divint = 88;
744 pll2_divfrac = 0;
745 refdiv = 5;
746 }
747
748 regval = REG_READ(ah, AR_PHY_PLL_MODE);
749 regval |= (0x1 << 16);
750 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
751 udelay(100);
752
753 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
754 (pll2_divint << 18) | pll2_divfrac);
755 udelay(100);
756
757 regval = REG_READ(ah, AR_PHY_PLL_MODE);
758 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
759 (0x4 << 26) | (0x18 << 19);
760 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
761 REG_WRITE(ah, AR_PHY_PLL_MODE,
762 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
763 udelay(1000);
22983c30 764 }
d09b17f7
VT		 765
766 pll = ath9k_hw_compute_pll_control(ah, chan);
f078f209 767
d03a66c1 768 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 769
0b488ac6 770 if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
3dfd7f60
VT		 771 udelay(1000);
772
c75724d1
LR		 773 /* Switch the core clock for ar9271 to 117Mhz */
774 if (AR_SREV_9271(ah)) {
25e2ab17
S		 775 udelay(500);
776 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 777 }
778
f1dc5600
S		 779 udelay(RTC_PLL_SETTLE_DELAY);
780
781 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
0b488ac6
VT		 782
783 if (AR_SREV_9340(ah)) {
784 if (ah->is_clk_25mhz) {
785 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
786 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
787 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
788 } else {
789 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
790 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
791 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
792 }
793 udelay(100);
794 }
f078f209
LR		 795}
796
cbe61d8a 797static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 798 enum nl80211_iftype opmode)
f078f209 799{
79d1d2b8 800 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 801 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 802 AR_IMR_TXURN |
803 AR_IMR_RXERR |
804 AR_IMR_RXORN |
805 AR_IMR_BCNMISC;
f078f209 806
79d1d2b8
VT		 807 if (AR_SREV_9340(ah))
808 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
809
66860240
VT		 810 if (AR_SREV_9300_20_OR_LATER(ah)) {
811 imr_reg |= AR_IMR_RXOK_HP;
812 if (ah->config.rx_intr_mitigation)
813 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
814 else
815 imr_reg |= AR_IMR_RXOK_LP;
f078f209 816
66860240
VT		 817 } else {
818 if (ah->config.rx_intr_mitigation)
819 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
820 else
821 imr_reg |= AR_IMR_RXOK;
822 }
f078f209 823
66860240
VT		 824 if (ah->config.tx_intr_mitigation)
825 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
826 else
827 imr_reg |= AR_IMR_TXOK;
f078f209 828
d97809db 829 if (opmode == NL80211_IFTYPE_AP)
152d530d 830 imr_reg |= AR_IMR_MIB;
f078f209 831
7d0d0df0
S		 832 ENABLE_REGWRITE_BUFFER(ah);
833
152d530d 834 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 835 ah->imrs2_reg |= AR_IMR_S2_GTT;
836 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 837
f1dc5600
S		 838 if (!AR_SREV_9100(ah)) {
839 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 840 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 841 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
842 }
66860240 843
7d0d0df0 844 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 845
66860240
VT		 846 if (AR_SREV_9300_20_OR_LATER(ah)) {
847 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
848 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
849 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
850 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
851 }
f078f209
LR		 852}
853
0005baf4 854static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 855{
0005baf4
FF		 856 u32 val = ath9k_hw_mac_to_clks(ah, us);
857 val = min(val, (u32) 0xFFFF);
858 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 859}
860
0005baf4 861static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 862{
0005baf4
FF		 863 u32 val = ath9k_hw_mac_to_clks(ah, us);
864 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
865 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
866}
867
868static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
869{
870 u32 val = ath9k_hw_mac_to_clks(ah, us);
871 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
872 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 873}
f1dc5600 874
cbe61d8a 875static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 876{
f078f209 877 if (tu > 0xFFFF) {
226afe68
JP		 878 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
879 "bad global tx timeout %u\n", tu);
2660b81a 880 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 881 return false;
882 } else {
883 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 884 ah->globaltxtimeout = tu;
f078f209
LR		 885 return true;
886 }
887}
888
0005baf4 889void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 890{
0005baf4
FF		 891 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
892 int acktimeout;
e239d859 893 int slottime;
0005baf4
FF		 894 int sifstime;
895
226afe68
JP		 896 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
897 ah->misc_mode);
f078f209 898
2660b81a 899 if (ah->misc_mode != 0)
ca7a4deb 900 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4
FF		 901
902 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
903 sifstime = 16;
904 else
905 sifstime = 10;
906
e239d859
FF		 907 /* As defined by IEEE 802.11-2007 17.3.8.6 */
908 slottime = ah->slottime + 3 * ah->coverage_class;
909 acktimeout = slottime + sifstime;
42c4568a
FF		 910
911 /*
912 * Workaround for early ACK timeouts, add an offset to match the
913 * initval's 64us ack timeout value.
914 * This was initially only meant to work around an issue with delayed
915 * BA frames in some implementations, but it has been found to fix ACK
916 * timeout issues in other cases as well.
917 */
918 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
919 acktimeout += 64 - sifstime - ah->slottime;
920
caabf2bf 921 ath9k_hw_setslottime(ah, ah->slottime);
0005baf4
FF		 922 ath9k_hw_set_ack_timeout(ah, acktimeout);
923 ath9k_hw_set_cts_timeout(ah, acktimeout);
2660b81a
S		 924 if (ah->globaltxtimeout != (u32) -1)
925 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600 926}
0005baf4 927EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 928
285f2dda 929void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 930{
211f5859
LR		 931 struct ath_common *common = ath9k_hw_common(ah);
932
736b3a27 933 if (common->state < ATH_HW_INITIALIZED)
211f5859
LR		 934 goto free_hw;
935
9ecdef4b 936 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 937
938free_hw:
8fe65368 939 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 940}
285f2dda 941EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 942
f1dc5600
S		 943/*******/
944/* INI */
945/*******/
946
8fe65368 947u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 948{
949 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
950
951 if (IS_CHAN_B(chan))
952 ctl |= CTL_11B;
953 else if (IS_CHAN_G(chan))
954 ctl |= CTL_11G;
955 else
956 ctl |= CTL_11A;
957
958 return ctl;
959}
960
f1dc5600
S		 961/****************************************/
962/* Reset and Channel Switching Routines */
963/****************************************/
f1dc5600 964
cbe61d8a 965static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 966{
57b32227 967 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 968
7d0d0df0
S		 969 ENABLE_REGWRITE_BUFFER(ah);
970
d7e7d229
LR		 971 /*
972 * set AHB_MODE not to do cacheline prefetches
973 */
ca7a4deb
FF		 974 if (!AR_SREV_9300_20_OR_LATER(ah))
975 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 976
d7e7d229
LR		 977 /*
978 * let mac dma reads be in 128 byte chunks
979 */
ca7a4deb 980 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 981
7d0d0df0 982 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 983
d7e7d229
LR		 984 /*
985 * Restore TX Trigger Level to its pre-reset value.
986 * The initial value depends on whether aggregation is enabled, and is
987 * adjusted whenever underruns are detected.
988 */
57b32227
FF		 989 if (!AR_SREV_9300_20_OR_LATER(ah))
990 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 991
7d0d0df0 992 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 993
d7e7d229
LR		 994 /*
995 * let mac dma writes be in 128 byte chunks
996 */
ca7a4deb 997 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 998
d7e7d229
LR		 999 /*
1000 * Setup receive FIFO threshold to hold off TX activities
1001 */
f1dc5600
S		 1002 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1003
57b32227
FF		 1004 if (AR_SREV_9300_20_OR_LATER(ah)) {
1005 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1006 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1007
1008 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1009 ah->caps.rx_status_len);
1010 }
1011
d7e7d229
LR		 1012 /*
1013 * reduce the number of usable entries in PCU TXBUF to avoid
1014 * wrap around issues.
1015 */
f1dc5600 1016 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1017 /* For AR9285 the number of Fifos are reduced to half.
1018 * So set the usable tx buf size also to half to
1019 * avoid data/delimiter underruns
1020 */
f1dc5600
S		 1021 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1022 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 1023 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 1024 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1025 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1026 }
744d4025 1027
7d0d0df0 1028 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1029
744d4025
VT		 1030 if (AR_SREV_9300_20_OR_LATER(ah))
1031 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1032}
1033
cbe61d8a 1034static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1035{
ca7a4deb
FF		 1036 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1037 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1038
f1dc5600 1039 switch (opmode) {
d97809db 1040 case NL80211_IFTYPE_ADHOC:
9cb5412b 1041 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb 1042 set |= AR_STA_ID1_ADHOC;
f1dc5600 1043 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1044 break;
ca7a4deb
FF		 1045 case NL80211_IFTYPE_AP:
1046 set |= AR_STA_ID1_STA_AP;
1047 /* fall through */
d97809db 1048 case NL80211_IFTYPE_STATION:
ca7a4deb 1049 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1050 break;
5f841b41 1051 default:
ca7a4deb
FF		 1052 if (!ah->is_monitoring)
1053 set = 0;
5f841b41 1054 break;
f1dc5600 1055 }
ca7a4deb 1056 REG_RMW(ah, AR_STA_ID1, set, mask);
f1dc5600
S		 1057}
1058
8fe65368
LR		 1059void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1060 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1061{
1062 u32 coef_exp, coef_man;
1063
1064 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1065 if ((coef_scaled >> coef_exp) & 0x1)
1066 break;
1067
1068 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1069
1070 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1071
1072 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1073 *coef_exponent = coef_exp - 16;
1074}
1075
cbe61d8a 1076static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1077{
1078 u32 rst_flags;
1079 u32 tmpReg;
1080
70768496 1081 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1082 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1083 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1084 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1085 }
1086
7d0d0df0
S		 1087 ENABLE_REGWRITE_BUFFER(ah);
1088
9a658d2b
LR		 1089 if (AR_SREV_9300_20_OR_LATER(ah)) {
1090 REG_WRITE(ah, AR_WA, ah->WARegVal);
1091 udelay(10);
1092 }
1093
f1dc5600
S		 1094 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1095 AR_RTC_FORCE_WAKE_ON_INT);
1096
1097 if (AR_SREV_9100(ah)) {
1098 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1099 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1100 } else {
1101 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1102 if (tmpReg &
1103 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1104 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 1105 u32 val;
f1dc5600 1106 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1107
1108 val = AR_RC_HOSTIF;
1109 if (!AR_SREV_9300_20_OR_LATER(ah))
1110 val |= AR_RC_AHB;
1111 REG_WRITE(ah, AR_RC, val);
1112
1113 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1114 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1115
1116 rst_flags = AR_RTC_RC_MAC_WARM;
1117 if (type == ATH9K_RESET_COLD)
1118 rst_flags |= AR_RTC_RC_MAC_COLD;
1119 }
1120
d03a66c1 1121 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1122
1123 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1124
f1dc5600
S		 1125 udelay(50);
1126
d03a66c1 1127 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1128 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
226afe68
JP		 1129 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1130 "RTC stuck in MAC reset\n");
f1dc5600
S		 1131 return false;
1132 }
1133
1134 if (!AR_SREV_9100(ah))
1135 REG_WRITE(ah, AR_RC, 0);
1136
f1dc5600
S		 1137 if (AR_SREV_9100(ah))
1138 udelay(50);
1139
1140 return true;
1141}
1142
cbe61d8a 1143static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1144{
7d0d0df0
S		 1145 ENABLE_REGWRITE_BUFFER(ah);
1146
9a658d2b
LR		 1147 if (AR_SREV_9300_20_OR_LATER(ah)) {
1148 REG_WRITE(ah, AR_WA, ah->WARegVal);
1149 udelay(10);
1150 }
1151
f1dc5600
S		 1152 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1153 AR_RTC_FORCE_WAKE_ON_INT);
1154
42d5bc3f 1155 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1156 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1157
d03a66c1 1158 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1159
7d0d0df0 1160 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1161
84e2169b
SB		 1162 if (!AR_SREV_9300_20_OR_LATER(ah))
1163 udelay(2);
1164
1165 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1166 REG_WRITE(ah, AR_RC, 0);
1167
d03a66c1 1168 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1169
1170 if (!ath9k_hw_wait(ah,
1171 AR_RTC_STATUS,
1172 AR_RTC_STATUS_M,
0caa7b14
S		 1173 AR_RTC_STATUS_ON,
1174 AH_WAIT_TIMEOUT)) {
226afe68
JP		 1175 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1176 "RTC not waking up\n");
f1dc5600 1177 return false;
f078f209
LR		 1178 }
1179
f1dc5600
S		 1180 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1181}
1182
cbe61d8a 1183static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1184{
9a658d2b
LR		 1185 if (AR_SREV_9300_20_OR_LATER(ah)) {
1186 REG_WRITE(ah, AR_WA, ah->WARegVal);
1187 udelay(10);
1188 }
1189
f1dc5600
S		 1190 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1191 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1192
1193 switch (type) {
1194 case ATH9K_RESET_POWER_ON:
1195 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1196 case ATH9K_RESET_WARM:
1197 case ATH9K_RESET_COLD:
1198 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1199 default:
1200 return false;
1201 }
f078f209
LR		 1202}
1203
cbe61d8a 1204static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1205 struct ath9k_channel *chan)
f078f209 1206{
42abfbee 1207 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1208 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1209 return false;
1210 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1211 return false;
f078f209 1212
9ecdef4b 1213 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1214 return false;
f078f209 1215
2660b81a 1216 ah->chip_fullsleep = false;
f1dc5600 1217 ath9k_hw_init_pll(ah, chan);
f1dc5600 1218 ath9k_hw_set_rfmode(ah, chan);
f078f209 1219
f1dc5600 1220 return true;
f078f209
LR		 1221}
1222
cbe61d8a 1223static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1224 struct ath9k_channel *chan)
f078f209 1225{
608b88cb 1226 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1227 struct ath_common *common = ath9k_hw_common(ah);
5f8e077c 1228 struct ieee80211_channel *channel = chan->chan;
8fe65368 1229 u32 qnum;
0a3b7bac 1230 int r;
f078f209
LR		 1231
1232 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1233 if (ath9k_hw_numtxpending(ah, qnum)) {
226afe68
JP		 1234 ath_dbg(common, ATH_DBG_QUEUE,
1235 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1236 return false;
1237 }
1238 }
1239
8fe65368 1240 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1241 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1242 return false;
1243 }
1244
8fe65368 1245 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1246
8fe65368 1247 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1248 if (r) {
3800276a 1249 ath_err(common, "Failed to set channel\n");
0a3b7bac 1250 return false;
f078f209 1251 }
dfdac8ac 1252 ath9k_hw_set_clockrate(ah);
f078f209 1253
8fbff4b8 1254 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1255 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1256 channel->max_antenna_gain * 2,
1257 channel->max_power * 2,
1258 min((u32) MAX_RATE_POWER,
de40f316 1259 (u32) regulatory->power_limit), false);
f078f209 1260
8fe65368 1261 ath9k_hw_rfbus_done(ah);
f078f209 1262
f1dc5600
S		 1263 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1264 ath9k_hw_set_delta_slope(ah, chan);
1265
8fe65368 1266 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1267
f1dc5600
S		 1268 return true;
1269}
1270
691680b8
FF		 1271static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1272{
1273 u32 gpio_mask = ah->gpio_mask;
1274 int i;
1275
1276 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1277 if (!(gpio_mask & 1))
1278 continue;
1279
1280 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1281 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1282 }
1283}
1284
c9c99e5e 1285bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1286{
c9c99e5e
FF		 1287 int count = 50;
1288 u32 reg;
1289
e17f83ea 1290 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1291 return true;
1292
1293 do {
1294 reg = REG_READ(ah, AR_OBS_BUS_1);
3b319aae 1295
c9c99e5e
FF		 1296 if ((reg & 0x7E7FFFEF) == 0x00702400)
1297 continue;
1298
1299 switch (reg & 0x7E000B00) {
1300 case 0x1E000000:
1301 case 0x52000B00:
1302 case 0x18000B00:
1303 continue;
1304 default:
1305 return true;
1306 }
1307 } while (count-- > 0);
3b319aae 1308
c9c99e5e 1309 return false;
3b319aae 1310}
c9c99e5e 1311EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1312
cbe61d8a 1313int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
20bd2a09 1314 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
f078f209 1315{
1510718d 1316 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1317 u32 saveLedState;
2660b81a 1318 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 1319 u32 saveDefAntenna;
1320 u32 macStaId1;
46fe782c 1321 u64 tsf = 0;
8fe65368 1322 int i, r;
f078f209 1323
43c27613
LR		 1324 ah->txchainmask = common->tx_chainmask;
1325 ah->rxchainmask = common->rx_chainmask;
f078f209 1326
6d50192c 1327 if ((common->bus_ops->ath_bus_type != ATH_USB) && !ah->chip_fullsleep) {
9b9cc61c 1328 ath9k_hw_abortpcurecv(ah);
9cc2f3e8 1329 if (!ath9k_hw_stopdmarecv(ah)) {
226afe68 1330 ath_dbg(common, ATH_DBG_XMIT,
9b9cc61c 1331 "Failed to stop receive dma\n");
9cc2f3e8
FF		 1332 bChannelChange = false;
1333 }
9b9cc61c
VT		 1334 }
1335
9ecdef4b 1336 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1337 return -EIO;
f078f209 1338
d9891c78 1339 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 1340 ath9k_hw_getnf(ah, curchan);
1341
20bd2a09
FF		 1342 ah->caldata = caldata;
1343 if (caldata &&
1344 (chan->channel != caldata->channel ||
1345 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1346 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1347 /* Operating channel changed, reset channel calibration data */
1348 memset(caldata, 0, sizeof(*caldata));
1349 ath9k_init_nfcal_hist_buffer(ah, chan);
1350 }
1351
f078f209 1352 if (bChannelChange &&
2660b81a
S		 1353 (ah->chip_fullsleep != true) &&
1354 (ah->curchan != NULL) &&
1355 (chan->channel != ah->curchan->channel) &&
f078f209 1356 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 1357 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
58d7e0f3 1358 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
f078f209 1359
25c56eec 1360 if (ath9k_hw_channel_change(ah, chan)) {
2660b81a 1361 ath9k_hw_loadnf(ah, ah->curchan);
00c86590 1362 ath9k_hw_start_nfcal(ah, true);
c2ba3342
RM		 1363 if (AR_SREV_9271(ah))
1364 ar9002_hw_load_ani_reg(ah, chan);
ae8d2858 1365 return 0;
f078f209
LR		 1366 }
1367 }
1368
1369 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1370 if (saveDefAntenna == 0)
1371 saveDefAntenna = 1;
1372
1373 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1374
46fe782c 1375 /* For chips on which RTC reset is done, save TSF before it gets cleared */
f860d526
FF		 1376 if (AR_SREV_9100(ah) ||
1377 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
46fe782c
S		 1378 tsf = ath9k_hw_gettsf64(ah);
1379
f078f209
LR		 1380 saveLedState = REG_READ(ah, AR_CFG_LED) &
1381 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1382 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1383
1384 ath9k_hw_mark_phy_inactive(ah);
1385
45ef6a0b
VT		 1386 ah->paprd_table_write_done = false;
1387
05020d23 1388 /* Only required on the first reset */
d7e7d229
LR		 1389 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1390 REG_WRITE(ah,
1391 AR9271_RESET_POWER_DOWN_CONTROL,
1392 AR9271_RADIO_RF_RST);
1393 udelay(50);
1394 }
1395
f078f209 1396 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1397 ath_err(common, "Chip reset failed\n");
ae8d2858 1398 return -EINVAL;
f078f209
LR		 1399 }
1400
05020d23 1401 /* Only required on the first reset */
d7e7d229
LR		 1402 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1403 ah->htc_reset_init = false;
1404 REG_WRITE(ah,
1405 AR9271_RESET_POWER_DOWN_CONTROL,
1406 AR9271_GATE_MAC_CTL);
1407 udelay(50);
1408 }
1409
46fe782c 1410 /* Restore TSF */
f860d526 1411 if (tsf)
46fe782c
S		 1412 ath9k_hw_settsf64(ah, tsf);
1413
7a37081e 1414 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1415 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1416
e9141f71
S		 1417 if (!AR_SREV_9300_20_OR_LATER(ah))
1418 ar9002_hw_enable_async_fifo(ah);
1419
25c56eec 1420 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1421 if (r)
1422 return r;
f078f209 1423
f860d526
FF		 1424 /*
1425 * Some AR91xx SoC devices frequently fail to accept TSF writes
1426 * right after the chip reset. When that happens, write a new
1427 * value after the initvals have been applied, with an offset
1428 * based on measured time difference
1429 */
1430 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1431 tsf += 1500;
1432 ath9k_hw_settsf64(ah, tsf);
1433 }
1434
0ced0e17
JM		 1435 /* Setup MFP options for CCMP */
1436 if (AR_SREV_9280_20_OR_LATER(ah)) {
1437 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1438 * frames when constructing CCMP AAD. */
1439 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1440 0xc7ff);
1441 ah->sw_mgmt_crypto = false;
1442 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1443 /* Disable hardware crypto for management frames */
1444 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1445 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1446 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1447 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1448 ah->sw_mgmt_crypto = true;
1449 } else
1450 ah->sw_mgmt_crypto = true;
1451
f078f209
LR		 1452 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1453 ath9k_hw_set_delta_slope(ah, chan);
1454
8fe65368 1455 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1456 ah->eep_ops->set_board_values(ah, chan);
a7765828 1457
7d0d0df0
S		 1458 ENABLE_REGWRITE_BUFFER(ah);
1459
1510718d
LR		 1460 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1461 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 1462 | macStaId1
1463 | AR_STA_ID1_RTS_USE_DEF
2660b81a 1464 | (ah->config.
60b67f51 1465 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a 1466 | ah->sta_id1_defaults);
13b81559 1467 ath_hw_setbssidmask(common);
f078f209 1468 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
3453ad88 1469 ath9k_hw_write_associd(ah);
f078f209 1470 REG_WRITE(ah, AR_ISR, ~0);
f078f209
LR		 1471 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1472
7d0d0df0 1473 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1474
00e0003e
SM		 1475 ath9k_hw_set_operating_mode(ah, ah->opmode);
1476
8fe65368 1477 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1478 if (r)
1479 return r;
f078f209 1480
dfdac8ac
FF		 1481 ath9k_hw_set_clockrate(ah);
1482
7d0d0df0
S		 1483 ENABLE_REGWRITE_BUFFER(ah);
1484
f078f209
LR		 1485 for (i = 0; i < AR_NUM_DCU; i++)
1486 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1487
7d0d0df0 1488 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1489
2660b81a 1490 ah->intr_txqs = 0;
f4c607dc 1491 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
f078f209
LR		 1492 ath9k_hw_resettxqueue(ah, i);
1493
2660b81a 1494 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1495 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1496 ath9k_hw_init_qos(ah);
1497
2660b81a 1498 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
55821324 1499 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3b319aae 1500
0005baf4 1501 ath9k_hw_init_global_settings(ah);
f078f209 1502
6c94fdc9 1503 if (!AR_SREV_9300_20_OR_LATER(ah)) {
e9141f71 1504 ar9002_hw_update_async_fifo(ah);
6c94fdc9 1505 ar9002_hw_enable_wep_aggregation(ah);
ac88b6ec
VN		 1506 }
1507
ca7a4deb 1508 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1509
1510 ath9k_hw_set_dma(ah);
1511
1512 REG_WRITE(ah, AR_OBS, 8);
1513
0ce024cb 1514 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1515 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1516 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1517 }
1518
7f62a136
VT		 1519 if (ah->config.tx_intr_mitigation) {
1520 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1521 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1522 }
1523
f078f209
LR		 1524 ath9k_hw_init_bb(ah, chan);
1525
ae8d2858 1526 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1527 return -EIO;
f078f209 1528
7d0d0df0 1529 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1530
8fe65368 1531 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1532 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1533
7d0d0df0 1534 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1535
d7e7d229
LR		 1536 /*
1537 * For big endian systems turn on swapping for descriptors
1538 */
f078f209
LR		 1539 if (AR_SREV_9100(ah)) {
1540 u32 mask;
1541 mask = REG_READ(ah, AR_CFG);
1542 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
226afe68 1543 ath_dbg(common, ATH_DBG_RESET,
04bd4638 1544 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 1545 } else {
1546 mask =
1547 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1548 REG_WRITE(ah, AR_CFG, mask);
226afe68 1549 ath_dbg(common, ATH_DBG_RESET,
04bd4638 1550 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 1551 }
1552 } else {
cbba8cd1
S		 1553 if (common->bus_ops->ath_bus_type == ATH_USB) {
1554 /* Configure AR9271 target WLAN */
1555 if (AR_SREV_9271(ah))
1556 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1557 else
1558 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1559 }
f078f209 1560#ifdef __BIG_ENDIAN
2be7bfe0
VT		 1561 else if (AR_SREV_9340(ah))
1562 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1563 else
d7e7d229 1564 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 1565#endif
1566 }
1567
766ec4a9 1568 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 1569 ath9k_hw_btcoex_enable(ah);
1570
00c86590 1571 if (AR_SREV_9300_20_OR_LATER(ah))
aea702b7 1572 ar9003_hw_bb_watchdog_config(ah);
d8903a53 1573
691680b8
FF		 1574 ath9k_hw_apply_gpio_override(ah);
1575
ae8d2858 1576 return 0;
f078f209 1577}
7322fd19 1578EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1579
f1dc5600
S		 1580/******************************/
1581/* Power Management (Chipset) */
1582/******************************/
1583
42d5bc3f
LR		 1584/*
1585 * Notify Power Mgt is disabled in self-generated frames.
1586 * If requested, force chip to sleep.
1587 */
cbe61d8a 1588static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 1589{
f1dc5600
S		 1590 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1591 if (setChip) {
42d5bc3f
LR		 1592 /*
1593 * Clear the RTC force wake bit to allow the
1594 * mac to go to sleep.
1595 */
f1dc5600
S		 1596 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1597 AR_RTC_FORCE_WAKE_EN);
42d5bc3f 1598 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1599 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 1600
42d5bc3f 1601 /* Shutdown chip. Active low */
14b3af38 1602 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
4921be80
S		 1603 REG_CLR_BIT(ah, (AR_RTC_RESET),
1604 AR_RTC_RESET_EN);
f1dc5600 1605 }
9a658d2b
LR		 1606
1607 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1608 if (AR_SREV_9300_20_OR_LATER(ah))
1609 REG_WRITE(ah, AR_WA,
1610 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 1611}
1612
bbd79af5
LR		 1613/*
1614 * Notify Power Management is enabled in self-generating
1615 * frames. If request, set power mode of chip to
1616 * auto/normal. Duration in units of 128us (1/8 TU).
1617 */
cbe61d8a 1618static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 1619{
f1dc5600
S		 1620 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1621 if (setChip) {
2660b81a 1622 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 1623
f1dc5600 1624 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
bbd79af5 1625 /* Set WakeOnInterrupt bit; clear ForceWake bit */
f1dc5600
S		 1626 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1627 AR_RTC_FORCE_WAKE_ON_INT);
1628 } else {
bbd79af5
LR		 1629 /*
1630 * Clear the RTC force wake bit to allow the
1631 * mac to go to sleep.
1632 */
f1dc5600
S		 1633 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1634 AR_RTC_FORCE_WAKE_EN);
f078f209 1635 }
f078f209 1636 }
9a658d2b
LR		 1637
1638 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1639 if (AR_SREV_9300_20_OR_LATER(ah))
1640 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 1641}
1642
cbe61d8a 1643static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 1644{
f1dc5600
S		 1645 u32 val;
1646 int i;
f078f209 1647
9a658d2b
LR		 1648 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1649 if (AR_SREV_9300_20_OR_LATER(ah)) {
1650 REG_WRITE(ah, AR_WA, ah->WARegVal);
1651 udelay(10);
1652 }
1653
f1dc5600
S		 1654 if (setChip) {
1655 if ((REG_READ(ah, AR_RTC_STATUS) &
1656 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1657 if (ath9k_hw_set_reset_reg(ah,
1658 ATH9K_RESET_POWER_ON) != true) {
1659 return false;
1660 }
e041228f
LR		 1661 if (!AR_SREV_9300_20_OR_LATER(ah))
1662 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 1663 }
1664 if (AR_SREV_9100(ah))
1665 REG_SET_BIT(ah, AR_RTC_RESET,
1666 AR_RTC_RESET_EN);
f078f209 1667
f1dc5600
S		 1668 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1669 AR_RTC_FORCE_WAKE_EN);
1670 udelay(50);
f078f209 1671
f1dc5600
S		 1672 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1673 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1674 if (val == AR_RTC_STATUS_ON)
1675 break;
1676 udelay(50);
1677 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1678 AR_RTC_FORCE_WAKE_EN);
f078f209 1679 }
f1dc5600 1680 if (i == 0) {
3800276a
JP		 1681 ath_err(ath9k_hw_common(ah),
1682 "Failed to wakeup in %uus\n",
1683 POWER_UP_TIME / 20);
f1dc5600 1684 return false;
f078f209 1685 }
f078f209
LR		 1686 }
1687
f1dc5600 1688 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 1689
f1dc5600 1690 return true;
f078f209
LR		 1691}
1692
9ecdef4b 1693bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 1694{
c46917bb 1695 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 1696 int status = true, setChip = true;
f1dc5600
S		 1697 static const char *modes[] = {
1698 "AWAKE",
1699 "FULL-SLEEP",
1700 "NETWORK SLEEP",
1701 "UNDEFINED"
1702 };
f1dc5600 1703
cbdec975
GJ		 1704 if (ah->power_mode == mode)
1705 return status;
1706
226afe68
JP		 1707 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1708 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 1709
1710 switch (mode) {
1711 case ATH9K_PM_AWAKE:
1712 status = ath9k_hw_set_power_awake(ah, setChip);
1713 break;
1714 case ATH9K_PM_FULL_SLEEP:
1715 ath9k_set_power_sleep(ah, setChip);
2660b81a 1716 ah->chip_fullsleep = true;
f1dc5600
S		 1717 break;
1718 case ATH9K_PM_NETWORK_SLEEP:
1719 ath9k_set_power_network_sleep(ah, setChip);
1720 break;
f078f209 1721 default:
3800276a 1722 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 1723 return false;
1724 }
2660b81a 1725 ah->power_mode = mode;
f1dc5600 1726
69f4aab1
LR		 1727 /*
1728 * XXX: If this warning never comes up after a while then
1729 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1730 * ath9k_hw_setpower() return type void.
1731 */
97dcec57
SM		 1732
1733 if (!(ah->ah_flags & AH_UNPLUGGED))
1734 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 1735
f1dc5600 1736 return status;
f078f209 1737}
7322fd19 1738EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 1739
f1dc5600
S		 1740/*******************/
1741/* Beacon Handling */
1742/*******************/
1743
cbe61d8a 1744void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 1745{
f078f209
LR		 1746 int flags = 0;
1747
7d0d0df0
S		 1748 ENABLE_REGWRITE_BUFFER(ah);
1749
2660b81a 1750 switch (ah->opmode) {
d97809db 1751 case NL80211_IFTYPE_ADHOC:
9cb5412b 1752 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 1753 REG_SET_BIT(ah, AR_TXCFG,
1754 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
dd347f2f
FF		 1755 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
1756 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
f078f209 1757 flags |= AR_NDP_TIMER_EN;
d97809db 1758 case NL80211_IFTYPE_AP:
dd347f2f
FF		 1759 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
1760 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
1761 TU_TO_USEC(ah->config.dma_beacon_response_time));
1762 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
1763 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 1764 flags |=
1765 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1766 break;
d97809db 1767 default:
226afe68
JP		 1768 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1769 "%s: unsupported opmode: %d\n",
1770 __func__, ah->opmode);
d97809db
CM		 1771 return;
1772 break;
f078f209
LR		 1773 }
1774
dd347f2f
FF		 1775 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
1776 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
1777 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
1778 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
f078f209 1779
7d0d0df0 1780 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1781
f078f209
LR		 1782 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1783}
7322fd19 1784EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 1785
cbe61d8a 1786void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 1787 const struct ath9k_beacon_state *bs)
f078f209
LR		 1788{
1789 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 1790 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1791 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1792
7d0d0df0
S		 1793 ENABLE_REGWRITE_BUFFER(ah);
1794
f078f209
LR		 1795 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1796
1797 REG_WRITE(ah, AR_BEACON_PERIOD,
1798 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1799 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1800 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1801
7d0d0df0 1802 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1803
f078f209
LR		 1804 REG_RMW_FIELD(ah, AR_RSSI_THR,
1805 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1806
1807 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1808
1809 if (bs->bs_sleepduration > beaconintval)
1810 beaconintval = bs->bs_sleepduration;
1811
1812 dtimperiod = bs->bs_dtimperiod;
1813 if (bs->bs_sleepduration > dtimperiod)
1814 dtimperiod = bs->bs_sleepduration;
1815
1816 if (beaconintval == dtimperiod)
1817 nextTbtt = bs->bs_nextdtim;
1818 else
1819 nextTbtt = bs->bs_nexttbtt;
1820
226afe68
JP		 1821 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1822 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1823 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1824 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 1825
7d0d0df0
S		 1826 ENABLE_REGWRITE_BUFFER(ah);
1827
f1dc5600
S		 1828 REG_WRITE(ah, AR_NEXT_DTIM,
1829 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1830 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 1831
f1dc5600
S		 1832 REG_WRITE(ah, AR_SLEEP1,
1833 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1834 | AR_SLEEP1_ASSUME_DTIM);
f078f209 1835
f1dc5600
S		 1836 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1837 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1838 else
1839 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 1840
f1dc5600
S		 1841 REG_WRITE(ah, AR_SLEEP2,
1842 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 1843
f1dc5600
S		 1844 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1845 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 1846
7d0d0df0 1847 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1848
f1dc5600
S		 1849 REG_SET_BIT(ah, AR_TIMER_MODE,
1850 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1851 AR_DTIM_TIMER_EN);
f078f209 1852
4af9cf4f
S		 1853 /* TSF Out of Range Threshold */
1854 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 1855}
7322fd19 1856EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 1857
f1dc5600
S		 1858/*******************/
1859/* HW Capabilities */
1860/*******************/
1861
a9a29ce6 1862int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 1863{
2660b81a 1864 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 1865 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1866 struct ath_common *common = ath9k_hw_common(ah);
766ec4a9 1867 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
608b88cb 1868
f1dc5600 1869 u16 capField = 0, eeval;
47c80de6 1870 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 1871
f74df6fb 1872 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 1873 regulatory->current_rd = eeval;
f078f209 1874
f74df6fb 1875 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
e17f83ea 1876 if (AR_SREV_9285_12_OR_LATER(ah))
fec0de11 1877 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 1878 regulatory->current_rd_ext = eeval;
f078f209 1879
f74df6fb 1880 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 1881
2660b81a 1882 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 1883 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 1884 if (regulatory->current_rd == 0x64 ||
1885 regulatory->current_rd == 0x65)
1886 regulatory->current_rd += 5;
1887 else if (regulatory->current_rd == 0x41)
1888 regulatory->current_rd = 0x43;
226afe68
JP		 1889 ath_dbg(common, ATH_DBG_REGULATORY,
1890 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 1891 }
f078f209 1892
f74df6fb 1893 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6 1894 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3800276a
JP		 1895 ath_err(common,
1896 "no band has been marked as supported in EEPROM\n");
a9a29ce6
GJ		 1897 return -EINVAL;
1898 }
1899
d4659912
FF		 1900 if (eeval & AR5416_OPFLAGS_11A)
1901 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 1902
d4659912
FF		 1903 if (eeval & AR5416_OPFLAGS_11G)
1904 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 1905
f74df6fb 1906 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 1907 /*
1908 * For AR9271 we will temporarilly uses the rx chainmax as read from
1909 * the EEPROM.
1910 */
8147f5de 1911 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 1912 !(eeval & AR5416_OPFLAGS_11A) &&
1913 !(AR_SREV_9271(ah)))
1914 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 1915 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 1916 else if (AR_SREV_9100(ah))
1917 pCap->rx_chainmask = 0x7;
8147f5de 1918 else
d7e7d229 1919 /* Use rx_chainmask from EEPROM. */
8147f5de 1920 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 1921
7a37081e 1922 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 1923
02d2ebb2
FF		 1924 /* enable key search for every frame in an aggregate */
1925 if (AR_SREV_9300_20_OR_LATER(ah))
1926 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
1927
ce2220d1
BR		 1928 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
1929
0db156e9 1930 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 1931 pCap->hw_caps |= ATH9K_HW_CAP_HT;
1932 else
1933 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 1934
5b5fa355
S		 1935 if (AR_SREV_9271(ah))
1936 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 1937 else if (AR_DEVID_7010(ah))
1938 pCap->num_gpio_pins = AR7010_NUM_GPIO;
e17f83ea 1939 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 1940 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 1941 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 1942 pCap->num_gpio_pins = AR928X_NUM_GPIO;
1943 else
1944 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 1945
f1dc5600
S		 1946 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
1947 pCap->hw_caps |= ATH9K_HW_CAP_CST;
1948 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1949 } else {
1950 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 1951 }
1952
e97275cb 1953#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 1954 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
1955 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
1956 ah->rfkill_gpio =
1957 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
1958 ah->rfkill_polarity =
1959 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 1960
1961 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 1962 }
f1dc5600 1963#endif
d5d1154f 1964 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 1965 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
1966 else
1967 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 1968
e7594072 1969 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 1970 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
1971 else
1972 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 1973
8f5dcb1c 1974 if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) {
766ec4a9
LR		 1975 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
1976 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
22f25d0d 1977
8c8f9ba7 1978 if (AR_SREV_9285(ah)) {
766ec4a9
LR		 1979 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
1980 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
8c8f9ba7 1981 } else {
766ec4a9 1982 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
8c8f9ba7 1983 }
22f25d0d 1984 } else {
766ec4a9 1985 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 1986 }
a9a29ce6 1987
ceb26445 1988 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503
VT		 1989 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
1990 if (!AR_SREV_9485(ah))
1991 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
1992
ceb26445
VT		 1993 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
1994 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
1995 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 1996 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 1997 pCap->txs_len = sizeof(struct ar9003_txs);
6f481010
LR		 1998 if (!ah->config.paprd_disable &&
1999 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
4935250a 2000 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
162c3be3
VT		 2001 } else {
2002 pCap->tx_desc_len = sizeof(struct ath_desc);
6b42e8d0
FF		 2003 if (AR_SREV_9280_20(ah) &&
2004 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2005 AR5416_EEP_MINOR_VER_16) ||
2006 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2007 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2008 }
1adf02ff 2009
6c84ce08
VT		 2010 if (AR_SREV_9300_20_OR_LATER(ah))
2011 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2012
6ee63f55
SB		 2013 if (AR_SREV_9300_20_OR_LATER(ah))
2014 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2015
a42acef0 2016 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2017 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2018
754dc536
VT		 2019 if (AR_SREV_9285(ah))
2020 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2021 ant_div_ctl1 =
2022 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2023 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2024 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2025 }
ea066d5a
MSS		 2026 if (AR_SREV_9300_20_OR_LATER(ah)) {
2027 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2028 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2029 }
2030
2031
754dc536 2032
8060e169
VT		 2033 if (AR_SREV_9485_10(ah)) {
2034 pCap->pcie_lcr_extsync_en = true;
2035 pCap->pcie_lcr_offset = 0x80;
2036 }
2037
47c80de6
VT		 2038 tx_chainmask = pCap->tx_chainmask;
2039 rx_chainmask = pCap->rx_chainmask;
2040 while (tx_chainmask || rx_chainmask) {
2041 if (tx_chainmask & BIT(0))
2042 pCap->max_txchains++;
2043 if (rx_chainmask & BIT(0))
2044 pCap->max_rxchains++;
2045
2046 tx_chainmask >>= 1;
2047 rx_chainmask >>= 1;
2048 }
2049
a9a29ce6 2050 return 0;
f078f209
LR		 2051}
2052
f1dc5600
S		 2053/****************************/
2054/* GPIO / RFKILL / Antennae */
2055/****************************/
f078f209 2056
cbe61d8a 2057static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2058 u32 gpio, u32 type)
2059{
2060 int addr;
2061 u32 gpio_shift, tmp;
f078f209 2062
f1dc5600
S		 2063 if (gpio > 11)
2064 addr = AR_GPIO_OUTPUT_MUX3;
2065 else if (gpio > 5)
2066 addr = AR_GPIO_OUTPUT_MUX2;
2067 else
2068 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2069
f1dc5600 2070 gpio_shift = (gpio % 6) * 5;
f078f209 2071
f1dc5600
S		 2072 if (AR_SREV_9280_20_OR_LATER(ah)
2073 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2074 REG_RMW(ah, addr, (type << gpio_shift),
2075 (0x1f << gpio_shift));
f078f209 2076 } else {
f1dc5600
S		 2077 tmp = REG_READ(ah, addr);
2078 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2079 tmp &= ~(0x1f << gpio_shift);
2080 tmp |= (type << gpio_shift);
2081 REG_WRITE(ah, addr, tmp);
f078f209 2082 }
f078f209
LR		 2083}
2084
cbe61d8a 2085void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2086{
f1dc5600 2087 u32 gpio_shift;
f078f209 2088
9680e8a3 2089 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2090
88c1f4f6
S		 2091 if (AR_DEVID_7010(ah)) {
2092 gpio_shift = gpio;
2093 REG_RMW(ah, AR7010_GPIO_OE,
2094 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2095 (AR7010_GPIO_OE_MASK << gpio_shift));
2096 return;
2097 }
f078f209 2098
88c1f4f6 2099 gpio_shift = gpio << 1;
f1dc5600
S		 2100 REG_RMW(ah,
2101 AR_GPIO_OE_OUT,
2102 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2103 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2104}
7322fd19 2105EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2106
cbe61d8a 2107u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2108{
cb33c412
SB		 2109#define MS_REG_READ(x, y) \
2110 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2111
2660b81a 2112 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2113 return 0xffffffff;
f078f209 2114
88c1f4f6
S		 2115 if (AR_DEVID_7010(ah)) {
2116 u32 val;
2117 val = REG_READ(ah, AR7010_GPIO_IN);
2118 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2119 } else if (AR_SREV_9300_20_OR_LATER(ah))
9306990a
VT		 2120 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2121 AR_GPIO_BIT(gpio)) != 0;
783dfca1 2122 else if (AR_SREV_9271(ah))
5b5fa355 2123 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2124 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2125 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2126 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2127 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2128 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2129 return MS_REG_READ(AR928X, gpio) != 0;
2130 else
2131 return MS_REG_READ(AR, gpio) != 0;
f078f209 2132}
7322fd19 2133EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2134
cbe61d8a 2135void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2136 u32 ah_signal_type)
f078f209 2137{
f1dc5600 2138 u32 gpio_shift;
f078f209 2139
88c1f4f6
S		 2140 if (AR_DEVID_7010(ah)) {
2141 gpio_shift = gpio;
2142 REG_RMW(ah, AR7010_GPIO_OE,
2143 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2144 (AR7010_GPIO_OE_MASK << gpio_shift));
2145 return;
2146 }
f078f209 2147
88c1f4f6 2148 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2149 gpio_shift = 2 * gpio;
f1dc5600
S		 2150 REG_RMW(ah,
2151 AR_GPIO_OE_OUT,
2152 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2153 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2154}
7322fd19 2155EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2156
cbe61d8a 2157void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2158{
88c1f4f6
S		 2159 if (AR_DEVID_7010(ah)) {
2160 val = val ? 0 : 1;
2161 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2162 AR_GPIO_BIT(gpio));
2163 return;
2164 }
2165
5b5fa355
S		 2166 if (AR_SREV_9271(ah))
2167 val = ~val;
2168
f1dc5600
S		 2169 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2170 AR_GPIO_BIT(gpio));
f078f209 2171}
7322fd19 2172EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2173
cbe61d8a 2174u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 2175{
f1dc5600 2176 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209 2177}
7322fd19 2178EXPORT_SYMBOL(ath9k_hw_getdefantenna);
f078f209 2179
cbe61d8a 2180void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2181{
f1dc5600 2182 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2183}
7322fd19 2184EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2185
f1dc5600
S		 2186/*********************/
2187/* General Operation */
2188/*********************/
2189
cbe61d8a 2190u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2191{
f1dc5600
S		 2192 u32 bits = REG_READ(ah, AR_RX_FILTER);
2193 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2194
f1dc5600
S		 2195 if (phybits & AR_PHY_ERR_RADAR)
2196 bits |= ATH9K_RX_FILTER_PHYRADAR;
2197 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2198 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2199
f1dc5600 2200 return bits;
f078f209 2201}
7322fd19 2202EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2203
cbe61d8a 2204void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2205{
f1dc5600 2206 u32 phybits;
f078f209 2207
7d0d0df0
S		 2208 ENABLE_REGWRITE_BUFFER(ah);
2209
7ea310be
S		 2210 REG_WRITE(ah, AR_RX_FILTER, bits);
2211
f1dc5600
S		 2212 phybits = 0;
2213 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2214 phybits |= AR_PHY_ERR_RADAR;
2215 if (bits & ATH9K_RX_FILTER_PHYERR)
2216 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2217 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2218
f1dc5600 2219 if (phybits)
ca7a4deb 2220 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2221 else
ca7a4deb 2222 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2223
2224 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2225}
7322fd19 2226EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2227
cbe61d8a 2228bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2229{
63a75b91
SB		 2230 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2231 return false;
2232
2233 ath9k_hw_init_pll(ah, NULL);
2234 return true;
f1dc5600 2235}
7322fd19 2236EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2237
cbe61d8a 2238bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2239{
9ecdef4b 2240 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2241 return false;
f078f209 2242
63a75b91
SB		 2243 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2244 return false;
2245
2246 ath9k_hw_init_pll(ah, NULL);
2247 return true;
f078f209 2248}
7322fd19 2249EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2250
de40f316 2251void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2252{
608b88cb 2253 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 2254 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2255 struct ieee80211_channel *channel = chan->chan;
f078f209 2256
608b88cb 2257 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 2258
8fbff4b8 2259 ah->eep_ops->set_txpower(ah, chan,
608b88cb 2260 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 2261 channel->max_antenna_gain * 2,
2262 channel->max_power * 2,
2263 min((u32) MAX_RATE_POWER,
de40f316 2264 (u32) regulatory->power_limit), test);
6f255425 2265}
7322fd19 2266EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2267
cbe61d8a 2268void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2269{
2660b81a 2270 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2271}
7322fd19 2272EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2273
cbe61d8a 2274void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2275{
f1dc5600
S		 2276 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2277 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2278}
7322fd19 2279EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2280
f2b2143e 2281void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2282{
1510718d
LR		 2283 struct ath_common *common = ath9k_hw_common(ah);
2284
2285 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2286 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2287 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2288}
7322fd19 2289EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2290
1c0fc65e
BP		 2291#define ATH9K_MAX_TSF_READ 10
2292
cbe61d8a 2293u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2294{
1c0fc65e
BP		 2295 u32 tsf_lower, tsf_upper1, tsf_upper2;
2296 int i;
2297
2298 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2299 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2300 tsf_lower = REG_READ(ah, AR_TSF_L32);
2301 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2302 if (tsf_upper2 == tsf_upper1)
2303 break;
2304 tsf_upper1 = tsf_upper2;
2305 }
f078f209 2306
1c0fc65e 2307 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2308
1c0fc65e 2309 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2310}
7322fd19 2311EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2312
cbe61d8a 2313void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2314{
27abe060 2315 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2316 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2317}
7322fd19 2318EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2319
cbe61d8a 2320void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2321{
f9b604f6
GJ		 2322 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2323 AH_TSF_WRITE_TIMEOUT))
226afe68
JP		 2324 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2325 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2326
f1dc5600
S		 2327 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2328}
7322fd19 2329EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2330
54e4cec6 2331void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 2332{
f1dc5600 2333 if (setting)
2660b81a 2334 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2335 else
2660b81a 2336 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2337}
7322fd19 2338EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2339
25c56eec 2340void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2341{
25c56eec 2342 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2343 u32 macmode;
2344
25c56eec 2345 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2346 macmode = AR_2040_JOINED_RX_CLEAR;
2347 else
2348 macmode = 0;
f078f209 2349
f1dc5600 2350 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2351}
ff155a45
VT		 2352
2353/* HW Generic timers configuration */
2354
2355static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2356{
2357 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2358 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2359 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2360 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2361 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2362 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2363 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2364 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2365 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2366 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2367 AR_NDP2_TIMER_MODE, 0x0002},
2368 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2369 AR_NDP2_TIMER_MODE, 0x0004},
2370 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2371 AR_NDP2_TIMER_MODE, 0x0008},
2372 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2373 AR_NDP2_TIMER_MODE, 0x0010},
2374 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2375 AR_NDP2_TIMER_MODE, 0x0020},
2376 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2377 AR_NDP2_TIMER_MODE, 0x0040},
2378 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2379 AR_NDP2_TIMER_MODE, 0x0080}
2380};
2381
2382/* HW generic timer primitives */
2383
2384/* compute and clear index of rightmost 1 */
2385static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2386{
2387 u32 b;
2388
2389 b = *mask;
2390 b &= (0-b);
2391 *mask &= ~b;
2392 b *= debruijn32;
2393 b >>= 27;
2394
2395 return timer_table->gen_timer_index[b];
2396}
2397
dd347f2f 2398u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2399{
2400 return REG_READ(ah, AR_TSF_L32);
2401}
dd347f2f 2402EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2403
2404struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2405 void (*trigger)(void *),
2406 void (*overflow)(void *),
2407 void *arg,
2408 u8 timer_index)
2409{
2410 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2411 struct ath_gen_timer *timer;
2412
2413 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2414
2415 if (timer == NULL) {
3800276a
JP		 2416 ath_err(ath9k_hw_common(ah),
2417 "Failed to allocate memory for hw timer[%d]\n",
2418 timer_index);
ff155a45
VT		 2419 return NULL;
2420 }
2421
2422 /* allocate a hardware generic timer slot */
2423 timer_table->timers[timer_index] = timer;
2424 timer->index = timer_index;
2425 timer->trigger = trigger;
2426 timer->overflow = overflow;
2427 timer->arg = arg;
2428
2429 return timer;
2430}
7322fd19 2431EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2432
cd9bf689
LR		 2433void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2434 struct ath_gen_timer *timer,
2435 u32 timer_next,
2436 u32 timer_period)
ff155a45
VT		 2437{
2438 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2439 u32 tsf;
2440
2441 BUG_ON(!timer_period);
2442
2443 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2444
2445 tsf = ath9k_hw_gettsf32(ah);
2446
226afe68
JP		 2447 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2448 "current tsf %x period %x timer_next %x\n",
2449 tsf, timer_period, timer_next);
ff155a45
VT		 2450
2451 /*
2452 * Pull timer_next forward if the current TSF already passed it
2453 * because of software latency
2454 */
2455 if (timer_next < tsf)
2456 timer_next = tsf + timer_period;
2457
2458 /*
2459 * Program generic timer registers
2460 */
2461 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2462 timer_next);
2463 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2464 timer_period);
2465 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2466 gen_tmr_configuration[timer->index].mode_mask);
2467
2468 /* Enable both trigger and thresh interrupt masks */
2469 REG_SET_BIT(ah, AR_IMR_S5,
2470 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2471 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 2472}
7322fd19 2473EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 2474
cd9bf689 2475void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 2476{
2477 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2478
2479 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2480 (timer->index >= ATH_MAX_GEN_TIMER)) {
2481 return;
2482 }
2483
2484 /* Clear generic timer enable bits. */
2485 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2486 gen_tmr_configuration[timer->index].mode_mask);
2487
2488 /* Disable both trigger and thresh interrupt masks */
2489 REG_CLR_BIT(ah, AR_IMR_S5,
2490 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2491 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2492
2493 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 2494}
7322fd19 2495EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 2496
2497void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2498{
2499 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2500
2501 /* free the hardware generic timer slot */
2502 timer_table->timers[timer->index] = NULL;
2503 kfree(timer);
2504}
7322fd19 2505EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 2506
2507/*
2508 * Generic Timer Interrupts handling
2509 */
2510void ath_gen_timer_isr(struct ath_hw *ah)
2511{
2512 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2513 struct ath_gen_timer *timer;
c46917bb 2514 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 2515 u32 trigger_mask, thresh_mask, index;
2516
2517 /* get hardware generic timer interrupt status */
2518 trigger_mask = ah->intr_gen_timer_trigger;
2519 thresh_mask = ah->intr_gen_timer_thresh;
2520 trigger_mask &= timer_table->timer_mask.val;
2521 thresh_mask &= timer_table->timer_mask.val;
2522
2523 trigger_mask &= ~thresh_mask;
2524
2525 while (thresh_mask) {
2526 index = rightmost_index(timer_table, &thresh_mask);
2527 timer = timer_table->timers[index];
2528 BUG_ON(!timer);
226afe68
JP		 2529 ath_dbg(common, ATH_DBG_HWTIMER,
2530 "TSF overflow for Gen timer %d\n", index);
ff155a45
VT		 2531 timer->overflow(timer->arg);
2532 }
2533
2534 while (trigger_mask) {
2535 index = rightmost_index(timer_table, &trigger_mask);
2536 timer = timer_table->timers[index];
2537 BUG_ON(!timer);
226afe68
JP		 2538 ath_dbg(common, ATH_DBG_HWTIMER,
2539 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 2540 timer->trigger(timer->arg);
2541 }
2542}
7322fd19 2543EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 2544
05020d23
S		 2545/********/
2546/* HTC */
2547/********/
2548
2549void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2550{
2551 ah->htc_reset_init = true;
2552}
2553EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2554
2da4f01a
LR		 2555static struct {
2556 u32 version;
2557 const char * name;
2558} ath_mac_bb_names[] = {
2559 /* Devices with external radios */
2560 { AR_SREV_VERSION_5416_PCI, "5416" },
2561 { AR_SREV_VERSION_5416_PCIE, "5418" },
2562 { AR_SREV_VERSION_9100, "9100" },
2563 { AR_SREV_VERSION_9160, "9160" },
2564 /* Single-chip solutions */
2565 { AR_SREV_VERSION_9280, "9280" },
2566 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 2567 { AR_SREV_VERSION_9287, "9287" },
2568 { AR_SREV_VERSION_9271, "9271" },
ec83903e 2569 { AR_SREV_VERSION_9300, "9300" },
8f06ca2c 2570 { AR_SREV_VERSION_9485, "9485" },
2da4f01a
LR		 2571};
2572
2573/* For devices with external radios */
2574static struct {
2575 u16 version;
2576 const char * name;
2577} ath_rf_names[] = {
2578 { 0, "5133" },
2579 { AR_RAD5133_SREV_MAJOR, "5133" },
2580 { AR_RAD5122_SREV_MAJOR, "5122" },
2581 { AR_RAD2133_SREV_MAJOR, "2133" },
2582 { AR_RAD2122_SREV_MAJOR, "2122" }
2583};
2584
2585/*
2586 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2587 */
f934c4d9 2588static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 2589{
2590 int i;
2591
2592 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2593 if (ath_mac_bb_names[i].version == mac_bb_version) {
2594 return ath_mac_bb_names[i].name;
2595 }
2596 }
2597
2598 return "????";
2599}
2da4f01a
LR		 2600
2601/*
2602 * Return the RF name. "????" is returned if the RF is unknown.
2603 * Used for devices with external radios.
2604 */
f934c4d9 2605static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 2606{
2607 int i;
2608
2609 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2610 if (ath_rf_names[i].version == rf_version) {
2611 return ath_rf_names[i].name;
2612 }
2613 }
2614
2615 return "????";
2616}
f934c4d9
LR		 2617
2618void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2619{
2620 int used;
2621
2622 /* chipsets >= AR9280 are single-chip */
7a37081e 2623 if (AR_SREV_9280_20_OR_LATER(ah)) {
f934c4d9
LR		 2624 used = snprintf(hw_name, len,
2625 "Atheros AR%s Rev:%x",
2626 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2627 ah->hw_version.macRev);
2628 }
2629 else {
2630 used = snprintf(hw_name, len,
2631 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2632 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2633 ah->hw_version.macRev,
2634 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2635 AR_RADIO_SREV_MAJOR)),
2636 ah->hw_version.phyRev);
2637 }
2638
2639 hw_name[used] = '\0';
2640}
2641EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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