Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/io.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
9d9779e7 | 19 | #include <linux/module.h> |
f078f209 LR |
20 | #include <asm/unaligned.h> |
21 | ||
af03abec | 22 | #include "hw.h" |
d70357d5 | 23 | #include "hw-ops.h" |
cfe8cba9 | 24 | #include "rc.h" |
b622a720 | 25 | #include "ar9003_mac.h" |
f4701b5a | 26 | #include "ar9003_mci.h" |
f078f209 | 27 | |
cbe61d8a | 28 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); |
f078f209 | 29 | |
7322fd19 LR |
30 | MODULE_AUTHOR("Atheros Communications"); |
31 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
32 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
33 | MODULE_LICENSE("Dual BSD/GPL"); | |
34 | ||
35 | static int __init ath9k_init(void) | |
36 | { | |
37 | return 0; | |
38 | } | |
39 | module_init(ath9k_init); | |
40 | ||
41 | static void __exit ath9k_exit(void) | |
42 | { | |
43 | return; | |
44 | } | |
45 | module_exit(ath9k_exit); | |
46 | ||
d70357d5 LR |
47 | /* Private hardware callbacks */ |
48 | ||
49 | static void ath9k_hw_init_cal_settings(struct ath_hw *ah) | |
50 | { | |
51 | ath9k_hw_private_ops(ah)->init_cal_settings(ah); | |
52 | } | |
53 | ||
54 | static void ath9k_hw_init_mode_regs(struct ath_hw *ah) | |
55 | { | |
56 | ath9k_hw_private_ops(ah)->init_mode_regs(ah); | |
57 | } | |
58 | ||
64773964 LR |
59 | static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, |
60 | struct ath9k_channel *chan) | |
61 | { | |
62 | return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); | |
63 | } | |
64 | ||
991312d8 LR |
65 | static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) |
66 | { | |
67 | if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) | |
68 | return; | |
69 | ||
70 | ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); | |
71 | } | |
72 | ||
e36b27af LR |
73 | static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah) |
74 | { | |
75 | /* You will not have this callback if using the old ANI */ | |
76 | if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs) | |
77 | return; | |
78 | ||
79 | ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah); | |
80 | } | |
81 | ||
f1dc5600 S |
82 | /********************/ |
83 | /* Helper Functions */ | |
84 | /********************/ | |
f078f209 | 85 | |
dfdac8ac | 86 | static void ath9k_hw_set_clockrate(struct ath_hw *ah) |
f1dc5600 | 87 | { |
b002a4a9 | 88 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
dfdac8ac FF |
89 | struct ath_common *common = ath9k_hw_common(ah); |
90 | unsigned int clockrate; | |
cbe61d8a | 91 | |
087b6ff6 FF |
92 | /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */ |
93 | if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) | |
94 | clockrate = 117; | |
95 | else if (!ah->curchan) /* should really check for CCK instead */ | |
dfdac8ac FF |
96 | clockrate = ATH9K_CLOCK_RATE_CCK; |
97 | else if (conf->channel->band == IEEE80211_BAND_2GHZ) | |
98 | clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM; | |
99 | else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) | |
100 | clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM; | |
e5553724 | 101 | else |
dfdac8ac FF |
102 | clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM; |
103 | ||
104 | if (conf_is_ht40(conf)) | |
105 | clockrate *= 2; | |
106 | ||
906c7205 FF |
107 | if (ah->curchan) { |
108 | if (IS_CHAN_HALF_RATE(ah->curchan)) | |
109 | clockrate /= 2; | |
110 | if (IS_CHAN_QUARTER_RATE(ah->curchan)) | |
111 | clockrate /= 4; | |
112 | } | |
113 | ||
dfdac8ac | 114 | common->clockrate = clockrate; |
f1dc5600 S |
115 | } |
116 | ||
cbe61d8a | 117 | static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) |
f1dc5600 | 118 | { |
dfdac8ac | 119 | struct ath_common *common = ath9k_hw_common(ah); |
cbe61d8a | 120 | |
dfdac8ac | 121 | return usecs * common->clockrate; |
f1dc5600 | 122 | } |
f078f209 | 123 | |
0caa7b14 | 124 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) |
f078f209 LR |
125 | { |
126 | int i; | |
127 | ||
0caa7b14 S |
128 | BUG_ON(timeout < AH_TIME_QUANTUM); |
129 | ||
130 | for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { | |
f078f209 LR |
131 | if ((REG_READ(ah, reg) & mask) == val) |
132 | return true; | |
133 | ||
134 | udelay(AH_TIME_QUANTUM); | |
135 | } | |
04bd4638 | 136 | |
d2182b69 | 137 | ath_dbg(ath9k_hw_common(ah), ANY, |
226afe68 JP |
138 | "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", |
139 | timeout, reg, REG_READ(ah, reg), mask, val); | |
f078f209 | 140 | |
f1dc5600 | 141 | return false; |
f078f209 | 142 | } |
7322fd19 | 143 | EXPORT_SYMBOL(ath9k_hw_wait); |
f078f209 | 144 | |
a9b6b256 FF |
145 | void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array, |
146 | int column, unsigned int *writecnt) | |
147 | { | |
148 | int r; | |
149 | ||
150 | ENABLE_REGWRITE_BUFFER(ah); | |
151 | for (r = 0; r < array->ia_rows; r++) { | |
152 | REG_WRITE(ah, INI_RA(array, r, 0), | |
153 | INI_RA(array, r, column)); | |
154 | DO_DELAY(*writecnt); | |
155 | } | |
156 | REGWRITE_BUFFER_FLUSH(ah); | |
157 | } | |
158 | ||
f078f209 LR |
159 | u32 ath9k_hw_reverse_bits(u32 val, u32 n) |
160 | { | |
161 | u32 retval; | |
162 | int i; | |
163 | ||
164 | for (i = 0, retval = 0; i < n; i++) { | |
165 | retval = (retval << 1) | (val & 1); | |
166 | val >>= 1; | |
167 | } | |
168 | return retval; | |
169 | } | |
170 | ||
cbe61d8a | 171 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
545750d3 | 172 | u8 phy, int kbps, |
f1dc5600 S |
173 | u32 frameLen, u16 rateix, |
174 | bool shortPreamble) | |
f078f209 | 175 | { |
f1dc5600 | 176 | u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; |
f078f209 | 177 | |
f1dc5600 S |
178 | if (kbps == 0) |
179 | return 0; | |
f078f209 | 180 | |
545750d3 | 181 | switch (phy) { |
46d14a58 | 182 | case WLAN_RC_PHY_CCK: |
f1dc5600 | 183 | phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; |
545750d3 | 184 | if (shortPreamble) |
f1dc5600 S |
185 | phyTime >>= 1; |
186 | numBits = frameLen << 3; | |
187 | txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); | |
188 | break; | |
46d14a58 | 189 | case WLAN_RC_PHY_OFDM: |
2660b81a | 190 | if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { |
f1dc5600 S |
191 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; |
192 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
193 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
194 | txTime = OFDM_SIFS_TIME_QUARTER | |
195 | + OFDM_PREAMBLE_TIME_QUARTER | |
196 | + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); | |
2660b81a S |
197 | } else if (ah->curchan && |
198 | IS_CHAN_HALF_RATE(ah->curchan)) { | |
f1dc5600 S |
199 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; |
200 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
201 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
202 | txTime = OFDM_SIFS_TIME_HALF + | |
203 | OFDM_PREAMBLE_TIME_HALF | |
204 | + (numSymbols * OFDM_SYMBOL_TIME_HALF); | |
205 | } else { | |
206 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; | |
207 | numBits = OFDM_PLCP_BITS + (frameLen << 3); | |
208 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); | |
209 | txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME | |
210 | + (numSymbols * OFDM_SYMBOL_TIME); | |
211 | } | |
212 | break; | |
213 | default: | |
3800276a JP |
214 | ath_err(ath9k_hw_common(ah), |
215 | "Unknown phy %u (rate ix %u)\n", phy, rateix); | |
f1dc5600 S |
216 | txTime = 0; |
217 | break; | |
218 | } | |
f078f209 | 219 | |
f1dc5600 S |
220 | return txTime; |
221 | } | |
7322fd19 | 222 | EXPORT_SYMBOL(ath9k_hw_computetxtime); |
f078f209 | 223 | |
cbe61d8a | 224 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
f1dc5600 S |
225 | struct ath9k_channel *chan, |
226 | struct chan_centers *centers) | |
f078f209 | 227 | { |
f1dc5600 | 228 | int8_t extoff; |
f078f209 | 229 | |
f1dc5600 S |
230 | if (!IS_CHAN_HT40(chan)) { |
231 | centers->ctl_center = centers->ext_center = | |
232 | centers->synth_center = chan->channel; | |
233 | return; | |
f078f209 | 234 | } |
f078f209 | 235 | |
f1dc5600 S |
236 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || |
237 | (chan->chanmode == CHANNEL_G_HT40PLUS)) { | |
238 | centers->synth_center = | |
239 | chan->channel + HT40_CHANNEL_CENTER_SHIFT; | |
240 | extoff = 1; | |
241 | } else { | |
242 | centers->synth_center = | |
243 | chan->channel - HT40_CHANNEL_CENTER_SHIFT; | |
244 | extoff = -1; | |
245 | } | |
f078f209 | 246 | |
f1dc5600 S |
247 | centers->ctl_center = |
248 | centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); | |
6420014c | 249 | /* 25 MHz spacing is supported by hw but not on upper layers */ |
f1dc5600 | 250 | centers->ext_center = |
6420014c | 251 | centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); |
f078f209 LR |
252 | } |
253 | ||
f1dc5600 S |
254 | /******************/ |
255 | /* Chip Revisions */ | |
256 | /******************/ | |
257 | ||
cbe61d8a | 258 | static void ath9k_hw_read_revisions(struct ath_hw *ah) |
f078f209 | 259 | { |
f1dc5600 | 260 | u32 val; |
f078f209 | 261 | |
ecb1d385 VT |
262 | switch (ah->hw_version.devid) { |
263 | case AR5416_AR9100_DEVID: | |
264 | ah->hw_version.macVersion = AR_SREV_VERSION_9100; | |
265 | break; | |
3762561a GJ |
266 | case AR9300_DEVID_AR9330: |
267 | ah->hw_version.macVersion = AR_SREV_VERSION_9330; | |
268 | if (ah->get_mac_revision) { | |
269 | ah->hw_version.macRev = ah->get_mac_revision(); | |
270 | } else { | |
271 | val = REG_READ(ah, AR_SREV); | |
272 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); | |
273 | } | |
274 | return; | |
ecb1d385 VT |
275 | case AR9300_DEVID_AR9340: |
276 | ah->hw_version.macVersion = AR_SREV_VERSION_9340; | |
277 | val = REG_READ(ah, AR_SREV); | |
278 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); | |
279 | return; | |
280 | } | |
281 | ||
f1dc5600 | 282 | val = REG_READ(ah, AR_SREV) & AR_SREV_ID; |
f078f209 | 283 | |
f1dc5600 S |
284 | if (val == 0xFF) { |
285 | val = REG_READ(ah, AR_SREV); | |
d535a42a S |
286 | ah->hw_version.macVersion = |
287 | (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; | |
288 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); | |
76ed94be | 289 | |
423e38e8 | 290 | if (AR_SREV_9462(ah)) |
76ed94be MSS |
291 | ah->is_pciexpress = true; |
292 | else | |
293 | ah->is_pciexpress = (val & | |
294 | AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; | |
f1dc5600 S |
295 | } else { |
296 | if (!AR_SREV_9100(ah)) | |
d535a42a | 297 | ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); |
f078f209 | 298 | |
d535a42a | 299 | ah->hw_version.macRev = val & AR_SREV_REVISION; |
f078f209 | 300 | |
d535a42a | 301 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) |
2660b81a | 302 | ah->is_pciexpress = true; |
f1dc5600 | 303 | } |
f078f209 LR |
304 | } |
305 | ||
f1dc5600 S |
306 | /************************************/ |
307 | /* HW Attach, Detach, Init Routines */ | |
308 | /************************************/ | |
309 | ||
cbe61d8a | 310 | static void ath9k_hw_disablepcie(struct ath_hw *ah) |
f078f209 | 311 | { |
040b74f7 | 312 | if (!AR_SREV_5416(ah)) |
f1dc5600 | 313 | return; |
f078f209 | 314 | |
f1dc5600 S |
315 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); |
316 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); | |
317 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); | |
318 | REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); | |
319 | REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); | |
320 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); | |
321 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); | |
322 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); | |
323 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); | |
f078f209 | 324 | |
f1dc5600 | 325 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
f078f209 LR |
326 | } |
327 | ||
d4930086 SG |
328 | static void ath9k_hw_aspm_init(struct ath_hw *ah) |
329 | { | |
330 | struct ath_common *common = ath9k_hw_common(ah); | |
331 | ||
332 | if (common->bus_ops->aspm_init) | |
333 | common->bus_ops->aspm_init(common); | |
334 | } | |
335 | ||
1f3f0618 | 336 | /* This should work for all families including legacy */ |
cbe61d8a | 337 | static bool ath9k_hw_chip_test(struct ath_hw *ah) |
f078f209 | 338 | { |
c46917bb | 339 | struct ath_common *common = ath9k_hw_common(ah); |
1f3f0618 | 340 | u32 regAddr[2] = { AR_STA_ID0 }; |
f1dc5600 | 341 | u32 regHold[2]; |
07b2fa5a JP |
342 | static const u32 patternData[4] = { |
343 | 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 | |
344 | }; | |
1f3f0618 | 345 | int i, j, loop_max; |
f078f209 | 346 | |
1f3f0618 SB |
347 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
348 | loop_max = 2; | |
349 | regAddr[1] = AR_PHY_BASE + (8 << 2); | |
350 | } else | |
351 | loop_max = 1; | |
352 | ||
353 | for (i = 0; i < loop_max; i++) { | |
f1dc5600 S |
354 | u32 addr = regAddr[i]; |
355 | u32 wrData, rdData; | |
f078f209 | 356 | |
f1dc5600 S |
357 | regHold[i] = REG_READ(ah, addr); |
358 | for (j = 0; j < 0x100; j++) { | |
359 | wrData = (j << 16) | j; | |
360 | REG_WRITE(ah, addr, wrData); | |
361 | rdData = REG_READ(ah, addr); | |
362 | if (rdData != wrData) { | |
3800276a JP |
363 | ath_err(common, |
364 | "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", | |
365 | addr, wrData, rdData); | |
f1dc5600 S |
366 | return false; |
367 | } | |
368 | } | |
369 | for (j = 0; j < 4; j++) { | |
370 | wrData = patternData[j]; | |
371 | REG_WRITE(ah, addr, wrData); | |
372 | rdData = REG_READ(ah, addr); | |
373 | if (wrData != rdData) { | |
3800276a JP |
374 | ath_err(common, |
375 | "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", | |
376 | addr, wrData, rdData); | |
f1dc5600 S |
377 | return false; |
378 | } | |
f078f209 | 379 | } |
f1dc5600 | 380 | REG_WRITE(ah, regAddr[i], regHold[i]); |
f078f209 | 381 | } |
f1dc5600 | 382 | udelay(100); |
cbe61d8a | 383 | |
f078f209 LR |
384 | return true; |
385 | } | |
386 | ||
b8b0f377 | 387 | static void ath9k_hw_init_config(struct ath_hw *ah) |
f1dc5600 S |
388 | { |
389 | int i; | |
f078f209 | 390 | |
2660b81a S |
391 | ah->config.dma_beacon_response_time = 2; |
392 | ah->config.sw_beacon_response_time = 10; | |
393 | ah->config.additional_swba_backoff = 0; | |
394 | ah->config.ack_6mb = 0x0; | |
395 | ah->config.cwm_ignore_extcca = 0; | |
2660b81a | 396 | ah->config.pcie_clock_req = 0; |
2660b81a S |
397 | ah->config.pcie_waen = 0; |
398 | ah->config.analog_shiftreg = 1; | |
03c72518 | 399 | ah->config.enable_ani = true; |
f078f209 | 400 | |
f1dc5600 | 401 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
2660b81a S |
402 | ah->config.spurchans[i][0] = AR_NO_SPUR; |
403 | ah->config.spurchans[i][1] = AR_NO_SPUR; | |
f078f209 LR |
404 | } |
405 | ||
6f481010 LR |
406 | /* PAPRD needs some more work to be enabled */ |
407 | ah->config.paprd_disable = 1; | |
408 | ||
0ce024cb | 409 | ah->config.rx_intr_mitigation = true; |
6a0ec30a | 410 | ah->config.pcieSerDesWrite = true; |
6158425b LR |
411 | |
412 | /* | |
413 | * We need this for PCI devices only (Cardbus, PCI, miniPCI) | |
414 | * _and_ if on non-uniprocessor systems (Multiprocessor/HT). | |
415 | * This means we use it for all AR5416 devices, and the few | |
416 | * minor PCI AR9280 devices out there. | |
417 | * | |
418 | * Serialization is required because these devices do not handle | |
419 | * well the case of two concurrent reads/writes due to the latency | |
420 | * involved. During one read/write another read/write can be issued | |
421 | * on another CPU while the previous read/write may still be working | |
422 | * on our hardware, if we hit this case the hardware poops in a loop. | |
423 | * We prevent this by serializing reads and writes. | |
424 | * | |
425 | * This issue is not present on PCI-Express devices or pre-AR5416 | |
426 | * devices (legacy, 802.11abg). | |
427 | */ | |
428 | if (num_possible_cpus() > 1) | |
2d6a5e95 | 429 | ah->config.serialize_regmode = SER_REG_MODE_AUTO; |
f078f209 LR |
430 | } |
431 | ||
50aca25b | 432 | static void ath9k_hw_init_defaults(struct ath_hw *ah) |
f078f209 | 433 | { |
608b88cb LR |
434 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
435 | ||
436 | regulatory->country_code = CTRY_DEFAULT; | |
437 | regulatory->power_limit = MAX_RATE_POWER; | |
608b88cb | 438 | |
d535a42a | 439 | ah->hw_version.magic = AR5416_MAGIC; |
d535a42a | 440 | ah->hw_version.subvendorid = 0; |
f078f209 | 441 | |
2660b81a | 442 | ah->atim_window = 0; |
16f2411f FF |
443 | ah->sta_id1_defaults = |
444 | AR_STA_ID1_CRPT_MIC_ENABLE | | |
445 | AR_STA_ID1_MCAST_KSRCH; | |
f171760c FF |
446 | if (AR_SREV_9100(ah)) |
447 | ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; | |
2660b81a | 448 | ah->enable_32kHz_clock = DONT_USE_32KHZ; |
e3f2acc7 | 449 | ah->slottime = ATH9K_SLOT_TIME_9; |
2660b81a | 450 | ah->globaltxtimeout = (u32) -1; |
cbdec975 | 451 | ah->power_mode = ATH9K_PM_UNDEFINED; |
f078f209 LR |
452 | } |
453 | ||
cbe61d8a | 454 | static int ath9k_hw_init_macaddr(struct ath_hw *ah) |
f078f209 | 455 | { |
1510718d | 456 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 LR |
457 | u32 sum; |
458 | int i; | |
459 | u16 eeval; | |
07b2fa5a | 460 | static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; |
f078f209 LR |
461 | |
462 | sum = 0; | |
463 | for (i = 0; i < 3; i++) { | |
49101676 | 464 | eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); |
f078f209 | 465 | sum += eeval; |
1510718d LR |
466 | common->macaddr[2 * i] = eeval >> 8; |
467 | common->macaddr[2 * i + 1] = eeval & 0xff; | |
f078f209 | 468 | } |
d8baa939 | 469 | if (sum == 0 || sum == 0xffff * 3) |
f078f209 | 470 | return -EADDRNOTAVAIL; |
f078f209 LR |
471 | |
472 | return 0; | |
473 | } | |
474 | ||
f637cfd6 | 475 | static int ath9k_hw_post_init(struct ath_hw *ah) |
f078f209 | 476 | { |
6cae913d | 477 | struct ath_common *common = ath9k_hw_common(ah); |
f1dc5600 | 478 | int ecode; |
f078f209 | 479 | |
6cae913d | 480 | if (common->bus_ops->ath_bus_type != ATH_USB) { |
527d485f S |
481 | if (!ath9k_hw_chip_test(ah)) |
482 | return -ENODEV; | |
483 | } | |
f078f209 | 484 | |
ebd5a14a LR |
485 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
486 | ecode = ar9002_hw_rf_claim(ah); | |
487 | if (ecode != 0) | |
488 | return ecode; | |
489 | } | |
f078f209 | 490 | |
f637cfd6 | 491 | ecode = ath9k_hw_eeprom_init(ah); |
f1dc5600 S |
492 | if (ecode != 0) |
493 | return ecode; | |
7d01b221 | 494 | |
d2182b69 | 495 | ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", |
226afe68 JP |
496 | ah->eep_ops->get_eeprom_ver(ah), |
497 | ah->eep_ops->get_eeprom_rev(ah)); | |
7d01b221 | 498 | |
8fe65368 LR |
499 | ecode = ath9k_hw_rf_alloc_ext_banks(ah); |
500 | if (ecode) { | |
3800276a JP |
501 | ath_err(ath9k_hw_common(ah), |
502 | "Failed allocating banks for external radio\n"); | |
48a7c3df | 503 | ath9k_hw_rf_free_ext_banks(ah); |
8fe65368 | 504 | return ecode; |
574d6b12 | 505 | } |
f078f209 | 506 | |
4279425c | 507 | if (ah->config.enable_ani) { |
f1dc5600 | 508 | ath9k_hw_ani_setup(ah); |
f637cfd6 | 509 | ath9k_hw_ani_init(ah); |
f078f209 LR |
510 | } |
511 | ||
f078f209 LR |
512 | return 0; |
513 | } | |
514 | ||
8525f280 | 515 | static void ath9k_hw_attach_ops(struct ath_hw *ah) |
ee2bb460 | 516 | { |
8525f280 LR |
517 | if (AR_SREV_9300_20_OR_LATER(ah)) |
518 | ar9003_hw_attach_ops(ah); | |
519 | else | |
520 | ar9002_hw_attach_ops(ah); | |
aa4058ae LR |
521 | } |
522 | ||
d70357d5 LR |
523 | /* Called for all hardware families */ |
524 | static int __ath9k_hw_init(struct ath_hw *ah) | |
aa4058ae | 525 | { |
c46917bb | 526 | struct ath_common *common = ath9k_hw_common(ah); |
95fafca2 | 527 | int r = 0; |
aa4058ae | 528 | |
ac45c12d SB |
529 | ath9k_hw_read_revisions(ah); |
530 | ||
0a8d7cb0 SB |
531 | /* |
532 | * Read back AR_WA into a permanent copy and set bits 14 and 17. | |
533 | * We need to do this to avoid RMW of this register. We cannot | |
534 | * read the reg when chip is asleep. | |
535 | */ | |
536 | ah->WARegVal = REG_READ(ah, AR_WA); | |
537 | ah->WARegVal |= (AR_WA_D3_L1_DISABLE | | |
538 | AR_WA_ASPM_TIMER_BASED_DISABLE); | |
539 | ||
aa4058ae | 540 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { |
3800276a | 541 | ath_err(common, "Couldn't reset chip\n"); |
95fafca2 | 542 | return -EIO; |
aa4058ae LR |
543 | } |
544 | ||
423e38e8 | 545 | if (AR_SREV_9462(ah)) |
eec353c5 RM |
546 | ah->WARegVal &= ~AR_WA_D3_L1_DISABLE; |
547 | ||
bab1f62e LR |
548 | ath9k_hw_init_defaults(ah); |
549 | ath9k_hw_init_config(ah); | |
550 | ||
8525f280 | 551 | ath9k_hw_attach_ops(ah); |
d70357d5 | 552 | |
9ecdef4b | 553 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { |
3800276a | 554 | ath_err(common, "Couldn't wakeup chip\n"); |
95fafca2 | 555 | return -EIO; |
aa4058ae LR |
556 | } |
557 | ||
558 | if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { | |
559 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || | |
4c85ab11 JL |
560 | ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) && |
561 | !ah->is_pciexpress)) { | |
aa4058ae LR |
562 | ah->config.serialize_regmode = |
563 | SER_REG_MODE_ON; | |
564 | } else { | |
565 | ah->config.serialize_regmode = | |
566 | SER_REG_MODE_OFF; | |
567 | } | |
568 | } | |
569 | ||
d2182b69 | 570 | ath_dbg(common, RESET, "serialize_regmode is %d\n", |
aa4058ae LR |
571 | ah->config.serialize_regmode); |
572 | ||
f4709fdf LR |
573 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
574 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; | |
575 | else | |
576 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; | |
577 | ||
6da5a720 FF |
578 | switch (ah->hw_version.macVersion) { |
579 | case AR_SREV_VERSION_5416_PCI: | |
580 | case AR_SREV_VERSION_5416_PCIE: | |
581 | case AR_SREV_VERSION_9160: | |
582 | case AR_SREV_VERSION_9100: | |
583 | case AR_SREV_VERSION_9280: | |
584 | case AR_SREV_VERSION_9285: | |
585 | case AR_SREV_VERSION_9287: | |
586 | case AR_SREV_VERSION_9271: | |
587 | case AR_SREV_VERSION_9300: | |
2c8e5937 | 588 | case AR_SREV_VERSION_9330: |
6da5a720 | 589 | case AR_SREV_VERSION_9485: |
bca04689 | 590 | case AR_SREV_VERSION_9340: |
423e38e8 | 591 | case AR_SREV_VERSION_9462: |
6da5a720 FF |
592 | break; |
593 | default: | |
3800276a JP |
594 | ath_err(common, |
595 | "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", | |
596 | ah->hw_version.macVersion, ah->hw_version.macRev); | |
95fafca2 | 597 | return -EOPNOTSUPP; |
aa4058ae LR |
598 | } |
599 | ||
2c8e5937 GJ |
600 | if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || |
601 | AR_SREV_9330(ah)) | |
d7e7d229 LR |
602 | ah->is_pciexpress = false; |
603 | ||
aa4058ae | 604 | ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); |
aa4058ae LR |
605 | ath9k_hw_init_cal_settings(ah); |
606 | ||
607 | ah->ani_function = ATH9K_ANI_ALL; | |
7a37081e | 608 | if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
aa4058ae | 609 | ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; |
e36b27af LR |
610 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
611 | ah->ani_function &= ~ATH9K_ANI_MRC_CCK; | |
aa4058ae | 612 | |
4f17c48e NM |
613 | /* disable ANI for 9340 */ |
614 | if (AR_SREV_9340(ah)) | |
4279425c NM |
615 | ah->config.enable_ani = false; |
616 | ||
aa4058ae LR |
617 | ath9k_hw_init_mode_regs(ah); |
618 | ||
69ce674b | 619 | if (!ah->is_pciexpress) |
aa4058ae LR |
620 | ath9k_hw_disablepcie(ah); |
621 | ||
d8f492b7 LR |
622 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
623 | ar9002_hw_cck_chan14_spread(ah); | |
193cd458 | 624 | |
f637cfd6 | 625 | r = ath9k_hw_post_init(ah); |
aa4058ae | 626 | if (r) |
95fafca2 | 627 | return r; |
aa4058ae LR |
628 | |
629 | ath9k_hw_init_mode_gain_regs(ah); | |
a9a29ce6 GJ |
630 | r = ath9k_hw_fill_cap_info(ah); |
631 | if (r) | |
632 | return r; | |
633 | ||
69ce674b SG |
634 | if (ah->is_pciexpress) |
635 | ath9k_hw_aspm_init(ah); | |
636 | ||
4f3acf81 LR |
637 | r = ath9k_hw_init_macaddr(ah); |
638 | if (r) { | |
3800276a | 639 | ath_err(common, "Failed to initialize MAC address\n"); |
95fafca2 | 640 | return r; |
f078f209 LR |
641 | } |
642 | ||
d7e7d229 | 643 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
2660b81a | 644 | ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); |
f1dc5600 | 645 | else |
2660b81a | 646 | ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); |
f078f209 | 647 | |
88e641df GJ |
648 | if (AR_SREV_9330(ah)) |
649 | ah->bb_watchdog_timeout_ms = 85; | |
650 | else | |
651 | ah->bb_watchdog_timeout_ms = 25; | |
f078f209 | 652 | |
211f5859 LR |
653 | common->state = ATH_HW_INITIALIZED; |
654 | ||
4f3acf81 | 655 | return 0; |
f078f209 LR |
656 | } |
657 | ||
d70357d5 | 658 | int ath9k_hw_init(struct ath_hw *ah) |
f078f209 | 659 | { |
d70357d5 LR |
660 | int ret; |
661 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 | 662 | |
d70357d5 LR |
663 | /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ |
664 | switch (ah->hw_version.devid) { | |
665 | case AR5416_DEVID_PCI: | |
666 | case AR5416_DEVID_PCIE: | |
667 | case AR5416_AR9100_DEVID: | |
668 | case AR9160_DEVID_PCI: | |
669 | case AR9280_DEVID_PCI: | |
670 | case AR9280_DEVID_PCIE: | |
671 | case AR9285_DEVID_PCIE: | |
db3cc53a SB |
672 | case AR9287_DEVID_PCI: |
673 | case AR9287_DEVID_PCIE: | |
d70357d5 | 674 | case AR2427_DEVID_PCIE: |
db3cc53a | 675 | case AR9300_DEVID_PCIE: |
3050c914 | 676 | case AR9300_DEVID_AR9485_PCIE: |
999a7a88 | 677 | case AR9300_DEVID_AR9330: |
bca04689 | 678 | case AR9300_DEVID_AR9340: |
5a63ef0f | 679 | case AR9300_DEVID_AR9580: |
423e38e8 | 680 | case AR9300_DEVID_AR9462: |
d70357d5 LR |
681 | break; |
682 | default: | |
683 | if (common->bus_ops->ath_bus_type == ATH_USB) | |
684 | break; | |
3800276a JP |
685 | ath_err(common, "Hardware device ID 0x%04x not supported\n", |
686 | ah->hw_version.devid); | |
d70357d5 LR |
687 | return -EOPNOTSUPP; |
688 | } | |
f078f209 | 689 | |
d70357d5 LR |
690 | ret = __ath9k_hw_init(ah); |
691 | if (ret) { | |
3800276a JP |
692 | ath_err(common, |
693 | "Unable to initialize hardware; initialization status: %d\n", | |
694 | ret); | |
d70357d5 LR |
695 | return ret; |
696 | } | |
f078f209 | 697 | |
d70357d5 | 698 | return 0; |
f078f209 | 699 | } |
d70357d5 | 700 | EXPORT_SYMBOL(ath9k_hw_init); |
f078f209 | 701 | |
cbe61d8a | 702 | static void ath9k_hw_init_qos(struct ath_hw *ah) |
f078f209 | 703 | { |
7d0d0df0 S |
704 | ENABLE_REGWRITE_BUFFER(ah); |
705 | ||
f1dc5600 S |
706 | REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); |
707 | REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); | |
f078f209 | 708 | |
f1dc5600 S |
709 | REG_WRITE(ah, AR_QOS_NO_ACK, |
710 | SM(2, AR_QOS_NO_ACK_TWO_BIT) | | |
711 | SM(5, AR_QOS_NO_ACK_BIT_OFF) | | |
712 | SM(0, AR_QOS_NO_ACK_BYTE_OFF)); | |
713 | ||
714 | REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); | |
715 | REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); | |
716 | REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); | |
717 | REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); | |
718 | REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); | |
7d0d0df0 S |
719 | |
720 | REGWRITE_BUFFER_FLUSH(ah); | |
f078f209 LR |
721 | } |
722 | ||
b84628eb | 723 | u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) |
b1415819 | 724 | { |
ca7a4deb FF |
725 | REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); |
726 | udelay(100); | |
727 | REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); | |
b1415819 | 728 | |
ca7a4deb FF |
729 | while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) |
730 | udelay(100); | |
b1415819 | 731 | |
ca7a4deb | 732 | return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; |
b1415819 VN |
733 | } |
734 | EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); | |
735 | ||
cbe61d8a | 736 | static void ath9k_hw_init_pll(struct ath_hw *ah, |
f1dc5600 | 737 | struct ath9k_channel *chan) |
f078f209 | 738 | { |
d09b17f7 VT |
739 | u32 pll; |
740 | ||
22983c30 | 741 | if (AR_SREV_9485(ah)) { |
22983c30 | 742 | |
3dfd7f60 VT |
743 | /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ |
744 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | |
745 | AR_CH0_BB_DPLL2_PLL_PWD, 0x1); | |
746 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | |
747 | AR_CH0_DPLL2_KD, 0x40); | |
748 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | |
749 | AR_CH0_DPLL2_KI, 0x4); | |
22983c30 | 750 | |
3dfd7f60 VT |
751 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, |
752 | AR_CH0_BB_DPLL1_REFDIV, 0x5); | |
753 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, | |
754 | AR_CH0_BB_DPLL1_NINI, 0x58); | |
755 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, | |
756 | AR_CH0_BB_DPLL1_NFRAC, 0x0); | |
22983c30 VN |
757 | |
758 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | |
3dfd7f60 VT |
759 | AR_CH0_BB_DPLL2_OUTDIV, 0x1); |
760 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | |
761 | AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); | |
22983c30 | 762 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, |
3dfd7f60 | 763 | AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); |
22983c30 | 764 | |
3dfd7f60 | 765 | /* program BB PLL phase_shift to 0x6 */ |
22983c30 | 766 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, |
3dfd7f60 VT |
767 | AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); |
768 | ||
769 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, | |
770 | AR_CH0_BB_DPLL2_PLL_PWD, 0x0); | |
75e03512 | 771 | udelay(1000); |
a5415d62 GJ |
772 | } else if (AR_SREV_9330(ah)) { |
773 | u32 ddr_dpll2, pll_control2, kd; | |
774 | ||
775 | if (ah->is_clk_25mhz) { | |
776 | ddr_dpll2 = 0x18e82f01; | |
777 | pll_control2 = 0xe04a3d; | |
778 | kd = 0x1d; | |
779 | } else { | |
780 | ddr_dpll2 = 0x19e82f01; | |
781 | pll_control2 = 0x886666; | |
782 | kd = 0x3d; | |
783 | } | |
784 | ||
785 | /* program DDR PLL ki and kd value */ | |
786 | REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); | |
787 | ||
788 | /* program DDR PLL phase_shift */ | |
789 | REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, | |
790 | AR_CH0_DPLL3_PHASE_SHIFT, 0x1); | |
791 | ||
792 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); | |
793 | udelay(1000); | |
794 | ||
795 | /* program refdiv, nint, frac to RTC register */ | |
796 | REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); | |
797 | ||
798 | /* program BB PLL kd and ki value */ | |
799 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); | |
800 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); | |
801 | ||
802 | /* program BB PLL phase_shift */ | |
803 | REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, | |
804 | AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); | |
0b488ac6 VT |
805 | } else if (AR_SREV_9340(ah)) { |
806 | u32 regval, pll2_divint, pll2_divfrac, refdiv; | |
807 | ||
808 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); | |
809 | udelay(1000); | |
810 | ||
811 | REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); | |
812 | udelay(100); | |
813 | ||
814 | if (ah->is_clk_25mhz) { | |
815 | pll2_divint = 0x54; | |
816 | pll2_divfrac = 0x1eb85; | |
817 | refdiv = 3; | |
818 | } else { | |
819 | pll2_divint = 88; | |
820 | pll2_divfrac = 0; | |
821 | refdiv = 5; | |
822 | } | |
823 | ||
824 | regval = REG_READ(ah, AR_PHY_PLL_MODE); | |
825 | regval |= (0x1 << 16); | |
826 | REG_WRITE(ah, AR_PHY_PLL_MODE, regval); | |
827 | udelay(100); | |
828 | ||
829 | REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | | |
830 | (pll2_divint << 18) | pll2_divfrac); | |
831 | udelay(100); | |
832 | ||
833 | regval = REG_READ(ah, AR_PHY_PLL_MODE); | |
834 | regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) | | |
835 | (0x4 << 26) | (0x18 << 19); | |
836 | REG_WRITE(ah, AR_PHY_PLL_MODE, regval); | |
837 | REG_WRITE(ah, AR_PHY_PLL_MODE, | |
838 | REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); | |
839 | udelay(1000); | |
22983c30 | 840 | } |
d09b17f7 VT |
841 | |
842 | pll = ath9k_hw_compute_pll_control(ah, chan); | |
f078f209 | 843 | |
d03a66c1 | 844 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); |
f078f209 | 845 | |
a5415d62 | 846 | if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah)) |
3dfd7f60 VT |
847 | udelay(1000); |
848 | ||
c75724d1 LR |
849 | /* Switch the core clock for ar9271 to 117Mhz */ |
850 | if (AR_SREV_9271(ah)) { | |
25e2ab17 S |
851 | udelay(500); |
852 | REG_WRITE(ah, 0x50040, 0x304); | |
c75724d1 LR |
853 | } |
854 | ||
f1dc5600 S |
855 | udelay(RTC_PLL_SETTLE_DELAY); |
856 | ||
857 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); | |
0b488ac6 VT |
858 | |
859 | if (AR_SREV_9340(ah)) { | |
860 | if (ah->is_clk_25mhz) { | |
861 | REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); | |
862 | REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); | |
863 | REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); | |
864 | } else { | |
865 | REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); | |
866 | REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); | |
867 | REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); | |
868 | } | |
869 | udelay(100); | |
870 | } | |
f078f209 LR |
871 | } |
872 | ||
cbe61d8a | 873 | static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, |
d97809db | 874 | enum nl80211_iftype opmode) |
f078f209 | 875 | { |
79d1d2b8 | 876 | u32 sync_default = AR_INTR_SYNC_DEFAULT; |
152d530d | 877 | u32 imr_reg = AR_IMR_TXERR | |
f1dc5600 S |
878 | AR_IMR_TXURN | |
879 | AR_IMR_RXERR | | |
880 | AR_IMR_RXORN | | |
881 | AR_IMR_BCNMISC; | |
f078f209 | 882 | |
79d1d2b8 VT |
883 | if (AR_SREV_9340(ah)) |
884 | sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; | |
885 | ||
66860240 VT |
886 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
887 | imr_reg |= AR_IMR_RXOK_HP; | |
888 | if (ah->config.rx_intr_mitigation) | |
889 | imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; | |
890 | else | |
891 | imr_reg |= AR_IMR_RXOK_LP; | |
f078f209 | 892 | |
66860240 VT |
893 | } else { |
894 | if (ah->config.rx_intr_mitigation) | |
895 | imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; | |
896 | else | |
897 | imr_reg |= AR_IMR_RXOK; | |
898 | } | |
f078f209 | 899 | |
66860240 VT |
900 | if (ah->config.tx_intr_mitigation) |
901 | imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; | |
902 | else | |
903 | imr_reg |= AR_IMR_TXOK; | |
f078f209 | 904 | |
d97809db | 905 | if (opmode == NL80211_IFTYPE_AP) |
152d530d | 906 | imr_reg |= AR_IMR_MIB; |
f078f209 | 907 | |
7d0d0df0 S |
908 | ENABLE_REGWRITE_BUFFER(ah); |
909 | ||
152d530d | 910 | REG_WRITE(ah, AR_IMR, imr_reg); |
74bad5cb PR |
911 | ah->imrs2_reg |= AR_IMR_S2_GTT; |
912 | REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); | |
f078f209 | 913 | |
f1dc5600 S |
914 | if (!AR_SREV_9100(ah)) { |
915 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); | |
79d1d2b8 | 916 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); |
f1dc5600 S |
917 | REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); |
918 | } | |
66860240 | 919 | |
7d0d0df0 | 920 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 921 | |
66860240 VT |
922 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
923 | REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); | |
924 | REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); | |
925 | REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); | |
926 | REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); | |
927 | } | |
f078f209 LR |
928 | } |
929 | ||
b6ba41bb FF |
930 | static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) |
931 | { | |
932 | u32 val = ath9k_hw_mac_to_clks(ah, us - 2); | |
933 | val = min(val, (u32) 0xFFFF); | |
934 | REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); | |
935 | } | |
936 | ||
0005baf4 | 937 | static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) |
f078f209 | 938 | { |
0005baf4 FF |
939 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
940 | val = min(val, (u32) 0xFFFF); | |
941 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); | |
f078f209 LR |
942 | } |
943 | ||
0005baf4 | 944 | static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) |
f078f209 | 945 | { |
0005baf4 FF |
946 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
947 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); | |
948 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); | |
949 | } | |
950 | ||
951 | static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) | |
952 | { | |
953 | u32 val = ath9k_hw_mac_to_clks(ah, us); | |
954 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); | |
955 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); | |
f078f209 | 956 | } |
f1dc5600 | 957 | |
cbe61d8a | 958 | static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) |
f078f209 | 959 | { |
f078f209 | 960 | if (tu > 0xFFFF) { |
d2182b69 JP |
961 | ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", |
962 | tu); | |
2660b81a | 963 | ah->globaltxtimeout = (u32) -1; |
f078f209 LR |
964 | return false; |
965 | } else { | |
966 | REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); | |
2660b81a | 967 | ah->globaltxtimeout = tu; |
f078f209 LR |
968 | return true; |
969 | } | |
970 | } | |
971 | ||
0005baf4 | 972 | void ath9k_hw_init_global_settings(struct ath_hw *ah) |
f078f209 | 973 | { |
b6ba41bb FF |
974 | struct ath_common *common = ath9k_hw_common(ah); |
975 | struct ieee80211_conf *conf = &common->hw->conf; | |
976 | const struct ath9k_channel *chan = ah->curchan; | |
adb5066a | 977 | int acktimeout, ctstimeout; |
e239d859 | 978 | int slottime; |
0005baf4 | 979 | int sifstime; |
b6ba41bb FF |
980 | int rx_lat = 0, tx_lat = 0, eifs = 0; |
981 | u32 reg; | |
0005baf4 | 982 | |
d2182b69 | 983 | ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", |
226afe68 | 984 | ah->misc_mode); |
f078f209 | 985 | |
b6ba41bb FF |
986 | if (!chan) |
987 | return; | |
988 | ||
2660b81a | 989 | if (ah->misc_mode != 0) |
ca7a4deb | 990 | REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); |
0005baf4 | 991 | |
81a91d57 RM |
992 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) |
993 | rx_lat = 41; | |
994 | else | |
995 | rx_lat = 37; | |
b6ba41bb FF |
996 | tx_lat = 54; |
997 | ||
998 | if (IS_CHAN_HALF_RATE(chan)) { | |
999 | eifs = 175; | |
1000 | rx_lat *= 2; | |
1001 | tx_lat *= 2; | |
1002 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) | |
1003 | tx_lat += 11; | |
1004 | ||
1005 | slottime = 13; | |
1006 | sifstime = 32; | |
1007 | } else if (IS_CHAN_QUARTER_RATE(chan)) { | |
1008 | eifs = 340; | |
81a91d57 | 1009 | rx_lat = (rx_lat * 4) - 1; |
b6ba41bb FF |
1010 | tx_lat *= 4; |
1011 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) | |
1012 | tx_lat += 22; | |
1013 | ||
1014 | slottime = 21; | |
1015 | sifstime = 64; | |
1016 | } else { | |
a7be039d RM |
1017 | if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { |
1018 | eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO; | |
1019 | reg = AR_USEC_ASYNC_FIFO; | |
1020 | } else { | |
1021 | eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ | |
1022 | common->clockrate; | |
1023 | reg = REG_READ(ah, AR_USEC); | |
1024 | } | |
b6ba41bb FF |
1025 | rx_lat = MS(reg, AR_USEC_RX_LAT); |
1026 | tx_lat = MS(reg, AR_USEC_TX_LAT); | |
1027 | ||
1028 | slottime = ah->slottime; | |
1029 | if (IS_CHAN_5GHZ(chan)) | |
1030 | sifstime = 16; | |
1031 | else | |
1032 | sifstime = 10; | |
1033 | } | |
0005baf4 | 1034 | |
e239d859 | 1035 | /* As defined by IEEE 802.11-2007 17.3.8.6 */ |
b6ba41bb | 1036 | acktimeout = slottime + sifstime + 3 * ah->coverage_class; |
adb5066a | 1037 | ctstimeout = acktimeout; |
42c4568a FF |
1038 | |
1039 | /* | |
1040 | * Workaround for early ACK timeouts, add an offset to match the | |
55a2bb4a | 1041 | * initval's 64us ack timeout value. Use 48us for the CTS timeout. |
42c4568a FF |
1042 | * This was initially only meant to work around an issue with delayed |
1043 | * BA frames in some implementations, but it has been found to fix ACK | |
1044 | * timeout issues in other cases as well. | |
1045 | */ | |
55a2bb4a | 1046 | if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) { |
42c4568a | 1047 | acktimeout += 64 - sifstime - ah->slottime; |
55a2bb4a FF |
1048 | ctstimeout += 48 - sifstime - ah->slottime; |
1049 | } | |
1050 | ||
42c4568a | 1051 | |
b6ba41bb FF |
1052 | ath9k_hw_set_sifs_time(ah, sifstime); |
1053 | ath9k_hw_setslottime(ah, slottime); | |
0005baf4 | 1054 | ath9k_hw_set_ack_timeout(ah, acktimeout); |
adb5066a | 1055 | ath9k_hw_set_cts_timeout(ah, ctstimeout); |
2660b81a S |
1056 | if (ah->globaltxtimeout != (u32) -1) |
1057 | ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); | |
b6ba41bb FF |
1058 | |
1059 | REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); | |
1060 | REG_RMW(ah, AR_USEC, | |
1061 | (common->clockrate - 1) | | |
1062 | SM(rx_lat, AR_USEC_RX_LAT) | | |
1063 | SM(tx_lat, AR_USEC_TX_LAT), | |
1064 | AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC); | |
1065 | ||
f1dc5600 | 1066 | } |
0005baf4 | 1067 | EXPORT_SYMBOL(ath9k_hw_init_global_settings); |
f1dc5600 | 1068 | |
285f2dda | 1069 | void ath9k_hw_deinit(struct ath_hw *ah) |
f1dc5600 | 1070 | { |
211f5859 LR |
1071 | struct ath_common *common = ath9k_hw_common(ah); |
1072 | ||
736b3a27 | 1073 | if (common->state < ATH_HW_INITIALIZED) |
211f5859 LR |
1074 | goto free_hw; |
1075 | ||
9ecdef4b | 1076 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); |
211f5859 LR |
1077 | |
1078 | free_hw: | |
8fe65368 | 1079 | ath9k_hw_rf_free_ext_banks(ah); |
f1dc5600 | 1080 | } |
285f2dda | 1081 | EXPORT_SYMBOL(ath9k_hw_deinit); |
f1dc5600 | 1082 | |
f1dc5600 S |
1083 | /*******/ |
1084 | /* INI */ | |
1085 | /*******/ | |
1086 | ||
8fe65368 | 1087 | u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) |
3a702e49 BC |
1088 | { |
1089 | u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); | |
1090 | ||
1091 | if (IS_CHAN_B(chan)) | |
1092 | ctl |= CTL_11B; | |
1093 | else if (IS_CHAN_G(chan)) | |
1094 | ctl |= CTL_11G; | |
1095 | else | |
1096 | ctl |= CTL_11A; | |
1097 | ||
1098 | return ctl; | |
1099 | } | |
1100 | ||
f1dc5600 S |
1101 | /****************************************/ |
1102 | /* Reset and Channel Switching Routines */ | |
1103 | /****************************************/ | |
f1dc5600 | 1104 | |
cbe61d8a | 1105 | static inline void ath9k_hw_set_dma(struct ath_hw *ah) |
f1dc5600 | 1106 | { |
57b32227 | 1107 | struct ath_common *common = ath9k_hw_common(ah); |
f1dc5600 | 1108 | |
7d0d0df0 S |
1109 | ENABLE_REGWRITE_BUFFER(ah); |
1110 | ||
d7e7d229 LR |
1111 | /* |
1112 | * set AHB_MODE not to do cacheline prefetches | |
1113 | */ | |
ca7a4deb FF |
1114 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
1115 | REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); | |
f1dc5600 | 1116 | |
d7e7d229 LR |
1117 | /* |
1118 | * let mac dma reads be in 128 byte chunks | |
1119 | */ | |
ca7a4deb | 1120 | REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); |
f1dc5600 | 1121 | |
7d0d0df0 | 1122 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1123 | |
d7e7d229 LR |
1124 | /* |
1125 | * Restore TX Trigger Level to its pre-reset value. | |
1126 | * The initial value depends on whether aggregation is enabled, and is | |
1127 | * adjusted whenever underruns are detected. | |
1128 | */ | |
57b32227 FF |
1129 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
1130 | REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); | |
f1dc5600 | 1131 | |
7d0d0df0 | 1132 | ENABLE_REGWRITE_BUFFER(ah); |
f1dc5600 | 1133 | |
d7e7d229 LR |
1134 | /* |
1135 | * let mac dma writes be in 128 byte chunks | |
1136 | */ | |
ca7a4deb | 1137 | REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); |
f1dc5600 | 1138 | |
d7e7d229 LR |
1139 | /* |
1140 | * Setup receive FIFO threshold to hold off TX activities | |
1141 | */ | |
f1dc5600 S |
1142 | REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); |
1143 | ||
57b32227 FF |
1144 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
1145 | REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); | |
1146 | REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); | |
1147 | ||
1148 | ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - | |
1149 | ah->caps.rx_status_len); | |
1150 | } | |
1151 | ||
d7e7d229 LR |
1152 | /* |
1153 | * reduce the number of usable entries in PCU TXBUF to avoid | |
1154 | * wrap around issues. | |
1155 | */ | |
f1dc5600 | 1156 | if (AR_SREV_9285(ah)) { |
d7e7d229 LR |
1157 | /* For AR9285 the number of Fifos are reduced to half. |
1158 | * So set the usable tx buf size also to half to | |
1159 | * avoid data/delimiter underruns | |
1160 | */ | |
f1dc5600 S |
1161 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, |
1162 | AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); | |
d7e7d229 | 1163 | } else if (!AR_SREV_9271(ah)) { |
f1dc5600 S |
1164 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, |
1165 | AR_PCU_TXBUF_CTRL_USABLE_SIZE); | |
1166 | } | |
744d4025 | 1167 | |
7d0d0df0 | 1168 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1169 | |
744d4025 VT |
1170 | if (AR_SREV_9300_20_OR_LATER(ah)) |
1171 | ath9k_hw_reset_txstatus_ring(ah); | |
f1dc5600 S |
1172 | } |
1173 | ||
cbe61d8a | 1174 | static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) |
f1dc5600 | 1175 | { |
ca7a4deb FF |
1176 | u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC; |
1177 | u32 set = AR_STA_ID1_KSRCH_MODE; | |
f1dc5600 | 1178 | |
f1dc5600 | 1179 | switch (opmode) { |
d97809db | 1180 | case NL80211_IFTYPE_ADHOC: |
9cb5412b | 1181 | case NL80211_IFTYPE_MESH_POINT: |
ca7a4deb | 1182 | set |= AR_STA_ID1_ADHOC; |
f1dc5600 | 1183 | REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); |
f078f209 | 1184 | break; |
ca7a4deb FF |
1185 | case NL80211_IFTYPE_AP: |
1186 | set |= AR_STA_ID1_STA_AP; | |
1187 | /* fall through */ | |
d97809db | 1188 | case NL80211_IFTYPE_STATION: |
ca7a4deb | 1189 | REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); |
f078f209 | 1190 | break; |
5f841b41 | 1191 | default: |
ca7a4deb FF |
1192 | if (!ah->is_monitoring) |
1193 | set = 0; | |
5f841b41 | 1194 | break; |
f1dc5600 | 1195 | } |
ca7a4deb | 1196 | REG_RMW(ah, AR_STA_ID1, set, mask); |
f1dc5600 S |
1197 | } |
1198 | ||
8fe65368 LR |
1199 | void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, |
1200 | u32 *coef_mantissa, u32 *coef_exponent) | |
f1dc5600 S |
1201 | { |
1202 | u32 coef_exp, coef_man; | |
1203 | ||
1204 | for (coef_exp = 31; coef_exp > 0; coef_exp--) | |
1205 | if ((coef_scaled >> coef_exp) & 0x1) | |
1206 | break; | |
1207 | ||
1208 | coef_exp = 14 - (coef_exp - COEF_SCALE_S); | |
1209 | ||
1210 | coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); | |
1211 | ||
1212 | *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); | |
1213 | *coef_exponent = coef_exp - 16; | |
1214 | } | |
1215 | ||
cbe61d8a | 1216 | static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) |
f1dc5600 S |
1217 | { |
1218 | u32 rst_flags; | |
1219 | u32 tmpReg; | |
1220 | ||
70768496 | 1221 | if (AR_SREV_9100(ah)) { |
ca7a4deb FF |
1222 | REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, |
1223 | AR_RTC_DERIVED_CLK_PERIOD, 1); | |
70768496 S |
1224 | (void)REG_READ(ah, AR_RTC_DERIVED_CLK); |
1225 | } | |
1226 | ||
7d0d0df0 S |
1227 | ENABLE_REGWRITE_BUFFER(ah); |
1228 | ||
9a658d2b LR |
1229 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
1230 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
1231 | udelay(10); | |
1232 | } | |
1233 | ||
f1dc5600 S |
1234 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
1235 | AR_RTC_FORCE_WAKE_ON_INT); | |
1236 | ||
1237 | if (AR_SREV_9100(ah)) { | |
1238 | rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | | |
1239 | AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; | |
1240 | } else { | |
1241 | tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); | |
1242 | if (tmpReg & | |
1243 | (AR_INTR_SYNC_LOCAL_TIMEOUT | | |
1244 | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { | |
42d5bc3f | 1245 | u32 val; |
f1dc5600 | 1246 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); |
42d5bc3f LR |
1247 | |
1248 | val = AR_RC_HOSTIF; | |
1249 | if (!AR_SREV_9300_20_OR_LATER(ah)) | |
1250 | val |= AR_RC_AHB; | |
1251 | REG_WRITE(ah, AR_RC, val); | |
1252 | ||
1253 | } else if (!AR_SREV_9300_20_OR_LATER(ah)) | |
f1dc5600 | 1254 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
f1dc5600 S |
1255 | |
1256 | rst_flags = AR_RTC_RC_MAC_WARM; | |
1257 | if (type == ATH9K_RESET_COLD) | |
1258 | rst_flags |= AR_RTC_RC_MAC_COLD; | |
1259 | } | |
1260 | ||
7d95847c GJ |
1261 | if (AR_SREV_9330(ah)) { |
1262 | int npend = 0; | |
1263 | int i; | |
1264 | ||
1265 | /* AR9330 WAR: | |
1266 | * call external reset function to reset WMAC if: | |
1267 | * - doing a cold reset | |
1268 | * - we have pending frames in the TX queues | |
1269 | */ | |
1270 | ||
1271 | for (i = 0; i < AR_NUM_QCU; i++) { | |
1272 | npend = ath9k_hw_numtxpending(ah, i); | |
1273 | if (npend) | |
1274 | break; | |
1275 | } | |
1276 | ||
1277 | if (ah->external_reset && | |
1278 | (npend || type == ATH9K_RESET_COLD)) { | |
1279 | int reset_err = 0; | |
1280 | ||
d2182b69 | 1281 | ath_dbg(ath9k_hw_common(ah), RESET, |
7d95847c GJ |
1282 | "reset MAC via external reset\n"); |
1283 | ||
1284 | reset_err = ah->external_reset(); | |
1285 | if (reset_err) { | |
1286 | ath_err(ath9k_hw_common(ah), | |
1287 | "External reset failed, err=%d\n", | |
1288 | reset_err); | |
1289 | return false; | |
1290 | } | |
1291 | ||
1292 | REG_WRITE(ah, AR_RTC_RESET, 1); | |
1293 | } | |
1294 | } | |
1295 | ||
d03a66c1 | 1296 | REG_WRITE(ah, AR_RTC_RC, rst_flags); |
7d0d0df0 S |
1297 | |
1298 | REGWRITE_BUFFER_FLUSH(ah); | |
7d0d0df0 | 1299 | |
f1dc5600 S |
1300 | udelay(50); |
1301 | ||
d03a66c1 | 1302 | REG_WRITE(ah, AR_RTC_RC, 0); |
0caa7b14 | 1303 | if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { |
d2182b69 | 1304 | ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); |
f1dc5600 S |
1305 | return false; |
1306 | } | |
1307 | ||
1308 | if (!AR_SREV_9100(ah)) | |
1309 | REG_WRITE(ah, AR_RC, 0); | |
1310 | ||
f1dc5600 S |
1311 | if (AR_SREV_9100(ah)) |
1312 | udelay(50); | |
1313 | ||
1314 | return true; | |
1315 | } | |
1316 | ||
cbe61d8a | 1317 | static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) |
f1dc5600 | 1318 | { |
7d0d0df0 S |
1319 | ENABLE_REGWRITE_BUFFER(ah); |
1320 | ||
9a658d2b LR |
1321 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
1322 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
1323 | udelay(10); | |
1324 | } | |
1325 | ||
f1dc5600 S |
1326 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
1327 | AR_RTC_FORCE_WAKE_ON_INT); | |
1328 | ||
42d5bc3f | 1329 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
1c29ce67 VT |
1330 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
1331 | ||
d03a66c1 | 1332 | REG_WRITE(ah, AR_RTC_RESET, 0); |
1c29ce67 | 1333 | |
7d0d0df0 | 1334 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1335 | |
84e2169b SB |
1336 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
1337 | udelay(2); | |
1338 | ||
1339 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) | |
1c29ce67 VT |
1340 | REG_WRITE(ah, AR_RC, 0); |
1341 | ||
d03a66c1 | 1342 | REG_WRITE(ah, AR_RTC_RESET, 1); |
f1dc5600 S |
1343 | |
1344 | if (!ath9k_hw_wait(ah, | |
1345 | AR_RTC_STATUS, | |
1346 | AR_RTC_STATUS_M, | |
0caa7b14 S |
1347 | AR_RTC_STATUS_ON, |
1348 | AH_WAIT_TIMEOUT)) { | |
d2182b69 | 1349 | ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); |
f1dc5600 | 1350 | return false; |
f078f209 LR |
1351 | } |
1352 | ||
f1dc5600 S |
1353 | return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); |
1354 | } | |
1355 | ||
cbe61d8a | 1356 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) |
f1dc5600 | 1357 | { |
7a9233ff | 1358 | bool ret = false; |
2577c6e8 | 1359 | |
9a658d2b LR |
1360 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
1361 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
1362 | udelay(10); | |
1363 | } | |
1364 | ||
f1dc5600 S |
1365 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
1366 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); | |
1367 | ||
1368 | switch (type) { | |
1369 | case ATH9K_RESET_POWER_ON: | |
7a9233ff MSS |
1370 | ret = ath9k_hw_set_reset_power_on(ah); |
1371 | break; | |
f1dc5600 S |
1372 | case ATH9K_RESET_WARM: |
1373 | case ATH9K_RESET_COLD: | |
7a9233ff MSS |
1374 | ret = ath9k_hw_set_reset(ah, type); |
1375 | break; | |
f1dc5600 | 1376 | default: |
7a9233ff | 1377 | break; |
f1dc5600 | 1378 | } |
7a9233ff MSS |
1379 | |
1380 | if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) | |
1381 | REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); | |
1382 | ||
1383 | return ret; | |
f078f209 LR |
1384 | } |
1385 | ||
cbe61d8a | 1386 | static bool ath9k_hw_chip_reset(struct ath_hw *ah, |
f1dc5600 | 1387 | struct ath9k_channel *chan) |
f078f209 | 1388 | { |
9c083af8 FF |
1389 | int reset_type = ATH9K_RESET_WARM; |
1390 | ||
1391 | if (AR_SREV_9280(ah)) { | |
1392 | if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) | |
1393 | reset_type = ATH9K_RESET_POWER_ON; | |
1394 | else | |
1395 | reset_type = ATH9K_RESET_COLD; | |
1396 | } | |
1397 | ||
1398 | if (!ath9k_hw_set_reset_reg(ah, reset_type)) | |
f1dc5600 | 1399 | return false; |
f078f209 | 1400 | |
9ecdef4b | 1401 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
f1dc5600 | 1402 | return false; |
f078f209 | 1403 | |
2660b81a | 1404 | ah->chip_fullsleep = false; |
f1dc5600 | 1405 | ath9k_hw_init_pll(ah, chan); |
f1dc5600 | 1406 | ath9k_hw_set_rfmode(ah, chan); |
f078f209 | 1407 | |
f1dc5600 | 1408 | return true; |
f078f209 LR |
1409 | } |
1410 | ||
cbe61d8a | 1411 | static bool ath9k_hw_channel_change(struct ath_hw *ah, |
25c56eec | 1412 | struct ath9k_channel *chan) |
f078f209 | 1413 | { |
c46917bb | 1414 | struct ath_common *common = ath9k_hw_common(ah); |
8fe65368 | 1415 | u32 qnum; |
0a3b7bac | 1416 | int r; |
5f0c04ea RM |
1417 | bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); |
1418 | bool band_switch, mode_diff; | |
1419 | u8 ini_reloaded; | |
1420 | ||
1421 | band_switch = (chan->channelFlags & (CHANNEL_2GHZ | CHANNEL_5GHZ)) != | |
1422 | (ah->curchan->channelFlags & (CHANNEL_2GHZ | | |
1423 | CHANNEL_5GHZ)); | |
1424 | mode_diff = (chan->chanmode != ah->curchan->chanmode); | |
f078f209 LR |
1425 | |
1426 | for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { | |
1427 | if (ath9k_hw_numtxpending(ah, qnum)) { | |
d2182b69 | 1428 | ath_dbg(common, QUEUE, |
226afe68 | 1429 | "Transmit frames pending on queue %d\n", qnum); |
f078f209 LR |
1430 | return false; |
1431 | } | |
1432 | } | |
1433 | ||
8fe65368 | 1434 | if (!ath9k_hw_rfbus_req(ah)) { |
3800276a | 1435 | ath_err(common, "Could not kill baseband RX\n"); |
f078f209 LR |
1436 | return false; |
1437 | } | |
1438 | ||
5f0c04ea RM |
1439 | if (edma && (band_switch || mode_diff)) { |
1440 | ath9k_hw_mark_phy_inactive(ah); | |
1441 | udelay(5); | |
1442 | ||
1443 | ath9k_hw_init_pll(ah, NULL); | |
1444 | ||
1445 | if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { | |
1446 | ath_err(common, "Failed to do fast channel change\n"); | |
1447 | return false; | |
1448 | } | |
1449 | } | |
1450 | ||
8fe65368 | 1451 | ath9k_hw_set_channel_regs(ah, chan); |
f078f209 | 1452 | |
8fe65368 | 1453 | r = ath9k_hw_rf_set_freq(ah, chan); |
0a3b7bac | 1454 | if (r) { |
3800276a | 1455 | ath_err(common, "Failed to set channel\n"); |
0a3b7bac | 1456 | return false; |
f078f209 | 1457 | } |
dfdac8ac | 1458 | ath9k_hw_set_clockrate(ah); |
ca2c68cc | 1459 | ath9k_hw_apply_txpower(ah, chan); |
8fe65368 | 1460 | ath9k_hw_rfbus_done(ah); |
f078f209 | 1461 | |
f1dc5600 S |
1462 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
1463 | ath9k_hw_set_delta_slope(ah, chan); | |
1464 | ||
8fe65368 | 1465 | ath9k_hw_spur_mitigate_freq(ah, chan); |
f1dc5600 | 1466 | |
5f0c04ea | 1467 | if (edma && (band_switch || mode_diff)) { |
a126ff51 | 1468 | ah->ah_flags |= AH_FASTCC; |
5f0c04ea RM |
1469 | if (band_switch || ini_reloaded) |
1470 | ah->eep_ops->set_board_values(ah, chan); | |
1471 | ||
1472 | ath9k_hw_init_bb(ah, chan); | |
1473 | ||
1474 | if (band_switch || ini_reloaded) | |
1475 | ath9k_hw_init_cal(ah, chan); | |
a126ff51 | 1476 | ah->ah_flags &= ~AH_FASTCC; |
5f0c04ea RM |
1477 | } |
1478 | ||
f1dc5600 S |
1479 | return true; |
1480 | } | |
1481 | ||
691680b8 FF |
1482 | static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) |
1483 | { | |
1484 | u32 gpio_mask = ah->gpio_mask; | |
1485 | int i; | |
1486 | ||
1487 | for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { | |
1488 | if (!(gpio_mask & 1)) | |
1489 | continue; | |
1490 | ||
1491 | ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
1492 | ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); | |
1493 | } | |
1494 | } | |
1495 | ||
c9c99e5e | 1496 | bool ath9k_hw_check_alive(struct ath_hw *ah) |
3b319aae | 1497 | { |
c9c99e5e FF |
1498 | int count = 50; |
1499 | u32 reg; | |
1500 | ||
e17f83ea | 1501 | if (AR_SREV_9285_12_OR_LATER(ah)) |
c9c99e5e FF |
1502 | return true; |
1503 | ||
1504 | do { | |
1505 | reg = REG_READ(ah, AR_OBS_BUS_1); | |
3b319aae | 1506 | |
c9c99e5e FF |
1507 | if ((reg & 0x7E7FFFEF) == 0x00702400) |
1508 | continue; | |
1509 | ||
1510 | switch (reg & 0x7E000B00) { | |
1511 | case 0x1E000000: | |
1512 | case 0x52000B00: | |
1513 | case 0x18000B00: | |
1514 | continue; | |
1515 | default: | |
1516 | return true; | |
1517 | } | |
1518 | } while (count-- > 0); | |
3b319aae | 1519 | |
c9c99e5e | 1520 | return false; |
3b319aae | 1521 | } |
c9c99e5e | 1522 | EXPORT_SYMBOL(ath9k_hw_check_alive); |
3b319aae | 1523 | |
caed6579 SM |
1524 | /* |
1525 | * Fast channel change: | |
1526 | * (Change synthesizer based on channel freq without resetting chip) | |
1527 | * | |
1528 | * Don't do FCC when | |
1529 | * - Flag is not set | |
1530 | * - Chip is just coming out of full sleep | |
1531 | * - Channel to be set is same as current channel | |
1532 | * - Channel flags are different, (eg.,moving from 2GHz to 5GHz channel) | |
1533 | */ | |
1534 | static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) | |
1535 | { | |
1536 | struct ath_common *common = ath9k_hw_common(ah); | |
1537 | int ret; | |
1538 | ||
1539 | if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) | |
1540 | goto fail; | |
1541 | ||
1542 | if (ah->chip_fullsleep) | |
1543 | goto fail; | |
1544 | ||
1545 | if (!ah->curchan) | |
1546 | goto fail; | |
1547 | ||
1548 | if (chan->channel == ah->curchan->channel) | |
1549 | goto fail; | |
1550 | ||
1551 | if ((chan->channelFlags & CHANNEL_ALL) != | |
1552 | (ah->curchan->channelFlags & CHANNEL_ALL)) | |
1553 | goto fail; | |
1554 | ||
1555 | if (!ath9k_hw_check_alive(ah)) | |
1556 | goto fail; | |
1557 | ||
1558 | /* | |
1559 | * For AR9462, make sure that calibration data for | |
1560 | * re-using are present. | |
1561 | */ | |
1562 | if (AR_SREV_9462(ah) && (!ah->caldata || | |
1563 | !ah->caldata->done_txiqcal_once || | |
1564 | !ah->caldata->done_txclcal_once || | |
1565 | !ah->caldata->rtt_hist.num_readings)) | |
1566 | goto fail; | |
1567 | ||
1568 | ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n", | |
1569 | ah->curchan->channel, chan->channel); | |
1570 | ||
1571 | ret = ath9k_hw_channel_change(ah, chan); | |
1572 | if (!ret) | |
1573 | goto fail; | |
1574 | ||
1575 | ath9k_hw_loadnf(ah, ah->curchan); | |
1576 | ath9k_hw_start_nfcal(ah, true); | |
1577 | ||
1578 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_MCI) && ar9003_mci_is_ready(ah)) | |
1579 | ar9003_mci_2g5g_switch(ah, true); | |
1580 | ||
1581 | if (AR_SREV_9271(ah)) | |
1582 | ar9002_hw_load_ani_reg(ah, chan); | |
1583 | ||
1584 | return 0; | |
1585 | fail: | |
1586 | return -EINVAL; | |
1587 | } | |
1588 | ||
cbe61d8a | 1589 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
caed6579 | 1590 | struct ath9k_hw_cal_data *caldata, bool fastcc) |
f078f209 | 1591 | { |
1510718d | 1592 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 1593 | u32 saveLedState; |
f078f209 LR |
1594 | u32 saveDefAntenna; |
1595 | u32 macStaId1; | |
46fe782c | 1596 | u64 tsf = 0; |
8fe65368 | 1597 | int i, r; |
caed6579 | 1598 | bool start_mci_reset = false; |
63d32967 MSS |
1599 | bool mci = !!(ah->caps.hw_caps & ATH9K_HW_CAP_MCI); |
1600 | bool save_fullsleep = ah->chip_fullsleep; | |
1601 | ||
1602 | if (mci) { | |
528e5d36 SM |
1603 | start_mci_reset = ar9003_mci_start_reset(ah, chan); |
1604 | if (start_mci_reset) | |
1605 | return 0; | |
63d32967 MSS |
1606 | } |
1607 | ||
9ecdef4b | 1608 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
ae8d2858 | 1609 | return -EIO; |
f078f209 | 1610 | |
caed6579 SM |
1611 | if (ah->curchan && !ah->chip_fullsleep) |
1612 | ath9k_hw_getnf(ah, ah->curchan); | |
f078f209 | 1613 | |
20bd2a09 FF |
1614 | ah->caldata = caldata; |
1615 | if (caldata && | |
1616 | (chan->channel != caldata->channel || | |
1617 | (chan->channelFlags & ~CHANNEL_CW_INT) != | |
1618 | (caldata->channelFlags & ~CHANNEL_CW_INT))) { | |
1619 | /* Operating channel changed, reset channel calibration data */ | |
1620 | memset(caldata, 0, sizeof(*caldata)); | |
1621 | ath9k_init_nfcal_hist_buffer(ah, chan); | |
1622 | } | |
f23fba49 | 1623 | ah->noise = ath9k_hw_getchan_noise(ah, chan); |
20bd2a09 | 1624 | |
caed6579 SM |
1625 | if (fastcc) { |
1626 | r = ath9k_hw_do_fastcc(ah, chan); | |
1627 | if (!r) | |
1628 | return r; | |
f078f209 LR |
1629 | } |
1630 | ||
528e5d36 SM |
1631 | if (mci) |
1632 | ar9003_mci_stop_bt(ah, save_fullsleep); | |
63d32967 | 1633 | |
f078f209 LR |
1634 | saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); |
1635 | if (saveDefAntenna == 0) | |
1636 | saveDefAntenna = 1; | |
1637 | ||
1638 | macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; | |
1639 | ||
46fe782c | 1640 | /* For chips on which RTC reset is done, save TSF before it gets cleared */ |
f860d526 FF |
1641 | if (AR_SREV_9100(ah) || |
1642 | (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))) | |
46fe782c S |
1643 | tsf = ath9k_hw_gettsf64(ah); |
1644 | ||
f078f209 LR |
1645 | saveLedState = REG_READ(ah, AR_CFG_LED) & |
1646 | (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | | |
1647 | AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); | |
1648 | ||
1649 | ath9k_hw_mark_phy_inactive(ah); | |
1650 | ||
45ef6a0b VT |
1651 | ah->paprd_table_write_done = false; |
1652 | ||
05020d23 | 1653 | /* Only required on the first reset */ |
d7e7d229 LR |
1654 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
1655 | REG_WRITE(ah, | |
1656 | AR9271_RESET_POWER_DOWN_CONTROL, | |
1657 | AR9271_RADIO_RF_RST); | |
1658 | udelay(50); | |
1659 | } | |
1660 | ||
f078f209 | 1661 | if (!ath9k_hw_chip_reset(ah, chan)) { |
3800276a | 1662 | ath_err(common, "Chip reset failed\n"); |
ae8d2858 | 1663 | return -EINVAL; |
f078f209 LR |
1664 | } |
1665 | ||
05020d23 | 1666 | /* Only required on the first reset */ |
d7e7d229 LR |
1667 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
1668 | ah->htc_reset_init = false; | |
1669 | REG_WRITE(ah, | |
1670 | AR9271_RESET_POWER_DOWN_CONTROL, | |
1671 | AR9271_GATE_MAC_CTL); | |
1672 | udelay(50); | |
1673 | } | |
1674 | ||
46fe782c | 1675 | /* Restore TSF */ |
f860d526 | 1676 | if (tsf) |
46fe782c S |
1677 | ath9k_hw_settsf64(ah, tsf); |
1678 | ||
7a37081e | 1679 | if (AR_SREV_9280_20_OR_LATER(ah)) |
369391db | 1680 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); |
f078f209 | 1681 | |
e9141f71 S |
1682 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
1683 | ar9002_hw_enable_async_fifo(ah); | |
1684 | ||
25c56eec | 1685 | r = ath9k_hw_process_ini(ah, chan); |
ae8d2858 LR |
1686 | if (r) |
1687 | return r; | |
f078f209 | 1688 | |
63d32967 MSS |
1689 | if (mci) |
1690 | ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); | |
1691 | ||
f860d526 FF |
1692 | /* |
1693 | * Some AR91xx SoC devices frequently fail to accept TSF writes | |
1694 | * right after the chip reset. When that happens, write a new | |
1695 | * value after the initvals have been applied, with an offset | |
1696 | * based on measured time difference | |
1697 | */ | |
1698 | if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { | |
1699 | tsf += 1500; | |
1700 | ath9k_hw_settsf64(ah, tsf); | |
1701 | } | |
1702 | ||
0ced0e17 JM |
1703 | /* Setup MFP options for CCMP */ |
1704 | if (AR_SREV_9280_20_OR_LATER(ah)) { | |
1705 | /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt | |
1706 | * frames when constructing CCMP AAD. */ | |
1707 | REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, | |
1708 | 0xc7ff); | |
1709 | ah->sw_mgmt_crypto = false; | |
1710 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { | |
1711 | /* Disable hardware crypto for management frames */ | |
1712 | REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, | |
1713 | AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); | |
1714 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, | |
1715 | AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); | |
1716 | ah->sw_mgmt_crypto = true; | |
1717 | } else | |
1718 | ah->sw_mgmt_crypto = true; | |
1719 | ||
f078f209 LR |
1720 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
1721 | ath9k_hw_set_delta_slope(ah, chan); | |
1722 | ||
8fe65368 | 1723 | ath9k_hw_spur_mitigate_freq(ah, chan); |
d6509151 | 1724 | ah->eep_ops->set_board_values(ah, chan); |
a7765828 | 1725 | |
7d0d0df0 S |
1726 | ENABLE_REGWRITE_BUFFER(ah); |
1727 | ||
1510718d LR |
1728 | REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); |
1729 | REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) | |
f078f209 LR |
1730 | | macStaId1 |
1731 | | AR_STA_ID1_RTS_USE_DEF | |
2660b81a | 1732 | | (ah->config. |
60b67f51 | 1733 | ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) |
2660b81a | 1734 | | ah->sta_id1_defaults); |
13b81559 | 1735 | ath_hw_setbssidmask(common); |
f078f209 | 1736 | REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); |
3453ad88 | 1737 | ath9k_hw_write_associd(ah); |
f078f209 | 1738 | REG_WRITE(ah, AR_ISR, ~0); |
f078f209 LR |
1739 | REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); |
1740 | ||
7d0d0df0 | 1741 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1742 | |
00e0003e SM |
1743 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
1744 | ||
8fe65368 | 1745 | r = ath9k_hw_rf_set_freq(ah, chan); |
0a3b7bac LR |
1746 | if (r) |
1747 | return r; | |
f078f209 | 1748 | |
dfdac8ac FF |
1749 | ath9k_hw_set_clockrate(ah); |
1750 | ||
7d0d0df0 S |
1751 | ENABLE_REGWRITE_BUFFER(ah); |
1752 | ||
f078f209 LR |
1753 | for (i = 0; i < AR_NUM_DCU; i++) |
1754 | REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); | |
1755 | ||
7d0d0df0 | 1756 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1757 | |
2660b81a | 1758 | ah->intr_txqs = 0; |
f4c607dc | 1759 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) |
f078f209 LR |
1760 | ath9k_hw_resettxqueue(ah, i); |
1761 | ||
2660b81a | 1762 | ath9k_hw_init_interrupt_masks(ah, ah->opmode); |
e36b27af | 1763 | ath9k_hw_ani_cache_ini_regs(ah); |
f078f209 LR |
1764 | ath9k_hw_init_qos(ah); |
1765 | ||
2660b81a | 1766 | if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) |
55821324 | 1767 | ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); |
3b319aae | 1768 | |
0005baf4 | 1769 | ath9k_hw_init_global_settings(ah); |
f078f209 | 1770 | |
fe2b6afb FF |
1771 | if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { |
1772 | REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, | |
1773 | AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768); | |
1774 | REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, | |
1775 | AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL); | |
1776 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, | |
1777 | AR_PCU_MISC_MODE2_ENABLE_AGGWEP); | |
ac88b6ec VN |
1778 | } |
1779 | ||
ca7a4deb | 1780 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); |
f078f209 LR |
1781 | |
1782 | ath9k_hw_set_dma(ah); | |
1783 | ||
1784 | REG_WRITE(ah, AR_OBS, 8); | |
1785 | ||
0ce024cb | 1786 | if (ah->config.rx_intr_mitigation) { |
f078f209 LR |
1787 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); |
1788 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); | |
1789 | } | |
1790 | ||
7f62a136 VT |
1791 | if (ah->config.tx_intr_mitigation) { |
1792 | REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); | |
1793 | REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); | |
1794 | } | |
1795 | ||
f078f209 LR |
1796 | ath9k_hw_init_bb(ah, chan); |
1797 | ||
77a5a664 | 1798 | if (caldata) { |
5f0c04ea | 1799 | caldata->done_txiqcal_once = false; |
77a5a664 | 1800 | caldata->done_txclcal_once = false; |
324c74ad | 1801 | caldata->rtt_hist.num_readings = 0; |
77a5a664 | 1802 | } |
ae8d2858 | 1803 | if (!ath9k_hw_init_cal(ah, chan)) |
6badaaf7 | 1804 | return -EIO; |
f078f209 | 1805 | |
93348928 RM |
1806 | ath9k_hw_loadnf(ah, chan); |
1807 | ath9k_hw_start_nfcal(ah, true); | |
1808 | ||
528e5d36 SM |
1809 | if (mci && ar9003_mci_end_reset(ah, chan, caldata)) |
1810 | return -EIO; | |
63d32967 | 1811 | |
7d0d0df0 | 1812 | ENABLE_REGWRITE_BUFFER(ah); |
f078f209 | 1813 | |
8fe65368 | 1814 | ath9k_hw_restore_chainmask(ah); |
f078f209 LR |
1815 | REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); |
1816 | ||
7d0d0df0 | 1817 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 1818 | |
d7e7d229 LR |
1819 | /* |
1820 | * For big endian systems turn on swapping for descriptors | |
1821 | */ | |
f078f209 LR |
1822 | if (AR_SREV_9100(ah)) { |
1823 | u32 mask; | |
1824 | mask = REG_READ(ah, AR_CFG); | |
1825 | if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { | |
d2182b69 JP |
1826 | ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", |
1827 | mask); | |
f078f209 LR |
1828 | } else { |
1829 | mask = | |
1830 | INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; | |
1831 | REG_WRITE(ah, AR_CFG, mask); | |
d2182b69 JP |
1832 | ath_dbg(common, RESET, "Setting CFG 0x%x\n", |
1833 | REG_READ(ah, AR_CFG)); | |
f078f209 LR |
1834 | } |
1835 | } else { | |
cbba8cd1 S |
1836 | if (common->bus_ops->ath_bus_type == ATH_USB) { |
1837 | /* Configure AR9271 target WLAN */ | |
1838 | if (AR_SREV_9271(ah)) | |
1839 | REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); | |
1840 | else | |
1841 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); | |
1842 | } | |
f078f209 | 1843 | #ifdef __BIG_ENDIAN |
4033bdad | 1844 | else if (AR_SREV_9330(ah) || AR_SREV_9340(ah)) |
2be7bfe0 VT |
1845 | REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); |
1846 | else | |
d7e7d229 | 1847 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); |
f078f209 LR |
1848 | #endif |
1849 | } | |
1850 | ||
dbccdd1d | 1851 | if (ath9k_hw_btcoex_is_enabled(ah)) |
42cc41ed VT |
1852 | ath9k_hw_btcoex_enable(ah); |
1853 | ||
528e5d36 SM |
1854 | if (mci) |
1855 | ar9003_mci_check_bt(ah); | |
63d32967 | 1856 | |
51ac8cbb | 1857 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
aea702b7 | 1858 | ar9003_hw_bb_watchdog_config(ah); |
d8903a53 | 1859 | |
51ac8cbb RM |
1860 | ar9003_hw_disable_phy_restart(ah); |
1861 | } | |
1862 | ||
691680b8 FF |
1863 | ath9k_hw_apply_gpio_override(ah); |
1864 | ||
ae8d2858 | 1865 | return 0; |
f078f209 | 1866 | } |
7322fd19 | 1867 | EXPORT_SYMBOL(ath9k_hw_reset); |
f078f209 | 1868 | |
f1dc5600 S |
1869 | /******************************/ |
1870 | /* Power Management (Chipset) */ | |
1871 | /******************************/ | |
1872 | ||
42d5bc3f LR |
1873 | /* |
1874 | * Notify Power Mgt is disabled in self-generated frames. | |
1875 | * If requested, force chip to sleep. | |
1876 | */ | |
cbe61d8a | 1877 | static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) |
f078f209 | 1878 | { |
f1dc5600 S |
1879 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
1880 | if (setChip) { | |
423e38e8 | 1881 | if (AR_SREV_9462(ah)) { |
2577c6e8 SB |
1882 | REG_WRITE(ah, AR_TIMER_MODE, |
1883 | REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00); | |
1884 | REG_WRITE(ah, AR_NDP2_TIMER_MODE, REG_READ(ah, | |
1885 | AR_NDP2_TIMER_MODE) & 0xFFFFFF00); | |
1886 | REG_WRITE(ah, AR_SLP32_INC, | |
1887 | REG_READ(ah, AR_SLP32_INC) & 0xFFF00000); | |
1888 | /* xxx Required for WLAN only case ? */ | |
1889 | REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); | |
1890 | udelay(100); | |
1891 | } | |
1892 | ||
42d5bc3f LR |
1893 | /* |
1894 | * Clear the RTC force wake bit to allow the | |
1895 | * mac to go to sleep. | |
1896 | */ | |
2577c6e8 SB |
1897 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); |
1898 | ||
423e38e8 | 1899 | if (AR_SREV_9462(ah)) |
2577c6e8 SB |
1900 | udelay(100); |
1901 | ||
42d5bc3f | 1902 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
f1dc5600 | 1903 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); |
f078f209 | 1904 | |
42d5bc3f | 1905 | /* Shutdown chip. Active low */ |
c91ec465 | 1906 | if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { |
2577c6e8 SB |
1907 | REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); |
1908 | udelay(2); | |
1909 | } | |
f1dc5600 | 1910 | } |
9a658d2b LR |
1911 | |
1912 | /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */ | |
a7322812 RW |
1913 | if (AR_SREV_9300_20_OR_LATER(ah)) |
1914 | REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); | |
f078f209 LR |
1915 | } |
1916 | ||
bbd79af5 LR |
1917 | /* |
1918 | * Notify Power Management is enabled in self-generating | |
1919 | * frames. If request, set power mode of chip to | |
1920 | * auto/normal. Duration in units of 128us (1/8 TU). | |
1921 | */ | |
cbe61d8a | 1922 | static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) |
f078f209 | 1923 | { |
2577c6e8 SB |
1924 | u32 val; |
1925 | ||
f1dc5600 S |
1926 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
1927 | if (setChip) { | |
2660b81a | 1928 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
f078f209 | 1929 | |
f1dc5600 | 1930 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
bbd79af5 | 1931 | /* Set WakeOnInterrupt bit; clear ForceWake bit */ |
f1dc5600 S |
1932 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
1933 | AR_RTC_FORCE_WAKE_ON_INT); | |
1934 | } else { | |
2577c6e8 SB |
1935 | |
1936 | /* When chip goes into network sleep, it could be waken | |
1937 | * up by MCI_INT interrupt caused by BT's HW messages | |
1938 | * (LNA_xxx, CONT_xxx) which chould be in a very fast | |
1939 | * rate (~100us). This will cause chip to leave and | |
1940 | * re-enter network sleep mode frequently, which in | |
1941 | * consequence will have WLAN MCI HW to generate lots of | |
1942 | * SYS_WAKING and SYS_SLEEPING messages which will make | |
1943 | * BT CPU to busy to process. | |
1944 | */ | |
423e38e8 | 1945 | if (AR_SREV_9462(ah)) { |
2577c6e8 SB |
1946 | val = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) & |
1947 | ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK; | |
1948 | REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, val); | |
1949 | } | |
bbd79af5 LR |
1950 | /* |
1951 | * Clear the RTC force wake bit to allow the | |
1952 | * mac to go to sleep. | |
1953 | */ | |
f1dc5600 S |
1954 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, |
1955 | AR_RTC_FORCE_WAKE_EN); | |
2577c6e8 | 1956 | |
423e38e8 | 1957 | if (AR_SREV_9462(ah)) |
2577c6e8 | 1958 | udelay(30); |
f078f209 | 1959 | } |
f078f209 | 1960 | } |
9a658d2b LR |
1961 | |
1962 | /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */ | |
1963 | if (AR_SREV_9300_20_OR_LATER(ah)) | |
1964 | REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); | |
f078f209 LR |
1965 | } |
1966 | ||
cbe61d8a | 1967 | static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) |
f078f209 | 1968 | { |
f1dc5600 S |
1969 | u32 val; |
1970 | int i; | |
f078f209 | 1971 | |
9a658d2b LR |
1972 | /* Set Bits 14 and 17 of AR_WA before powering on the chip. */ |
1973 | if (AR_SREV_9300_20_OR_LATER(ah)) { | |
1974 | REG_WRITE(ah, AR_WA, ah->WARegVal); | |
1975 | udelay(10); | |
1976 | } | |
1977 | ||
f1dc5600 S |
1978 | if (setChip) { |
1979 | if ((REG_READ(ah, AR_RTC_STATUS) & | |
1980 | AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { | |
1981 | if (ath9k_hw_set_reset_reg(ah, | |
1982 | ATH9K_RESET_POWER_ON) != true) { | |
1983 | return false; | |
1984 | } | |
e041228f LR |
1985 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
1986 | ath9k_hw_init_pll(ah, NULL); | |
f1dc5600 S |
1987 | } |
1988 | if (AR_SREV_9100(ah)) | |
1989 | REG_SET_BIT(ah, AR_RTC_RESET, | |
1990 | AR_RTC_RESET_EN); | |
f078f209 | 1991 | |
f1dc5600 S |
1992 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, |
1993 | AR_RTC_FORCE_WAKE_EN); | |
1994 | udelay(50); | |
f078f209 | 1995 | |
f1dc5600 S |
1996 | for (i = POWER_UP_TIME / 50; i > 0; i--) { |
1997 | val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; | |
1998 | if (val == AR_RTC_STATUS_ON) | |
1999 | break; | |
2000 | udelay(50); | |
2001 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, | |
2002 | AR_RTC_FORCE_WAKE_EN); | |
f078f209 | 2003 | } |
f1dc5600 | 2004 | if (i == 0) { |
3800276a JP |
2005 | ath_err(ath9k_hw_common(ah), |
2006 | "Failed to wakeup in %uus\n", | |
2007 | POWER_UP_TIME / 20); | |
f1dc5600 | 2008 | return false; |
f078f209 | 2009 | } |
f078f209 LR |
2010 | } |
2011 | ||
f1dc5600 | 2012 | REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
f078f209 | 2013 | |
f1dc5600 | 2014 | return true; |
f078f209 LR |
2015 | } |
2016 | ||
9ecdef4b | 2017 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) |
f078f209 | 2018 | { |
c46917bb | 2019 | struct ath_common *common = ath9k_hw_common(ah); |
cbe61d8a | 2020 | int status = true, setChip = true; |
f1dc5600 S |
2021 | static const char *modes[] = { |
2022 | "AWAKE", | |
2023 | "FULL-SLEEP", | |
2024 | "NETWORK SLEEP", | |
2025 | "UNDEFINED" | |
2026 | }; | |
f1dc5600 | 2027 | |
cbdec975 GJ |
2028 | if (ah->power_mode == mode) |
2029 | return status; | |
2030 | ||
d2182b69 | 2031 | ath_dbg(common, RESET, "%s -> %s\n", |
226afe68 | 2032 | modes[ah->power_mode], modes[mode]); |
f1dc5600 S |
2033 | |
2034 | switch (mode) { | |
2035 | case ATH9K_PM_AWAKE: | |
2036 | status = ath9k_hw_set_power_awake(ah, setChip); | |
1010911e MSS |
2037 | |
2038 | if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) | |
2039 | REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); | |
2040 | ||
f1dc5600 S |
2041 | break; |
2042 | case ATH9K_PM_FULL_SLEEP: | |
d1ca8b8e SM |
2043 | if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) |
2044 | ar9003_mci_set_full_sleep(ah); | |
1010911e | 2045 | |
f1dc5600 | 2046 | ath9k_set_power_sleep(ah, setChip); |
2660b81a | 2047 | ah->chip_fullsleep = true; |
f1dc5600 S |
2048 | break; |
2049 | case ATH9K_PM_NETWORK_SLEEP: | |
1010911e MSS |
2050 | |
2051 | if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) | |
2052 | REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2); | |
2053 | ||
f1dc5600 S |
2054 | ath9k_set_power_network_sleep(ah, setChip); |
2055 | break; | |
f078f209 | 2056 | default: |
3800276a | 2057 | ath_err(common, "Unknown power mode %u\n", mode); |
f078f209 LR |
2058 | return false; |
2059 | } | |
2660b81a | 2060 | ah->power_mode = mode; |
f1dc5600 | 2061 | |
69f4aab1 LR |
2062 | /* |
2063 | * XXX: If this warning never comes up after a while then | |
2064 | * simply keep the ATH_DBG_WARN_ON_ONCE() but make | |
2065 | * ath9k_hw_setpower() return type void. | |
2066 | */ | |
97dcec57 SM |
2067 | |
2068 | if (!(ah->ah_flags & AH_UNPLUGGED)) | |
2069 | ATH_DBG_WARN_ON_ONCE(!status); | |
69f4aab1 | 2070 | |
f1dc5600 | 2071 | return status; |
f078f209 | 2072 | } |
7322fd19 | 2073 | EXPORT_SYMBOL(ath9k_hw_setpower); |
f078f209 | 2074 | |
f1dc5600 S |
2075 | /*******************/ |
2076 | /* Beacon Handling */ | |
2077 | /*******************/ | |
2078 | ||
cbe61d8a | 2079 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) |
f078f209 | 2080 | { |
f078f209 LR |
2081 | int flags = 0; |
2082 | ||
7d0d0df0 S |
2083 | ENABLE_REGWRITE_BUFFER(ah); |
2084 | ||
2660b81a | 2085 | switch (ah->opmode) { |
d97809db | 2086 | case NL80211_IFTYPE_ADHOC: |
9cb5412b | 2087 | case NL80211_IFTYPE_MESH_POINT: |
f078f209 LR |
2088 | REG_SET_BIT(ah, AR_TXCFG, |
2089 | AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); | |
dd347f2f FF |
2090 | REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon + |
2091 | TU_TO_USEC(ah->atim_window ? ah->atim_window : 1)); | |
f078f209 | 2092 | flags |= AR_NDP_TIMER_EN; |
d97809db | 2093 | case NL80211_IFTYPE_AP: |
dd347f2f FF |
2094 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); |
2095 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - | |
2096 | TU_TO_USEC(ah->config.dma_beacon_response_time)); | |
2097 | REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - | |
2098 | TU_TO_USEC(ah->config.sw_beacon_response_time)); | |
f078f209 LR |
2099 | flags |= |
2100 | AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; | |
2101 | break; | |
d97809db | 2102 | default: |
d2182b69 JP |
2103 | ath_dbg(ath9k_hw_common(ah), BEACON, |
2104 | "%s: unsupported opmode: %d\n", __func__, ah->opmode); | |
d97809db CM |
2105 | return; |
2106 | break; | |
f078f209 LR |
2107 | } |
2108 | ||
dd347f2f FF |
2109 | REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); |
2110 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); | |
2111 | REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); | |
2112 | REG_WRITE(ah, AR_NDP_PERIOD, beacon_period); | |
f078f209 | 2113 | |
7d0d0df0 | 2114 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 2115 | |
f078f209 LR |
2116 | REG_SET_BIT(ah, AR_TIMER_MODE, flags); |
2117 | } | |
7322fd19 | 2118 | EXPORT_SYMBOL(ath9k_hw_beaconinit); |
f078f209 | 2119 | |
cbe61d8a | 2120 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, |
f1dc5600 | 2121 | const struct ath9k_beacon_state *bs) |
f078f209 LR |
2122 | { |
2123 | u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; | |
2660b81a | 2124 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
c46917bb | 2125 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 2126 | |
7d0d0df0 S |
2127 | ENABLE_REGWRITE_BUFFER(ah); |
2128 | ||
f078f209 LR |
2129 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); |
2130 | ||
2131 | REG_WRITE(ah, AR_BEACON_PERIOD, | |
f29f5c08 | 2132 | TU_TO_USEC(bs->bs_intval)); |
f078f209 | 2133 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, |
f29f5c08 | 2134 | TU_TO_USEC(bs->bs_intval)); |
f078f209 | 2135 | |
7d0d0df0 | 2136 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 2137 | |
f078f209 LR |
2138 | REG_RMW_FIELD(ah, AR_RSSI_THR, |
2139 | AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); | |
2140 | ||
f29f5c08 | 2141 | beaconintval = bs->bs_intval; |
f078f209 LR |
2142 | |
2143 | if (bs->bs_sleepduration > beaconintval) | |
2144 | beaconintval = bs->bs_sleepduration; | |
2145 | ||
2146 | dtimperiod = bs->bs_dtimperiod; | |
2147 | if (bs->bs_sleepduration > dtimperiod) | |
2148 | dtimperiod = bs->bs_sleepduration; | |
2149 | ||
2150 | if (beaconintval == dtimperiod) | |
2151 | nextTbtt = bs->bs_nextdtim; | |
2152 | else | |
2153 | nextTbtt = bs->bs_nexttbtt; | |
2154 | ||
d2182b69 JP |
2155 | ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim); |
2156 | ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt); | |
2157 | ath_dbg(common, BEACON, "beacon period %d\n", beaconintval); | |
2158 | ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod); | |
f078f209 | 2159 | |
7d0d0df0 S |
2160 | ENABLE_REGWRITE_BUFFER(ah); |
2161 | ||
f1dc5600 S |
2162 | REG_WRITE(ah, AR_NEXT_DTIM, |
2163 | TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); | |
2164 | REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); | |
f078f209 | 2165 | |
f1dc5600 S |
2166 | REG_WRITE(ah, AR_SLEEP1, |
2167 | SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) | |
2168 | | AR_SLEEP1_ASSUME_DTIM); | |
f078f209 | 2169 | |
f1dc5600 S |
2170 | if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) |
2171 | beacontimeout = (BEACON_TIMEOUT_VAL << 3); | |
2172 | else | |
2173 | beacontimeout = MIN_BEACON_TIMEOUT_VAL; | |
f078f209 | 2174 | |
f1dc5600 S |
2175 | REG_WRITE(ah, AR_SLEEP2, |
2176 | SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); | |
f078f209 | 2177 | |
f1dc5600 S |
2178 | REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); |
2179 | REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); | |
f078f209 | 2180 | |
7d0d0df0 | 2181 | REGWRITE_BUFFER_FLUSH(ah); |
7d0d0df0 | 2182 | |
f1dc5600 S |
2183 | REG_SET_BIT(ah, AR_TIMER_MODE, |
2184 | AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | | |
2185 | AR_DTIM_TIMER_EN); | |
f078f209 | 2186 | |
4af9cf4f S |
2187 | /* TSF Out of Range Threshold */ |
2188 | REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); | |
f078f209 | 2189 | } |
7322fd19 | 2190 | EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); |
f078f209 | 2191 | |
f1dc5600 S |
2192 | /*******************/ |
2193 | /* HW Capabilities */ | |
2194 | /*******************/ | |
2195 | ||
6054069a FF |
2196 | static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask) |
2197 | { | |
2198 | eeprom_chainmask &= chip_chainmask; | |
2199 | if (eeprom_chainmask) | |
2200 | return eeprom_chainmask; | |
2201 | else | |
2202 | return chip_chainmask; | |
2203 | } | |
2204 | ||
9a66af33 ZK |
2205 | /** |
2206 | * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset | |
2207 | * @ah: the atheros hardware data structure | |
2208 | * | |
2209 | * We enable DFS support upstream on chipsets which have passed a series | |
2210 | * of tests. The testing requirements are going to be documented. Desired | |
2211 | * test requirements are documented at: | |
2212 | * | |
2213 | * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs | |
2214 | * | |
2215 | * Once a new chipset gets properly tested an individual commit can be used | |
2216 | * to document the testing for DFS for that chipset. | |
2217 | */ | |
2218 | static bool ath9k_hw_dfs_tested(struct ath_hw *ah) | |
2219 | { | |
2220 | ||
2221 | switch (ah->hw_version.macVersion) { | |
2222 | /* AR9580 will likely be our first target to get testing on */ | |
2223 | case AR_SREV_VERSION_9580: | |
2224 | default: | |
2225 | return false; | |
2226 | } | |
2227 | } | |
2228 | ||
a9a29ce6 | 2229 | int ath9k_hw_fill_cap_info(struct ath_hw *ah) |
f078f209 | 2230 | { |
2660b81a | 2231 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
608b88cb | 2232 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
c46917bb | 2233 | struct ath_common *common = ath9k_hw_common(ah); |
6054069a | 2234 | unsigned int chip_chainmask; |
608b88cb | 2235 | |
0ff2b5c0 | 2236 | u16 eeval; |
47c80de6 | 2237 | u8 ant_div_ctl1, tx_chainmask, rx_chainmask; |
f078f209 | 2238 | |
f74df6fb | 2239 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); |
608b88cb | 2240 | regulatory->current_rd = eeval; |
f078f209 | 2241 | |
2660b81a | 2242 | if (ah->opmode != NL80211_IFTYPE_AP && |
d535a42a | 2243 | ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { |
608b88cb LR |
2244 | if (regulatory->current_rd == 0x64 || |
2245 | regulatory->current_rd == 0x65) | |
2246 | regulatory->current_rd += 5; | |
2247 | else if (regulatory->current_rd == 0x41) | |
2248 | regulatory->current_rd = 0x43; | |
d2182b69 JP |
2249 | ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", |
2250 | regulatory->current_rd); | |
f1dc5600 | 2251 | } |
f078f209 | 2252 | |
f74df6fb | 2253 | eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); |
a9a29ce6 | 2254 | if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { |
3800276a JP |
2255 | ath_err(common, |
2256 | "no band has been marked as supported in EEPROM\n"); | |
a9a29ce6 GJ |
2257 | return -EINVAL; |
2258 | } | |
2259 | ||
d4659912 FF |
2260 | if (eeval & AR5416_OPFLAGS_11A) |
2261 | pCap->hw_caps |= ATH9K_HW_CAP_5GHZ; | |
f078f209 | 2262 | |
d4659912 FF |
2263 | if (eeval & AR5416_OPFLAGS_11G) |
2264 | pCap->hw_caps |= ATH9K_HW_CAP_2GHZ; | |
f1dc5600 | 2265 | |
6054069a FF |
2266 | if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah)) |
2267 | chip_chainmask = 1; | |
ba5736a5 MSS |
2268 | else if (AR_SREV_9462(ah)) |
2269 | chip_chainmask = 3; | |
6054069a FF |
2270 | else if (!AR_SREV_9280_20_OR_LATER(ah)) |
2271 | chip_chainmask = 7; | |
2272 | else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah)) | |
2273 | chip_chainmask = 3; | |
2274 | else | |
2275 | chip_chainmask = 7; | |
2276 | ||
f74df6fb | 2277 | pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); |
d7e7d229 LR |
2278 | /* |
2279 | * For AR9271 we will temporarilly uses the rx chainmax as read from | |
2280 | * the EEPROM. | |
2281 | */ | |
8147f5de | 2282 | if ((ah->hw_version.devid == AR5416_DEVID_PCI) && |
d7e7d229 LR |
2283 | !(eeval & AR5416_OPFLAGS_11A) && |
2284 | !(AR_SREV_9271(ah))) | |
2285 | /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ | |
8147f5de | 2286 | pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; |
598cdd52 FF |
2287 | else if (AR_SREV_9100(ah)) |
2288 | pCap->rx_chainmask = 0x7; | |
8147f5de | 2289 | else |
d7e7d229 | 2290 | /* Use rx_chainmask from EEPROM. */ |
8147f5de | 2291 | pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); |
f078f209 | 2292 | |
6054069a FF |
2293 | pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask); |
2294 | pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask); | |
82b2d334 FF |
2295 | ah->txchainmask = pCap->tx_chainmask; |
2296 | ah->rxchainmask = pCap->rx_chainmask; | |
6054069a | 2297 | |
7a37081e | 2298 | ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; |
f078f209 | 2299 | |
02d2ebb2 FF |
2300 | /* enable key search for every frame in an aggregate */ |
2301 | if (AR_SREV_9300_20_OR_LATER(ah)) | |
2302 | ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; | |
2303 | ||
ce2220d1 BR |
2304 | common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM; |
2305 | ||
0db156e9 | 2306 | if (ah->hw_version.devid != AR2427_DEVID_PCIE) |
f1dc5600 S |
2307 | pCap->hw_caps |= ATH9K_HW_CAP_HT; |
2308 | else | |
2309 | pCap->hw_caps &= ~ATH9K_HW_CAP_HT; | |
f078f209 | 2310 | |
5b5fa355 S |
2311 | if (AR_SREV_9271(ah)) |
2312 | pCap->num_gpio_pins = AR9271_NUM_GPIO; | |
88c1f4f6 S |
2313 | else if (AR_DEVID_7010(ah)) |
2314 | pCap->num_gpio_pins = AR7010_NUM_GPIO; | |
6321eb09 MSS |
2315 | else if (AR_SREV_9300_20_OR_LATER(ah)) |
2316 | pCap->num_gpio_pins = AR9300_NUM_GPIO; | |
2317 | else if (AR_SREV_9287_11_OR_LATER(ah)) | |
2318 | pCap->num_gpio_pins = AR9287_NUM_GPIO; | |
e17f83ea | 2319 | else if (AR_SREV_9285_12_OR_LATER(ah)) |
cb33c412 | 2320 | pCap->num_gpio_pins = AR9285_NUM_GPIO; |
7a37081e | 2321 | else if (AR_SREV_9280_20_OR_LATER(ah)) |
f1dc5600 S |
2322 | pCap->num_gpio_pins = AR928X_NUM_GPIO; |
2323 | else | |
2324 | pCap->num_gpio_pins = AR_NUM_GPIO; | |
f078f209 | 2325 | |
1b2538b2 | 2326 | if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) |
f1dc5600 | 2327 | pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; |
1b2538b2 | 2328 | else |
f1dc5600 | 2329 | pCap->rts_aggr_limit = (8 * 1024); |
f078f209 | 2330 | |
e97275cb | 2331 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
2660b81a S |
2332 | ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); |
2333 | if (ah->rfsilent & EEP_RFSILENT_ENABLED) { | |
2334 | ah->rfkill_gpio = | |
2335 | MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); | |
2336 | ah->rfkill_polarity = | |
2337 | MS(ah->rfsilent, EEP_RFSILENT_POLARITY); | |
f1dc5600 S |
2338 | |
2339 | pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; | |
f078f209 | 2340 | } |
f1dc5600 | 2341 | #endif |
d5d1154f | 2342 | if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) |
bde748a4 VN |
2343 | pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; |
2344 | else | |
2345 | pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; | |
f078f209 | 2346 | |
e7594072 | 2347 | if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) |
f1dc5600 S |
2348 | pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; |
2349 | else | |
2350 | pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; | |
f078f209 | 2351 | |
ceb26445 | 2352 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
784ad503 | 2353 | pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; |
0e707a94 | 2354 | if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah)) |
784ad503 VT |
2355 | pCap->hw_caps |= ATH9K_HW_CAP_LDPC; |
2356 | ||
ceb26445 VT |
2357 | pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; |
2358 | pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; | |
2359 | pCap->rx_status_len = sizeof(struct ar9003_rxs); | |
162c3be3 | 2360 | pCap->tx_desc_len = sizeof(struct ar9003_txc); |
5088c2f1 | 2361 | pCap->txs_len = sizeof(struct ar9003_txs); |
6f481010 LR |
2362 | if (!ah->config.paprd_disable && |
2363 | ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) | |
4935250a | 2364 | pCap->hw_caps |= ATH9K_HW_CAP_PAPRD; |
162c3be3 VT |
2365 | } else { |
2366 | pCap->tx_desc_len = sizeof(struct ath_desc); | |
a949b172 | 2367 | if (AR_SREV_9280_20(ah)) |
6b42e8d0 | 2368 | pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK; |
ceb26445 | 2369 | } |
1adf02ff | 2370 | |
6c84ce08 VT |
2371 | if (AR_SREV_9300_20_OR_LATER(ah)) |
2372 | pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; | |
2373 | ||
6ee63f55 SB |
2374 | if (AR_SREV_9300_20_OR_LATER(ah)) |
2375 | ah->ent_mode = REG_READ(ah, AR_ENT_OTP); | |
2376 | ||
a42acef0 | 2377 | if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) |
6473d24d VT |
2378 | pCap->hw_caps |= ATH9K_HW_CAP_SGI_20; |
2379 | ||
754dc536 VT |
2380 | if (AR_SREV_9285(ah)) |
2381 | if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { | |
2382 | ant_div_ctl1 = | |
2383 | ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); | |
2384 | if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) | |
2385 | pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; | |
2386 | } | |
ea066d5a MSS |
2387 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
2388 | if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) | |
2389 | pCap->hw_caps |= ATH9K_HW_CAP_APM; | |
2390 | } | |
2391 | ||
2392 | ||
431da56a | 2393 | if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { |
21d2c63a MSS |
2394 | ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); |
2395 | /* | |
2396 | * enable the diversity-combining algorithm only when | |
2397 | * both enable_lna_div and enable_fast_div are set | |
2398 | * Table for Diversity | |
2399 | * ant_div_alt_lnaconf bit 0-1 | |
2400 | * ant_div_main_lnaconf bit 2-3 | |
2401 | * ant_div_alt_gaintb bit 4 | |
2402 | * ant_div_main_gaintb bit 5 | |
2403 | * enable_ant_div_lnadiv bit 6 | |
2404 | * enable_ant_fast_div bit 7 | |
2405 | */ | |
2406 | if ((ant_div_ctl1 >> 0x6) == 0x3) | |
2407 | pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB; | |
2408 | } | |
754dc536 | 2409 | |
8060e169 VT |
2410 | if (AR_SREV_9485_10(ah)) { |
2411 | pCap->pcie_lcr_extsync_en = true; | |
2412 | pCap->pcie_lcr_offset = 0x80; | |
2413 | } | |
2414 | ||
9a66af33 ZK |
2415 | if (ath9k_hw_dfs_tested(ah)) |
2416 | pCap->hw_caps |= ATH9K_HW_CAP_DFS; | |
2417 | ||
47c80de6 VT |
2418 | tx_chainmask = pCap->tx_chainmask; |
2419 | rx_chainmask = pCap->rx_chainmask; | |
2420 | while (tx_chainmask || rx_chainmask) { | |
2421 | if (tx_chainmask & BIT(0)) | |
2422 | pCap->max_txchains++; | |
2423 | if (rx_chainmask & BIT(0)) | |
2424 | pCap->max_rxchains++; | |
2425 | ||
2426 | tx_chainmask >>= 1; | |
2427 | rx_chainmask >>= 1; | |
2428 | } | |
2429 | ||
8ad74c4d RM |
2430 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
2431 | ah->enabled_cals |= TX_IQ_CAL; | |
6fea593d | 2432 | if (AR_SREV_9485_OR_LATER(ah)) |
8ad74c4d RM |
2433 | ah->enabled_cals |= TX_IQ_ON_AGC_CAL; |
2434 | } | |
3789d59c MSS |
2435 | |
2436 | if (AR_SREV_9462(ah)) { | |
2437 | ||
2438 | if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) | |
2439 | pCap->hw_caps |= ATH9K_HW_CAP_MCI; | |
2440 | ||
2441 | if (AR_SREV_9462_20(ah)) | |
2442 | pCap->hw_caps |= ATH9K_HW_CAP_RTT; | |
2443 | ||
2444 | } | |
2445 | ||
324c74ad | 2446 | |
a9a29ce6 | 2447 | return 0; |
f078f209 LR |
2448 | } |
2449 | ||
f1dc5600 S |
2450 | /****************************/ |
2451 | /* GPIO / RFKILL / Antennae */ | |
2452 | /****************************/ | |
f078f209 | 2453 | |
cbe61d8a | 2454 | static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, |
f1dc5600 S |
2455 | u32 gpio, u32 type) |
2456 | { | |
2457 | int addr; | |
2458 | u32 gpio_shift, tmp; | |
f078f209 | 2459 | |
f1dc5600 S |
2460 | if (gpio > 11) |
2461 | addr = AR_GPIO_OUTPUT_MUX3; | |
2462 | else if (gpio > 5) | |
2463 | addr = AR_GPIO_OUTPUT_MUX2; | |
2464 | else | |
2465 | addr = AR_GPIO_OUTPUT_MUX1; | |
f078f209 | 2466 | |
f1dc5600 | 2467 | gpio_shift = (gpio % 6) * 5; |
f078f209 | 2468 | |
f1dc5600 S |
2469 | if (AR_SREV_9280_20_OR_LATER(ah) |
2470 | || (addr != AR_GPIO_OUTPUT_MUX1)) { | |
2471 | REG_RMW(ah, addr, (type << gpio_shift), | |
2472 | (0x1f << gpio_shift)); | |
f078f209 | 2473 | } else { |
f1dc5600 S |
2474 | tmp = REG_READ(ah, addr); |
2475 | tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); | |
2476 | tmp &= ~(0x1f << gpio_shift); | |
2477 | tmp |= (type << gpio_shift); | |
2478 | REG_WRITE(ah, addr, tmp); | |
f078f209 | 2479 | } |
f078f209 LR |
2480 | } |
2481 | ||
cbe61d8a | 2482 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) |
f078f209 | 2483 | { |
f1dc5600 | 2484 | u32 gpio_shift; |
f078f209 | 2485 | |
9680e8a3 | 2486 | BUG_ON(gpio >= ah->caps.num_gpio_pins); |
f078f209 | 2487 | |
88c1f4f6 S |
2488 | if (AR_DEVID_7010(ah)) { |
2489 | gpio_shift = gpio; | |
2490 | REG_RMW(ah, AR7010_GPIO_OE, | |
2491 | (AR7010_GPIO_OE_AS_INPUT << gpio_shift), | |
2492 | (AR7010_GPIO_OE_MASK << gpio_shift)); | |
2493 | return; | |
2494 | } | |
f078f209 | 2495 | |
88c1f4f6 | 2496 | gpio_shift = gpio << 1; |
f1dc5600 S |
2497 | REG_RMW(ah, |
2498 | AR_GPIO_OE_OUT, | |
2499 | (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), | |
2500 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); | |
f078f209 | 2501 | } |
7322fd19 | 2502 | EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); |
f078f209 | 2503 | |
cbe61d8a | 2504 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) |
f078f209 | 2505 | { |
cb33c412 SB |
2506 | #define MS_REG_READ(x, y) \ |
2507 | (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) | |
2508 | ||
2660b81a | 2509 | if (gpio >= ah->caps.num_gpio_pins) |
f1dc5600 | 2510 | return 0xffffffff; |
f078f209 | 2511 | |
88c1f4f6 S |
2512 | if (AR_DEVID_7010(ah)) { |
2513 | u32 val; | |
2514 | val = REG_READ(ah, AR7010_GPIO_IN); | |
2515 | return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0; | |
2516 | } else if (AR_SREV_9300_20_OR_LATER(ah)) | |
9306990a VT |
2517 | return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & |
2518 | AR_GPIO_BIT(gpio)) != 0; | |
783dfca1 | 2519 | else if (AR_SREV_9271(ah)) |
5b5fa355 | 2520 | return MS_REG_READ(AR9271, gpio) != 0; |
a42acef0 | 2521 | else if (AR_SREV_9287_11_OR_LATER(ah)) |
ac88b6ec | 2522 | return MS_REG_READ(AR9287, gpio) != 0; |
e17f83ea | 2523 | else if (AR_SREV_9285_12_OR_LATER(ah)) |
cb33c412 | 2524 | return MS_REG_READ(AR9285, gpio) != 0; |
7a37081e | 2525 | else if (AR_SREV_9280_20_OR_LATER(ah)) |
cb33c412 SB |
2526 | return MS_REG_READ(AR928X, gpio) != 0; |
2527 | else | |
2528 | return MS_REG_READ(AR, gpio) != 0; | |
f078f209 | 2529 | } |
7322fd19 | 2530 | EXPORT_SYMBOL(ath9k_hw_gpio_get); |
f078f209 | 2531 | |
cbe61d8a | 2532 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, |
f1dc5600 | 2533 | u32 ah_signal_type) |
f078f209 | 2534 | { |
f1dc5600 | 2535 | u32 gpio_shift; |
f078f209 | 2536 | |
88c1f4f6 S |
2537 | if (AR_DEVID_7010(ah)) { |
2538 | gpio_shift = gpio; | |
2539 | REG_RMW(ah, AR7010_GPIO_OE, | |
2540 | (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift), | |
2541 | (AR7010_GPIO_OE_MASK << gpio_shift)); | |
2542 | return; | |
2543 | } | |
f078f209 | 2544 | |
88c1f4f6 | 2545 | ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); |
f1dc5600 | 2546 | gpio_shift = 2 * gpio; |
f1dc5600 S |
2547 | REG_RMW(ah, |
2548 | AR_GPIO_OE_OUT, | |
2549 | (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), | |
2550 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); | |
f078f209 | 2551 | } |
7322fd19 | 2552 | EXPORT_SYMBOL(ath9k_hw_cfg_output); |
f078f209 | 2553 | |
cbe61d8a | 2554 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) |
f078f209 | 2555 | { |
88c1f4f6 S |
2556 | if (AR_DEVID_7010(ah)) { |
2557 | val = val ? 0 : 1; | |
2558 | REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), | |
2559 | AR_GPIO_BIT(gpio)); | |
2560 | return; | |
2561 | } | |
2562 | ||
5b5fa355 S |
2563 | if (AR_SREV_9271(ah)) |
2564 | val = ~val; | |
2565 | ||
f1dc5600 S |
2566 | REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), |
2567 | AR_GPIO_BIT(gpio)); | |
f078f209 | 2568 | } |
7322fd19 | 2569 | EXPORT_SYMBOL(ath9k_hw_set_gpio); |
f078f209 | 2570 | |
cbe61d8a | 2571 | u32 ath9k_hw_getdefantenna(struct ath_hw *ah) |
f078f209 | 2572 | { |
f1dc5600 | 2573 | return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; |
f078f209 | 2574 | } |
7322fd19 | 2575 | EXPORT_SYMBOL(ath9k_hw_getdefantenna); |
f078f209 | 2576 | |
cbe61d8a | 2577 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) |
f078f209 | 2578 | { |
f1dc5600 | 2579 | REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); |
f078f209 | 2580 | } |
7322fd19 | 2581 | EXPORT_SYMBOL(ath9k_hw_setantenna); |
f078f209 | 2582 | |
f1dc5600 S |
2583 | /*********************/ |
2584 | /* General Operation */ | |
2585 | /*********************/ | |
2586 | ||
cbe61d8a | 2587 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah) |
f078f209 | 2588 | { |
f1dc5600 S |
2589 | u32 bits = REG_READ(ah, AR_RX_FILTER); |
2590 | u32 phybits = REG_READ(ah, AR_PHY_ERR); | |
f078f209 | 2591 | |
f1dc5600 S |
2592 | if (phybits & AR_PHY_ERR_RADAR) |
2593 | bits |= ATH9K_RX_FILTER_PHYRADAR; | |
2594 | if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) | |
2595 | bits |= ATH9K_RX_FILTER_PHYERR; | |
dc2222a8 | 2596 | |
f1dc5600 | 2597 | return bits; |
f078f209 | 2598 | } |
7322fd19 | 2599 | EXPORT_SYMBOL(ath9k_hw_getrxfilter); |
f078f209 | 2600 | |
cbe61d8a | 2601 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) |
f078f209 | 2602 | { |
f1dc5600 | 2603 | u32 phybits; |
f078f209 | 2604 | |
7d0d0df0 S |
2605 | ENABLE_REGWRITE_BUFFER(ah); |
2606 | ||
423e38e8 | 2607 | if (AR_SREV_9462(ah)) |
2577c6e8 SB |
2608 | bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER; |
2609 | ||
7ea310be S |
2610 | REG_WRITE(ah, AR_RX_FILTER, bits); |
2611 | ||
f1dc5600 S |
2612 | phybits = 0; |
2613 | if (bits & ATH9K_RX_FILTER_PHYRADAR) | |
2614 | phybits |= AR_PHY_ERR_RADAR; | |
2615 | if (bits & ATH9K_RX_FILTER_PHYERR) | |
2616 | phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; | |
2617 | REG_WRITE(ah, AR_PHY_ERR, phybits); | |
f078f209 | 2618 | |
f1dc5600 | 2619 | if (phybits) |
ca7a4deb | 2620 | REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); |
f1dc5600 | 2621 | else |
ca7a4deb | 2622 | REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); |
7d0d0df0 S |
2623 | |
2624 | REGWRITE_BUFFER_FLUSH(ah); | |
f1dc5600 | 2625 | } |
7322fd19 | 2626 | EXPORT_SYMBOL(ath9k_hw_setrxfilter); |
f078f209 | 2627 | |
cbe61d8a | 2628 | bool ath9k_hw_phy_disable(struct ath_hw *ah) |
f1dc5600 | 2629 | { |
63a75b91 SB |
2630 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) |
2631 | return false; | |
2632 | ||
2633 | ath9k_hw_init_pll(ah, NULL); | |
2634 | return true; | |
f1dc5600 | 2635 | } |
7322fd19 | 2636 | EXPORT_SYMBOL(ath9k_hw_phy_disable); |
f078f209 | 2637 | |
cbe61d8a | 2638 | bool ath9k_hw_disable(struct ath_hw *ah) |
f1dc5600 | 2639 | { |
9ecdef4b | 2640 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
f1dc5600 | 2641 | return false; |
f078f209 | 2642 | |
63a75b91 SB |
2643 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) |
2644 | return false; | |
2645 | ||
2646 | ath9k_hw_init_pll(ah, NULL); | |
2647 | return true; | |
f078f209 | 2648 | } |
7322fd19 | 2649 | EXPORT_SYMBOL(ath9k_hw_disable); |
f078f209 | 2650 | |
ca2c68cc FF |
2651 | static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) |
2652 | { | |
2653 | enum eeprom_param gain_param; | |
2654 | ||
2655 | if (IS_CHAN_2GHZ(chan)) | |
2656 | gain_param = EEP_ANTENNA_GAIN_2G; | |
2657 | else | |
2658 | gain_param = EEP_ANTENNA_GAIN_5G; | |
2659 | ||
2660 | return ah->eep_ops->get_eeprom(ah, gain_param); | |
2661 | } | |
2662 | ||
2663 | void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan) | |
2664 | { | |
2665 | struct ath_regulatory *reg = ath9k_hw_regulatory(ah); | |
2666 | struct ieee80211_channel *channel; | |
2667 | int chan_pwr, new_pwr, max_gain; | |
2668 | int ant_gain, ant_reduction = 0; | |
2669 | ||
2670 | if (!chan) | |
2671 | return; | |
2672 | ||
2673 | channel = chan->chan; | |
2674 | chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER); | |
2675 | new_pwr = min_t(int, chan_pwr, reg->power_limit); | |
2676 | max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2; | |
2677 | ||
2678 | ant_gain = get_antenna_gain(ah, chan); | |
2679 | if (ant_gain > max_gain) | |
2680 | ant_reduction = ant_gain - max_gain; | |
2681 | ||
2682 | ah->eep_ops->set_txpower(ah, chan, | |
2683 | ath9k_regd_get_ctl(reg, chan), | |
2684 | ant_reduction, new_pwr, false); | |
2685 | } | |
2686 | ||
de40f316 | 2687 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) |
f078f209 | 2688 | { |
ca2c68cc | 2689 | struct ath_regulatory *reg = ath9k_hw_regulatory(ah); |
2660b81a | 2690 | struct ath9k_channel *chan = ah->curchan; |
5f8e077c | 2691 | struct ieee80211_channel *channel = chan->chan; |
9c204b46 | 2692 | |
48ef5c42 | 2693 | reg->power_limit = min_t(u32, limit, MAX_RATE_POWER); |
9c204b46 | 2694 | if (test) |
ca2c68cc | 2695 | channel->max_power = MAX_RATE_POWER / 2; |
f078f209 | 2696 | |
ca2c68cc | 2697 | ath9k_hw_apply_txpower(ah, chan); |
6f255425 | 2698 | |
ca2c68cc FF |
2699 | if (test) |
2700 | channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2); | |
6f255425 | 2701 | } |
7322fd19 | 2702 | EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); |
6f255425 | 2703 | |
cbe61d8a | 2704 | void ath9k_hw_setopmode(struct ath_hw *ah) |
f078f209 | 2705 | { |
2660b81a | 2706 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
f078f209 | 2707 | } |
7322fd19 | 2708 | EXPORT_SYMBOL(ath9k_hw_setopmode); |
f078f209 | 2709 | |
cbe61d8a | 2710 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) |
f078f209 | 2711 | { |
f1dc5600 S |
2712 | REG_WRITE(ah, AR_MCAST_FIL0, filter0); |
2713 | REG_WRITE(ah, AR_MCAST_FIL1, filter1); | |
f078f209 | 2714 | } |
7322fd19 | 2715 | EXPORT_SYMBOL(ath9k_hw_setmcastfilter); |
f078f209 | 2716 | |
f2b2143e | 2717 | void ath9k_hw_write_associd(struct ath_hw *ah) |
f078f209 | 2718 | { |
1510718d LR |
2719 | struct ath_common *common = ath9k_hw_common(ah); |
2720 | ||
2721 | REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); | |
2722 | REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | | |
2723 | ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); | |
f078f209 | 2724 | } |
7322fd19 | 2725 | EXPORT_SYMBOL(ath9k_hw_write_associd); |
f078f209 | 2726 | |
1c0fc65e BP |
2727 | #define ATH9K_MAX_TSF_READ 10 |
2728 | ||
cbe61d8a | 2729 | u64 ath9k_hw_gettsf64(struct ath_hw *ah) |
f078f209 | 2730 | { |
1c0fc65e BP |
2731 | u32 tsf_lower, tsf_upper1, tsf_upper2; |
2732 | int i; | |
2733 | ||
2734 | tsf_upper1 = REG_READ(ah, AR_TSF_U32); | |
2735 | for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { | |
2736 | tsf_lower = REG_READ(ah, AR_TSF_L32); | |
2737 | tsf_upper2 = REG_READ(ah, AR_TSF_U32); | |
2738 | if (tsf_upper2 == tsf_upper1) | |
2739 | break; | |
2740 | tsf_upper1 = tsf_upper2; | |
2741 | } | |
f078f209 | 2742 | |
1c0fc65e | 2743 | WARN_ON( i == ATH9K_MAX_TSF_READ ); |
f078f209 | 2744 | |
1c0fc65e | 2745 | return (((u64)tsf_upper1 << 32) | tsf_lower); |
f1dc5600 | 2746 | } |
7322fd19 | 2747 | EXPORT_SYMBOL(ath9k_hw_gettsf64); |
f078f209 | 2748 | |
cbe61d8a | 2749 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) |
27abe060 | 2750 | { |
27abe060 | 2751 | REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); |
b9a16197 | 2752 | REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); |
27abe060 | 2753 | } |
7322fd19 | 2754 | EXPORT_SYMBOL(ath9k_hw_settsf64); |
27abe060 | 2755 | |
cbe61d8a | 2756 | void ath9k_hw_reset_tsf(struct ath_hw *ah) |
f1dc5600 | 2757 | { |
f9b604f6 GJ |
2758 | if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, |
2759 | AH_TSF_WRITE_TIMEOUT)) | |
d2182b69 | 2760 | ath_dbg(ath9k_hw_common(ah), RESET, |
226afe68 | 2761 | "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); |
f9b604f6 | 2762 | |
f1dc5600 S |
2763 | REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); |
2764 | } | |
7322fd19 | 2765 | EXPORT_SYMBOL(ath9k_hw_reset_tsf); |
f078f209 | 2766 | |
54e4cec6 | 2767 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) |
f1dc5600 | 2768 | { |
f1dc5600 | 2769 | if (setting) |
2660b81a | 2770 | ah->misc_mode |= AR_PCU_TX_ADD_TSF; |
f1dc5600 | 2771 | else |
2660b81a | 2772 | ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; |
f1dc5600 | 2773 | } |
7322fd19 | 2774 | EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); |
f078f209 | 2775 | |
25c56eec | 2776 | void ath9k_hw_set11nmac2040(struct ath_hw *ah) |
f1dc5600 | 2777 | { |
25c56eec | 2778 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
f1dc5600 S |
2779 | u32 macmode; |
2780 | ||
25c56eec | 2781 | if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) |
f1dc5600 S |
2782 | macmode = AR_2040_JOINED_RX_CLEAR; |
2783 | else | |
2784 | macmode = 0; | |
f078f209 | 2785 | |
f1dc5600 | 2786 | REG_WRITE(ah, AR_2040_MODE, macmode); |
f078f209 | 2787 | } |
ff155a45 VT |
2788 | |
2789 | /* HW Generic timers configuration */ | |
2790 | ||
2791 | static const struct ath_gen_timer_configuration gen_tmr_configuration[] = | |
2792 | { | |
2793 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2794 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2795 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2796 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2797 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2798 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2799 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2800 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, | |
2801 | {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, | |
2802 | {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, | |
2803 | AR_NDP2_TIMER_MODE, 0x0002}, | |
2804 | {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, | |
2805 | AR_NDP2_TIMER_MODE, 0x0004}, | |
2806 | {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, | |
2807 | AR_NDP2_TIMER_MODE, 0x0008}, | |
2808 | {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, | |
2809 | AR_NDP2_TIMER_MODE, 0x0010}, | |
2810 | {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, | |
2811 | AR_NDP2_TIMER_MODE, 0x0020}, | |
2812 | {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, | |
2813 | AR_NDP2_TIMER_MODE, 0x0040}, | |
2814 | {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, | |
2815 | AR_NDP2_TIMER_MODE, 0x0080} | |
2816 | }; | |
2817 | ||
2818 | /* HW generic timer primitives */ | |
2819 | ||
2820 | /* compute and clear index of rightmost 1 */ | |
2821 | static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) | |
2822 | { | |
2823 | u32 b; | |
2824 | ||
2825 | b = *mask; | |
2826 | b &= (0-b); | |
2827 | *mask &= ~b; | |
2828 | b *= debruijn32; | |
2829 | b >>= 27; | |
2830 | ||
2831 | return timer_table->gen_timer_index[b]; | |
2832 | } | |
2833 | ||
dd347f2f | 2834 | u32 ath9k_hw_gettsf32(struct ath_hw *ah) |
ff155a45 VT |
2835 | { |
2836 | return REG_READ(ah, AR_TSF_L32); | |
2837 | } | |
dd347f2f | 2838 | EXPORT_SYMBOL(ath9k_hw_gettsf32); |
ff155a45 VT |
2839 | |
2840 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, | |
2841 | void (*trigger)(void *), | |
2842 | void (*overflow)(void *), | |
2843 | void *arg, | |
2844 | u8 timer_index) | |
2845 | { | |
2846 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
2847 | struct ath_gen_timer *timer; | |
2848 | ||
2849 | timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); | |
2850 | ||
2851 | if (timer == NULL) { | |
3800276a JP |
2852 | ath_err(ath9k_hw_common(ah), |
2853 | "Failed to allocate memory for hw timer[%d]\n", | |
2854 | timer_index); | |
ff155a45 VT |
2855 | return NULL; |
2856 | } | |
2857 | ||
2858 | /* allocate a hardware generic timer slot */ | |
2859 | timer_table->timers[timer_index] = timer; | |
2860 | timer->index = timer_index; | |
2861 | timer->trigger = trigger; | |
2862 | timer->overflow = overflow; | |
2863 | timer->arg = arg; | |
2864 | ||
2865 | return timer; | |
2866 | } | |
7322fd19 | 2867 | EXPORT_SYMBOL(ath_gen_timer_alloc); |
ff155a45 | 2868 | |
cd9bf689 LR |
2869 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
2870 | struct ath_gen_timer *timer, | |
788f6875 | 2871 | u32 trig_timeout, |
cd9bf689 | 2872 | u32 timer_period) |
ff155a45 VT |
2873 | { |
2874 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
788f6875 | 2875 | u32 tsf, timer_next; |
ff155a45 VT |
2876 | |
2877 | BUG_ON(!timer_period); | |
2878 | ||
2879 | set_bit(timer->index, &timer_table->timer_mask.timer_bits); | |
2880 | ||
2881 | tsf = ath9k_hw_gettsf32(ah); | |
2882 | ||
788f6875 VT |
2883 | timer_next = tsf + trig_timeout; |
2884 | ||
d2182b69 | 2885 | ath_dbg(ath9k_hw_common(ah), HWTIMER, |
226afe68 JP |
2886 | "current tsf %x period %x timer_next %x\n", |
2887 | tsf, timer_period, timer_next); | |
ff155a45 | 2888 | |
ff155a45 VT |
2889 | /* |
2890 | * Program generic timer registers | |
2891 | */ | |
2892 | REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, | |
2893 | timer_next); | |
2894 | REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, | |
2895 | timer_period); | |
2896 | REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, | |
2897 | gen_tmr_configuration[timer->index].mode_mask); | |
2898 | ||
423e38e8 | 2899 | if (AR_SREV_9462(ah)) { |
2577c6e8 | 2900 | /* |
423e38e8 | 2901 | * Starting from AR9462, each generic timer can select which tsf |
2577c6e8 SB |
2902 | * to use. But we still follow the old rule, 0 - 7 use tsf and |
2903 | * 8 - 15 use tsf2. | |
2904 | */ | |
2905 | if ((timer->index < AR_GEN_TIMER_BANK_1_LEN)) | |
2906 | REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, | |
2907 | (1 << timer->index)); | |
2908 | else | |
2909 | REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, | |
2910 | (1 << timer->index)); | |
2911 | } | |
2912 | ||
ff155a45 VT |
2913 | /* Enable both trigger and thresh interrupt masks */ |
2914 | REG_SET_BIT(ah, AR_IMR_S5, | |
2915 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | | |
2916 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); | |
ff155a45 | 2917 | } |
7322fd19 | 2918 | EXPORT_SYMBOL(ath9k_hw_gen_timer_start); |
ff155a45 | 2919 | |
cd9bf689 | 2920 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) |
ff155a45 VT |
2921 | { |
2922 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
2923 | ||
2924 | if ((timer->index < AR_FIRST_NDP_TIMER) || | |
2925 | (timer->index >= ATH_MAX_GEN_TIMER)) { | |
2926 | return; | |
2927 | } | |
2928 | ||
2929 | /* Clear generic timer enable bits. */ | |
2930 | REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, | |
2931 | gen_tmr_configuration[timer->index].mode_mask); | |
2932 | ||
2933 | /* Disable both trigger and thresh interrupt masks */ | |
2934 | REG_CLR_BIT(ah, AR_IMR_S5, | |
2935 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | | |
2936 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); | |
2937 | ||
2938 | clear_bit(timer->index, &timer_table->timer_mask.timer_bits); | |
ff155a45 | 2939 | } |
7322fd19 | 2940 | EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); |
ff155a45 VT |
2941 | |
2942 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) | |
2943 | { | |
2944 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
2945 | ||
2946 | /* free the hardware generic timer slot */ | |
2947 | timer_table->timers[timer->index] = NULL; | |
2948 | kfree(timer); | |
2949 | } | |
7322fd19 | 2950 | EXPORT_SYMBOL(ath_gen_timer_free); |
ff155a45 VT |
2951 | |
2952 | /* | |
2953 | * Generic Timer Interrupts handling | |
2954 | */ | |
2955 | void ath_gen_timer_isr(struct ath_hw *ah) | |
2956 | { | |
2957 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; | |
2958 | struct ath_gen_timer *timer; | |
c46917bb | 2959 | struct ath_common *common = ath9k_hw_common(ah); |
ff155a45 VT |
2960 | u32 trigger_mask, thresh_mask, index; |
2961 | ||
2962 | /* get hardware generic timer interrupt status */ | |
2963 | trigger_mask = ah->intr_gen_timer_trigger; | |
2964 | thresh_mask = ah->intr_gen_timer_thresh; | |
2965 | trigger_mask &= timer_table->timer_mask.val; | |
2966 | thresh_mask &= timer_table->timer_mask.val; | |
2967 | ||
2968 | trigger_mask &= ~thresh_mask; | |
2969 | ||
2970 | while (thresh_mask) { | |
2971 | index = rightmost_index(timer_table, &thresh_mask); | |
2972 | timer = timer_table->timers[index]; | |
2973 | BUG_ON(!timer); | |
d2182b69 JP |
2974 | ath_dbg(common, HWTIMER, "TSF overflow for Gen timer %d\n", |
2975 | index); | |
ff155a45 VT |
2976 | timer->overflow(timer->arg); |
2977 | } | |
2978 | ||
2979 | while (trigger_mask) { | |
2980 | index = rightmost_index(timer_table, &trigger_mask); | |
2981 | timer = timer_table->timers[index]; | |
2982 | BUG_ON(!timer); | |
d2182b69 | 2983 | ath_dbg(common, HWTIMER, |
226afe68 | 2984 | "Gen timer[%d] trigger\n", index); |
ff155a45 VT |
2985 | timer->trigger(timer->arg); |
2986 | } | |
2987 | } | |
7322fd19 | 2988 | EXPORT_SYMBOL(ath_gen_timer_isr); |
2da4f01a | 2989 | |
05020d23 S |
2990 | /********/ |
2991 | /* HTC */ | |
2992 | /********/ | |
2993 | ||
2994 | void ath9k_hw_htc_resetinit(struct ath_hw *ah) | |
2995 | { | |
2996 | ah->htc_reset_init = true; | |
2997 | } | |
2998 | EXPORT_SYMBOL(ath9k_hw_htc_resetinit); | |
2999 | ||
2da4f01a LR |
3000 | static struct { |
3001 | u32 version; | |
3002 | const char * name; | |
3003 | } ath_mac_bb_names[] = { | |
3004 | /* Devices with external radios */ | |
3005 | { AR_SREV_VERSION_5416_PCI, "5416" }, | |
3006 | { AR_SREV_VERSION_5416_PCIE, "5418" }, | |
3007 | { AR_SREV_VERSION_9100, "9100" }, | |
3008 | { AR_SREV_VERSION_9160, "9160" }, | |
3009 | /* Single-chip solutions */ | |
3010 | { AR_SREV_VERSION_9280, "9280" }, | |
3011 | { AR_SREV_VERSION_9285, "9285" }, | |
11158472 LR |
3012 | { AR_SREV_VERSION_9287, "9287" }, |
3013 | { AR_SREV_VERSION_9271, "9271" }, | |
ec83903e | 3014 | { AR_SREV_VERSION_9300, "9300" }, |
2c8e5937 | 3015 | { AR_SREV_VERSION_9330, "9330" }, |
397e5d5b | 3016 | { AR_SREV_VERSION_9340, "9340" }, |
8f06ca2c | 3017 | { AR_SREV_VERSION_9485, "9485" }, |
423e38e8 | 3018 | { AR_SREV_VERSION_9462, "9462" }, |
2da4f01a LR |
3019 | }; |
3020 | ||
3021 | /* For devices with external radios */ | |
3022 | static struct { | |
3023 | u16 version; | |
3024 | const char * name; | |
3025 | } ath_rf_names[] = { | |
3026 | { 0, "5133" }, | |
3027 | { AR_RAD5133_SREV_MAJOR, "5133" }, | |
3028 | { AR_RAD5122_SREV_MAJOR, "5122" }, | |
3029 | { AR_RAD2133_SREV_MAJOR, "2133" }, | |
3030 | { AR_RAD2122_SREV_MAJOR, "2122" } | |
3031 | }; | |
3032 | ||
3033 | /* | |
3034 | * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. | |
3035 | */ | |
f934c4d9 | 3036 | static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) |
2da4f01a LR |
3037 | { |
3038 | int i; | |
3039 | ||
3040 | for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { | |
3041 | if (ath_mac_bb_names[i].version == mac_bb_version) { | |
3042 | return ath_mac_bb_names[i].name; | |
3043 | } | |
3044 | } | |
3045 | ||
3046 | return "????"; | |
3047 | } | |
2da4f01a LR |
3048 | |
3049 | /* | |
3050 | * Return the RF name. "????" is returned if the RF is unknown. | |
3051 | * Used for devices with external radios. | |
3052 | */ | |
f934c4d9 | 3053 | static const char *ath9k_hw_rf_name(u16 rf_version) |
2da4f01a LR |
3054 | { |
3055 | int i; | |
3056 | ||
3057 | for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { | |
3058 | if (ath_rf_names[i].version == rf_version) { | |
3059 | return ath_rf_names[i].name; | |
3060 | } | |
3061 | } | |
3062 | ||
3063 | return "????"; | |
3064 | } | |
f934c4d9 LR |
3065 | |
3066 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) | |
3067 | { | |
3068 | int used; | |
3069 | ||
3070 | /* chipsets >= AR9280 are single-chip */ | |
7a37081e | 3071 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
f934c4d9 LR |
3072 | used = snprintf(hw_name, len, |
3073 | "Atheros AR%s Rev:%x", | |
3074 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), | |
3075 | ah->hw_version.macRev); | |
3076 | } | |
3077 | else { | |
3078 | used = snprintf(hw_name, len, | |
3079 | "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", | |
3080 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), | |
3081 | ah->hw_version.macRev, | |
3082 | ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & | |
3083 | AR_RADIO_SREV_MAJOR)), | |
3084 | ah->hw_version.phyRev); | |
3085 | } | |
3086 | ||
3087 | hw_name[used] = '\0'; | |
3088 | } | |
3089 | EXPORT_SYMBOL(ath9k_hw_name); |