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drm: vmwgfx: Use nsec based interfaces
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
5a0e3ad6 18#include <linux/slab.h>
9d9779e7 19#include <linux/module.h>
09d8e315 20#include <linux/time.h>
c67ce339 21#include <linux/bitops.h>
f078f209
LR		 22#include <asm/unaligned.h>
23
af03abec 24#include "hw.h"
d70357d5 25#include "hw-ops.h"
b622a720 26#include "ar9003_mac.h"
f4701b5a 27#include "ar9003_mci.h"
362cd03f 28#include "ar9003_phy.h"
462e58f2 29#include "ath9k.h"
f078f209 30
cbe61d8a 31static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 32
7322fd19
LR		 33MODULE_AUTHOR("Atheros Communications");
34MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
35MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
36MODULE_LICENSE("Dual BSD/GPL");
37
dfdac8ac 38static void ath9k_hw_set_clockrate(struct ath_hw *ah)
f1dc5600 39{
dfdac8ac 40 struct ath_common *common = ath9k_hw_common(ah);
e4744ec7 41 struct ath9k_channel *chan = ah->curchan;
dfdac8ac 42 unsigned int clockrate;
cbe61d8a 43
087b6ff6
FF		 44 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
45 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
46 clockrate = 117;
e4744ec7 47 else if (!chan) /* should really check for CCK instead */
dfdac8ac 48 clockrate = ATH9K_CLOCK_RATE_CCK;
e4744ec7 49 else if (IS_CHAN_2GHZ(chan))
dfdac8ac
FF		 50 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
51 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
52 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
e5553724 53 else
dfdac8ac
FF		 54 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
55
beae416b
MN		 56 if (chan) {
57 if (IS_CHAN_HT40(chan))
58 clockrate *= 2;
e4744ec7 59 if (IS_CHAN_HALF_RATE(chan))
906c7205 60 clockrate /= 2;
e4744ec7 61 if (IS_CHAN_QUARTER_RATE(chan))
906c7205
FF		 62 clockrate /= 4;
63 }
64
dfdac8ac 65 common->clockrate = clockrate;
f1dc5600
S		 66}
67
cbe61d8a 68static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 69{
dfdac8ac 70 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 71
dfdac8ac 72 return usecs * common->clockrate;
f1dc5600 73}
f078f209 74
0caa7b14 75bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 76{
77 int i;
78
0caa7b14
S		 79 BUG_ON(timeout < AH_TIME_QUANTUM);
80
81 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 82 if ((REG_READ(ah, reg) & mask) == val)
83 return true;
84
85 udelay(AH_TIME_QUANTUM);
86 }
04bd4638 87
d2182b69 88 ath_dbg(ath9k_hw_common(ah), ANY,
226afe68
JP		 89 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
90 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 91
f1dc5600 92 return false;
f078f209 93}
7322fd19 94EXPORT_SYMBOL(ath9k_hw_wait);
f078f209 95
7c5adc8d
FF		 96void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
97 int hw_delay)
98{
1a5e6326 99 hw_delay /= 10;
7c5adc8d
FF		 100
101 if (IS_CHAN_HALF_RATE(chan))
102 hw_delay *= 2;
103 else if (IS_CHAN_QUARTER_RATE(chan))
104 hw_delay *= 4;
105
106 udelay(hw_delay + BASE_ACTIVATE_DELAY);
107}
108
0166b4be 109void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
a9b6b256
FF		 110 int column, unsigned int *writecnt)
111{
112 int r;
113
114 ENABLE_REGWRITE_BUFFER(ah);
115 for (r = 0; r < array->ia_rows; r++) {
116 REG_WRITE(ah, INI_RA(array, r, 0),
117 INI_RA(array, r, column));
118 DO_DELAY(*writecnt);
119 }
120 REGWRITE_BUFFER_FLUSH(ah);
121}
122
f078f209
LR		 123u32 ath9k_hw_reverse_bits(u32 val, u32 n)
124{
125 u32 retval;
126 int i;
127
128 for (i = 0, retval = 0; i < n; i++) {
129 retval = (retval << 1) | (val & 1);
130 val >>= 1;
131 }
132 return retval;
133}
134
cbe61d8a 135u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 136 u8 phy, int kbps,
f1dc5600
S		 137 u32 frameLen, u16 rateix,
138 bool shortPreamble)
f078f209 139{
f1dc5600 140 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 141
f1dc5600
S		 142 if (kbps == 0)
143 return 0;
f078f209 144
545750d3 145 switch (phy) {
46d14a58 146 case WLAN_RC_PHY_CCK:
f1dc5600 147 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 148 if (shortPreamble)
f1dc5600
S		 149 phyTime >>= 1;
150 numBits = frameLen << 3;
151 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
152 break;
46d14a58 153 case WLAN_RC_PHY_OFDM:
2660b81a 154 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 155 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
156 numBits = OFDM_PLCP_BITS + (frameLen << 3);
157 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
158 txTime = OFDM_SIFS_TIME_QUARTER
159 + OFDM_PREAMBLE_TIME_QUARTER
160 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 161 } else if (ah->curchan &&
162 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 163 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
164 numBits = OFDM_PLCP_BITS + (frameLen << 3);
165 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
166 txTime = OFDM_SIFS_TIME_HALF +
167 OFDM_PREAMBLE_TIME_HALF
168 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
169 } else {
170 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
171 numBits = OFDM_PLCP_BITS + (frameLen << 3);
172 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
173 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
174 + (numSymbols * OFDM_SYMBOL_TIME);
175 }
176 break;
177 default:
3800276a
JP		 178 ath_err(ath9k_hw_common(ah),
179 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 180 txTime = 0;
181 break;
182 }
f078f209 183
f1dc5600
S		 184 return txTime;
185}
7322fd19 186EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 187
cbe61d8a 188void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 189 struct ath9k_channel *chan,
190 struct chan_centers *centers)
f078f209 191{
f1dc5600 192 int8_t extoff;
f078f209 193
f1dc5600
S		 194 if (!IS_CHAN_HT40(chan)) {
195 centers->ctl_center = centers->ext_center =
196 centers->synth_center = chan->channel;
197 return;
f078f209 198 }
f078f209 199
8896934c 200 if (IS_CHAN_HT40PLUS(chan)) {
f1dc5600
S		 201 centers->synth_center =
202 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
203 extoff = 1;
204 } else {
205 centers->synth_center =
206 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
207 extoff = -1;
208 }
f078f209 209
f1dc5600
S		 210 centers->ctl_center =
211 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 212 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 213 centers->ext_center =
6420014c 214 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 215}
216
f1dc5600
S		 217/******************/
218/* Chip Revisions */
219/******************/
220
cbe61d8a 221static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 222{
f1dc5600 223 u32 val;
f078f209 224
ecb1d385
VT		 225 switch (ah->hw_version.devid) {
226 case AR5416_AR9100_DEVID:
227 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
228 break;
3762561a
GJ		 229 case AR9300_DEVID_AR9330:
230 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
231 if (ah->get_mac_revision) {
232 ah->hw_version.macRev = ah->get_mac_revision();
233 } else {
234 val = REG_READ(ah, AR_SREV);
235 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
236 }
237 return;
ecb1d385
VT		 238 case AR9300_DEVID_AR9340:
239 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
240 val = REG_READ(ah, AR_SREV);
241 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
242 return;
813831dc
GJ		 243 case AR9300_DEVID_QCA955X:
244 ah->hw_version.macVersion = AR_SREV_VERSION_9550;
245 return;
e6b1e46e
SM		 246 case AR9300_DEVID_AR953X:
247 ah->hw_version.macVersion = AR_SREV_VERSION_9531;
7a42e4e7
FF		 248 if (ah->get_mac_revision)
249 ah->hw_version.macRev = ah->get_mac_revision();
e6b1e46e 250 return;
ecb1d385
VT		 251 }
252
f1dc5600 253 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 254
f1dc5600
S		 255 if (val == 0xFF) {
256 val = REG_READ(ah, AR_SREV);
d535a42a
S		 257 ah->hw_version.macVersion =
258 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
259 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
76ed94be 260
77fac465 261 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
76ed94be
MSS		 262 ah->is_pciexpress = true;
263 else
264 ah->is_pciexpress = (val &
265 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 266 } else {
267 if (!AR_SREV_9100(ah))
d535a42a 268 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 269
d535a42a 270 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 271
d535a42a 272 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 273 ah->is_pciexpress = true;
f1dc5600 274 }
f078f209
LR		 275}
276
f1dc5600
S		 277/************************************/
278/* HW Attach, Detach, Init Routines */
279/************************************/
280
cbe61d8a 281static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 282{
040b74f7 283 if (!AR_SREV_5416(ah))
f1dc5600 284 return;
f078f209 285
f1dc5600
S		 286 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 295
f1dc5600 296 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 297}
298
1f3f0618 299/* This should work for all families including legacy */
cbe61d8a 300static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 301{
c46917bb 302 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 303 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600 304 u32 regHold[2];
07b2fa5a
JP		 305 static const u32 patternData[4] = {
306 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
307 };
1f3f0618 308 int i, j, loop_max;
f078f209 309
1f3f0618
SB		 310 if (!AR_SREV_9300_20_OR_LATER(ah)) {
311 loop_max = 2;
312 regAddr[1] = AR_PHY_BASE + (8 << 2);
313 } else
314 loop_max = 1;
315
316 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 317 u32 addr = regAddr[i];
318 u32 wrData, rdData;
f078f209 319
f1dc5600
S		 320 regHold[i] = REG_READ(ah, addr);
321 for (j = 0; j < 0x100; j++) {
322 wrData = (j << 16) | j;
323 REG_WRITE(ah, addr, wrData);
324 rdData = REG_READ(ah, addr);
325 if (rdData != wrData) {
3800276a
JP		 326 ath_err(common,
327 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
328 addr, wrData, rdData);
f1dc5600
S		 329 return false;
330 }
331 }
332 for (j = 0; j < 4; j++) {
333 wrData = patternData[j];
334 REG_WRITE(ah, addr, wrData);
335 rdData = REG_READ(ah, addr);
336 if (wrData != rdData) {
3800276a
JP		 337 ath_err(common,
338 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
339 addr, wrData, rdData);
f1dc5600
S		 340 return false;
341 }
f078f209 342 }
f1dc5600 343 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 344 }
f1dc5600 345 udelay(100);
cbe61d8a 346
f078f209
LR		 347 return true;
348}
349
b8b0f377 350static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600 351{
f57cf939
SM		 352 struct ath_common *common = ath9k_hw_common(ah);
353
689e756f
FF		 354 ah->config.dma_beacon_response_time = 1;
355 ah->config.sw_beacon_response_time = 6;
2660b81a 356 ah->config.cwm_ignore_extcca = 0;
2660b81a 357 ah->config.analog_shiftreg = 1;
f078f209 358
0ce024cb 359 ah->config.rx_intr_mitigation = true;
6158425b 360
a64e1a45
SM		 361 if (AR_SREV_9300_20_OR_LATER(ah)) {
362 ah->config.rimt_last = 500;
363 ah->config.rimt_first = 2000;
364 } else {
365 ah->config.rimt_last = 250;
366 ah->config.rimt_first = 700;
367 }
368
6158425b
LR		 369 /*
370 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
371 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
372 * This means we use it for all AR5416 devices, and the few
373 * minor PCI AR9280 devices out there.
374 *
375 * Serialization is required because these devices do not handle
376 * well the case of two concurrent reads/writes due to the latency
377 * involved. During one read/write another read/write can be issued
378 * on another CPU while the previous read/write may still be working
379 * on our hardware, if we hit this case the hardware poops in a loop.
380 * We prevent this by serializing reads and writes.
381 *
382 * This issue is not present on PCI-Express devices or pre-AR5416
383 * devices (legacy, 802.11abg).
384 */
385 if (num_possible_cpus() > 1)
2d6a5e95 386 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f57cf939
SM		 387
388 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
389 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
390 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
391 !ah->is_pciexpress)) {
392 ah->config.serialize_regmode = SER_REG_MODE_ON;
393 } else {
394 ah->config.serialize_regmode = SER_REG_MODE_OFF;
395 }
396 }
397
398 ath_dbg(common, RESET, "serialize_regmode is %d\n",
399 ah->config.serialize_regmode);
400
401 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
402 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
403 else
404 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
f078f209
LR		 405}
406
50aca25b 407static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 408{
608b88cb
LR		 409 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
410
411 regulatory->country_code = CTRY_DEFAULT;
412 regulatory->power_limit = MAX_RATE_POWER;
608b88cb 413
d535a42a 414 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 415 ah->hw_version.subvendorid = 0;
f078f209 416
f57cf939
SM		 417 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
418 AR_STA_ID1_MCAST_KSRCH;
f171760c
FF		 419 if (AR_SREV_9100(ah))
420 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
f57cf939 421
e3f2acc7 422 ah->slottime = ATH9K_SLOT_TIME_9;
2660b81a 423 ah->globaltxtimeout = (u32) -1;
cbdec975 424 ah->power_mode = ATH9K_PM_UNDEFINED;
8efa7a81 425 ah->htc_reset_init = true;
f57cf939
SM		 426
427 ah->ani_function = ATH9K_ANI_ALL;
428 if (!AR_SREV_9300_20_OR_LATER(ah))
429 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
430
431 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
432 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
433 else
434 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209
LR		 435}
436
cbe61d8a 437static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 438{
1510718d 439 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 440 u32 sum;
441 int i;
442 u16 eeval;
07b2fa5a 443 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 444
445 sum = 0;
446 for (i = 0; i < 3; i++) {
49101676 447 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 448 sum += eeval;
1510718d
LR		 449 common->macaddr[2 * i] = eeval >> 8;
450 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 451 }
d8baa939 452 if (sum == 0 || sum == 0xffff * 3)
f078f209 453 return -EADDRNOTAVAIL;
f078f209
LR		 454
455 return 0;
456}
457
f637cfd6 458static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 459{
6cae913d 460 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600 461 int ecode;
f078f209 462
6cae913d 463 if (common->bus_ops->ath_bus_type != ATH_USB) {
527d485f
S		 464 if (!ath9k_hw_chip_test(ah))
465 return -ENODEV;
466 }
f078f209 467
ebd5a14a
LR		 468 if (!AR_SREV_9300_20_OR_LATER(ah)) {
469 ecode = ar9002_hw_rf_claim(ah);
470 if (ecode != 0)
471 return ecode;
472 }
f078f209 473
f637cfd6 474 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 475 if (ecode != 0)
476 return ecode;
7d01b221 477
d2182b69 478 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
226afe68
JP		 479 ah->eep_ops->get_eeprom_ver(ah),
480 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 481
e323300d 482 ath9k_hw_ani_init(ah);
f078f209 483
d3b371cb
SM		 484 /*
485 * EEPROM needs to be initialized before we do this.
486 * This is required for regulatory compliance.
487 */
0c7c2bb4 488 if (AR_SREV_9300_20_OR_LATER(ah)) {
d3b371cb
SM		 489 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
490 if ((regdmn & 0xF0) == CTL_FCC) {
0c7c2bb4
SM		 491 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
492 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
d3b371cb
SM		 493 }
494 }
495
f078f209
LR		 496 return 0;
497}
498
c1b976d2 499static int ath9k_hw_attach_ops(struct ath_hw *ah)
ee2bb460 500{
c1b976d2
FF		 501 if (!AR_SREV_9300_20_OR_LATER(ah))
502 return ar9002_hw_attach_ops(ah);
503
504 ar9003_hw_attach_ops(ah);
505 return 0;
aa4058ae
LR		 506}
507
d70357d5
LR		 508/* Called for all hardware families */
509static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 510{
c46917bb 511 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 512 int r = 0;
aa4058ae 513
ac45c12d
SB		 514 ath9k_hw_read_revisions(ah);
515
de82582b
SM		 516 switch (ah->hw_version.macVersion) {
517 case AR_SREV_VERSION_5416_PCI:
518 case AR_SREV_VERSION_5416_PCIE:
519 case AR_SREV_VERSION_9160:
520 case AR_SREV_VERSION_9100:
521 case AR_SREV_VERSION_9280:
522 case AR_SREV_VERSION_9285:
523 case AR_SREV_VERSION_9287:
524 case AR_SREV_VERSION_9271:
525 case AR_SREV_VERSION_9300:
526 case AR_SREV_VERSION_9330:
527 case AR_SREV_VERSION_9485:
528 case AR_SREV_VERSION_9340:
529 case AR_SREV_VERSION_9462:
530 case AR_SREV_VERSION_9550:
531 case AR_SREV_VERSION_9565:
e6b1e46e 532 case AR_SREV_VERSION_9531:
de82582b
SM		 533 break;
534 default:
535 ath_err(common,
536 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
537 ah->hw_version.macVersion, ah->hw_version.macRev);
538 return -EOPNOTSUPP;
539 }
540
0a8d7cb0
SB		 541 /*
542 * Read back AR_WA into a permanent copy and set bits 14 and 17.
543 * We need to do this to avoid RMW of this register. We cannot
544 * read the reg when chip is asleep.
545 */
27251e00
SM		 546 if (AR_SREV_9300_20_OR_LATER(ah)) {
547 ah->WARegVal = REG_READ(ah, AR_WA);
548 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
549 AR_WA_ASPM_TIMER_BASED_DISABLE);
550 }
0a8d7cb0 551
aa4058ae 552 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
3800276a 553 ath_err(common, "Couldn't reset chip\n");
95fafca2 554 return -EIO;
aa4058ae
LR		 555 }
556
a4a2954f
SM		 557 if (AR_SREV_9565(ah)) {
558 ah->WARegVal |= AR_WA_BIT22;
559 REG_WRITE(ah, AR_WA, ah->WARegVal);
560 }
561
bab1f62e
LR		 562 ath9k_hw_init_defaults(ah);
563 ath9k_hw_init_config(ah);
564
c1b976d2
FF		 565 r = ath9k_hw_attach_ops(ah);
566 if (r)
567 return r;
d70357d5 568
9ecdef4b 569 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
3800276a 570 ath_err(common, "Couldn't wakeup chip\n");
95fafca2 571 return -EIO;
aa4058ae
LR		 572 }
573
2c8e5937 574 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
c95b584b 575 AR_SREV_9330(ah) || AR_SREV_9550(ah))
d7e7d229
LR		 576 ah->is_pciexpress = false;
577
aa4058ae 578 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 579 ath9k_hw_init_cal_settings(ah);
580
69ce674b 581 if (!ah->is_pciexpress)
aa4058ae
LR		 582 ath9k_hw_disablepcie(ah);
583
f637cfd6 584 r = ath9k_hw_post_init(ah);
aa4058ae 585 if (r)
95fafca2 586 return r;
aa4058ae
LR		 587
588 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 589 r = ath9k_hw_fill_cap_info(ah);
590 if (r)
591 return r;
592
4f3acf81
LR		 593 r = ath9k_hw_init_macaddr(ah);
594 if (r) {
3800276a 595 ath_err(common, "Failed to initialize MAC address\n");
95fafca2 596 return r;
f078f209
LR		 597 }
598
4598702d 599 ath9k_hw_init_hang_checks(ah);
f078f209 600
211f5859
LR		 601 common->state = ATH_HW_INITIALIZED;
602
4f3acf81 603 return 0;
f078f209
LR		 604}
605
d70357d5 606int ath9k_hw_init(struct ath_hw *ah)
f078f209 607{
d70357d5
LR		 608 int ret;
609 struct ath_common *common = ath9k_hw_common(ah);
f078f209 610
77fac465 611 /* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
d70357d5
LR		 612 switch (ah->hw_version.devid) {
613 case AR5416_DEVID_PCI:
614 case AR5416_DEVID_PCIE:
615 case AR5416_AR9100_DEVID:
616 case AR9160_DEVID_PCI:
617 case AR9280_DEVID_PCI:
618 case AR9280_DEVID_PCIE:
619 case AR9285_DEVID_PCIE:
db3cc53a
SB		 620 case AR9287_DEVID_PCI:
621 case AR9287_DEVID_PCIE:
d70357d5 622 case AR2427_DEVID_PCIE:
db3cc53a 623 case AR9300_DEVID_PCIE:
3050c914 624 case AR9300_DEVID_AR9485_PCIE:
999a7a88 625 case AR9300_DEVID_AR9330:
bca04689 626 case AR9300_DEVID_AR9340:
2b943a33 627 case AR9300_DEVID_QCA955X:
5a63ef0f 628 case AR9300_DEVID_AR9580:
423e38e8 629 case AR9300_DEVID_AR9462:
d4e5979c 630 case AR9485_DEVID_AR1111:
77fac465 631 case AR9300_DEVID_AR9565:
e6b1e46e 632 case AR9300_DEVID_AR953X:
d70357d5
LR		 633 break;
634 default:
635 if (common->bus_ops->ath_bus_type == ATH_USB)
636 break;
3800276a
JP		 637 ath_err(common, "Hardware device ID 0x%04x not supported\n",
638 ah->hw_version.devid);
d70357d5
LR		 639 return -EOPNOTSUPP;
640 }
f078f209 641
d70357d5
LR		 642 ret = __ath9k_hw_init(ah);
643 if (ret) {
3800276a
JP		 644 ath_err(common,
645 "Unable to initialize hardware; initialization status: %d\n",
646 ret);
d70357d5
LR		 647 return ret;
648 }
f078f209 649
d70357d5 650 return 0;
f078f209 651}
d70357d5 652EXPORT_SYMBOL(ath9k_hw_init);
f078f209 653
cbe61d8a 654static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 655{
7d0d0df0
S		 656 ENABLE_REGWRITE_BUFFER(ah);
657
f1dc5600
S		 658 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
659 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 660
f1dc5600
S		 661 REG_WRITE(ah, AR_QOS_NO_ACK,
662 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
663 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
664 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
665
666 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
667 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
668 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
669 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
670 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
7d0d0df0
S		 671
672 REGWRITE_BUFFER_FLUSH(ah);
f078f209
LR		 673}
674
b84628eb 675u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
b1415819 676{
f18e3c6b
MSS		 677 struct ath_common *common = ath9k_hw_common(ah);
678 int i = 0;
679
ca7a4deb
FF		 680 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
681 udelay(100);
682 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
b1415819 683
f18e3c6b
MSS		 684 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
685
ca7a4deb 686 udelay(100);
b1415819 687
f18e3c6b
MSS		 688 if (WARN_ON_ONCE(i >= 100)) {
689 ath_err(common, "PLL4 meaurement not done\n");
690 break;
691 }
692
693 i++;
694 }
695
ca7a4deb 696 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
b1415819
VN		 697}
698EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
699
cbe61d8a 700static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 701 struct ath9k_channel *chan)
f078f209 702{
d09b17f7
VT		 703 u32 pll;
704
a4a2954f 705 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3dfd7f60
VT		 706 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
707 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
708 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
709 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
710 AR_CH0_DPLL2_KD, 0x40);
711 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
712 AR_CH0_DPLL2_KI, 0x4);
22983c30 713
3dfd7f60
VT		 714 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
715 AR_CH0_BB_DPLL1_REFDIV, 0x5);
716 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
717 AR_CH0_BB_DPLL1_NINI, 0x58);
718 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
719 AR_CH0_BB_DPLL1_NFRAC, 0x0);
22983c30
VN		 720
721 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60
VT		 722 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
723 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
724 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
22983c30 725 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
3dfd7f60 726 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
22983c30 727
3dfd7f60 728 /* program BB PLL phase_shift to 0x6 */
22983c30 729 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
3dfd7f60
VT		 730 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
731
732 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
733 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
75e03512 734 udelay(1000);
a5415d62
GJ		 735 } else if (AR_SREV_9330(ah)) {
736 u32 ddr_dpll2, pll_control2, kd;
737
738 if (ah->is_clk_25mhz) {
739 ddr_dpll2 = 0x18e82f01;
740 pll_control2 = 0xe04a3d;
741 kd = 0x1d;
742 } else {
743 ddr_dpll2 = 0x19e82f01;
744 pll_control2 = 0x886666;
745 kd = 0x3d;
746 }
747
748 /* program DDR PLL ki and kd value */
749 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
750
751 /* program DDR PLL phase_shift */
752 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
753 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
754
755 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
756 udelay(1000);
757
758 /* program refdiv, nint, frac to RTC register */
759 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
760
761 /* program BB PLL kd and ki value */
762 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
763 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
764
765 /* program BB PLL phase_shift */
766 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
767 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
2c323058 768 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
0b488ac6
VT		 769 u32 regval, pll2_divint, pll2_divfrac, refdiv;
770
771 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
772 udelay(1000);
773
774 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
775 udelay(100);
776
777 if (ah->is_clk_25mhz) {
2c323058
SM		 778 if (AR_SREV_9531(ah)) {
779 pll2_divint = 0x1c;
780 pll2_divfrac = 0xa3d2;
781 refdiv = 1;
782 } else {
783 pll2_divint = 0x54;
784 pll2_divfrac = 0x1eb85;
785 refdiv = 3;
786 }
0b488ac6 787 } else {
fc05a317
GJ		 788 if (AR_SREV_9340(ah)) {
789 pll2_divint = 88;
790 pll2_divfrac = 0;
791 refdiv = 5;
792 } else {
793 pll2_divint = 0x11;
794 pll2_divfrac = 0x26666;
795 refdiv = 1;
796 }
0b488ac6
VT		 797 }
798
799 regval = REG_READ(ah, AR_PHY_PLL_MODE);
2c323058
SM		 800 if (AR_SREV_9531(ah))
801 regval |= (0x1 << 22);
802 else
803 regval |= (0x1 << 16);
0b488ac6
VT		 804 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
805 udelay(100);
806
807 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
808 (pll2_divint << 18) | pll2_divfrac);
809 udelay(100);
810
811 regval = REG_READ(ah, AR_PHY_PLL_MODE);
fc05a317 812 if (AR_SREV_9340(ah))
2c323058
SM		 813 regval = (regval & 0x80071fff) |
814 (0x1 << 30) |
815 (0x1 << 13) |
816 (0x4 << 26) |
817 (0x18 << 19);
818 else if (AR_SREV_9531(ah))
819 regval = (regval & 0x01c00fff) |
820 (0x1 << 31) |
821 (0x2 << 29) |
822 (0xa << 25) |
823 (0x1 << 19) |
824 (0x6 << 12);
fc05a317 825 else
2c323058
SM		 826 regval = (regval & 0x80071fff) |
827 (0x3 << 30) |
828 (0x1 << 13) |
829 (0x4 << 26) |
830 (0x60 << 19);
0b488ac6 831 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
2c323058
SM		 832
833 if (AR_SREV_9531(ah))
834 REG_WRITE(ah, AR_PHY_PLL_MODE,
835 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
836 else
837 REG_WRITE(ah, AR_PHY_PLL_MODE,
838 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
839
0b488ac6 840 udelay(1000);
22983c30 841 }
d09b17f7
VT		 842
843 pll = ath9k_hw_compute_pll_control(ah, chan);
8565f8bf
SM		 844 if (AR_SREV_9565(ah))
845 pll |= 0x40000;
d03a66c1 846 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 847
fc05a317
GJ		 848 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
849 AR_SREV_9550(ah))
3dfd7f60
VT		 850 udelay(1000);
851
c75724d1
LR		 852 /* Switch the core clock for ar9271 to 117Mhz */
853 if (AR_SREV_9271(ah)) {
25e2ab17
S		 854 udelay(500);
855 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 856 }
857
f1dc5600
S		 858 udelay(RTC_PLL_SETTLE_DELAY);
859
860 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
0b488ac6 861
fc05a317 862 if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
0b488ac6
VT		 863 if (ah->is_clk_25mhz) {
864 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
865 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
866 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
867 } else {
868 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
869 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
870 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
871 }
872 udelay(100);
873 }
f078f209
LR		 874}
875
cbe61d8a 876static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 877 enum nl80211_iftype opmode)
f078f209 878{
79d1d2b8 879 u32 sync_default = AR_INTR_SYNC_DEFAULT;
152d530d 880 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 881 AR_IMR_TXURN |
882 AR_IMR_RXERR |
883 AR_IMR_RXORN |
884 AR_IMR_BCNMISC;
f078f209 885
c90d4f7b 886 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah))
79d1d2b8
VT		 887 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
888
66860240
VT		 889 if (AR_SREV_9300_20_OR_LATER(ah)) {
890 imr_reg |= AR_IMR_RXOK_HP;
891 if (ah->config.rx_intr_mitigation)
892 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
893 else
894 imr_reg |= AR_IMR_RXOK_LP;
f078f209 895
66860240
VT		 896 } else {
897 if (ah->config.rx_intr_mitigation)
898 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
899 else
900 imr_reg |= AR_IMR_RXOK;
901 }
f078f209 902
66860240
VT		 903 if (ah->config.tx_intr_mitigation)
904 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
905 else
906 imr_reg |= AR_IMR_TXOK;
f078f209 907
7d0d0df0
S		 908 ENABLE_REGWRITE_BUFFER(ah);
909
152d530d 910 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 911 ah->imrs2_reg |= AR_IMR_S2_GTT;
912 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 913
f1dc5600
S		 914 if (!AR_SREV_9100(ah)) {
915 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
79d1d2b8 916 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
f1dc5600
S		 917 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
918 }
66860240 919
7d0d0df0 920 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 921
66860240
VT		 922 if (AR_SREV_9300_20_OR_LATER(ah)) {
923 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
924 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
925 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
926 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
927 }
f078f209
LR		 928}
929
b6ba41bb
FF		 930static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
931{
932 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
933 val = min(val, (u32) 0xFFFF);
934 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
935}
936
0005baf4 937static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 938{
0005baf4
FF		 939 u32 val = ath9k_hw_mac_to_clks(ah, us);
940 val = min(val, (u32) 0xFFFF);
941 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 942}
943
0005baf4 944static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 945{
0005baf4
FF		 946 u32 val = ath9k_hw_mac_to_clks(ah, us);
947 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
948 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
949}
950
951static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
952{
953 u32 val = ath9k_hw_mac_to_clks(ah, us);
954 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
955 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 956}
f1dc5600 957
cbe61d8a 958static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 959{
f078f209 960 if (tu > 0xFFFF) {
d2182b69
JP		 961 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
962 tu);
2660b81a 963 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 964 return false;
965 } else {
966 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 967 ah->globaltxtimeout = tu;
f078f209
LR		 968 return true;
969 }
970}
971
0005baf4 972void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 973{
b6ba41bb 974 struct ath_common *common = ath9k_hw_common(ah);
b6ba41bb 975 const struct ath9k_channel *chan = ah->curchan;
e115b7ec 976 int acktimeout, ctstimeout, ack_offset = 0;
e239d859 977 int slottime;
0005baf4 978 int sifstime;
b6ba41bb
FF		 979 int rx_lat = 0, tx_lat = 0, eifs = 0;
980 u32 reg;
0005baf4 981
d2182b69 982 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
226afe68 983 ah->misc_mode);
f078f209 984
b6ba41bb
FF		 985 if (!chan)
986 return;
987
2660b81a 988 if (ah->misc_mode != 0)
ca7a4deb 989 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
0005baf4 990
81a91d57
RM		 991 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
992 rx_lat = 41;
993 else
994 rx_lat = 37;
b6ba41bb
FF		 995 tx_lat = 54;
996
e88e4861
FF		 997 if (IS_CHAN_5GHZ(chan))
998 sifstime = 16;
999 else
1000 sifstime = 10;
1001
b6ba41bb
FF		 1002 if (IS_CHAN_HALF_RATE(chan)) {
1003 eifs = 175;
1004 rx_lat *= 2;
1005 tx_lat *= 2;
1006 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1007 tx_lat += 11;
1008
92367fe7 1009 sifstime = 32;
e115b7ec 1010 ack_offset = 16;
b6ba41bb 1011 slottime = 13;
b6ba41bb
FF		 1012 } else if (IS_CHAN_QUARTER_RATE(chan)) {
1013 eifs = 340;
81a91d57 1014 rx_lat = (rx_lat * 4) - 1;
b6ba41bb
FF		 1015 tx_lat *= 4;
1016 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1017 tx_lat += 22;
1018
92367fe7 1019 sifstime = 64;
e115b7ec 1020 ack_offset = 32;
b6ba41bb 1021 slottime = 21;
b6ba41bb 1022 } else {
a7be039d
RM		 1023 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1024 eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1025 reg = AR_USEC_ASYNC_FIFO;
1026 } else {
1027 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1028 common->clockrate;
1029 reg = REG_READ(ah, AR_USEC);
1030 }
b6ba41bb
FF		 1031 rx_lat = MS(reg, AR_USEC_RX_LAT);
1032 tx_lat = MS(reg, AR_USEC_TX_LAT);
1033
1034 slottime = ah->slottime;
b6ba41bb 1035 }
0005baf4 1036
e239d859 1037 /* As defined by IEEE 802.11-2007 17.3.8.6 */
f77f8234
MK		 1038 slottime += 3 * ah->coverage_class;
1039 acktimeout = slottime + sifstime + ack_offset;
adb5066a 1040 ctstimeout = acktimeout;
42c4568a
FF		 1041
1042 /*
1043 * Workaround for early ACK timeouts, add an offset to match the
55a2bb4a 1044 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
42c4568a
FF		 1045 * This was initially only meant to work around an issue with delayed
1046 * BA frames in some implementations, but it has been found to fix ACK
1047 * timeout issues in other cases as well.
1048 */
e4744ec7 1049 if (IS_CHAN_2GHZ(chan) &&
e115b7ec 1050 !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
42c4568a 1051 acktimeout += 64 - sifstime - ah->slottime;
55a2bb4a
FF		 1052 ctstimeout += 48 - sifstime - ah->slottime;
1053 }
1054
b6ba41bb
FF		 1055 ath9k_hw_set_sifs_time(ah, sifstime);
1056 ath9k_hw_setslottime(ah, slottime);
0005baf4 1057 ath9k_hw_set_ack_timeout(ah, acktimeout);
adb5066a 1058 ath9k_hw_set_cts_timeout(ah, ctstimeout);
2660b81a
S		 1059 if (ah->globaltxtimeout != (u32) -1)
1060 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
b6ba41bb
FF		 1061
1062 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1063 REG_RMW(ah, AR_USEC,
1064 (common->clockrate - 1) |
1065 SM(rx_lat, AR_USEC_RX_LAT) |
1066 SM(tx_lat, AR_USEC_TX_LAT),
1067 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1068
f1dc5600 1069}
0005baf4 1070EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 1071
285f2dda 1072void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 1073{
211f5859
LR		 1074 struct ath_common *common = ath9k_hw_common(ah);
1075
736b3a27 1076 if (common->state < ATH_HW_INITIALIZED)
c1b976d2 1077 return;
211f5859 1078
9ecdef4b 1079 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
f1dc5600 1080}
285f2dda 1081EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 1082
f1dc5600
S		 1083/*******/
1084/* INI */
1085/*******/
1086
8fe65368 1087u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 1088{
1089 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1090
6b21fd20 1091 if (IS_CHAN_2GHZ(chan))
3a702e49
BC		 1092 ctl |= CTL_11G;
1093 else
1094 ctl |= CTL_11A;
1095
1096 return ctl;
1097}
1098
f1dc5600
S		 1099/****************************************/
1100/* Reset and Channel Switching Routines */
1101/****************************************/
f1dc5600 1102
cbe61d8a 1103static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600 1104{
57b32227 1105 struct ath_common *common = ath9k_hw_common(ah);
86c157b3 1106 int txbuf_size;
f1dc5600 1107
7d0d0df0
S		 1108 ENABLE_REGWRITE_BUFFER(ah);
1109
d7e7d229
LR		 1110 /*
1111 * set AHB_MODE not to do cacheline prefetches
1112 */
ca7a4deb
FF		 1113 if (!AR_SREV_9300_20_OR_LATER(ah))
1114 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
f1dc5600 1115
d7e7d229
LR		 1116 /*
1117 * let mac dma reads be in 128 byte chunks
1118 */
ca7a4deb 1119 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
f1dc5600 1120
7d0d0df0 1121 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1122
d7e7d229
LR		 1123 /*
1124 * Restore TX Trigger Level to its pre-reset value.
1125 * The initial value depends on whether aggregation is enabled, and is
1126 * adjusted whenever underruns are detected.
1127 */
57b32227
FF		 1128 if (!AR_SREV_9300_20_OR_LATER(ah))
1129 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 1130
7d0d0df0 1131 ENABLE_REGWRITE_BUFFER(ah);
f1dc5600 1132
d7e7d229
LR		 1133 /*
1134 * let mac dma writes be in 128 byte chunks
1135 */
ca7a4deb 1136 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
f1dc5600 1137
d7e7d229
LR		 1138 /*
1139 * Setup receive FIFO threshold to hold off TX activities
1140 */
f1dc5600
S		 1141 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1142
57b32227
FF		 1143 if (AR_SREV_9300_20_OR_LATER(ah)) {
1144 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1145 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1146
1147 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1148 ah->caps.rx_status_len);
1149 }
1150
d7e7d229
LR		 1151 /*
1152 * reduce the number of usable entries in PCU TXBUF to avoid
1153 * wrap around issues.
1154 */
f1dc5600 1155 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 1156 /* For AR9285 the number of Fifos are reduced to half.
1157 * So set the usable tx buf size also to half to
1158 * avoid data/delimiter underruns
1159 */
86c157b3
FF		 1160 txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1161 } else if (AR_SREV_9340_13_OR_LATER(ah)) {
1162 /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1163 txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1164 } else {
1165 txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
f1dc5600 1166 }
744d4025 1167
86c157b3
FF		 1168 if (!AR_SREV_9271(ah))
1169 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1170
7d0d0df0 1171 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1172
744d4025
VT		 1173 if (AR_SREV_9300_20_OR_LATER(ah))
1174 ath9k_hw_reset_txstatus_ring(ah);
f1dc5600
S		 1175}
1176
cbe61d8a 1177static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600 1178{
ca7a4deb
FF		 1179 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1180 u32 set = AR_STA_ID1_KSRCH_MODE;
f1dc5600 1181
f1dc5600 1182 switch (opmode) {
d97809db 1183 case NL80211_IFTYPE_ADHOC:
ca7a4deb 1184 set |= AR_STA_ID1_ADHOC;
f1dc5600 1185 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1186 break;
2664d666 1187 case NL80211_IFTYPE_MESH_POINT:
ca7a4deb
FF		 1188 case NL80211_IFTYPE_AP:
1189 set |= AR_STA_ID1_STA_AP;
1190 /* fall through */
d97809db 1191 case NL80211_IFTYPE_STATION:
ca7a4deb 1192 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 1193 break;
5f841b41 1194 default:
ca7a4deb
FF		 1195 if (!ah->is_monitoring)
1196 set = 0;
5f841b41 1197 break;
f1dc5600 1198 }
ca7a4deb 1199 REG_RMW(ah, AR_STA_ID1, set, mask);
f1dc5600
S		 1200}
1201
8fe65368
LR		 1202void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1203 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 1204{
1205 u32 coef_exp, coef_man;
1206
1207 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1208 if ((coef_scaled >> coef_exp) & 0x1)
1209 break;
1210
1211 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1212
1213 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1214
1215 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1216 *coef_exponent = coef_exp - 16;
1217}
1218
d7df7a55
SM		 1219/* AR9330 WAR:
1220 * call external reset function to reset WMAC if:
1221 * - doing a cold reset
1222 * - we have pending frames in the TX queues.
1223 */
1224static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1225{
1226 int i, npend = 0;
1227
1228 for (i = 0; i < AR_NUM_QCU; i++) {
1229 npend = ath9k_hw_numtxpending(ah, i);
1230 if (npend)
1231 break;
1232 }
1233
1234 if (ah->external_reset &&
1235 (npend || type == ATH9K_RESET_COLD)) {
1236 int reset_err = 0;
1237
1238 ath_dbg(ath9k_hw_common(ah), RESET,
1239 "reset MAC via external reset\n");
1240
1241 reset_err = ah->external_reset();
1242 if (reset_err) {
1243 ath_err(ath9k_hw_common(ah),
1244 "External reset failed, err=%d\n",
1245 reset_err);
1246 return false;
1247 }
1248
1249 REG_WRITE(ah, AR_RTC_RESET, 1);
1250 }
1251
1252 return true;
1253}
1254
cbe61d8a 1255static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 1256{
1257 u32 rst_flags;
1258 u32 tmpReg;
1259
70768496 1260 if (AR_SREV_9100(ah)) {
ca7a4deb
FF		 1261 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1262 AR_RTC_DERIVED_CLK_PERIOD, 1);
70768496
S		 1263 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1264 }
1265
7d0d0df0
S		 1266 ENABLE_REGWRITE_BUFFER(ah);
1267
9a658d2b
LR		 1268 if (AR_SREV_9300_20_OR_LATER(ah)) {
1269 REG_WRITE(ah, AR_WA, ah->WARegVal);
1270 udelay(10);
1271 }
1272
f1dc5600
S		 1273 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1274 AR_RTC_FORCE_WAKE_ON_INT);
1275
1276 if (AR_SREV_9100(ah)) {
1277 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1278 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1279 } else {
1280 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
a37a9910
FF		 1281 if (AR_SREV_9340(ah))
1282 tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1283 else
1284 tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1285 AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1286
1287 if (tmpReg) {
42d5bc3f 1288 u32 val;
f1dc5600 1289 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1290
1291 val = AR_RC_HOSTIF;
1292 if (!AR_SREV_9300_20_OR_LATER(ah))
1293 val |= AR_RC_AHB;
1294 REG_WRITE(ah, AR_RC, val);
1295
1296 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1297 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1298
1299 rst_flags = AR_RTC_RC_MAC_WARM;
1300 if (type == ATH9K_RESET_COLD)
1301 rst_flags |= AR_RTC_RC_MAC_COLD;
1302 }
1303
7d95847c 1304 if (AR_SREV_9330(ah)) {
d7df7a55
SM		 1305 if (!ath9k_hw_ar9330_reset_war(ah, type))
1306 return false;
7d95847c
GJ		 1307 }
1308
3863495b 1309 if (ath9k_hw_mci_is_enabled(ah))
506847ad 1310 ar9003_mci_check_gpm_offset(ah);
3863495b 1311
d03a66c1 1312 REG_WRITE(ah, AR_RTC_RC, rst_flags);
7d0d0df0
S		 1313
1314 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1315
4dc78c43
SM		 1316 if (AR_SREV_9300_20_OR_LATER(ah))
1317 udelay(50);
1318 else if (AR_SREV_9100(ah))
3683a07b 1319 mdelay(10);
4dc78c43
SM		 1320 else
1321 udelay(100);
f1dc5600 1322
d03a66c1 1323 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1324 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
d2182b69 1325 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
f1dc5600
S		 1326 return false;
1327 }
1328
1329 if (!AR_SREV_9100(ah))
1330 REG_WRITE(ah, AR_RC, 0);
1331
f1dc5600
S		 1332 if (AR_SREV_9100(ah))
1333 udelay(50);
1334
1335 return true;
1336}
1337
cbe61d8a 1338static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600 1339{
7d0d0df0
S		 1340 ENABLE_REGWRITE_BUFFER(ah);
1341
9a658d2b
LR		 1342 if (AR_SREV_9300_20_OR_LATER(ah)) {
1343 REG_WRITE(ah, AR_WA, ah->WARegVal);
1344 udelay(10);
1345 }
1346
f1dc5600
S		 1347 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1348 AR_RTC_FORCE_WAKE_ON_INT);
1349
42d5bc3f 1350 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1351 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1352
d03a66c1 1353 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1354
7d0d0df0 1355 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1356
afe36533 1357 udelay(2);
84e2169b
SB		 1358
1359 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1360 REG_WRITE(ah, AR_RC, 0);
1361
d03a66c1 1362 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1363
1364 if (!ath9k_hw_wait(ah,
1365 AR_RTC_STATUS,
1366 AR_RTC_STATUS_M,
0caa7b14
S		 1367 AR_RTC_STATUS_ON,
1368 AH_WAIT_TIMEOUT)) {
d2182b69 1369 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
f1dc5600 1370 return false;
f078f209
LR		 1371 }
1372
f1dc5600
S		 1373 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1374}
1375
cbe61d8a 1376static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600 1377{
7a9233ff 1378 bool ret = false;
2577c6e8 1379
9a658d2b
LR		 1380 if (AR_SREV_9300_20_OR_LATER(ah)) {
1381 REG_WRITE(ah, AR_WA, ah->WARegVal);
1382 udelay(10);
1383 }
1384
f1dc5600
S		 1385 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1386 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1387
ceb26a60
FF		 1388 if (!ah->reset_power_on)
1389 type = ATH9K_RESET_POWER_ON;
1390
f1dc5600
S		 1391 switch (type) {
1392 case ATH9K_RESET_POWER_ON:
7a9233ff 1393 ret = ath9k_hw_set_reset_power_on(ah);
da8fb123 1394 if (ret)
ceb26a60 1395 ah->reset_power_on = true;
7a9233ff 1396 break;
f1dc5600
S		 1397 case ATH9K_RESET_WARM:
1398 case ATH9K_RESET_COLD:
7a9233ff
MSS		 1399 ret = ath9k_hw_set_reset(ah, type);
1400 break;
f1dc5600 1401 default:
7a9233ff 1402 break;
f1dc5600 1403 }
7a9233ff 1404
7a9233ff 1405 return ret;
f078f209
LR		 1406}
1407
cbe61d8a 1408static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1409 struct ath9k_channel *chan)
f078f209 1410{
9c083af8
FF		 1411 int reset_type = ATH9K_RESET_WARM;
1412
1413 if (AR_SREV_9280(ah)) {
1414 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1415 reset_type = ATH9K_RESET_POWER_ON;
1416 else
1417 reset_type = ATH9K_RESET_COLD;
3412f2f0
FF		 1418 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1419 (REG_READ(ah, AR_CR) & AR_CR_RXE))
1420 reset_type = ATH9K_RESET_COLD;
9c083af8
FF		 1421
1422 if (!ath9k_hw_set_reset_reg(ah, reset_type))
f1dc5600 1423 return false;
f078f209 1424
9ecdef4b 1425 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1426 return false;
f078f209 1427
2660b81a 1428 ah->chip_fullsleep = false;
bfc441a4
FF		 1429
1430 if (AR_SREV_9330(ah))
1431 ar9003_hw_internal_regulator_apply(ah);
f1dc5600 1432 ath9k_hw_init_pll(ah, chan);
f078f209 1433
f1dc5600 1434 return true;
f078f209
LR		 1435}
1436
cbe61d8a 1437static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1438 struct ath9k_channel *chan)
f078f209 1439{
c46917bb 1440 struct ath_common *common = ath9k_hw_common(ah);
b840cffe
SM		 1441 struct ath9k_hw_capabilities *pCap = &ah->caps;
1442 bool band_switch = false, mode_diff = false;
70e89a71 1443 u8 ini_reloaded = 0;
8fe65368 1444 u32 qnum;
0a3b7bac 1445 int r;
5f0c04ea 1446
b840cffe 1447 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
af02efb3
FF		 1448 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1449 band_switch = !!(flags_diff & CHANNEL_5GHZ);
1450 mode_diff = !!(flags_diff & ~CHANNEL_HT);
b840cffe 1451 }
f078f209
LR		 1452
1453 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1454 if (ath9k_hw_numtxpending(ah, qnum)) {
d2182b69 1455 ath_dbg(common, QUEUE,
226afe68 1456 "Transmit frames pending on queue %d\n", qnum);
f078f209
LR		 1457 return false;
1458 }
1459 }
1460
8fe65368 1461 if (!ath9k_hw_rfbus_req(ah)) {
3800276a 1462 ath_err(common, "Could not kill baseband RX\n");
f078f209
LR		 1463 return false;
1464 }
1465
b840cffe 1466 if (band_switch || mode_diff) {
5f0c04ea
RM		 1467 ath9k_hw_mark_phy_inactive(ah);
1468 udelay(5);
1469
5f35c0fa
SM		 1470 if (band_switch)
1471 ath9k_hw_init_pll(ah, chan);
5f0c04ea
RM		 1472
1473 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1474 ath_err(common, "Failed to do fast channel change\n");
1475 return false;
1476 }
1477 }
1478
8fe65368 1479 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1480
8fe65368 1481 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac 1482 if (r) {
3800276a 1483 ath_err(common, "Failed to set channel\n");
0a3b7bac 1484 return false;
f078f209 1485 }
dfdac8ac 1486 ath9k_hw_set_clockrate(ah);
64ea57d0 1487 ath9k_hw_apply_txpower(ah, chan, false);
f078f209 1488
81c507a8 1489 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1490 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600 1491
70e89a71
SM		 1492 if (band_switch || ini_reloaded)
1493 ah->eep_ops->set_board_values(ah, chan);
5f0c04ea 1494
70e89a71
SM		 1495 ath9k_hw_init_bb(ah, chan);
1496 ath9k_hw_rfbus_done(ah);
5f0c04ea 1497
70e89a71
SM		 1498 if (band_switch || ini_reloaded) {
1499 ah->ah_flags |= AH_FASTCC;
1500 ath9k_hw_init_cal(ah, chan);
a126ff51 1501 ah->ah_flags &= ~AH_FASTCC;
5f0c04ea
RM		 1502 }
1503
f1dc5600
S		 1504 return true;
1505}
1506
691680b8
FF		 1507static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1508{
1509 u32 gpio_mask = ah->gpio_mask;
1510 int i;
1511
1512 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1513 if (!(gpio_mask & 1))
1514 continue;
1515
1516 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1517 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1518 }
1519}
1520
1e516ca7
SM		 1521void ath9k_hw_check_nav(struct ath_hw *ah)
1522{
1523 struct ath_common *common = ath9k_hw_common(ah);
1524 u32 val;
1525
1526 val = REG_READ(ah, AR_NAV);
1527 if (val != 0xdeadbeef && val > 0x7fff) {
1528 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1529 REG_WRITE(ah, AR_NAV, 0);
1530 }
1531}
1532EXPORT_SYMBOL(ath9k_hw_check_nav);
1533
c9c99e5e 1534bool ath9k_hw_check_alive(struct ath_hw *ah)
3b319aae 1535{
c9c99e5e 1536 int count = 50;
d31a36a6 1537 u32 reg, last_val;
c9c99e5e 1538
01e18918
RM		 1539 if (AR_SREV_9300(ah))
1540 return !ath9k_hw_detect_mac_hang(ah);
1541
e17f83ea 1542 if (AR_SREV_9285_12_OR_LATER(ah))
c9c99e5e
FF		 1543 return true;
1544
d31a36a6 1545 last_val = REG_READ(ah, AR_OBS_BUS_1);
c9c99e5e
FF		 1546 do {
1547 reg = REG_READ(ah, AR_OBS_BUS_1);
d31a36a6
FF		 1548 if (reg != last_val)
1549 return true;
3b319aae 1550
105ff411 1551 udelay(1);
d31a36a6 1552 last_val = reg;
c9c99e5e
FF		 1553 if ((reg & 0x7E7FFFEF) == 0x00702400)
1554 continue;
1555
1556 switch (reg & 0x7E000B00) {
1557 case 0x1E000000:
1558 case 0x52000B00:
1559 case 0x18000B00:
1560 continue;
1561 default:
1562 return true;
1563 }
1564 } while (count-- > 0);
3b319aae 1565
c9c99e5e 1566 return false;
3b319aae 1567}
c9c99e5e 1568EXPORT_SYMBOL(ath9k_hw_check_alive);
3b319aae 1569
15d2b585
SM		 1570static void ath9k_hw_init_mfp(struct ath_hw *ah)
1571{
1572 /* Setup MFP options for CCMP */
1573 if (AR_SREV_9280_20_OR_LATER(ah)) {
1574 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1575 * frames when constructing CCMP AAD. */
1576 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1577 0xc7ff);
1578 ah->sw_mgmt_crypto = false;
1579 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1580 /* Disable hardware crypto for management frames */
1581 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1582 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1583 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1584 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1585 ah->sw_mgmt_crypto = true;
1586 } else {
1587 ah->sw_mgmt_crypto = true;
1588 }
1589}
1590
1591static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1592 u32 macStaId1, u32 saveDefAntenna)
1593{
1594 struct ath_common *common = ath9k_hw_common(ah);
1595
1596 ENABLE_REGWRITE_BUFFER(ah);
1597
ecbbed32 1598 REG_RMW(ah, AR_STA_ID1, macStaId1
15d2b585 1599 | AR_STA_ID1_RTS_USE_DEF
ecbbed32
FF		 1600 | ah->sta_id1_defaults,
1601 ~AR_STA_ID1_SADH_MASK);
15d2b585
SM		 1602 ath_hw_setbssidmask(common);
1603 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1604 ath9k_hw_write_associd(ah);
1605 REG_WRITE(ah, AR_ISR, ~0);
1606 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1607
1608 REGWRITE_BUFFER_FLUSH(ah);
1609
1610 ath9k_hw_set_operating_mode(ah, ah->opmode);
1611}
1612
1613static void ath9k_hw_init_queues(struct ath_hw *ah)
1614{
1615 int i;
1616
1617 ENABLE_REGWRITE_BUFFER(ah);
1618
1619 for (i = 0; i < AR_NUM_DCU; i++)
1620 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1621
1622 REGWRITE_BUFFER_FLUSH(ah);
1623
1624 ah->intr_txqs = 0;
1625 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1626 ath9k_hw_resettxqueue(ah, i);
1627}
1628
1629/*
1630 * For big endian systems turn on swapping for descriptors
1631 */
1632static void ath9k_hw_init_desc(struct ath_hw *ah)
1633{
1634 struct ath_common *common = ath9k_hw_common(ah);
1635
1636 if (AR_SREV_9100(ah)) {
1637 u32 mask;
1638 mask = REG_READ(ah, AR_CFG);
1639 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1640 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1641 mask);
1642 } else {
1643 mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1644 REG_WRITE(ah, AR_CFG, mask);
1645 ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1646 REG_READ(ah, AR_CFG));
1647 }
1648 } else {
1649 if (common->bus_ops->ath_bus_type == ATH_USB) {
1650 /* Configure AR9271 target WLAN */
1651 if (AR_SREV_9271(ah))
1652 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1653 else
1654 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1655 }
1656#ifdef __BIG_ENDIAN
1657 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
2c323058 1658 AR_SREV_9550(ah) || AR_SREV_9531(ah))
15d2b585
SM		 1659 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1660 else
1661 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1662#endif
1663 }
1664}
1665
caed6579
SM		 1666/*
1667 * Fast channel change:
1668 * (Change synthesizer based on channel freq without resetting chip)
caed6579
SM		 1669 */
1670static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1671{
1672 struct ath_common *common = ath9k_hw_common(ah);
b840cffe 1673 struct ath9k_hw_capabilities *pCap = &ah->caps;
caed6579
SM		 1674 int ret;
1675
1676 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1677 goto fail;
1678
1679 if (ah->chip_fullsleep)
1680 goto fail;
1681
1682 if (!ah->curchan)
1683 goto fail;
1684
1685 if (chan->channel == ah->curchan->channel)
1686 goto fail;
1687
feb7bc99
FF		 1688 if ((ah->curchan->channelFlags | chan->channelFlags) &
1689 (CHANNEL_HALF | CHANNEL_QUARTER))
1690 goto fail;
1691
b840cffe 1692 /*
6b21fd20 1693 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
b840cffe 1694 */
6b21fd20 1695 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
af02efb3 1696 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
6b21fd20 1697 goto fail;
caed6579
SM		 1698
1699 if (!ath9k_hw_check_alive(ah))
1700 goto fail;
1701
1702 /*
1703 * For AR9462, make sure that calibration data for
1704 * re-using are present.
1705 */
8a90555f 1706 if (AR_SREV_9462(ah) && (ah->caldata &&
4b9b42bf
SM		 1707 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1708 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1709 !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
caed6579
SM		 1710 goto fail;
1711
1712 ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1713 ah->curchan->channel, chan->channel);
1714
1715 ret = ath9k_hw_channel_change(ah, chan);
1716 if (!ret)
1717 goto fail;
1718
5955b2b0 1719 if (ath9k_hw_mci_is_enabled(ah))
1bde95fa 1720 ar9003_mci_2g5g_switch(ah, false);
caed6579 1721
88033318
RM		 1722 ath9k_hw_loadnf(ah, ah->curchan);
1723 ath9k_hw_start_nfcal(ah, true);
1724
caed6579
SM		 1725 if (AR_SREV_9271(ah))
1726 ar9002_hw_load_ani_reg(ah, chan);
1727
1728 return 0;
1729fail:
1730 return -EINVAL;
1731}
1732
cbe61d8a 1733int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
caed6579 1734 struct ath9k_hw_cal_data *caldata, bool fastcc)
f078f209 1735{
1510718d 1736 struct ath_common *common = ath9k_hw_common(ah);
09d8e315 1737 struct timespec ts;
f078f209 1738 u32 saveLedState;
f078f209
LR		 1739 u32 saveDefAntenna;
1740 u32 macStaId1;
46fe782c 1741 u64 tsf = 0;
09d8e315 1742 s64 usec = 0;
15d2b585 1743 int r;
caed6579 1744 bool start_mci_reset = false;
63d32967
MSS		 1745 bool save_fullsleep = ah->chip_fullsleep;
1746
5955b2b0 1747 if (ath9k_hw_mci_is_enabled(ah)) {
528e5d36
SM		 1748 start_mci_reset = ar9003_mci_start_reset(ah, chan);
1749 if (start_mci_reset)
1750 return 0;
63d32967
MSS		 1751 }
1752
9ecdef4b 1753 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1754 return -EIO;
f078f209 1755
caed6579
SM		 1756 if (ah->curchan && !ah->chip_fullsleep)
1757 ath9k_hw_getnf(ah, ah->curchan);
f078f209 1758
20bd2a09 1759 ah->caldata = caldata;
fcb9a3de 1760 if (caldata && (chan->channel != caldata->channel ||
6b21fd20 1761 chan->channelFlags != caldata->channelFlags)) {
20bd2a09
FF		 1762 /* Operating channel changed, reset channel calibration data */
1763 memset(caldata, 0, sizeof(*caldata));
1764 ath9k_init_nfcal_hist_buffer(ah, chan);
51dea9be 1765 } else if (caldata) {
4b9b42bf 1766 clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
20bd2a09 1767 }
5bc225ac 1768 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
20bd2a09 1769
caed6579
SM		 1770 if (fastcc) {
1771 r = ath9k_hw_do_fastcc(ah, chan);
1772 if (!r)
1773 return r;
f078f209
LR		 1774 }
1775
5955b2b0 1776 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1777 ar9003_mci_stop_bt(ah, save_fullsleep);
63d32967 1778
f078f209
LR		 1779 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1780 if (saveDefAntenna == 0)
1781 saveDefAntenna = 1;
1782
1783 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1784
09d8e315
FF		 1785 /* Save TSF before chip reset, a cold reset clears it */
1786 tsf = ath9k_hw_gettsf64(ah);
1787 getrawmonotonic(&ts);
cca213fd 1788 usec = ts.tv_sec * 1000000ULL + ts.tv_nsec / 1000;
46fe782c 1789
f078f209
LR		 1790 saveLedState = REG_READ(ah, AR_CFG_LED) &
1791 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1792 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1793
1794 ath9k_hw_mark_phy_inactive(ah);
1795
45ef6a0b
VT		 1796 ah->paprd_table_write_done = false;
1797
05020d23 1798 /* Only required on the first reset */
d7e7d229
LR		 1799 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1800 REG_WRITE(ah,
1801 AR9271_RESET_POWER_DOWN_CONTROL,
1802 AR9271_RADIO_RF_RST);
1803 udelay(50);
1804 }
1805
f078f209 1806 if (!ath9k_hw_chip_reset(ah, chan)) {
3800276a 1807 ath_err(common, "Chip reset failed\n");
ae8d2858 1808 return -EINVAL;
f078f209
LR		 1809 }
1810
05020d23 1811 /* Only required on the first reset */
d7e7d229
LR		 1812 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1813 ah->htc_reset_init = false;
1814 REG_WRITE(ah,
1815 AR9271_RESET_POWER_DOWN_CONTROL,
1816 AR9271_GATE_MAC_CTL);
1817 udelay(50);
1818 }
1819
46fe782c 1820 /* Restore TSF */
09d8e315 1821 getrawmonotonic(&ts);
cca213fd 1822 usec = ts.tv_sec * 1000000ULL + ts.tv_nsec / 1000 - usec;
09d8e315 1823 ath9k_hw_settsf64(ah, tsf + usec);
46fe782c 1824
7a37081e 1825 if (AR_SREV_9280_20_OR_LATER(ah))
369391db 1826 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1827
e9141f71
S		 1828 if (!AR_SREV_9300_20_OR_LATER(ah))
1829 ar9002_hw_enable_async_fifo(ah);
1830
25c56eec 1831 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1832 if (r)
1833 return r;
f078f209 1834
935d00cc
LB		 1835 ath9k_hw_set_rfmode(ah, chan);
1836
5955b2b0 1837 if (ath9k_hw_mci_is_enabled(ah))
63d32967
MSS		 1838 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1839
f860d526
FF		 1840 /*
1841 * Some AR91xx SoC devices frequently fail to accept TSF writes
1842 * right after the chip reset. When that happens, write a new
1843 * value after the initvals have been applied, with an offset
1844 * based on measured time difference
1845 */
1846 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1847 tsf += 1500;
1848 ath9k_hw_settsf64(ah, tsf);
1849 }
1850
15d2b585 1851 ath9k_hw_init_mfp(ah);
0ced0e17 1852
81c507a8 1853 ath9k_hw_set_delta_slope(ah, chan);
8fe65368 1854 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1855 ah->eep_ops->set_board_values(ah, chan);
a7765828 1856
15d2b585 1857 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
00e0003e 1858
8fe65368 1859 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1860 if (r)
1861 return r;
f078f209 1862
dfdac8ac
FF		 1863 ath9k_hw_set_clockrate(ah);
1864
15d2b585 1865 ath9k_hw_init_queues(ah);
2660b81a 1866 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
e36b27af 1867 ath9k_hw_ani_cache_ini_regs(ah);
f078f209
LR		 1868 ath9k_hw_init_qos(ah);
1869
2660b81a 1870 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
55821324 1871 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3b319aae 1872
0005baf4 1873 ath9k_hw_init_global_settings(ah);
f078f209 1874
fe2b6afb
FF		 1875 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1876 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1877 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1878 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1879 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1880 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1881 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
ac88b6ec
VN		 1882 }
1883
ca7a4deb 1884 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
f078f209
LR		 1885
1886 ath9k_hw_set_dma(ah);
1887
ed6ebd8b
RM		 1888 if (!ath9k_hw_mci_is_enabled(ah))
1889 REG_WRITE(ah, AR_OBS, 8);
f078f209 1890
0ce024cb 1891 if (ah->config.rx_intr_mitigation) {
a64e1a45
SM		 1892 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
1893 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
f078f209
LR		 1894 }
1895
7f62a136
VT		 1896 if (ah->config.tx_intr_mitigation) {
1897 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1898 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1899 }
1900
f078f209
LR		 1901 ath9k_hw_init_bb(ah, chan);
1902
77a5a664 1903 if (caldata) {
4b9b42bf
SM		 1904 clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
1905 clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
77a5a664 1906 }
ae8d2858 1907 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1908 return -EIO;
f078f209 1909
5955b2b0 1910 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
528e5d36 1911 return -EIO;
63d32967 1912
7d0d0df0 1913 ENABLE_REGWRITE_BUFFER(ah);
f078f209 1914
8fe65368 1915 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1916 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1917
7d0d0df0 1918 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 1919
15d2b585 1920 ath9k_hw_init_desc(ah);
f078f209 1921
dbccdd1d 1922 if (ath9k_hw_btcoex_is_enabled(ah))
42cc41ed
VT		 1923 ath9k_hw_btcoex_enable(ah);
1924
5955b2b0 1925 if (ath9k_hw_mci_is_enabled(ah))
528e5d36 1926 ar9003_mci_check_bt(ah);
63d32967 1927
1fe860ed
RM		 1928 ath9k_hw_loadnf(ah, chan);
1929 ath9k_hw_start_nfcal(ah, true);
1930
a7abaf7d 1931 if (AR_SREV_9300_20_OR_LATER(ah))
aea702b7 1932 ar9003_hw_bb_watchdog_config(ah);
a7abaf7d
SM		 1933
1934 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
51ac8cbb 1935 ar9003_hw_disable_phy_restart(ah);
51ac8cbb 1936
691680b8
FF		 1937 ath9k_hw_apply_gpio_override(ah);
1938
7bdea96a 1939 if (AR_SREV_9565(ah) && common->bt_ant_diversity)
362cd03f
SM		 1940 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
1941
ae8d2858 1942 return 0;
f078f209 1943}
7322fd19 1944EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1945
f1dc5600
S		 1946/******************************/
1947/* Power Management (Chipset) */
1948/******************************/
1949
42d5bc3f
LR		 1950/*
1951 * Notify Power Mgt is disabled in self-generated frames.
1952 * If requested, force chip to sleep.
1953 */
31604cf0 1954static void ath9k_set_power_sleep(struct ath_hw *ah)
f078f209 1955{
f1dc5600 1956 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2577c6e8 1957
a4a2954f 1958 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
153dccd4
RM		 1959 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
1960 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
1961 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
31604cf0
SM		 1962 /* xxx Required for WLAN only case ? */
1963 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
1964 udelay(100);
1965 }
2577c6e8 1966
31604cf0
SM		 1967 /*
1968 * Clear the RTC force wake bit to allow the
1969 * mac to go to sleep.
1970 */
1971 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1972
153dccd4 1973 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 1974 udelay(100);
2577c6e8 1975
31604cf0
SM		 1976 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1977 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 1978
31604cf0
SM		 1979 /* Shutdown chip. Active low */
1980 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
1981 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
1982 udelay(2);
f1dc5600 1983 }
9a658d2b
LR		 1984
1985 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
a7322812
RW		 1986 if (AR_SREV_9300_20_OR_LATER(ah))
1987 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 1988}
1989
bbd79af5
LR		 1990/*
1991 * Notify Power Management is enabled in self-generating
1992 * frames. If request, set power mode of chip to
1993 * auto/normal. Duration in units of 128us (1/8 TU).
1994 */
31604cf0 1995static void ath9k_set_power_network_sleep(struct ath_hw *ah)
f078f209 1996{
31604cf0 1997 struct ath9k_hw_capabilities *pCap = &ah->caps;
2577c6e8 1998
f1dc5600 1999 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2000
31604cf0
SM		 2001 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2002 /* Set WakeOnInterrupt bit; clear ForceWake bit */
2003 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2004 AR_RTC_FORCE_WAKE_ON_INT);
2005 } else {
2577c6e8 2006
31604cf0
SM		 2007 /* When chip goes into network sleep, it could be waken
2008 * up by MCI_INT interrupt caused by BT's HW messages
2009 * (LNA_xxx, CONT_xxx) which chould be in a very fast
2010 * rate (~100us). This will cause chip to leave and
2011 * re-enter network sleep mode frequently, which in
2012 * consequence will have WLAN MCI HW to generate lots of
2013 * SYS_WAKING and SYS_SLEEPING messages which will make
2014 * BT CPU to busy to process.
2015 */
153dccd4
RM		 2016 if (ath9k_hw_mci_is_enabled(ah))
2017 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2018 AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
31604cf0
SM		 2019 /*
2020 * Clear the RTC force wake bit to allow the
2021 * mac to go to sleep.
2022 */
153dccd4 2023 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
31604cf0 2024
153dccd4 2025 if (ath9k_hw_mci_is_enabled(ah))
31604cf0 2026 udelay(30);
f078f209 2027 }
9a658d2b
LR		 2028
2029 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
2030 if (AR_SREV_9300_20_OR_LATER(ah))
2031 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
f078f209
LR		 2032}
2033
31604cf0 2034static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
f078f209 2035{
f1dc5600
S		 2036 u32 val;
2037 int i;
f078f209 2038
9a658d2b
LR		 2039 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
2040 if (AR_SREV_9300_20_OR_LATER(ah)) {
2041 REG_WRITE(ah, AR_WA, ah->WARegVal);
2042 udelay(10);
2043 }
2044
31604cf0
SM		 2045 if ((REG_READ(ah, AR_RTC_STATUS) &
2046 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2047 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2048 return false;
f1dc5600 2049 }
31604cf0
SM		 2050 if (!AR_SREV_9300_20_OR_LATER(ah))
2051 ath9k_hw_init_pll(ah, NULL);
2052 }
2053 if (AR_SREV_9100(ah))
2054 REG_SET_BIT(ah, AR_RTC_RESET,
2055 AR_RTC_RESET_EN);
2056
2057 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2058 AR_RTC_FORCE_WAKE_EN);
04575f21 2059 if (AR_SREV_9100(ah))
3683a07b 2060 mdelay(10);
04575f21
SM		 2061 else
2062 udelay(50);
f078f209 2063
31604cf0
SM		 2064 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2065 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2066 if (val == AR_RTC_STATUS_ON)
2067 break;
2068 udelay(50);
f1dc5600
S		 2069 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2070 AR_RTC_FORCE_WAKE_EN);
31604cf0
SM		 2071 }
2072 if (i == 0) {
2073 ath_err(ath9k_hw_common(ah),
2074 "Failed to wakeup in %uus\n",
2075 POWER_UP_TIME / 20);
2076 return false;
f078f209
LR		 2077 }
2078
cdbe408d
RM		 2079 if (ath9k_hw_mci_is_enabled(ah))
2080 ar9003_mci_set_power_awake(ah);
2081
f1dc5600 2082 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 2083
f1dc5600 2084 return true;
f078f209
LR		 2085}
2086
9ecdef4b 2087bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 2088{
c46917bb 2089 struct ath_common *common = ath9k_hw_common(ah);
31604cf0 2090 int status = true;
f1dc5600
S		 2091 static const char *modes[] = {
2092 "AWAKE",
2093 "FULL-SLEEP",
2094 "NETWORK SLEEP",
2095 "UNDEFINED"
2096 };
f1dc5600 2097
cbdec975
GJ		 2098 if (ah->power_mode == mode)
2099 return status;
2100
d2182b69 2101 ath_dbg(common, RESET, "%s -> %s\n",
226afe68 2102 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 2103
2104 switch (mode) {
2105 case ATH9K_PM_AWAKE:
31604cf0 2106 status = ath9k_hw_set_power_awake(ah);
f1dc5600
S		 2107 break;
2108 case ATH9K_PM_FULL_SLEEP:
5955b2b0 2109 if (ath9k_hw_mci_is_enabled(ah))
d1ca8b8e 2110 ar9003_mci_set_full_sleep(ah);
1010911e 2111
31604cf0 2112 ath9k_set_power_sleep(ah);
2660b81a 2113 ah->chip_fullsleep = true;
f1dc5600
S		 2114 break;
2115 case ATH9K_PM_NETWORK_SLEEP:
31604cf0 2116 ath9k_set_power_network_sleep(ah);
f1dc5600 2117 break;
f078f209 2118 default:
3800276a 2119 ath_err(common, "Unknown power mode %u\n", mode);
f078f209
LR		 2120 return false;
2121 }
2660b81a 2122 ah->power_mode = mode;
f1dc5600 2123
69f4aab1
LR		 2124 /*
2125 * XXX: If this warning never comes up after a while then
2126 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2127 * ath9k_hw_setpower() return type void.
2128 */
97dcec57
SM		 2129
2130 if (!(ah->ah_flags & AH_UNPLUGGED))
2131 ATH_DBG_WARN_ON_ONCE(!status);
69f4aab1 2132
f1dc5600 2133 return status;
f078f209 2134}
7322fd19 2135EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 2136
f1dc5600
S		 2137/*******************/
2138/* Beacon Handling */
2139/*******************/
2140
cbe61d8a 2141void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 2142{
f078f209
LR		 2143 int flags = 0;
2144
7d0d0df0
S		 2145 ENABLE_REGWRITE_BUFFER(ah);
2146
2660b81a 2147 switch (ah->opmode) {
d97809db 2148 case NL80211_IFTYPE_ADHOC:
f078f209
LR		 2149 REG_SET_BIT(ah, AR_TXCFG,
2150 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2664d666 2151 case NL80211_IFTYPE_MESH_POINT:
d97809db 2152 case NL80211_IFTYPE_AP:
dd347f2f
FF		 2153 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2154 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2155 TU_TO_USEC(ah->config.dma_beacon_response_time));
2156 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2157 TU_TO_USEC(ah->config.sw_beacon_response_time));
f078f209
LR		 2158 flags |=
2159 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2160 break;
d97809db 2161 default:
d2182b69
JP		 2162 ath_dbg(ath9k_hw_common(ah), BEACON,
2163 "%s: unsupported opmode: %d\n", __func__, ah->opmode);
d97809db
CM		 2164 return;
2165 break;
f078f209
LR		 2166 }
2167
dd347f2f
FF		 2168 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2169 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2170 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
f078f209 2171
7d0d0df0 2172 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2173
f078f209
LR		 2174 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2175}
7322fd19 2176EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 2177
cbe61d8a 2178void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 2179 const struct ath9k_beacon_state *bs)
f078f209
LR		 2180{
2181 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 2182 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 2183 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2184
7d0d0df0
S		 2185 ENABLE_REGWRITE_BUFFER(ah);
2186
4ed15762
FF		 2187 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2188 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2189 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
f078f209 2190
7d0d0df0 2191 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2192
f078f209
LR		 2193 REG_RMW_FIELD(ah, AR_RSSI_THR,
2194 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2195
f29f5c08 2196 beaconintval = bs->bs_intval;
f078f209
LR		 2197
2198 if (bs->bs_sleepduration > beaconintval)
2199 beaconintval = bs->bs_sleepduration;
2200
2201 dtimperiod = bs->bs_dtimperiod;
2202 if (bs->bs_sleepduration > dtimperiod)
2203 dtimperiod = bs->bs_sleepduration;
2204
2205 if (beaconintval == dtimperiod)
2206 nextTbtt = bs->bs_nextdtim;
2207 else
2208 nextTbtt = bs->bs_nexttbtt;
2209
d2182b69
JP		 2210 ath_dbg(common, BEACON, "next DTIM %d\n", bs->bs_nextdtim);
2211 ath_dbg(common, BEACON, "next beacon %d\n", nextTbtt);
2212 ath_dbg(common, BEACON, "beacon period %d\n", beaconintval);
2213 ath_dbg(common, BEACON, "DTIM period %d\n", dtimperiod);
f078f209 2214
7d0d0df0
S		 2215 ENABLE_REGWRITE_BUFFER(ah);
2216
4ed15762
FF		 2217 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2218 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
f078f209 2219
f1dc5600
S		 2220 REG_WRITE(ah, AR_SLEEP1,
2221 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2222 | AR_SLEEP1_ASSUME_DTIM);
f078f209 2223
f1dc5600
S		 2224 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2225 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2226 else
2227 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 2228
f1dc5600
S		 2229 REG_WRITE(ah, AR_SLEEP2,
2230 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 2231
4ed15762
FF		 2232 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2233 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
f078f209 2234
7d0d0df0 2235 REGWRITE_BUFFER_FLUSH(ah);
7d0d0df0 2236
f1dc5600
S		 2237 REG_SET_BIT(ah, AR_TIMER_MODE,
2238 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2239 AR_DTIM_TIMER_EN);
f078f209 2240
4af9cf4f
S		 2241 /* TSF Out of Range Threshold */
2242 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 2243}
7322fd19 2244EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 2245
f1dc5600
S		 2246/*******************/
2247/* HW Capabilities */
2248/*******************/
2249
6054069a
FF		 2250static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2251{
2252 eeprom_chainmask &= chip_chainmask;
2253 if (eeprom_chainmask)
2254 return eeprom_chainmask;
2255 else
2256 return chip_chainmask;
2257}
2258
9a66af33
ZK		 2259/**
2260 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2261 * @ah: the atheros hardware data structure
2262 *
2263 * We enable DFS support upstream on chipsets which have passed a series
2264 * of tests. The testing requirements are going to be documented. Desired
2265 * test requirements are documented at:
2266 *
2267 * http://wireless.kernel.org/en/users/Drivers/ath9k/dfs
2268 *
2269 * Once a new chipset gets properly tested an individual commit can be used
2270 * to document the testing for DFS for that chipset.
2271 */
2272static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2273{
2274
2275 switch (ah->hw_version.macVersion) {
73e4937d
ZK		 2276 /* for temporary testing DFS with 9280 */
2277 case AR_SREV_VERSION_9280:
9a66af33
ZK		 2278 /* AR9580 will likely be our first target to get testing on */
2279 case AR_SREV_VERSION_9580:
73e4937d 2280 return true;
9a66af33
ZK		 2281 default:
2282 return false;
2283 }
2284}
2285
a9a29ce6 2286int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 2287{
2660b81a 2288 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 2289 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 2290 struct ath_common *common = ath9k_hw_common(ah);
6054069a 2291 unsigned int chip_chainmask;
608b88cb 2292
0ff2b5c0 2293 u16 eeval;
47c80de6 2294 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
f078f209 2295
f74df6fb 2296 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 2297 regulatory->current_rd = eeval;
f078f209 2298
2660b81a 2299 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 2300 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 2301 if (regulatory->current_rd == 0x64 ||
2302 regulatory->current_rd == 0x65)
2303 regulatory->current_rd += 5;
2304 else if (regulatory->current_rd == 0x41)
2305 regulatory->current_rd = 0x43;
d2182b69
JP		 2306 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2307 regulatory->current_rd);
f1dc5600 2308 }
f078f209 2309
f74df6fb 2310 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6 2311 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3800276a
JP		 2312 ath_err(common,
2313 "no band has been marked as supported in EEPROM\n");
a9a29ce6
GJ		 2314 return -EINVAL;
2315 }
2316
d4659912
FF		 2317 if (eeval & AR5416_OPFLAGS_11A)
2318 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
f078f209 2319
d4659912
FF		 2320 if (eeval & AR5416_OPFLAGS_11G)
2321 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
f1dc5600 2322
e41db61d
SM		 2323 if (AR_SREV_9485(ah) ||
2324 AR_SREV_9285(ah) ||
2325 AR_SREV_9330(ah) ||
2326 AR_SREV_9565(ah))
6054069a 2327 chip_chainmask = 1;
ba5736a5
MSS		 2328 else if (AR_SREV_9462(ah))
2329 chip_chainmask = 3;
6054069a
FF		 2330 else if (!AR_SREV_9280_20_OR_LATER(ah))
2331 chip_chainmask = 7;
2332 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2333 chip_chainmask = 3;
2334 else
2335 chip_chainmask = 7;
2336
f74df6fb 2337 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2338 /*
2339 * For AR9271 we will temporarilly uses the rx chainmax as read from
2340 * the EEPROM.
2341 */
8147f5de 2342 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2343 !(eeval & AR5416_OPFLAGS_11A) &&
2344 !(AR_SREV_9271(ah)))
2345 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de 2346 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
598cdd52
FF		 2347 else if (AR_SREV_9100(ah))
2348 pCap->rx_chainmask = 0x7;
8147f5de 2349 else
d7e7d229 2350 /* Use rx_chainmask from EEPROM. */
8147f5de 2351 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2352
6054069a
FF		 2353 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2354 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
82b2d334
FF		 2355 ah->txchainmask = pCap->tx_chainmask;
2356 ah->rxchainmask = pCap->rx_chainmask;
6054069a 2357
7a37081e 2358 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2359
02d2ebb2
FF		 2360 /* enable key search for every frame in an aggregate */
2361 if (AR_SREV_9300_20_OR_LATER(ah))
2362 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2363
ce2220d1
BR		 2364 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2365
0db156e9 2366 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
f1dc5600
S		 2367 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2368 else
2369 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2370
5b5fa355
S		 2371 if (AR_SREV_9271(ah))
2372 pCap->num_gpio_pins = AR9271_NUM_GPIO;
88c1f4f6
S		 2373 else if (AR_DEVID_7010(ah))
2374 pCap->num_gpio_pins = AR7010_NUM_GPIO;
6321eb09
MSS		 2375 else if (AR_SREV_9300_20_OR_LATER(ah))
2376 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2377 else if (AR_SREV_9287_11_OR_LATER(ah))
2378 pCap->num_gpio_pins = AR9287_NUM_GPIO;
e17f83ea 2379 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2380 pCap->num_gpio_pins = AR9285_NUM_GPIO;
7a37081e 2381 else if (AR_SREV_9280_20_OR_LATER(ah))
f1dc5600
S		 2382 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2383 else
2384 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2385
1b2538b2 2386 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
f1dc5600 2387 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
1b2538b2 2388 else
f1dc5600 2389 pCap->rts_aggr_limit = (8 * 1024);
f078f209 2390
74e13060 2391#ifdef CONFIG_ATH9K_RFKILL
2660b81a
S		 2392 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2393 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2394 ah->rfkill_gpio =
2395 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2396 ah->rfkill_polarity =
2397 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2398
2399 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2400 }
f1dc5600 2401#endif
d5d1154f 2402 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
bde748a4
VN		 2403 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2404 else
2405 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2406
e7594072 2407 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2408 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2409 else
2410 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2411
ceb26445 2412 if (AR_SREV_9300_20_OR_LATER(ah)) {
784ad503 2413 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
a4a2954f 2414 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && !AR_SREV_9565(ah))
784ad503
VT		 2415 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2416
ceb26445
VT		 2417 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2418 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2419 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3 2420 pCap->tx_desc_len = sizeof(struct ar9003_txc);
5088c2f1 2421 pCap->txs_len = sizeof(struct ar9003_txs);
162c3be3
VT		 2422 } else {
2423 pCap->tx_desc_len = sizeof(struct ath_desc);
a949b172 2424 if (AR_SREV_9280_20(ah))
6b42e8d0 2425 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
ceb26445 2426 }
1adf02ff 2427
6c84ce08
VT		 2428 if (AR_SREV_9300_20_OR_LATER(ah))
2429 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2430
6ee63f55
SB		 2431 if (AR_SREV_9300_20_OR_LATER(ah))
2432 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2433
a42acef0 2434 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
6473d24d
VT		 2435 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2436
f85c3371 2437 if (AR_SREV_9285(ah)) {
754dc536
VT		 2438 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2439 ant_div_ctl1 =
2440 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2441 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
754dc536 2442 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2443 ath_info(common, "Enable LNA combining\n");
2444 }
754dc536 2445 }
f85c3371
SM		 2446 }
2447
ea066d5a
MSS		 2448 if (AR_SREV_9300_20_OR_LATER(ah)) {
2449 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2450 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2451 }
2452
06236e53 2453 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
21d2c63a 2454 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
f85c3371 2455 if ((ant_div_ctl1 >> 0x6) == 0x3) {
21d2c63a 2456 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
f85c3371
SM		 2457 ath_info(common, "Enable LNA combining\n");
2458 }
21d2c63a 2459 }
754dc536 2460
9a66af33
ZK		 2461 if (ath9k_hw_dfs_tested(ah))
2462 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2463
47c80de6
VT		 2464 tx_chainmask = pCap->tx_chainmask;
2465 rx_chainmask = pCap->rx_chainmask;
2466 while (tx_chainmask || rx_chainmask) {
2467 if (tx_chainmask & BIT(0))
2468 pCap->max_txchains++;
2469 if (rx_chainmask & BIT(0))
2470 pCap->max_rxchains++;
2471
2472 tx_chainmask >>= 1;
2473 rx_chainmask >>= 1;
2474 }
2475
a4a2954f 2476 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3789d59c
MSS		 2477 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2478 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2479
2b5e54e2 2480 if (AR_SREV_9462_20_OR_LATER(ah))
3789d59c 2481 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
3789d59c
MSS		 2482 }
2483
846e438f
SM		 2484 if (AR_SREV_9462(ah))
2485 pCap->hw_caps |= ATH9K_HW_WOW_DEVICE_CAPABLE;
d687809b 2486
0f21ee8d
SM		 2487 if (AR_SREV_9300_20_OR_LATER(ah) &&
2488 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2489 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2490
a9a29ce6 2491 return 0;
f078f209
LR		 2492}
2493
f1dc5600
S		 2494/****************************/
2495/* GPIO / RFKILL / Antennae */
2496/****************************/
f078f209 2497
cbe61d8a 2498static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2499 u32 gpio, u32 type)
2500{
2501 int addr;
2502 u32 gpio_shift, tmp;
f078f209 2503
f1dc5600
S		 2504 if (gpio > 11)
2505 addr = AR_GPIO_OUTPUT_MUX3;
2506 else if (gpio > 5)
2507 addr = AR_GPIO_OUTPUT_MUX2;
2508 else
2509 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2510
f1dc5600 2511 gpio_shift = (gpio % 6) * 5;
f078f209 2512
f1dc5600
S		 2513 if (AR_SREV_9280_20_OR_LATER(ah)
2514 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2515 REG_RMW(ah, addr, (type << gpio_shift),
2516 (0x1f << gpio_shift));
f078f209 2517 } else {
f1dc5600
S		 2518 tmp = REG_READ(ah, addr);
2519 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2520 tmp &= ~(0x1f << gpio_shift);
2521 tmp |= (type << gpio_shift);
2522 REG_WRITE(ah, addr, tmp);
f078f209 2523 }
f078f209
LR		 2524}
2525
cbe61d8a 2526void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2527{
f1dc5600 2528 u32 gpio_shift;
f078f209 2529
9680e8a3 2530 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2531
88c1f4f6
S		 2532 if (AR_DEVID_7010(ah)) {
2533 gpio_shift = gpio;
2534 REG_RMW(ah, AR7010_GPIO_OE,
2535 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2536 (AR7010_GPIO_OE_MASK << gpio_shift));
2537 return;
2538 }
f078f209 2539
88c1f4f6 2540 gpio_shift = gpio << 1;
f1dc5600
S		 2541 REG_RMW(ah,
2542 AR_GPIO_OE_OUT,
2543 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2544 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2545}
7322fd19 2546EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2547
cbe61d8a 2548u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2549{
cb33c412
SB		 2550#define MS_REG_READ(x, y) \
2551 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2552
2660b81a 2553 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2554 return 0xffffffff;
f078f209 2555
88c1f4f6
S		 2556 if (AR_DEVID_7010(ah)) {
2557 u32 val;
2558 val = REG_READ(ah, AR7010_GPIO_IN);
2559 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2560 } else if (AR_SREV_9300_20_OR_LATER(ah))
9306990a
VT		 2561 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2562 AR_GPIO_BIT(gpio)) != 0;
783dfca1 2563 else if (AR_SREV_9271(ah))
5b5fa355 2564 return MS_REG_READ(AR9271, gpio) != 0;
a42acef0 2565 else if (AR_SREV_9287_11_OR_LATER(ah))
ac88b6ec 2566 return MS_REG_READ(AR9287, gpio) != 0;
e17f83ea 2567 else if (AR_SREV_9285_12_OR_LATER(ah))
cb33c412 2568 return MS_REG_READ(AR9285, gpio) != 0;
7a37081e 2569 else if (AR_SREV_9280_20_OR_LATER(ah))
cb33c412
SB		 2570 return MS_REG_READ(AR928X, gpio) != 0;
2571 else
2572 return MS_REG_READ(AR, gpio) != 0;
f078f209 2573}
7322fd19 2574EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2575
cbe61d8a 2576void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2577 u32 ah_signal_type)
f078f209 2578{
f1dc5600 2579 u32 gpio_shift;
f078f209 2580
88c1f4f6
S		 2581 if (AR_DEVID_7010(ah)) {
2582 gpio_shift = gpio;
2583 REG_RMW(ah, AR7010_GPIO_OE,
2584 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2585 (AR7010_GPIO_OE_MASK << gpio_shift));
2586 return;
2587 }
f078f209 2588
88c1f4f6 2589 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f1dc5600 2590 gpio_shift = 2 * gpio;
f1dc5600
S		 2591 REG_RMW(ah,
2592 AR_GPIO_OE_OUT,
2593 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2594 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2595}
7322fd19 2596EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2597
cbe61d8a 2598void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2599{
88c1f4f6
S		 2600 if (AR_DEVID_7010(ah)) {
2601 val = val ? 0 : 1;
2602 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2603 AR_GPIO_BIT(gpio));
2604 return;
2605 }
2606
5b5fa355
S		 2607 if (AR_SREV_9271(ah))
2608 val = ~val;
2609
f1dc5600
S		 2610 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2611 AR_GPIO_BIT(gpio));
f078f209 2612}
7322fd19 2613EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2614
cbe61d8a 2615void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2616{
f1dc5600 2617 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2618}
7322fd19 2619EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2620
f1dc5600
S		 2621/*********************/
2622/* General Operation */
2623/*********************/
2624
cbe61d8a 2625u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2626{
f1dc5600
S		 2627 u32 bits = REG_READ(ah, AR_RX_FILTER);
2628 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2629
f1dc5600
S		 2630 if (phybits & AR_PHY_ERR_RADAR)
2631 bits |= ATH9K_RX_FILTER_PHYRADAR;
2632 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2633 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2634
f1dc5600 2635 return bits;
f078f209 2636}
7322fd19 2637EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2638
cbe61d8a 2639void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2640{
f1dc5600 2641 u32 phybits;
f078f209 2642
7d0d0df0
S		 2643 ENABLE_REGWRITE_BUFFER(ah);
2644
a4a2954f 2645 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
2577c6e8
SB		 2646 bits |= ATH9K_RX_FILTER_CONTROL_WRAPPER;
2647
7ea310be
S		 2648 REG_WRITE(ah, AR_RX_FILTER, bits);
2649
f1dc5600
S		 2650 phybits = 0;
2651 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2652 phybits |= AR_PHY_ERR_RADAR;
2653 if (bits & ATH9K_RX_FILTER_PHYERR)
2654 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2655 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2656
f1dc5600 2657 if (phybits)
ca7a4deb 2658 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
f1dc5600 2659 else
ca7a4deb 2660 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
7d0d0df0
S		 2661
2662 REGWRITE_BUFFER_FLUSH(ah);
f1dc5600 2663}
7322fd19 2664EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2665
cbe61d8a 2666bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2667{
99922a45
RM		 2668 if (ath9k_hw_mci_is_enabled(ah))
2669 ar9003_mci_bt_gain_ctrl(ah);
2670
63a75b91
SB		 2671 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2672 return false;
2673
2674 ath9k_hw_init_pll(ah, NULL);
8efa7a81 2675 ah->htc_reset_init = true;
63a75b91 2676 return true;
f1dc5600 2677}
7322fd19 2678EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2679
cbe61d8a 2680bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2681{
9ecdef4b 2682 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2683 return false;
f078f209 2684
63a75b91
SB		 2685 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2686 return false;
2687
2688 ath9k_hw_init_pll(ah, NULL);
2689 return true;
f078f209 2690}
7322fd19 2691EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2692
ca2c68cc
FF		 2693static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2694{
2695 enum eeprom_param gain_param;
2696
2697 if (IS_CHAN_2GHZ(chan))
2698 gain_param = EEP_ANTENNA_GAIN_2G;
2699 else
2700 gain_param = EEP_ANTENNA_GAIN_5G;
2701
2702 return ah->eep_ops->get_eeprom(ah, gain_param);
2703}
2704
64ea57d0
GJ		 2705void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2706 bool test)
ca2c68cc
FF		 2707{
2708 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2709 struct ieee80211_channel *channel;
2710 int chan_pwr, new_pwr, max_gain;
2711 int ant_gain, ant_reduction = 0;
2712
2713 if (!chan)
2714 return;
2715
2716 channel = chan->chan;
2717 chan_pwr = min_t(int, channel->max_power * 2, MAX_RATE_POWER);
2718 new_pwr = min_t(int, chan_pwr, reg->power_limit);
2719 max_gain = chan_pwr - new_pwr + channel->max_antenna_gain * 2;
2720
2721 ant_gain = get_antenna_gain(ah, chan);
2722 if (ant_gain > max_gain)
2723 ant_reduction = ant_gain - max_gain;
2724
2725 ah->eep_ops->set_txpower(ah, chan,
2726 ath9k_regd_get_ctl(reg, chan),
64ea57d0 2727 ant_reduction, new_pwr, test);
ca2c68cc
FF		 2728}
2729
de40f316 2730void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
f078f209 2731{
ca2c68cc 2732 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2660b81a 2733 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2734 struct ieee80211_channel *channel = chan->chan;
9c204b46 2735
48ef5c42 2736 reg->power_limit = min_t(u32, limit, MAX_RATE_POWER);
9c204b46 2737 if (test)
ca2c68cc 2738 channel->max_power = MAX_RATE_POWER / 2;
f078f209 2739
64ea57d0 2740 ath9k_hw_apply_txpower(ah, chan, test);
6f255425 2741
ca2c68cc
FF		 2742 if (test)
2743 channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
6f255425 2744}
7322fd19 2745EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2746
cbe61d8a 2747void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2748{
2660b81a 2749 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2750}
7322fd19 2751EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2752
cbe61d8a 2753void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2754{
f1dc5600
S		 2755 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2756 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2757}
7322fd19 2758EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2759
f2b2143e 2760void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2761{
1510718d
LR		 2762 struct ath_common *common = ath9k_hw_common(ah);
2763
2764 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2765 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2766 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2767}
7322fd19 2768EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2769
1c0fc65e
BP		 2770#define ATH9K_MAX_TSF_READ 10
2771
cbe61d8a 2772u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2773{
1c0fc65e
BP		 2774 u32 tsf_lower, tsf_upper1, tsf_upper2;
2775 int i;
2776
2777 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2778 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2779 tsf_lower = REG_READ(ah, AR_TSF_L32);
2780 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2781 if (tsf_upper2 == tsf_upper1)
2782 break;
2783 tsf_upper1 = tsf_upper2;
2784 }
f078f209 2785
1c0fc65e 2786 WARN_ON( i == ATH9K_MAX_TSF_READ );
f078f209 2787
1c0fc65e 2788 return (((u64)tsf_upper1 << 32) | tsf_lower);
f1dc5600 2789}
7322fd19 2790EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2791
cbe61d8a 2792void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2793{
27abe060 2794 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2795 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2796}
7322fd19 2797EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2798
cbe61d8a 2799void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2800{
f9b604f6
GJ		 2801 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2802 AH_TSF_WRITE_TIMEOUT))
d2182b69 2803 ath_dbg(ath9k_hw_common(ah), RESET,
226afe68 2804 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2805
f1dc5600
S		 2806 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2807}
7322fd19 2808EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2809
60ca9f87 2810void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
f1dc5600 2811{
60ca9f87 2812 if (set)
2660b81a 2813 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2814 else
2660b81a 2815 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2816}
7322fd19 2817EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2818
e4744ec7 2819void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
f1dc5600
S		 2820{
2821 u32 macmode;
2822
e4744ec7 2823 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2824 macmode = AR_2040_JOINED_RX_CLEAR;
2825 else
2826 macmode = 0;
f078f209 2827
f1dc5600 2828 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2829}
ff155a45
VT		 2830
2831/* HW Generic timers configuration */
2832
2833static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2834{
2835 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2836 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2837 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2838 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2839 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2840 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2841 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2842 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2843 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2844 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2845 AR_NDP2_TIMER_MODE, 0x0002},
2846 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2847 AR_NDP2_TIMER_MODE, 0x0004},
2848 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2849 AR_NDP2_TIMER_MODE, 0x0008},
2850 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2851 AR_NDP2_TIMER_MODE, 0x0010},
2852 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2853 AR_NDP2_TIMER_MODE, 0x0020},
2854 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2855 AR_NDP2_TIMER_MODE, 0x0040},
2856 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2857 AR_NDP2_TIMER_MODE, 0x0080}
2858};
2859
2860/* HW generic timer primitives */
2861
dd347f2f 2862u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2863{
2864 return REG_READ(ah, AR_TSF_L32);
2865}
dd347f2f 2866EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2867
2868struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2869 void (*trigger)(void *),
2870 void (*overflow)(void *),
2871 void *arg,
2872 u8 timer_index)
2873{
2874 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2875 struct ath_gen_timer *timer;
2876
c67ce339
FF		 2877 if ((timer_index < AR_FIRST_NDP_TIMER) ||
2878 (timer_index >= ATH_MAX_GEN_TIMER))
2879 return NULL;
2880
ff155a45 2881 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
14f8dc49 2882 if (timer == NULL)
ff155a45 2883 return NULL;
ff155a45
VT		 2884
2885 /* allocate a hardware generic timer slot */
2886 timer_table->timers[timer_index] = timer;
2887 timer->index = timer_index;
2888 timer->trigger = trigger;
2889 timer->overflow = overflow;
2890 timer->arg = arg;
2891
2892 return timer;
2893}
7322fd19 2894EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2895
cd9bf689
LR		 2896void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2897 struct ath_gen_timer *timer,
c67ce339 2898 u32 timer_next,
cd9bf689 2899 u32 timer_period)
ff155a45
VT		 2900{
2901 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
c67ce339 2902 u32 mask = 0;
788f6875 2903
c67ce339 2904 timer_table->timer_mask |= BIT(timer->index);
ff155a45 2905
ff155a45
VT		 2906 /*
2907 * Program generic timer registers
2908 */
2909 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2910 timer_next);
2911 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2912 timer_period);
2913 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2914 gen_tmr_configuration[timer->index].mode_mask);
2915
a4a2954f 2916 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2577c6e8 2917 /*
423e38e8 2918 * Starting from AR9462, each generic timer can select which tsf
2577c6e8
SB		 2919 * to use. But we still follow the old rule, 0 - 7 use tsf and
2920 * 8 - 15 use tsf2.
2921 */
2922 if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
2923 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2924 (1 << timer->index));
2925 else
2926 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2927 (1 << timer->index));
2928 }
2929
c67ce339
FF		 2930 if (timer->trigger)
2931 mask |= SM(AR_GENTMR_BIT(timer->index),
2932 AR_IMR_S5_GENTIMER_TRIG);
2933 if (timer->overflow)
2934 mask |= SM(AR_GENTMR_BIT(timer->index),
2935 AR_IMR_S5_GENTIMER_THRESH);
2936
2937 REG_SET_BIT(ah, AR_IMR_S5, mask);
2938
2939 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
2940 ah->imask |= ATH9K_INT_GENTIMER;
2941 ath9k_hw_set_interrupts(ah);
2942 }
ff155a45 2943}
7322fd19 2944EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 2945
cd9bf689 2946void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 2947{
2948 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2949
ff155a45
VT		 2950 /* Clear generic timer enable bits. */
2951 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2952 gen_tmr_configuration[timer->index].mode_mask);
2953
b7f59766
SM		 2954 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2955 /*
2956 * Need to switch back to TSF if it was using TSF2.
2957 */
2958 if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
2959 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
2960 (1 << timer->index));
2961 }
2962 }
2963
ff155a45
VT		 2964 /* Disable both trigger and thresh interrupt masks */
2965 REG_CLR_BIT(ah, AR_IMR_S5,
2966 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2967 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2968
c67ce339
FF		 2969 timer_table->timer_mask &= ~BIT(timer->index);
2970
2971 if (timer_table->timer_mask == 0) {
2972 ah->imask &= ~ATH9K_INT_GENTIMER;
2973 ath9k_hw_set_interrupts(ah);
2974 }
ff155a45 2975}
7322fd19 2976EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 2977
2978void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2979{
2980 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2981
2982 /* free the hardware generic timer slot */
2983 timer_table->timers[timer->index] = NULL;
2984 kfree(timer);
2985}
7322fd19 2986EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 2987
2988/*
2989 * Generic Timer Interrupts handling
2990 */
2991void ath_gen_timer_isr(struct ath_hw *ah)
2992{
2993 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2994 struct ath_gen_timer *timer;
c67ce339
FF		 2995 unsigned long trigger_mask, thresh_mask;
2996 unsigned int index;
ff155a45
VT		 2997
2998 /* get hardware generic timer interrupt status */
2999 trigger_mask = ah->intr_gen_timer_trigger;
3000 thresh_mask = ah->intr_gen_timer_thresh;
c67ce339
FF		 3001 trigger_mask &= timer_table->timer_mask;
3002 thresh_mask &= timer_table->timer_mask;
ff155a45 3003
c67ce339 3004 for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3005 timer = timer_table->timers[index];
c67ce339
FF		 3006 if (!timer)
3007 continue;
3008 if (!timer->overflow)
3009 continue;
a6a172b2
FF		 3010
3011 trigger_mask &= ~BIT(index);
ff155a45
VT		 3012 timer->overflow(timer->arg);
3013 }
3014
c67ce339 3015 for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
ff155a45 3016 timer = timer_table->timers[index];
c67ce339
FF		 3017 if (!timer)
3018 continue;
3019 if (!timer->trigger)
3020 continue;
ff155a45
VT		 3021 timer->trigger(timer->arg);
3022 }
3023}
7322fd19 3024EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 3025
05020d23
S		 3026/********/
3027/* HTC */
3028/********/
3029
2da4f01a
LR		 3030static struct {
3031 u32 version;
3032 const char * name;
3033} ath_mac_bb_names[] = {
3034 /* Devices with external radios */
3035 { AR_SREV_VERSION_5416_PCI, "5416" },
3036 { AR_SREV_VERSION_5416_PCIE, "5418" },
3037 { AR_SREV_VERSION_9100, "9100" },
3038 { AR_SREV_VERSION_9160, "9160" },
3039 /* Single-chip solutions */
3040 { AR_SREV_VERSION_9280, "9280" },
3041 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 3042 { AR_SREV_VERSION_9287, "9287" },
3043 { AR_SREV_VERSION_9271, "9271" },
ec83903e 3044 { AR_SREV_VERSION_9300, "9300" },
2c8e5937 3045 { AR_SREV_VERSION_9330, "9330" },
397e5d5b 3046 { AR_SREV_VERSION_9340, "9340" },
8f06ca2c 3047 { AR_SREV_VERSION_9485, "9485" },
423e38e8 3048 { AR_SREV_VERSION_9462, "9462" },
485124cb 3049 { AR_SREV_VERSION_9550, "9550" },
77fac465 3050 { AR_SREV_VERSION_9565, "9565" },
c08148bb 3051 { AR_SREV_VERSION_9531, "9531" },
2da4f01a
LR		 3052};
3053
3054/* For devices with external radios */
3055static struct {
3056 u16 version;
3057 const char * name;
3058} ath_rf_names[] = {
3059 { 0, "5133" },
3060 { AR_RAD5133_SREV_MAJOR, "5133" },
3061 { AR_RAD5122_SREV_MAJOR, "5122" },
3062 { AR_RAD2133_SREV_MAJOR, "2133" },
3063 { AR_RAD2122_SREV_MAJOR, "2122" }
3064};
3065
3066/*
3067 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3068 */
f934c4d9 3069static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 3070{
3071 int i;
3072
3073 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3074 if (ath_mac_bb_names[i].version == mac_bb_version) {
3075 return ath_mac_bb_names[i].name;
3076 }
3077 }
3078
3079 return "????";
3080}
2da4f01a
LR		 3081
3082/*
3083 * Return the RF name. "????" is returned if the RF is unknown.
3084 * Used for devices with external radios.
3085 */
f934c4d9 3086static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 3087{
3088 int i;
3089
3090 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3091 if (ath_rf_names[i].version == rf_version) {
3092 return ath_rf_names[i].name;
3093 }
3094 }
3095
3096 return "????";
3097}
f934c4d9
LR		 3098
3099void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3100{
3101 int used;
3102
3103 /* chipsets >= AR9280 are single-chip */
7a37081e 3104 if (AR_SREV_9280_20_OR_LATER(ah)) {
5e88ba62
ZK		 3105 used = scnprintf(hw_name, len,
3106 "Atheros AR%s Rev:%x",
3107 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3108 ah->hw_version.macRev);
f934c4d9
LR		 3109 }
3110 else {
5e88ba62
ZK		 3111 used = scnprintf(hw_name, len,
3112 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3113 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3114 ah->hw_version.macRev,
3115 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3116 & AR_RADIO_SREV_MAJOR)),
3117 ah->hw_version.phyRev);
f934c4d9
LR		 3118 }
3119
3120 hw_name[used] = '\0';
3121}
3122EXPORT_SYMBOL(ath9k_hw_name);
Linux kernel - Deliverables
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