Commit | Line | Data |
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f078f209 | 1 | /* |
b3950e6a | 2 | * Copyright (c) 2008-2010 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef HW_H | |
18 | #define HW_H | |
19 | ||
20 | #include <linux/if_ether.h> | |
21 | #include <linux/delay.h> | |
394cf0a1 S |
22 | #include <linux/io.h> |
23 | ||
24 | #include "mac.h" | |
25 | #include "ani.h" | |
26 | #include "eeprom.h" | |
27 | #include "calib.h" | |
394cf0a1 S |
28 | #include "reg.h" |
29 | #include "phy.h" | |
af03abec | 30 | #include "btcoex.h" |
ceb26445 | 31 | #include "ar9003_mac.h" |
394cf0a1 | 32 | |
203c4805 | 33 | #include "../regd.h" |
c46917bb | 34 | #include "../debug.h" |
3a702e49 | 35 | |
394cf0a1 | 36 | #define ATHEROS_VENDOR_ID 0x168c |
7976b426 | 37 | |
394cf0a1 S |
38 | #define AR5416_DEVID_PCI 0x0023 |
39 | #define AR5416_DEVID_PCIE 0x0024 | |
40 | #define AR9160_DEVID_PCI 0x0027 | |
41 | #define AR9280_DEVID_PCI 0x0029 | |
42 | #define AR9280_DEVID_PCIE 0x002a | |
43 | #define AR9285_DEVID_PCIE 0x002b | |
5ffaf8a3 | 44 | #define AR2427_DEVID_PCIE 0x002c |
db3cc53a SB |
45 | #define AR9287_DEVID_PCI 0x002d |
46 | #define AR9287_DEVID_PCIE 0x002e | |
47 | #define AR9300_DEVID_PCIE 0x0030 | |
7976b426 | 48 | |
394cf0a1 | 49 | #define AR5416_AR9100_DEVID 0x000b |
7976b426 | 50 | |
394cf0a1 S |
51 | #define AR_SUBVENDOR_ID_NOG 0x0e11 |
52 | #define AR_SUBVENDOR_ID_NEW_A 0x7065 | |
53 | #define AR5416_MAGIC 0x19641014 | |
54 | ||
fe12946e VT |
55 | #define AR9280_COEX2WIRE_SUBSYSID 0x309b |
56 | #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa | |
57 | #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab | |
58 | ||
e3d01bfc LR |
59 | #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1) |
60 | ||
cfe8cba9 LR |
61 | #define ATH_DEFAULT_NOISE_FLOOR -95 |
62 | ||
04658fba | 63 | #define ATH9K_RSSI_BAD -128 |
990b70ab | 64 | |
394cf0a1 | 65 | /* Register read/write primitives */ |
9e4bffd2 LR |
66 | #define REG_WRITE(_ah, _reg, _val) \ |
67 | ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg)) | |
68 | ||
69 | #define REG_READ(_ah, _reg) \ | |
70 | ath9k_hw_common(_ah)->ops->read((_ah), (_reg)) | |
394cf0a1 S |
71 | |
72 | #define SM(_v, _f) (((_v) << _f##_S) & _f) | |
73 | #define MS(_v, _f) (((_v) & _f) >> _f##_S) | |
74 | #define REG_RMW(_a, _r, _set, _clr) \ | |
75 | REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set)) | |
76 | #define REG_RMW_FIELD(_a, _r, _f, _v) \ | |
77 | REG_WRITE(_a, _r, \ | |
78 | (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f)) | |
79 | #define REG_SET_BIT(_a, _r, _f) \ | |
80 | REG_WRITE(_a, _r, REG_READ(_a, _r) | _f) | |
81 | #define REG_CLR_BIT(_a, _r, _f) \ | |
82 | REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f) | |
f078f209 | 83 | |
394cf0a1 S |
84 | #define DO_DELAY(x) do { \ |
85 | if ((++(x) % 64) == 0) \ | |
86 | udelay(1); \ | |
87 | } while (0) | |
f078f209 | 88 | |
394cf0a1 S |
89 | #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ |
90 | int r; \ | |
91 | for (r = 0; r < ((iniarray)->ia_rows); r++) { \ | |
92 | REG_WRITE(ah, INI_RA((iniarray), (r), 0), \ | |
93 | INI_RA((iniarray), r, (column))); \ | |
94 | DO_DELAY(regWr); \ | |
95 | } \ | |
96 | } while (0) | |
f078f209 | 97 | |
394cf0a1 S |
98 | #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0 |
99 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1 | |
100 | #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2 | |
101 | #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3 | |
1773912b | 102 | #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4 |
394cf0a1 S |
103 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5 |
104 | #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6 | |
f078f209 | 105 | |
394cf0a1 S |
106 | #define AR_GPIOD_MASK 0x00001FFF |
107 | #define AR_GPIO_BIT(_gpio) (1 << (_gpio)) | |
f078f209 | 108 | |
394cf0a1 | 109 | #define BASE_ACTIVATE_DELAY 100 |
63a75b91 | 110 | #define RTC_PLL_SETTLE_DELAY 100 |
394cf0a1 S |
111 | #define COEF_SCALE_S 24 |
112 | #define HT40_CHANNEL_CENTER_SHIFT 10 | |
f078f209 | 113 | |
394cf0a1 S |
114 | #define ATH9K_ANTENNA0_CHAINMASK 0x1 |
115 | #define ATH9K_ANTENNA1_CHAINMASK 0x2 | |
116 | ||
117 | #define ATH9K_NUM_DMA_DEBUG_REGS 8 | |
118 | #define ATH9K_NUM_QUEUES 10 | |
119 | ||
120 | #define MAX_RATE_POWER 63 | |
0caa7b14 | 121 | #define AH_WAIT_TIMEOUT 100000 /* (us) */ |
f9b604f6 | 122 | #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */ |
394cf0a1 S |
123 | #define AH_TIME_QUANTUM 10 |
124 | #define AR_KEYTABLE_SIZE 128 | |
d8caa839 | 125 | #define POWER_UP_TIME 10000 |
394cf0a1 S |
126 | #define SPUR_RSSI_THRESH 40 |
127 | ||
128 | #define CAB_TIMEOUT_VAL 10 | |
129 | #define BEACON_TIMEOUT_VAL 10 | |
130 | #define MIN_BEACON_TIMEOUT_VAL 1 | |
131 | #define SLEEP_SLOP 3 | |
132 | ||
133 | #define INIT_CONFIG_STATUS 0x00000000 | |
134 | #define INIT_RSSI_THR 0x00000700 | |
135 | #define INIT_BCON_CNTRL_REG 0x00000000 | |
136 | ||
137 | #define TU_TO_USEC(_tu) ((_tu) << 10) | |
138 | ||
ceb26445 VT |
139 | #define ATH9K_HW_RX_HP_QDEPTH 16 |
140 | #define ATH9K_HW_RX_LP_QDEPTH 128 | |
141 | ||
13ce3e99 LR |
142 | enum ath_ini_subsys { |
143 | ATH_INI_PRE = 0, | |
144 | ATH_INI_CORE, | |
145 | ATH_INI_POST, | |
146 | ATH_INI_NUM_SPLIT, | |
147 | }; | |
148 | ||
394cf0a1 S |
149 | enum wireless_mode { |
150 | ATH9K_MODE_11A = 0, | |
b9b6e15a LR |
151 | ATH9K_MODE_11G, |
152 | ATH9K_MODE_11NA_HT20, | |
153 | ATH9K_MODE_11NG_HT20, | |
154 | ATH9K_MODE_11NA_HT40PLUS, | |
155 | ATH9K_MODE_11NA_HT40MINUS, | |
156 | ATH9K_MODE_11NG_HT40PLUS, | |
157 | ATH9K_MODE_11NG_HT40MINUS, | |
158 | ATH9K_MODE_MAX, | |
394cf0a1 | 159 | }; |
f078f209 | 160 | |
394cf0a1 | 161 | enum ath9k_hw_caps { |
bdbdf46d S |
162 | ATH9K_HW_CAP_MIC_AESCCM = BIT(0), |
163 | ATH9K_HW_CAP_MIC_CKIP = BIT(1), | |
164 | ATH9K_HW_CAP_MIC_TKIP = BIT(2), | |
165 | ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3), | |
166 | ATH9K_HW_CAP_CIPHER_CKIP = BIT(4), | |
167 | ATH9K_HW_CAP_CIPHER_TKIP = BIT(5), | |
168 | ATH9K_HW_CAP_VEOL = BIT(6), | |
169 | ATH9K_HW_CAP_BSSIDMASK = BIT(7), | |
170 | ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8), | |
171 | ATH9K_HW_CAP_HT = BIT(9), | |
172 | ATH9K_HW_CAP_GTT = BIT(10), | |
173 | ATH9K_HW_CAP_FASTCC = BIT(11), | |
174 | ATH9K_HW_CAP_RFSILENT = BIT(12), | |
175 | ATH9K_HW_CAP_CST = BIT(13), | |
176 | ATH9K_HW_CAP_ENHANCEDPM = BIT(14), | |
177 | ATH9K_HW_CAP_AUTOSLEEP = BIT(15), | |
178 | ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16), | |
1adf02ff | 179 | ATH9K_HW_CAP_EDMA = BIT(17), |
394cf0a1 | 180 | }; |
f078f209 | 181 | |
394cf0a1 S |
182 | enum ath9k_capability_type { |
183 | ATH9K_CAP_CIPHER = 0, | |
184 | ATH9K_CAP_TKIP_MIC, | |
185 | ATH9K_CAP_TKIP_SPLIT, | |
394cf0a1 | 186 | ATH9K_CAP_TXPOW, |
394cf0a1 | 187 | ATH9K_CAP_MCAST_KEYSRCH, |
8bd1d07f | 188 | ATH9K_CAP_DS |
394cf0a1 | 189 | }; |
f078f209 | 190 | |
394cf0a1 S |
191 | struct ath9k_hw_capabilities { |
192 | u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */ | |
193 | DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */ | |
194 | u16 total_queues; | |
195 | u16 keycache_size; | |
196 | u16 low_5ghz_chan, high_5ghz_chan; | |
197 | u16 low_2ghz_chan, high_2ghz_chan; | |
394cf0a1 S |
198 | u16 rts_aggr_limit; |
199 | u8 tx_chainmask; | |
200 | u8 rx_chainmask; | |
201 | u16 tx_triglevel_max; | |
202 | u16 reg_cap; | |
203 | u8 num_gpio_pins; | |
204 | u8 num_antcfg_2ghz; | |
205 | u8 num_antcfg_5ghz; | |
ceb26445 VT |
206 | u8 rx_hp_qdepth; |
207 | u8 rx_lp_qdepth; | |
208 | u8 rx_status_len; | |
162c3be3 | 209 | u8 tx_desc_len; |
394cf0a1 | 210 | }; |
f078f209 | 211 | |
394cf0a1 S |
212 | struct ath9k_ops_config { |
213 | int dma_beacon_response_time; | |
214 | int sw_beacon_response_time; | |
215 | int additional_swba_backoff; | |
216 | int ack_6mb; | |
217 | int cwm_ignore_extcca; | |
218 | u8 pcie_powersave_enable; | |
394cf0a1 S |
219 | u8 pcie_clock_req; |
220 | u32 pcie_waen; | |
394cf0a1 S |
221 | u8 analog_shiftreg; |
222 | u8 ht_enable; | |
223 | u32 ofdm_trig_low; | |
224 | u32 ofdm_trig_high; | |
225 | u32 cck_trig_high; | |
226 | u32 cck_trig_low; | |
227 | u32 enable_ani; | |
394cf0a1 | 228 | int serialize_regmode; |
0ce024cb | 229 | bool rx_intr_mitigation; |
55e82df4 | 230 | bool tx_intr_mitigation; |
394cf0a1 S |
231 | #define SPUR_DISABLE 0 |
232 | #define SPUR_ENABLE_IOCTL 1 | |
233 | #define SPUR_ENABLE_EEPROM 2 | |
234 | #define AR_EEPROM_MODAL_SPURS 5 | |
235 | #define AR_SPUR_5413_1 1640 | |
236 | #define AR_SPUR_5413_2 1200 | |
237 | #define AR_NO_SPUR 0x8000 | |
238 | #define AR_BASE_FREQ_2GHZ 2300 | |
239 | #define AR_BASE_FREQ_5GHZ 4900 | |
240 | #define AR_SPUR_FEEQ_BOUND_HT40 19 | |
241 | #define AR_SPUR_FEEQ_BOUND_HT20 10 | |
242 | int spurmode; | |
243 | u16 spurchans[AR_EEPROM_MODAL_SPURS][2]; | |
f4709fdf | 244 | u8 max_txtrig_level; |
394cf0a1 | 245 | }; |
f078f209 | 246 | |
394cf0a1 S |
247 | enum ath9k_int { |
248 | ATH9K_INT_RX = 0x00000001, | |
249 | ATH9K_INT_RXDESC = 0x00000002, | |
b5c80475 FF |
250 | ATH9K_INT_RXHP = 0x00000001, |
251 | ATH9K_INT_RXLP = 0x00000002, | |
394cf0a1 S |
252 | ATH9K_INT_RXNOFRM = 0x00000008, |
253 | ATH9K_INT_RXEOL = 0x00000010, | |
254 | ATH9K_INT_RXORN = 0x00000020, | |
255 | ATH9K_INT_TX = 0x00000040, | |
256 | ATH9K_INT_TXDESC = 0x00000080, | |
257 | ATH9K_INT_TIM_TIMER = 0x00000100, | |
258 | ATH9K_INT_TXURN = 0x00000800, | |
259 | ATH9K_INT_MIB = 0x00001000, | |
260 | ATH9K_INT_RXPHY = 0x00004000, | |
261 | ATH9K_INT_RXKCM = 0x00008000, | |
262 | ATH9K_INT_SWBA = 0x00010000, | |
263 | ATH9K_INT_BMISS = 0x00040000, | |
264 | ATH9K_INT_BNR = 0x00100000, | |
265 | ATH9K_INT_TIM = 0x00200000, | |
266 | ATH9K_INT_DTIM = 0x00400000, | |
267 | ATH9K_INT_DTIMSYNC = 0x00800000, | |
268 | ATH9K_INT_GPIO = 0x01000000, | |
269 | ATH9K_INT_CABEND = 0x02000000, | |
4af9cf4f | 270 | ATH9K_INT_TSFOOR = 0x04000000, |
ff155a45 | 271 | ATH9K_INT_GENTIMER = 0x08000000, |
394cf0a1 S |
272 | ATH9K_INT_CST = 0x10000000, |
273 | ATH9K_INT_GTT = 0x20000000, | |
274 | ATH9K_INT_FATAL = 0x40000000, | |
275 | ATH9K_INT_GLOBAL = 0x80000000, | |
276 | ATH9K_INT_BMISC = ATH9K_INT_TIM | | |
277 | ATH9K_INT_DTIM | | |
278 | ATH9K_INT_DTIMSYNC | | |
4af9cf4f | 279 | ATH9K_INT_TSFOOR | |
394cf0a1 S |
280 | ATH9K_INT_CABEND, |
281 | ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM | | |
282 | ATH9K_INT_RXDESC | | |
283 | ATH9K_INT_RXEOL | | |
284 | ATH9K_INT_RXORN | | |
285 | ATH9K_INT_TXURN | | |
286 | ATH9K_INT_TXDESC | | |
287 | ATH9K_INT_MIB | | |
288 | ATH9K_INT_RXPHY | | |
289 | ATH9K_INT_RXKCM | | |
290 | ATH9K_INT_SWBA | | |
291 | ATH9K_INT_BMISS | | |
292 | ATH9K_INT_GPIO, | |
293 | ATH9K_INT_NOCARD = 0xffffffff | |
294 | }; | |
f078f209 | 295 | |
394cf0a1 S |
296 | #define CHANNEL_CW_INT 0x00002 |
297 | #define CHANNEL_CCK 0x00020 | |
298 | #define CHANNEL_OFDM 0x00040 | |
299 | #define CHANNEL_2GHZ 0x00080 | |
300 | #define CHANNEL_5GHZ 0x00100 | |
301 | #define CHANNEL_PASSIVE 0x00200 | |
302 | #define CHANNEL_DYN 0x00400 | |
303 | #define CHANNEL_HALF 0x04000 | |
304 | #define CHANNEL_QUARTER 0x08000 | |
305 | #define CHANNEL_HT20 0x10000 | |
306 | #define CHANNEL_HT40PLUS 0x20000 | |
307 | #define CHANNEL_HT40MINUS 0x40000 | |
308 | ||
394cf0a1 S |
309 | #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) |
310 | #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) | |
311 | #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) | |
312 | #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20) | |
313 | #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20) | |
314 | #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS) | |
315 | #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS) | |
316 | #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS) | |
317 | #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS) | |
318 | #define CHANNEL_ALL \ | |
319 | (CHANNEL_OFDM| \ | |
320 | CHANNEL_CCK| \ | |
321 | CHANNEL_2GHZ | \ | |
322 | CHANNEL_5GHZ | \ | |
323 | CHANNEL_HT20 | \ | |
324 | CHANNEL_HT40PLUS | \ | |
325 | CHANNEL_HT40MINUS) | |
326 | ||
327 | struct ath9k_channel { | |
328 | struct ieee80211_channel *chan; | |
329 | u16 channel; | |
330 | u32 channelFlags; | |
331 | u32 chanmode; | |
332 | int32_t CalValid; | |
333 | bool oneTimeCalsDone; | |
334 | int8_t iCoff; | |
335 | int8_t qCoff; | |
336 | int16_t rawNoiseFloor; | |
337 | }; | |
f078f209 | 338 | |
394cf0a1 S |
339 | #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \ |
340 | (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \ | |
341 | (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \ | |
342 | (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS)) | |
343 | #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0) | |
344 | #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0) | |
345 | #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0) | |
394cf0a1 S |
346 | #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0) |
347 | #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0) | |
348 | #define IS_CHAN_A_5MHZ_SPACED(_c) \ | |
349 | ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \ | |
350 | (((_c)->channel % 20) != 0) && \ | |
351 | (((_c)->channel % 10) != 0)) | |
352 | ||
353 | /* These macros check chanmode and not channelFlags */ | |
354 | #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B) | |
355 | #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \ | |
356 | ((_c)->chanmode == CHANNEL_G_HT20)) | |
357 | #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \ | |
358 | ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \ | |
359 | ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \ | |
360 | ((_c)->chanmode == CHANNEL_G_HT40MINUS)) | |
361 | #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c))) | |
362 | ||
363 | enum ath9k_power_mode { | |
364 | ATH9K_PM_AWAKE = 0, | |
365 | ATH9K_PM_FULL_SLEEP, | |
366 | ATH9K_PM_NETWORK_SLEEP, | |
367 | ATH9K_PM_UNDEFINED | |
368 | }; | |
f078f209 | 369 | |
394cf0a1 S |
370 | enum ath9k_tp_scale { |
371 | ATH9K_TP_SCALE_MAX = 0, | |
372 | ATH9K_TP_SCALE_50, | |
373 | ATH9K_TP_SCALE_25, | |
374 | ATH9K_TP_SCALE_12, | |
375 | ATH9K_TP_SCALE_MIN | |
376 | }; | |
f078f209 | 377 | |
394cf0a1 S |
378 | enum ser_reg_mode { |
379 | SER_REG_MODE_OFF = 0, | |
380 | SER_REG_MODE_ON = 1, | |
381 | SER_REG_MODE_AUTO = 2, | |
382 | }; | |
f078f209 | 383 | |
ad7b8060 VT |
384 | enum ath9k_rx_qtype { |
385 | ATH9K_RX_QUEUE_HP, | |
386 | ATH9K_RX_QUEUE_LP, | |
387 | ATH9K_RX_QUEUE_MAX, | |
388 | }; | |
389 | ||
394cf0a1 S |
390 | struct ath9k_beacon_state { |
391 | u32 bs_nexttbtt; | |
392 | u32 bs_nextdtim; | |
393 | u32 bs_intval; | |
394 | #define ATH9K_BEACON_PERIOD 0x0000ffff | |
395 | #define ATH9K_BEACON_ENA 0x00800000 | |
396 | #define ATH9K_BEACON_RESET_TSF 0x01000000 | |
4af9cf4f | 397 | #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */ |
394cf0a1 S |
398 | u32 bs_dtimperiod; |
399 | u16 bs_cfpperiod; | |
400 | u16 bs_cfpmaxduration; | |
401 | u32 bs_cfpnext; | |
402 | u16 bs_timoffset; | |
403 | u16 bs_bmissthreshold; | |
404 | u32 bs_sleepduration; | |
4af9cf4f | 405 | u32 bs_tsfoor_threshold; |
394cf0a1 | 406 | }; |
f078f209 | 407 | |
394cf0a1 S |
408 | struct chan_centers { |
409 | u16 synth_center; | |
410 | u16 ctl_center; | |
411 | u16 ext_center; | |
412 | }; | |
f078f209 | 413 | |
394cf0a1 S |
414 | enum { |
415 | ATH9K_RESET_POWER_ON, | |
416 | ATH9K_RESET_WARM, | |
417 | ATH9K_RESET_COLD, | |
418 | }; | |
f078f209 | 419 | |
d535a42a S |
420 | struct ath9k_hw_version { |
421 | u32 magic; | |
422 | u16 devid; | |
423 | u16 subvendorid; | |
424 | u32 macVersion; | |
425 | u16 macRev; | |
426 | u16 phyRev; | |
427 | u16 analog5GhzRev; | |
428 | u16 analog2GhzRev; | |
aeac355d | 429 | u16 subsysid; |
d535a42a | 430 | }; |
394cf0a1 | 431 | |
ff155a45 VT |
432 | /* Generic TSF timer definitions */ |
433 | ||
434 | #define ATH_MAX_GEN_TIMER 16 | |
435 | ||
436 | #define AR_GENTMR_BIT(_index) (1 << (_index)) | |
437 | ||
438 | /* | |
439 | * Using de Bruijin sequence to to look up 1's index in a 32 bit number | |
440 | * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001 | |
441 | */ | |
c90017dd | 442 | #define debruijn32 0x077CB531U |
ff155a45 VT |
443 | |
444 | struct ath_gen_timer_configuration { | |
445 | u32 next_addr; | |
446 | u32 period_addr; | |
447 | u32 mode_addr; | |
448 | u32 mode_mask; | |
449 | }; | |
450 | ||
451 | struct ath_gen_timer { | |
452 | void (*trigger)(void *arg); | |
453 | void (*overflow)(void *arg); | |
454 | void *arg; | |
455 | u8 index; | |
456 | }; | |
457 | ||
458 | struct ath_gen_timer_table { | |
459 | u32 gen_timer_index[32]; | |
460 | struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER]; | |
461 | union { | |
462 | unsigned long timer_bits; | |
463 | u16 val; | |
464 | } timer_mask; | |
465 | }; | |
466 | ||
d70357d5 LR |
467 | /** |
468 | * struct ath_hw_private_ops - callbacks used internally by hardware code | |
469 | * | |
470 | * This structure contains private callbacks designed to only be used internally | |
471 | * by the hardware core. | |
472 | * | |
795f5e2c LR |
473 | * @init_cal_settings: setup types of calibrations supported |
474 | * @init_cal: starts actual calibration | |
475 | * | |
d70357d5 | 476 | * @init_mode_regs: Initializes mode registers |
991312d8 | 477 | * @init_mode_gain_regs: Initialize TX/RX gain registers |
d70357d5 | 478 | * @macversion_supported: If this specific mac revision is supported |
8fe65368 LR |
479 | * |
480 | * @rf_set_freq: change frequency | |
481 | * @spur_mitigate_freq: spur mitigation | |
482 | * @rf_alloc_ext_banks: | |
483 | * @rf_free_ext_banks: | |
484 | * @set_rf_regs: | |
64773964 LR |
485 | * @compute_pll_control: compute the PLL control value to use for |
486 | * AR_RTC_PLL_CONTROL for a given channel | |
795f5e2c LR |
487 | * @setup_calibration: set up calibration |
488 | * @iscal_supported: used to query if a type of calibration is supported | |
d70357d5 LR |
489 | */ |
490 | struct ath_hw_private_ops { | |
795f5e2c | 491 | /* Calibration ops */ |
d70357d5 | 492 | void (*init_cal_settings)(struct ath_hw *ah); |
795f5e2c LR |
493 | bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan); |
494 | ||
d70357d5 | 495 | void (*init_mode_regs)(struct ath_hw *ah); |
991312d8 | 496 | void (*init_mode_gain_regs)(struct ath_hw *ah); |
d70357d5 | 497 | bool (*macversion_supported)(u32 macversion); |
795f5e2c LR |
498 | void (*setup_calibration)(struct ath_hw *ah, |
499 | struct ath9k_cal_list *currCal); | |
500 | bool (*iscal_supported)(struct ath_hw *ah, | |
501 | enum ath9k_cal_types calType); | |
8fe65368 LR |
502 | |
503 | /* PHY ops */ | |
504 | int (*rf_set_freq)(struct ath_hw *ah, | |
505 | struct ath9k_channel *chan); | |
506 | void (*spur_mitigate_freq)(struct ath_hw *ah, | |
507 | struct ath9k_channel *chan); | |
508 | int (*rf_alloc_ext_banks)(struct ath_hw *ah); | |
509 | void (*rf_free_ext_banks)(struct ath_hw *ah); | |
510 | bool (*set_rf_regs)(struct ath_hw *ah, | |
511 | struct ath9k_channel *chan, | |
512 | u16 modesIndex); | |
513 | void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan); | |
514 | void (*init_bb)(struct ath_hw *ah, | |
515 | struct ath9k_channel *chan); | |
516 | int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan); | |
517 | void (*olc_init)(struct ath_hw *ah); | |
518 | void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan); | |
519 | void (*mark_phy_inactive)(struct ath_hw *ah); | |
520 | void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan); | |
521 | bool (*rfbus_req)(struct ath_hw *ah); | |
522 | void (*rfbus_done)(struct ath_hw *ah); | |
523 | void (*enable_rfkill)(struct ath_hw *ah); | |
524 | void (*restore_chainmask)(struct ath_hw *ah); | |
525 | void (*set_diversity)(struct ath_hw *ah, bool value); | |
64773964 LR |
526 | u32 (*compute_pll_control)(struct ath_hw *ah, |
527 | struct ath9k_channel *chan); | |
c16fcb49 FF |
528 | bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd, |
529 | int param); | |
641d9921 | 530 | void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]); |
d70357d5 LR |
531 | }; |
532 | ||
533 | /** | |
534 | * struct ath_hw_ops - callbacks used by hardware code and driver code | |
535 | * | |
536 | * This structure contains callbacks designed to to be used internally by | |
537 | * hardware code and also by the lower level driver. | |
538 | * | |
539 | * @config_pci_powersave: | |
795f5e2c | 540 | * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC |
d70357d5 LR |
541 | */ |
542 | struct ath_hw_ops { | |
543 | void (*config_pci_powersave)(struct ath_hw *ah, | |
544 | int restore, | |
545 | int power_off); | |
cee1f625 | 546 | void (*rx_enable)(struct ath_hw *ah); |
87d5efbb VT |
547 | void (*set_desc_link)(void *ds, u32 link); |
548 | void (*get_desc_link)(void *ds, u32 **link); | |
795f5e2c LR |
549 | bool (*calibrate)(struct ath_hw *ah, |
550 | struct ath9k_channel *chan, | |
551 | u8 rxchainmask, | |
552 | bool longcal); | |
55e82df4 | 553 | bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked); |
d70357d5 LR |
554 | }; |
555 | ||
cbe61d8a | 556 | struct ath_hw { |
b002a4a9 | 557 | struct ieee80211_hw *hw; |
27c51f1a | 558 | struct ath_common common; |
cbe61d8a | 559 | struct ath9k_hw_version hw_version; |
2660b81a S |
560 | struct ath9k_ops_config config; |
561 | struct ath9k_hw_capabilities caps; | |
2660b81a S |
562 | struct ath9k_channel channels[38]; |
563 | struct ath9k_channel *curchan; | |
394cf0a1 | 564 | |
cbe61d8a S |
565 | union { |
566 | struct ar5416_eeprom_def def; | |
567 | struct ar5416_eeprom_4k map4k; | |
475f5989 | 568 | struct ar9287_eeprom map9287; |
2660b81a | 569 | } eeprom; |
f74df6fb | 570 | const struct eeprom_ops *eep_ops; |
cbe61d8a S |
571 | |
572 | bool sw_mgmt_crypto; | |
2660b81a | 573 | bool is_pciexpress; |
2eb46d9b | 574 | bool need_an_top2_fixup; |
2660b81a | 575 | u16 tx_trig_level; |
641d9921 FF |
576 | s16 nf_2g_max; |
577 | s16 nf_2g_min; | |
578 | s16 nf_5g_max; | |
579 | s16 nf_5g_min; | |
2660b81a S |
580 | u16 rfsilent; |
581 | u32 rfkill_gpio; | |
582 | u32 rfkill_polarity; | |
cbe61d8a | 583 | u32 ah_flags; |
394cf0a1 | 584 | |
d7e7d229 LR |
585 | bool htc_reset_init; |
586 | ||
2660b81a S |
587 | enum nl80211_iftype opmode; |
588 | enum ath9k_power_mode power_mode; | |
f078f209 | 589 | |
cbe61d8a | 590 | struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS]; |
a13883b0 | 591 | struct ath9k_pacal_info pacal_info; |
2660b81a S |
592 | struct ar5416Stats stats; |
593 | struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES]; | |
594 | ||
595 | int16_t curchan_rad_index; | |
3069168c | 596 | enum ath9k_int imask; |
74bad5cb | 597 | u32 imrs2_reg; |
2660b81a S |
598 | u32 txok_interrupt_mask; |
599 | u32 txerr_interrupt_mask; | |
600 | u32 txdesc_interrupt_mask; | |
601 | u32 txeol_interrupt_mask; | |
602 | u32 txurn_interrupt_mask; | |
603 | bool chip_fullsleep; | |
604 | u32 atim_window; | |
6a2b9e8c S |
605 | |
606 | /* Calibration */ | |
cbfe9468 S |
607 | enum ath9k_cal_types supp_cals; |
608 | struct ath9k_cal_list iq_caldata; | |
609 | struct ath9k_cal_list adcgain_caldata; | |
610 | struct ath9k_cal_list adcdc_calinitdata; | |
611 | struct ath9k_cal_list adcdc_caldata; | |
612 | struct ath9k_cal_list *cal_list; | |
613 | struct ath9k_cal_list *cal_list_last; | |
614 | struct ath9k_cal_list *cal_list_curr; | |
2660b81a S |
615 | #define totalPowerMeasI meas0.unsign |
616 | #define totalPowerMeasQ meas1.unsign | |
617 | #define totalIqCorrMeas meas2.sign | |
618 | #define totalAdcIOddPhase meas0.unsign | |
619 | #define totalAdcIEvenPhase meas1.unsign | |
620 | #define totalAdcQOddPhase meas2.unsign | |
621 | #define totalAdcQEvenPhase meas3.unsign | |
622 | #define totalAdcDcOffsetIOddPhase meas0.sign | |
623 | #define totalAdcDcOffsetIEvenPhase meas1.sign | |
624 | #define totalAdcDcOffsetQOddPhase meas2.sign | |
625 | #define totalAdcDcOffsetQEvenPhase meas3.sign | |
f078f209 LR |
626 | union { |
627 | u32 unsign[AR5416_MAX_CHAINS]; | |
628 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 629 | } meas0; |
f078f209 LR |
630 | union { |
631 | u32 unsign[AR5416_MAX_CHAINS]; | |
632 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 633 | } meas1; |
f078f209 LR |
634 | union { |
635 | u32 unsign[AR5416_MAX_CHAINS]; | |
636 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a | 637 | } meas2; |
f078f209 LR |
638 | union { |
639 | u32 unsign[AR5416_MAX_CHAINS]; | |
640 | int32_t sign[AR5416_MAX_CHAINS]; | |
2660b81a S |
641 | } meas3; |
642 | u16 cal_samples; | |
6a2b9e8c | 643 | |
2660b81a S |
644 | u32 sta_id1_defaults; |
645 | u32 misc_mode; | |
f078f209 LR |
646 | enum { |
647 | AUTO_32KHZ, | |
648 | USE_32KHZ, | |
649 | DONT_USE_32KHZ, | |
2660b81a | 650 | } enable_32kHz_clock; |
6a2b9e8c | 651 | |
d70357d5 LR |
652 | /* Private to hardware code */ |
653 | struct ath_hw_private_ops private_ops; | |
654 | /* Accessed by the lower level driver */ | |
655 | struct ath_hw_ops ops; | |
656 | ||
e68a060b | 657 | /* Used to program the radio on non single-chip devices */ |
2660b81a S |
658 | u32 *analogBank0Data; |
659 | u32 *analogBank1Data; | |
660 | u32 *analogBank2Data; | |
661 | u32 *analogBank3Data; | |
662 | u32 *analogBank6Data; | |
663 | u32 *analogBank6TPCData; | |
664 | u32 *analogBank7Data; | |
665 | u32 *addac5416_21; | |
666 | u32 *bank6Temp; | |
667 | ||
668 | int16_t txpower_indexoffset; | |
e239d859 | 669 | int coverage_class; |
2660b81a S |
670 | u32 beacon_interval; |
671 | u32 slottime; | |
2660b81a | 672 | u32 globaltxtimeout; |
6a2b9e8c S |
673 | |
674 | /* ANI */ | |
2660b81a | 675 | u32 proc_phyerr; |
2660b81a S |
676 | u32 aniperiod; |
677 | struct ar5416AniState *curani; | |
678 | struct ar5416AniState ani[255]; | |
679 | int totalSizeDesired[5]; | |
680 | int coarse_high[5]; | |
681 | int coarse_low[5]; | |
682 | int firpwr[5]; | |
683 | enum ath9k_ani_cmd ani_function; | |
684 | ||
af03abec | 685 | /* Bluetooth coexistance */ |
766ec4a9 | 686 | struct ath_btcoex_hw btcoex_hw; |
af03abec | 687 | |
2660b81a | 688 | u32 intr_txqs; |
2660b81a S |
689 | u8 txchainmask; |
690 | u8 rxchainmask; | |
691 | ||
8bd1d07f SB |
692 | u32 originalGain[22]; |
693 | int initPDADC; | |
694 | int PDADCdelta; | |
08fc5c1b | 695 | u8 led_pin; |
8bd1d07f | 696 | |
2660b81a S |
697 | struct ar5416IniArray iniModes; |
698 | struct ar5416IniArray iniCommon; | |
699 | struct ar5416IniArray iniBank0; | |
700 | struct ar5416IniArray iniBB_RfGain; | |
701 | struct ar5416IniArray iniBank1; | |
702 | struct ar5416IniArray iniBank2; | |
703 | struct ar5416IniArray iniBank3; | |
704 | struct ar5416IniArray iniBank6; | |
705 | struct ar5416IniArray iniBank6TPC; | |
706 | struct ar5416IniArray iniBank7; | |
707 | struct ar5416IniArray iniAddac; | |
708 | struct ar5416IniArray iniPcieSerdes; | |
13ce3e99 | 709 | struct ar5416IniArray iniPcieSerdesLowPower; |
2660b81a S |
710 | struct ar5416IniArray iniModesAdditional; |
711 | struct ar5416IniArray iniModesRxGain; | |
712 | struct ar5416IniArray iniModesTxGain; | |
8564328d | 713 | struct ar5416IniArray iniModes_9271_1_0_only; |
193cd458 S |
714 | struct ar5416IniArray iniCckfirNormal; |
715 | struct ar5416IniArray iniCckfirJapan2484; | |
70807e99 S |
716 | struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271; |
717 | struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271; | |
718 | struct ar5416IniArray iniModes_9271_ANI_reg; | |
719 | struct ar5416IniArray iniModes_high_power_tx_gain_9271; | |
720 | struct ar5416IniArray iniModes_normal_power_tx_gain_9271; | |
ff155a45 | 721 | |
13ce3e99 LR |
722 | struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT]; |
723 | struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT]; | |
724 | struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT]; | |
725 | struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT]; | |
726 | ||
ff155a45 VT |
727 | u32 intr_gen_timer_trigger; |
728 | u32 intr_gen_timer_thresh; | |
729 | struct ath_gen_timer_table hw_gen_timers; | |
f078f209 | 730 | }; |
f078f209 | 731 | |
9e4bffd2 LR |
732 | static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah) |
733 | { | |
734 | return &ah->common; | |
735 | } | |
736 | ||
737 | static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah) | |
738 | { | |
739 | return &(ath9k_hw_common(ah)->regulatory); | |
740 | } | |
741 | ||
d70357d5 LR |
742 | static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah) |
743 | { | |
744 | return &ah->private_ops; | |
745 | } | |
746 | ||
747 | static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah) | |
748 | { | |
749 | return &ah->ops; | |
750 | } | |
751 | ||
f637cfd6 | 752 | /* Initialization, Detach, Reset */ |
394cf0a1 | 753 | const char *ath9k_hw_probe(u16 vendorid, u16 devid); |
285f2dda | 754 | void ath9k_hw_deinit(struct ath_hw *ah); |
f637cfd6 | 755 | int ath9k_hw_init(struct ath_hw *ah); |
cbe61d8a | 756 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
394cf0a1 | 757 | bool bChannelChange); |
a9a29ce6 | 758 | int ath9k_hw_fill_cap_info(struct ath_hw *ah); |
cbe61d8a | 759 | bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, |
394cf0a1 | 760 | u32 capability, u32 *result); |
cbe61d8a | 761 | bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, |
394cf0a1 | 762 | u32 capability, u32 setting, int *status); |
8fe65368 | 763 | u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan); |
394cf0a1 S |
764 | |
765 | /* Key Cache Management */ | |
cbe61d8a S |
766 | bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry); |
767 | bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac); | |
768 | bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, | |
394cf0a1 | 769 | const struct ath9k_keyval *k, |
e0caf9ea | 770 | const u8 *mac); |
cbe61d8a | 771 | bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry); |
394cf0a1 S |
772 | |
773 | /* GPIO / RFKILL / Antennae */ | |
cbe61d8a S |
774 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio); |
775 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio); | |
776 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, | |
394cf0a1 | 777 | u32 ah_signal_type); |
cbe61d8a | 778 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val); |
cbe61d8a S |
779 | u32 ath9k_hw_getdefantenna(struct ath_hw *ah); |
780 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna); | |
394cf0a1 S |
781 | |
782 | /* General Operation */ | |
0caa7b14 | 783 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout); |
394cf0a1 | 784 | u32 ath9k_hw_reverse_bits(u32 val, u32 n); |
cbe61d8a | 785 | bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high); |
4f0fc7c3 | 786 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
545750d3 | 787 | u8 phy, int kbps, |
394cf0a1 | 788 | u32 frameLen, u16 rateix, bool shortPreamble); |
cbe61d8a | 789 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
394cf0a1 S |
790 | struct ath9k_channel *chan, |
791 | struct chan_centers *centers); | |
cbe61d8a S |
792 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah); |
793 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits); | |
794 | bool ath9k_hw_phy_disable(struct ath_hw *ah); | |
795 | bool ath9k_hw_disable(struct ath_hw *ah); | |
8fbff4b8 | 796 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit); |
cbe61d8a S |
797 | void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac); |
798 | void ath9k_hw_setopmode(struct ath_hw *ah); | |
799 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1); | |
f2b2143e LR |
800 | void ath9k_hw_setbssidmask(struct ath_hw *ah); |
801 | void ath9k_hw_write_associd(struct ath_hw *ah); | |
cbe61d8a S |
802 | u64 ath9k_hw_gettsf64(struct ath_hw *ah); |
803 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64); | |
804 | void ath9k_hw_reset_tsf(struct ath_hw *ah); | |
54e4cec6 | 805 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting); |
30cbd422 | 806 | u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp); |
0005baf4 | 807 | void ath9k_hw_init_global_settings(struct ath_hw *ah); |
25c56eec | 808 | void ath9k_hw_set11nmac2040(struct ath_hw *ah); |
cbe61d8a S |
809 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period); |
810 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, | |
394cf0a1 | 811 | const struct ath9k_beacon_state *bs); |
a91d75ae | 812 | |
9ecdef4b | 813 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode); |
a91d75ae | 814 | |
ff155a45 VT |
815 | /* Generic hw timer primitives */ |
816 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, | |
817 | void (*trigger)(void *), | |
818 | void (*overflow)(void *), | |
819 | void *arg, | |
820 | u8 timer_index); | |
cd9bf689 LR |
821 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
822 | struct ath_gen_timer *timer, | |
823 | u32 timer_next, | |
824 | u32 timer_period); | |
825 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer); | |
826 | ||
ff155a45 VT |
827 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer); |
828 | void ath_gen_timer_isr(struct ath_hw *hw); | |
1773912b | 829 | u32 ath9k_hw_gettsf32(struct ath_hw *ah); |
ff155a45 | 830 | |
f934c4d9 | 831 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len); |
2da4f01a | 832 | |
05020d23 S |
833 | /* HTC */ |
834 | void ath9k_hw_htc_resetinit(struct ath_hw *ah); | |
835 | ||
8fe65368 LR |
836 | /* PHY */ |
837 | void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, | |
838 | u32 *coef_mantissa, u32 *coef_exponent); | |
839 | ||
d8f492b7 LR |
840 | void ar9002_hw_cck_chan14_spread(struct ath_hw *ah); |
841 | ||
641d9921 FF |
842 | /* |
843 | * Code specifric to AR9003, we stuff these here to avoid callbacks | |
844 | * for older families | |
845 | */ | |
846 | void ar9003_hw_set_nf_limits(struct ath_hw *ah); | |
847 | ||
848 | /* Hardware family op attach helpers */ | |
8fe65368 | 849 | void ar5008_hw_attach_phy_ops(struct ath_hw *ah); |
8525f280 LR |
850 | void ar9002_hw_attach_phy_ops(struct ath_hw *ah); |
851 | void ar9003_hw_attach_phy_ops(struct ath_hw *ah); | |
8fe65368 | 852 | |
795f5e2c LR |
853 | void ar9002_hw_attach_calib_ops(struct ath_hw *ah); |
854 | void ar9003_hw_attach_calib_ops(struct ath_hw *ah); | |
855 | ||
b3950e6a LR |
856 | void ar9002_hw_attach_ops(struct ath_hw *ah); |
857 | void ar9003_hw_attach_ops(struct ath_hw *ah); | |
858 | ||
7b6840ab VT |
859 | #define ATH_PCIE_CAP_LINK_CTRL 0x70 |
860 | #define ATH_PCIE_CAP_LINK_L0S 1 | |
861 | #define ATH_PCIE_CAP_LINK_L1 2 | |
862 | ||
f078f209 | 863 | #endif |