ath9k_hw: fall back to OTP ROM when platform data has no valid eeprom data
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
313eb87f 22u8 ath9k_parse_mpdudensity(u8 mpdudensity)
ff37e337
S
23{
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55}
56
69081624
VT
57static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
58{
59 bool pending = false;
60
61 spin_lock_bh(&txq->axq_lock);
62
63 if (txq->axq_depth || !list_empty(&txq->axq_acq))
64 pending = true;
69081624
VT
65
66 spin_unlock_bh(&txq->axq_lock);
67 return pending;
68}
69
6d79cb4c 70static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
71{
72 unsigned long flags;
73 bool ret;
74
9ecdef4b
LR
75 spin_lock_irqsave(&sc->sc_pm_lock, flags);
76 ret = ath9k_hw_setpower(sc->sc_ah, mode);
77 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
78
79 return ret;
80}
81
a91d75ae
LR
82void ath9k_ps_wakeup(struct ath_softc *sc)
83{
898c914a 84 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 85 unsigned long flags;
fbb078fc 86 enum ath9k_power_mode power_mode;
a91d75ae
LR
87
88 spin_lock_irqsave(&sc->sc_pm_lock, flags);
89 if (++sc->ps_usecount != 1)
90 goto unlock;
91
fbb078fc 92 power_mode = sc->sc_ah->power_mode;
9ecdef4b 93 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 94
898c914a
FF
95 /*
96 * While the hardware is asleep, the cycle counters contain no
97 * useful data. Better clear them now so that they don't mess up
98 * survey data results.
99 */
fbb078fc
FF
100 if (power_mode != ATH9K_PM_AWAKE) {
101 spin_lock(&common->cc_lock);
102 ath_hw_cycle_counters_update(common);
103 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
c9ae6ab4 104 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
fbb078fc
FF
105 spin_unlock(&common->cc_lock);
106 }
898c914a 107
a91d75ae
LR
108 unlock:
109 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
110}
111
112void ath9k_ps_restore(struct ath_softc *sc)
113{
898c914a 114 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
c6c539f0 115 enum ath9k_power_mode mode;
a91d75ae 116 unsigned long flags;
ad128860 117 bool reset;
a91d75ae
LR
118
119 spin_lock_irqsave(&sc->sc_pm_lock, flags);
120 if (--sc->ps_usecount != 0)
121 goto unlock;
122
ad128860
SM
123 if (sc->ps_idle) {
124 ath9k_hw_setrxabort(sc->sc_ah, 1);
125 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
c6c539f0 126 mode = ATH9K_PM_FULL_SLEEP;
ad128860
SM
127 } else if (sc->ps_enabled &&
128 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
129 PS_WAIT_FOR_CAB |
130 PS_WAIT_FOR_PSPOLL_DATA |
131 PS_WAIT_FOR_TX_ACK))) {
c6c539f0 132 mode = ATH9K_PM_NETWORK_SLEEP;
08d4df41
RM
133 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
134 ath9k_btcoex_stop_gen_timer(sc);
ad128860 135 } else {
c6c539f0 136 goto unlock;
ad128860 137 }
c6c539f0
FF
138
139 spin_lock(&common->cc_lock);
140 ath_hw_cycle_counters_update(common);
141 spin_unlock(&common->cc_lock);
142
1a8f0d39 143 ath9k_hw_setpower(sc->sc_ah, mode);
a91d75ae
LR
144
145 unlock:
146 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
147}
148
9adcf440 149static void __ath_cancel_work(struct ath_softc *sc)
ff37e337 150{
5ee08656
FF
151 cancel_work_sync(&sc->paprd_work);
152 cancel_work_sync(&sc->hw_check_work);
153 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 154 cancel_delayed_work_sync(&sc->hw_pll_work);
fad29cd2 155
bf52592f 156#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
fad29cd2
SM
157 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
158 cancel_work_sync(&sc->mci_work);
bf52592f 159#endif
9adcf440 160}
5ee08656 161
9adcf440
FF
162static void ath_cancel_work(struct ath_softc *sc)
163{
164 __ath_cancel_work(sc);
165 cancel_work_sync(&sc->hw_reset_work);
166}
3cbb5dd7 167
af68abad
SM
168static void ath_restart_work(struct ath_softc *sc)
169{
170 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
171
172 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
173
c12b6021
GJ
174 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
175 AR_SREV_9550(sc->sc_ah))
af68abad
SM
176 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
177 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
178
179 ath_start_rx_poll(sc, 3);
180
181 if (!common->disable_ani)
182 ath_start_ani(common);
183}
184
9adcf440
FF
185static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
186{
187 struct ath_hw *ah = sc->sc_ah;
188 struct ath_common *common = ath9k_hw_common(ah);
ceea2a51 189 bool ret = true;
6a6733f2 190
9adcf440 191 ieee80211_stop_queues(sc->hw);
5e848f78 192
9adcf440
FF
193 sc->hw_busy_count = 0;
194 del_timer_sync(&common->ani.timer);
01e18918 195 del_timer_sync(&sc->rx_poll_timer);
ff37e337 196
9adcf440
FF
197 ath9k_debug_samp_bb_mac(sc);
198 ath9k_hw_disable_interrupts(ah);
8b3f4616 199
9adcf440
FF
200 if (!ath_stoprecv(sc))
201 ret = false;
c0d7c7af 202
ceea2a51
FF
203 if (!ath_drain_all_txq(sc, retry_tx))
204 ret = false;
205
9adcf440
FF
206 if (!flush) {
207 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
3483288c
FF
208 ath_rx_tasklet(sc, 1, true);
209 ath_rx_tasklet(sc, 1, false);
9adcf440
FF
210 } else {
211 ath_flushrecv(sc);
212 }
20bd2a09 213
9adcf440
FF
214 return ret;
215}
ff37e337 216
9adcf440
FF
217static bool ath_complete_reset(struct ath_softc *sc, bool start)
218{
219 struct ath_hw *ah = sc->sc_ah;
220 struct ath_common *common = ath9k_hw_common(ah);
196fb860 221 unsigned long flags;
c0d7c7af 222
c0d7c7af 223 if (ath_startrecv(sc) != 0) {
3800276a 224 ath_err(common, "Unable to restart recv logic\n");
9adcf440 225 return false;
c0d7c7af
LR
226 }
227
5048e8c3
RM
228 ath9k_cmn_update_txpow(ah, sc->curtxpow,
229 sc->config.txpowlimit, &sc->curtxpow);
b74713d0
SM
230
231 clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
72d874c6 232 ath9k_hw_set_interrupts(ah);
b037b693 233 ath9k_hw_enable_interrupts(ah);
3989279c 234
4cb54fa3 235 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
196fb860
SM
236 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
237 goto work;
238
239 ath_set_beacon(sc);
240
241 if (ah->opmode == NL80211_IFTYPE_STATION &&
242 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
243 spin_lock_irqsave(&sc->sc_pm_lock, flags);
244 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
245 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
246 }
247 work:
af68abad 248 ath_restart_work(sc);
5ee08656
FF
249 }
250
8da07830
SM
251 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
252 ath_ant_comb_update(sc);
43c35284 253
9adcf440
FF
254 ieee80211_wake_queues(sc->hw);
255
256 return true;
257}
258
259static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
260 bool retry_tx)
261{
262 struct ath_hw *ah = sc->sc_ah;
263 struct ath_common *common = ath9k_hw_common(ah);
264 struct ath9k_hw_cal_data *caldata = NULL;
265 bool fastcc = true;
266 bool flush = false;
267 int r;
268
269 __ath_cancel_work(sc);
270
271 spin_lock_bh(&sc->sc_pcu_lock);
92460412 272
4cb54fa3 273 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
9adcf440
FF
274 fastcc = false;
275 caldata = &sc->caldata;
276 }
277
278 if (!hchan) {
279 fastcc = false;
280 flush = true;
281 hchan = ah->curchan;
282 }
283
9adcf440
FF
284 if (!ath_prepare_reset(sc, retry_tx, flush))
285 fastcc = false;
286
d2182b69 287 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
feced201 288 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
9adcf440
FF
289
290 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
291 if (r) {
292 ath_err(common,
293 "Unable to reset channel, reset status %d\n", r);
294 goto out;
295 }
296
297 if (!ath_complete_reset(sc, true))
298 r = -EIO;
299
300out:
6a6733f2 301 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440
FF
302 return r;
303}
304
305
306/*
307 * Set/change channels. If the channel is really being changed, it's done
308 * by reseting the chip. To accomplish this we must first cleanup any pending
309 * DMA, then restart stuff.
310*/
311static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
312 struct ath9k_channel *hchan)
313{
314 int r;
315
781b14a3 316 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
9adcf440
FF
317 return -EIO;
318
9adcf440 319 r = ath_reset_internal(sc, hchan, false);
6a6733f2 320
3989279c 321 return r;
ff37e337
S
322}
323
7e1e3864
BG
324static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
325 struct ieee80211_vif *vif)
ff37e337
S
326{
327 struct ath_node *an;
313eb87f 328 u8 density;
ff37e337
S
329 an = (struct ath_node *)sta->drv_priv;
330
7f010c93
BG
331#ifdef CONFIG_ATH9K_DEBUGFS
332 spin_lock(&sc->nodes_lock);
333 list_add(&an->list, &sc->nodes);
334 spin_unlock(&sc->nodes_lock);
156369fa 335#endif
7f010c93 336 an->sta = sta;
7e1e3864 337 an->vif = vif;
3d4e20f2 338
a4d6367f 339 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337 340 ath_tx_node_init(sc, an);
9e98ac65 341 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc 342 sta->ht_cap.ampdu_factor);
313eb87f
SE
343 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
344 an->mpdudensity = density;
87792efc 345 }
ff37e337
S
346}
347
348static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
349{
350 struct ath_node *an = (struct ath_node *)sta->drv_priv;
351
7f010c93
BG
352#ifdef CONFIG_ATH9K_DEBUGFS
353 spin_lock(&sc->nodes_lock);
354 list_del(&an->list);
355 spin_unlock(&sc->nodes_lock);
356 an->sta = NULL;
357#endif
358
a4d6367f 359 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
ff37e337
S
360 ath_tx_node_cleanup(sc, an);
361}
362
55624204 363void ath9k_tasklet(unsigned long data)
ff37e337
S
364{
365 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 366 struct ath_hw *ah = sc->sc_ah;
c46917bb 367 struct ath_common *common = ath9k_hw_common(ah);
07c15a3f 368 unsigned long flags;
17d7904d 369 u32 status = sc->intrstatus;
b5c80475 370 u32 rxmask;
ff37e337 371
e3927007
FF
372 ath9k_ps_wakeup(sc);
373 spin_lock(&sc->sc_pcu_lock);
374
a4d86d95
RM
375 if ((status & ATH9K_INT_FATAL) ||
376 (status & ATH9K_INT_BB_WATCHDOG)) {
030d6294
FF
377#ifdef CONFIG_ATH9K_DEBUGFS
378 enum ath_reset_type type;
379
380 if (status & ATH9K_INT_FATAL)
381 type = RESET_TYPE_FATAL_INT;
382 else
383 type = RESET_TYPE_BB_WATCHDOG;
384
385 RESET_STAT_INC(sc, type);
386#endif
b74713d0 387 set_bit(SC_OP_HW_RESET, &sc->sc_flags);
236de514 388 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
e3927007 389 goto out;
063d8be3 390 }
ff37e337 391
07c15a3f 392 spin_lock_irqsave(&sc->sc_pm_lock, flags);
4105f807
RM
393 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
394 /*
395 * TSF sync does not look correct; remain awake to sync with
396 * the next Beacon.
397 */
d2182b69 398 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
e8fe7336 399 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
4105f807 400 }
07c15a3f 401 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
4105f807 402
b5c80475
FF
403 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
404 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
405 ATH9K_INT_RXORN);
406 else
407 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
408
409 if (status & rxmask) {
b5c80475
FF
410 /* Check for high priority Rx first */
411 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
412 (status & ATH9K_INT_RXHP))
413 ath_rx_tasklet(sc, 0, true);
414
415 ath_rx_tasklet(sc, 0, false);
ff37e337
S
416 }
417
e5003249
VT
418 if (status & ATH9K_INT_TX) {
419 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
420 ath_tx_edma_tasklet(sc);
421 else
422 ath_tx_tasklet(sc);
423 }
063d8be3 424
56ca0dba 425 ath9k_btcoex_handle_interrupt(sc, status);
19686ddf 426
e3927007 427out:
ff37e337 428 /* re-enable hardware interrupt */
4df3071e 429 ath9k_hw_enable_interrupts(ah);
6a6733f2 430
52671e43 431 spin_unlock(&sc->sc_pcu_lock);
153e080d 432 ath9k_ps_restore(sc);
ff37e337
S
433}
434
6baff7f9 435irqreturn_t ath_isr(int irq, void *dev)
ff37e337 436{
063d8be3
S
437#define SCHED_INTR ( \
438 ATH9K_INT_FATAL | \
a4d86d95 439 ATH9K_INT_BB_WATCHDOG | \
063d8be3
S
440 ATH9K_INT_RXORN | \
441 ATH9K_INT_RXEOL | \
442 ATH9K_INT_RX | \
b5c80475
FF
443 ATH9K_INT_RXLP | \
444 ATH9K_INT_RXHP | \
063d8be3
S
445 ATH9K_INT_TX | \
446 ATH9K_INT_BMISS | \
447 ATH9K_INT_CST | \
ebb8e1d7 448 ATH9K_INT_TSFOOR | \
40dc5392
MSS
449 ATH9K_INT_GENTIMER | \
450 ATH9K_INT_MCI)
063d8be3 451
ff37e337 452 struct ath_softc *sc = dev;
cbe61d8a 453 struct ath_hw *ah = sc->sc_ah;
b5bfc568 454 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
455 enum ath9k_int status;
456 bool sched = false;
457
063d8be3
S
458 /*
459 * The hardware is not ready/present, don't
460 * touch anything. Note this can happen early
461 * on if the IRQ is shared.
462 */
781b14a3 463 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
063d8be3 464 return IRQ_NONE;
ff37e337 465
063d8be3
S
466 /* shared irq, not for us */
467
153e080d 468 if (!ath9k_hw_intrpend(ah))
063d8be3 469 return IRQ_NONE;
063d8be3 470
b74713d0
SM
471 if(test_bit(SC_OP_HW_RESET, &sc->sc_flags))
472 return IRQ_HANDLED;
473
063d8be3
S
474 /*
475 * Figure out the reason(s) for the interrupt. Note
476 * that the hal returns a pseudo-ISR that may include
477 * bits we haven't explicitly enabled so we mask the
478 * value to insure we only process bits we requested.
479 */
480 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 481 status &= ah->imask; /* discard unasked-for bits */
ff37e337 482
063d8be3
S
483 /*
484 * If there are no status bits set, then this interrupt was not
485 * for me (should have been caught above).
486 */
153e080d 487 if (!status)
063d8be3 488 return IRQ_NONE;
ff37e337 489
063d8be3
S
490 /* Cache the status */
491 sc->intrstatus = status;
492
493 if (status & SCHED_INTR)
494 sched = true;
495
b11e640a
MSS
496#ifdef CONFIG_PM_SLEEP
497 if (status & ATH9K_INT_BMISS) {
498 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
499 ath_dbg(common, ANY, "during WoW we got a BMISS\n");
500 atomic_inc(&sc->wow_got_bmiss_intr);
501 atomic_dec(&sc->wow_sleep_proc_intr);
502 }
503 ath_dbg(common, INTERRUPT, "beacon miss interrupt\n");
504 }
505#endif
506
063d8be3
S
507 /*
508 * If a FATAL or RXORN interrupt is received, we have to reset the
509 * chip immediately.
510 */
b5c80475
FF
511 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
512 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S
513 goto chip_reset;
514
08578b8f
LR
515 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
516 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF
517
518 spin_lock(&common->cc_lock);
519 ath_hw_cycle_counters_update(common);
08578b8f 520 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF
521 spin_unlock(&common->cc_lock);
522
08578b8f
LR
523 goto chip_reset;
524 }
525
063d8be3
S
526 if (status & ATH9K_INT_SWBA)
527 tasklet_schedule(&sc->bcon_tasklet);
528
529 if (status & ATH9K_INT_TXURN)
530 ath9k_hw_updatetxtriglevel(ah, true);
531
0682c9b5
RM
532 if (status & ATH9K_INT_RXEOL) {
533 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
72d874c6 534 ath9k_hw_set_interrupts(ah);
b5c80475
FF
535 }
536
153e080d
VT
537 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
538 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR
539 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
540 goto chip_reset;
063d8be3
S
541 /* Clear RxAbort bit so that we can
542 * receive frames */
9ecdef4b 543 ath9k_setpower(sc, ATH9K_PM_AWAKE);
07c15a3f 544 spin_lock(&sc->sc_pm_lock);
153e080d 545 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 546 sc->ps_flags |= PS_WAIT_FOR_BEACON;
07c15a3f 547 spin_unlock(&sc->sc_pm_lock);
ff37e337 548 }
063d8be3
S
549
550chip_reset:
ff37e337 551
817e11de
S
552 ath_debug_stat_interrupt(sc, status);
553
ff37e337 554 if (sched) {
4df3071e
FF
555 /* turn off every interrupt */
556 ath9k_hw_disable_interrupts(ah);
ff37e337
S
557 tasklet_schedule(&sc->intr_tq);
558 }
559
560 return IRQ_HANDLED;
063d8be3
S
561
562#undef SCHED_INTR
ff37e337
S
563}
564
236de514 565static int ath_reset(struct ath_softc *sc, bool retry_tx)
ff37e337 566{
ae8d2858 567 int r;
ff37e337 568
783cd01e 569 ath9k_ps_wakeup(sc);
6a6733f2 570
9adcf440 571 r = ath_reset_internal(sc, NULL, retry_tx);
ff37e337
S
572
573 if (retry_tx) {
574 int i;
575 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
576 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
577 spin_lock_bh(&sc->tx.txq[i].axq_lock);
578 ath_txq_schedule(sc, &sc->tx.txq[i]);
579 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
580 }
581 }
582 }
583
783cd01e 584 ath9k_ps_restore(sc);
2ab81d4a 585
ae8d2858 586 return r;
ff37e337
S
587}
588
236de514
FF
589void ath_reset_work(struct work_struct *work)
590{
591 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
592
236de514 593 ath_reset(sc, true);
236de514
FF
594}
595
ff37e337
S
596/**********************/
597/* mac80211 callbacks */
598/**********************/
599
8feceb67 600static int ath9k_start(struct ieee80211_hw *hw)
f078f209 601{
9ac58615 602 struct ath_softc *sc = hw->priv;
af03abec 603 struct ath_hw *ah = sc->sc_ah;
c46917bb 604 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 605 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 606 struct ath9k_channel *init_channel;
82880a7c 607 int r;
f078f209 608
d2182b69 609 ath_dbg(common, CONFIG,
226afe68
JP
610 "Starting driver with initial channel: %d MHz\n",
611 curchan->center_freq);
f078f209 612
f62d816f 613 ath9k_ps_wakeup(sc);
141b38b6
S
614 mutex_lock(&sc->mutex);
615
c344c9cb 616 init_channel = ath9k_cmn_get_curchannel(hw, ah);
ff37e337
S
617
618 /* Reset SERDES registers */
84c87dc8 619 ath9k_hw_configpcipowersave(ah, false);
ff37e337
S
620
621 /*
622 * The basic interface to setting the hardware in a good
623 * state is ``reset''. On return the hardware is known to
624 * be powered up and with interrupts disabled. This must
625 * be followed by initialization of the appropriate bits
626 * and then setup of the interrupt mask.
627 */
4bdd1e97 628 spin_lock_bh(&sc->sc_pcu_lock);
c0c11741
FF
629
630 atomic_set(&ah->intr_ref_cnt, -1);
631
20bd2a09 632 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 633 if (r) {
3800276a
JP
634 ath_err(common,
635 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
636 r, curchan->center_freq);
4bdd1e97 637 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 638 goto mutex_unlock;
ff37e337 639 }
ff37e337 640
ff37e337 641 /* Setup our intr mask. */
b5c80475
FF
642 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
643 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
644 ATH9K_INT_GLOBAL;
645
646 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR
647 ah->imask |= ATH9K_INT_RXHP |
648 ATH9K_INT_RXLP |
649 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF
650 else
651 ah->imask |= ATH9K_INT_RX;
ff37e337 652
364734fa 653 ah->imask |= ATH9K_INT_GTT;
ff37e337 654
af03abec 655 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 656 ah->imask |= ATH9K_INT_CST;
ff37e337 657
e270e776 658 ath_mci_enable(sc);
40dc5392 659
781b14a3 660 clear_bit(SC_OP_INVALID, &sc->sc_flags);
5f841b41 661 sc->sc_ah->is_monitoring = false;
ff37e337 662
9adcf440
FF
663 if (!ath_complete_reset(sc, false)) {
664 r = -EIO;
665 spin_unlock_bh(&sc->sc_pcu_lock);
666 goto mutex_unlock;
667 }
ff37e337 668
c0c11741
FF
669 if (ah->led_pin >= 0) {
670 ath9k_hw_cfg_output(ah, ah->led_pin,
671 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
672 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
673 }
674
675 /*
676 * Reset key cache to sane defaults (all entries cleared) instead of
677 * semi-random values after suspend/resume.
678 */
679 ath9k_cmn_init_crypto(sc->sc_ah);
680
9adcf440 681 spin_unlock_bh(&sc->sc_pcu_lock);
164ace38 682
8060e169
VT
683 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
684 common->bus_ops->extn_synch_en(common);
685
141b38b6
S
686mutex_unlock:
687 mutex_unlock(&sc->mutex);
688
f62d816f
FF
689 ath9k_ps_restore(sc);
690
ae8d2858 691 return r;
f078f209
LR
692}
693
7bb45683 694static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
f078f209 695{
9ac58615 696 struct ath_softc *sc = hw->priv;
c46917bb 697 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 698 struct ath_tx_control txctl;
1bc14880 699 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
07c15a3f 700 unsigned long flags;
528f0c6b 701
96148326 702 if (sc->ps_enabled) {
dc8c4585
JM
703 /*
704 * mac80211 does not set PM field for normal data frames, so we
705 * need to update that based on the current PS mode.
706 */
707 if (ieee80211_is_data(hdr->frame_control) &&
708 !ieee80211_is_nullfunc(hdr->frame_control) &&
709 !ieee80211_has_pm(hdr->frame_control)) {
d2182b69 710 ath_dbg(common, PS,
226afe68 711 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM
712 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
713 }
714 }
715
ad128860 716 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
9a23f9ca
JM
717 /*
718 * We are using PS-Poll and mac80211 can request TX while in
719 * power save mode. Need to wake up hardware for the TX to be
720 * completed and if needed, also for RX of buffered frames.
721 */
9a23f9ca 722 ath9k_ps_wakeup(sc);
07c15a3f 723 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fdf76622
VT
724 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
725 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 726 if (ieee80211_is_pspoll(hdr->frame_control)) {
d2182b69 727 ath_dbg(common, PS,
226afe68 728 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 729 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 730 } else {
d2182b69 731 ath_dbg(common, PS, "Wake up to complete TX\n");
1b04b930 732 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
733 }
734 /*
735 * The actual restore operation will happen only after
ad128860 736 * the ps_flags bit is cleared. We are just dropping
9a23f9ca
JM
737 * the ps_usecount here.
738 */
07c15a3f 739 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
9a23f9ca
JM
740 ath9k_ps_restore(sc);
741 }
742
ad128860
SM
743 /*
744 * Cannot tx while the hardware is in full sleep, it first needs a full
745 * chip reset to recover from that
746 */
747 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
748 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
749 goto exit;
750 }
751
528f0c6b 752 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 753 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
528f0c6b 754
d2182b69 755 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 756
c52f33d0 757 if (ath_tx_start(hw, skb, &txctl) != 0) {
d2182b69 758 ath_dbg(common, XMIT, "TX failed\n");
a5a0bca1 759 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
528f0c6b 760 goto exit;
8feceb67
VT
761 }
762
7bb45683 763 return;
528f0c6b
S
764exit:
765 dev_kfree_skb_any(skb);
f078f209
LR
766}
767
8feceb67 768static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 769{
9ac58615 770 struct ath_softc *sc = hw->priv;
af03abec 771 struct ath_hw *ah = sc->sc_ah;
c46917bb 772 struct ath_common *common = ath9k_hw_common(ah);
c0c11741 773 bool prev_idle;
f078f209 774
4c483817
S
775 mutex_lock(&sc->mutex);
776
9adcf440 777 ath_cancel_work(sc);
01e18918 778 del_timer_sync(&sc->rx_poll_timer);
c94dbff7 779
781b14a3 780 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
d2182b69 781 ath_dbg(common, ANY, "Device not present\n");
4c483817 782 mutex_unlock(&sc->mutex);
9c84b797
S
783 return;
784 }
8feceb67 785
3867cf6a
S
786 /* Ensure HW is awake when we try to shut it down. */
787 ath9k_ps_wakeup(sc);
788
6a6733f2
LR
789 spin_lock_bh(&sc->sc_pcu_lock);
790
203043f5
SG
791 /* prevent tasklets to enable interrupts once we disable them */
792 ah->imask &= ~ATH9K_INT_GLOBAL;
793
ff37e337
S
794 /* make sure h/w will not generate any interrupt
795 * before setting the invalid flag. */
4df3071e 796 ath9k_hw_disable_interrupts(ah);
ff37e337 797
c0c11741
FF
798 spin_unlock_bh(&sc->sc_pcu_lock);
799
800 /* we can now sync irq and kill any running tasklets, since we already
801 * disabled interrupts and not holding a spin lock */
802 synchronize_irq(sc->irq);
803 tasklet_kill(&sc->intr_tq);
804 tasklet_kill(&sc->bcon_tasklet);
805
806 prev_idle = sc->ps_idle;
807 sc->ps_idle = true;
808
809 spin_lock_bh(&sc->sc_pcu_lock);
810
811 if (ah->led_pin >= 0) {
812 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
813 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
814 }
815
816 ath_prepare_reset(sc, false, true);
ff37e337 817
0d95521e
FF
818 if (sc->rx.frag) {
819 dev_kfree_skb_any(sc->rx.frag);
820 sc->rx.frag = NULL;
821 }
822
c0c11741
FF
823 if (!ah->curchan)
824 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
6a6733f2 825
c0c11741
FF
826 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
827 ath9k_hw_phy_disable(ah);
6a6733f2 828
c0c11741 829 ath9k_hw_configpcipowersave(ah, true);
203043f5 830
c0c11741 831 spin_unlock_bh(&sc->sc_pcu_lock);
3867cf6a 832
c0c11741 833 ath9k_ps_restore(sc);
ff37e337 834
781b14a3 835 set_bit(SC_OP_INVALID, &sc->sc_flags);
c0c11741 836 sc->ps_idle = prev_idle;
500c064d 837
141b38b6
S
838 mutex_unlock(&sc->mutex);
839
d2182b69 840 ath_dbg(common, CONFIG, "Driver halt\n");
f078f209
LR
841}
842
4801416c
BG
843bool ath9k_uses_beacons(int type)
844{
845 switch (type) {
846 case NL80211_IFTYPE_AP:
847 case NL80211_IFTYPE_ADHOC:
848 case NL80211_IFTYPE_MESH_POINT:
849 return true;
850 default:
851 return false;
852 }
853}
854
855static void ath9k_reclaim_beacon(struct ath_softc *sc,
856 struct ieee80211_vif *vif)
f078f209 857{
1ed32e4f 858 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67 859
014cf3bb 860 ath9k_set_beaconing_status(sc, false);
4801416c 861 ath_beacon_return(sc, avp);
014cf3bb 862 ath9k_set_beaconing_status(sc, true);
4801416c
BG
863}
864
865static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
866{
867 struct ath9k_vif_iter_data *iter_data = data;
868 int i;
869
870 if (iter_data->hw_macaddr)
871 for (i = 0; i < ETH_ALEN; i++)
872 iter_data->mask[i] &=
873 ~(iter_data->hw_macaddr[i] ^ mac[i]);
141b38b6 874
1ed32e4f 875 switch (vif->type) {
4801416c
BG
876 case NL80211_IFTYPE_AP:
877 iter_data->naps++;
f078f209 878 break;
4801416c
BG
879 case NL80211_IFTYPE_STATION:
880 iter_data->nstations++;
e51f3eff 881 break;
05c914fe 882 case NL80211_IFTYPE_ADHOC:
4801416c
BG
883 iter_data->nadhocs++;
884 break;
9cb5412b 885 case NL80211_IFTYPE_MESH_POINT:
4801416c
BG
886 iter_data->nmeshes++;
887 break;
888 case NL80211_IFTYPE_WDS:
889 iter_data->nwds++;
f078f209
LR
890 break;
891 default:
4801416c 892 break;
f078f209 893 }
4801416c 894}
f078f209 895
4801416c
BG
896/* Called with sc->mutex held. */
897void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
898 struct ieee80211_vif *vif,
899 struct ath9k_vif_iter_data *iter_data)
900{
9ac58615 901 struct ath_softc *sc = hw->priv;
4801416c
BG
902 struct ath_hw *ah = sc->sc_ah;
903 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 904
4801416c
BG
905 /*
906 * Use the hardware MAC address as reference, the hardware uses it
907 * together with the BSSID mask when matching addresses.
908 */
909 memset(iter_data, 0, sizeof(*iter_data));
910 iter_data->hw_macaddr = common->macaddr;
911 memset(&iter_data->mask, 0xff, ETH_ALEN);
5640b08e 912
4801416c
BG
913 if (vif)
914 ath9k_vif_iter(iter_data, vif->addr, vif);
915
916 /* Get list of all active MAC addresses */
4801416c
BG
917 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
918 iter_data);
4801416c 919}
8ca21f01 920
4801416c
BG
921/* Called with sc->mutex held. */
922static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
923 struct ieee80211_vif *vif)
924{
9ac58615 925 struct ath_softc *sc = hw->priv;
4801416c
BG
926 struct ath_hw *ah = sc->sc_ah;
927 struct ath_common *common = ath9k_hw_common(ah);
928 struct ath9k_vif_iter_data iter_data;
8ca21f01 929
4801416c 930 ath9k_calculate_iter_data(hw, vif, &iter_data);
2c3db3d5 931
4801416c
BG
932 /* Set BSSID mask. */
933 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
934 ath_hw_setbssidmask(common);
935
936 /* Set op-mode & TSF */
937 if (iter_data.naps > 0) {
3069168c 938 ath9k_hw_set_tsfadjust(ah, 1);
781b14a3 939 set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
4801416c
BG
940 ah->opmode = NL80211_IFTYPE_AP;
941 } else {
942 ath9k_hw_set_tsfadjust(ah, 0);
781b14a3 943 clear_bit(SC_OP_TSF_RESET, &sc->sc_flags);
5640b08e 944
fd5999cf
JC
945 if (iter_data.nmeshes)
946 ah->opmode = NL80211_IFTYPE_MESH_POINT;
947 else if (iter_data.nwds)
4801416c
BG
948 ah->opmode = NL80211_IFTYPE_AP;
949 else if (iter_data.nadhocs)
950 ah->opmode = NL80211_IFTYPE_ADHOC;
951 else
952 ah->opmode = NL80211_IFTYPE_STATION;
953 }
5640b08e 954
4e30ffa2
VN
955 /*
956 * Enable MIB interrupts when there are hardware phy counters.
4e30ffa2 957 */
198823fd 958 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
3069168c 959 ah->imask |= ATH9K_INT_TSFOOR;
198823fd 960 else
4801416c 961 ah->imask &= ~ATH9K_INT_TSFOOR;
4af9cf4f 962
72d874c6 963 ath9k_hw_set_interrupts(ah);
4e30ffa2 964
4801416c 965 /* Set up ANI */
2e5ef459 966 if (iter_data.naps > 0) {
729da390 967 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
05c0be2f
MSS
968
969 if (!common->disable_ani) {
781b14a3 970 set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
05c0be2f
MSS
971 ath_start_ani(common);
972 }
973
f60c49b6 974 } else {
781b14a3 975 clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
f60c49b6 976 del_timer_sync(&common->ani.timer);
6c3118e2 977 }
4801416c 978}
6f255425 979
4801416c
BG
980/* Called with sc->mutex held, vif counts set up properly. */
981static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
982 struct ieee80211_vif *vif)
983{
9ac58615 984 struct ath_softc *sc = hw->priv;
4801416c
BG
985
986 ath9k_calculate_summary_state(hw, vif);
987
988 if (ath9k_uses_beacons(vif->type)) {
ed2578cd 989 /* Reserve a beacon slot for the vif */
014cf3bb 990 ath9k_set_beaconing_status(sc, false);
ed2578cd 991 ath_beacon_alloc(sc, vif);
014cf3bb 992 ath9k_set_beaconing_status(sc, true);
4801416c 993 }
f078f209
LR
994}
995
4801416c
BG
996static int ath9k_add_interface(struct ieee80211_hw *hw,
997 struct ieee80211_vif *vif)
6b3b991d 998{
9ac58615 999 struct ath_softc *sc = hw->priv;
4801416c
BG
1000 struct ath_hw *ah = sc->sc_ah;
1001 struct ath_common *common = ath9k_hw_common(ah);
4801416c 1002 int ret = 0;
6b3b991d 1003
96f372c9 1004 ath9k_ps_wakeup(sc);
4801416c 1005 mutex_lock(&sc->mutex);
6b3b991d 1006
4801416c
BG
1007 switch (vif->type) {
1008 case NL80211_IFTYPE_STATION:
1009 case NL80211_IFTYPE_WDS:
1010 case NL80211_IFTYPE_ADHOC:
1011 case NL80211_IFTYPE_AP:
1012 case NL80211_IFTYPE_MESH_POINT:
1013 break;
1014 default:
1015 ath_err(common, "Interface type %d not yet supported\n",
1016 vif->type);
1017 ret = -EOPNOTSUPP;
1018 goto out;
1019 }
6b3b991d 1020
4801416c
BG
1021 if (ath9k_uses_beacons(vif->type)) {
1022 if (sc->nbcnvifs >= ATH_BCBUF) {
1023 ath_err(common, "Not enough beacon buffers when adding"
1024 " new interface of type: %i\n",
1025 vif->type);
1026 ret = -ENOBUFS;
1027 goto out;
1028 }
1029 }
1030
d2182b69 1031 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
4801416c 1032
4801416c
BG
1033 sc->nvifs++;
1034
1035 ath9k_do_vif_add_setup(hw, vif);
1036out:
1037 mutex_unlock(&sc->mutex);
96f372c9 1038 ath9k_ps_restore(sc);
4801416c 1039 return ret;
6b3b991d
RM
1040}
1041
1042static int ath9k_change_interface(struct ieee80211_hw *hw,
1043 struct ieee80211_vif *vif,
1044 enum nl80211_iftype new_type,
1045 bool p2p)
1046{
9ac58615 1047 struct ath_softc *sc = hw->priv;
6b3b991d 1048 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
6dab55bf 1049 int ret = 0;
6b3b991d 1050
d2182b69 1051 ath_dbg(common, CONFIG, "Change Interface\n");
6b3b991d 1052 mutex_lock(&sc->mutex);
96f372c9 1053 ath9k_ps_wakeup(sc);
6b3b991d 1054
4801416c
BG
1055 if (ath9k_uses_beacons(new_type) &&
1056 !ath9k_uses_beacons(vif->type)) {
6b3b991d
RM
1057 if (sc->nbcnvifs >= ATH_BCBUF) {
1058 ath_err(common, "No beacon slot available\n");
6dab55bf
DC
1059 ret = -ENOBUFS;
1060 goto out;
6b3b991d 1061 }
6b3b991d 1062 }
4801416c
BG
1063
1064 /* Clean up old vif stuff */
1065 if (ath9k_uses_beacons(vif->type))
1066 ath9k_reclaim_beacon(sc, vif);
1067
1068 /* Add new settings */
6b3b991d
RM
1069 vif->type = new_type;
1070 vif->p2p = p2p;
1071
4801416c 1072 ath9k_do_vif_add_setup(hw, vif);
6dab55bf 1073out:
96f372c9 1074 ath9k_ps_restore(sc);
6b3b991d 1075 mutex_unlock(&sc->mutex);
6dab55bf 1076 return ret;
6b3b991d
RM
1077}
1078
8feceb67 1079static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1080 struct ieee80211_vif *vif)
f078f209 1081{
9ac58615 1082 struct ath_softc *sc = hw->priv;
c46917bb 1083 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f078f209 1084
d2182b69 1085 ath_dbg(common, CONFIG, "Detach Interface\n");
f078f209 1086
96f372c9 1087 ath9k_ps_wakeup(sc);
141b38b6
S
1088 mutex_lock(&sc->mutex);
1089
4801416c 1090 sc->nvifs--;
580f0b8a 1091
8feceb67 1092 /* Reclaim beacon resources */
4801416c 1093 if (ath9k_uses_beacons(vif->type))
6b3b991d 1094 ath9k_reclaim_beacon(sc, vif);
2c3db3d5 1095
4801416c 1096 ath9k_calculate_summary_state(hw, NULL);
141b38b6
S
1097
1098 mutex_unlock(&sc->mutex);
96f372c9 1099 ath9k_ps_restore(sc);
f078f209
LR
1100}
1101
fbab7390 1102static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1103{
3069168c 1104 struct ath_hw *ah = sc->sc_ah;
ad128860 1105 struct ath_common *common = ath9k_hw_common(ah);
3069168c 1106
3f7c5c10 1107 sc->ps_enabled = true;
3069168c
PR
1108 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1109 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1110 ah->imask |= ATH9K_INT_TIM_TIMER;
72d874c6 1111 ath9k_hw_set_interrupts(ah);
3f7c5c10 1112 }
fdf76622 1113 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1114 }
ad128860 1115 ath_dbg(common, PS, "PowerSave enabled\n");
3f7c5c10
SB
1116}
1117
845d708e
SB
1118static void ath9k_disable_ps(struct ath_softc *sc)
1119{
1120 struct ath_hw *ah = sc->sc_ah;
ad128860 1121 struct ath_common *common = ath9k_hw_common(ah);
845d708e
SB
1122
1123 sc->ps_enabled = false;
1124 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1125 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1126 ath9k_hw_setrxabort(ah, 0);
1127 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1128 PS_WAIT_FOR_CAB |
1129 PS_WAIT_FOR_PSPOLL_DATA |
1130 PS_WAIT_FOR_TX_ACK);
1131 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1132 ah->imask &= ~ATH9K_INT_TIM_TIMER;
72d874c6 1133 ath9k_hw_set_interrupts(ah);
845d708e
SB
1134 }
1135 }
ad128860 1136 ath_dbg(common, PS, "PowerSave disabled\n");
845d708e
SB
1137}
1138
e8975581 1139static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1140{
9ac58615 1141 struct ath_softc *sc = hw->priv;
3430098a
FF
1142 struct ath_hw *ah = sc->sc_ah;
1143 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1144 struct ieee80211_conf *conf = &hw->conf;
75600abf 1145 bool reset_channel = false;
f078f209 1146
c0c11741 1147 ath9k_ps_wakeup(sc);
aa33de09 1148 mutex_lock(&sc->mutex);
141b38b6 1149
daa1b6ee 1150 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4 1151 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
b73f3e78 1152 if (sc->ps_idle) {
daa1b6ee 1153 ath_cancel_work(sc);
b73f3e78
RM
1154 ath9k_stop_btcoex(sc);
1155 } else {
1156 ath9k_start_btcoex(sc);
75600abf
FF
1157 /*
1158 * The chip needs a reset to properly wake up from
1159 * full sleep
1160 */
1161 reset_channel = ah->chip_fullsleep;
b73f3e78 1162 }
daa1b6ee 1163 }
64839170 1164
e7824a50
LR
1165 /*
1166 * We just prepare to enable PS. We have to wait until our AP has
1167 * ACK'd our null data frame to disable RX otherwise we'll ignore
1168 * those ACKs and end up retransmitting the same null data frames.
1169 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1170 */
3cbb5dd7 1171 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR
1172 unsigned long flags;
1173 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB
1174 if (conf->flags & IEEE80211_CONF_PS)
1175 ath9k_enable_ps(sc);
845d708e
SB
1176 else
1177 ath9k_disable_ps(sc);
8ab2cd09 1178 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN
1179 }
1180
199afd9d
S
1181 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1182 if (conf->flags & IEEE80211_CONF_MONITOR) {
d2182b69 1183 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
5f841b41
RM
1184 sc->sc_ah->is_monitoring = true;
1185 } else {
d2182b69 1186 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
5f841b41 1187 sc->sc_ah->is_monitoring = false;
199afd9d
S
1188 }
1189 }
1190
75600abf 1191 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
99405f93 1192 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1193 int pos = curchan->hw_value;
3430098a
FF
1194 int old_pos = -1;
1195 unsigned long flags;
1196
1197 if (ah->curchan)
1198 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1199
d2182b69 1200 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
8c79a610 1201 curchan->center_freq, conf->channel_type);
f078f209 1202
3430098a
FF
1203 /* update survey stats for the old channel before switching */
1204 spin_lock_irqsave(&common->cc_lock, flags);
1205 ath_update_survey_stats(sc);
1206 spin_unlock_irqrestore(&common->cc_lock, flags);
1207
e338a85e
RM
1208 /*
1209 * Preserve the current channel values, before updating
1210 * the same channel
1211 */
1a19f77f
RM
1212 if (ah->curchan && (old_pos == pos))
1213 ath9k_hw_getnf(ah, ah->curchan);
e338a85e
RM
1214
1215 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1216 curchan, conf->channel_type);
1217
3430098a
FF
1218 /*
1219 * If the operating channel changes, change the survey in-use flags
1220 * along with it.
1221 * Reset the survey data for the new channel, unless we're switching
1222 * back to the operating channel from an off-channel operation.
1223 */
1224 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1225 sc->cur_survey != &sc->survey[pos]) {
1226
1227 if (sc->cur_survey)
1228 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1229
1230 sc->cur_survey = &sc->survey[pos];
1231
1232 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1233 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1234 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1235 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1236 }
1237
0e2dedf9 1238 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
3800276a 1239 ath_err(common, "Unable to set channel\n");
aa33de09 1240 mutex_unlock(&sc->mutex);
8389fb3f 1241 ath9k_ps_restore(sc);
e11602b7
S
1242 return -EINVAL;
1243 }
3430098a
FF
1244
1245 /*
1246 * The most recent snapshot of channel->noisefloor for the old
1247 * channel is only available after the hardware reset. Copy it to
1248 * the survey stats now.
1249 */
1250 if (old_pos >= 0)
1251 ath_update_survey_nf(sc, old_pos);
094d05dc 1252 }
f078f209 1253
c9f6a656 1254 if (changed & IEEE80211_CONF_CHANGE_POWER) {
d2182b69 1255 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
17d7904d 1256 sc->config.txpowlimit = 2 * conf->power_level;
5048e8c3
RM
1257 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1258 sc->config.txpowlimit, &sc->curtxpow);
64839170
LR
1259 }
1260
aa33de09 1261 mutex_unlock(&sc->mutex);
c0c11741 1262 ath9k_ps_restore(sc);
141b38b6 1263
f078f209
LR
1264 return 0;
1265}
1266
8feceb67
VT
1267#define SUPPORTED_FILTERS \
1268 (FIF_PROMISC_IN_BSS | \
1269 FIF_ALLMULTI | \
1270 FIF_CONTROL | \
af6a3fc7 1271 FIF_PSPOLL | \
8feceb67
VT
1272 FIF_OTHER_BSS | \
1273 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1274 FIF_PROBE_REQ | \
8feceb67 1275 FIF_FCSFAIL)
c83be688 1276
8feceb67
VT
1277/* FIXME: sc->sc_full_reset ? */
1278static void ath9k_configure_filter(struct ieee80211_hw *hw,
1279 unsigned int changed_flags,
1280 unsigned int *total_flags,
3ac64bee 1281 u64 multicast)
8feceb67 1282{
9ac58615 1283 struct ath_softc *sc = hw->priv;
8feceb67 1284 u32 rfilt;
f078f209 1285
8feceb67
VT
1286 changed_flags &= SUPPORTED_FILTERS;
1287 *total_flags &= SUPPORTED_FILTERS;
f078f209 1288
b77f483f 1289 sc->rx.rxfilter = *total_flags;
aa68aeaa 1290 ath9k_ps_wakeup(sc);
8feceb67
VT
1291 rfilt = ath_calcrxfilter(sc);
1292 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1293 ath9k_ps_restore(sc);
f078f209 1294
d2182b69
JP
1295 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1296 rfilt);
8feceb67 1297}
f078f209 1298
4ca77860
JB
1299static int ath9k_sta_add(struct ieee80211_hw *hw,
1300 struct ieee80211_vif *vif,
1301 struct ieee80211_sta *sta)
8feceb67 1302{
9ac58615 1303 struct ath_softc *sc = hw->priv;
93ae2dd2
FF
1304 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1305 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1306 struct ieee80211_key_conf ps_key = { };
f078f209 1307
7e1e3864 1308 ath_node_attach(sc, sta, vif);
f59a59fe
FF
1309
1310 if (vif->type != NL80211_IFTYPE_AP &&
1311 vif->type != NL80211_IFTYPE_AP_VLAN)
1312 return 0;
1313
93ae2dd2 1314 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
4ca77860
JB
1315
1316 return 0;
1317}
1318
93ae2dd2
FF
1319static void ath9k_del_ps_key(struct ath_softc *sc,
1320 struct ieee80211_vif *vif,
1321 struct ieee80211_sta *sta)
1322{
1323 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1324 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1325 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1326
1327 if (!an->ps_key)
1328 return;
1329
1330 ath_key_delete(common, &ps_key);
1331}
1332
4ca77860
JB
1333static int ath9k_sta_remove(struct ieee80211_hw *hw,
1334 struct ieee80211_vif *vif,
1335 struct ieee80211_sta *sta)
1336{
9ac58615 1337 struct ath_softc *sc = hw->priv;
4ca77860 1338
93ae2dd2 1339 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB
1340 ath_node_detach(sc, sta);
1341
1342 return 0;
f078f209
LR
1343}
1344
5519541d
FF
1345static void ath9k_sta_notify(struct ieee80211_hw *hw,
1346 struct ieee80211_vif *vif,
1347 enum sta_notify_cmd cmd,
1348 struct ieee80211_sta *sta)
1349{
1350 struct ath_softc *sc = hw->priv;
1351 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1352
3d4e20f2 1353 if (!sta->ht_cap.ht_supported)
b25bfda3
MSS
1354 return;
1355
5519541d
FF
1356 switch (cmd) {
1357 case STA_NOTIFY_SLEEP:
1358 an->sleeping = true;
042ec453 1359 ath_tx_aggr_sleep(sta, sc, an);
5519541d
FF
1360 break;
1361 case STA_NOTIFY_AWAKE:
1362 an->sleeping = false;
1363 ath_tx_aggr_wakeup(sc, an);
1364 break;
1365 }
1366}
1367
8a3a3c85
EP
1368static int ath9k_conf_tx(struct ieee80211_hw *hw,
1369 struct ieee80211_vif *vif, u16 queue,
8feceb67 1370 const struct ieee80211_tx_queue_params *params)
f078f209 1371{
9ac58615 1372 struct ath_softc *sc = hw->priv;
c46917bb 1373 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1374 struct ath_txq *txq;
8feceb67 1375 struct ath9k_tx_queue_info qi;
066dae93 1376 int ret = 0;
f078f209 1377
8feceb67
VT
1378 if (queue >= WME_NUM_AC)
1379 return 0;
f078f209 1380
066dae93
FF
1381 txq = sc->tx.txq_map[queue];
1382
96f372c9 1383 ath9k_ps_wakeup(sc);
141b38b6
S
1384 mutex_lock(&sc->mutex);
1385
1ffb0610
S
1386 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1387
8feceb67
VT
1388 qi.tqi_aifs = params->aifs;
1389 qi.tqi_cwmin = params->cw_min;
1390 qi.tqi_cwmax = params->cw_max;
1391 qi.tqi_burstTime = params->txop;
f078f209 1392
d2182b69 1393 ath_dbg(common, CONFIG,
226afe68
JP
1394 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1395 queue, txq->axq_qnum, params->aifs, params->cw_min,
1396 params->cw_max, params->txop);
f078f209 1397
066dae93 1398 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1399 if (ret)
3800276a 1400 ath_err(common, "TXQ Update failed\n");
f078f209 1401
94db2936 1402 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
066dae93 1403 if (queue == WME_AC_BE && !ret)
94db2936
VN
1404 ath_beaconq_config(sc);
1405
141b38b6 1406 mutex_unlock(&sc->mutex);
96f372c9 1407 ath9k_ps_restore(sc);
141b38b6 1408
8feceb67
VT
1409 return ret;
1410}
f078f209 1411
8feceb67
VT
1412static int ath9k_set_key(struct ieee80211_hw *hw,
1413 enum set_key_cmd cmd,
dc822b5d
JB
1414 struct ieee80211_vif *vif,
1415 struct ieee80211_sta *sta,
8feceb67
VT
1416 struct ieee80211_key_conf *key)
1417{
9ac58615 1418 struct ath_softc *sc = hw->priv;
c46917bb 1419 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1420 int ret = 0;
f078f209 1421
3e6109c5 1422 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM
1423 return -ENOSPC;
1424
5bd5e9a6
CYY
1425 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1426 vif->type == NL80211_IFTYPE_MESH_POINT) &&
cfdc9a8b
JM
1427 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1428 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1429 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1430 /*
1431 * For now, disable hw crypto for the RSN IBSS group keys. This
1432 * could be optimized in the future to use a modified key cache
1433 * design to support per-STA RX GTK, but until that gets
1434 * implemented, use of software crypto for group addressed
1435 * frames is a acceptable to allow RSN IBSS to be used.
1436 */
1437 return -EOPNOTSUPP;
1438 }
1439
141b38b6 1440 mutex_lock(&sc->mutex);
3cbb5dd7 1441 ath9k_ps_wakeup(sc);
d2182b69 1442 ath_dbg(common, CONFIG, "Set HW Key\n");
f078f209 1443
8feceb67
VT
1444 switch (cmd) {
1445 case SET_KEY:
93ae2dd2
FF
1446 if (sta)
1447 ath9k_del_ps_key(sc, vif, sta);
1448
040e539e 1449 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1450 if (ret >= 0) {
1451 key->hw_key_idx = ret;
8feceb67
VT
1452 /* push IV and Michael MIC generation to stack */
1453 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1454 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1455 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB
1456 if (sc->sc_ah->sw_mgmt_crypto &&
1457 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 1458 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1459 ret = 0;
8feceb67
VT
1460 }
1461 break;
1462 case DISABLE_KEY:
040e539e 1463 ath_key_delete(common, key);
8feceb67
VT
1464 break;
1465 default:
1466 ret = -EINVAL;
1467 }
f078f209 1468
3cbb5dd7 1469 ath9k_ps_restore(sc);
141b38b6
S
1470 mutex_unlock(&sc->mutex);
1471
8feceb67
VT
1472 return ret;
1473}
4f5ef75b
RM
1474static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1475{
1476 struct ath_softc *sc = data;
1477 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1478 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1479 struct ath_vif *avp = (void *)vif->drv_priv;
07c15a3f 1480 unsigned long flags;
2e5ef459
RM
1481 /*
1482 * Skip iteration if primary station vif's bss info
1483 * was not changed
1484 */
781b14a3 1485 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
2e5ef459
RM
1486 return;
1487
1488 if (bss_conf->assoc) {
781b14a3 1489 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
2e5ef459 1490 avp->primary_sta_vif = true;
4f5ef75b
RM
1491 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1492 common->curaid = bss_conf->aid;
1493 ath9k_hw_write_associd(sc->sc_ah);
d2182b69
JP
1494 ath_dbg(common, CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
1495 bss_conf->aid, common->curbssid);
2e5ef459
RM
1496 ath_beacon_config(sc, vif);
1497 /*
1498 * Request a re-configuration of Beacon related timers
1499 * on the receipt of the first Beacon frame (i.e.,
1500 * after time sync with the AP).
1501 */
07c15a3f 1502 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2e5ef459 1503 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
07c15a3f
SM
1504 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1505
2e5ef459
RM
1506 /* Reset rssi stats */
1507 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1508 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
99e4d43a 1509
01e18918
RM
1510 ath_start_rx_poll(sc, 3);
1511
05c0be2f 1512 if (!common->disable_ani) {
781b14a3 1513 set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
05c0be2f
MSS
1514 ath_start_ani(common);
1515 }
1516
4f5ef75b
RM
1517 }
1518}
1519
1520static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
1521{
1522 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1523 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1524 struct ath_vif *avp = (void *)vif->drv_priv;
1525
2e5ef459
RM
1526 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
1527 return;
1528
4f5ef75b
RM
1529 /* Reconfigure bss info */
1530 if (avp->primary_sta_vif && !bss_conf->assoc) {
d2182b69 1531 ath_dbg(common, CONFIG, "Bss Info DISASSOC %d, bssid %pM\n",
99e4d43a 1532 common->curaid, common->curbssid);
781b14a3
SM
1533 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1534 clear_bit(SC_OP_BEACONS, &sc->sc_flags);
4f5ef75b
RM
1535 avp->primary_sta_vif = false;
1536 memset(common->curbssid, 0, ETH_ALEN);
1537 common->curaid = 0;
1538 }
1539
1540 ieee80211_iterate_active_interfaces_atomic(
1541 sc->hw, ath9k_bss_iter, sc);
1542
1543 /*
1544 * None of station vifs are associated.
1545 * Clear bssid & aid
1546 */
781b14a3 1547 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
4f5ef75b 1548 ath9k_hw_write_associd(sc->sc_ah);
781b14a3 1549 clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
99e4d43a 1550 del_timer_sync(&common->ani.timer);
01e18918 1551 del_timer_sync(&sc->rx_poll_timer);
d2c71c20 1552 memset(&sc->caldata, 0, sizeof(sc->caldata));
99e4d43a 1553 }
4f5ef75b 1554}
f078f209 1555
8feceb67
VT
1556static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1557 struct ieee80211_vif *vif,
1558 struct ieee80211_bss_conf *bss_conf,
1559 u32 changed)
1560{
9ac58615 1561 struct ath_softc *sc = hw->priv;
2d0ddec5 1562 struct ath_hw *ah = sc->sc_ah;
1510718d 1563 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1564 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 1565 int slottime;
f078f209 1566
96f372c9 1567 ath9k_ps_wakeup(sc);
141b38b6
S
1568 mutex_lock(&sc->mutex);
1569
9f61903c 1570 if (changed & BSS_CHANGED_ASSOC) {
4f5ef75b 1571 ath9k_config_bss(sc, vif);
2d0ddec5 1572
d2182b69 1573 ath_dbg(common, CONFIG, "BSSID: %pM aid: 0x%x\n",
226afe68 1574 common->curbssid, common->curaid);
c6089ccc 1575 }
2d0ddec5 1576
2e5ef459
RM
1577 if (changed & BSS_CHANGED_IBSS) {
1578 /* There can be only one vif available */
1579 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1580 common->curaid = bss_conf->aid;
1581 ath9k_hw_write_associd(sc->sc_ah);
1582
1583 if (bss_conf->ibss_joined) {
1584 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
05c0be2f
MSS
1585
1586 if (!common->disable_ani) {
781b14a3 1587 set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
05c0be2f
MSS
1588 ath_start_ani(common);
1589 }
1590
2e5ef459 1591 } else {
781b14a3 1592 clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
2e5ef459 1593 del_timer_sync(&common->ani.timer);
01e18918 1594 del_timer_sync(&sc->rx_poll_timer);
2e5ef459
RM
1595 }
1596 }
1597
ed2578cd
RM
1598 /*
1599 * In case of AP mode, the HW TSF has to be reset
1600 * when the beacon interval changes.
1601 */
1602 if ((changed & BSS_CHANGED_BEACON_INT) &&
1603 (vif->type == NL80211_IFTYPE_AP))
781b14a3 1604 set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
ed2578cd
RM
1605
1606 /* Configure beaconing (AP, IBSS, MESH) */
1607 if (ath9k_uses_beacons(vif->type) &&
1608 ((changed & BSS_CHANGED_BEACON) ||
1609 (changed & BSS_CHANGED_BEACON_ENABLED) ||
1610 (changed & BSS_CHANGED_BEACON_INT))) {
014cf3bb 1611 ath9k_set_beaconing_status(sc, false);
ed2578cd
RM
1612 if (bss_conf->enable_beacon)
1613 ath_beacon_alloc(sc, vif);
1614 else
1615 avp->is_bslot_active = false;
1616 ath_beacon_config(sc, vif);
014cf3bb 1617 ath9k_set_beaconing_status(sc, true);
0005baf4
FF
1618 }
1619
1620 if (changed & BSS_CHANGED_ERP_SLOT) {
1621 if (bss_conf->use_short_slot)
1622 slottime = 9;
1623 else
1624 slottime = 20;
1625 if (vif->type == NL80211_IFTYPE_AP) {
1626 /*
1627 * Defer update, so that connected stations can adjust
1628 * their settings at the same time.
1629 * See beacon.c for more details
1630 */
1631 sc->beacon.slottime = slottime;
1632 sc->beacon.updateslot = UPDATE;
1633 } else {
1634 ah->slottime = slottime;
1635 ath9k_hw_init_global_settings(ah);
1636 }
2d0ddec5
JB
1637 }
1638
141b38b6 1639 mutex_unlock(&sc->mutex);
96f372c9 1640 ath9k_ps_restore(sc);
8feceb67 1641}
f078f209 1642
37a41b4a 1643static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1644{
9ac58615 1645 struct ath_softc *sc = hw->priv;
8feceb67 1646 u64 tsf;
f078f209 1647
141b38b6 1648 mutex_lock(&sc->mutex);
9abbfb27 1649 ath9k_ps_wakeup(sc);
141b38b6 1650 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 1651 ath9k_ps_restore(sc);
141b38b6 1652 mutex_unlock(&sc->mutex);
f078f209 1653
8feceb67
VT
1654 return tsf;
1655}
f078f209 1656
37a41b4a
EP
1657static void ath9k_set_tsf(struct ieee80211_hw *hw,
1658 struct ieee80211_vif *vif,
1659 u64 tsf)
3b5d665b 1660{
9ac58615 1661 struct ath_softc *sc = hw->priv;
3b5d665b 1662
141b38b6 1663 mutex_lock(&sc->mutex);
9abbfb27 1664 ath9k_ps_wakeup(sc);
141b38b6 1665 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 1666 ath9k_ps_restore(sc);
141b38b6 1667 mutex_unlock(&sc->mutex);
3b5d665b
AF
1668}
1669
37a41b4a 1670static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1671{
9ac58615 1672 struct ath_softc *sc = hw->priv;
c83be688 1673
141b38b6 1674 mutex_lock(&sc->mutex);
21526d57
LR
1675
1676 ath9k_ps_wakeup(sc);
141b38b6 1677 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
1678 ath9k_ps_restore(sc);
1679
141b38b6 1680 mutex_unlock(&sc->mutex);
8feceb67 1681}
f078f209 1682
8feceb67 1683static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 1684 struct ieee80211_vif *vif,
141b38b6
S
1685 enum ieee80211_ampdu_mlme_action action,
1686 struct ieee80211_sta *sta,
0b01f030 1687 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 1688{
9ac58615 1689 struct ath_softc *sc = hw->priv;
8feceb67 1690 int ret = 0;
f078f209 1691
85ad181e
JB
1692 local_bh_disable();
1693
8feceb67
VT
1694 switch (action) {
1695 case IEEE80211_AMPDU_RX_START:
8feceb67
VT
1696 break;
1697 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
1698 break;
1699 case IEEE80211_AMPDU_TX_START:
8b685ba9 1700 ath9k_ps_wakeup(sc);
231c3a1f
FF
1701 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1702 if (!ret)
1703 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1704 ath9k_ps_restore(sc);
8feceb67
VT
1705 break;
1706 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 1707 ath9k_ps_wakeup(sc);
f83da965 1708 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 1709 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1710 ath9k_ps_restore(sc);
8feceb67 1711 break;
b1720231 1712 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 1713 ath9k_ps_wakeup(sc);
8469cdef 1714 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 1715 ath9k_ps_restore(sc);
8469cdef 1716 break;
8feceb67 1717 default:
3800276a 1718 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT
1719 }
1720
85ad181e
JB
1721 local_bh_enable();
1722
8feceb67 1723 return ret;
f078f209
LR
1724}
1725
62dad5b0
BP
1726static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1727 struct survey_info *survey)
1728{
9ac58615 1729 struct ath_softc *sc = hw->priv;
3430098a 1730 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 1731 struct ieee80211_supported_band *sband;
3430098a
FF
1732 struct ieee80211_channel *chan;
1733 unsigned long flags;
1734 int pos;
1735
1736 spin_lock_irqsave(&common->cc_lock, flags);
1737 if (idx == 0)
1738 ath_update_survey_stats(sc);
39162dbe
FF
1739
1740 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1741 if (sband && idx >= sband->n_channels) {
1742 idx -= sband->n_channels;
1743 sband = NULL;
1744 }
62dad5b0 1745
39162dbe
FF
1746 if (!sband)
1747 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 1748
3430098a
FF
1749 if (!sband || idx >= sband->n_channels) {
1750 spin_unlock_irqrestore(&common->cc_lock, flags);
1751 return -ENOENT;
4f1a5a4b 1752 }
62dad5b0 1753
3430098a
FF
1754 chan = &sband->channels[idx];
1755 pos = chan->hw_value;
1756 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1757 survey->channel = chan;
1758 spin_unlock_irqrestore(&common->cc_lock, flags);
1759
62dad5b0
BP
1760 return 0;
1761}
1762
e239d859
FF
1763static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
1764{
9ac58615 1765 struct ath_softc *sc = hw->priv;
e239d859
FF
1766 struct ath_hw *ah = sc->sc_ah;
1767
1768 mutex_lock(&sc->mutex);
1769 ah->coverage_class = coverage_class;
8b2a3827
MSS
1770
1771 ath9k_ps_wakeup(sc);
e239d859 1772 ath9k_hw_init_global_settings(ah);
8b2a3827
MSS
1773 ath9k_ps_restore(sc);
1774
e239d859
FF
1775 mutex_unlock(&sc->mutex);
1776}
1777
69081624
VT
1778static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
1779{
69081624 1780 struct ath_softc *sc = hw->priv;
99aa55b6
MSS
1781 struct ath_hw *ah = sc->sc_ah;
1782 struct ath_common *common = ath9k_hw_common(ah);
86271e46
FF
1783 int timeout = 200; /* ms */
1784 int i, j;
2f6fc351 1785 bool drain_txq;
69081624
VT
1786
1787 mutex_lock(&sc->mutex);
69081624
VT
1788 cancel_delayed_work_sync(&sc->tx_complete_work);
1789
6a6b3f3e 1790 if (ah->ah_flags & AH_UNPLUGGED) {
d2182b69 1791 ath_dbg(common, ANY, "Device has been unplugged!\n");
6a6b3f3e
MSS
1792 mutex_unlock(&sc->mutex);
1793 return;
1794 }
1795
781b14a3 1796 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
d2182b69 1797 ath_dbg(common, ANY, "Device not present\n");
99aa55b6
MSS
1798 mutex_unlock(&sc->mutex);
1799 return;
1800 }
1801
86271e46 1802 for (j = 0; j < timeout; j++) {
108697c4 1803 bool npend = false;
86271e46
FF
1804
1805 if (j)
1806 usleep_range(1000, 2000);
69081624 1807
86271e46
FF
1808 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1809 if (!ATH_TXQ_SETUP(sc, i))
1810 continue;
1811
108697c4
MSS
1812 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1813
1814 if (npend)
1815 break;
69081624 1816 }
86271e46
FF
1817
1818 if (!npend)
9df0d6a2 1819 break;
69081624
VT
1820 }
1821
9df0d6a2
FF
1822 if (drop) {
1823 ath9k_ps_wakeup(sc);
1824 spin_lock_bh(&sc->sc_pcu_lock);
1825 drain_txq = ath_drain_all_txq(sc, false);
1826 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440 1827
9df0d6a2
FF
1828 if (!drain_txq)
1829 ath_reset(sc, false);
9adcf440 1830
9df0d6a2
FF
1831 ath9k_ps_restore(sc);
1832 ieee80211_wake_queues(hw);
1833 }
d78f4b3e 1834
69081624
VT
1835 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
1836 mutex_unlock(&sc->mutex);
1837}
1838
15b91e83
VN
1839static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
1840{
1841 struct ath_softc *sc = hw->priv;
1842 int i;
1843
1844 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1845 if (!ATH_TXQ_SETUP(sc, i))
1846 continue;
1847
1848 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
1849 return true;
1850 }
1851 return false;
1852}
1853
5595f119 1854static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
ba4903f9
FF
1855{
1856 struct ath_softc *sc = hw->priv;
1857 struct ath_hw *ah = sc->sc_ah;
1858 struct ieee80211_vif *vif;
1859 struct ath_vif *avp;
1860 struct ath_buf *bf;
1861 struct ath_tx_status ts;
4286df60 1862 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
ba4903f9
FF
1863 int status;
1864
1865 vif = sc->beacon.bslot[0];
1866 if (!vif)
1867 return 0;
1868
1869 avp = (void *)vif->drv_priv;
1870 if (!avp->is_bslot_active)
1871 return 0;
1872
4286df60 1873 if (!sc->beacon.tx_processed && !edma) {
ba4903f9
FF
1874 tasklet_disable(&sc->bcon_tasklet);
1875
1876 bf = avp->av_bcbuf;
1877 if (!bf || !bf->bf_mpdu)
1878 goto skip;
1879
1880 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
1881 if (status == -EINPROGRESS)
1882 goto skip;
1883
1884 sc->beacon.tx_processed = true;
1885 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
1886
1887skip:
1888 tasklet_enable(&sc->bcon_tasklet);
1889 }
1890
1891 return sc->beacon.tx_last;
1892}
1893
52c94f41
MSS
1894static int ath9k_get_stats(struct ieee80211_hw *hw,
1895 struct ieee80211_low_level_stats *stats)
1896{
1897 struct ath_softc *sc = hw->priv;
1898 struct ath_hw *ah = sc->sc_ah;
1899 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
1900
1901 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
1902 stats->dot11RTSFailureCount = mib_stats->rts_bad;
1903 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
1904 stats->dot11RTSSuccessCount = mib_stats->rts_good;
1905 return 0;
1906}
1907
43c35284
FF
1908static u32 fill_chainmask(u32 cap, u32 new)
1909{
1910 u32 filled = 0;
1911 int i;
1912
1913 for (i = 0; cap && new; i++, cap >>= 1) {
1914 if (!(cap & BIT(0)))
1915 continue;
1916
1917 if (new & BIT(0))
1918 filled |= BIT(i);
1919
1920 new >>= 1;
1921 }
1922
1923 return filled;
1924}
1925
1926static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
1927{
1928 struct ath_softc *sc = hw->priv;
1929 struct ath_hw *ah = sc->sc_ah;
1930
1931 if (!rx_ant || !tx_ant)
1932 return -EINVAL;
1933
1934 sc->ant_rx = rx_ant;
1935 sc->ant_tx = tx_ant;
1936
1937 if (ah->caps.rx_chainmask == 1)
1938 return 0;
1939
1940 /* AR9100 runs into calibration issues if not all rx chains are enabled */
1941 if (AR_SREV_9100(ah))
1942 ah->rxchainmask = 0x7;
1943 else
1944 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
1945
1946 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
1947 ath9k_reload_chainmask_settings(sc);
1948
1949 return 0;
1950}
1951
1952static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
1953{
1954 struct ath_softc *sc = hw->priv;
1955
1956 *tx_ant = sc->ant_tx;
1957 *rx_ant = sc->ant_rx;
1958 return 0;
1959}
1960
b90bd9d1
BG
1961#ifdef CONFIG_ATH9K_DEBUGFS
1962
1963/* Ethtool support for get-stats */
1964
1965#define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
1966static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
1967 "tx_pkts_nic",
1968 "tx_bytes_nic",
1969 "rx_pkts_nic",
1970 "rx_bytes_nic",
1971 AMKSTR(d_tx_pkts),
1972 AMKSTR(d_tx_bytes),
1973 AMKSTR(d_tx_mpdus_queued),
1974 AMKSTR(d_tx_mpdus_completed),
1975 AMKSTR(d_tx_mpdu_xretries),
1976 AMKSTR(d_tx_aggregates),
1977 AMKSTR(d_tx_ampdus_queued_hw),
1978 AMKSTR(d_tx_ampdus_queued_sw),
1979 AMKSTR(d_tx_ampdus_completed),
1980 AMKSTR(d_tx_ampdu_retries),
1981 AMKSTR(d_tx_ampdu_xretries),
1982 AMKSTR(d_tx_fifo_underrun),
1983 AMKSTR(d_tx_op_exceeded),
1984 AMKSTR(d_tx_timer_expiry),
1985 AMKSTR(d_tx_desc_cfg_err),
1986 AMKSTR(d_tx_data_underrun),
1987 AMKSTR(d_tx_delim_underrun),
1988
1989 "d_rx_decrypt_crc_err",
1990 "d_rx_phy_err",
1991 "d_rx_mic_err",
1992 "d_rx_pre_delim_crc_err",
1993 "d_rx_post_delim_crc_err",
1994 "d_rx_decrypt_busy_err",
1995
1996 "d_rx_phyerr_radar",
1997 "d_rx_phyerr_ofdm_timing",
1998 "d_rx_phyerr_cck_timing",
1999
2000};
2001#define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
2002
2003static void ath9k_get_et_strings(struct ieee80211_hw *hw,
2004 struct ieee80211_vif *vif,
2005 u32 sset, u8 *data)
2006{
2007 if (sset == ETH_SS_STATS)
2008 memcpy(data, *ath9k_gstrings_stats,
2009 sizeof(ath9k_gstrings_stats));
2010}
2011
2012static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
2013 struct ieee80211_vif *vif, int sset)
2014{
2015 if (sset == ETH_SS_STATS)
2016 return ATH9K_SSTATS_LEN;
2017 return 0;
2018}
2019
2020#define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
2021#define AWDATA(elem) \
2022 do { \
2023 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
2024 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
2025 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
2026 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
2027 } while (0)
2028
2029#define AWDATA_RX(elem) \
2030 do { \
2031 data[i++] = sc->debug.stats.rxstats.elem; \
2032 } while (0)
2033
2034static void ath9k_get_et_stats(struct ieee80211_hw *hw,
2035 struct ieee80211_vif *vif,
2036 struct ethtool_stats *stats, u64 *data)
2037{
2038 struct ath_softc *sc = hw->priv;
2039 int i = 0;
2040
2041 data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
2042 sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
2043 sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
2044 sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
2045 data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
2046 sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
2047 sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
2048 sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
2049 AWDATA_RX(rx_pkts_all);
2050 AWDATA_RX(rx_bytes_all);
2051
2052 AWDATA(tx_pkts_all);
2053 AWDATA(tx_bytes_all);
2054 AWDATA(queued);
2055 AWDATA(completed);
2056 AWDATA(xretries);
2057 AWDATA(a_aggr);
2058 AWDATA(a_queued_hw);
2059 AWDATA(a_queued_sw);
2060 AWDATA(a_completed);
2061 AWDATA(a_retries);
2062 AWDATA(a_xretries);
2063 AWDATA(fifo_underrun);
2064 AWDATA(xtxop);
2065 AWDATA(timer_exp);
2066 AWDATA(desc_cfg_err);
2067 AWDATA(data_underrun);
2068 AWDATA(delim_underrun);
2069
2070 AWDATA_RX(decrypt_crc_err);
2071 AWDATA_RX(phy_err);
2072 AWDATA_RX(mic_err);
2073 AWDATA_RX(pre_delim_crc_err);
2074 AWDATA_RX(post_delim_crc_err);
2075 AWDATA_RX(decrypt_busy_err);
2076
2077 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
2078 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
2079 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
2080
2081 WARN_ON(i != ATH9K_SSTATS_LEN);
2082}
2083
2084/* End of ethtool get-stats functions */
2085
2086#endif
2087
2088
b11e640a
MSS
2089#ifdef CONFIG_PM_SLEEP
2090
2091static void ath9k_wow_map_triggers(struct ath_softc *sc,
2092 struct cfg80211_wowlan *wowlan,
2093 u32 *wow_triggers)
2094{
2095 if (wowlan->disconnect)
2096 *wow_triggers |= AH_WOW_LINK_CHANGE |
2097 AH_WOW_BEACON_MISS;
2098 if (wowlan->magic_pkt)
2099 *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
2100
2101 if (wowlan->n_patterns)
2102 *wow_triggers |= AH_WOW_USER_PATTERN_EN;
2103
2104 sc->wow_enabled = *wow_triggers;
2105
2106}
2107
2108static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
2109{
2110 struct ath_hw *ah = sc->sc_ah;
2111 struct ath_common *common = ath9k_hw_common(ah);
2112 struct ath9k_hw_capabilities *pcaps = &ah->caps;
2113 int pattern_count = 0;
2114 int i, byte_cnt;
2115 u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
2116 u8 dis_deauth_mask[MAX_PATTERN_SIZE];
2117
2118 memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
2119 memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
2120
2121 /*
2122 * Create Dissassociate / Deauthenticate packet filter
2123 *
2124 * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
2125 * +--------------+----------+---------+--------+--------+----
2126 * + Frame Control+ Duration + DA + SA + BSSID +
2127 * +--------------+----------+---------+--------+--------+----
2128 *
2129 * The above is the management frame format for disassociate/
2130 * deauthenticate pattern, from this we need to match the first byte
2131 * of 'Frame Control' and DA, SA, and BSSID fields
2132 * (skipping 2nd byte of FC and Duration feild.
2133 *
2134 * Disassociate pattern
2135 * --------------------
2136 * Frame control = 00 00 1010
2137 * DA, SA, BSSID = x:x:x:x:x:x
2138 * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2139 * | x:x:x:x:x:x -- 22 bytes
2140 *
2141 * Deauthenticate pattern
2142 * ----------------------
2143 * Frame control = 00 00 1100
2144 * DA, SA, BSSID = x:x:x:x:x:x
2145 * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2146 * | x:x:x:x:x:x -- 22 bytes
2147 */
2148
2149 /* Create Disassociate Pattern first */
2150
2151 byte_cnt = 0;
2152
2153 /* Fill out the mask with all FF's */
2154
2155 for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
2156 dis_deauth_mask[i] = 0xff;
2157
2158 /* copy the first byte of frame control field */
2159 dis_deauth_pattern[byte_cnt] = 0xa0;
2160 byte_cnt++;
2161
2162 /* skip 2nd byte of frame control and Duration field */
2163 byte_cnt += 3;
2164
2165 /*
2166 * need not match the destination mac address, it can be a broadcast
2167 * mac address or an unicast to this station
2168 */
2169 byte_cnt += 6;
2170
2171 /* copy the source mac address */
2172 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2173
2174 byte_cnt += 6;
2175
2176 /* copy the bssid, its same as the source mac address */
2177
2178 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2179
2180 /* Create Disassociate pattern mask */
2181
2182 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
2183
2184 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
2185 /*
2186 * for AR9280, because of hardware limitation, the
2187 * first 4 bytes have to be matched for all patterns.
2188 * the mask for disassociation and de-auth pattern
2189 * matching need to enable the first 4 bytes.
2190 * also the duration field needs to be filled.
2191 */
2192 dis_deauth_mask[0] = 0xf0;
2193
2194 /*
2195 * fill in duration field
2196 FIXME: what is the exact value ?
2197 */
2198 dis_deauth_pattern[2] = 0xff;
2199 dis_deauth_pattern[3] = 0xff;
2200 } else {
2201 dis_deauth_mask[0] = 0xfe;
2202 }
2203
2204 dis_deauth_mask[1] = 0x03;
2205 dis_deauth_mask[2] = 0xc0;
2206 } else {
2207 dis_deauth_mask[0] = 0xef;
2208 dis_deauth_mask[1] = 0x3f;
2209 dis_deauth_mask[2] = 0x00;
2210 dis_deauth_mask[3] = 0xfc;
2211 }
2212
2213 ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
2214
2215 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2216 pattern_count, byte_cnt);
2217
2218 pattern_count++;
2219 /*
2220 * for de-authenticate pattern, only the first byte of the frame
2221 * control field gets changed from 0xA0 to 0xC0
2222 */
2223 dis_deauth_pattern[0] = 0xC0;
2224
2225 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2226 pattern_count, byte_cnt);
2227
2228}
2229
2230static void ath9k_wow_add_pattern(struct ath_softc *sc,
2231 struct cfg80211_wowlan *wowlan)
2232{
2233 struct ath_hw *ah = sc->sc_ah;
2234 struct ath9k_wow_pattern *wow_pattern = NULL;
2235 struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
2236 int mask_len;
2237 s8 i = 0;
2238
2239 if (!wowlan->n_patterns)
2240 return;
2241
2242 /*
2243 * Add the new user configured patterns
2244 */
2245 for (i = 0; i < wowlan->n_patterns; i++) {
2246
2247 wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
2248
2249 if (!wow_pattern)
2250 return;
2251
2252 /*
2253 * TODO: convert the generic user space pattern to
2254 * appropriate chip specific/802.11 pattern.
2255 */
2256
2257 mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
2258 memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
2259 memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
2260 memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
2261 patterns[i].pattern_len);
2262 memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
2263 wow_pattern->pattern_len = patterns[i].pattern_len;
2264
2265 /*
2266 * just need to take care of deauth and disssoc pattern,
2267 * make sure we don't overwrite them.
2268 */
2269
2270 ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
2271 wow_pattern->mask_bytes,
2272 i + 2,
2273 wow_pattern->pattern_len);
2274 kfree(wow_pattern);
2275
2276 }
2277
2278}
2279
2280static int ath9k_suspend(struct ieee80211_hw *hw,
2281 struct cfg80211_wowlan *wowlan)
2282{
2283 struct ath_softc *sc = hw->priv;
2284 struct ath_hw *ah = sc->sc_ah;
2285 struct ath_common *common = ath9k_hw_common(ah);
2286 u32 wow_triggers_enabled = 0;
2287 int ret = 0;
2288
2289 mutex_lock(&sc->mutex);
2290
2291 ath_cancel_work(sc);
2292 del_timer_sync(&common->ani.timer);
2293 del_timer_sync(&sc->rx_poll_timer);
2294
2295 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
2296 ath_dbg(common, ANY, "Device not present\n");
2297 ret = -EINVAL;
2298 goto fail_wow;
2299 }
2300
2301 if (WARN_ON(!wowlan)) {
2302 ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
2303 ret = -EINVAL;
2304 goto fail_wow;
2305 }
2306
2307 if (!device_can_wakeup(sc->dev)) {
2308 ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
2309 ret = 1;
2310 goto fail_wow;
2311 }
2312
2313 /*
2314 * none of the sta vifs are associated
2315 * and we are not currently handling multivif
2316 * cases, for instance we have to seperately
2317 * configure 'keep alive frame' for each
2318 * STA.
2319 */
2320
2321 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
2322 ath_dbg(common, WOW, "None of the STA vifs are associated\n");
2323 ret = 1;
2324 goto fail_wow;
2325 }
2326
2327 if (sc->nvifs > 1) {
2328 ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
2329 ret = 1;
2330 goto fail_wow;
2331 }
2332
2333 ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
2334
2335 ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
2336 wow_triggers_enabled);
2337
2338 ath9k_ps_wakeup(sc);
2339
2340 ath9k_stop_btcoex(sc);
2341
2342 /*
2343 * Enable wake up on recieving disassoc/deauth
2344 * frame by default.
2345 */
2346 ath9k_wow_add_disassoc_deauth_pattern(sc);
2347
2348 if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
2349 ath9k_wow_add_pattern(sc, wowlan);
2350
2351 spin_lock_bh(&sc->sc_pcu_lock);
2352 /*
2353 * To avoid false wake, we enable beacon miss interrupt only
2354 * when we go to sleep. We save the current interrupt mask
2355 * so we can restore it after the system wakes up
2356 */
2357 sc->wow_intr_before_sleep = ah->imask;
2358 ah->imask &= ~ATH9K_INT_GLOBAL;
2359 ath9k_hw_disable_interrupts(ah);
2360 ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
2361 ath9k_hw_set_interrupts(ah);
2362 ath9k_hw_enable_interrupts(ah);
2363
2364 spin_unlock_bh(&sc->sc_pcu_lock);
2365
2366 /*
2367 * we can now sync irq and kill any running tasklets, since we already
2368 * disabled interrupts and not holding a spin lock
2369 */
2370 synchronize_irq(sc->irq);
2371 tasklet_kill(&sc->intr_tq);
2372
2373 ath9k_hw_wow_enable(ah, wow_triggers_enabled);
2374
2375 ath9k_ps_restore(sc);
2376 ath_dbg(common, ANY, "WoW enabled in ath9k\n");
2377 atomic_inc(&sc->wow_sleep_proc_intr);
2378
2379fail_wow:
2380 mutex_unlock(&sc->mutex);
2381 return ret;
2382}
2383
2384static int ath9k_resume(struct ieee80211_hw *hw)
2385{
2386 struct ath_softc *sc = hw->priv;
2387 struct ath_hw *ah = sc->sc_ah;
2388 struct ath_common *common = ath9k_hw_common(ah);
2389 u32 wow_status;
2390
2391 mutex_lock(&sc->mutex);
2392
2393 ath9k_ps_wakeup(sc);
2394
2395 spin_lock_bh(&sc->sc_pcu_lock);
2396
2397 ath9k_hw_disable_interrupts(ah);
2398 ah->imask = sc->wow_intr_before_sleep;
2399 ath9k_hw_set_interrupts(ah);
2400 ath9k_hw_enable_interrupts(ah);
2401
2402 spin_unlock_bh(&sc->sc_pcu_lock);
2403
2404 wow_status = ath9k_hw_wow_wakeup(ah);
2405
2406 if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
2407 /*
2408 * some devices may not pick beacon miss
2409 * as the reason they woke up so we add
2410 * that here for that shortcoming.
2411 */
2412 wow_status |= AH_WOW_BEACON_MISS;
2413 atomic_dec(&sc->wow_got_bmiss_intr);
2414 ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
2415 }
2416
2417 atomic_dec(&sc->wow_sleep_proc_intr);
2418
2419 if (wow_status) {
2420 ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
2421 ath9k_hw_wow_event_to_string(wow_status), wow_status);
2422 }
2423
2424 ath_restart_work(sc);
2425 ath9k_start_btcoex(sc);
2426
2427 ath9k_ps_restore(sc);
2428 mutex_unlock(&sc->mutex);
2429
2430 return 0;
2431}
2432
2433static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
2434{
2435 struct ath_softc *sc = hw->priv;
2436
2437 mutex_lock(&sc->mutex);
2438 device_init_wakeup(sc->dev, 1);
2439 device_set_wakeup_enable(sc->dev, enabled);
2440 mutex_unlock(&sc->mutex);
2441}
2442
2443#endif
2444
6baff7f9 2445struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2446 .tx = ath9k_tx,
2447 .start = ath9k_start,
2448 .stop = ath9k_stop,
2449 .add_interface = ath9k_add_interface,
6b3b991d 2450 .change_interface = ath9k_change_interface,
8feceb67
VT
2451 .remove_interface = ath9k_remove_interface,
2452 .config = ath9k_config,
8feceb67 2453 .configure_filter = ath9k_configure_filter,
4ca77860
JB
2454 .sta_add = ath9k_sta_add,
2455 .sta_remove = ath9k_sta_remove,
5519541d 2456 .sta_notify = ath9k_sta_notify,
8feceb67 2457 .conf_tx = ath9k_conf_tx,
8feceb67 2458 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2459 .set_key = ath9k_set_key,
8feceb67 2460 .get_tsf = ath9k_get_tsf,
3b5d665b 2461 .set_tsf = ath9k_set_tsf,
8feceb67 2462 .reset_tsf = ath9k_reset_tsf,
4233df6b 2463 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2464 .get_survey = ath9k_get_survey,
3b319aae 2465 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2466 .set_coverage_class = ath9k_set_coverage_class,
69081624 2467 .flush = ath9k_flush,
15b91e83 2468 .tx_frames_pending = ath9k_tx_frames_pending,
52c94f41
MSS
2469 .tx_last_beacon = ath9k_tx_last_beacon,
2470 .get_stats = ath9k_get_stats,
43c35284
FF
2471 .set_antenna = ath9k_set_antenna,
2472 .get_antenna = ath9k_get_antenna,
b90bd9d1 2473
b11e640a
MSS
2474#ifdef CONFIG_PM_SLEEP
2475 .suspend = ath9k_suspend,
2476 .resume = ath9k_resume,
2477 .set_wakeup = ath9k_set_wakeup,
2478#endif
2479
b90bd9d1
BG
2480#ifdef CONFIG_ATH9K_DEBUGFS
2481 .get_et_sset_count = ath9k_get_et_sset_count,
2482 .get_et_stats = ath9k_get_et_stats,
2483 .get_et_strings = ath9k_get_et_strings,
2484#endif
8feceb67 2485};
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