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ath9k: Move P2P functions to channel.c
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
313eb87f 22u8 ath9k_parse_mpdudensity(u8 mpdudensity)
ff37e337
S		 23{
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55}
56
69081624
VT		 57static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
58{
59 bool pending = false;
60
61 spin_lock_bh(&txq->axq_lock);
62
0453531e 63 if (txq->axq_depth)
69081624 64 pending = true;
69081624 65
0453531e
FF		 66 if (txq->mac80211_qnum >= 0) {
67 struct list_head *list;
68
69 list = &sc->cur_chan->acq[txq->mac80211_qnum];
70 if (!list_empty(list))
71 pending = true;
72 }
69081624
VT		 73 spin_unlock_bh(&txq->axq_lock);
74 return pending;
75}
76
6d79cb4c 77static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR		 78{
79 unsigned long flags;
80 bool ret;
81
9ecdef4b
LR		 82 spin_lock_irqsave(&sc->sc_pm_lock, flags);
83 ret = ath9k_hw_setpower(sc->sc_ah, mode);
84 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR		 85
86 return ret;
87}
88
bf3dac5a
FF		 89void ath_ps_full_sleep(unsigned long data)
90{
91 struct ath_softc *sc = (struct ath_softc *) data;
92 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
93 bool reset;
94
95 spin_lock(&common->cc_lock);
96 ath_hw_cycle_counters_update(common);
97 spin_unlock(&common->cc_lock);
98
99 ath9k_hw_setrxabort(sc->sc_ah, 1);
100 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
101
102 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
103}
104
a91d75ae
LR		 105void ath9k_ps_wakeup(struct ath_softc *sc)
106{
898c914a 107 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 108 unsigned long flags;
fbb078fc 109 enum ath9k_power_mode power_mode;
a91d75ae
LR		 110
111 spin_lock_irqsave(&sc->sc_pm_lock, flags);
112 if (++sc->ps_usecount != 1)
113 goto unlock;
114
bf3dac5a 115 del_timer_sync(&sc->sleep_timer);
fbb078fc 116 power_mode = sc->sc_ah->power_mode;
9ecdef4b 117 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 118
898c914a
FF		 119 /*
120 * While the hardware is asleep, the cycle counters contain no
121 * useful data. Better clear them now so that they don't mess up
122 * survey data results.
123 */
fbb078fc
FF		 124 if (power_mode != ATH9K_PM_AWAKE) {
125 spin_lock(&common->cc_lock);
126 ath_hw_cycle_counters_update(common);
127 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
c9ae6ab4 128 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
fbb078fc
FF		 129 spin_unlock(&common->cc_lock);
130 }
898c914a 131
a91d75ae
LR		 132 unlock:
133 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
134}
135
136void ath9k_ps_restore(struct ath_softc *sc)
137{
898c914a 138 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
c6c539f0 139 enum ath9k_power_mode mode;
a91d75ae
LR		 140 unsigned long flags;
141
142 spin_lock_irqsave(&sc->sc_pm_lock, flags);
143 if (--sc->ps_usecount != 0)
144 goto unlock;
145
ad128860 146 if (sc->ps_idle) {
bf3dac5a
FF		 147 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
148 goto unlock;
149 }
150
151 if (sc->ps_enabled &&
ad128860
SM		 152 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
153 PS_WAIT_FOR_CAB |
154 PS_WAIT_FOR_PSPOLL_DATA |
424749c7
RM		 155 PS_WAIT_FOR_TX_ACK |
156 PS_WAIT_FOR_ANI))) {
c6c539f0 157 mode = ATH9K_PM_NETWORK_SLEEP;
08d4df41
RM		 158 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
159 ath9k_btcoex_stop_gen_timer(sc);
ad128860 160 } else {
c6c539f0 161 goto unlock;
ad128860 162 }
c6c539f0
FF		 163
164 spin_lock(&common->cc_lock);
165 ath_hw_cycle_counters_update(common);
166 spin_unlock(&common->cc_lock);
167
1a8f0d39 168 ath9k_hw_setpower(sc->sc_ah, mode);
a91d75ae
LR		 169
170 unlock:
171 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
172}
173
9adcf440 174static void __ath_cancel_work(struct ath_softc *sc)
ff37e337 175{
5ee08656 176 cancel_work_sync(&sc->paprd_work);
5ee08656 177 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 178 cancel_delayed_work_sync(&sc->hw_pll_work);
fad29cd2 179
bf52592f 180#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
fad29cd2
SM		 181 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
182 cancel_work_sync(&sc->mci_work);
bf52592f 183#endif
9adcf440 184}
5ee08656 185
e60001e7 186void ath_cancel_work(struct ath_softc *sc)
9adcf440
FF		 187{
188 __ath_cancel_work(sc);
189 cancel_work_sync(&sc->hw_reset_work);
190}
3cbb5dd7 191
e60001e7 192void ath_restart_work(struct ath_softc *sc)
af68abad 193{
af68abad
SM		 194 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
195
19c36160 196 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
af68abad
SM		 197 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
198 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
199
da0d45f7 200 ath_start_ani(sc);
af68abad
SM		 201}
202
9ebea382 203static bool ath_prepare_reset(struct ath_softc *sc)
9adcf440
FF		 204{
205 struct ath_hw *ah = sc->sc_ah;
ceea2a51 206 bool ret = true;
6a6733f2 207
9adcf440 208 ieee80211_stop_queues(sc->hw);
da0d45f7 209 ath_stop_ani(sc);
9adcf440 210 ath9k_hw_disable_interrupts(ah);
8b3f4616 211
1381559b 212 if (!ath_drain_all_txq(sc))
9adcf440 213 ret = false;
c0d7c7af 214
0a62acb1 215 if (!ath_stoprecv(sc))
ceea2a51
FF		 216 ret = false;
217
9adcf440
FF		 218 return ret;
219}
ff37e337 220
9adcf440
FF		 221static bool ath_complete_reset(struct ath_softc *sc, bool start)
222{
223 struct ath_hw *ah = sc->sc_ah;
224 struct ath_common *common = ath9k_hw_common(ah);
196fb860 225 unsigned long flags;
3ad9c386 226 int i;
c0d7c7af 227
c0d7c7af 228 if (ath_startrecv(sc) != 0) {
3800276a 229 ath_err(common, "Unable to restart recv logic\n");
9adcf440 230 return false;
c0d7c7af
LR		 231 }
232
5048e8c3 233 ath9k_cmn_update_txpow(ah, sc->curtxpow,
bc7e1be7 234 sc->cur_chan->txpower, &sc->curtxpow);
b74713d0 235
eefa01dd 236 clear_bit(ATH_OP_HW_RESET, &common->op_flags);
9a9c4fbc 237 ath9k_calculate_summary_state(sc, sc->cur_chan);
3989279c 238
fbbcd146 239 if (!sc->cur_chan->offchannel && start) {
8d7e09dd
FF		 240 /* restore per chanctx TSF timer */
241 if (sc->cur_chan->tsf_val) {
242 u32 offset;
243
244 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
245 NULL);
246 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
247 }
248
249
eefa01dd 250 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
196fb860
SM		 251 goto work;
252
196fb860 253 if (ah->opmode == NL80211_IFTYPE_STATION &&
eefa01dd 254 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
196fb860
SM		 255 spin_lock_irqsave(&sc->sc_pm_lock, flags);
256 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
257 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
a6768280
SM		 258 } else {
259 ath9k_set_beacon(sc);
196fb860
SM		 260 }
261 work:
af68abad 262 ath_restart_work(sc);
0453531e 263 ath_txq_schedule_all(sc);
5ee08656
FF		 264 }
265
071aa9a8 266 sc->gtt_cnt = 0;
9a9c4fbc
RM		 267
268 ath9k_hw_set_interrupts(ah);
269 ath9k_hw_enable_interrupts(ah);
270
3ad9c386
RM		 271 if (!ath9k_use_chanctx)
272 ieee80211_wake_queues(sc->hw);
273 else {
274 if (sc->cur_chan == &sc->offchannel.chan)
275 ieee80211_wake_queue(sc->hw,
276 sc->hw->offchannel_tx_hw_queue);
277 else {
278 for (i = 0; i < IEEE80211_NUM_ACS; i++)
279 ieee80211_wake_queue(sc->hw,
280 sc->cur_chan->hw_queue_base + i);
281 }
282 if (ah->opmode == NL80211_IFTYPE_AP)
283 ieee80211_wake_queue(sc->hw, sc->hw->queues - 2);
284 }
9adcf440 285
d463af4a
FF		 286 ath9k_p2p_ps_timer(sc);
287
9adcf440
FF		 288 return true;
289}
290
fbbcd146 291int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
9adcf440
FF		 292{
293 struct ath_hw *ah = sc->sc_ah;
294 struct ath_common *common = ath9k_hw_common(ah);
295 struct ath9k_hw_cal_data *caldata = NULL;
296 bool fastcc = true;
9adcf440
FF		 297 int r;
298
299 __ath_cancel_work(sc);
300
4668cce5 301 tasklet_disable(&sc->intr_tq);
9adcf440 302 spin_lock_bh(&sc->sc_pcu_lock);
92460412 303
fbbcd146 304 if (!sc->cur_chan->offchannel) {
9adcf440 305 fastcc = false;
b01459e8 306 caldata = &sc->cur_chan->caldata;
9adcf440
FF		 307 }
308
309 if (!hchan) {
310 fastcc = false;
9adcf440
FF		 311 hchan = ah->curchan;
312 }
313
9ebea382 314 if (!ath_prepare_reset(sc))
9adcf440
FF		 315 fastcc = false;
316
d6067f0e
RM		 317 spin_lock_bh(&sc->chan_lock);
318 sc->cur_chandef = sc->cur_chan->chandef;
319 spin_unlock_bh(&sc->chan_lock);
bff11766 320
d2182b69 321 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
feced201 322 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
9adcf440
FF		 323
324 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
325 if (r) {
326 ath_err(common,
327 "Unable to reset channel, reset status %d\n", r);
f50b1cd3
RS		 328
329 ath9k_hw_enable_interrupts(ah);
330 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
331
9adcf440
FF		 332 goto out;
333 }
334
e82cb03f 335 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
fbbcd146 336 sc->cur_chan->offchannel)
e82cb03f
RM		 337 ath9k_mci_set_txpower(sc, true, false);
338
9adcf440
FF		 339 if (!ath_complete_reset(sc, true))
340 r = -EIO;
341
342out:
6a6733f2 343 spin_unlock_bh(&sc->sc_pcu_lock);
4668cce5
FF		 344 tasklet_enable(&sc->intr_tq);
345
9adcf440
FF		 346 return r;
347}
348
7e1e3864
BG		 349static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
350 struct ieee80211_vif *vif)
ff37e337
S		 351{
352 struct ath_node *an;
ff37e337
S		 353 an = (struct ath_node *)sta->drv_priv;
354
a145daf7 355 an->sc = sc;
7f010c93 356 an->sta = sta;
7e1e3864 357 an->vif = vif;
4bbf4414 358 memset(&an->key_idx, 0, sizeof(an->key_idx));
3d4e20f2 359
dd5ee59b 360 ath_tx_node_init(sc, an);
ff37e337
S		 361}
362
363static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
364{
365 struct ath_node *an = (struct ath_node *)sta->drv_priv;
dd5ee59b 366 ath_tx_node_cleanup(sc, an);
ff37e337
S		 367}
368
55624204 369void ath9k_tasklet(unsigned long data)
ff37e337
S		 370{
371 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 372 struct ath_hw *ah = sc->sc_ah;
c46917bb 373 struct ath_common *common = ath9k_hw_common(ah);
124b979b 374 enum ath_reset_type type;
07c15a3f 375 unsigned long flags;
17d7904d 376 u32 status = sc->intrstatus;
b5c80475 377 u32 rxmask;
ff37e337 378
e3927007
FF		 379 ath9k_ps_wakeup(sc);
380 spin_lock(&sc->sc_pcu_lock);
381
6549a860
SM		 382 if (status & ATH9K_INT_FATAL) {
383 type = RESET_TYPE_FATAL_INT;
124b979b 384 ath9k_queue_reset(sc, type);
c6cc47b1
SM		 385
386 /*
387 * Increment the ref. counter here so that
388 * interrupts are enabled in the reset routine.
389 */
390 atomic_inc(&ah->intr_ref_cnt);
affad456 391 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
e3927007 392 goto out;
063d8be3 393 }
ff37e337 394
6549a860
SM		 395 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
396 (status & ATH9K_INT_BB_WATCHDOG)) {
0c759977
SM		 397 spin_lock(&common->cc_lock);
398 ath_hw_cycle_counters_update(common);
399 ar9003_hw_bb_watchdog_dbg_info(ah);
400 spin_unlock(&common->cc_lock);
401
6549a860
SM		 402 if (ar9003_hw_bb_watchdog_check(ah)) {
403 type = RESET_TYPE_BB_WATCHDOG;
404 ath9k_queue_reset(sc, type);
405
406 /*
407 * Increment the ref. counter here so that
408 * interrupts are enabled in the reset routine.
409 */
410 atomic_inc(&ah->intr_ref_cnt);
affad456 411 ath_dbg(common, RESET,
6549a860
SM		 412 "BB_WATCHDOG: Skipping interrupts\n");
413 goto out;
414 }
415 }
416
071aa9a8
SM		 417 if (status & ATH9K_INT_GTT) {
418 sc->gtt_cnt++;
419
420 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
421 type = RESET_TYPE_TX_GTT;
422 ath9k_queue_reset(sc, type);
423 atomic_inc(&ah->intr_ref_cnt);
affad456 424 ath_dbg(common, RESET,
071aa9a8
SM		 425 "GTT: Skipping interrupts\n");
426 goto out;
427 }
428 }
429
07c15a3f 430 spin_lock_irqsave(&sc->sc_pm_lock, flags);
4105f807
RM		 431 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
432 /*
433 * TSF sync does not look correct; remain awake to sync with
434 * the next Beacon.
435 */
d2182b69 436 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
e8fe7336 437 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
4105f807 438 }
07c15a3f 439 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
4105f807 440
b5c80475
FF		 441 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
442 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
443 ATH9K_INT_RXORN);
444 else
445 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
446
447 if (status & rxmask) {
b5c80475
FF		 448 /* Check for high priority Rx first */
449 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
450 (status & ATH9K_INT_RXHP))
451 ath_rx_tasklet(sc, 0, true);
452
453 ath_rx_tasklet(sc, 0, false);
ff37e337
S		 454 }
455
e5003249 456 if (status & ATH9K_INT_TX) {
071aa9a8
SM		 457 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
458 /*
459 * For EDMA chips, TX completion is enabled for the
460 * beacon queue, so if a beacon has been transmitted
461 * successfully after a GTT interrupt, the GTT counter
462 * gets reset to zero here.
463 */
3b745c7b 464 sc->gtt_cnt = 0;
071aa9a8 465
e5003249 466 ath_tx_edma_tasklet(sc);
071aa9a8 467 } else {
e5003249 468 ath_tx_tasklet(sc);
071aa9a8 469 }
10e23181
FF		 470
471 wake_up(&sc->tx_wait);
e5003249 472 }
063d8be3 473
c67ce339
FF		 474 if (status & ATH9K_INT_GENTIMER)
475 ath_gen_timer_isr(sc->sc_ah);
476
56ca0dba 477 ath9k_btcoex_handle_interrupt(sc, status);
19686ddf 478
ff37e337 479 /* re-enable hardware interrupt */
4df3071e 480 ath9k_hw_enable_interrupts(ah);
c6cc47b1 481out:
52671e43 482 spin_unlock(&sc->sc_pcu_lock);
153e080d 483 ath9k_ps_restore(sc);
ff37e337
S		 484}
485
6baff7f9 486irqreturn_t ath_isr(int irq, void *dev)
ff37e337 487{
063d8be3
S		 488#define SCHED_INTR ( \
489 ATH9K_INT_FATAL | \
a4d86d95 490 ATH9K_INT_BB_WATCHDOG | \
063d8be3
S		 491 ATH9K_INT_RXORN | \
492 ATH9K_INT_RXEOL | \
493 ATH9K_INT_RX | \
b5c80475
FF		 494 ATH9K_INT_RXLP | \
495 ATH9K_INT_RXHP | \
063d8be3
S		 496 ATH9K_INT_TX | \
497 ATH9K_INT_BMISS | \
498 ATH9K_INT_CST | \
071aa9a8 499 ATH9K_INT_GTT | \
ebb8e1d7 500 ATH9K_INT_TSFOOR | \
40dc5392
MSS		 501 ATH9K_INT_GENTIMER | \
502 ATH9K_INT_MCI)
063d8be3 503
ff37e337 504 struct ath_softc *sc = dev;
cbe61d8a 505 struct ath_hw *ah = sc->sc_ah;
eefa01dd 506 struct ath_common *common = ath9k_hw_common(ah);
ff37e337 507 enum ath9k_int status;
78c8a950 508 u32 sync_cause = 0;
ff37e337
S		 509 bool sched = false;
510
063d8be3
S		 511 /*
512 * The hardware is not ready/present, don't
513 * touch anything. Note this can happen early
514 * on if the IRQ is shared.
515 */
eefa01dd 516 if (test_bit(ATH_OP_INVALID, &common->op_flags))
063d8be3 517 return IRQ_NONE;
ff37e337 518
063d8be3
S		 519 /* shared irq, not for us */
520
153e080d 521 if (!ath9k_hw_intrpend(ah))
063d8be3 522 return IRQ_NONE;
063d8be3 523
eefa01dd 524 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) {
f41a9b3b 525 ath9k_hw_kill_interrupts(ah);
b74713d0 526 return IRQ_HANDLED;
f41a9b3b 527 }
b74713d0 528
063d8be3
S		 529 /*
530 * Figure out the reason(s) for the interrupt. Note
531 * that the hal returns a pseudo-ISR that may include
532 * bits we haven't explicitly enabled so we mask the
533 * value to insure we only process bits we requested.
534 */
6a4d05dc
FF		 535 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
536 ath9k_debug_sync_cause(sc, sync_cause);
3069168c 537 status &= ah->imask; /* discard unasked-for bits */
ff37e337 538
063d8be3
S		 539 /*
540 * If there are no status bits set, then this interrupt was not
541 * for me (should have been caught above).
542 */
153e080d 543 if (!status)
063d8be3 544 return IRQ_NONE;
ff37e337 545
063d8be3
S		 546 /* Cache the status */
547 sc->intrstatus = status;
548
549 if (status & SCHED_INTR)
550 sched = true;
551
552 /*
553 * If a FATAL or RXORN interrupt is received, we have to reset the
554 * chip immediately.
555 */
b5c80475
FF		 556 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
557 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S		 558 goto chip_reset;
559
a6bb860b 560 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
0c759977 561 (status & ATH9K_INT_BB_WATCHDOG))
08578b8f 562 goto chip_reset;
e60001e7
SM		 563
564#ifdef CONFIG_ATH9K_WOW
ca90ef44
RM		 565 if (status & ATH9K_INT_BMISS) {
566 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
ca90ef44
RM		 567 atomic_inc(&sc->wow_got_bmiss_intr);
568 atomic_dec(&sc->wow_sleep_proc_intr);
569 }
570 }
571#endif
e60001e7 572
063d8be3
S		 573 if (status & ATH9K_INT_SWBA)
574 tasklet_schedule(&sc->bcon_tasklet);
575
576 if (status & ATH9K_INT_TXURN)
577 ath9k_hw_updatetxtriglevel(ah, true);
578
0682c9b5
RM		 579 if (status & ATH9K_INT_RXEOL) {
580 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
72d874c6 581 ath9k_hw_set_interrupts(ah);
b5c80475
FF		 582 }
583
153e080d
VT		 584 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
585 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR		 586 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
587 goto chip_reset;
063d8be3
S		 588 /* Clear RxAbort bit so that we can
589 * receive frames */
9ecdef4b 590 ath9k_setpower(sc, ATH9K_PM_AWAKE);
07c15a3f 591 spin_lock(&sc->sc_pm_lock);
153e080d 592 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 593 sc->ps_flags |= PS_WAIT_FOR_BEACON;
07c15a3f 594 spin_unlock(&sc->sc_pm_lock);
ff37e337 595 }
063d8be3
S		 596
597chip_reset:
ff37e337 598
817e11de
S		 599 ath_debug_stat_interrupt(sc, status);
600
ff37e337 601 if (sched) {
4df3071e
FF		 602 /* turn off every interrupt */
603 ath9k_hw_disable_interrupts(ah);
ff37e337
S		 604 tasklet_schedule(&sc->intr_tq);
605 }
606
607 return IRQ_HANDLED;
063d8be3
S		 608
609#undef SCHED_INTR
ff37e337
S		 610}
611
ef6b19e4 612int ath_reset(struct ath_softc *sc)
ff37e337 613{
ec30326e 614 int r;
ff37e337 615
783cd01e 616 ath9k_ps_wakeup(sc);
1381559b 617 r = ath_reset_internal(sc, NULL);
783cd01e 618 ath9k_ps_restore(sc);
2ab81d4a 619
ae8d2858 620 return r;
ff37e337
S		 621}
622
124b979b
RM		 623void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
624{
eefa01dd 625 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
124b979b
RM		 626#ifdef CONFIG_ATH9K_DEBUGFS
627 RESET_STAT_INC(sc, type);
628#endif
eefa01dd 629 set_bit(ATH_OP_HW_RESET, &common->op_flags);
124b979b
RM		 630 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
631}
632
236de514
FF		 633void ath_reset_work(struct work_struct *work)
634{
635 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
636
1381559b 637 ath_reset(sc);
236de514
FF		 638}
639
ff37e337
S		 640/**********************/
641/* mac80211 callbacks */
642/**********************/
643
8feceb67 644static int ath9k_start(struct ieee80211_hw *hw)
f078f209 645{
9ac58615 646 struct ath_softc *sc = hw->priv;
af03abec 647 struct ath_hw *ah = sc->sc_ah;
c46917bb 648 struct ath_common *common = ath9k_hw_common(ah);
39305635 649 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
fbbcd146 650 struct ath_chanctx *ctx = sc->cur_chan;
ff37e337 651 struct ath9k_channel *init_channel;
82880a7c 652 int r;
f078f209 653
d2182b69 654 ath_dbg(common, CONFIG,
226afe68
JP		 655 "Starting driver with initial channel: %d MHz\n",
656 curchan->center_freq);
f078f209 657
f62d816f 658 ath9k_ps_wakeup(sc);
141b38b6
S		 659 mutex_lock(&sc->mutex);
660
fbbcd146 661 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
bff11766 662 sc->cur_chandef = hw->conf.chandef;
ff37e337
S		 663
664 /* Reset SERDES registers */
84c87dc8 665 ath9k_hw_configpcipowersave(ah, false);
ff37e337
S		 666
667 /*
668 * The basic interface to setting the hardware in a good
669 * state is ``reset''. On return the hardware is known to
670 * be powered up and with interrupts disabled. This must
671 * be followed by initialization of the appropriate bits
672 * and then setup of the interrupt mask.
673 */
4bdd1e97 674 spin_lock_bh(&sc->sc_pcu_lock);
c0c11741
FF		 675
676 atomic_set(&ah->intr_ref_cnt, -1);
677
20bd2a09 678 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 679 if (r) {
3800276a
JP		 680 ath_err(common,
681 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
682 r, curchan->center_freq);
ceb26a60 683 ah->reset_power_on = false;
ff37e337 684 }
ff37e337 685
ff37e337 686 /* Setup our intr mask. */
b5c80475
FF		 687 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
688 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
689 ATH9K_INT_GLOBAL;
690
691 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f 692 ah->imask |= ATH9K_INT_RXHP |
a6bb860b 693 ATH9K_INT_RXLP;
b5c80475
FF		 694 else
695 ah->imask |= ATH9K_INT_RX;
ff37e337 696
a6bb860b
SM		 697 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
698 ah->imask |= ATH9K_INT_BB_WATCHDOG;
699
071aa9a8
SM		 700 /*
701 * Enable GTT interrupts only for AR9003/AR9004 chips
702 * for now.
703 */
704 if (AR_SREV_9300_20_OR_LATER(ah))
705 ah->imask |= ATH9K_INT_GTT;
ff37e337 706
af03abec 707 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 708 ah->imask |= ATH9K_INT_CST;
ff37e337 709
e270e776 710 ath_mci_enable(sc);
40dc5392 711
eefa01dd 712 clear_bit(ATH_OP_INVALID, &common->op_flags);
5f841b41 713 sc->sc_ah->is_monitoring = false;
ff37e337 714
ceb26a60
FF		 715 if (!ath_complete_reset(sc, false))
716 ah->reset_power_on = false;
ff37e337 717
c0c11741
FF		 718 if (ah->led_pin >= 0) {
719 ath9k_hw_cfg_output(ah, ah->led_pin,
720 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
721 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
722 }
723
724 /*
725 * Reset key cache to sane defaults (all entries cleared) instead of
726 * semi-random values after suspend/resume.
727 */
728 ath9k_cmn_init_crypto(sc->sc_ah);
729
a35051ce
FF		 730 ath9k_hw_reset_tsf(ah);
731
9adcf440 732 spin_unlock_bh(&sc->sc_pcu_lock);
164ace38 733
141b38b6
S		 734 mutex_unlock(&sc->mutex);
735
f62d816f
FF		 736 ath9k_ps_restore(sc);
737
ceb26a60 738 return 0;
f078f209
LR		 739}
740
36323f81
TH		 741static void ath9k_tx(struct ieee80211_hw *hw,
742 struct ieee80211_tx_control *control,
743 struct sk_buff *skb)
f078f209 744{
9ac58615 745 struct ath_softc *sc = hw->priv;
c46917bb 746 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 747 struct ath_tx_control txctl;
1bc14880 748 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
07c15a3f 749 unsigned long flags;
528f0c6b 750
96148326 751 if (sc->ps_enabled) {
dc8c4585
JM		 752 /*
753 * mac80211 does not set PM field for normal data frames, so we
754 * need to update that based on the current PS mode.
755 */
756 if (ieee80211_is_data(hdr->frame_control) &&
757 !ieee80211_is_nullfunc(hdr->frame_control) &&
758 !ieee80211_has_pm(hdr->frame_control)) {
d2182b69 759 ath_dbg(common, PS,
226afe68 760 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM		 761 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
762 }
763 }
764
ad128860 765 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
9a23f9ca
JM		 766 /*
767 * We are using PS-Poll and mac80211 can request TX while in
768 * power save mode. Need to wake up hardware for the TX to be
769 * completed and if needed, also for RX of buffered frames.
770 */
9a23f9ca 771 ath9k_ps_wakeup(sc);
07c15a3f 772 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fdf76622
VT		 773 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
774 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 775 if (ieee80211_is_pspoll(hdr->frame_control)) {
d2182b69 776 ath_dbg(common, PS,
226afe68 777 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 778 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 779 } else {
d2182b69 780 ath_dbg(common, PS, "Wake up to complete TX\n");
1b04b930 781 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM		 782 }
783 /*
784 * The actual restore operation will happen only after
ad128860 785 * the ps_flags bit is cleared. We are just dropping
9a23f9ca
JM		 786 * the ps_usecount here.
787 */
07c15a3f 788 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
9a23f9ca
JM		 789 ath9k_ps_restore(sc);
790 }
791
ad128860
SM		 792 /*
793 * Cannot tx while the hardware is in full sleep, it first needs a full
794 * chip reset to recover from that
795 */
796 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
797 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
798 goto exit;
799 }
800
528f0c6b 801 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 802 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
36323f81 803 txctl.sta = control->sta;
528f0c6b 804
d2182b69 805 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 806
c52f33d0 807 if (ath_tx_start(hw, skb, &txctl) != 0) {
d2182b69 808 ath_dbg(common, XMIT, "TX failed\n");
a5a0bca1 809 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
528f0c6b 810 goto exit;
8feceb67
VT		 811 }
812
7bb45683 813 return;
528f0c6b 814exit:
249ee722 815 ieee80211_free_txskb(hw, skb);
f078f209
LR		 816}
817
8feceb67 818static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 819{
9ac58615 820 struct ath_softc *sc = hw->priv;
af03abec 821 struct ath_hw *ah = sc->sc_ah;
c46917bb 822 struct ath_common *common = ath9k_hw_common(ah);
c0c11741 823 bool prev_idle;
f078f209 824
bff11766 825 cancel_work_sync(&sc->chanctx_work);
4c483817
S		 826 mutex_lock(&sc->mutex);
827
9adcf440 828 ath_cancel_work(sc);
c94dbff7 829
eefa01dd 830 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
d2182b69 831 ath_dbg(common, ANY, "Device not present\n");
4c483817 832 mutex_unlock(&sc->mutex);
9c84b797
S		 833 return;
834 }
8feceb67 835
3867cf6a
S		 836 /* Ensure HW is awake when we try to shut it down. */
837 ath9k_ps_wakeup(sc);
838
6a6733f2
LR		 839 spin_lock_bh(&sc->sc_pcu_lock);
840
203043f5
SG		 841 /* prevent tasklets to enable interrupts once we disable them */
842 ah->imask &= ~ATH9K_INT_GLOBAL;
843
ff37e337
S		 844 /* make sure h/w will not generate any interrupt
845 * before setting the invalid flag. */
4df3071e 846 ath9k_hw_disable_interrupts(ah);
ff37e337 847
c0c11741
FF		 848 spin_unlock_bh(&sc->sc_pcu_lock);
849
850 /* we can now sync irq and kill any running tasklets, since we already
851 * disabled interrupts and not holding a spin lock */
852 synchronize_irq(sc->irq);
853 tasklet_kill(&sc->intr_tq);
854 tasklet_kill(&sc->bcon_tasklet);
855
856 prev_idle = sc->ps_idle;
857 sc->ps_idle = true;
858
859 spin_lock_bh(&sc->sc_pcu_lock);
860
861 if (ah->led_pin >= 0) {
862 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
863 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
864 }
865
9ebea382 866 ath_prepare_reset(sc);
ff37e337 867
0d95521e
FF		 868 if (sc->rx.frag) {
869 dev_kfree_skb_any(sc->rx.frag);
870 sc->rx.frag = NULL;
871 }
872
c0c11741 873 if (!ah->curchan)
fbbcd146
FF		 874 ah->curchan = ath9k_cmn_get_channel(hw, ah,
875 &sc->cur_chan->chandef);
6a6733f2 876
c0c11741
FF		 877 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
878 ath9k_hw_phy_disable(ah);
6a6733f2 879
c0c11741 880 ath9k_hw_configpcipowersave(ah, true);
203043f5 881
c0c11741 882 spin_unlock_bh(&sc->sc_pcu_lock);
3867cf6a 883
c0c11741 884 ath9k_ps_restore(sc);
ff37e337 885
eefa01dd 886 set_bit(ATH_OP_INVALID, &common->op_flags);
c0c11741 887 sc->ps_idle = prev_idle;
500c064d 888
141b38b6
S		 889 mutex_unlock(&sc->mutex);
890
d2182b69 891 ath_dbg(common, CONFIG, "Driver halt\n");
f078f209
LR		 892}
893
c648ecb0 894static bool ath9k_uses_beacons(int type)
4801416c
BG		 895{
896 switch (type) {
897 case NL80211_IFTYPE_AP:
898 case NL80211_IFTYPE_ADHOC:
899 case NL80211_IFTYPE_MESH_POINT:
900 return true;
901 default:
902 return false;
903 }
904}
905
4801416c
BG		 906static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
907{
908 struct ath9k_vif_iter_data *iter_data = data;
909 int i;
910
ab11bb28 911 if (iter_data->has_hw_macaddr) {
4801416c
BG		 912 for (i = 0; i < ETH_ALEN; i++)
913 iter_data->mask[i] &=
914 ~(iter_data->hw_macaddr[i] ^ mac[i]);
ab11bb28
FF		 915 } else {
916 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
917 iter_data->has_hw_macaddr = true;
918 }
141b38b6 919
9a9c4fbc
RM		 920 if (!vif->bss_conf.use_short_slot)
921 iter_data->slottime = ATH9K_SLOT_TIME_20;
922
1ed32e4f 923 switch (vif->type) {
4801416c
BG		 924 case NL80211_IFTYPE_AP:
925 iter_data->naps++;
9a9c4fbc
RM		 926 if (vif->bss_conf.enable_beacon)
927 iter_data->beacons = true;
f078f209 928 break;
4801416c
BG		 929 case NL80211_IFTYPE_STATION:
930 iter_data->nstations++;
9a9c4fbc
RM		 931 if (vif->bss_conf.assoc && !iter_data->primary_sta)
932 iter_data->primary_sta = vif;
e51f3eff 933 break;
05c914fe 934 case NL80211_IFTYPE_ADHOC:
4801416c 935 iter_data->nadhocs++;
9a9c4fbc
RM		 936 if (vif->bss_conf.enable_beacon)
937 iter_data->beacons = true;
4801416c 938 break;
9cb5412b 939 case NL80211_IFTYPE_MESH_POINT:
4801416c 940 iter_data->nmeshes++;
9a9c4fbc
RM		 941 if (vif->bss_conf.enable_beacon)
942 iter_data->beacons = true;
4801416c
BG		 943 break;
944 case NL80211_IFTYPE_WDS:
945 iter_data->nwds++;
f078f209
LR		 946 break;
947 default:
4801416c 948 break;
f078f209 949 }
4801416c 950}
f078f209 951
4801416c 952/* Called with sc->mutex held. */
9a9c4fbc
RM		 953void ath9k_calculate_iter_data(struct ath_softc *sc,
954 struct ath_chanctx *ctx,
4801416c
BG		 955 struct ath9k_vif_iter_data *iter_data)
956{
9a9c4fbc 957 struct ath_vif *avp;
8feceb67 958
4801416c 959 /*
657eb17d
MV		 960 * Pick the MAC address of the first interface as the new hardware
961 * MAC address. The hardware will use it together with the BSSID mask
962 * when matching addresses.
4801416c
BG		 963 */
964 memset(iter_data, 0, sizeof(*iter_data));
4801416c 965 memset(&iter_data->mask, 0xff, ETH_ALEN);
9a9c4fbc
RM		 966 iter_data->slottime = ATH9K_SLOT_TIME_9;
967
968 list_for_each_entry(avp, &ctx->vifs, list)
969 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
970
971 if (ctx == &sc->offchannel.chan) {
972 struct ieee80211_vif *vif;
973
974 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
975 vif = sc->offchannel.scan_vif;
976 else
977 vif = sc->offchannel.roc_vif;
978
979 if (vif)
980 ath9k_vif_iter(iter_data, vif->addr, vif);
981 iter_data->beacons = false;
982 }
983}
984
985static void ath9k_set_assoc_state(struct ath_softc *sc,
986 struct ieee80211_vif *vif, bool changed)
987{
988 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
989 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
990 unsigned long flags;
991
992 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
993 /* Set the AID, BSSID and do beacon-sync only when
994 * the HW opmode is STATION.
995 *
996 * But the primary bit is set above in any case.
997 */
998 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
999 return;
1000
1001 ether_addr_copy(common->curbssid, bss_conf->bssid);
1002 common->curaid = bss_conf->aid;
1003 ath9k_hw_write_associd(sc->sc_ah);
1004
1005 if (changed) {
1006 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1007 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
5640b08e 1008
9a9c4fbc
RM		 1009 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1010 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1011 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1012 }
4801416c 1013
9a9c4fbc
RM		 1014 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1015 ath9k_mci_update_wlan_channels(sc, false);
ab11bb28 1016
9a9c4fbc
RM		 1017 ath_dbg(common, CONFIG,
1018 "Primary Station interface: %pM, BSSID: %pM\n",
1019 vif->addr, common->curbssid);
4801416c 1020}
8ca21f01 1021
4801416c 1022/* Called with sc->mutex held. */
9a9c4fbc
RM		 1023void ath9k_calculate_summary_state(struct ath_softc *sc,
1024 struct ath_chanctx *ctx)
4801416c 1025{
4801416c
BG		 1026 struct ath_hw *ah = sc->sc_ah;
1027 struct ath_common *common = ath9k_hw_common(ah);
1028 struct ath9k_vif_iter_data iter_data;
8ca21f01 1029
9a9c4fbc
RM		 1030 ath_chanctx_check_active(sc, ctx);
1031
1032 if (ctx != sc->cur_chan)
1033 return;
1034
1035 ath9k_ps_wakeup(sc);
1036 ath9k_calculate_iter_data(sc, ctx, &iter_data);
1037
1038 if (iter_data.has_hw_macaddr)
1039 ether_addr_copy(common->macaddr, iter_data.hw_macaddr);
2c3db3d5 1040
4801416c
BG		 1041 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1042 ath_hw_setbssidmask(common);
1043
4801416c 1044 if (iter_data.naps > 0) {
60ca9f87 1045 ath9k_hw_set_tsfadjust(ah, true);
4801416c
BG		 1046 ah->opmode = NL80211_IFTYPE_AP;
1047 } else {
60ca9f87 1048 ath9k_hw_set_tsfadjust(ah, false);
5640b08e 1049
fd5999cf
JC		 1050 if (iter_data.nmeshes)
1051 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1052 else if (iter_data.nwds)
4801416c
BG		 1053 ah->opmode = NL80211_IFTYPE_AP;
1054 else if (iter_data.nadhocs)
1055 ah->opmode = NL80211_IFTYPE_ADHOC;
1056 else
1057 ah->opmode = NL80211_IFTYPE_STATION;
1058 }
5640b08e 1059
df35d29e
SM		 1060 ath9k_hw_setopmode(ah);
1061
748299f2 1062 ctx->switch_after_beacon = false;
198823fd 1063 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
3069168c 1064 ah->imask |= ATH9K_INT_TSFOOR;
748299f2 1065 else {
4801416c 1066 ah->imask &= ~ATH9K_INT_TSFOOR;
748299f2
FF		 1067 if (iter_data.naps == 1 && iter_data.beacons)
1068 ctx->switch_after_beacon = true;
1069 }
4af9cf4f 1070
9a9c4fbc
RM		 1071 ah->imask &= ~ATH9K_INT_SWBA;
1072 if (ah->opmode == NL80211_IFTYPE_STATION) {
1073 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1074
1075 iter_data.beacons = true;
1076 if (iter_data.primary_sta) {
1077 ath9k_set_assoc_state(sc, iter_data.primary_sta,
1078 changed);
1079 if (!ctx->primary_sta ||
1080 !ctx->primary_sta->bss_conf.assoc)
1081 ctx->primary_sta = iter_data.primary_sta;
1082 } else {
1083 ctx->primary_sta = NULL;
1084 memset(common->curbssid, 0, ETH_ALEN);
1085 common->curaid = 0;
1086 ath9k_hw_write_associd(sc->sc_ah);
1087 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1088 ath9k_mci_update_wlan_channels(sc, true);
1089 }
1090 } else if (iter_data.beacons) {
1091 ah->imask |= ATH9K_INT_SWBA;
1092 }
72d874c6 1093 ath9k_hw_set_interrupts(ah);
6dcc3444 1094
9a9c4fbc
RM		 1095 if (iter_data.beacons)
1096 set_bit(ATH_OP_BEACONS, &common->op_flags);
1097 else
1098 clear_bit(ATH_OP_BEACONS, &common->op_flags);
1099
1100 if (ah->slottime != iter_data.slottime) {
1101 ah->slottime = iter_data.slottime;
1102 ath9k_hw_init_global_settings(ah);
6dcc3444 1103 }
9a9c4fbc
RM		 1104
1105 if (iter_data.primary_sta)
1106 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1107 else
1108 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1109
1110 ctx->primary_sta = iter_data.primary_sta;
1111
1112 ath9k_ps_restore(sc);
4801416c 1113}
6f255425 1114
4801416c
BG		 1115static int ath9k_add_interface(struct ieee80211_hw *hw,
1116 struct ieee80211_vif *vif)
6b3b991d 1117{
9ac58615 1118 struct ath_softc *sc = hw->priv;
4801416c
BG		 1119 struct ath_hw *ah = sc->sc_ah;
1120 struct ath_common *common = ath9k_hw_common(ah);
f89d1bc4
FF		 1121 struct ath_vif *avp = (void *)vif->drv_priv;
1122 struct ath_node *an = &avp->mcast_node;
3ad9c386 1123 int i;
6b3b991d 1124
4801416c 1125 mutex_lock(&sc->mutex);
6b3b991d 1126
89f927af
LR		 1127 if (config_enabled(CONFIG_ATH9K_TX99)) {
1128 if (sc->nvifs >= 1) {
1129 mutex_unlock(&sc->mutex);
1130 return -EOPNOTSUPP;
1131 }
1132 sc->tx99_vif = vif;
1133 }
1134
d2182b69 1135 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
4801416c
BG		 1136 sc->nvifs++;
1137
130ef6e9
SM		 1138 if (ath9k_uses_beacons(vif->type))
1139 ath9k_beacon_assign_slot(sc, vif);
1140
d463af4a 1141 avp->vif = vif;
9a9c4fbc 1142 if (!ath9k_use_chanctx) {
39305635 1143 avp->chanctx = sc->cur_chan;
9a9c4fbc
RM		 1144 list_add_tail(&avp->list, &avp->chanctx->vifs);
1145 }
3ad9c386
RM		 1146 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1147 vif->hw_queue[i] = i;
1148 if (vif->type == NL80211_IFTYPE_AP)
1149 vif->cab_queue = hw->queues - 2;
1150 else
1151 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
0453531e 1152
f89d1bc4
FF		 1153 an->sc = sc;
1154 an->sta = NULL;
1155 an->vif = vif;
1156 an->no_ps_filter = true;
1157 ath_tx_node_init(sc, an);
1158
4801416c 1159 mutex_unlock(&sc->mutex);
327967cb 1160 return 0;
6b3b991d
RM		 1161}
1162
1163static int ath9k_change_interface(struct ieee80211_hw *hw,
1164 struct ieee80211_vif *vif,
1165 enum nl80211_iftype new_type,
1166 bool p2p)
1167{
9ac58615 1168 struct ath_softc *sc = hw->priv;
6b3b991d 1169 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
c083ce99 1170 struct ath_vif *avp = (void *)vif->drv_priv;
3ad9c386 1171 int i;
6b3b991d 1172
6b3b991d 1173 mutex_lock(&sc->mutex);
4801416c 1174
89f927af
LR		 1175 if (config_enabled(CONFIG_ATH9K_TX99)) {
1176 mutex_unlock(&sc->mutex);
1177 return -EOPNOTSUPP;
1178 }
1179
1180 ath_dbg(common, CONFIG, "Change Interface\n");
1181
4801416c 1182 if (ath9k_uses_beacons(vif->type))
130ef6e9 1183 ath9k_beacon_remove_slot(sc, vif);
4801416c 1184
6b3b991d
RM		 1185 vif->type = new_type;
1186 vif->p2p = p2p;
1187
130ef6e9
SM		 1188 if (ath9k_uses_beacons(vif->type))
1189 ath9k_beacon_assign_slot(sc, vif);
9a9c4fbc 1190
3ad9c386
RM		 1191 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1192 vif->hw_queue[i] = i;
1193
1194 if (vif->type == NL80211_IFTYPE_AP)
1195 vif->cab_queue = hw->queues - 2;
1196 else
1197 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1198
9a9c4fbc 1199 ath9k_calculate_summary_state(sc, avp->chanctx);
130ef6e9 1200
6b3b991d 1201 mutex_unlock(&sc->mutex);
327967cb 1202 return 0;
6b3b991d
RM		 1203}
1204
8feceb67 1205static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1206 struct ieee80211_vif *vif)
f078f209 1207{
9ac58615 1208 struct ath_softc *sc = hw->priv;
c46917bb 1209 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f89d1bc4 1210 struct ath_vif *avp = (void *)vif->drv_priv;
f078f209 1211
d2182b69 1212 ath_dbg(common, CONFIG, "Detach Interface\n");
f078f209 1213
141b38b6
S		 1214 mutex_lock(&sc->mutex);
1215
d463af4a
FF		 1216 spin_lock_bh(&sc->sc_pcu_lock);
1217 if (avp == sc->p2p_ps_vif) {
1218 sc->p2p_ps_vif = NULL;
1219 ath9k_update_p2p_ps_timer(sc, NULL);
1220 }
1221 spin_unlock_bh(&sc->sc_pcu_lock);
1222
4801416c 1223 sc->nvifs--;
89f927af 1224 sc->tx99_vif = NULL;
9a9c4fbc
RM		 1225 if (!ath9k_use_chanctx)
1226 list_del(&avp->list);
580f0b8a 1227
4801416c 1228 if (ath9k_uses_beacons(vif->type))
130ef6e9 1229 ath9k_beacon_remove_slot(sc, vif);
2c3db3d5 1230
f89d1bc4
FF		 1231 ath_tx_node_cleanup(sc, &avp->mcast_node);
1232
141b38b6 1233 mutex_unlock(&sc->mutex);
f078f209
LR		 1234}
1235
fbab7390 1236static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1237{
3069168c 1238 struct ath_hw *ah = sc->sc_ah;
ad128860 1239 struct ath_common *common = ath9k_hw_common(ah);
3069168c 1240
89f927af
LR		 1241 if (config_enabled(CONFIG_ATH9K_TX99))
1242 return;
1243
3f7c5c10 1244 sc->ps_enabled = true;
3069168c
PR		 1245 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1246 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1247 ah->imask |= ATH9K_INT_TIM_TIMER;
72d874c6 1248 ath9k_hw_set_interrupts(ah);
3f7c5c10 1249 }
fdf76622 1250 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1251 }
ad128860 1252 ath_dbg(common, PS, "PowerSave enabled\n");
3f7c5c10
SB		 1253}
1254
845d708e
SB		 1255static void ath9k_disable_ps(struct ath_softc *sc)
1256{
1257 struct ath_hw *ah = sc->sc_ah;
ad128860 1258 struct ath_common *common = ath9k_hw_common(ah);
845d708e 1259
89f927af
LR		 1260 if (config_enabled(CONFIG_ATH9K_TX99))
1261 return;
1262
845d708e
SB		 1263 sc->ps_enabled = false;
1264 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1265 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1266 ath9k_hw_setrxabort(ah, 0);
1267 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1268 PS_WAIT_FOR_CAB |
1269 PS_WAIT_FOR_PSPOLL_DATA |
1270 PS_WAIT_FOR_TX_ACK);
1271 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1272 ah->imask &= ~ATH9K_INT_TIM_TIMER;
72d874c6 1273 ath9k_hw_set_interrupts(ah);
845d708e
SB		 1274 }
1275 }
ad128860 1276 ath_dbg(common, PS, "PowerSave disabled\n");
845d708e
SB		 1277}
1278
e93d083f
SW		 1279void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw)
1280{
1281 struct ath_softc *sc = hw->priv;
1282 struct ath_hw *ah = sc->sc_ah;
1283 struct ath_common *common = ath9k_hw_common(ah);
1284 u32 rxfilter;
1285
89f927af
LR		 1286 if (config_enabled(CONFIG_ATH9K_TX99))
1287 return;
1288
e93d083f
SW		 1289 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
1290 ath_err(common, "spectrum analyzer not implemented on this hardware\n");
1291 return;
1292 }
1293
1294 ath9k_ps_wakeup(sc);
1295 rxfilter = ath9k_hw_getrxfilter(ah);
1296 ath9k_hw_setrxfilter(ah, rxfilter |
1297 ATH9K_RX_FILTER_PHYRADAR |
1298 ATH9K_RX_FILTER_PHYERR);
1299
1300 /* TODO: usually this should not be neccesary, but for some reason
1301 * (or in some mode?) the trigger must be called after the
1302 * configuration, otherwise the register will have its values reset
1303 * (on my ar9220 to value 0x01002310)
1304 */
1305 ath9k_spectral_scan_config(hw, sc->spectral_mode);
1306 ath9k_hw_ops(ah)->spectral_scan_trigger(ah);
1307 ath9k_ps_restore(sc);
1308}
1309
1310int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
1311 enum spectral_mode spectral_mode)
1312{
1313 struct ath_softc *sc = hw->priv;
1314 struct ath_hw *ah = sc->sc_ah;
1315 struct ath_common *common = ath9k_hw_common(ah);
e93d083f
SW		 1316
1317 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
1318 ath_err(common, "spectrum analyzer not implemented on this hardware\n");
1319 return -1;
1320 }
1321
e93d083f
SW		 1322 switch (spectral_mode) {
1323 case SPECTRAL_DISABLED:
04ccd4a1 1324 sc->spec_config.enabled = 0;
e93d083f
SW		 1325 break;
1326 case SPECTRAL_BACKGROUND:
1327 /* send endless samples.
1328 * TODO: is this really useful for "background"?
1329 */
04ccd4a1
SW		 1330 sc->spec_config.endless = 1;
1331 sc->spec_config.enabled = 1;
e93d083f
SW		 1332 break;
1333 case SPECTRAL_CHANSCAN:
e93d083f 1334 case SPECTRAL_MANUAL:
04ccd4a1
SW		 1335 sc->spec_config.endless = 0;
1336 sc->spec_config.enabled = 1;
e93d083f
SW		 1337 break;
1338 default:
1339 return -1;
1340 }
1341
1342 ath9k_ps_wakeup(sc);
04ccd4a1 1343 ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config);
e93d083f
SW		 1344 ath9k_ps_restore(sc);
1345
1346 sc->spectral_mode = spectral_mode;
1347
1348 return 0;
1349}
1350
e8975581 1351static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1352{
9ac58615 1353 struct ath_softc *sc = hw->priv;
3430098a
FF		 1354 struct ath_hw *ah = sc->sc_ah;
1355 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1356 struct ieee80211_conf *conf = &hw->conf;
fbbcd146 1357 struct ath_chanctx *ctx = sc->cur_chan;
f078f209 1358
c0c11741 1359 ath9k_ps_wakeup(sc);
aa33de09 1360 mutex_lock(&sc->mutex);
141b38b6 1361
daa1b6ee 1362 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4 1363 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
b73f3e78 1364 if (sc->ps_idle) {
daa1b6ee 1365 ath_cancel_work(sc);
b73f3e78
RM		 1366 ath9k_stop_btcoex(sc);
1367 } else {
1368 ath9k_start_btcoex(sc);
75600abf
FF		 1369 /*
1370 * The chip needs a reset to properly wake up from
1371 * full sleep
1372 */
39305635 1373 ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
b73f3e78 1374 }
daa1b6ee 1375 }
64839170 1376
e7824a50
LR		 1377 /*
1378 * We just prepare to enable PS. We have to wait until our AP has
1379 * ACK'd our null data frame to disable RX otherwise we'll ignore
1380 * those ACKs and end up retransmitting the same null data frames.
1381 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1382 */
3cbb5dd7 1383 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR		 1384 unsigned long flags;
1385 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB		 1386 if (conf->flags & IEEE80211_CONF_PS)
1387 ath9k_enable_ps(sc);
845d708e
SB		 1388 else
1389 ath9k_disable_ps(sc);
8ab2cd09 1390 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN		 1391 }
1392
199afd9d
S		 1393 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1394 if (conf->flags & IEEE80211_CONF_MONITOR) {
d2182b69 1395 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
5f841b41
RM		 1396 sc->sc_ah->is_monitoring = true;
1397 } else {
d2182b69 1398 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
5f841b41 1399 sc->sc_ah->is_monitoring = false;
199afd9d
S		 1400 }
1401 }
1402
39305635 1403 if (!ath9k_use_chanctx && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
fbbcd146 1404 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
bff11766 1405 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
094d05dc 1406 }
f078f209 1407
c9f6a656 1408 if (changed & IEEE80211_CONF_CHANGE_POWER) {
d2182b69 1409 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
bc7e1be7 1410 sc->cur_chan->txpower = 2 * conf->power_level;
5048e8c3 1411 ath9k_cmn_update_txpow(ah, sc->curtxpow,
bc7e1be7 1412 sc->cur_chan->txpower, &sc->curtxpow);
64839170
LR		 1413 }
1414
aa33de09 1415 mutex_unlock(&sc->mutex);
c0c11741 1416 ath9k_ps_restore(sc);
141b38b6 1417
f078f209
LR		 1418 return 0;
1419}
1420
8feceb67
VT		 1421#define SUPPORTED_FILTERS \
1422 (FIF_PROMISC_IN_BSS | \
1423 FIF_ALLMULTI | \
1424 FIF_CONTROL | \
af6a3fc7 1425 FIF_PSPOLL | \
8feceb67
VT		 1426 FIF_OTHER_BSS | \
1427 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1428 FIF_PROBE_REQ | \
8feceb67 1429 FIF_FCSFAIL)
c83be688 1430
8feceb67
VT		 1431/* FIXME: sc->sc_full_reset ? */
1432static void ath9k_configure_filter(struct ieee80211_hw *hw,
1433 unsigned int changed_flags,
1434 unsigned int *total_flags,
3ac64bee 1435 u64 multicast)
8feceb67 1436{
9ac58615 1437 struct ath_softc *sc = hw->priv;
8feceb67 1438 u32 rfilt;
f078f209 1439
8feceb67
VT		 1440 changed_flags &= SUPPORTED_FILTERS;
1441 *total_flags &= SUPPORTED_FILTERS;
f078f209 1442
b77f483f 1443 sc->rx.rxfilter = *total_flags;
aa68aeaa 1444 ath9k_ps_wakeup(sc);
8feceb67
VT		 1445 rfilt = ath_calcrxfilter(sc);
1446 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1447 ath9k_ps_restore(sc);
f078f209 1448
d2182b69
JP		 1449 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1450 rfilt);
8feceb67 1451}
f078f209 1452
4ca77860
JB		 1453static int ath9k_sta_add(struct ieee80211_hw *hw,
1454 struct ieee80211_vif *vif,
1455 struct ieee80211_sta *sta)
8feceb67 1456{
9ac58615 1457 struct ath_softc *sc = hw->priv;
93ae2dd2
FF		 1458 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1459 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1460 struct ieee80211_key_conf ps_key = { };
4ef69d03 1461 int key;
f078f209 1462
7e1e3864 1463 ath_node_attach(sc, sta, vif);
f59a59fe
FF		 1464
1465 if (vif->type != NL80211_IFTYPE_AP &&
1466 vif->type != NL80211_IFTYPE_AP_VLAN)
1467 return 0;
1468
4ef69d03 1469 key = ath_key_config(common, vif, sta, &ps_key);
4bbf4414 1470 if (key > 0) {
4ef69d03 1471 an->ps_key = key;
4bbf4414
RM		 1472 an->key_idx[0] = key;
1473 }
4ca77860
JB		 1474
1475 return 0;
1476}
1477
93ae2dd2
FF		 1478static void ath9k_del_ps_key(struct ath_softc *sc,
1479 struct ieee80211_vif *vif,
1480 struct ieee80211_sta *sta)
1481{
1482 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1483 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1484 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1485
1486 if (!an->ps_key)
1487 return;
1488
1489 ath_key_delete(common, &ps_key);
4ef69d03 1490 an->ps_key = 0;
4bbf4414 1491 an->key_idx[0] = 0;
93ae2dd2
FF		 1492}
1493
4ca77860
JB		 1494static int ath9k_sta_remove(struct ieee80211_hw *hw,
1495 struct ieee80211_vif *vif,
1496 struct ieee80211_sta *sta)
1497{
9ac58615 1498 struct ath_softc *sc = hw->priv;
4ca77860 1499
93ae2dd2 1500 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB		 1501 ath_node_detach(sc, sta);
1502
1503 return 0;
f078f209
LR		 1504}
1505
4bbf4414
RM		 1506static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1507 struct ath_node *an,
1508 bool set)
1509{
1510 int i;
1511
1512 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1513 if (!an->key_idx[i])
1514 continue;
1515 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1516 }
1517}
1518
5519541d
FF		 1519static void ath9k_sta_notify(struct ieee80211_hw *hw,
1520 struct ieee80211_vif *vif,
1521 enum sta_notify_cmd cmd,
1522 struct ieee80211_sta *sta)
1523{
1524 struct ath_softc *sc = hw->priv;
1525 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1526
1527 switch (cmd) {
1528 case STA_NOTIFY_SLEEP:
1529 an->sleeping = true;
042ec453 1530 ath_tx_aggr_sleep(sta, sc, an);
4bbf4414 1531 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
5519541d
FF		 1532 break;
1533 case STA_NOTIFY_AWAKE:
4bbf4414 1534 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
5519541d
FF		 1535 an->sleeping = false;
1536 ath_tx_aggr_wakeup(sc, an);
1537 break;
1538 }
1539}
1540
8a3a3c85
EP		 1541static int ath9k_conf_tx(struct ieee80211_hw *hw,
1542 struct ieee80211_vif *vif, u16 queue,
8feceb67 1543 const struct ieee80211_tx_queue_params *params)
f078f209 1544{
9ac58615 1545 struct ath_softc *sc = hw->priv;
c46917bb 1546 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1547 struct ath_txq *txq;
8feceb67 1548 struct ath9k_tx_queue_info qi;
066dae93 1549 int ret = 0;
f078f209 1550
bea843c7 1551 if (queue >= IEEE80211_NUM_ACS)
8feceb67 1552 return 0;
f078f209 1553
066dae93
FF		 1554 txq = sc->tx.txq_map[queue];
1555
96f372c9 1556 ath9k_ps_wakeup(sc);
141b38b6
S		 1557 mutex_lock(&sc->mutex);
1558
1ffb0610
S		 1559 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1560
8feceb67
VT		 1561 qi.tqi_aifs = params->aifs;
1562 qi.tqi_cwmin = params->cw_min;
1563 qi.tqi_cwmax = params->cw_max;
531bd079 1564 qi.tqi_burstTime = params->txop * 32;
f078f209 1565
d2182b69 1566 ath_dbg(common, CONFIG,
226afe68
JP		 1567 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1568 queue, txq->axq_qnum, params->aifs, params->cw_min,
1569 params->cw_max, params->txop);
f078f209 1570
aa5955c3 1571 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
066dae93 1572 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1573 if (ret)
3800276a 1574 ath_err(common, "TXQ Update failed\n");
f078f209 1575
141b38b6 1576 mutex_unlock(&sc->mutex);
96f372c9 1577 ath9k_ps_restore(sc);
141b38b6 1578
8feceb67
VT		 1579 return ret;
1580}
f078f209 1581
8feceb67
VT		 1582static int ath9k_set_key(struct ieee80211_hw *hw,
1583 enum set_key_cmd cmd,
dc822b5d
JB		 1584 struct ieee80211_vif *vif,
1585 struct ieee80211_sta *sta,
8feceb67
VT		 1586 struct ieee80211_key_conf *key)
1587{
9ac58615 1588 struct ath_softc *sc = hw->priv;
c46917bb 1589 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
4bbf4414
RM		 1590 struct ath_node *an = NULL;
1591 int ret = 0, i;
f078f209 1592
3e6109c5 1593 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM		 1594 return -ENOSPC;
1595
5bd5e9a6
CYY		 1596 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1597 vif->type == NL80211_IFTYPE_MESH_POINT) &&
cfdc9a8b
JM		 1598 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1599 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1600 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1601 /*
1602 * For now, disable hw crypto for the RSN IBSS group keys. This
1603 * could be optimized in the future to use a modified key cache
1604 * design to support per-STA RX GTK, but until that gets
1605 * implemented, use of software crypto for group addressed
1606 * frames is a acceptable to allow RSN IBSS to be used.
1607 */
1608 return -EOPNOTSUPP;
1609 }
1610
141b38b6 1611 mutex_lock(&sc->mutex);
3cbb5dd7 1612 ath9k_ps_wakeup(sc);
4bbf4414
RM		 1613 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1614 if (sta)
1615 an = (struct ath_node *)sta->drv_priv;
f078f209 1616
8feceb67
VT		 1617 switch (cmd) {
1618 case SET_KEY:
93ae2dd2
FF		 1619 if (sta)
1620 ath9k_del_ps_key(sc, vif, sta);
1621
4bbf4414 1622 key->hw_key_idx = 0;
040e539e 1623 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM		 1624 if (ret >= 0) {
1625 key->hw_key_idx = ret;
8feceb67
VT		 1626 /* push IV and Michael MIC generation to stack */
1627 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1628 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1629 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB		 1630 if (sc->sc_ah->sw_mgmt_crypto &&
1631 key->cipher == WLAN_CIPHER_SUITE_CCMP)
e548c49e 1632 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
6ace2891 1633 ret = 0;
8feceb67 1634 }
4bbf4414
RM		 1635 if (an && key->hw_key_idx) {
1636 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1637 if (an->key_idx[i])
1638 continue;
1639 an->key_idx[i] = key->hw_key_idx;
1640 break;
1641 }
1642 WARN_ON(i == ARRAY_SIZE(an->key_idx));
1643 }
8feceb67
VT		 1644 break;
1645 case DISABLE_KEY:
040e539e 1646 ath_key_delete(common, key);
4bbf4414
RM		 1647 if (an) {
1648 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1649 if (an->key_idx[i] != key->hw_key_idx)
1650 continue;
1651 an->key_idx[i] = 0;
1652 break;
1653 }
1654 }
1655 key->hw_key_idx = 0;
8feceb67
VT		 1656 break;
1657 default:
1658 ret = -EINVAL;
1659 }
f078f209 1660
3cbb5dd7 1661 ath9k_ps_restore(sc);
141b38b6
S		 1662 mutex_unlock(&sc->mutex);
1663
8feceb67
VT		 1664 return ret;
1665}
6c43c090 1666
8feceb67
VT		 1667static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1668 struct ieee80211_vif *vif,
1669 struct ieee80211_bss_conf *bss_conf,
1670 u32 changed)
1671{
da0d45f7
SM		 1672#define CHECK_ANI \
1673 (BSS_CHANGED_ASSOC | \
1674 BSS_CHANGED_IBSS | \
1675 BSS_CHANGED_BEACON_ENABLED)
1676
9ac58615 1677 struct ath_softc *sc = hw->priv;
2d0ddec5 1678 struct ath_hw *ah = sc->sc_ah;
1510718d 1679 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1680 struct ath_vif *avp = (void *)vif->drv_priv;
60ccc107 1681 unsigned long flags;
0005baf4 1682 int slottime;
f078f209 1683
96f372c9 1684 ath9k_ps_wakeup(sc);
141b38b6
S		 1685 mutex_lock(&sc->mutex);
1686
9f61903c 1687 if (changed & BSS_CHANGED_ASSOC) {
6c43c090
SM		 1688 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1689 bss_conf->bssid, bss_conf->assoc);
1690
9a9c4fbc 1691 ath9k_calculate_summary_state(sc, avp->chanctx);
73fa2f26
FF		 1692 if (bss_conf->assoc)
1693 ath_chanctx_event(sc, vif, ATH_CHANCTX_EVENT_ASSOC);
c6089ccc 1694 }
2d0ddec5 1695
2e5ef459 1696 if (changed & BSS_CHANGED_IBSS) {
2e5ef459
RM		 1697 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1698 common->curaid = bss_conf->aid;
1699 ath9k_hw_write_associd(sc->sc_ah);
2e5ef459
RM		 1700 }
1701
ef4ad633 1702 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
9198cf4a
RM		 1703 (changed & BSS_CHANGED_BEACON_INT) ||
1704 (changed & BSS_CHANGED_BEACON_INFO)) {
9a9c4fbc
RM		 1705 if (changed & BSS_CHANGED_BEACON_ENABLED)
1706 ath9k_calculate_summary_state(sc, avp->chanctx);
c32e4e51 1707 ath9k_beacon_config(sc, vif, changed);
9a9c4fbc 1708 }
0005baf4 1709
9a9c4fbc
RM		 1710 if ((avp->chanctx == sc->cur_chan) &&
1711 (changed & BSS_CHANGED_ERP_SLOT)) {
0005baf4
FF		 1712 if (bss_conf->use_short_slot)
1713 slottime = 9;
1714 else
1715 slottime = 20;
1716 if (vif->type == NL80211_IFTYPE_AP) {
1717 /*
1718 * Defer update, so that connected stations can adjust
1719 * their settings at the same time.
1720 * See beacon.c for more details
1721 */
1722 sc->beacon.slottime = slottime;
1723 sc->beacon.updateslot = UPDATE;
1724 } else {
1725 ah->slottime = slottime;
1726 ath9k_hw_init_global_settings(ah);
1727 }
2d0ddec5
JB		 1728 }
1729
d463af4a
FF		 1730 if (changed & BSS_CHANGED_P2P_PS) {
1731 spin_lock_bh(&sc->sc_pcu_lock);
60ccc107
RM		 1732 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1733 if (!(sc->ps_flags & PS_BEACON_SYNC))
1734 ath9k_update_p2p_ps(sc, vif);
1735 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
d463af4a
FF		 1736 spin_unlock_bh(&sc->sc_pcu_lock);
1737 }
1738
da0d45f7
SM		 1739 if (changed & CHECK_ANI)
1740 ath_check_ani(sc);
1741
141b38b6 1742 mutex_unlock(&sc->mutex);
96f372c9 1743 ath9k_ps_restore(sc);
da0d45f7
SM		 1744
1745#undef CHECK_ANI
8feceb67 1746}
f078f209 1747
37a41b4a 1748static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1749{
9ac58615 1750 struct ath_softc *sc = hw->priv;
8feceb67 1751 u64 tsf;
f078f209 1752
141b38b6 1753 mutex_lock(&sc->mutex);
9abbfb27 1754 ath9k_ps_wakeup(sc);
141b38b6 1755 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 1756 ath9k_ps_restore(sc);
141b38b6 1757 mutex_unlock(&sc->mutex);
f078f209 1758
8feceb67
VT		 1759 return tsf;
1760}
f078f209 1761
37a41b4a
EP		 1762static void ath9k_set_tsf(struct ieee80211_hw *hw,
1763 struct ieee80211_vif *vif,
1764 u64 tsf)
3b5d665b 1765{
9ac58615 1766 struct ath_softc *sc = hw->priv;
3b5d665b 1767
141b38b6 1768 mutex_lock(&sc->mutex);
9abbfb27 1769 ath9k_ps_wakeup(sc);
141b38b6 1770 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 1771 ath9k_ps_restore(sc);
141b38b6 1772 mutex_unlock(&sc->mutex);
3b5d665b
AF		 1773}
1774
37a41b4a 1775static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1776{
9ac58615 1777 struct ath_softc *sc = hw->priv;
c83be688 1778
141b38b6 1779 mutex_lock(&sc->mutex);
21526d57
LR		 1780
1781 ath9k_ps_wakeup(sc);
141b38b6 1782 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR		 1783 ath9k_ps_restore(sc);
1784
141b38b6 1785 mutex_unlock(&sc->mutex);
8feceb67 1786}
f078f209 1787
8feceb67 1788static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 1789 struct ieee80211_vif *vif,
141b38b6
S		 1790 enum ieee80211_ampdu_mlme_action action,
1791 struct ieee80211_sta *sta,
0b01f030 1792 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 1793{
9ac58615 1794 struct ath_softc *sc = hw->priv;
16e23428 1795 bool flush = false;
8feceb67 1796 int ret = 0;
f078f209 1797
7ca7c776 1798 mutex_lock(&sc->mutex);
85ad181e 1799
8feceb67
VT		 1800 switch (action) {
1801 case IEEE80211_AMPDU_RX_START:
8feceb67
VT		 1802 break;
1803 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 1804 break;
1805 case IEEE80211_AMPDU_TX_START:
8b685ba9 1806 ath9k_ps_wakeup(sc);
231c3a1f
FF		 1807 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1808 if (!ret)
1809 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1810 ath9k_ps_restore(sc);
8feceb67 1811 break;
18b559d5
JB		 1812 case IEEE80211_AMPDU_TX_STOP_FLUSH:
1813 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
16e23428
FF		 1814 flush = true;
1815 case IEEE80211_AMPDU_TX_STOP_CONT:
8b685ba9 1816 ath9k_ps_wakeup(sc);
f83da965 1817 ath_tx_aggr_stop(sc, sta, tid);
08c96abd 1818 if (!flush)
16e23428 1819 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1820 ath9k_ps_restore(sc);
8feceb67 1821 break;
b1720231 1822 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 1823 ath9k_ps_wakeup(sc);
8469cdef 1824 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 1825 ath9k_ps_restore(sc);
8469cdef 1826 break;
8feceb67 1827 default:
3800276a 1828 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT		 1829 }
1830
7ca7c776 1831 mutex_unlock(&sc->mutex);
85ad181e 1832
8feceb67 1833 return ret;
f078f209
LR		 1834}
1835
62dad5b0
BP		 1836static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1837 struct survey_info *survey)
1838{
9ac58615 1839 struct ath_softc *sc = hw->priv;
3430098a 1840 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 1841 struct ieee80211_supported_band *sband;
3430098a 1842 struct ieee80211_channel *chan;
3430098a
FF		 1843 int pos;
1844
89f927af
LR		 1845 if (config_enabled(CONFIG_ATH9K_TX99))
1846 return -EOPNOTSUPP;
1847
b7cc9b97 1848 spin_lock_bh(&common->cc_lock);
3430098a
FF		 1849 if (idx == 0)
1850 ath_update_survey_stats(sc);
39162dbe
FF		 1851
1852 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1853 if (sband && idx >= sband->n_channels) {
1854 idx -= sband->n_channels;
1855 sband = NULL;
1856 }
62dad5b0 1857
39162dbe
FF		 1858 if (!sband)
1859 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 1860
3430098a 1861 if (!sband || idx >= sband->n_channels) {
b7cc9b97 1862 spin_unlock_bh(&common->cc_lock);
3430098a 1863 return -ENOENT;
4f1a5a4b 1864 }
62dad5b0 1865
3430098a
FF		 1866 chan = &sband->channels[idx];
1867 pos = chan->hw_value;
1868 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1869 survey->channel = chan;
b7cc9b97 1870 spin_unlock_bh(&common->cc_lock);
3430098a 1871
62dad5b0
BP		 1872 return 0;
1873}
1874
e239d859
FF		 1875static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
1876{
9ac58615 1877 struct ath_softc *sc = hw->priv;
e239d859
FF		 1878 struct ath_hw *ah = sc->sc_ah;
1879
89f927af
LR		 1880 if (config_enabled(CONFIG_ATH9K_TX99))
1881 return;
1882
e239d859
FF		 1883 mutex_lock(&sc->mutex);
1884 ah->coverage_class = coverage_class;
8b2a3827
MSS		 1885
1886 ath9k_ps_wakeup(sc);
e239d859 1887 ath9k_hw_init_global_settings(ah);
8b2a3827
MSS		 1888 ath9k_ps_restore(sc);
1889
e239d859
FF		 1890 mutex_unlock(&sc->mutex);
1891}
1892
10e23181
FF		 1893static bool ath9k_has_tx_pending(struct ath_softc *sc)
1894{
f7838073 1895 int i, npend = 0;
10e23181
FF		 1896
1897 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1898 if (!ATH_TXQ_SETUP(sc, i))
1899 continue;
1900
1901 if (!sc->tx.txq[i].axq_depth)
1902 continue;
1903
1904 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1905 if (npend)
1906 break;
1907 }
1908
1909 return !!npend;
1910}
1911
77be2c54
EG		 1912static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1913 u32 queues, bool drop)
bff11766
FF		 1914{
1915 struct ath_softc *sc = hw->priv;
1916
1917 mutex_lock(&sc->mutex);
1918 __ath9k_flush(hw, queues, drop);
1919 mutex_unlock(&sc->mutex);
1920}
1921
1922void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
69081624 1923{
69081624 1924 struct ath_softc *sc = hw->priv;
99aa55b6
MSS		 1925 struct ath_hw *ah = sc->sc_ah;
1926 struct ath_common *common = ath9k_hw_common(ah);
10e23181 1927 int timeout = HZ / 5; /* 200 ms */
2f6fc351 1928 bool drain_txq;
3ad9c386 1929 int i;
69081624 1930
69081624
VT		 1931 cancel_delayed_work_sync(&sc->tx_complete_work);
1932
6a6b3f3e 1933 if (ah->ah_flags & AH_UNPLUGGED) {
d2182b69 1934 ath_dbg(common, ANY, "Device has been unplugged!\n");
6a6b3f3e
MSS		 1935 return;
1936 }
1937
eefa01dd 1938 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
d2182b69 1939 ath_dbg(common, ANY, "Device not present\n");
99aa55b6
MSS		 1940 return;
1941 }
1942
10e23181
FF		 1943 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc),
1944 timeout) > 0)
1945 drop = false;
69081624 1946
9df0d6a2
FF		 1947 if (drop) {
1948 ath9k_ps_wakeup(sc);
1949 spin_lock_bh(&sc->sc_pcu_lock);
1381559b 1950 drain_txq = ath_drain_all_txq(sc);
9df0d6a2 1951 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440 1952
9df0d6a2 1953 if (!drain_txq)
1381559b 1954 ath_reset(sc);
9adcf440 1955
9df0d6a2 1956 ath9k_ps_restore(sc);
3ad9c386
RM		 1957 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
1958 ieee80211_wake_queue(sc->hw,
1959 sc->cur_chan->hw_queue_base + i);
1960 }
9df0d6a2 1961 }
d78f4b3e 1962
69081624 1963 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
69081624
VT		 1964}
1965
15b91e83
VN		 1966static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
1967{
1968 struct ath_softc *sc = hw->priv;
1969 int i;
1970
1971 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1972 if (!ATH_TXQ_SETUP(sc, i))
1973 continue;
1974
1975 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
1976 return true;
1977 }
1978 return false;
1979}
1980
5595f119 1981static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
ba4903f9
FF		 1982{
1983 struct ath_softc *sc = hw->priv;
1984 struct ath_hw *ah = sc->sc_ah;
1985 struct ieee80211_vif *vif;
1986 struct ath_vif *avp;
1987 struct ath_buf *bf;
1988 struct ath_tx_status ts;
4286df60 1989 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
ba4903f9
FF		 1990 int status;
1991
1992 vif = sc->beacon.bslot[0];
1993 if (!vif)
1994 return 0;
1995
aa45fe96 1996 if (!vif->bss_conf.enable_beacon)
ba4903f9
FF		 1997 return 0;
1998
aa45fe96
SM		 1999 avp = (void *)vif->drv_priv;
2000
4286df60 2001 if (!sc->beacon.tx_processed && !edma) {
ba4903f9
FF		 2002 tasklet_disable(&sc->bcon_tasklet);
2003
2004 bf = avp->av_bcbuf;
2005 if (!bf || !bf->bf_mpdu)
2006 goto skip;
2007
2008 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2009 if (status == -EINPROGRESS)
2010 goto skip;
2011
2012 sc->beacon.tx_processed = true;
2013 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2014
2015skip:
2016 tasklet_enable(&sc->bcon_tasklet);
2017 }
2018
2019 return sc->beacon.tx_last;
2020}
2021
52c94f41
MSS		 2022static int ath9k_get_stats(struct ieee80211_hw *hw,
2023 struct ieee80211_low_level_stats *stats)
2024{
2025 struct ath_softc *sc = hw->priv;
2026 struct ath_hw *ah = sc->sc_ah;
2027 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2028
2029 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2030 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2031 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2032 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2033 return 0;
2034}
2035
43c35284
FF		 2036static u32 fill_chainmask(u32 cap, u32 new)
2037{
2038 u32 filled = 0;
2039 int i;
2040
2041 for (i = 0; cap && new; i++, cap >>= 1) {
2042 if (!(cap & BIT(0)))
2043 continue;
2044
2045 if (new & BIT(0))
2046 filled |= BIT(i);
2047
2048 new >>= 1;
2049 }
2050
2051 return filled;
2052}
2053
5d9c7e3c
FF		 2054static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2055{
fea92cbf
FF		 2056 if (AR_SREV_9300_20_OR_LATER(ah))
2057 return true;
2058
5d9c7e3c
FF		 2059 switch (val & 0x7) {
2060 case 0x1:
2061 case 0x3:
2062 case 0x7:
2063 return true;
2064 case 0x2:
2065 return (ah->caps.rx_chainmask == 1);
2066 default:
2067 return false;
2068 }
2069}
2070
43c35284
FF		 2071static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2072{
2073 struct ath_softc *sc = hw->priv;
2074 struct ath_hw *ah = sc->sc_ah;
2075
5d9c7e3c
FF		 2076 if (ah->caps.rx_chainmask != 1)
2077 rx_ant |= tx_ant;
2078
2079 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
43c35284
FF		 2080 return -EINVAL;
2081
2082 sc->ant_rx = rx_ant;
2083 sc->ant_tx = tx_ant;
2084
2085 if (ah->caps.rx_chainmask == 1)
2086 return 0;
2087
2088 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2089 if (AR_SREV_9100(ah))
2090 ah->rxchainmask = 0x7;
2091 else
2092 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2093
2094 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
b57ba3b2 2095 ath9k_cmn_reload_chainmask(ah);
43c35284
FF		 2096
2097 return 0;
2098}
2099
2100static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2101{
2102 struct ath_softc *sc = hw->priv;
2103
2104 *tx_ant = sc->ant_tx;
2105 *rx_ant = sc->ant_rx;
2106 return 0;
2107}
2108
e93d083f
SW		 2109static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2110{
2111 struct ath_softc *sc = hw->priv;
eefa01dd
OR		 2112 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2113 set_bit(ATH_OP_SCANNING, &common->op_flags);
e93d083f
SW		 2114}
2115
2116static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2117{
2118 struct ath_softc *sc = hw->priv;
eefa01dd
OR		 2119 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2120 clear_bit(ATH_OP_SCANNING, &common->op_flags);
e93d083f 2121}
b11e640a 2122
78b21949 2123static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
855df36d 2124 struct ieee80211_scan_request *hw_req)
78b21949 2125{
855df36d 2126 struct cfg80211_scan_request *req = &hw_req->req;
78b21949
FF		 2127 struct ath_softc *sc = hw->priv;
2128 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2129 int ret = 0;
2130
2131 mutex_lock(&sc->mutex);
2132
2133 if (WARN_ON(sc->offchannel.scan_req)) {
2134 ret = -EBUSY;
2135 goto out;
2136 }
2137
2138 ath9k_ps_wakeup(sc);
2139 set_bit(ATH_OP_SCANNING, &common->op_flags);
2140 sc->offchannel.scan_vif = vif;
2141 sc->offchannel.scan_req = req;
2142 sc->offchannel.scan_idx = 0;
78b21949 2143
bc81d43a
SM		 2144 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2145 vif->addr);
2146
2147 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2148 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
405393cf 2149 ath_offchannel_next(sc);
bc81d43a 2150 }
78b21949
FF		 2151
2152out:
2153 mutex_unlock(&sc->mutex);
2154
2155 return ret;
2156}
2157
2158static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2159 struct ieee80211_vif *vif)
2160{
2161 struct ath_softc *sc = hw->priv;
bc81d43a
SM		 2162 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2163
2164 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
78b21949
FF		 2165
2166 mutex_lock(&sc->mutex);
2167 del_timer_sync(&sc->offchannel.timer);
2168 ath_scan_complete(sc, true);
2169 mutex_unlock(&sc->mutex);
2170}
2171
405393cf
FF		 2172static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2173 struct ieee80211_vif *vif,
2174 struct ieee80211_channel *chan, int duration,
2175 enum ieee80211_roc_type type)
2176{
2177 struct ath_softc *sc = hw->priv;
bc81d43a 2178 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
405393cf
FF		 2179 int ret = 0;
2180
2181 mutex_lock(&sc->mutex);
2182
2183 if (WARN_ON(sc->offchannel.roc_vif)) {
2184 ret = -EBUSY;
2185 goto out;
2186 }
2187
2188 ath9k_ps_wakeup(sc);
2189 sc->offchannel.roc_vif = vif;
2190 sc->offchannel.roc_chan = chan;
2191 sc->offchannel.roc_duration = duration;
2192
bc81d43a
SM		 2193 ath_dbg(common, CHAN_CTX,
2194 "RoC request on vif: %pM, type: %d duration: %d\n",
2195 vif->addr, type, duration);
2196
2197 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2198 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
405393cf 2199 ath_offchannel_next(sc);
bc81d43a 2200 }
405393cf
FF		 2201
2202out:
2203 mutex_unlock(&sc->mutex);
2204
2205 return ret;
2206}
2207
2208static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw)
2209{
2210 struct ath_softc *sc = hw->priv;
bc81d43a 2211 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
405393cf
FF		 2212
2213 mutex_lock(&sc->mutex);
2214
bc81d43a 2215 ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
405393cf
FF		 2216 del_timer_sync(&sc->offchannel.timer);
2217
2218 if (sc->offchannel.roc_vif) {
2219 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2220 ath_roc_complete(sc, true);
2221 }
2222
2223 mutex_unlock(&sc->mutex);
2224
2225 return 0;
2226}
2227
39305635
FF		 2228static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2229 struct ieee80211_chanctx_conf *conf)
2230{
2231 struct ath_softc *sc = hw->priv;
bc81d43a 2232 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635 2233 struct ath_chanctx *ctx, **ptr;
3ad9c386 2234 int pos;
39305635
FF		 2235
2236 mutex_lock(&sc->mutex);
c4dc0d04
RM		 2237
2238 ath_for_each_chanctx(sc, ctx) {
2239 if (ctx->assigned)
2240 continue;
2241
2242 ptr = (void *) conf->drv_priv;
2243 *ptr = ctx;
2244 ctx->assigned = true;
3ad9c386
RM		 2245 pos = ctx - &sc->chanctx[0];
2246 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
bc81d43a
SM		 2247
2248 ath_dbg(common, CHAN_CTX,
2249 "Add channel context: %d MHz\n",
2250 conf->def.chan->center_freq);
2251
c4dc0d04 2252 ath_chanctx_set_channel(sc, ctx, &conf->def);
39305635 2253 mutex_unlock(&sc->mutex);
c4dc0d04 2254 return 0;
39305635 2255 }
bc81d43a 2256
39305635 2257 mutex_unlock(&sc->mutex);
c4dc0d04 2258 return -ENOSPC;
39305635
FF		 2259}
2260
2261
2262static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2263 struct ieee80211_chanctx_conf *conf)
2264{
2265 struct ath_softc *sc = hw->priv;
bc81d43a 2266 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635
FF		 2267 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2268
2269 mutex_lock(&sc->mutex);
bc81d43a
SM		 2270
2271 ath_dbg(common, CHAN_CTX,
2272 "Remove channel context: %d MHz\n",
2273 conf->def.chan->center_freq);
2274
39305635 2275 ctx->assigned = false;
3ad9c386 2276 ctx->hw_queue_base = -1;
73fa2f26 2277 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
bc81d43a 2278
39305635
FF		 2279 mutex_unlock(&sc->mutex);
2280}
2281
2282static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2283 struct ieee80211_chanctx_conf *conf,
2284 u32 changed)
2285{
2286 struct ath_softc *sc = hw->priv;
bc81d43a 2287 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635
FF		 2288 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2289
2290 mutex_lock(&sc->mutex);
bc81d43a
SM		 2291 ath_dbg(common, CHAN_CTX,
2292 "Change channel context: %d MHz\n",
2293 conf->def.chan->center_freq);
39305635
FF		 2294 ath_chanctx_set_channel(sc, ctx, &conf->def);
2295 mutex_unlock(&sc->mutex);
2296}
2297
2298static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2299 struct ieee80211_vif *vif,
2300 struct ieee80211_chanctx_conf *conf)
2301{
2302 struct ath_softc *sc = hw->priv;
bc81d43a 2303 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635
FF		 2304 struct ath_vif *avp = (void *)vif->drv_priv;
2305 struct ath_chanctx *ctx = ath_chanctx_get(conf);
3ad9c386 2306 int i;
39305635
FF		 2307
2308 mutex_lock(&sc->mutex);
bc81d43a
SM		 2309
2310 ath_dbg(common, CHAN_CTX,
2311 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2312 vif->addr, vif->type, vif->p2p,
2313 conf->def.chan->center_freq);
2314
39305635
FF		 2315 avp->chanctx = ctx;
2316 list_add_tail(&avp->list, &ctx->vifs);
9a9c4fbc 2317 ath9k_calculate_summary_state(sc, ctx);
3ad9c386
RM		 2318 for (i = 0; i < IEEE80211_NUM_ACS; i++)
2319 vif->hw_queue[i] = ctx->hw_queue_base + i;
bc81d43a 2320
39305635
FF		 2321 mutex_unlock(&sc->mutex);
2322
2323 return 0;
2324}
2325
2326static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2327 struct ieee80211_vif *vif,
2328 struct ieee80211_chanctx_conf *conf)
2329{
2330 struct ath_softc *sc = hw->priv;
bc81d43a 2331 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635
FF		 2332 struct ath_vif *avp = (void *)vif->drv_priv;
2333 struct ath_chanctx *ctx = ath_chanctx_get(conf);
3ad9c386 2334 int ac;
39305635
FF		 2335
2336 mutex_lock(&sc->mutex);
bc81d43a
SM		 2337
2338 ath_dbg(common, CHAN_CTX,
2339 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2340 vif->addr, vif->type, vif->p2p,
2341 conf->def.chan->center_freq);
2342
39305635
FF		 2343 avp->chanctx = NULL;
2344 list_del(&avp->list);
9a9c4fbc 2345 ath9k_calculate_summary_state(sc, ctx);
3ad9c386
RM		 2346 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2347 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
bc81d43a 2348
39305635
FF		 2349 mutex_unlock(&sc->mutex);
2350}
2351
78b21949
FF		 2352void ath9k_fill_chanctx_ops(void)
2353{
2354 if (!ath9k_use_chanctx)
2355 return;
2356
bc81d43a
SM		 2357 ath9k_ops.hw_scan = ath9k_hw_scan;
2358 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
2359 ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
405393cf 2360 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
bc81d43a
SM		 2361 ath9k_ops.add_chanctx = ath9k_add_chanctx;
2362 ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
2363 ath9k_ops.change_chanctx = ath9k_change_chanctx;
2364 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
2365 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
2366 ath9k_ops.mgd_prepare_tx = ath9k_chanctx_force_active;
78b21949
FF		 2367}
2368
6baff7f9 2369struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2370 .tx = ath9k_tx,
2371 .start = ath9k_start,
2372 .stop = ath9k_stop,
2373 .add_interface = ath9k_add_interface,
6b3b991d 2374 .change_interface = ath9k_change_interface,
8feceb67
VT		 2375 .remove_interface = ath9k_remove_interface,
2376 .config = ath9k_config,
8feceb67 2377 .configure_filter = ath9k_configure_filter,
4ca77860
JB		 2378 .sta_add = ath9k_sta_add,
2379 .sta_remove = ath9k_sta_remove,
5519541d 2380 .sta_notify = ath9k_sta_notify,
8feceb67 2381 .conf_tx = ath9k_conf_tx,
8feceb67 2382 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2383 .set_key = ath9k_set_key,
8feceb67 2384 .get_tsf = ath9k_get_tsf,
3b5d665b 2385 .set_tsf = ath9k_set_tsf,
8feceb67 2386 .reset_tsf = ath9k_reset_tsf,
4233df6b 2387 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2388 .get_survey = ath9k_get_survey,
3b319aae 2389 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2390 .set_coverage_class = ath9k_set_coverage_class,
69081624 2391 .flush = ath9k_flush,
15b91e83 2392 .tx_frames_pending = ath9k_tx_frames_pending,
52c94f41 2393 .tx_last_beacon = ath9k_tx_last_beacon,
86a22acf 2394 .release_buffered_frames = ath9k_release_buffered_frames,
52c94f41 2395 .get_stats = ath9k_get_stats,
43c35284
FF		 2396 .set_antenna = ath9k_set_antenna,
2397 .get_antenna = ath9k_get_antenna,
b90bd9d1 2398
e60001e7 2399#ifdef CONFIG_ATH9K_WOW
b11e640a
MSS		 2400 .suspend = ath9k_suspend,
2401 .resume = ath9k_resume,
2402 .set_wakeup = ath9k_set_wakeup,
2403#endif
2404
b90bd9d1
BG		 2405#ifdef CONFIG_ATH9K_DEBUGFS
2406 .get_et_sset_count = ath9k_get_et_sset_count,
a145daf7
SM		 2407 .get_et_stats = ath9k_get_et_stats,
2408 .get_et_strings = ath9k_get_et_strings,
2409#endif
2410
1cdbaf0d 2411#if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
a145daf7 2412 .sta_add_debugfs = ath9k_sta_add_debugfs,
b90bd9d1 2413#endif
e93d083f
SW		 2414 .sw_scan_start = ath9k_sw_scan_start,
2415 .sw_scan_complete = ath9k_sw_scan_complete,
8feceb67 2416};
Linux kernel - Deliverables
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