Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
394cf0a1 | 18 | #include "ath9k.h" |
af03abec | 19 | #include "btcoex.h" |
f078f209 | 20 | |
ce111bad LR |
21 | static void ath_cache_conf_rate(struct ath_softc *sc, |
22 | struct ieee80211_conf *conf) | |
ff37e337 | 23 | { |
030bb495 LR |
24 | switch (conf->channel->band) { |
25 | case IEEE80211_BAND_2GHZ: | |
26 | if (conf_is_ht20(conf)) | |
545750d3 | 27 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT20; |
030bb495 | 28 | else if (conf_is_ht40_minus(conf)) |
545750d3 | 29 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS; |
030bb495 | 30 | else if (conf_is_ht40_plus(conf)) |
545750d3 | 31 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS; |
96742256 | 32 | else |
545750d3 | 33 | sc->cur_rate_mode = ATH9K_MODE_11G; |
030bb495 LR |
34 | break; |
35 | case IEEE80211_BAND_5GHZ: | |
36 | if (conf_is_ht20(conf)) | |
545750d3 | 37 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT20; |
030bb495 | 38 | else if (conf_is_ht40_minus(conf)) |
545750d3 | 39 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS; |
030bb495 | 40 | else if (conf_is_ht40_plus(conf)) |
545750d3 | 41 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS; |
030bb495 | 42 | else |
545750d3 | 43 | sc->cur_rate_mode = ATH9K_MODE_11A; |
030bb495 LR |
44 | break; |
45 | default: | |
ce111bad | 46 | BUG_ON(1); |
030bb495 LR |
47 | break; |
48 | } | |
ff37e337 S |
49 | } |
50 | ||
51 | static void ath_update_txpow(struct ath_softc *sc) | |
52 | { | |
cbe61d8a | 53 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
54 | u32 txpow; |
55 | ||
17d7904d S |
56 | if (sc->curtxpow != sc->config.txpowlimit) { |
57 | ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit); | |
ff37e337 S |
58 | /* read back in case value is clamped */ |
59 | ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow); | |
17d7904d | 60 | sc->curtxpow = txpow; |
ff37e337 S |
61 | } |
62 | } | |
63 | ||
64 | static u8 parse_mpdudensity(u8 mpdudensity) | |
65 | { | |
66 | /* | |
67 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
68 | * 0 for no restriction | |
69 | * 1 for 1/4 us | |
70 | * 2 for 1/2 us | |
71 | * 3 for 1 us | |
72 | * 4 for 2 us | |
73 | * 5 for 4 us | |
74 | * 6 for 8 us | |
75 | * 7 for 16 us | |
76 | */ | |
77 | switch (mpdudensity) { | |
78 | case 0: | |
79 | return 0; | |
80 | case 1: | |
81 | case 2: | |
82 | case 3: | |
83 | /* Our lower layer calculations limit our precision to | |
84 | 1 microsecond */ | |
85 | return 1; | |
86 | case 4: | |
87 | return 2; | |
88 | case 5: | |
89 | return 4; | |
90 | case 6: | |
91 | return 8; | |
92 | case 7: | |
93 | return 16; | |
94 | default: | |
95 | return 0; | |
96 | } | |
97 | } | |
98 | ||
82880a7c VT |
99 | static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc, |
100 | struct ieee80211_hw *hw) | |
101 | { | |
102 | struct ieee80211_channel *curchan = hw->conf.channel; | |
103 | struct ath9k_channel *channel; | |
104 | u8 chan_idx; | |
105 | ||
106 | chan_idx = curchan->hw_value; | |
107 | channel = &sc->sc_ah->channels[chan_idx]; | |
108 | ath9k_update_ichannel(sc, hw, channel); | |
109 | return channel; | |
110 | } | |
111 | ||
55624204 | 112 | bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
113 | { |
114 | unsigned long flags; | |
115 | bool ret; | |
116 | ||
9ecdef4b LR |
117 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
118 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
119 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
120 | |
121 | return ret; | |
122 | } | |
123 | ||
a91d75ae LR |
124 | void ath9k_ps_wakeup(struct ath_softc *sc) |
125 | { | |
126 | unsigned long flags; | |
127 | ||
128 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
129 | if (++sc->ps_usecount != 1) | |
130 | goto unlock; | |
131 | ||
9ecdef4b | 132 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae LR |
133 | |
134 | unlock: | |
135 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
136 | } | |
137 | ||
138 | void ath9k_ps_restore(struct ath_softc *sc) | |
139 | { | |
140 | unsigned long flags; | |
141 | ||
142 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
143 | if (--sc->ps_usecount != 0) | |
144 | goto unlock; | |
145 | ||
146 | if (sc->ps_enabled && | |
1b04b930 S |
147 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | |
148 | PS_WAIT_FOR_CAB | | |
149 | PS_WAIT_FOR_PSPOLL_DATA | | |
150 | PS_WAIT_FOR_TX_ACK))) | |
9ecdef4b | 151 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); |
a91d75ae LR |
152 | |
153 | unlock: | |
154 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
155 | } | |
156 | ||
ff37e337 S |
157 | /* |
158 | * Set/change channels. If the channel is really being changed, it's done | |
159 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
160 | * DMA, then restart stuff. | |
161 | */ | |
0e2dedf9 JM |
162 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, |
163 | struct ath9k_channel *hchan) | |
ff37e337 | 164 | { |
cbe61d8a | 165 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 166 | struct ath_common *common = ath9k_hw_common(ah); |
25c56eec | 167 | struct ieee80211_conf *conf = &common->hw->conf; |
ff37e337 | 168 | bool fastcc = true, stopped; |
ae8d2858 LR |
169 | struct ieee80211_channel *channel = hw->conf.channel; |
170 | int r; | |
ff37e337 S |
171 | |
172 | if (sc->sc_flags & SC_OP_INVALID) | |
173 | return -EIO; | |
174 | ||
3cbb5dd7 VN |
175 | ath9k_ps_wakeup(sc); |
176 | ||
c0d7c7af LR |
177 | /* |
178 | * This is only performed if the channel settings have | |
179 | * actually changed. | |
180 | * | |
181 | * To switch channels clear any pending DMA operations; | |
182 | * wait long enough for the RX fifo to drain, reset the | |
183 | * hardware at the new frequency, and then re-enable | |
184 | * the relevant bits of the h/w. | |
185 | */ | |
186 | ath9k_hw_set_interrupts(ah, 0); | |
043a0405 | 187 | ath_drain_all_txq(sc, false); |
c0d7c7af | 188 | stopped = ath_stoprecv(sc); |
ff37e337 | 189 | |
c0d7c7af LR |
190 | /* XXX: do not flush receive queue here. We don't want |
191 | * to flush data frames already in queue because of | |
192 | * changing channel. */ | |
ff37e337 | 193 | |
c0d7c7af LR |
194 | if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET)) |
195 | fastcc = false; | |
196 | ||
c46917bb | 197 | ath_print(common, ATH_DBG_CONFIG, |
25c56eec | 198 | "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n", |
c46917bb | 199 | sc->sc_ah->curchan->channel, |
25c56eec | 200 | channel->center_freq, conf_is_ht40(conf)); |
ff37e337 | 201 | |
c0d7c7af LR |
202 | spin_lock_bh(&sc->sc_resetlock); |
203 | ||
204 | r = ath9k_hw_reset(ah, hchan, fastcc); | |
205 | if (r) { | |
c46917bb LR |
206 | ath_print(common, ATH_DBG_FATAL, |
207 | "Unable to reset channel (%u Mhz) " | |
208 | "reset status %d\n", | |
209 | channel->center_freq, r); | |
c0d7c7af | 210 | spin_unlock_bh(&sc->sc_resetlock); |
3989279c | 211 | goto ps_restore; |
ff37e337 | 212 | } |
c0d7c7af LR |
213 | spin_unlock_bh(&sc->sc_resetlock); |
214 | ||
c0d7c7af LR |
215 | sc->sc_flags &= ~SC_OP_FULL_RESET; |
216 | ||
217 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
218 | ath_print(common, ATH_DBG_FATAL, |
219 | "Unable to restart recv logic\n"); | |
3989279c GJ |
220 | r = -EIO; |
221 | goto ps_restore; | |
c0d7c7af LR |
222 | } |
223 | ||
224 | ath_cache_conf_rate(sc, &hw->conf); | |
225 | ath_update_txpow(sc); | |
17d7904d | 226 | ath9k_hw_set_interrupts(ah, sc->imask); |
3989279c GJ |
227 | |
228 | ps_restore: | |
3cbb5dd7 | 229 | ath9k_ps_restore(sc); |
3989279c | 230 | return r; |
ff37e337 S |
231 | } |
232 | ||
233 | /* | |
234 | * This routine performs the periodic noise floor calibration function | |
235 | * that is used to adjust and optimize the chip performance. This | |
236 | * takes environmental changes (location, temperature) into account. | |
237 | * When the task is complete, it reschedules itself depending on the | |
238 | * appropriate interval that was calculated. | |
239 | */ | |
55624204 | 240 | void ath_ani_calibrate(unsigned long data) |
ff37e337 | 241 | { |
20977d3e S |
242 | struct ath_softc *sc = (struct ath_softc *)data; |
243 | struct ath_hw *ah = sc->sc_ah; | |
c46917bb | 244 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
245 | bool longcal = false; |
246 | bool shortcal = false; | |
247 | bool aniflag = false; | |
248 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
20977d3e | 249 | u32 cal_interval, short_cal_interval; |
ff37e337 | 250 | |
20977d3e S |
251 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
252 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 | 253 | |
1ffc1c61 JM |
254 | /* Only calibrate if awake */ |
255 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
256 | goto set_timer; | |
257 | ||
258 | ath9k_ps_wakeup(sc); | |
259 | ||
ff37e337 | 260 | /* Long calibration runs independently of short calibration. */ |
3d536acf | 261 | if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { |
ff37e337 | 262 | longcal = true; |
c46917bb | 263 | ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
3d536acf | 264 | common->ani.longcal_timer = timestamp; |
ff37e337 S |
265 | } |
266 | ||
17d7904d | 267 | /* Short calibration applies only while caldone is false */ |
3d536acf LR |
268 | if (!common->ani.caldone) { |
269 | if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { | |
ff37e337 | 270 | shortcal = true; |
c46917bb LR |
271 | ath_print(common, ATH_DBG_ANI, |
272 | "shortcal @%lu\n", jiffies); | |
3d536acf LR |
273 | common->ani.shortcal_timer = timestamp; |
274 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
275 | } |
276 | } else { | |
3d536acf | 277 | if ((timestamp - common->ani.resetcal_timer) >= |
ff37e337 | 278 | ATH_RESTART_CALINTERVAL) { |
3d536acf LR |
279 | common->ani.caldone = ath9k_hw_reset_calvalid(ah); |
280 | if (common->ani.caldone) | |
281 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
282 | } |
283 | } | |
284 | ||
285 | /* Verify whether we must check ANI */ | |
3d536acf | 286 | if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) { |
ff37e337 | 287 | aniflag = true; |
3d536acf | 288 | common->ani.checkani_timer = timestamp; |
ff37e337 S |
289 | } |
290 | ||
291 | /* Skip all processing if there's nothing to do. */ | |
292 | if (longcal || shortcal || aniflag) { | |
293 | /* Call ANI routine if necessary */ | |
294 | if (aniflag) | |
22e66a4c | 295 | ath9k_hw_ani_monitor(ah, ah->curchan); |
ff37e337 S |
296 | |
297 | /* Perform calibration if necessary */ | |
298 | if (longcal || shortcal) { | |
3d536acf | 299 | common->ani.caldone = |
43c27613 LR |
300 | ath9k_hw_calibrate(ah, |
301 | ah->curchan, | |
302 | common->rx_chainmask, | |
303 | longcal); | |
379f0440 S |
304 | |
305 | if (longcal) | |
3d536acf | 306 | common->ani.noise_floor = ath9k_hw_getchan_noise(ah, |
379f0440 S |
307 | ah->curchan); |
308 | ||
c46917bb LR |
309 | ath_print(common, ATH_DBG_ANI, |
310 | " calibrate chan %u/%x nf: %d\n", | |
311 | ah->curchan->channel, | |
312 | ah->curchan->channelFlags, | |
3d536acf | 313 | common->ani.noise_floor); |
ff37e337 S |
314 | } |
315 | } | |
316 | ||
1ffc1c61 JM |
317 | ath9k_ps_restore(sc); |
318 | ||
20977d3e | 319 | set_timer: |
ff37e337 S |
320 | /* |
321 | * Set timer interval based on previous results. | |
322 | * The interval must be the shortest necessary to satisfy ANI, | |
323 | * short calibration and long calibration. | |
324 | */ | |
aac9207e | 325 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 326 | if (sc->sc_ah->config.enable_ani) |
aac9207e | 327 | cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL); |
3d536acf | 328 | if (!common->ani.caldone) |
20977d3e | 329 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 330 | |
3d536acf | 331 | mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
ff37e337 S |
332 | } |
333 | ||
3d536acf | 334 | static void ath_start_ani(struct ath_common *common) |
415f738e S |
335 | { |
336 | unsigned long timestamp = jiffies_to_msecs(jiffies); | |
337 | ||
3d536acf LR |
338 | common->ani.longcal_timer = timestamp; |
339 | common->ani.shortcal_timer = timestamp; | |
340 | common->ani.checkani_timer = timestamp; | |
415f738e | 341 | |
3d536acf | 342 | mod_timer(&common->ani.timer, |
415f738e S |
343 | jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL)); |
344 | } | |
345 | ||
ff37e337 S |
346 | /* |
347 | * Update tx/rx chainmask. For legacy association, | |
348 | * hard code chainmask to 1x1, for 11n association, use | |
c97c92d9 VT |
349 | * the chainmask configuration, for bt coexistence, use |
350 | * the chainmask configuration even in legacy mode. | |
ff37e337 | 351 | */ |
0e2dedf9 | 352 | void ath_update_chainmask(struct ath_softc *sc, int is_ht) |
ff37e337 | 353 | { |
af03abec | 354 | struct ath_hw *ah = sc->sc_ah; |
43c27613 | 355 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 356 | |
3d832611 | 357 | if ((sc->sc_flags & SC_OP_SCANNING) || is_ht || |
766ec4a9 | 358 | (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) { |
43c27613 LR |
359 | common->tx_chainmask = ah->caps.tx_chainmask; |
360 | common->rx_chainmask = ah->caps.rx_chainmask; | |
ff37e337 | 361 | } else { |
43c27613 LR |
362 | common->tx_chainmask = 1; |
363 | common->rx_chainmask = 1; | |
ff37e337 S |
364 | } |
365 | ||
43c27613 | 366 | ath_print(common, ATH_DBG_CONFIG, |
c46917bb | 367 | "tx chmask: %d, rx chmask: %d\n", |
43c27613 LR |
368 | common->tx_chainmask, |
369 | common->rx_chainmask); | |
ff37e337 S |
370 | } |
371 | ||
372 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
373 | { | |
374 | struct ath_node *an; | |
375 | ||
376 | an = (struct ath_node *)sta->drv_priv; | |
377 | ||
87792efc | 378 | if (sc->sc_flags & SC_OP_TXAGGR) { |
ff37e337 | 379 | ath_tx_node_init(sc, an); |
9e98ac65 | 380 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc S |
381 | sta->ht_cap.ampdu_factor); |
382 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
a59b5a5e | 383 | an->last_rssi = ATH_RSSI_DUMMY_MARKER; |
87792efc | 384 | } |
ff37e337 S |
385 | } |
386 | ||
387 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
388 | { | |
389 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
390 | ||
391 | if (sc->sc_flags & SC_OP_TXAGGR) | |
392 | ath_tx_node_cleanup(sc, an); | |
393 | } | |
394 | ||
55624204 | 395 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
396 | { |
397 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 398 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 399 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 400 | |
17d7904d | 401 | u32 status = sc->intrstatus; |
ff37e337 | 402 | |
153e080d VT |
403 | ath9k_ps_wakeup(sc); |
404 | ||
ff37e337 | 405 | if (status & ATH9K_INT_FATAL) { |
ff37e337 | 406 | ath_reset(sc, false); |
153e080d | 407 | ath9k_ps_restore(sc); |
ff37e337 | 408 | return; |
063d8be3 | 409 | } |
ff37e337 | 410 | |
063d8be3 S |
411 | if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) { |
412 | spin_lock_bh(&sc->rx.rxflushlock); | |
413 | ath_rx_tasklet(sc, 0); | |
414 | spin_unlock_bh(&sc->rx.rxflushlock); | |
ff37e337 S |
415 | } |
416 | ||
063d8be3 S |
417 | if (status & ATH9K_INT_TX) |
418 | ath_tx_tasklet(sc); | |
419 | ||
96148326 | 420 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
54ce846e JM |
421 | /* |
422 | * TSF sync does not look correct; remain awake to sync with | |
423 | * the next Beacon. | |
424 | */ | |
c46917bb LR |
425 | ath_print(common, ATH_DBG_PS, |
426 | "TSFOOR - Sync with next Beacon\n"); | |
1b04b930 | 427 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
54ce846e JM |
428 | } |
429 | ||
766ec4a9 | 430 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
ebb8e1d7 VT |
431 | if (status & ATH9K_INT_GENTIMER) |
432 | ath_gen_timer_isr(sc->sc_ah); | |
433 | ||
ff37e337 | 434 | /* re-enable hardware interrupt */ |
af03abec | 435 | ath9k_hw_set_interrupts(ah, sc->imask); |
153e080d | 436 | ath9k_ps_restore(sc); |
ff37e337 S |
437 | } |
438 | ||
6baff7f9 | 439 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 440 | { |
063d8be3 S |
441 | #define SCHED_INTR ( \ |
442 | ATH9K_INT_FATAL | \ | |
443 | ATH9K_INT_RXORN | \ | |
444 | ATH9K_INT_RXEOL | \ | |
445 | ATH9K_INT_RX | \ | |
446 | ATH9K_INT_TX | \ | |
447 | ATH9K_INT_BMISS | \ | |
448 | ATH9K_INT_CST | \ | |
ebb8e1d7 VT |
449 | ATH9K_INT_TSFOOR | \ |
450 | ATH9K_INT_GENTIMER) | |
063d8be3 | 451 | |
ff37e337 | 452 | struct ath_softc *sc = dev; |
cbe61d8a | 453 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
454 | enum ath9k_int status; |
455 | bool sched = false; | |
456 | ||
063d8be3 S |
457 | /* |
458 | * The hardware is not ready/present, don't | |
459 | * touch anything. Note this can happen early | |
460 | * on if the IRQ is shared. | |
461 | */ | |
462 | if (sc->sc_flags & SC_OP_INVALID) | |
463 | return IRQ_NONE; | |
ff37e337 | 464 | |
063d8be3 S |
465 | |
466 | /* shared irq, not for us */ | |
467 | ||
153e080d | 468 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 469 | return IRQ_NONE; |
063d8be3 S |
470 | |
471 | /* | |
472 | * Figure out the reason(s) for the interrupt. Note | |
473 | * that the hal returns a pseudo-ISR that may include | |
474 | * bits we haven't explicitly enabled so we mask the | |
475 | * value to insure we only process bits we requested. | |
476 | */ | |
477 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
478 | status &= sc->imask; /* discard unasked-for bits */ | |
ff37e337 | 479 | |
063d8be3 S |
480 | /* |
481 | * If there are no status bits set, then this interrupt was not | |
482 | * for me (should have been caught above). | |
483 | */ | |
153e080d | 484 | if (!status) |
063d8be3 | 485 | return IRQ_NONE; |
ff37e337 | 486 | |
063d8be3 S |
487 | /* Cache the status */ |
488 | sc->intrstatus = status; | |
489 | ||
490 | if (status & SCHED_INTR) | |
491 | sched = true; | |
492 | ||
493 | /* | |
494 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
495 | * chip immediately. | |
496 | */ | |
497 | if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN)) | |
498 | goto chip_reset; | |
499 | ||
500 | if (status & ATH9K_INT_SWBA) | |
501 | tasklet_schedule(&sc->bcon_tasklet); | |
502 | ||
503 | if (status & ATH9K_INT_TXURN) | |
504 | ath9k_hw_updatetxtriglevel(ah, true); | |
505 | ||
506 | if (status & ATH9K_INT_MIB) { | |
ff37e337 | 507 | /* |
063d8be3 S |
508 | * Disable interrupts until we service the MIB |
509 | * interrupt; otherwise it will continue to | |
510 | * fire. | |
ff37e337 | 511 | */ |
063d8be3 S |
512 | ath9k_hw_set_interrupts(ah, 0); |
513 | /* | |
514 | * Let the hal handle the event. We assume | |
515 | * it will clear whatever condition caused | |
516 | * the interrupt. | |
517 | */ | |
22e66a4c | 518 | ath9k_hw_procmibevent(ah); |
063d8be3 S |
519 | ath9k_hw_set_interrupts(ah, sc->imask); |
520 | } | |
ff37e337 | 521 | |
153e080d VT |
522 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
523 | if (status & ATH9K_INT_TIM_TIMER) { | |
063d8be3 S |
524 | /* Clear RxAbort bit so that we can |
525 | * receive frames */ | |
9ecdef4b | 526 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
153e080d | 527 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 528 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
ff37e337 | 529 | } |
063d8be3 S |
530 | |
531 | chip_reset: | |
ff37e337 | 532 | |
817e11de S |
533 | ath_debug_stat_interrupt(sc, status); |
534 | ||
ff37e337 S |
535 | if (sched) { |
536 | /* turn off every interrupt except SWBA */ | |
17d7904d | 537 | ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA)); |
ff37e337 S |
538 | tasklet_schedule(&sc->intr_tq); |
539 | } | |
540 | ||
541 | return IRQ_HANDLED; | |
063d8be3 S |
542 | |
543 | #undef SCHED_INTR | |
ff37e337 S |
544 | } |
545 | ||
f078f209 | 546 | static u32 ath_get_extchanmode(struct ath_softc *sc, |
99405f93 | 547 | struct ieee80211_channel *chan, |
094d05dc | 548 | enum nl80211_channel_type channel_type) |
f078f209 LR |
549 | { |
550 | u32 chanmode = 0; | |
f078f209 LR |
551 | |
552 | switch (chan->band) { | |
553 | case IEEE80211_BAND_2GHZ: | |
094d05dc S |
554 | switch(channel_type) { |
555 | case NL80211_CHAN_NO_HT: | |
556 | case NL80211_CHAN_HT20: | |
f078f209 | 557 | chanmode = CHANNEL_G_HT20; |
094d05dc S |
558 | break; |
559 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 560 | chanmode = CHANNEL_G_HT40PLUS; |
094d05dc S |
561 | break; |
562 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 563 | chanmode = CHANNEL_G_HT40MINUS; |
094d05dc S |
564 | break; |
565 | } | |
f078f209 LR |
566 | break; |
567 | case IEEE80211_BAND_5GHZ: | |
094d05dc S |
568 | switch(channel_type) { |
569 | case NL80211_CHAN_NO_HT: | |
570 | case NL80211_CHAN_HT20: | |
f078f209 | 571 | chanmode = CHANNEL_A_HT20; |
094d05dc S |
572 | break; |
573 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 574 | chanmode = CHANNEL_A_HT40PLUS; |
094d05dc S |
575 | break; |
576 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 577 | chanmode = CHANNEL_A_HT40MINUS; |
094d05dc S |
578 | break; |
579 | } | |
f078f209 LR |
580 | break; |
581 | default: | |
582 | break; | |
583 | } | |
584 | ||
585 | return chanmode; | |
586 | } | |
587 | ||
7e86c104 | 588 | static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key, |
3f53dd64 JM |
589 | struct ath9k_keyval *hk, const u8 *addr, |
590 | bool authenticator) | |
f078f209 | 591 | { |
7e86c104 | 592 | struct ath_hw *ah = common->ah; |
6ace2891 JM |
593 | const u8 *key_rxmic; |
594 | const u8 *key_txmic; | |
f078f209 | 595 | |
6ace2891 JM |
596 | key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY; |
597 | key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY; | |
f078f209 LR |
598 | |
599 | if (addr == NULL) { | |
d216aaa6 JM |
600 | /* |
601 | * Group key installation - only two key cache entries are used | |
602 | * regardless of splitmic capability since group key is only | |
603 | * used either for TX or RX. | |
604 | */ | |
3f53dd64 JM |
605 | if (authenticator) { |
606 | memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); | |
607 | memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic)); | |
608 | } else { | |
609 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); | |
610 | memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic)); | |
611 | } | |
7e86c104 | 612 | return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr); |
f078f209 | 613 | } |
7e86c104 | 614 | if (!common->splitmic) { |
d216aaa6 | 615 | /* TX and RX keys share the same key cache entry. */ |
f078f209 LR |
616 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); |
617 | memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic)); | |
7e86c104 | 618 | return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr); |
f078f209 | 619 | } |
d216aaa6 JM |
620 | |
621 | /* Separate key cache entries for TX and RX */ | |
622 | ||
623 | /* TX key goes at first index, RX key at +32. */ | |
f078f209 | 624 | memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); |
7e86c104 | 625 | if (!ath9k_hw_set_keycache_entry(ah, keyix, hk, NULL)) { |
d216aaa6 | 626 | /* TX MIC entry failed. No need to proceed further */ |
7e86c104 | 627 | ath_print(common, ATH_DBG_FATAL, |
c46917bb | 628 | "Setting TX MIC Key Failed\n"); |
f078f209 LR |
629 | return 0; |
630 | } | |
631 | ||
632 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); | |
633 | /* XXX delete tx key on failure? */ | |
7e86c104 | 634 | return ath9k_hw_set_keycache_entry(ah, keyix + 32, hk, addr); |
6ace2891 JM |
635 | } |
636 | ||
7e86c104 | 637 | static int ath_reserve_key_cache_slot_tkip(struct ath_common *common) |
6ace2891 JM |
638 | { |
639 | int i; | |
640 | ||
7e86c104 LR |
641 | for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) { |
642 | if (test_bit(i, common->keymap) || | |
643 | test_bit(i + 64, common->keymap)) | |
6ace2891 | 644 | continue; /* At least one part of TKIP key allocated */ |
7e86c104 LR |
645 | if (common->splitmic && |
646 | (test_bit(i + 32, common->keymap) || | |
647 | test_bit(i + 64 + 32, common->keymap))) | |
6ace2891 JM |
648 | continue; /* At least one part of TKIP key allocated */ |
649 | ||
650 | /* Found a free slot for a TKIP key */ | |
651 | return i; | |
652 | } | |
653 | return -1; | |
654 | } | |
655 | ||
7e86c104 | 656 | static int ath_reserve_key_cache_slot(struct ath_common *common) |
6ace2891 JM |
657 | { |
658 | int i; | |
659 | ||
660 | /* First, try to find slots that would not be available for TKIP. */ | |
7e86c104 LR |
661 | if (common->splitmic) { |
662 | for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) { | |
663 | if (!test_bit(i, common->keymap) && | |
664 | (test_bit(i + 32, common->keymap) || | |
665 | test_bit(i + 64, common->keymap) || | |
666 | test_bit(i + 64 + 32, common->keymap))) | |
6ace2891 | 667 | return i; |
7e86c104 LR |
668 | if (!test_bit(i + 32, common->keymap) && |
669 | (test_bit(i, common->keymap) || | |
670 | test_bit(i + 64, common->keymap) || | |
671 | test_bit(i + 64 + 32, common->keymap))) | |
6ace2891 | 672 | return i + 32; |
7e86c104 LR |
673 | if (!test_bit(i + 64, common->keymap) && |
674 | (test_bit(i , common->keymap) || | |
675 | test_bit(i + 32, common->keymap) || | |
676 | test_bit(i + 64 + 32, common->keymap))) | |
ea612132 | 677 | return i + 64; |
7e86c104 LR |
678 | if (!test_bit(i + 64 + 32, common->keymap) && |
679 | (test_bit(i, common->keymap) || | |
680 | test_bit(i + 32, common->keymap) || | |
681 | test_bit(i + 64, common->keymap))) | |
ea612132 | 682 | return i + 64 + 32; |
6ace2891 JM |
683 | } |
684 | } else { | |
7e86c104 LR |
685 | for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) { |
686 | if (!test_bit(i, common->keymap) && | |
687 | test_bit(i + 64, common->keymap)) | |
6ace2891 | 688 | return i; |
7e86c104 LR |
689 | if (test_bit(i, common->keymap) && |
690 | !test_bit(i + 64, common->keymap)) | |
6ace2891 JM |
691 | return i + 64; |
692 | } | |
693 | } | |
694 | ||
695 | /* No partially used TKIP slots, pick any available slot */ | |
7e86c104 | 696 | for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) { |
be2864cf JM |
697 | /* Do not allow slots that could be needed for TKIP group keys |
698 | * to be used. This limitation could be removed if we know that | |
699 | * TKIP will not be used. */ | |
700 | if (i >= 64 && i < 64 + IEEE80211_WEP_NKID) | |
701 | continue; | |
7e86c104 | 702 | if (common->splitmic) { |
be2864cf JM |
703 | if (i >= 32 && i < 32 + IEEE80211_WEP_NKID) |
704 | continue; | |
705 | if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID) | |
706 | continue; | |
707 | } | |
708 | ||
7e86c104 | 709 | if (!test_bit(i, common->keymap)) |
6ace2891 JM |
710 | return i; /* Found a free slot for a key */ |
711 | } | |
712 | ||
713 | /* No free slot found */ | |
714 | return -1; | |
f078f209 LR |
715 | } |
716 | ||
7e86c104 | 717 | static int ath_key_config(struct ath_common *common, |
3f53dd64 | 718 | struct ieee80211_vif *vif, |
dc822b5d | 719 | struct ieee80211_sta *sta, |
f078f209 LR |
720 | struct ieee80211_key_conf *key) |
721 | { | |
7e86c104 | 722 | struct ath_hw *ah = common->ah; |
f078f209 LR |
723 | struct ath9k_keyval hk; |
724 | const u8 *mac = NULL; | |
725 | int ret = 0; | |
6ace2891 | 726 | int idx; |
f078f209 LR |
727 | |
728 | memset(&hk, 0, sizeof(hk)); | |
729 | ||
730 | switch (key->alg) { | |
731 | case ALG_WEP: | |
732 | hk.kv_type = ATH9K_CIPHER_WEP; | |
733 | break; | |
734 | case ALG_TKIP: | |
735 | hk.kv_type = ATH9K_CIPHER_TKIP; | |
736 | break; | |
737 | case ALG_CCMP: | |
738 | hk.kv_type = ATH9K_CIPHER_AES_CCM; | |
739 | break; | |
740 | default: | |
ca470b29 | 741 | return -EOPNOTSUPP; |
f078f209 LR |
742 | } |
743 | ||
6ace2891 | 744 | hk.kv_len = key->keylen; |
f078f209 LR |
745 | memcpy(hk.kv_val, key->key, key->keylen); |
746 | ||
6ace2891 JM |
747 | if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { |
748 | /* For now, use the default keys for broadcast keys. This may | |
749 | * need to change with virtual interfaces. */ | |
750 | idx = key->keyidx; | |
751 | } else if (key->keyidx) { | |
dc822b5d JB |
752 | if (WARN_ON(!sta)) |
753 | return -EOPNOTSUPP; | |
754 | mac = sta->addr; | |
755 | ||
6ace2891 JM |
756 | if (vif->type != NL80211_IFTYPE_AP) { |
757 | /* Only keyidx 0 should be used with unicast key, but | |
758 | * allow this for client mode for now. */ | |
759 | idx = key->keyidx; | |
760 | } else | |
761 | return -EIO; | |
f078f209 | 762 | } else { |
dc822b5d JB |
763 | if (WARN_ON(!sta)) |
764 | return -EOPNOTSUPP; | |
765 | mac = sta->addr; | |
766 | ||
6ace2891 | 767 | if (key->alg == ALG_TKIP) |
7e86c104 | 768 | idx = ath_reserve_key_cache_slot_tkip(common); |
6ace2891 | 769 | else |
7e86c104 | 770 | idx = ath_reserve_key_cache_slot(common); |
6ace2891 | 771 | if (idx < 0) |
ca470b29 | 772 | return -ENOSPC; /* no free key cache entries */ |
f078f209 LR |
773 | } |
774 | ||
775 | if (key->alg == ALG_TKIP) | |
7e86c104 | 776 | ret = ath_setkey_tkip(common, idx, key->key, &hk, mac, |
3f53dd64 | 777 | vif->type == NL80211_IFTYPE_AP); |
f078f209 | 778 | else |
7e86c104 | 779 | ret = ath9k_hw_set_keycache_entry(ah, idx, &hk, mac); |
f078f209 LR |
780 | |
781 | if (!ret) | |
782 | return -EIO; | |
783 | ||
7e86c104 | 784 | set_bit(idx, common->keymap); |
6ace2891 | 785 | if (key->alg == ALG_TKIP) { |
7e86c104 LR |
786 | set_bit(idx + 64, common->keymap); |
787 | if (common->splitmic) { | |
788 | set_bit(idx + 32, common->keymap); | |
789 | set_bit(idx + 64 + 32, common->keymap); | |
6ace2891 JM |
790 | } |
791 | } | |
792 | ||
793 | return idx; | |
f078f209 LR |
794 | } |
795 | ||
7e86c104 | 796 | static void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key) |
f078f209 | 797 | { |
7e86c104 LR |
798 | struct ath_hw *ah = common->ah; |
799 | ||
800 | ath9k_hw_keyreset(ah, key->hw_key_idx); | |
6ace2891 JM |
801 | if (key->hw_key_idx < IEEE80211_WEP_NKID) |
802 | return; | |
803 | ||
7e86c104 | 804 | clear_bit(key->hw_key_idx, common->keymap); |
6ace2891 JM |
805 | if (key->alg != ALG_TKIP) |
806 | return; | |
f078f209 | 807 | |
7e86c104 LR |
808 | clear_bit(key->hw_key_idx + 64, common->keymap); |
809 | if (common->splitmic) { | |
810 | clear_bit(key->hw_key_idx + 32, common->keymap); | |
811 | clear_bit(key->hw_key_idx + 64 + 32, common->keymap); | |
6ace2891 | 812 | } |
f078f209 LR |
813 | } |
814 | ||
8feceb67 | 815 | static void ath9k_bss_assoc_info(struct ath_softc *sc, |
5640b08e | 816 | struct ieee80211_vif *vif, |
8feceb67 | 817 | struct ieee80211_bss_conf *bss_conf) |
f078f209 | 818 | { |
f2b2143e | 819 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 820 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 821 | |
8feceb67 | 822 | if (bss_conf->assoc) { |
c46917bb LR |
823 | ath_print(common, ATH_DBG_CONFIG, |
824 | "Bss Info ASSOC %d, bssid: %pM\n", | |
825 | bss_conf->aid, common->curbssid); | |
f078f209 | 826 | |
8feceb67 | 827 | /* New association, store aid */ |
1510718d | 828 | common->curaid = bss_conf->aid; |
f2b2143e | 829 | ath9k_hw_write_associd(ah); |
2664f201 SB |
830 | |
831 | /* | |
832 | * Request a re-configuration of Beacon related timers | |
833 | * on the receipt of the first Beacon frame (i.e., | |
834 | * after time sync with the AP). | |
835 | */ | |
1b04b930 | 836 | sc->ps_flags |= PS_BEACON_SYNC; |
f078f209 | 837 | |
8feceb67 | 838 | /* Configure the beacon */ |
2c3db3d5 | 839 | ath_beacon_config(sc, vif); |
f078f209 | 840 | |
8feceb67 | 841 | /* Reset rssi stats */ |
22e66a4c | 842 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; |
f078f209 | 843 | |
3d536acf | 844 | ath_start_ani(common); |
8feceb67 | 845 | } else { |
c46917bb | 846 | ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); |
1510718d | 847 | common->curaid = 0; |
f38faa31 | 848 | /* Stop ANI */ |
3d536acf | 849 | del_timer_sync(&common->ani.timer); |
f078f209 | 850 | } |
8feceb67 | 851 | } |
f078f209 | 852 | |
68a89116 | 853 | void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 854 | { |
cbe61d8a | 855 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 856 | struct ath_common *common = ath9k_hw_common(ah); |
68a89116 | 857 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 858 | int r; |
500c064d | 859 | |
3cbb5dd7 | 860 | ath9k_ps_wakeup(sc); |
93b1b37f | 861 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ae8d2858 | 862 | |
159cd468 VT |
863 | if (!ah->curchan) |
864 | ah->curchan = ath_get_curchannel(sc, sc->hw); | |
865 | ||
d2f5b3a6 | 866 | spin_lock_bh(&sc->sc_resetlock); |
2660b81a | 867 | r = ath9k_hw_reset(ah, ah->curchan, false); |
ae8d2858 | 868 | if (r) { |
c46917bb LR |
869 | ath_print(common, ATH_DBG_FATAL, |
870 | "Unable to reset channel %u (%uMhz) ", | |
871 | "reset status %d\n", | |
872 | channel->center_freq, r); | |
500c064d VT |
873 | } |
874 | spin_unlock_bh(&sc->sc_resetlock); | |
875 | ||
876 | ath_update_txpow(sc); | |
877 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
878 | ath_print(common, ATH_DBG_FATAL, |
879 | "Unable to restart recv logic\n"); | |
500c064d VT |
880 | return; |
881 | } | |
882 | ||
883 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 884 | ath_beacon_config(sc, NULL); /* restart beacons */ |
500c064d VT |
885 | |
886 | /* Re-Enable interrupts */ | |
17d7904d | 887 | ath9k_hw_set_interrupts(ah, sc->imask); |
500c064d VT |
888 | |
889 | /* Enable LED */ | |
08fc5c1b | 890 | ath9k_hw_cfg_output(ah, ah->led_pin, |
500c064d | 891 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
08fc5c1b | 892 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); |
500c064d | 893 | |
68a89116 | 894 | ieee80211_wake_queues(hw); |
3cbb5dd7 | 895 | ath9k_ps_restore(sc); |
500c064d VT |
896 | } |
897 | ||
68a89116 | 898 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 899 | { |
cbe61d8a | 900 | struct ath_hw *ah = sc->sc_ah; |
68a89116 | 901 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 902 | int r; |
500c064d | 903 | |
3cbb5dd7 | 904 | ath9k_ps_wakeup(sc); |
68a89116 | 905 | ieee80211_stop_queues(hw); |
500c064d VT |
906 | |
907 | /* Disable LED */ | |
08fc5c1b VN |
908 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); |
909 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
500c064d VT |
910 | |
911 | /* Disable interrupts */ | |
912 | ath9k_hw_set_interrupts(ah, 0); | |
913 | ||
043a0405 | 914 | ath_drain_all_txq(sc, false); /* clear pending tx frames */ |
500c064d VT |
915 | ath_stoprecv(sc); /* turn off frame recv */ |
916 | ath_flushrecv(sc); /* flush recv queue */ | |
917 | ||
159cd468 | 918 | if (!ah->curchan) |
68a89116 | 919 | ah->curchan = ath_get_curchannel(sc, hw); |
159cd468 | 920 | |
500c064d | 921 | spin_lock_bh(&sc->sc_resetlock); |
2660b81a | 922 | r = ath9k_hw_reset(ah, ah->curchan, false); |
ae8d2858 | 923 | if (r) { |
c46917bb LR |
924 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
925 | "Unable to reset channel %u (%uMhz) " | |
926 | "reset status %d\n", | |
927 | channel->center_freq, r); | |
500c064d VT |
928 | } |
929 | spin_unlock_bh(&sc->sc_resetlock); | |
930 | ||
931 | ath9k_hw_phy_disable(ah); | |
93b1b37f | 932 | ath9k_hw_configpcipowersave(ah, 1, 1); |
3cbb5dd7 | 933 | ath9k_ps_restore(sc); |
9ecdef4b | 934 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
500c064d VT |
935 | } |
936 | ||
ff37e337 S |
937 | int ath_reset(struct ath_softc *sc, bool retry_tx) |
938 | { | |
cbe61d8a | 939 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 940 | struct ath_common *common = ath9k_hw_common(ah); |
030bb495 | 941 | struct ieee80211_hw *hw = sc->hw; |
ae8d2858 | 942 | int r; |
ff37e337 | 943 | |
2ab81d4a S |
944 | /* Stop ANI */ |
945 | del_timer_sync(&common->ani.timer); | |
946 | ||
ff37e337 | 947 | ath9k_hw_set_interrupts(ah, 0); |
043a0405 | 948 | ath_drain_all_txq(sc, retry_tx); |
ff37e337 S |
949 | ath_stoprecv(sc); |
950 | ath_flushrecv(sc); | |
951 | ||
952 | spin_lock_bh(&sc->sc_resetlock); | |
2660b81a | 953 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false); |
ae8d2858 | 954 | if (r) |
c46917bb LR |
955 | ath_print(common, ATH_DBG_FATAL, |
956 | "Unable to reset hardware; reset status %d\n", r); | |
ff37e337 S |
957 | spin_unlock_bh(&sc->sc_resetlock); |
958 | ||
959 | if (ath_startrecv(sc) != 0) | |
c46917bb LR |
960 | ath_print(common, ATH_DBG_FATAL, |
961 | "Unable to start recv logic\n"); | |
ff37e337 S |
962 | |
963 | /* | |
964 | * We may be doing a reset in response to a request | |
965 | * that changes the channel so update any state that | |
966 | * might change as a result. | |
967 | */ | |
ce111bad | 968 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
969 | |
970 | ath_update_txpow(sc); | |
971 | ||
972 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 973 | ath_beacon_config(sc, NULL); /* restart beacons */ |
ff37e337 | 974 | |
17d7904d | 975 | ath9k_hw_set_interrupts(ah, sc->imask); |
ff37e337 S |
976 | |
977 | if (retry_tx) { | |
978 | int i; | |
979 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
980 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
981 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
982 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
983 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
984 | } |
985 | } | |
986 | } | |
987 | ||
2ab81d4a S |
988 | /* Start ANI */ |
989 | ath_start_ani(common); | |
990 | ||
ae8d2858 | 991 | return r; |
ff37e337 S |
992 | } |
993 | ||
ff37e337 S |
994 | int ath_get_hal_qnum(u16 queue, struct ath_softc *sc) |
995 | { | |
996 | int qnum; | |
997 | ||
998 | switch (queue) { | |
999 | case 0: | |
b77f483f | 1000 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO]; |
ff37e337 S |
1001 | break; |
1002 | case 1: | |
b77f483f | 1003 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI]; |
ff37e337 S |
1004 | break; |
1005 | case 2: | |
b77f483f | 1006 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE]; |
ff37e337 S |
1007 | break; |
1008 | case 3: | |
b77f483f | 1009 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK]; |
ff37e337 S |
1010 | break; |
1011 | default: | |
b77f483f | 1012 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE]; |
ff37e337 S |
1013 | break; |
1014 | } | |
1015 | ||
1016 | return qnum; | |
1017 | } | |
1018 | ||
1019 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc) | |
1020 | { | |
1021 | int qnum; | |
1022 | ||
1023 | switch (queue) { | |
1024 | case ATH9K_WME_AC_VO: | |
1025 | qnum = 0; | |
1026 | break; | |
1027 | case ATH9K_WME_AC_VI: | |
1028 | qnum = 1; | |
1029 | break; | |
1030 | case ATH9K_WME_AC_BE: | |
1031 | qnum = 2; | |
1032 | break; | |
1033 | case ATH9K_WME_AC_BK: | |
1034 | qnum = 3; | |
1035 | break; | |
1036 | default: | |
1037 | qnum = -1; | |
1038 | break; | |
1039 | } | |
1040 | ||
1041 | return qnum; | |
1042 | } | |
1043 | ||
5f8e077c LR |
1044 | /* XXX: Remove me once we don't depend on ath9k_channel for all |
1045 | * this redundant data */ | |
0e2dedf9 JM |
1046 | void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, |
1047 | struct ath9k_channel *ichan) | |
5f8e077c | 1048 | { |
5f8e077c LR |
1049 | struct ieee80211_channel *chan = hw->conf.channel; |
1050 | struct ieee80211_conf *conf = &hw->conf; | |
1051 | ||
1052 | ichan->channel = chan->center_freq; | |
1053 | ichan->chan = chan; | |
1054 | ||
1055 | if (chan->band == IEEE80211_BAND_2GHZ) { | |
1056 | ichan->chanmode = CHANNEL_G; | |
8813262e | 1057 | ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G; |
5f8e077c LR |
1058 | } else { |
1059 | ichan->chanmode = CHANNEL_A; | |
1060 | ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM; | |
1061 | } | |
1062 | ||
25c56eec | 1063 | if (conf_is_ht(conf)) |
5f8e077c LR |
1064 | ichan->chanmode = ath_get_extchanmode(sc, chan, |
1065 | conf->channel_type); | |
5f8e077c LR |
1066 | } |
1067 | ||
ff37e337 S |
1068 | /**********************/ |
1069 | /* mac80211 callbacks */ | |
1070 | /**********************/ | |
1071 | ||
8feceb67 | 1072 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 1073 | { |
bce048d7 JM |
1074 | struct ath_wiphy *aphy = hw->priv; |
1075 | struct ath_softc *sc = aphy->sc; | |
af03abec | 1076 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1077 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 1078 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 1079 | struct ath9k_channel *init_channel; |
82880a7c | 1080 | int r; |
f078f209 | 1081 | |
c46917bb LR |
1082 | ath_print(common, ATH_DBG_CONFIG, |
1083 | "Starting driver with initial channel: %d MHz\n", | |
1084 | curchan->center_freq); | |
f078f209 | 1085 | |
141b38b6 S |
1086 | mutex_lock(&sc->mutex); |
1087 | ||
9580a222 JM |
1088 | if (ath9k_wiphy_started(sc)) { |
1089 | if (sc->chan_idx == curchan->hw_value) { | |
1090 | /* | |
1091 | * Already on the operational channel, the new wiphy | |
1092 | * can be marked active. | |
1093 | */ | |
1094 | aphy->state = ATH_WIPHY_ACTIVE; | |
1095 | ieee80211_wake_queues(hw); | |
1096 | } else { | |
1097 | /* | |
1098 | * Another wiphy is on another channel, start the new | |
1099 | * wiphy in paused state. | |
1100 | */ | |
1101 | aphy->state = ATH_WIPHY_PAUSED; | |
1102 | ieee80211_stop_queues(hw); | |
1103 | } | |
1104 | mutex_unlock(&sc->mutex); | |
1105 | return 0; | |
1106 | } | |
1107 | aphy->state = ATH_WIPHY_ACTIVE; | |
1108 | ||
8feceb67 | 1109 | /* setup initial channel */ |
f078f209 | 1110 | |
82880a7c | 1111 | sc->chan_idx = curchan->hw_value; |
f078f209 | 1112 | |
82880a7c | 1113 | init_channel = ath_get_curchannel(sc, hw); |
ff37e337 S |
1114 | |
1115 | /* Reset SERDES registers */ | |
af03abec | 1116 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ff37e337 S |
1117 | |
1118 | /* | |
1119 | * The basic interface to setting the hardware in a good | |
1120 | * state is ``reset''. On return the hardware is known to | |
1121 | * be powered up and with interrupts disabled. This must | |
1122 | * be followed by initialization of the appropriate bits | |
1123 | * and then setup of the interrupt mask. | |
1124 | */ | |
1125 | spin_lock_bh(&sc->sc_resetlock); | |
af03abec | 1126 | r = ath9k_hw_reset(ah, init_channel, false); |
ae8d2858 | 1127 | if (r) { |
c46917bb LR |
1128 | ath_print(common, ATH_DBG_FATAL, |
1129 | "Unable to reset hardware; reset status %d " | |
1130 | "(freq %u MHz)\n", r, | |
1131 | curchan->center_freq); | |
ff37e337 | 1132 | spin_unlock_bh(&sc->sc_resetlock); |
141b38b6 | 1133 | goto mutex_unlock; |
ff37e337 S |
1134 | } |
1135 | spin_unlock_bh(&sc->sc_resetlock); | |
1136 | ||
1137 | /* | |
1138 | * This is needed only to setup initial state | |
1139 | * but it's best done after a reset. | |
1140 | */ | |
1141 | ath_update_txpow(sc); | |
8feceb67 | 1142 | |
ff37e337 S |
1143 | /* |
1144 | * Setup the hardware after reset: | |
1145 | * The receive engine is set going. | |
1146 | * Frame transmit is handled entirely | |
1147 | * in the frame output path; there's nothing to do | |
1148 | * here except setup the interrupt mask. | |
1149 | */ | |
1150 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
1151 | ath_print(common, ATH_DBG_FATAL, |
1152 | "Unable to start recv logic\n"); | |
141b38b6 S |
1153 | r = -EIO; |
1154 | goto mutex_unlock; | |
f078f209 | 1155 | } |
8feceb67 | 1156 | |
ff37e337 | 1157 | /* Setup our intr mask. */ |
17d7904d | 1158 | sc->imask = ATH9K_INT_RX | ATH9K_INT_TX |
ff37e337 S |
1159 | | ATH9K_INT_RXEOL | ATH9K_INT_RXORN |
1160 | | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL; | |
1161 | ||
af03abec | 1162 | if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT) |
17d7904d | 1163 | sc->imask |= ATH9K_INT_GTT; |
ff37e337 | 1164 | |
af03abec | 1165 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
17d7904d | 1166 | sc->imask |= ATH9K_INT_CST; |
ff37e337 | 1167 | |
ce111bad | 1168 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
1169 | |
1170 | sc->sc_flags &= ~SC_OP_INVALID; | |
1171 | ||
1172 | /* Disable BMISS interrupt when we're not associated */ | |
17d7904d | 1173 | sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
af03abec | 1174 | ath9k_hw_set_interrupts(ah, sc->imask); |
ff37e337 | 1175 | |
bce048d7 | 1176 | ieee80211_wake_queues(hw); |
ff37e337 | 1177 | |
42935eca | 1178 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
164ace38 | 1179 | |
766ec4a9 LR |
1180 | if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && |
1181 | !ah->btcoex_hw.enabled) { | |
5e197292 LR |
1182 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, |
1183 | AR_STOMP_LOW_WLAN_WGHT); | |
af03abec | 1184 | ath9k_hw_btcoex_enable(ah); |
f985ad12 | 1185 | |
5bb12791 LR |
1186 | if (common->bus_ops->bt_coex_prep) |
1187 | common->bus_ops->bt_coex_prep(common); | |
766ec4a9 | 1188 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1189 | ath9k_btcoex_timer_resume(sc); |
1773912b VT |
1190 | } |
1191 | ||
141b38b6 S |
1192 | mutex_unlock: |
1193 | mutex_unlock(&sc->mutex); | |
1194 | ||
ae8d2858 | 1195 | return r; |
f078f209 LR |
1196 | } |
1197 | ||
8feceb67 VT |
1198 | static int ath9k_tx(struct ieee80211_hw *hw, |
1199 | struct sk_buff *skb) | |
f078f209 | 1200 | { |
528f0c6b | 1201 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
bce048d7 JM |
1202 | struct ath_wiphy *aphy = hw->priv; |
1203 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1204 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1205 | struct ath_tx_control txctl; |
1bc14880 BP |
1206 | int padpos, padsize; |
1207 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
528f0c6b | 1208 | |
8089cc47 | 1209 | if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { |
c46917bb LR |
1210 | ath_print(common, ATH_DBG_XMIT, |
1211 | "ath9k: %s: TX in unexpected wiphy state " | |
1212 | "%d\n", wiphy_name(hw->wiphy), aphy->state); | |
ee166a0e JM |
1213 | goto exit; |
1214 | } | |
1215 | ||
96148326 | 1216 | if (sc->ps_enabled) { |
dc8c4585 JM |
1217 | /* |
1218 | * mac80211 does not set PM field for normal data frames, so we | |
1219 | * need to update that based on the current PS mode. | |
1220 | */ | |
1221 | if (ieee80211_is_data(hdr->frame_control) && | |
1222 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
1223 | !ieee80211_has_pm(hdr->frame_control)) { | |
c46917bb LR |
1224 | ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame " |
1225 | "while in PS mode\n"); | |
dc8c4585 JM |
1226 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
1227 | } | |
1228 | } | |
1229 | ||
9a23f9ca JM |
1230 | if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { |
1231 | /* | |
1232 | * We are using PS-Poll and mac80211 can request TX while in | |
1233 | * power save mode. Need to wake up hardware for the TX to be | |
1234 | * completed and if needed, also for RX of buffered frames. | |
1235 | */ | |
9a23f9ca JM |
1236 | ath9k_ps_wakeup(sc); |
1237 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
1238 | if (ieee80211_is_pspoll(hdr->frame_control)) { | |
c46917bb LR |
1239 | ath_print(common, ATH_DBG_PS, |
1240 | "Sending PS-Poll to pick a buffered frame\n"); | |
1b04b930 | 1241 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 1242 | } else { |
c46917bb LR |
1243 | ath_print(common, ATH_DBG_PS, |
1244 | "Wake up to complete TX\n"); | |
1b04b930 | 1245 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
1246 | } |
1247 | /* | |
1248 | * The actual restore operation will happen only after | |
1249 | * the sc_flags bit is cleared. We are just dropping | |
1250 | * the ps_usecount here. | |
1251 | */ | |
1252 | ath9k_ps_restore(sc); | |
1253 | } | |
1254 | ||
528f0c6b | 1255 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 | 1256 | |
8feceb67 VT |
1257 | /* |
1258 | * As a temporary workaround, assign seq# here; this will likely need | |
1259 | * to be cleaned up to work better with Beacon transmission and virtual | |
1260 | * BSSes. | |
1261 | */ | |
1262 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
8feceb67 | 1263 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) |
b77f483f | 1264 | sc->tx.seq_no += 0x10; |
8feceb67 | 1265 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
b77f483f | 1266 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); |
8feceb67 | 1267 | } |
f078f209 | 1268 | |
8feceb67 | 1269 | /* Add the padding after the header if this is not already done */ |
1bc14880 BP |
1270 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
1271 | padsize = padpos & 3; | |
1272 | if (padsize && skb->len>padpos) { | |
8feceb67 VT |
1273 | if (skb_headroom(skb) < padsize) |
1274 | return -1; | |
1275 | skb_push(skb, padsize); | |
1bc14880 | 1276 | memmove(skb->data, skb->data + padsize, padpos); |
8feceb67 VT |
1277 | } |
1278 | ||
528f0c6b S |
1279 | /* Check if a tx queue is available */ |
1280 | ||
1281 | txctl.txq = ath_test_get_txq(sc, skb); | |
1282 | if (!txctl.txq) | |
1283 | goto exit; | |
1284 | ||
c46917bb | 1285 | ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 1286 | |
c52f33d0 | 1287 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
c46917bb | 1288 | ath_print(common, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 1289 | goto exit; |
8feceb67 VT |
1290 | } |
1291 | ||
528f0c6b S |
1292 | return 0; |
1293 | exit: | |
1294 | dev_kfree_skb_any(skb); | |
8feceb67 | 1295 | return 0; |
f078f209 LR |
1296 | } |
1297 | ||
8feceb67 | 1298 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 1299 | { |
bce048d7 JM |
1300 | struct ath_wiphy *aphy = hw->priv; |
1301 | struct ath_softc *sc = aphy->sc; | |
af03abec | 1302 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1303 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 1304 | |
4c483817 S |
1305 | mutex_lock(&sc->mutex); |
1306 | ||
9580a222 JM |
1307 | aphy->state = ATH_WIPHY_INACTIVE; |
1308 | ||
c94dbff7 LR |
1309 | cancel_delayed_work_sync(&sc->ath_led_blink_work); |
1310 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
1311 | ||
1312 | if (!sc->num_sec_wiphy) { | |
1313 | cancel_delayed_work_sync(&sc->wiphy_work); | |
1314 | cancel_work_sync(&sc->chan_work); | |
1315 | } | |
1316 | ||
9c84b797 | 1317 | if (sc->sc_flags & SC_OP_INVALID) { |
c46917bb | 1318 | ath_print(common, ATH_DBG_ANY, "Device not present\n"); |
4c483817 | 1319 | mutex_unlock(&sc->mutex); |
9c84b797 S |
1320 | return; |
1321 | } | |
8feceb67 | 1322 | |
9580a222 JM |
1323 | if (ath9k_wiphy_started(sc)) { |
1324 | mutex_unlock(&sc->mutex); | |
1325 | return; /* another wiphy still in use */ | |
1326 | } | |
1327 | ||
3867cf6a S |
1328 | /* Ensure HW is awake when we try to shut it down. */ |
1329 | ath9k_ps_wakeup(sc); | |
1330 | ||
766ec4a9 | 1331 | if (ah->btcoex_hw.enabled) { |
af03abec | 1332 | ath9k_hw_btcoex_disable(ah); |
766ec4a9 | 1333 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1334 | ath9k_btcoex_timer_pause(sc); |
1773912b VT |
1335 | } |
1336 | ||
ff37e337 S |
1337 | /* make sure h/w will not generate any interrupt |
1338 | * before setting the invalid flag. */ | |
af03abec | 1339 | ath9k_hw_set_interrupts(ah, 0); |
ff37e337 S |
1340 | |
1341 | if (!(sc->sc_flags & SC_OP_INVALID)) { | |
043a0405 | 1342 | ath_drain_all_txq(sc, false); |
ff37e337 | 1343 | ath_stoprecv(sc); |
af03abec | 1344 | ath9k_hw_phy_disable(ah); |
ff37e337 | 1345 | } else |
b77f483f | 1346 | sc->rx.rxlink = NULL; |
ff37e337 | 1347 | |
ff37e337 | 1348 | /* disable HAL and put h/w to sleep */ |
af03abec LR |
1349 | ath9k_hw_disable(ah); |
1350 | ath9k_hw_configpcipowersave(ah, 1, 1); | |
3867cf6a S |
1351 | ath9k_ps_restore(sc); |
1352 | ||
1353 | /* Finally, put the chip in FULL SLEEP mode */ | |
9ecdef4b | 1354 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
ff37e337 S |
1355 | |
1356 | sc->sc_flags |= SC_OP_INVALID; | |
500c064d | 1357 | |
141b38b6 S |
1358 | mutex_unlock(&sc->mutex); |
1359 | ||
c46917bb | 1360 | ath_print(common, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
1361 | } |
1362 | ||
8feceb67 | 1363 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1364 | struct ieee80211_vif *vif) |
f078f209 | 1365 | { |
bce048d7 JM |
1366 | struct ath_wiphy *aphy = hw->priv; |
1367 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1368 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1ed32e4f | 1369 | struct ath_vif *avp = (void *)vif->drv_priv; |
d97809db | 1370 | enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; |
2c3db3d5 | 1371 | int ret = 0; |
8feceb67 | 1372 | |
141b38b6 S |
1373 | mutex_lock(&sc->mutex); |
1374 | ||
8ca21f01 JM |
1375 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) && |
1376 | sc->nvifs > 0) { | |
1377 | ret = -ENOBUFS; | |
1378 | goto out; | |
1379 | } | |
1380 | ||
1ed32e4f | 1381 | switch (vif->type) { |
05c914fe | 1382 | case NL80211_IFTYPE_STATION: |
d97809db | 1383 | ic_opmode = NL80211_IFTYPE_STATION; |
f078f209 | 1384 | break; |
05c914fe | 1385 | case NL80211_IFTYPE_ADHOC: |
05c914fe | 1386 | case NL80211_IFTYPE_AP: |
9cb5412b | 1387 | case NL80211_IFTYPE_MESH_POINT: |
2c3db3d5 JM |
1388 | if (sc->nbcnvifs >= ATH_BCBUF) { |
1389 | ret = -ENOBUFS; | |
1390 | goto out; | |
1391 | } | |
1ed32e4f | 1392 | ic_opmode = vif->type; |
f078f209 LR |
1393 | break; |
1394 | default: | |
c46917bb | 1395 | ath_print(common, ATH_DBG_FATAL, |
1ed32e4f | 1396 | "Interface type %d not yet supported\n", vif->type); |
2c3db3d5 JM |
1397 | ret = -EOPNOTSUPP; |
1398 | goto out; | |
f078f209 LR |
1399 | } |
1400 | ||
c46917bb LR |
1401 | ath_print(common, ATH_DBG_CONFIG, |
1402 | "Attach a VIF of type: %d\n", ic_opmode); | |
8feceb67 | 1403 | |
17d7904d | 1404 | /* Set the VIF opmode */ |
5640b08e S |
1405 | avp->av_opmode = ic_opmode; |
1406 | avp->av_bslot = -1; | |
1407 | ||
2c3db3d5 | 1408 | sc->nvifs++; |
8ca21f01 JM |
1409 | |
1410 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) | |
1411 | ath9k_set_bssid_mask(hw); | |
1412 | ||
2c3db3d5 JM |
1413 | if (sc->nvifs > 1) |
1414 | goto out; /* skip global settings for secondary vif */ | |
1415 | ||
b238e90e | 1416 | if (ic_opmode == NL80211_IFTYPE_AP) { |
5640b08e | 1417 | ath9k_hw_set_tsfadjust(sc->sc_ah, 1); |
b238e90e S |
1418 | sc->sc_flags |= SC_OP_TSF_RESET; |
1419 | } | |
5640b08e | 1420 | |
5640b08e | 1421 | /* Set the device opmode */ |
2660b81a | 1422 | sc->sc_ah->opmode = ic_opmode; |
5640b08e | 1423 | |
4e30ffa2 VN |
1424 | /* |
1425 | * Enable MIB interrupts when there are hardware phy counters. | |
1426 | * Note we only do this (at the moment) for station mode. | |
1427 | */ | |
1ed32e4f JB |
1428 | if ((vif->type == NL80211_IFTYPE_STATION) || |
1429 | (vif->type == NL80211_IFTYPE_ADHOC) || | |
1430 | (vif->type == NL80211_IFTYPE_MESH_POINT)) { | |
1aa8e847 | 1431 | sc->imask |= ATH9K_INT_MIB; |
4af9cf4f S |
1432 | sc->imask |= ATH9K_INT_TSFOOR; |
1433 | } | |
1434 | ||
17d7904d | 1435 | ath9k_hw_set_interrupts(sc->sc_ah, sc->imask); |
4e30ffa2 | 1436 | |
1ed32e4f JB |
1437 | if (vif->type == NL80211_IFTYPE_AP || |
1438 | vif->type == NL80211_IFTYPE_ADHOC || | |
1439 | vif->type == NL80211_IFTYPE_MONITOR) | |
3d536acf | 1440 | ath_start_ani(common); |
6f255425 | 1441 | |
2c3db3d5 | 1442 | out: |
141b38b6 | 1443 | mutex_unlock(&sc->mutex); |
2c3db3d5 | 1444 | return ret; |
f078f209 LR |
1445 | } |
1446 | ||
8feceb67 | 1447 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1448 | struct ieee80211_vif *vif) |
f078f209 | 1449 | { |
bce048d7 JM |
1450 | struct ath_wiphy *aphy = hw->priv; |
1451 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1452 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1ed32e4f | 1453 | struct ath_vif *avp = (void *)vif->drv_priv; |
2c3db3d5 | 1454 | int i; |
f078f209 | 1455 | |
c46917bb | 1456 | ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 1457 | |
141b38b6 S |
1458 | mutex_lock(&sc->mutex); |
1459 | ||
6f255425 | 1460 | /* Stop ANI */ |
3d536acf | 1461 | del_timer_sync(&common->ani.timer); |
580f0b8a | 1462 | |
8feceb67 | 1463 | /* Reclaim beacon resources */ |
9cb5412b PE |
1464 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || |
1465 | (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) || | |
1466 | (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) { | |
5f70a88f | 1467 | ath9k_ps_wakeup(sc); |
b77f483f | 1468 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); |
8feceb67 | 1469 | ath_beacon_return(sc, avp); |
5f70a88f | 1470 | ath9k_ps_restore(sc); |
580f0b8a | 1471 | } |
f078f209 | 1472 | |
8feceb67 | 1473 | sc->sc_flags &= ~SC_OP_BEACONS; |
f078f209 | 1474 | |
2c3db3d5 | 1475 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { |
1ed32e4f | 1476 | if (sc->beacon.bslot[i] == vif) { |
2c3db3d5 JM |
1477 | printk(KERN_DEBUG "%s: vif had allocated beacon " |
1478 | "slot\n", __func__); | |
1479 | sc->beacon.bslot[i] = NULL; | |
c52f33d0 | 1480 | sc->beacon.bslot_aphy[i] = NULL; |
2c3db3d5 JM |
1481 | } |
1482 | } | |
1483 | ||
17d7904d | 1484 | sc->nvifs--; |
141b38b6 S |
1485 | |
1486 | mutex_unlock(&sc->mutex); | |
f078f209 LR |
1487 | } |
1488 | ||
e8975581 | 1489 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1490 | { |
bce048d7 JM |
1491 | struct ath_wiphy *aphy = hw->priv; |
1492 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1493 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8975581 | 1494 | struct ieee80211_conf *conf = &hw->conf; |
8782b41d | 1495 | struct ath_hw *ah = sc->sc_ah; |
194b7c13 | 1496 | bool disable_radio; |
f078f209 | 1497 | |
aa33de09 | 1498 | mutex_lock(&sc->mutex); |
141b38b6 | 1499 | |
194b7c13 LR |
1500 | /* |
1501 | * Leave this as the first check because we need to turn on the | |
1502 | * radio if it was disabled before prior to processing the rest | |
1503 | * of the changes. Likewise we must only disable the radio towards | |
1504 | * the end. | |
1505 | */ | |
64839170 | 1506 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
194b7c13 LR |
1507 | bool enable_radio; |
1508 | bool all_wiphys_idle; | |
1509 | bool idle = !!(conf->flags & IEEE80211_CONF_IDLE); | |
64839170 LR |
1510 | |
1511 | spin_lock_bh(&sc->wiphy_lock); | |
1512 | all_wiphys_idle = ath9k_all_wiphys_idle(sc); | |
194b7c13 LR |
1513 | ath9k_set_wiphy_idle(aphy, idle); |
1514 | ||
1515 | if (!idle && all_wiphys_idle) | |
1516 | enable_radio = true; | |
1517 | ||
1518 | /* | |
1519 | * After we unlock here its possible another wiphy | |
1520 | * can be re-renabled so to account for that we will | |
1521 | * only disable the radio toward the end of this routine | |
1522 | * if by then all wiphys are still idle. | |
1523 | */ | |
64839170 LR |
1524 | spin_unlock_bh(&sc->wiphy_lock); |
1525 | ||
194b7c13 | 1526 | if (enable_radio) { |
68a89116 | 1527 | ath_radio_enable(sc, hw); |
c46917bb LR |
1528 | ath_print(common, ATH_DBG_CONFIG, |
1529 | "not-idle: enabling radio\n"); | |
64839170 LR |
1530 | } |
1531 | } | |
1532 | ||
e7824a50 LR |
1533 | /* |
1534 | * We just prepare to enable PS. We have to wait until our AP has | |
1535 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1536 | * those ACKs and end up retransmitting the same null data frames. | |
1537 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1538 | */ | |
3cbb5dd7 VN |
1539 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
1540 | if (conf->flags & IEEE80211_CONF_PS) { | |
1b04b930 | 1541 | sc->ps_flags |= PS_ENABLED; |
8782b41d VN |
1542 | if (!(ah->caps.hw_caps & |
1543 | ATH9K_HW_CAP_AUTOSLEEP)) { | |
1544 | if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1545 | sc->imask |= ATH9K_INT_TIM_TIMER; | |
1546 | ath9k_hw_set_interrupts(sc->sc_ah, | |
1547 | sc->imask); | |
1548 | } | |
3cbb5dd7 | 1549 | } |
e7824a50 LR |
1550 | /* |
1551 | * At this point we know hardware has received an ACK | |
1552 | * of a previously sent null data frame. | |
1553 | */ | |
1b04b930 S |
1554 | if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) { |
1555 | sc->ps_flags &= ~PS_NULLFUNC_COMPLETED; | |
e7824a50 LR |
1556 | sc->ps_enabled = true; |
1557 | ath9k_hw_setrxabort(sc->sc_ah, 1); | |
1558 | } | |
3cbb5dd7 | 1559 | } else { |
96148326 | 1560 | sc->ps_enabled = false; |
1b04b930 S |
1561 | sc->ps_flags &= ~(PS_ENABLED | |
1562 | PS_NULLFUNC_COMPLETED); | |
9ecdef4b | 1563 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
8782b41d VN |
1564 | if (!(ah->caps.hw_caps & |
1565 | ATH9K_HW_CAP_AUTOSLEEP)) { | |
1566 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
1b04b930 S |
1567 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | |
1568 | PS_WAIT_FOR_CAB | | |
1569 | PS_WAIT_FOR_PSPOLL_DATA | | |
1570 | PS_WAIT_FOR_TX_ACK); | |
8782b41d VN |
1571 | if (sc->imask & ATH9K_INT_TIM_TIMER) { |
1572 | sc->imask &= ~ATH9K_INT_TIM_TIMER; | |
1573 | ath9k_hw_set_interrupts(sc->sc_ah, | |
1574 | sc->imask); | |
1575 | } | |
3cbb5dd7 VN |
1576 | } |
1577 | } | |
1578 | } | |
1579 | ||
4797938c | 1580 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
99405f93 | 1581 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 1582 | int pos = curchan->hw_value; |
ae5eb026 | 1583 | |
0e2dedf9 JM |
1584 | aphy->chan_idx = pos; |
1585 | aphy->chan_is_ht = conf_is_ht(conf); | |
1586 | ||
8089cc47 JM |
1587 | if (aphy->state == ATH_WIPHY_SCAN || |
1588 | aphy->state == ATH_WIPHY_ACTIVE) | |
1589 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
1590 | else { | |
1591 | /* | |
1592 | * Do not change operational channel based on a paused | |
1593 | * wiphy changes. | |
1594 | */ | |
1595 | goto skip_chan_change; | |
1596 | } | |
0e2dedf9 | 1597 | |
c46917bb LR |
1598 | ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", |
1599 | curchan->center_freq); | |
f078f209 | 1600 | |
5f8e077c | 1601 | /* XXX: remove me eventualy */ |
0e2dedf9 | 1602 | ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); |
e11602b7 | 1603 | |
ecf70441 | 1604 | ath_update_chainmask(sc, conf_is_ht(conf)); |
86060f0d | 1605 | |
0e2dedf9 | 1606 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
c46917bb LR |
1607 | ath_print(common, ATH_DBG_FATAL, |
1608 | "Unable to set channel\n"); | |
aa33de09 | 1609 | mutex_unlock(&sc->mutex); |
e11602b7 S |
1610 | return -EINVAL; |
1611 | } | |
094d05dc | 1612 | } |
f078f209 | 1613 | |
8089cc47 | 1614 | skip_chan_change: |
5c020dc6 | 1615 | if (changed & IEEE80211_CONF_CHANGE_POWER) |
17d7904d | 1616 | sc->config.txpowlimit = 2 * conf->power_level; |
f078f209 | 1617 | |
194b7c13 LR |
1618 | spin_lock_bh(&sc->wiphy_lock); |
1619 | disable_radio = ath9k_all_wiphys_idle(sc); | |
1620 | spin_unlock_bh(&sc->wiphy_lock); | |
1621 | ||
64839170 | 1622 | if (disable_radio) { |
c46917bb | 1623 | ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); |
68a89116 | 1624 | ath_radio_disable(sc, hw); |
64839170 LR |
1625 | } |
1626 | ||
aa33de09 | 1627 | mutex_unlock(&sc->mutex); |
141b38b6 | 1628 | |
f078f209 LR |
1629 | return 0; |
1630 | } | |
1631 | ||
8feceb67 VT |
1632 | #define SUPPORTED_FILTERS \ |
1633 | (FIF_PROMISC_IN_BSS | \ | |
1634 | FIF_ALLMULTI | \ | |
1635 | FIF_CONTROL | \ | |
af6a3fc7 | 1636 | FIF_PSPOLL | \ |
8feceb67 VT |
1637 | FIF_OTHER_BSS | \ |
1638 | FIF_BCN_PRBRESP_PROMISC | \ | |
1639 | FIF_FCSFAIL) | |
c83be688 | 1640 | |
8feceb67 VT |
1641 | /* FIXME: sc->sc_full_reset ? */ |
1642 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1643 | unsigned int changed_flags, | |
1644 | unsigned int *total_flags, | |
3ac64bee | 1645 | u64 multicast) |
8feceb67 | 1646 | { |
bce048d7 JM |
1647 | struct ath_wiphy *aphy = hw->priv; |
1648 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 1649 | u32 rfilt; |
f078f209 | 1650 | |
8feceb67 VT |
1651 | changed_flags &= SUPPORTED_FILTERS; |
1652 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1653 | |
b77f483f | 1654 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1655 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1656 | rfilt = ath_calcrxfilter(sc); |
1657 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1658 | ath9k_ps_restore(sc); |
f078f209 | 1659 | |
c46917bb LR |
1660 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, |
1661 | "Set HW RX filter: 0x%x\n", rfilt); | |
8feceb67 | 1662 | } |
f078f209 | 1663 | |
8feceb67 VT |
1664 | static void ath9k_sta_notify(struct ieee80211_hw *hw, |
1665 | struct ieee80211_vif *vif, | |
1666 | enum sta_notify_cmd cmd, | |
17741cdc | 1667 | struct ieee80211_sta *sta) |
8feceb67 | 1668 | { |
bce048d7 JM |
1669 | struct ath_wiphy *aphy = hw->priv; |
1670 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 1671 | |
8feceb67 VT |
1672 | switch (cmd) { |
1673 | case STA_NOTIFY_ADD: | |
5640b08e | 1674 | ath_node_attach(sc, sta); |
8feceb67 VT |
1675 | break; |
1676 | case STA_NOTIFY_REMOVE: | |
b5aa9bf9 | 1677 | ath_node_detach(sc, sta); |
8feceb67 VT |
1678 | break; |
1679 | default: | |
1680 | break; | |
1681 | } | |
f078f209 LR |
1682 | } |
1683 | ||
141b38b6 | 1684 | static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
8feceb67 | 1685 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1686 | { |
bce048d7 JM |
1687 | struct ath_wiphy *aphy = hw->priv; |
1688 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1689 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 VT |
1690 | struct ath9k_tx_queue_info qi; |
1691 | int ret = 0, qnum; | |
f078f209 | 1692 | |
8feceb67 VT |
1693 | if (queue >= WME_NUM_AC) |
1694 | return 0; | |
f078f209 | 1695 | |
141b38b6 S |
1696 | mutex_lock(&sc->mutex); |
1697 | ||
1ffb0610 S |
1698 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1699 | ||
8feceb67 VT |
1700 | qi.tqi_aifs = params->aifs; |
1701 | qi.tqi_cwmin = params->cw_min; | |
1702 | qi.tqi_cwmax = params->cw_max; | |
1703 | qi.tqi_burstTime = params->txop; | |
1704 | qnum = ath_get_hal_qnum(queue, sc); | |
f078f209 | 1705 | |
c46917bb LR |
1706 | ath_print(common, ATH_DBG_CONFIG, |
1707 | "Configure tx [queue/halq] [%d/%d], " | |
1708 | "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | |
1709 | queue, qnum, params->aifs, params->cw_min, | |
1710 | params->cw_max, params->txop); | |
f078f209 | 1711 | |
8feceb67 VT |
1712 | ret = ath_txq_update(sc, qnum, &qi); |
1713 | if (ret) | |
c46917bb | 1714 | ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n"); |
f078f209 | 1715 | |
94db2936 VN |
1716 | if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) |
1717 | if ((qnum == sc->tx.hwq_map[ATH9K_WME_AC_BE]) && !ret) | |
1718 | ath_beaconq_config(sc); | |
1719 | ||
141b38b6 S |
1720 | mutex_unlock(&sc->mutex); |
1721 | ||
8feceb67 VT |
1722 | return ret; |
1723 | } | |
f078f209 | 1724 | |
8feceb67 VT |
1725 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1726 | enum set_key_cmd cmd, | |
dc822b5d JB |
1727 | struct ieee80211_vif *vif, |
1728 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1729 | struct ieee80211_key_conf *key) |
1730 | { | |
bce048d7 JM |
1731 | struct ath_wiphy *aphy = hw->priv; |
1732 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1733 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1734 | int ret = 0; |
f078f209 | 1735 | |
b3bd89ce JM |
1736 | if (modparam_nohwcrypt) |
1737 | return -ENOSPC; | |
1738 | ||
141b38b6 | 1739 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1740 | ath9k_ps_wakeup(sc); |
c46917bb | 1741 | ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n"); |
f078f209 | 1742 | |
8feceb67 VT |
1743 | switch (cmd) { |
1744 | case SET_KEY: | |
7e86c104 | 1745 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1746 | if (ret >= 0) { |
1747 | key->hw_key_idx = ret; | |
8feceb67 VT |
1748 | /* push IV and Michael MIC generation to stack */ |
1749 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
1750 | if (key->alg == ALG_TKIP) | |
1751 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; | |
0ced0e17 JM |
1752 | if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP) |
1753 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; | |
6ace2891 | 1754 | ret = 0; |
8feceb67 VT |
1755 | } |
1756 | break; | |
1757 | case DISABLE_KEY: | |
7e86c104 | 1758 | ath_key_delete(common, key); |
8feceb67 VT |
1759 | break; |
1760 | default: | |
1761 | ret = -EINVAL; | |
1762 | } | |
f078f209 | 1763 | |
3cbb5dd7 | 1764 | ath9k_ps_restore(sc); |
141b38b6 S |
1765 | mutex_unlock(&sc->mutex); |
1766 | ||
8feceb67 VT |
1767 | return ret; |
1768 | } | |
f078f209 | 1769 | |
8feceb67 VT |
1770 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1771 | struct ieee80211_vif *vif, | |
1772 | struct ieee80211_bss_conf *bss_conf, | |
1773 | u32 changed) | |
1774 | { | |
bce048d7 JM |
1775 | struct ath_wiphy *aphy = hw->priv; |
1776 | struct ath_softc *sc = aphy->sc; | |
2d0ddec5 | 1777 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1778 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1779 | struct ath_vif *avp = (void *)vif->drv_priv; |
c6089ccc | 1780 | int error; |
f078f209 | 1781 | |
141b38b6 S |
1782 | mutex_lock(&sc->mutex); |
1783 | ||
c6089ccc S |
1784 | if (changed & BSS_CHANGED_BSSID) { |
1785 | /* Set BSSID */ | |
1786 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | |
1787 | memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); | |
1510718d | 1788 | common->curaid = 0; |
f2b2143e | 1789 | ath9k_hw_write_associd(ah); |
2d0ddec5 | 1790 | |
c6089ccc S |
1791 | /* Set aggregation protection mode parameters */ |
1792 | sc->config.ath_aggr_prot = 0; | |
2d0ddec5 | 1793 | |
c6089ccc S |
1794 | /* Only legacy IBSS for now */ |
1795 | if (vif->type == NL80211_IFTYPE_ADHOC) | |
1796 | ath_update_chainmask(sc, 0); | |
2d0ddec5 | 1797 | |
c6089ccc S |
1798 | ath_print(common, ATH_DBG_CONFIG, |
1799 | "BSSID: %pM aid: 0x%x\n", | |
1800 | common->curbssid, common->curaid); | |
2d0ddec5 | 1801 | |
c6089ccc S |
1802 | /* need to reconfigure the beacon */ |
1803 | sc->sc_flags &= ~SC_OP_BEACONS ; | |
1804 | } | |
2d0ddec5 | 1805 | |
c6089ccc S |
1806 | /* Enable transmission of beacons (AP, IBSS, MESH) */ |
1807 | if ((changed & BSS_CHANGED_BEACON) || | |
1808 | ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { | |
1809 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1810 | error = ath_beacon_alloc(aphy, vif); | |
1811 | if (!error) | |
1812 | ath_beacon_config(sc, vif); | |
2d0ddec5 JB |
1813 | } |
1814 | ||
c6089ccc S |
1815 | /* Disable transmission of beacons */ |
1816 | if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon) | |
1817 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 | 1818 | |
c6089ccc S |
1819 | if (changed & BSS_CHANGED_BEACON_INT) { |
1820 | sc->beacon_interval = bss_conf->beacon_int; | |
1821 | /* | |
1822 | * In case of AP mode, the HW TSF has to be reset | |
1823 | * when the beacon interval changes. | |
1824 | */ | |
1825 | if (vif->type == NL80211_IFTYPE_AP) { | |
1826 | sc->sc_flags |= SC_OP_TSF_RESET; | |
1827 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 JB |
1828 | error = ath_beacon_alloc(aphy, vif); |
1829 | if (!error) | |
1830 | ath_beacon_config(sc, vif); | |
c6089ccc S |
1831 | } else { |
1832 | ath_beacon_config(sc, vif); | |
2d0ddec5 JB |
1833 | } |
1834 | } | |
1835 | ||
8feceb67 | 1836 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
c46917bb LR |
1837 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
1838 | bss_conf->use_short_preamble); | |
8feceb67 VT |
1839 | if (bss_conf->use_short_preamble) |
1840 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
1841 | else | |
1842 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
1843 | } | |
f078f209 | 1844 | |
8feceb67 | 1845 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
c46917bb LR |
1846 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
1847 | bss_conf->use_cts_prot); | |
8feceb67 VT |
1848 | if (bss_conf->use_cts_prot && |
1849 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
1850 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
1851 | else | |
1852 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
1853 | } | |
f078f209 | 1854 | |
8feceb67 | 1855 | if (changed & BSS_CHANGED_ASSOC) { |
c46917bb | 1856 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", |
8feceb67 | 1857 | bss_conf->assoc); |
5640b08e | 1858 | ath9k_bss_assoc_info(sc, vif, bss_conf); |
8feceb67 | 1859 | } |
141b38b6 S |
1860 | |
1861 | mutex_unlock(&sc->mutex); | |
8feceb67 | 1862 | } |
f078f209 | 1863 | |
8feceb67 VT |
1864 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) |
1865 | { | |
1866 | u64 tsf; | |
bce048d7 JM |
1867 | struct ath_wiphy *aphy = hw->priv; |
1868 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 1869 | |
141b38b6 S |
1870 | mutex_lock(&sc->mutex); |
1871 | tsf = ath9k_hw_gettsf64(sc->sc_ah); | |
1872 | mutex_unlock(&sc->mutex); | |
f078f209 | 1873 | |
8feceb67 VT |
1874 | return tsf; |
1875 | } | |
f078f209 | 1876 | |
3b5d665b AF |
1877 | static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) |
1878 | { | |
bce048d7 JM |
1879 | struct ath_wiphy *aphy = hw->priv; |
1880 | struct ath_softc *sc = aphy->sc; | |
3b5d665b | 1881 | |
141b38b6 S |
1882 | mutex_lock(&sc->mutex); |
1883 | ath9k_hw_settsf64(sc->sc_ah, tsf); | |
1884 | mutex_unlock(&sc->mutex); | |
3b5d665b AF |
1885 | } |
1886 | ||
8feceb67 VT |
1887 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) |
1888 | { | |
bce048d7 JM |
1889 | struct ath_wiphy *aphy = hw->priv; |
1890 | struct ath_softc *sc = aphy->sc; | |
c83be688 | 1891 | |
141b38b6 | 1892 | mutex_lock(&sc->mutex); |
21526d57 LR |
1893 | |
1894 | ath9k_ps_wakeup(sc); | |
141b38b6 | 1895 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
1896 | ath9k_ps_restore(sc); |
1897 | ||
141b38b6 | 1898 | mutex_unlock(&sc->mutex); |
8feceb67 | 1899 | } |
f078f209 | 1900 | |
8feceb67 | 1901 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 1902 | struct ieee80211_vif *vif, |
141b38b6 S |
1903 | enum ieee80211_ampdu_mlme_action action, |
1904 | struct ieee80211_sta *sta, | |
1905 | u16 tid, u16 *ssn) | |
8feceb67 | 1906 | { |
bce048d7 JM |
1907 | struct ath_wiphy *aphy = hw->priv; |
1908 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 1909 | int ret = 0; |
f078f209 | 1910 | |
8feceb67 VT |
1911 | switch (action) { |
1912 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
1913 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
1914 | ret = -ENOTSUPP; | |
8feceb67 VT |
1915 | break; |
1916 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
1917 | break; |
1918 | case IEEE80211_AMPDU_TX_START: | |
8b685ba9 | 1919 | ath9k_ps_wakeup(sc); |
f83da965 | 1920 | ath_tx_aggr_start(sc, sta, tid, ssn); |
c951ad35 | 1921 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1922 | ath9k_ps_restore(sc); |
8feceb67 VT |
1923 | break; |
1924 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 1925 | ath9k_ps_wakeup(sc); |
f83da965 | 1926 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 1927 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1928 | ath9k_ps_restore(sc); |
8feceb67 | 1929 | break; |
b1720231 | 1930 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 1931 | ath9k_ps_wakeup(sc); |
8469cdef | 1932 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 1933 | ath9k_ps_restore(sc); |
8469cdef | 1934 | break; |
8feceb67 | 1935 | default: |
c46917bb LR |
1936 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
1937 | "Unknown AMPDU action\n"); | |
8feceb67 VT |
1938 | } |
1939 | ||
1940 | return ret; | |
f078f209 LR |
1941 | } |
1942 | ||
0c98de65 S |
1943 | static void ath9k_sw_scan_start(struct ieee80211_hw *hw) |
1944 | { | |
bce048d7 JM |
1945 | struct ath_wiphy *aphy = hw->priv; |
1946 | struct ath_softc *sc = aphy->sc; | |
05c78d6d | 1947 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
0c98de65 | 1948 | |
3d832611 | 1949 | mutex_lock(&sc->mutex); |
8089cc47 JM |
1950 | if (ath9k_wiphy_scanning(sc)) { |
1951 | printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the " | |
1952 | "same time\n"); | |
1953 | /* | |
1954 | * Do not allow the concurrent scanning state for now. This | |
1955 | * could be improved with scanning control moved into ath9k. | |
1956 | */ | |
3d832611 | 1957 | mutex_unlock(&sc->mutex); |
8089cc47 JM |
1958 | return; |
1959 | } | |
1960 | ||
1961 | aphy->state = ATH_WIPHY_SCAN; | |
1962 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
0c98de65 | 1963 | sc->sc_flags |= SC_OP_SCANNING; |
05c78d6d | 1964 | del_timer_sync(&common->ani.timer); |
b6ce5c33 | 1965 | cancel_delayed_work_sync(&sc->tx_complete_work); |
3d832611 | 1966 | mutex_unlock(&sc->mutex); |
0c98de65 S |
1967 | } |
1968 | ||
1969 | static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) | |
1970 | { | |
bce048d7 JM |
1971 | struct ath_wiphy *aphy = hw->priv; |
1972 | struct ath_softc *sc = aphy->sc; | |
05c78d6d | 1973 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
0c98de65 | 1974 | |
3d832611 | 1975 | mutex_lock(&sc->mutex); |
8089cc47 | 1976 | aphy->state = ATH_WIPHY_ACTIVE; |
0c98de65 | 1977 | sc->sc_flags &= ~SC_OP_SCANNING; |
9c07a777 | 1978 | sc->sc_flags |= SC_OP_FULL_RESET; |
05c78d6d | 1979 | ath_start_ani(common); |
b6ce5c33 | 1980 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
d0bec342 | 1981 | ath_beacon_config(sc, NULL); |
3d832611 | 1982 | mutex_unlock(&sc->mutex); |
0c98de65 S |
1983 | } |
1984 | ||
6baff7f9 | 1985 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
1986 | .tx = ath9k_tx, |
1987 | .start = ath9k_start, | |
1988 | .stop = ath9k_stop, | |
1989 | .add_interface = ath9k_add_interface, | |
1990 | .remove_interface = ath9k_remove_interface, | |
1991 | .config = ath9k_config, | |
8feceb67 | 1992 | .configure_filter = ath9k_configure_filter, |
8feceb67 VT |
1993 | .sta_notify = ath9k_sta_notify, |
1994 | .conf_tx = ath9k_conf_tx, | |
8feceb67 | 1995 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 1996 | .set_key = ath9k_set_key, |
8feceb67 | 1997 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 1998 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 1999 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2000 | .ampdu_action = ath9k_ampdu_action, |
0c98de65 S |
2001 | .sw_scan_start = ath9k_sw_scan_start, |
2002 | .sw_scan_complete = ath9k_sw_scan_complete, | |
3b319aae | 2003 | .rfkill_poll = ath9k_rfkill_poll_state, |
8feceb67 | 2004 | }; |