mac80211: move ieee80211_remove_tid_tx function
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
6dcc3444
SM
22static void ath9k_set_assoc_state(struct ath_softc *sc,
23 struct ieee80211_vif *vif);
24
313eb87f 25u8 ath9k_parse_mpdudensity(u8 mpdudensity)
ff37e337
S
26{
27 /*
28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
29 * 0 for no restriction
30 * 1 for 1/4 us
31 * 2 for 1/2 us
32 * 3 for 1 us
33 * 4 for 2 us
34 * 5 for 4 us
35 * 6 for 8 us
36 * 7 for 16 us
37 */
38 switch (mpdudensity) {
39 case 0:
40 return 0;
41 case 1:
42 case 2:
43 case 3:
44 /* Our lower layer calculations limit our precision to
45 1 microsecond */
46 return 1;
47 case 4:
48 return 2;
49 case 5:
50 return 4;
51 case 6:
52 return 8;
53 case 7:
54 return 16;
55 default:
56 return 0;
57 }
58}
59
69081624
VT
60static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
61{
62 bool pending = false;
63
64 spin_lock_bh(&txq->axq_lock);
65
66 if (txq->axq_depth || !list_empty(&txq->axq_acq))
67 pending = true;
69081624
VT
68
69 spin_unlock_bh(&txq->axq_lock);
70 return pending;
71}
72
6d79cb4c 73static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
74{
75 unsigned long flags;
76 bool ret;
77
9ecdef4b
LR
78 spin_lock_irqsave(&sc->sc_pm_lock, flags);
79 ret = ath9k_hw_setpower(sc->sc_ah, mode);
80 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
81
82 return ret;
83}
84
a91d75ae
LR
85void ath9k_ps_wakeup(struct ath_softc *sc)
86{
898c914a 87 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 88 unsigned long flags;
fbb078fc 89 enum ath9k_power_mode power_mode;
a91d75ae
LR
90
91 spin_lock_irqsave(&sc->sc_pm_lock, flags);
92 if (++sc->ps_usecount != 1)
93 goto unlock;
94
fbb078fc 95 power_mode = sc->sc_ah->power_mode;
9ecdef4b 96 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 97
898c914a
FF
98 /*
99 * While the hardware is asleep, the cycle counters contain no
100 * useful data. Better clear them now so that they don't mess up
101 * survey data results.
102 */
fbb078fc
FF
103 if (power_mode != ATH9K_PM_AWAKE) {
104 spin_lock(&common->cc_lock);
105 ath_hw_cycle_counters_update(common);
106 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
c9ae6ab4 107 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
fbb078fc
FF
108 spin_unlock(&common->cc_lock);
109 }
898c914a 110
a91d75ae
LR
111 unlock:
112 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
113}
114
115void ath9k_ps_restore(struct ath_softc *sc)
116{
898c914a 117 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
c6c539f0 118 enum ath9k_power_mode mode;
a91d75ae 119 unsigned long flags;
ad128860 120 bool reset;
a91d75ae
LR
121
122 spin_lock_irqsave(&sc->sc_pm_lock, flags);
123 if (--sc->ps_usecount != 0)
124 goto unlock;
125
ad128860
SM
126 if (sc->ps_idle) {
127 ath9k_hw_setrxabort(sc->sc_ah, 1);
128 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
c6c539f0 129 mode = ATH9K_PM_FULL_SLEEP;
ad128860
SM
130 } else if (sc->ps_enabled &&
131 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
132 PS_WAIT_FOR_CAB |
133 PS_WAIT_FOR_PSPOLL_DATA |
424749c7
RM
134 PS_WAIT_FOR_TX_ACK |
135 PS_WAIT_FOR_ANI))) {
c6c539f0 136 mode = ATH9K_PM_NETWORK_SLEEP;
08d4df41
RM
137 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
138 ath9k_btcoex_stop_gen_timer(sc);
ad128860 139 } else {
c6c539f0 140 goto unlock;
ad128860 141 }
c6c539f0
FF
142
143 spin_lock(&common->cc_lock);
144 ath_hw_cycle_counters_update(common);
145 spin_unlock(&common->cc_lock);
146
1a8f0d39 147 ath9k_hw_setpower(sc->sc_ah, mode);
a91d75ae
LR
148
149 unlock:
150 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
151}
152
9adcf440 153static void __ath_cancel_work(struct ath_softc *sc)
ff37e337 154{
5ee08656
FF
155 cancel_work_sync(&sc->paprd_work);
156 cancel_work_sync(&sc->hw_check_work);
157 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 158 cancel_delayed_work_sync(&sc->hw_pll_work);
fad29cd2 159
bf52592f 160#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
fad29cd2
SM
161 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
162 cancel_work_sync(&sc->mci_work);
bf52592f 163#endif
9adcf440 164}
5ee08656 165
9adcf440
FF
166static void ath_cancel_work(struct ath_softc *sc)
167{
168 __ath_cancel_work(sc);
169 cancel_work_sync(&sc->hw_reset_work);
170}
3cbb5dd7 171
af68abad
SM
172static void ath_restart_work(struct ath_softc *sc)
173{
af68abad
SM
174 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
175
c12b6021
GJ
176 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
177 AR_SREV_9550(sc->sc_ah))
af68abad
SM
178 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
179 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
180
181 ath_start_rx_poll(sc, 3);
da0d45f7 182 ath_start_ani(sc);
af68abad
SM
183}
184
9adcf440
FF
185static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
186{
187 struct ath_hw *ah = sc->sc_ah;
ceea2a51 188 bool ret = true;
6a6733f2 189
9adcf440 190 ieee80211_stop_queues(sc->hw);
5e848f78 191
9adcf440 192 sc->hw_busy_count = 0;
da0d45f7 193 ath_stop_ani(sc);
01e18918 194 del_timer_sync(&sc->rx_poll_timer);
ff37e337 195
9adcf440
FF
196 ath9k_debug_samp_bb_mac(sc);
197 ath9k_hw_disable_interrupts(ah);
8b3f4616 198
9adcf440
FF
199 if (!ath_stoprecv(sc))
200 ret = false;
c0d7c7af 201
ceea2a51
FF
202 if (!ath_drain_all_txq(sc, retry_tx))
203 ret = false;
204
9adcf440
FF
205 if (!flush) {
206 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
3483288c
FF
207 ath_rx_tasklet(sc, 1, true);
208 ath_rx_tasklet(sc, 1, false);
9adcf440
FF
209 } else {
210 ath_flushrecv(sc);
211 }
20bd2a09 212
9adcf440
FF
213 return ret;
214}
ff37e337 215
9adcf440
FF
216static bool ath_complete_reset(struct ath_softc *sc, bool start)
217{
218 struct ath_hw *ah = sc->sc_ah;
219 struct ath_common *common = ath9k_hw_common(ah);
196fb860 220 unsigned long flags;
c0d7c7af 221
c0d7c7af 222 if (ath_startrecv(sc) != 0) {
3800276a 223 ath_err(common, "Unable to restart recv logic\n");
9adcf440 224 return false;
c0d7c7af
LR
225 }
226
5048e8c3
RM
227 ath9k_cmn_update_txpow(ah, sc->curtxpow,
228 sc->config.txpowlimit, &sc->curtxpow);
b74713d0
SM
229
230 clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
72d874c6 231 ath9k_hw_set_interrupts(ah);
b037b693 232 ath9k_hw_enable_interrupts(ah);
3989279c 233
4cb54fa3 234 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
196fb860
SM
235 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
236 goto work;
237
ef4ad633 238 ath9k_set_beacon(sc);
196fb860
SM
239
240 if (ah->opmode == NL80211_IFTYPE_STATION &&
241 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
242 spin_lock_irqsave(&sc->sc_pm_lock, flags);
243 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
244 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
245 }
246 work:
af68abad 247 ath_restart_work(sc);
5ee08656
FF
248 }
249
8da07830
SM
250 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
251 ath_ant_comb_update(sc);
43c35284 252
9adcf440
FF
253 ieee80211_wake_queues(sc->hw);
254
255 return true;
256}
257
258static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
259 bool retry_tx)
260{
261 struct ath_hw *ah = sc->sc_ah;
262 struct ath_common *common = ath9k_hw_common(ah);
263 struct ath9k_hw_cal_data *caldata = NULL;
264 bool fastcc = true;
265 bool flush = false;
266 int r;
267
268 __ath_cancel_work(sc);
269
270 spin_lock_bh(&sc->sc_pcu_lock);
92460412 271
4cb54fa3 272 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
9adcf440
FF
273 fastcc = false;
274 caldata = &sc->caldata;
275 }
276
277 if (!hchan) {
278 fastcc = false;
279 flush = true;
280 hchan = ah->curchan;
281 }
282
9adcf440
FF
283 if (!ath_prepare_reset(sc, retry_tx, flush))
284 fastcc = false;
285
d2182b69 286 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
feced201 287 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
9adcf440
FF
288
289 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
290 if (r) {
291 ath_err(common,
292 "Unable to reset channel, reset status %d\n", r);
293 goto out;
294 }
295
e82cb03f
RM
296 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
297 (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
298 ath9k_mci_set_txpower(sc, true, false);
299
9adcf440
FF
300 if (!ath_complete_reset(sc, true))
301 r = -EIO;
302
303out:
6a6733f2 304 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440
FF
305 return r;
306}
307
308
309/*
310 * Set/change channels. If the channel is really being changed, it's done
311 * by reseting the chip. To accomplish this we must first cleanup any pending
312 * DMA, then restart stuff.
313*/
314static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
315 struct ath9k_channel *hchan)
316{
317 int r;
318
781b14a3 319 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
9adcf440
FF
320 return -EIO;
321
9adcf440 322 r = ath_reset_internal(sc, hchan, false);
6a6733f2 323
3989279c 324 return r;
ff37e337
S
325}
326
7e1e3864
BG
327static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
328 struct ieee80211_vif *vif)
ff37e337
S
329{
330 struct ath_node *an;
313eb87f 331 u8 density;
ff37e337
S
332 an = (struct ath_node *)sta->drv_priv;
333
a145daf7 334 an->sc = sc;
7f010c93 335 an->sta = sta;
7e1e3864 336 an->vif = vif;
3d4e20f2 337
a4d6367f 338 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337 339 ath_tx_node_init(sc, an);
9e98ac65 340 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc 341 sta->ht_cap.ampdu_factor);
313eb87f
SE
342 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
343 an->mpdudensity = density;
87792efc 344 }
ff37e337
S
345}
346
347static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
348{
349 struct ath_node *an = (struct ath_node *)sta->drv_priv;
350
a4d6367f 351 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
ff37e337
S
352 ath_tx_node_cleanup(sc, an);
353}
354
55624204 355void ath9k_tasklet(unsigned long data)
ff37e337
S
356{
357 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 358 struct ath_hw *ah = sc->sc_ah;
c46917bb 359 struct ath_common *common = ath9k_hw_common(ah);
124b979b 360 enum ath_reset_type type;
07c15a3f 361 unsigned long flags;
17d7904d 362 u32 status = sc->intrstatus;
b5c80475 363 u32 rxmask;
ff37e337 364
e3927007
FF
365 ath9k_ps_wakeup(sc);
366 spin_lock(&sc->sc_pcu_lock);
367
a4d86d95
RM
368 if ((status & ATH9K_INT_FATAL) ||
369 (status & ATH9K_INT_BB_WATCHDOG)) {
030d6294
FF
370
371 if (status & ATH9K_INT_FATAL)
372 type = RESET_TYPE_FATAL_INT;
373 else
374 type = RESET_TYPE_BB_WATCHDOG;
375
124b979b 376 ath9k_queue_reset(sc, type);
e3927007 377 goto out;
063d8be3 378 }
ff37e337 379
07c15a3f 380 spin_lock_irqsave(&sc->sc_pm_lock, flags);
4105f807
RM
381 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
382 /*
383 * TSF sync does not look correct; remain awake to sync with
384 * the next Beacon.
385 */
d2182b69 386 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
e8fe7336 387 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
4105f807 388 }
07c15a3f 389 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
4105f807 390
b5c80475
FF
391 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
392 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
393 ATH9K_INT_RXORN);
394 else
395 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
396
397 if (status & rxmask) {
b5c80475
FF
398 /* Check for high priority Rx first */
399 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
400 (status & ATH9K_INT_RXHP))
401 ath_rx_tasklet(sc, 0, true);
402
403 ath_rx_tasklet(sc, 0, false);
ff37e337
S
404 }
405
e5003249
VT
406 if (status & ATH9K_INT_TX) {
407 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
408 ath_tx_edma_tasklet(sc);
409 else
410 ath_tx_tasklet(sc);
411 }
063d8be3 412
56ca0dba 413 ath9k_btcoex_handle_interrupt(sc, status);
19686ddf 414
e3927007 415out:
ff37e337 416 /* re-enable hardware interrupt */
4df3071e 417 ath9k_hw_enable_interrupts(ah);
6a6733f2 418
52671e43 419 spin_unlock(&sc->sc_pcu_lock);
153e080d 420 ath9k_ps_restore(sc);
ff37e337
S
421}
422
6baff7f9 423irqreturn_t ath_isr(int irq, void *dev)
ff37e337 424{
063d8be3
S
425#define SCHED_INTR ( \
426 ATH9K_INT_FATAL | \
a4d86d95 427 ATH9K_INT_BB_WATCHDOG | \
063d8be3
S
428 ATH9K_INT_RXORN | \
429 ATH9K_INT_RXEOL | \
430 ATH9K_INT_RX | \
b5c80475
FF
431 ATH9K_INT_RXLP | \
432 ATH9K_INT_RXHP | \
063d8be3
S
433 ATH9K_INT_TX | \
434 ATH9K_INT_BMISS | \
435 ATH9K_INT_CST | \
ebb8e1d7 436 ATH9K_INT_TSFOOR | \
40dc5392
MSS
437 ATH9K_INT_GENTIMER | \
438 ATH9K_INT_MCI)
063d8be3 439
ff37e337 440 struct ath_softc *sc = dev;
cbe61d8a 441 struct ath_hw *ah = sc->sc_ah;
b5bfc568 442 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
443 enum ath9k_int status;
444 bool sched = false;
445
063d8be3
S
446 /*
447 * The hardware is not ready/present, don't
448 * touch anything. Note this can happen early
449 * on if the IRQ is shared.
450 */
781b14a3 451 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
063d8be3 452 return IRQ_NONE;
ff37e337 453
063d8be3
S
454 /* shared irq, not for us */
455
153e080d 456 if (!ath9k_hw_intrpend(ah))
063d8be3 457 return IRQ_NONE;
063d8be3 458
f41a9b3b
FF
459 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
460 ath9k_hw_kill_interrupts(ah);
b74713d0 461 return IRQ_HANDLED;
f41a9b3b 462 }
b74713d0 463
063d8be3
S
464 /*
465 * Figure out the reason(s) for the interrupt. Note
466 * that the hal returns a pseudo-ISR that may include
467 * bits we haven't explicitly enabled so we mask the
468 * value to insure we only process bits we requested.
469 */
470 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 471 status &= ah->imask; /* discard unasked-for bits */
ff37e337 472
063d8be3
S
473 /*
474 * If there are no status bits set, then this interrupt was not
475 * for me (should have been caught above).
476 */
153e080d 477 if (!status)
063d8be3 478 return IRQ_NONE;
ff37e337 479
063d8be3
S
480 /* Cache the status */
481 sc->intrstatus = status;
482
483 if (status & SCHED_INTR)
484 sched = true;
485
486 /*
487 * If a FATAL or RXORN interrupt is received, we have to reset the
488 * chip immediately.
489 */
b5c80475
FF
490 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
491 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S
492 goto chip_reset;
493
08578b8f
LR
494 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
495 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF
496
497 spin_lock(&common->cc_lock);
498 ath_hw_cycle_counters_update(common);
08578b8f 499 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF
500 spin_unlock(&common->cc_lock);
501
08578b8f
LR
502 goto chip_reset;
503 }
ca90ef44
RM
504#ifdef CONFIG_PM_SLEEP
505 if (status & ATH9K_INT_BMISS) {
506 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
507 ath_dbg(common, ANY, "during WoW we got a BMISS\n");
508 atomic_inc(&sc->wow_got_bmiss_intr);
509 atomic_dec(&sc->wow_sleep_proc_intr);
510 }
511 }
512#endif
063d8be3
S
513 if (status & ATH9K_INT_SWBA)
514 tasklet_schedule(&sc->bcon_tasklet);
515
516 if (status & ATH9K_INT_TXURN)
517 ath9k_hw_updatetxtriglevel(ah, true);
518
0682c9b5
RM
519 if (status & ATH9K_INT_RXEOL) {
520 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
72d874c6 521 ath9k_hw_set_interrupts(ah);
b5c80475
FF
522 }
523
153e080d
VT
524 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
525 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR
526 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
527 goto chip_reset;
063d8be3
S
528 /* Clear RxAbort bit so that we can
529 * receive frames */
9ecdef4b 530 ath9k_setpower(sc, ATH9K_PM_AWAKE);
07c15a3f 531 spin_lock(&sc->sc_pm_lock);
153e080d 532 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 533 sc->ps_flags |= PS_WAIT_FOR_BEACON;
07c15a3f 534 spin_unlock(&sc->sc_pm_lock);
ff37e337 535 }
063d8be3
S
536
537chip_reset:
ff37e337 538
817e11de
S
539 ath_debug_stat_interrupt(sc, status);
540
ff37e337 541 if (sched) {
4df3071e
FF
542 /* turn off every interrupt */
543 ath9k_hw_disable_interrupts(ah);
ff37e337
S
544 tasklet_schedule(&sc->intr_tq);
545 }
546
547 return IRQ_HANDLED;
063d8be3
S
548
549#undef SCHED_INTR
ff37e337
S
550}
551
236de514 552static int ath_reset(struct ath_softc *sc, bool retry_tx)
ff37e337 553{
ae8d2858 554 int r;
ff37e337 555
783cd01e 556 ath9k_ps_wakeup(sc);
6a6733f2 557
9adcf440 558 r = ath_reset_internal(sc, NULL, retry_tx);
ff37e337
S
559
560 if (retry_tx) {
561 int i;
562 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
563 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
564 spin_lock_bh(&sc->tx.txq[i].axq_lock);
565 ath_txq_schedule(sc, &sc->tx.txq[i]);
566 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
567 }
568 }
569 }
570
783cd01e 571 ath9k_ps_restore(sc);
2ab81d4a 572
ae8d2858 573 return r;
ff37e337
S
574}
575
124b979b
RM
576void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
577{
578#ifdef CONFIG_ATH9K_DEBUGFS
579 RESET_STAT_INC(sc, type);
580#endif
581 set_bit(SC_OP_HW_RESET, &sc->sc_flags);
582 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
583}
584
236de514
FF
585void ath_reset_work(struct work_struct *work)
586{
587 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
588
236de514 589 ath_reset(sc, true);
236de514
FF
590}
591
ff37e337
S
592/**********************/
593/* mac80211 callbacks */
594/**********************/
595
8feceb67 596static int ath9k_start(struct ieee80211_hw *hw)
f078f209 597{
9ac58615 598 struct ath_softc *sc = hw->priv;
af03abec 599 struct ath_hw *ah = sc->sc_ah;
c46917bb 600 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 601 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 602 struct ath9k_channel *init_channel;
82880a7c 603 int r;
f078f209 604
d2182b69 605 ath_dbg(common, CONFIG,
226afe68
JP
606 "Starting driver with initial channel: %d MHz\n",
607 curchan->center_freq);
f078f209 608
f62d816f 609 ath9k_ps_wakeup(sc);
141b38b6
S
610 mutex_lock(&sc->mutex);
611
c344c9cb 612 init_channel = ath9k_cmn_get_curchannel(hw, ah);
ff37e337
S
613
614 /* Reset SERDES registers */
84c87dc8 615 ath9k_hw_configpcipowersave(ah, false);
ff37e337
S
616
617 /*
618 * The basic interface to setting the hardware in a good
619 * state is ``reset''. On return the hardware is known to
620 * be powered up and with interrupts disabled. This must
621 * be followed by initialization of the appropriate bits
622 * and then setup of the interrupt mask.
623 */
4bdd1e97 624 spin_lock_bh(&sc->sc_pcu_lock);
c0c11741
FF
625
626 atomic_set(&ah->intr_ref_cnt, -1);
627
20bd2a09 628 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 629 if (r) {
3800276a
JP
630 ath_err(common,
631 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
632 r, curchan->center_freq);
ceb26a60 633 ah->reset_power_on = false;
ff37e337 634 }
ff37e337 635
ff37e337 636 /* Setup our intr mask. */
b5c80475
FF
637 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
638 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
639 ATH9K_INT_GLOBAL;
640
641 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR
642 ah->imask |= ATH9K_INT_RXHP |
643 ATH9K_INT_RXLP |
644 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF
645 else
646 ah->imask |= ATH9K_INT_RX;
ff37e337 647
364734fa 648 ah->imask |= ATH9K_INT_GTT;
ff37e337 649
af03abec 650 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 651 ah->imask |= ATH9K_INT_CST;
ff37e337 652
e270e776 653 ath_mci_enable(sc);
40dc5392 654
781b14a3 655 clear_bit(SC_OP_INVALID, &sc->sc_flags);
5f841b41 656 sc->sc_ah->is_monitoring = false;
ff37e337 657
ceb26a60
FF
658 if (!ath_complete_reset(sc, false))
659 ah->reset_power_on = false;
ff37e337 660
c0c11741
FF
661 if (ah->led_pin >= 0) {
662 ath9k_hw_cfg_output(ah, ah->led_pin,
663 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
664 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
665 }
666
667 /*
668 * Reset key cache to sane defaults (all entries cleared) instead of
669 * semi-random values after suspend/resume.
670 */
671 ath9k_cmn_init_crypto(sc->sc_ah);
672
9adcf440 673 spin_unlock_bh(&sc->sc_pcu_lock);
164ace38 674
141b38b6
S
675 mutex_unlock(&sc->mutex);
676
f62d816f
FF
677 ath9k_ps_restore(sc);
678
ceb26a60 679 return 0;
f078f209
LR
680}
681
36323f81
TH
682static void ath9k_tx(struct ieee80211_hw *hw,
683 struct ieee80211_tx_control *control,
684 struct sk_buff *skb)
f078f209 685{
9ac58615 686 struct ath_softc *sc = hw->priv;
c46917bb 687 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 688 struct ath_tx_control txctl;
1bc14880 689 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
07c15a3f 690 unsigned long flags;
528f0c6b 691
96148326 692 if (sc->ps_enabled) {
dc8c4585
JM
693 /*
694 * mac80211 does not set PM field for normal data frames, so we
695 * need to update that based on the current PS mode.
696 */
697 if (ieee80211_is_data(hdr->frame_control) &&
698 !ieee80211_is_nullfunc(hdr->frame_control) &&
699 !ieee80211_has_pm(hdr->frame_control)) {
d2182b69 700 ath_dbg(common, PS,
226afe68 701 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM
702 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
703 }
704 }
705
ad128860 706 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
9a23f9ca
JM
707 /*
708 * We are using PS-Poll and mac80211 can request TX while in
709 * power save mode. Need to wake up hardware for the TX to be
710 * completed and if needed, also for RX of buffered frames.
711 */
9a23f9ca 712 ath9k_ps_wakeup(sc);
07c15a3f 713 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fdf76622
VT
714 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
715 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 716 if (ieee80211_is_pspoll(hdr->frame_control)) {
d2182b69 717 ath_dbg(common, PS,
226afe68 718 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 719 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 720 } else {
d2182b69 721 ath_dbg(common, PS, "Wake up to complete TX\n");
1b04b930 722 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
723 }
724 /*
725 * The actual restore operation will happen only after
ad128860 726 * the ps_flags bit is cleared. We are just dropping
9a23f9ca
JM
727 * the ps_usecount here.
728 */
07c15a3f 729 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
9a23f9ca
JM
730 ath9k_ps_restore(sc);
731 }
732
ad128860
SM
733 /*
734 * Cannot tx while the hardware is in full sleep, it first needs a full
735 * chip reset to recover from that
736 */
737 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
738 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
739 goto exit;
740 }
741
528f0c6b 742 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 743 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
36323f81 744 txctl.sta = control->sta;
528f0c6b 745
d2182b69 746 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 747
c52f33d0 748 if (ath_tx_start(hw, skb, &txctl) != 0) {
d2182b69 749 ath_dbg(common, XMIT, "TX failed\n");
a5a0bca1 750 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
528f0c6b 751 goto exit;
8feceb67
VT
752 }
753
7bb45683 754 return;
528f0c6b 755exit:
249ee722 756 ieee80211_free_txskb(hw, skb);
f078f209
LR
757}
758
8feceb67 759static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 760{
9ac58615 761 struct ath_softc *sc = hw->priv;
af03abec 762 struct ath_hw *ah = sc->sc_ah;
c46917bb 763 struct ath_common *common = ath9k_hw_common(ah);
c0c11741 764 bool prev_idle;
f078f209 765
4c483817
S
766 mutex_lock(&sc->mutex);
767
9adcf440 768 ath_cancel_work(sc);
01e18918 769 del_timer_sync(&sc->rx_poll_timer);
c94dbff7 770
781b14a3 771 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
d2182b69 772 ath_dbg(common, ANY, "Device not present\n");
4c483817 773 mutex_unlock(&sc->mutex);
9c84b797
S
774 return;
775 }
8feceb67 776
3867cf6a
S
777 /* Ensure HW is awake when we try to shut it down. */
778 ath9k_ps_wakeup(sc);
779
6a6733f2
LR
780 spin_lock_bh(&sc->sc_pcu_lock);
781
203043f5
SG
782 /* prevent tasklets to enable interrupts once we disable them */
783 ah->imask &= ~ATH9K_INT_GLOBAL;
784
ff37e337
S
785 /* make sure h/w will not generate any interrupt
786 * before setting the invalid flag. */
4df3071e 787 ath9k_hw_disable_interrupts(ah);
ff37e337 788
c0c11741
FF
789 spin_unlock_bh(&sc->sc_pcu_lock);
790
791 /* we can now sync irq and kill any running tasklets, since we already
792 * disabled interrupts and not holding a spin lock */
793 synchronize_irq(sc->irq);
794 tasklet_kill(&sc->intr_tq);
795 tasklet_kill(&sc->bcon_tasklet);
796
797 prev_idle = sc->ps_idle;
798 sc->ps_idle = true;
799
800 spin_lock_bh(&sc->sc_pcu_lock);
801
802 if (ah->led_pin >= 0) {
803 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
804 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
805 }
806
807 ath_prepare_reset(sc, false, true);
ff37e337 808
0d95521e
FF
809 if (sc->rx.frag) {
810 dev_kfree_skb_any(sc->rx.frag);
811 sc->rx.frag = NULL;
812 }
813
c0c11741
FF
814 if (!ah->curchan)
815 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
6a6733f2 816
c0c11741
FF
817 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
818 ath9k_hw_phy_disable(ah);
6a6733f2 819
c0c11741 820 ath9k_hw_configpcipowersave(ah, true);
203043f5 821
c0c11741 822 spin_unlock_bh(&sc->sc_pcu_lock);
3867cf6a 823
c0c11741 824 ath9k_ps_restore(sc);
ff37e337 825
781b14a3 826 set_bit(SC_OP_INVALID, &sc->sc_flags);
c0c11741 827 sc->ps_idle = prev_idle;
500c064d 828
141b38b6
S
829 mutex_unlock(&sc->mutex);
830
d2182b69 831 ath_dbg(common, CONFIG, "Driver halt\n");
f078f209
LR
832}
833
4801416c
BG
834bool ath9k_uses_beacons(int type)
835{
836 switch (type) {
837 case NL80211_IFTYPE_AP:
838 case NL80211_IFTYPE_ADHOC:
839 case NL80211_IFTYPE_MESH_POINT:
840 return true;
841 default:
842 return false;
843 }
844}
845
4801416c
BG
846static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
847{
848 struct ath9k_vif_iter_data *iter_data = data;
849 int i;
850
851 if (iter_data->hw_macaddr)
852 for (i = 0; i < ETH_ALEN; i++)
853 iter_data->mask[i] &=
854 ~(iter_data->hw_macaddr[i] ^ mac[i]);
141b38b6 855
1ed32e4f 856 switch (vif->type) {
4801416c
BG
857 case NL80211_IFTYPE_AP:
858 iter_data->naps++;
f078f209 859 break;
4801416c
BG
860 case NL80211_IFTYPE_STATION:
861 iter_data->nstations++;
e51f3eff 862 break;
05c914fe 863 case NL80211_IFTYPE_ADHOC:
4801416c
BG
864 iter_data->nadhocs++;
865 break;
9cb5412b 866 case NL80211_IFTYPE_MESH_POINT:
4801416c
BG
867 iter_data->nmeshes++;
868 break;
869 case NL80211_IFTYPE_WDS:
870 iter_data->nwds++;
f078f209
LR
871 break;
872 default:
4801416c 873 break;
f078f209 874 }
4801416c 875}
f078f209 876
6dcc3444
SM
877static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
878{
879 struct ath_softc *sc = data;
880 struct ath_vif *avp = (void *)vif->drv_priv;
881
882 if (vif->type != NL80211_IFTYPE_STATION)
883 return;
884
885 if (avp->primary_sta_vif)
886 ath9k_set_assoc_state(sc, vif);
887}
888
4801416c
BG
889/* Called with sc->mutex held. */
890void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
891 struct ieee80211_vif *vif,
892 struct ath9k_vif_iter_data *iter_data)
893{
9ac58615 894 struct ath_softc *sc = hw->priv;
4801416c
BG
895 struct ath_hw *ah = sc->sc_ah;
896 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 897
4801416c
BG
898 /*
899 * Use the hardware MAC address as reference, the hardware uses it
900 * together with the BSSID mask when matching addresses.
901 */
902 memset(iter_data, 0, sizeof(*iter_data));
903 iter_data->hw_macaddr = common->macaddr;
904 memset(&iter_data->mask, 0xff, ETH_ALEN);
5640b08e 905
4801416c
BG
906 if (vif)
907 ath9k_vif_iter(iter_data, vif->addr, vif);
908
909 /* Get list of all active MAC addresses */
8b2c9824
JB
910 ieee80211_iterate_active_interfaces_atomic(
911 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
912 ath9k_vif_iter, iter_data);
4801416c 913}
8ca21f01 914
4801416c
BG
915/* Called with sc->mutex held. */
916static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
917 struct ieee80211_vif *vif)
918{
9ac58615 919 struct ath_softc *sc = hw->priv;
4801416c
BG
920 struct ath_hw *ah = sc->sc_ah;
921 struct ath_common *common = ath9k_hw_common(ah);
922 struct ath9k_vif_iter_data iter_data;
6dcc3444 923 enum nl80211_iftype old_opmode = ah->opmode;
8ca21f01 924
4801416c 925 ath9k_calculate_iter_data(hw, vif, &iter_data);
2c3db3d5 926
4801416c
BG
927 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
928 ath_hw_setbssidmask(common);
929
4801416c 930 if (iter_data.naps > 0) {
60ca9f87 931 ath9k_hw_set_tsfadjust(ah, true);
4801416c
BG
932 ah->opmode = NL80211_IFTYPE_AP;
933 } else {
60ca9f87 934 ath9k_hw_set_tsfadjust(ah, false);
5640b08e 935
fd5999cf
JC
936 if (iter_data.nmeshes)
937 ah->opmode = NL80211_IFTYPE_MESH_POINT;
938 else if (iter_data.nwds)
4801416c
BG
939 ah->opmode = NL80211_IFTYPE_AP;
940 else if (iter_data.nadhocs)
941 ah->opmode = NL80211_IFTYPE_ADHOC;
942 else
943 ah->opmode = NL80211_IFTYPE_STATION;
944 }
5640b08e 945
df35d29e
SM
946 ath9k_hw_setopmode(ah);
947
198823fd 948 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
3069168c 949 ah->imask |= ATH9K_INT_TSFOOR;
198823fd 950 else
4801416c 951 ah->imask &= ~ATH9K_INT_TSFOOR;
4af9cf4f 952
72d874c6 953 ath9k_hw_set_interrupts(ah);
6dcc3444
SM
954
955 /*
956 * If we are changing the opmode to STATION,
957 * a beacon sync needs to be done.
958 */
959 if (ah->opmode == NL80211_IFTYPE_STATION &&
960 old_opmode == NL80211_IFTYPE_AP &&
961 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
8b2c9824
JB
962 ieee80211_iterate_active_interfaces_atomic(
963 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
964 ath9k_sta_vif_iter, sc);
6dcc3444 965 }
4801416c 966}
6f255425 967
4801416c
BG
968static int ath9k_add_interface(struct ieee80211_hw *hw,
969 struct ieee80211_vif *vif)
6b3b991d 970{
9ac58615 971 struct ath_softc *sc = hw->priv;
4801416c
BG
972 struct ath_hw *ah = sc->sc_ah;
973 struct ath_common *common = ath9k_hw_common(ah);
6b3b991d 974
4801416c 975 mutex_lock(&sc->mutex);
6b3b991d 976
d2182b69 977 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
4801416c
BG
978 sc->nvifs++;
979
327967cb 980 ath9k_ps_wakeup(sc);
130ef6e9 981 ath9k_calculate_summary_state(hw, vif);
327967cb
MSS
982 ath9k_ps_restore(sc);
983
130ef6e9
SM
984 if (ath9k_uses_beacons(vif->type))
985 ath9k_beacon_assign_slot(sc, vif);
986
4801416c 987 mutex_unlock(&sc->mutex);
327967cb 988 return 0;
6b3b991d
RM
989}
990
991static int ath9k_change_interface(struct ieee80211_hw *hw,
992 struct ieee80211_vif *vif,
993 enum nl80211_iftype new_type,
994 bool p2p)
995{
9ac58615 996 struct ath_softc *sc = hw->priv;
6b3b991d
RM
997 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
998
d2182b69 999 ath_dbg(common, CONFIG, "Change Interface\n");
6b3b991d 1000 mutex_lock(&sc->mutex);
4801416c 1001
4801416c 1002 if (ath9k_uses_beacons(vif->type))
130ef6e9 1003 ath9k_beacon_remove_slot(sc, vif);
4801416c 1004
6b3b991d
RM
1005 vif->type = new_type;
1006 vif->p2p = p2p;
1007
327967cb 1008 ath9k_ps_wakeup(sc);
130ef6e9 1009 ath9k_calculate_summary_state(hw, vif);
327967cb
MSS
1010 ath9k_ps_restore(sc);
1011
130ef6e9
SM
1012 if (ath9k_uses_beacons(vif->type))
1013 ath9k_beacon_assign_slot(sc, vif);
1014
6b3b991d 1015 mutex_unlock(&sc->mutex);
327967cb 1016 return 0;
6b3b991d
RM
1017}
1018
8feceb67 1019static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1020 struct ieee80211_vif *vif)
f078f209 1021{
9ac58615 1022 struct ath_softc *sc = hw->priv;
c46917bb 1023 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f078f209 1024
d2182b69 1025 ath_dbg(common, CONFIG, "Detach Interface\n");
f078f209 1026
141b38b6
S
1027 mutex_lock(&sc->mutex);
1028
4801416c 1029 sc->nvifs--;
580f0b8a 1030
4801416c 1031 if (ath9k_uses_beacons(vif->type))
130ef6e9 1032 ath9k_beacon_remove_slot(sc, vif);
2c3db3d5 1033
327967cb 1034 ath9k_ps_wakeup(sc);
4801416c 1035 ath9k_calculate_summary_state(hw, NULL);
327967cb 1036 ath9k_ps_restore(sc);
141b38b6
S
1037
1038 mutex_unlock(&sc->mutex);
f078f209
LR
1039}
1040
fbab7390 1041static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1042{
3069168c 1043 struct ath_hw *ah = sc->sc_ah;
ad128860 1044 struct ath_common *common = ath9k_hw_common(ah);
3069168c 1045
3f7c5c10 1046 sc->ps_enabled = true;
3069168c
PR
1047 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1048 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1049 ah->imask |= ATH9K_INT_TIM_TIMER;
72d874c6 1050 ath9k_hw_set_interrupts(ah);
3f7c5c10 1051 }
fdf76622 1052 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1053 }
ad128860 1054 ath_dbg(common, PS, "PowerSave enabled\n");
3f7c5c10
SB
1055}
1056
845d708e
SB
1057static void ath9k_disable_ps(struct ath_softc *sc)
1058{
1059 struct ath_hw *ah = sc->sc_ah;
ad128860 1060 struct ath_common *common = ath9k_hw_common(ah);
845d708e
SB
1061
1062 sc->ps_enabled = false;
1063 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1064 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1065 ath9k_hw_setrxabort(ah, 0);
1066 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1067 PS_WAIT_FOR_CAB |
1068 PS_WAIT_FOR_PSPOLL_DATA |
1069 PS_WAIT_FOR_TX_ACK);
1070 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1071 ah->imask &= ~ATH9K_INT_TIM_TIMER;
72d874c6 1072 ath9k_hw_set_interrupts(ah);
845d708e
SB
1073 }
1074 }
ad128860 1075 ath_dbg(common, PS, "PowerSave disabled\n");
845d708e
SB
1076}
1077
e8975581 1078static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1079{
9ac58615 1080 struct ath_softc *sc = hw->priv;
3430098a
FF
1081 struct ath_hw *ah = sc->sc_ah;
1082 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1083 struct ieee80211_conf *conf = &hw->conf;
75600abf 1084 bool reset_channel = false;
f078f209 1085
c0c11741 1086 ath9k_ps_wakeup(sc);
aa33de09 1087 mutex_lock(&sc->mutex);
141b38b6 1088
daa1b6ee 1089 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4 1090 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
b73f3e78 1091 if (sc->ps_idle) {
daa1b6ee 1092 ath_cancel_work(sc);
b73f3e78
RM
1093 ath9k_stop_btcoex(sc);
1094 } else {
1095 ath9k_start_btcoex(sc);
75600abf
FF
1096 /*
1097 * The chip needs a reset to properly wake up from
1098 * full sleep
1099 */
1100 reset_channel = ah->chip_fullsleep;
b73f3e78 1101 }
daa1b6ee 1102 }
64839170 1103
e7824a50
LR
1104 /*
1105 * We just prepare to enable PS. We have to wait until our AP has
1106 * ACK'd our null data frame to disable RX otherwise we'll ignore
1107 * those ACKs and end up retransmitting the same null data frames.
1108 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1109 */
3cbb5dd7 1110 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR
1111 unsigned long flags;
1112 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB
1113 if (conf->flags & IEEE80211_CONF_PS)
1114 ath9k_enable_ps(sc);
845d708e
SB
1115 else
1116 ath9k_disable_ps(sc);
8ab2cd09 1117 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN
1118 }
1119
199afd9d
S
1120 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1121 if (conf->flags & IEEE80211_CONF_MONITOR) {
d2182b69 1122 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
5f841b41
RM
1123 sc->sc_ah->is_monitoring = true;
1124 } else {
d2182b69 1125 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
5f841b41 1126 sc->sc_ah->is_monitoring = false;
199afd9d
S
1127 }
1128 }
1129
75600abf 1130 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
99405f93 1131 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1132 int pos = curchan->hw_value;
3430098a
FF
1133 int old_pos = -1;
1134 unsigned long flags;
1135
1136 if (ah->curchan)
1137 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1138
d2182b69 1139 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
8c79a610 1140 curchan->center_freq, conf->channel_type);
f078f209 1141
3430098a
FF
1142 /* update survey stats for the old channel before switching */
1143 spin_lock_irqsave(&common->cc_lock, flags);
1144 ath_update_survey_stats(sc);
1145 spin_unlock_irqrestore(&common->cc_lock, flags);
1146
e338a85e
RM
1147 /*
1148 * Preserve the current channel values, before updating
1149 * the same channel
1150 */
1a19f77f
RM
1151 if (ah->curchan && (old_pos == pos))
1152 ath9k_hw_getnf(ah, ah->curchan);
e338a85e
RM
1153
1154 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1155 curchan, conf->channel_type);
1156
3430098a
FF
1157 /*
1158 * If the operating channel changes, change the survey in-use flags
1159 * along with it.
1160 * Reset the survey data for the new channel, unless we're switching
1161 * back to the operating channel from an off-channel operation.
1162 */
1163 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1164 sc->cur_survey != &sc->survey[pos]) {
1165
1166 if (sc->cur_survey)
1167 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1168
1169 sc->cur_survey = &sc->survey[pos];
1170
1171 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1172 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1173 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1174 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1175 }
1176
0e2dedf9 1177 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
3800276a 1178 ath_err(common, "Unable to set channel\n");
aa33de09 1179 mutex_unlock(&sc->mutex);
8389fb3f 1180 ath9k_ps_restore(sc);
e11602b7
S
1181 return -EINVAL;
1182 }
3430098a
FF
1183
1184 /*
1185 * The most recent snapshot of channel->noisefloor for the old
1186 * channel is only available after the hardware reset. Copy it to
1187 * the survey stats now.
1188 */
1189 if (old_pos >= 0)
1190 ath_update_survey_nf(sc, old_pos);
094d05dc 1191 }
f078f209 1192
c9f6a656 1193 if (changed & IEEE80211_CONF_CHANGE_POWER) {
d2182b69 1194 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
17d7904d 1195 sc->config.txpowlimit = 2 * conf->power_level;
5048e8c3
RM
1196 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1197 sc->config.txpowlimit, &sc->curtxpow);
64839170
LR
1198 }
1199
aa33de09 1200 mutex_unlock(&sc->mutex);
c0c11741 1201 ath9k_ps_restore(sc);
141b38b6 1202
f078f209
LR
1203 return 0;
1204}
1205
8feceb67
VT
1206#define SUPPORTED_FILTERS \
1207 (FIF_PROMISC_IN_BSS | \
1208 FIF_ALLMULTI | \
1209 FIF_CONTROL | \
af6a3fc7 1210 FIF_PSPOLL | \
8feceb67
VT
1211 FIF_OTHER_BSS | \
1212 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1213 FIF_PROBE_REQ | \
8feceb67 1214 FIF_FCSFAIL)
c83be688 1215
8feceb67
VT
1216/* FIXME: sc->sc_full_reset ? */
1217static void ath9k_configure_filter(struct ieee80211_hw *hw,
1218 unsigned int changed_flags,
1219 unsigned int *total_flags,
3ac64bee 1220 u64 multicast)
8feceb67 1221{
9ac58615 1222 struct ath_softc *sc = hw->priv;
8feceb67 1223 u32 rfilt;
f078f209 1224
8feceb67
VT
1225 changed_flags &= SUPPORTED_FILTERS;
1226 *total_flags &= SUPPORTED_FILTERS;
f078f209 1227
b77f483f 1228 sc->rx.rxfilter = *total_flags;
aa68aeaa 1229 ath9k_ps_wakeup(sc);
8feceb67
VT
1230 rfilt = ath_calcrxfilter(sc);
1231 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1232 ath9k_ps_restore(sc);
f078f209 1233
d2182b69
JP
1234 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1235 rfilt);
8feceb67 1236}
f078f209 1237
4ca77860
JB
1238static int ath9k_sta_add(struct ieee80211_hw *hw,
1239 struct ieee80211_vif *vif,
1240 struct ieee80211_sta *sta)
8feceb67 1241{
9ac58615 1242 struct ath_softc *sc = hw->priv;
93ae2dd2
FF
1243 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1244 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1245 struct ieee80211_key_conf ps_key = { };
f078f209 1246
7e1e3864 1247 ath_node_attach(sc, sta, vif);
f59a59fe
FF
1248
1249 if (vif->type != NL80211_IFTYPE_AP &&
1250 vif->type != NL80211_IFTYPE_AP_VLAN)
1251 return 0;
1252
93ae2dd2 1253 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
4ca77860
JB
1254
1255 return 0;
1256}
1257
93ae2dd2
FF
1258static void ath9k_del_ps_key(struct ath_softc *sc,
1259 struct ieee80211_vif *vif,
1260 struct ieee80211_sta *sta)
1261{
1262 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1263 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1264 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1265
1266 if (!an->ps_key)
1267 return;
1268
1269 ath_key_delete(common, &ps_key);
1270}
1271
4ca77860
JB
1272static int ath9k_sta_remove(struct ieee80211_hw *hw,
1273 struct ieee80211_vif *vif,
1274 struct ieee80211_sta *sta)
1275{
9ac58615 1276 struct ath_softc *sc = hw->priv;
4ca77860 1277
93ae2dd2 1278 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB
1279 ath_node_detach(sc, sta);
1280
1281 return 0;
f078f209
LR
1282}
1283
5519541d
FF
1284static void ath9k_sta_notify(struct ieee80211_hw *hw,
1285 struct ieee80211_vif *vif,
1286 enum sta_notify_cmd cmd,
1287 struct ieee80211_sta *sta)
1288{
1289 struct ath_softc *sc = hw->priv;
1290 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1291
3d4e20f2 1292 if (!sta->ht_cap.ht_supported)
b25bfda3
MSS
1293 return;
1294
5519541d
FF
1295 switch (cmd) {
1296 case STA_NOTIFY_SLEEP:
1297 an->sleeping = true;
042ec453 1298 ath_tx_aggr_sleep(sta, sc, an);
5519541d
FF
1299 break;
1300 case STA_NOTIFY_AWAKE:
1301 an->sleeping = false;
1302 ath_tx_aggr_wakeup(sc, an);
1303 break;
1304 }
1305}
1306
8a3a3c85
EP
1307static int ath9k_conf_tx(struct ieee80211_hw *hw,
1308 struct ieee80211_vif *vif, u16 queue,
8feceb67 1309 const struct ieee80211_tx_queue_params *params)
f078f209 1310{
9ac58615 1311 struct ath_softc *sc = hw->priv;
c46917bb 1312 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1313 struct ath_txq *txq;
8feceb67 1314 struct ath9k_tx_queue_info qi;
066dae93 1315 int ret = 0;
f078f209 1316
bea843c7 1317 if (queue >= IEEE80211_NUM_ACS)
8feceb67 1318 return 0;
f078f209 1319
066dae93
FF
1320 txq = sc->tx.txq_map[queue];
1321
96f372c9 1322 ath9k_ps_wakeup(sc);
141b38b6
S
1323 mutex_lock(&sc->mutex);
1324
1ffb0610
S
1325 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1326
8feceb67
VT
1327 qi.tqi_aifs = params->aifs;
1328 qi.tqi_cwmin = params->cw_min;
1329 qi.tqi_cwmax = params->cw_max;
531bd079 1330 qi.tqi_burstTime = params->txop * 32;
f078f209 1331
d2182b69 1332 ath_dbg(common, CONFIG,
226afe68
JP
1333 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1334 queue, txq->axq_qnum, params->aifs, params->cw_min,
1335 params->cw_max, params->txop);
f078f209 1336
aa5955c3 1337 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
066dae93 1338 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1339 if (ret)
3800276a 1340 ath_err(common, "TXQ Update failed\n");
f078f209 1341
141b38b6 1342 mutex_unlock(&sc->mutex);
96f372c9 1343 ath9k_ps_restore(sc);
141b38b6 1344
8feceb67
VT
1345 return ret;
1346}
f078f209 1347
8feceb67
VT
1348static int ath9k_set_key(struct ieee80211_hw *hw,
1349 enum set_key_cmd cmd,
dc822b5d
JB
1350 struct ieee80211_vif *vif,
1351 struct ieee80211_sta *sta,
8feceb67
VT
1352 struct ieee80211_key_conf *key)
1353{
9ac58615 1354 struct ath_softc *sc = hw->priv;
c46917bb 1355 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1356 int ret = 0;
f078f209 1357
3e6109c5 1358 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM
1359 return -ENOSPC;
1360
5bd5e9a6
CYY
1361 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1362 vif->type == NL80211_IFTYPE_MESH_POINT) &&
cfdc9a8b
JM
1363 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1364 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1365 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1366 /*
1367 * For now, disable hw crypto for the RSN IBSS group keys. This
1368 * could be optimized in the future to use a modified key cache
1369 * design to support per-STA RX GTK, but until that gets
1370 * implemented, use of software crypto for group addressed
1371 * frames is a acceptable to allow RSN IBSS to be used.
1372 */
1373 return -EOPNOTSUPP;
1374 }
1375
141b38b6 1376 mutex_lock(&sc->mutex);
3cbb5dd7 1377 ath9k_ps_wakeup(sc);
d2182b69 1378 ath_dbg(common, CONFIG, "Set HW Key\n");
f078f209 1379
8feceb67
VT
1380 switch (cmd) {
1381 case SET_KEY:
93ae2dd2
FF
1382 if (sta)
1383 ath9k_del_ps_key(sc, vif, sta);
1384
040e539e 1385 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1386 if (ret >= 0) {
1387 key->hw_key_idx = ret;
8feceb67
VT
1388 /* push IV and Michael MIC generation to stack */
1389 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1390 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1391 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB
1392 if (sc->sc_ah->sw_mgmt_crypto &&
1393 key->cipher == WLAN_CIPHER_SUITE_CCMP)
e548c49e 1394 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
6ace2891 1395 ret = 0;
8feceb67
VT
1396 }
1397 break;
1398 case DISABLE_KEY:
040e539e 1399 ath_key_delete(common, key);
8feceb67
VT
1400 break;
1401 default:
1402 ret = -EINVAL;
1403 }
f078f209 1404
3cbb5dd7 1405 ath9k_ps_restore(sc);
141b38b6
S
1406 mutex_unlock(&sc->mutex);
1407
8feceb67
VT
1408 return ret;
1409}
6c43c090
SM
1410
1411static void ath9k_set_assoc_state(struct ath_softc *sc,
1412 struct ieee80211_vif *vif)
4f5ef75b 1413{
4f5ef75b 1414 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
4f5ef75b 1415 struct ath_vif *avp = (void *)vif->drv_priv;
6c43c090 1416 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
07c15a3f 1417 unsigned long flags;
6c43c090
SM
1418
1419 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1420 avp->primary_sta_vif = true;
1421
2e5ef459 1422 /*
6c43c090
SM
1423 * Set the AID, BSSID and do beacon-sync only when
1424 * the HW opmode is STATION.
1425 *
1426 * But the primary bit is set above in any case.
2e5ef459 1427 */
6c43c090 1428 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
2e5ef459
RM
1429 return;
1430
6c43c090
SM
1431 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1432 common->curaid = bss_conf->aid;
1433 ath9k_hw_write_associd(sc->sc_ah);
07c15a3f 1434
6c43c090
SM
1435 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1436 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
99e4d43a 1437
6c43c090
SM
1438 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1439 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1440 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
05c0be2f 1441
50072ebc
RM
1442 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1443 ath9k_mci_update_wlan_channels(sc, false);
1444
6c43c090
SM
1445 ath_dbg(common, CONFIG,
1446 "Primary Station interface: %pM, BSSID: %pM\n",
1447 vif->addr, common->curbssid);
4f5ef75b
RM
1448}
1449
6c43c090 1450static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
4f5ef75b 1451{
6c43c090 1452 struct ath_softc *sc = data;
4f5ef75b 1453 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
4f5ef75b 1454
6c43c090 1455 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
2e5ef459
RM
1456 return;
1457
6c43c090
SM
1458 if (bss_conf->assoc)
1459 ath9k_set_assoc_state(sc, vif);
4f5ef75b 1460}
f078f209 1461
8feceb67
VT
1462static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1463 struct ieee80211_vif *vif,
1464 struct ieee80211_bss_conf *bss_conf,
1465 u32 changed)
1466{
da0d45f7
SM
1467#define CHECK_ANI \
1468 (BSS_CHANGED_ASSOC | \
1469 BSS_CHANGED_IBSS | \
1470 BSS_CHANGED_BEACON_ENABLED)
1471
9ac58615 1472 struct ath_softc *sc = hw->priv;
2d0ddec5 1473 struct ath_hw *ah = sc->sc_ah;
1510718d 1474 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1475 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 1476 int slottime;
f078f209 1477
96f372c9 1478 ath9k_ps_wakeup(sc);
141b38b6
S
1479 mutex_lock(&sc->mutex);
1480
9f61903c 1481 if (changed & BSS_CHANGED_ASSOC) {
6c43c090
SM
1482 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1483 bss_conf->bssid, bss_conf->assoc);
1484
1485 if (avp->primary_sta_vif && !bss_conf->assoc) {
1486 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1487 avp->primary_sta_vif = false;
1488
1489 if (ah->opmode == NL80211_IFTYPE_STATION)
1490 clear_bit(SC_OP_BEACONS, &sc->sc_flags);
1491 }
1492
8b2c9824
JB
1493 ieee80211_iterate_active_interfaces_atomic(
1494 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1495 ath9k_bss_assoc_iter, sc);
2d0ddec5 1496
6c43c090
SM
1497 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
1498 ah->opmode == NL80211_IFTYPE_STATION) {
1499 memset(common->curbssid, 0, ETH_ALEN);
1500 common->curaid = 0;
1501 ath9k_hw_write_associd(sc->sc_ah);
50072ebc
RM
1502 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1503 ath9k_mci_update_wlan_channels(sc, true);
6c43c090 1504 }
c6089ccc 1505 }
2d0ddec5 1506
2e5ef459 1507 if (changed & BSS_CHANGED_IBSS) {
2e5ef459
RM
1508 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1509 common->curaid = bss_conf->aid;
1510 ath9k_hw_write_associd(sc->sc_ah);
2e5ef459
RM
1511 }
1512
ef4ad633
SM
1513 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1514 (changed & BSS_CHANGED_BEACON_INT)) {
2f8e82e8
SM
1515 if (ah->opmode == NL80211_IFTYPE_AP &&
1516 bss_conf->enable_beacon)
1517 ath9k_set_tsfadjust(sc, vif);
ef4ad633
SM
1518 if (ath9k_allow_beacon_config(sc, vif))
1519 ath9k_beacon_config(sc, vif, changed);
0005baf4
FF
1520 }
1521
1522 if (changed & BSS_CHANGED_ERP_SLOT) {
1523 if (bss_conf->use_short_slot)
1524 slottime = 9;
1525 else
1526 slottime = 20;
1527 if (vif->type == NL80211_IFTYPE_AP) {
1528 /*
1529 * Defer update, so that connected stations can adjust
1530 * their settings at the same time.
1531 * See beacon.c for more details
1532 */
1533 sc->beacon.slottime = slottime;
1534 sc->beacon.updateslot = UPDATE;
1535 } else {
1536 ah->slottime = slottime;
1537 ath9k_hw_init_global_settings(ah);
1538 }
2d0ddec5
JB
1539 }
1540
da0d45f7
SM
1541 if (changed & CHECK_ANI)
1542 ath_check_ani(sc);
1543
141b38b6 1544 mutex_unlock(&sc->mutex);
96f372c9 1545 ath9k_ps_restore(sc);
da0d45f7
SM
1546
1547#undef CHECK_ANI
8feceb67 1548}
f078f209 1549
37a41b4a 1550static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1551{
9ac58615 1552 struct ath_softc *sc = hw->priv;
8feceb67 1553 u64 tsf;
f078f209 1554
141b38b6 1555 mutex_lock(&sc->mutex);
9abbfb27 1556 ath9k_ps_wakeup(sc);
141b38b6 1557 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 1558 ath9k_ps_restore(sc);
141b38b6 1559 mutex_unlock(&sc->mutex);
f078f209 1560
8feceb67
VT
1561 return tsf;
1562}
f078f209 1563
37a41b4a
EP
1564static void ath9k_set_tsf(struct ieee80211_hw *hw,
1565 struct ieee80211_vif *vif,
1566 u64 tsf)
3b5d665b 1567{
9ac58615 1568 struct ath_softc *sc = hw->priv;
3b5d665b 1569
141b38b6 1570 mutex_lock(&sc->mutex);
9abbfb27 1571 ath9k_ps_wakeup(sc);
141b38b6 1572 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 1573 ath9k_ps_restore(sc);
141b38b6 1574 mutex_unlock(&sc->mutex);
3b5d665b
AF
1575}
1576
37a41b4a 1577static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1578{
9ac58615 1579 struct ath_softc *sc = hw->priv;
c83be688 1580
141b38b6 1581 mutex_lock(&sc->mutex);
21526d57
LR
1582
1583 ath9k_ps_wakeup(sc);
141b38b6 1584 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
1585 ath9k_ps_restore(sc);
1586
141b38b6 1587 mutex_unlock(&sc->mutex);
8feceb67 1588}
f078f209 1589
8feceb67 1590static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 1591 struct ieee80211_vif *vif,
141b38b6
S
1592 enum ieee80211_ampdu_mlme_action action,
1593 struct ieee80211_sta *sta,
0b01f030 1594 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 1595{
9ac58615 1596 struct ath_softc *sc = hw->priv;
8feceb67 1597 int ret = 0;
f078f209 1598
85ad181e
JB
1599 local_bh_disable();
1600
8feceb67
VT
1601 switch (action) {
1602 case IEEE80211_AMPDU_RX_START:
8feceb67
VT
1603 break;
1604 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
1605 break;
1606 case IEEE80211_AMPDU_TX_START:
8b685ba9 1607 ath9k_ps_wakeup(sc);
231c3a1f
FF
1608 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1609 if (!ret)
1610 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1611 ath9k_ps_restore(sc);
8feceb67
VT
1612 break;
1613 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 1614 ath9k_ps_wakeup(sc);
f83da965 1615 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 1616 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1617 ath9k_ps_restore(sc);
8feceb67 1618 break;
b1720231 1619 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 1620 ath9k_ps_wakeup(sc);
8469cdef 1621 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 1622 ath9k_ps_restore(sc);
8469cdef 1623 break;
8feceb67 1624 default:
3800276a 1625 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT
1626 }
1627
85ad181e
JB
1628 local_bh_enable();
1629
8feceb67 1630 return ret;
f078f209
LR
1631}
1632
62dad5b0
BP
1633static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1634 struct survey_info *survey)
1635{
9ac58615 1636 struct ath_softc *sc = hw->priv;
3430098a 1637 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 1638 struct ieee80211_supported_band *sband;
3430098a
FF
1639 struct ieee80211_channel *chan;
1640 unsigned long flags;
1641 int pos;
1642
1643 spin_lock_irqsave(&common->cc_lock, flags);
1644 if (idx == 0)
1645 ath_update_survey_stats(sc);
39162dbe
FF
1646
1647 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1648 if (sband && idx >= sband->n_channels) {
1649 idx -= sband->n_channels;
1650 sband = NULL;
1651 }
62dad5b0 1652
39162dbe
FF
1653 if (!sband)
1654 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 1655
3430098a
FF
1656 if (!sband || idx >= sband->n_channels) {
1657 spin_unlock_irqrestore(&common->cc_lock, flags);
1658 return -ENOENT;
4f1a5a4b 1659 }
62dad5b0 1660
3430098a
FF
1661 chan = &sband->channels[idx];
1662 pos = chan->hw_value;
1663 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1664 survey->channel = chan;
1665 spin_unlock_irqrestore(&common->cc_lock, flags);
1666
62dad5b0
BP
1667 return 0;
1668}
1669
e239d859
FF
1670static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
1671{
9ac58615 1672 struct ath_softc *sc = hw->priv;
e239d859
FF
1673 struct ath_hw *ah = sc->sc_ah;
1674
1675 mutex_lock(&sc->mutex);
1676 ah->coverage_class = coverage_class;
8b2a3827
MSS
1677
1678 ath9k_ps_wakeup(sc);
e239d859 1679 ath9k_hw_init_global_settings(ah);
8b2a3827
MSS
1680 ath9k_ps_restore(sc);
1681
e239d859
FF
1682 mutex_unlock(&sc->mutex);
1683}
1684
69081624
VT
1685static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
1686{
69081624 1687 struct ath_softc *sc = hw->priv;
99aa55b6
MSS
1688 struct ath_hw *ah = sc->sc_ah;
1689 struct ath_common *common = ath9k_hw_common(ah);
86271e46
FF
1690 int timeout = 200; /* ms */
1691 int i, j;
2f6fc351 1692 bool drain_txq;
69081624
VT
1693
1694 mutex_lock(&sc->mutex);
69081624
VT
1695 cancel_delayed_work_sync(&sc->tx_complete_work);
1696
6a6b3f3e 1697 if (ah->ah_flags & AH_UNPLUGGED) {
d2182b69 1698 ath_dbg(common, ANY, "Device has been unplugged!\n");
6a6b3f3e
MSS
1699 mutex_unlock(&sc->mutex);
1700 return;
1701 }
1702
781b14a3 1703 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
d2182b69 1704 ath_dbg(common, ANY, "Device not present\n");
99aa55b6
MSS
1705 mutex_unlock(&sc->mutex);
1706 return;
1707 }
1708
86271e46 1709 for (j = 0; j < timeout; j++) {
108697c4 1710 bool npend = false;
86271e46
FF
1711
1712 if (j)
1713 usleep_range(1000, 2000);
69081624 1714
86271e46
FF
1715 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1716 if (!ATH_TXQ_SETUP(sc, i))
1717 continue;
1718
108697c4
MSS
1719 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1720
1721 if (npend)
1722 break;
69081624 1723 }
86271e46
FF
1724
1725 if (!npend)
9df0d6a2 1726 break;
69081624
VT
1727 }
1728
9df0d6a2
FF
1729 if (drop) {
1730 ath9k_ps_wakeup(sc);
1731 spin_lock_bh(&sc->sc_pcu_lock);
1732 drain_txq = ath_drain_all_txq(sc, false);
1733 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440 1734
9df0d6a2
FF
1735 if (!drain_txq)
1736 ath_reset(sc, false);
9adcf440 1737
9df0d6a2
FF
1738 ath9k_ps_restore(sc);
1739 ieee80211_wake_queues(hw);
1740 }
d78f4b3e 1741
69081624
VT
1742 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
1743 mutex_unlock(&sc->mutex);
1744}
1745
15b91e83
VN
1746static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
1747{
1748 struct ath_softc *sc = hw->priv;
1749 int i;
1750
1751 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1752 if (!ATH_TXQ_SETUP(sc, i))
1753 continue;
1754
1755 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
1756 return true;
1757 }
1758 return false;
1759}
1760
5595f119 1761static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
ba4903f9
FF
1762{
1763 struct ath_softc *sc = hw->priv;
1764 struct ath_hw *ah = sc->sc_ah;
1765 struct ieee80211_vif *vif;
1766 struct ath_vif *avp;
1767 struct ath_buf *bf;
1768 struct ath_tx_status ts;
4286df60 1769 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
ba4903f9
FF
1770 int status;
1771
1772 vif = sc->beacon.bslot[0];
1773 if (!vif)
1774 return 0;
1775
aa45fe96 1776 if (!vif->bss_conf.enable_beacon)
ba4903f9
FF
1777 return 0;
1778
aa45fe96
SM
1779 avp = (void *)vif->drv_priv;
1780
4286df60 1781 if (!sc->beacon.tx_processed && !edma) {
ba4903f9
FF
1782 tasklet_disable(&sc->bcon_tasklet);
1783
1784 bf = avp->av_bcbuf;
1785 if (!bf || !bf->bf_mpdu)
1786 goto skip;
1787
1788 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
1789 if (status == -EINPROGRESS)
1790 goto skip;
1791
1792 sc->beacon.tx_processed = true;
1793 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
1794
1795skip:
1796 tasklet_enable(&sc->bcon_tasklet);
1797 }
1798
1799 return sc->beacon.tx_last;
1800}
1801
52c94f41
MSS
1802static int ath9k_get_stats(struct ieee80211_hw *hw,
1803 struct ieee80211_low_level_stats *stats)
1804{
1805 struct ath_softc *sc = hw->priv;
1806 struct ath_hw *ah = sc->sc_ah;
1807 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
1808
1809 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
1810 stats->dot11RTSFailureCount = mib_stats->rts_bad;
1811 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
1812 stats->dot11RTSSuccessCount = mib_stats->rts_good;
1813 return 0;
1814}
1815
43c35284
FF
1816static u32 fill_chainmask(u32 cap, u32 new)
1817{
1818 u32 filled = 0;
1819 int i;
1820
1821 for (i = 0; cap && new; i++, cap >>= 1) {
1822 if (!(cap & BIT(0)))
1823 continue;
1824
1825 if (new & BIT(0))
1826 filled |= BIT(i);
1827
1828 new >>= 1;
1829 }
1830
1831 return filled;
1832}
1833
5d9c7e3c
FF
1834static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
1835{
1836 switch (val & 0x7) {
1837 case 0x1:
1838 case 0x3:
1839 case 0x7:
1840 return true;
1841 case 0x2:
1842 return (ah->caps.rx_chainmask == 1);
1843 default:
1844 return false;
1845 }
1846}
1847
43c35284
FF
1848static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
1849{
1850 struct ath_softc *sc = hw->priv;
1851 struct ath_hw *ah = sc->sc_ah;
1852
5d9c7e3c
FF
1853 if (ah->caps.rx_chainmask != 1)
1854 rx_ant |= tx_ant;
1855
1856 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
43c35284
FF
1857 return -EINVAL;
1858
1859 sc->ant_rx = rx_ant;
1860 sc->ant_tx = tx_ant;
1861
1862 if (ah->caps.rx_chainmask == 1)
1863 return 0;
1864
1865 /* AR9100 runs into calibration issues if not all rx chains are enabled */
1866 if (AR_SREV_9100(ah))
1867 ah->rxchainmask = 0x7;
1868 else
1869 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
1870
1871 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
1872 ath9k_reload_chainmask_settings(sc);
1873
1874 return 0;
1875}
1876
1877static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
1878{
1879 struct ath_softc *sc = hw->priv;
1880
1881 *tx_ant = sc->ant_tx;
1882 *rx_ant = sc->ant_rx;
1883 return 0;
1884}
1885
b11e640a
MSS
1886#ifdef CONFIG_PM_SLEEP
1887
1888static void ath9k_wow_map_triggers(struct ath_softc *sc,
1889 struct cfg80211_wowlan *wowlan,
1890 u32 *wow_triggers)
1891{
1892 if (wowlan->disconnect)
1893 *wow_triggers |= AH_WOW_LINK_CHANGE |
1894 AH_WOW_BEACON_MISS;
1895 if (wowlan->magic_pkt)
1896 *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
1897
1898 if (wowlan->n_patterns)
1899 *wow_triggers |= AH_WOW_USER_PATTERN_EN;
1900
1901 sc->wow_enabled = *wow_triggers;
1902
1903}
1904
1905static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
1906{
1907 struct ath_hw *ah = sc->sc_ah;
1908 struct ath_common *common = ath9k_hw_common(ah);
1909 struct ath9k_hw_capabilities *pcaps = &ah->caps;
1910 int pattern_count = 0;
1911 int i, byte_cnt;
1912 u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
1913 u8 dis_deauth_mask[MAX_PATTERN_SIZE];
1914
1915 memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
1916 memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
1917
1918 /*
1919 * Create Dissassociate / Deauthenticate packet filter
1920 *
1921 * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
1922 * +--------------+----------+---------+--------+--------+----
1923 * + Frame Control+ Duration + DA + SA + BSSID +
1924 * +--------------+----------+---------+--------+--------+----
1925 *
1926 * The above is the management frame format for disassociate/
1927 * deauthenticate pattern, from this we need to match the first byte
1928 * of 'Frame Control' and DA, SA, and BSSID fields
1929 * (skipping 2nd byte of FC and Duration feild.
1930 *
1931 * Disassociate pattern
1932 * --------------------
1933 * Frame control = 00 00 1010
1934 * DA, SA, BSSID = x:x:x:x:x:x
1935 * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
1936 * | x:x:x:x:x:x -- 22 bytes
1937 *
1938 * Deauthenticate pattern
1939 * ----------------------
1940 * Frame control = 00 00 1100
1941 * DA, SA, BSSID = x:x:x:x:x:x
1942 * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
1943 * | x:x:x:x:x:x -- 22 bytes
1944 */
1945
1946 /* Create Disassociate Pattern first */
1947
1948 byte_cnt = 0;
1949
1950 /* Fill out the mask with all FF's */
1951
1952 for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
1953 dis_deauth_mask[i] = 0xff;
1954
1955 /* copy the first byte of frame control field */
1956 dis_deauth_pattern[byte_cnt] = 0xa0;
1957 byte_cnt++;
1958
1959 /* skip 2nd byte of frame control and Duration field */
1960 byte_cnt += 3;
1961
1962 /*
1963 * need not match the destination mac address, it can be a broadcast
1964 * mac address or an unicast to this station
1965 */
1966 byte_cnt += 6;
1967
1968 /* copy the source mac address */
1969 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
1970
1971 byte_cnt += 6;
1972
1973 /* copy the bssid, its same as the source mac address */
1974
1975 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
1976
1977 /* Create Disassociate pattern mask */
1978
1979 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
1980
1981 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
1982 /*
1983 * for AR9280, because of hardware limitation, the
1984 * first 4 bytes have to be matched for all patterns.
1985 * the mask for disassociation and de-auth pattern
1986 * matching need to enable the first 4 bytes.
1987 * also the duration field needs to be filled.
1988 */
1989 dis_deauth_mask[0] = 0xf0;
1990
1991 /*
1992 * fill in duration field
1993 FIXME: what is the exact value ?
1994 */
1995 dis_deauth_pattern[2] = 0xff;
1996 dis_deauth_pattern[3] = 0xff;
1997 } else {
1998 dis_deauth_mask[0] = 0xfe;
1999 }
2000
2001 dis_deauth_mask[1] = 0x03;
2002 dis_deauth_mask[2] = 0xc0;
2003 } else {
2004 dis_deauth_mask[0] = 0xef;
2005 dis_deauth_mask[1] = 0x3f;
2006 dis_deauth_mask[2] = 0x00;
2007 dis_deauth_mask[3] = 0xfc;
2008 }
2009
2010 ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
2011
2012 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2013 pattern_count, byte_cnt);
2014
2015 pattern_count++;
2016 /*
2017 * for de-authenticate pattern, only the first byte of the frame
2018 * control field gets changed from 0xA0 to 0xC0
2019 */
2020 dis_deauth_pattern[0] = 0xC0;
2021
2022 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2023 pattern_count, byte_cnt);
2024
2025}
2026
2027static void ath9k_wow_add_pattern(struct ath_softc *sc,
2028 struct cfg80211_wowlan *wowlan)
2029{
2030 struct ath_hw *ah = sc->sc_ah;
2031 struct ath9k_wow_pattern *wow_pattern = NULL;
2032 struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
2033 int mask_len;
2034 s8 i = 0;
2035
2036 if (!wowlan->n_patterns)
2037 return;
2038
2039 /*
2040 * Add the new user configured patterns
2041 */
2042 for (i = 0; i < wowlan->n_patterns; i++) {
2043
2044 wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
2045
2046 if (!wow_pattern)
2047 return;
2048
2049 /*
2050 * TODO: convert the generic user space pattern to
2051 * appropriate chip specific/802.11 pattern.
2052 */
2053
2054 mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
2055 memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
2056 memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
2057 memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
2058 patterns[i].pattern_len);
2059 memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
2060 wow_pattern->pattern_len = patterns[i].pattern_len;
2061
2062 /*
2063 * just need to take care of deauth and disssoc pattern,
2064 * make sure we don't overwrite them.
2065 */
2066
2067 ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
2068 wow_pattern->mask_bytes,
2069 i + 2,
2070 wow_pattern->pattern_len);
2071 kfree(wow_pattern);
2072
2073 }
2074
2075}
2076
2077static int ath9k_suspend(struct ieee80211_hw *hw,
2078 struct cfg80211_wowlan *wowlan)
2079{
2080 struct ath_softc *sc = hw->priv;
2081 struct ath_hw *ah = sc->sc_ah;
2082 struct ath_common *common = ath9k_hw_common(ah);
2083 u32 wow_triggers_enabled = 0;
2084 int ret = 0;
2085
2086 mutex_lock(&sc->mutex);
2087
2088 ath_cancel_work(sc);
5686cac5 2089 ath_stop_ani(sc);
b11e640a
MSS
2090 del_timer_sync(&sc->rx_poll_timer);
2091
2092 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
2093 ath_dbg(common, ANY, "Device not present\n");
2094 ret = -EINVAL;
2095 goto fail_wow;
2096 }
2097
2098 if (WARN_ON(!wowlan)) {
2099 ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
2100 ret = -EINVAL;
2101 goto fail_wow;
2102 }
2103
2104 if (!device_can_wakeup(sc->dev)) {
2105 ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
2106 ret = 1;
2107 goto fail_wow;
2108 }
2109
2110 /*
2111 * none of the sta vifs are associated
2112 * and we are not currently handling multivif
2113 * cases, for instance we have to seperately
2114 * configure 'keep alive frame' for each
2115 * STA.
2116 */
2117
2118 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
2119 ath_dbg(common, WOW, "None of the STA vifs are associated\n");
2120 ret = 1;
2121 goto fail_wow;
2122 }
2123
2124 if (sc->nvifs > 1) {
2125 ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
2126 ret = 1;
2127 goto fail_wow;
2128 }
2129
2130 ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
2131
2132 ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
2133 wow_triggers_enabled);
2134
2135 ath9k_ps_wakeup(sc);
2136
2137 ath9k_stop_btcoex(sc);
2138
2139 /*
2140 * Enable wake up on recieving disassoc/deauth
2141 * frame by default.
2142 */
2143 ath9k_wow_add_disassoc_deauth_pattern(sc);
2144
2145 if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
2146 ath9k_wow_add_pattern(sc, wowlan);
2147
2148 spin_lock_bh(&sc->sc_pcu_lock);
2149 /*
2150 * To avoid false wake, we enable beacon miss interrupt only
2151 * when we go to sleep. We save the current interrupt mask
2152 * so we can restore it after the system wakes up
2153 */
2154 sc->wow_intr_before_sleep = ah->imask;
2155 ah->imask &= ~ATH9K_INT_GLOBAL;
2156 ath9k_hw_disable_interrupts(ah);
2157 ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
2158 ath9k_hw_set_interrupts(ah);
2159 ath9k_hw_enable_interrupts(ah);
2160
2161 spin_unlock_bh(&sc->sc_pcu_lock);
2162
2163 /*
2164 * we can now sync irq and kill any running tasklets, since we already
2165 * disabled interrupts and not holding a spin lock
2166 */
2167 synchronize_irq(sc->irq);
2168 tasklet_kill(&sc->intr_tq);
2169
2170 ath9k_hw_wow_enable(ah, wow_triggers_enabled);
2171
2172 ath9k_ps_restore(sc);
2173 ath_dbg(common, ANY, "WoW enabled in ath9k\n");
2174 atomic_inc(&sc->wow_sleep_proc_intr);
2175
2176fail_wow:
2177 mutex_unlock(&sc->mutex);
2178 return ret;
2179}
2180
2181static int ath9k_resume(struct ieee80211_hw *hw)
2182{
2183 struct ath_softc *sc = hw->priv;
2184 struct ath_hw *ah = sc->sc_ah;
2185 struct ath_common *common = ath9k_hw_common(ah);
2186 u32 wow_status;
2187
2188 mutex_lock(&sc->mutex);
2189
2190 ath9k_ps_wakeup(sc);
2191
2192 spin_lock_bh(&sc->sc_pcu_lock);
2193
2194 ath9k_hw_disable_interrupts(ah);
2195 ah->imask = sc->wow_intr_before_sleep;
2196 ath9k_hw_set_interrupts(ah);
2197 ath9k_hw_enable_interrupts(ah);
2198
2199 spin_unlock_bh(&sc->sc_pcu_lock);
2200
2201 wow_status = ath9k_hw_wow_wakeup(ah);
2202
2203 if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
2204 /*
2205 * some devices may not pick beacon miss
2206 * as the reason they woke up so we add
2207 * that here for that shortcoming.
2208 */
2209 wow_status |= AH_WOW_BEACON_MISS;
2210 atomic_dec(&sc->wow_got_bmiss_intr);
2211 ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
2212 }
2213
2214 atomic_dec(&sc->wow_sleep_proc_intr);
2215
2216 if (wow_status) {
2217 ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
2218 ath9k_hw_wow_event_to_string(wow_status), wow_status);
2219 }
2220
2221 ath_restart_work(sc);
2222 ath9k_start_btcoex(sc);
2223
2224 ath9k_ps_restore(sc);
2225 mutex_unlock(&sc->mutex);
2226
2227 return 0;
2228}
2229
2230static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
2231{
2232 struct ath_softc *sc = hw->priv;
2233
2234 mutex_lock(&sc->mutex);
2235 device_init_wakeup(sc->dev, 1);
2236 device_set_wakeup_enable(sc->dev, enabled);
2237 mutex_unlock(&sc->mutex);
2238}
2239
2240#endif
2241
6baff7f9 2242struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2243 .tx = ath9k_tx,
2244 .start = ath9k_start,
2245 .stop = ath9k_stop,
2246 .add_interface = ath9k_add_interface,
6b3b991d 2247 .change_interface = ath9k_change_interface,
8feceb67
VT
2248 .remove_interface = ath9k_remove_interface,
2249 .config = ath9k_config,
8feceb67 2250 .configure_filter = ath9k_configure_filter,
4ca77860
JB
2251 .sta_add = ath9k_sta_add,
2252 .sta_remove = ath9k_sta_remove,
5519541d 2253 .sta_notify = ath9k_sta_notify,
8feceb67 2254 .conf_tx = ath9k_conf_tx,
8feceb67 2255 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2256 .set_key = ath9k_set_key,
8feceb67 2257 .get_tsf = ath9k_get_tsf,
3b5d665b 2258 .set_tsf = ath9k_set_tsf,
8feceb67 2259 .reset_tsf = ath9k_reset_tsf,
4233df6b 2260 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2261 .get_survey = ath9k_get_survey,
3b319aae 2262 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2263 .set_coverage_class = ath9k_set_coverage_class,
69081624 2264 .flush = ath9k_flush,
15b91e83 2265 .tx_frames_pending = ath9k_tx_frames_pending,
52c94f41
MSS
2266 .tx_last_beacon = ath9k_tx_last_beacon,
2267 .get_stats = ath9k_get_stats,
43c35284
FF
2268 .set_antenna = ath9k_set_antenna,
2269 .get_antenna = ath9k_get_antenna,
b90bd9d1 2270
b11e640a
MSS
2271#ifdef CONFIG_PM_SLEEP
2272 .suspend = ath9k_suspend,
2273 .resume = ath9k_resume,
2274 .set_wakeup = ath9k_set_wakeup,
2275#endif
2276
b90bd9d1
BG
2277#ifdef CONFIG_ATH9K_DEBUGFS
2278 .get_et_sset_count = ath9k_get_et_sset_count,
a145daf7
SM
2279 .get_et_stats = ath9k_get_et_stats,
2280 .get_et_strings = ath9k_get_et_strings,
2281#endif
2282
2283#if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS)
2284 .sta_add_debugfs = ath9k_sta_add_debugfs,
2285 .sta_remove_debugfs = ath9k_sta_remove_debugfs,
b90bd9d1 2286#endif
8feceb67 2287};
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