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ath9k_hw: move ath_extend_tsf() to hw code to share as ath9k_hw_extend_tsf()
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
af03abec 19#include "btcoex.h"
f078f209 20
f078f209
LR		 21static char *dev_info = "ath9k";
22
23MODULE_AUTHOR("Atheros Communications");
24MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26MODULE_LICENSE("Dual BSD/GPL");
27
b3bd89ce
JM		 28static int modparam_nohwcrypt;
29module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
30MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
31
faa27fae
LR		 32static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
33module_param_named(debug, ath9k_debug, uint, 0);
af1fc67c 34MODULE_PARM_DESC(debug, "Debugging mask");
faa27fae 35
5f8e077c
LR		 36/* We use the hw_value as an index into our private channel structure */
37
38#define CHAN2G(_freq, _idx) { \
39 .center_freq = (_freq), \
40 .hw_value = (_idx), \
eeddfd9d 41 .max_power = 20, \
5f8e077c
LR		 42}
43
44#define CHAN5G(_freq, _idx) { \
45 .band = IEEE80211_BAND_5GHZ, \
46 .center_freq = (_freq), \
47 .hw_value = (_idx), \
eeddfd9d 48 .max_power = 20, \
5f8e077c
LR		 49}
50
51/* Some 2 GHz radios are actually tunable on 2312-2732
52 * on 5 MHz steps, we support the channels which we know
53 * we have calibration data for all cards though to make
54 * this static */
55static struct ieee80211_channel ath9k_2ghz_chantable[] = {
56 CHAN2G(2412, 0), /* Channel 1 */
57 CHAN2G(2417, 1), /* Channel 2 */
58 CHAN2G(2422, 2), /* Channel 3 */
59 CHAN2G(2427, 3), /* Channel 4 */
60 CHAN2G(2432, 4), /* Channel 5 */
61 CHAN2G(2437, 5), /* Channel 6 */
62 CHAN2G(2442, 6), /* Channel 7 */
63 CHAN2G(2447, 7), /* Channel 8 */
64 CHAN2G(2452, 8), /* Channel 9 */
65 CHAN2G(2457, 9), /* Channel 10 */
66 CHAN2G(2462, 10), /* Channel 11 */
67 CHAN2G(2467, 11), /* Channel 12 */
68 CHAN2G(2472, 12), /* Channel 13 */
69 CHAN2G(2484, 13), /* Channel 14 */
70};
71
72/* Some 5 GHz radios are actually tunable on XXXX-YYYY
73 * on 5 MHz steps, we support the channels which we know
74 * we have calibration data for all cards though to make
75 * this static */
76static struct ieee80211_channel ath9k_5ghz_chantable[] = {
77 /* _We_ call this UNII 1 */
78 CHAN5G(5180, 14), /* Channel 36 */
79 CHAN5G(5200, 15), /* Channel 40 */
80 CHAN5G(5220, 16), /* Channel 44 */
81 CHAN5G(5240, 17), /* Channel 48 */
82 /* _We_ call this UNII 2 */
83 CHAN5G(5260, 18), /* Channel 52 */
84 CHAN5G(5280, 19), /* Channel 56 */
85 CHAN5G(5300, 20), /* Channel 60 */
86 CHAN5G(5320, 21), /* Channel 64 */
87 /* _We_ call this "Middle band" */
88 CHAN5G(5500, 22), /* Channel 100 */
89 CHAN5G(5520, 23), /* Channel 104 */
90 CHAN5G(5540, 24), /* Channel 108 */
91 CHAN5G(5560, 25), /* Channel 112 */
92 CHAN5G(5580, 26), /* Channel 116 */
93 CHAN5G(5600, 27), /* Channel 120 */
94 CHAN5G(5620, 28), /* Channel 124 */
95 CHAN5G(5640, 29), /* Channel 128 */
96 CHAN5G(5660, 30), /* Channel 132 */
97 CHAN5G(5680, 31), /* Channel 136 */
98 CHAN5G(5700, 32), /* Channel 140 */
99 /* _We_ call this UNII 3 */
100 CHAN5G(5745, 33), /* Channel 149 */
101 CHAN5G(5765, 34), /* Channel 153 */
102 CHAN5G(5785, 35), /* Channel 157 */
103 CHAN5G(5805, 36), /* Channel 161 */
104 CHAN5G(5825, 37), /* Channel 165 */
105};
106
ce111bad
LR		 107static void ath_cache_conf_rate(struct ath_softc *sc,
108 struct ieee80211_conf *conf)
ff37e337 109{
030bb495
LR		 110 switch (conf->channel->band) {
111 case IEEE80211_BAND_2GHZ:
112 if (conf_is_ht20(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
115 else if (conf_is_ht40_minus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
118 else if (conf_is_ht40_plus(conf))
119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 121 else
030bb495
LR		 122 sc->cur_rate_table =
123 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 124 break;
125 case IEEE80211_BAND_5GHZ:
126 if (conf_is_ht20(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
129 else if (conf_is_ht40_minus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
132 else if (conf_is_ht40_plus(conf))
133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
135 else
96742256
LR		 136 sc->cur_rate_table =
137 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 138 break;
139 default:
ce111bad 140 BUG_ON(1);
030bb495
LR		 141 break;
142 }
ff37e337
S		 143}
144
145static void ath_update_txpow(struct ath_softc *sc)
146{
cbe61d8a 147 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 148 u32 txpow;
149
17d7904d
S		 150 if (sc->curtxpow != sc->config.txpowlimit) {
151 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 152 /* read back in case value is clamped */
153 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 154 sc->curtxpow = txpow;
ff37e337
S		 155 }
156}
157
158static u8 parse_mpdudensity(u8 mpdudensity)
159{
160 /*
161 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
162 * 0 for no restriction
163 * 1 for 1/4 us
164 * 2 for 1/2 us
165 * 3 for 1 us
166 * 4 for 2 us
167 * 5 for 4 us
168 * 6 for 8 us
169 * 7 for 16 us
170 */
171 switch (mpdudensity) {
172 case 0:
173 return 0;
174 case 1:
175 case 2:
176 case 3:
177 /* Our lower layer calculations limit our precision to
178 1 microsecond */
179 return 1;
180 case 4:
181 return 2;
182 case 5:
183 return 4;
184 case 6:
185 return 8;
186 case 7:
187 return 16;
188 default:
189 return 0;
190 }
191}
192
193static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
194{
4f0fc7c3 195 const struct ath_rate_table *rate_table = NULL;
ff37e337
S		 196 struct ieee80211_supported_band *sband;
197 struct ieee80211_rate *rate;
198 int i, maxrates;
199
200 switch (band) {
201 case IEEE80211_BAND_2GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
203 break;
204 case IEEE80211_BAND_5GHZ:
205 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
206 break;
207 default:
208 break;
209 }
210
211 if (rate_table == NULL)
212 return;
213
214 sband = &sc->sbands[band];
215 rate = sc->rates[band];
216
217 if (rate_table->rate_cnt > ATH_RATE_MAX)
218 maxrates = ATH_RATE_MAX;
219 else
220 maxrates = rate_table->rate_cnt;
221
222 for (i = 0; i < maxrates; i++) {
223 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
224 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 225 if (rate_table->info[i].short_preamble) {
226 rate[i].hw_value_short = rate_table->info[i].ratecode |
227 rate_table->info[i].short_preamble;
228 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
229 }
ff37e337 230 sband->n_bitrates++;
f46730d1 231
c46917bb
LR		 232 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
233 "Rate: %2dMbps, ratecode: %2d\n",
234 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 235 }
236}
237
82880a7c
VT		 238static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
239 struct ieee80211_hw *hw)
240{
241 struct ieee80211_channel *curchan = hw->conf.channel;
242 struct ath9k_channel *channel;
243 u8 chan_idx;
244
245 chan_idx = curchan->hw_value;
246 channel = &sc->sc_ah->channels[chan_idx];
247 ath9k_update_ichannel(sc, hw, channel);
248 return channel;
249}
250
9ecdef4b 251static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR		 252{
253 unsigned long flags;
254 bool ret;
255
9ecdef4b
LR		 256 spin_lock_irqsave(&sc->sc_pm_lock, flags);
257 ret = ath9k_hw_setpower(sc->sc_ah, mode);
258 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR		 259
260 return ret;
261}
262
a91d75ae
LR		 263void ath9k_ps_wakeup(struct ath_softc *sc)
264{
265 unsigned long flags;
266
267 spin_lock_irqsave(&sc->sc_pm_lock, flags);
268 if (++sc->ps_usecount != 1)
269 goto unlock;
270
9ecdef4b 271 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae
LR		 272
273 unlock:
274 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
275}
276
277void ath9k_ps_restore(struct ath_softc *sc)
278{
279 unsigned long flags;
280
281 spin_lock_irqsave(&sc->sc_pm_lock, flags);
282 if (--sc->ps_usecount != 0)
283 goto unlock;
284
285 if (sc->ps_enabled &&
286 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
287 SC_OP_WAIT_FOR_CAB |
288 SC_OP_WAIT_FOR_PSPOLL_DATA |
289 SC_OP_WAIT_FOR_TX_ACK)))
9ecdef4b 290 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR		 291
292 unlock:
293 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
294}
295
ff37e337
S		 296/*
297 * Set/change channels. If the channel is really being changed, it's done
298 * by reseting the chip. To accomplish this we must first cleanup any pending
299 * DMA, then restart stuff.
300*/
0e2dedf9
JM		 301int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
302 struct ath9k_channel *hchan)
ff37e337 303{
cbe61d8a 304 struct ath_hw *ah = sc->sc_ah;
c46917bb 305 struct ath_common *common = ath9k_hw_common(ah);
25c56eec 306 struct ieee80211_conf *conf = &common->hw->conf;
ff37e337 307 bool fastcc = true, stopped;
ae8d2858
LR		 308 struct ieee80211_channel *channel = hw->conf.channel;
309 int r;
ff37e337
S		 310
311 if (sc->sc_flags & SC_OP_INVALID)
312 return -EIO;
313
3cbb5dd7
VN		 314 ath9k_ps_wakeup(sc);
315
c0d7c7af
LR		 316 /*
317 * This is only performed if the channel settings have
318 * actually changed.
319 *
320 * To switch channels clear any pending DMA operations;
321 * wait long enough for the RX fifo to drain, reset the
322 * hardware at the new frequency, and then re-enable
323 * the relevant bits of the h/w.
324 */
325 ath9k_hw_set_interrupts(ah, 0);
043a0405 326 ath_drain_all_txq(sc, false);
c0d7c7af 327 stopped = ath_stoprecv(sc);
ff37e337 328
c0d7c7af
LR		 329 /* XXX: do not flush receive queue here. We don't want
330 * to flush data frames already in queue because of
331 * changing channel. */
ff37e337 332
c0d7c7af
LR		 333 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
334 fastcc = false;
335
c46917bb 336 ath_print(common, ATH_DBG_CONFIG,
25c56eec 337 "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
c46917bb 338 sc->sc_ah->curchan->channel,
25c56eec 339 channel->center_freq, conf_is_ht40(conf));
ff37e337 340
c0d7c7af
LR		 341 spin_lock_bh(&sc->sc_resetlock);
342
343 r = ath9k_hw_reset(ah, hchan, fastcc);
344 if (r) {
c46917bb
LR		 345 ath_print(common, ATH_DBG_FATAL,
346 "Unable to reset channel (%u Mhz) "
347 "reset status %d\n",
348 channel->center_freq, r);
c0d7c7af 349 spin_unlock_bh(&sc->sc_resetlock);
3989279c 350 goto ps_restore;
ff37e337 351 }
c0d7c7af
LR		 352 spin_unlock_bh(&sc->sc_resetlock);
353
c0d7c7af
LR		 354 sc->sc_flags &= ~SC_OP_FULL_RESET;
355
356 if (ath_startrecv(sc) != 0) {
c46917bb
LR		 357 ath_print(common, ATH_DBG_FATAL,
358 "Unable to restart recv logic\n");
3989279c
GJ		 359 r = -EIO;
360 goto ps_restore;
c0d7c7af
LR		 361 }
362
363 ath_cache_conf_rate(sc, &hw->conf);
364 ath_update_txpow(sc);
17d7904d 365 ath9k_hw_set_interrupts(ah, sc->imask);
3989279c
GJ		 366
367 ps_restore:
3cbb5dd7 368 ath9k_ps_restore(sc);
3989279c 369 return r;
ff37e337
S		 370}
371
372/*
373 * This routine performs the periodic noise floor calibration function
374 * that is used to adjust and optimize the chip performance. This
375 * takes environmental changes (location, temperature) into account.
376 * When the task is complete, it reschedules itself depending on the
377 * appropriate interval that was calculated.
378 */
379static void ath_ani_calibrate(unsigned long data)
380{
20977d3e
S		 381 struct ath_softc *sc = (struct ath_softc *)data;
382 struct ath_hw *ah = sc->sc_ah;
c46917bb 383 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S		 384 bool longcal = false;
385 bool shortcal = false;
386 bool aniflag = false;
387 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 388 u32 cal_interval, short_cal_interval;
ff37e337 389
20977d3e
S		 390 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
391 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 392
393 /*
394 * don't calibrate when we're scanning.
395 * we are most likely not on our home channel.
396 */
e5f0921a 397 spin_lock(&sc->ani_lock);
0c98de65 398 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 399 goto set_timer;
ff37e337 400
1ffc1c61
JM		 401 /* Only calibrate if awake */
402 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
403 goto set_timer;
404
405 ath9k_ps_wakeup(sc);
406
ff37e337 407 /* Long calibration runs independently of short calibration. */
17d7904d 408 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 409 longcal = true;
c46917bb 410 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 411 sc->ani.longcal_timer = timestamp;
ff37e337
S		 412 }
413
17d7904d
S		 414 /* Short calibration applies only while caldone is false */
415 if (!sc->ani.caldone) {
20977d3e 416 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 417 shortcal = true;
c46917bb
LR		 418 ath_print(common, ATH_DBG_ANI,
419 "shortcal @%lu\n", jiffies);
17d7904d
S		 420 sc->ani.shortcal_timer = timestamp;
421 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 422 }
423 } else {
17d7904d 424 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 425 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 426 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
427 if (sc->ani.caldone)
428 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 429 }
430 }
431
432 /* Verify whether we must check ANI */
20977d3e 433 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 434 aniflag = true;
17d7904d 435 sc->ani.checkani_timer = timestamp;
ff37e337
S		 436 }
437
438 /* Skip all processing if there's nothing to do. */
439 if (longcal || shortcal || aniflag) {
440 /* Call ANI routine if necessary */
441 if (aniflag)
22e66a4c 442 ath9k_hw_ani_monitor(ah, ah->curchan);
ff37e337
S		 443
444 /* Perform calibration if necessary */
445 if (longcal || shortcal) {
43c27613
LR		 446 sc->ani.caldone =
447 ath9k_hw_calibrate(ah,
448 ah->curchan,
449 common->rx_chainmask,
450 longcal);
379f0440
S		 451
452 if (longcal)
453 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
454 ah->curchan);
455
c46917bb
LR		 456 ath_print(common, ATH_DBG_ANI,
457 " calibrate chan %u/%x nf: %d\n",
458 ah->curchan->channel,
459 ah->curchan->channelFlags,
460 sc->ani.noise_floor);
ff37e337
S		 461 }
462 }
463
1ffc1c61
JM		 464 ath9k_ps_restore(sc);
465
20977d3e 466set_timer:
e5f0921a 467 spin_unlock(&sc->ani_lock);
ff37e337
S		 468 /*
469 * Set timer interval based on previous results.
470 * The interval must be the shortest necessary to satisfy ANI,
471 * short calibration and long calibration.
472 */
aac9207e 473 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 474 if (sc->sc_ah->config.enable_ani)
aac9207e 475 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 476 if (!sc->ani.caldone)
20977d3e 477 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 478
17d7904d 479 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 480}
481
415f738e
S		 482static void ath_start_ani(struct ath_softc *sc)
483{
484 unsigned long timestamp = jiffies_to_msecs(jiffies);
485
486 sc->ani.longcal_timer = timestamp;
487 sc->ani.shortcal_timer = timestamp;
488 sc->ani.checkani_timer = timestamp;
489
490 mod_timer(&sc->ani.timer,
491 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
492}
493
ff37e337
S		 494/*
495 * Update tx/rx chainmask. For legacy association,
496 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 497 * the chainmask configuration, for bt coexistence, use
498 * the chainmask configuration even in legacy mode.
ff37e337 499 */
0e2dedf9 500void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 501{
af03abec 502 struct ath_hw *ah = sc->sc_ah;
43c27613 503 struct ath_common *common = ath9k_hw_common(ah);
af03abec 504
3d832611 505 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
766ec4a9 506 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
43c27613
LR		 507 common->tx_chainmask = ah->caps.tx_chainmask;
508 common->rx_chainmask = ah->caps.rx_chainmask;
ff37e337 509 } else {
43c27613
LR		 510 common->tx_chainmask = 1;
511 common->rx_chainmask = 1;
ff37e337
S		 512 }
513
43c27613 514 ath_print(common, ATH_DBG_CONFIG,
c46917bb 515 "tx chmask: %d, rx chmask: %d\n",
43c27613
LR		 516 common->tx_chainmask,
517 common->rx_chainmask);
ff37e337
S		 518}
519
520static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
521{
522 struct ath_node *an;
523
524 an = (struct ath_node *)sta->drv_priv;
525
87792efc 526 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 527 ath_tx_node_init(sc, an);
9e98ac65 528 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S		 529 sta->ht_cap.ampdu_factor);
530 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
a59b5a5e 531 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
87792efc 532 }
ff37e337
S		 533}
534
535static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
536{
537 struct ath_node *an = (struct ath_node *)sta->drv_priv;
538
539 if (sc->sc_flags & SC_OP_TXAGGR)
540 ath_tx_node_cleanup(sc, an);
541}
542
543static void ath9k_tasklet(unsigned long data)
544{
545 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 546 struct ath_hw *ah = sc->sc_ah;
c46917bb 547 struct ath_common *common = ath9k_hw_common(ah);
af03abec 548
17d7904d 549 u32 status = sc->intrstatus;
ff37e337 550
153e080d
VT		 551 ath9k_ps_wakeup(sc);
552
ff37e337 553 if (status & ATH9K_INT_FATAL) {
ff37e337 554 ath_reset(sc, false);
153e080d 555 ath9k_ps_restore(sc);
ff37e337 556 return;
063d8be3 557 }
ff37e337 558
063d8be3
S		 559 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
560 spin_lock_bh(&sc->rx.rxflushlock);
561 ath_rx_tasklet(sc, 0);
562 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 563 }
564
063d8be3
S		 565 if (status & ATH9K_INT_TX)
566 ath_tx_tasklet(sc);
567
96148326 568 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM		 569 /*
570 * TSF sync does not look correct; remain awake to sync with
571 * the next Beacon.
572 */
c46917bb
LR		 573 ath_print(common, ATH_DBG_PS,
574 "TSFOOR - Sync with next Beacon\n");
ccdfeab6 575 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
54ce846e
JM		 576 }
577
766ec4a9 578 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT		 579 if (status & ATH9K_INT_GENTIMER)
580 ath_gen_timer_isr(sc->sc_ah);
581
ff37e337 582 /* re-enable hardware interrupt */
af03abec 583 ath9k_hw_set_interrupts(ah, sc->imask);
153e080d 584 ath9k_ps_restore(sc);
ff37e337
S		 585}
586
6baff7f9 587irqreturn_t ath_isr(int irq, void *dev)
ff37e337 588{
063d8be3
S		 589#define SCHED_INTR ( \
590 ATH9K_INT_FATAL | \
591 ATH9K_INT_RXORN | \
592 ATH9K_INT_RXEOL | \
593 ATH9K_INT_RX | \
594 ATH9K_INT_TX | \
595 ATH9K_INT_BMISS | \
596 ATH9K_INT_CST | \
ebb8e1d7
VT		 597 ATH9K_INT_TSFOOR | \
598 ATH9K_INT_GENTIMER)
063d8be3 599
ff37e337 600 struct ath_softc *sc = dev;
cbe61d8a 601 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 602 enum ath9k_int status;
603 bool sched = false;
604
063d8be3
S		 605 /*
606 * The hardware is not ready/present, don't
607 * touch anything. Note this can happen early
608 * on if the IRQ is shared.
609 */
610 if (sc->sc_flags & SC_OP_INVALID)
611 return IRQ_NONE;
ff37e337 612
063d8be3
S		 613
614 /* shared irq, not for us */
615
153e080d 616 if (!ath9k_hw_intrpend(ah))
063d8be3 617 return IRQ_NONE;
063d8be3
S		 618
619 /*
620 * Figure out the reason(s) for the interrupt. Note
621 * that the hal returns a pseudo-ISR that may include
622 * bits we haven't explicitly enabled so we mask the
623 * value to insure we only process bits we requested.
624 */
625 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
626 status &= sc->imask; /* discard unasked-for bits */
ff37e337 627
063d8be3
S		 628 /*
629 * If there are no status bits set, then this interrupt was not
630 * for me (should have been caught above).
631 */
153e080d 632 if (!status)
063d8be3 633 return IRQ_NONE;
ff37e337 634
063d8be3
S		 635 /* Cache the status */
636 sc->intrstatus = status;
637
638 if (status & SCHED_INTR)
639 sched = true;
640
641 /*
642 * If a FATAL or RXORN interrupt is received, we have to reset the
643 * chip immediately.
644 */
645 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
646 goto chip_reset;
647
648 if (status & ATH9K_INT_SWBA)
649 tasklet_schedule(&sc->bcon_tasklet);
650
651 if (status & ATH9K_INT_TXURN)
652 ath9k_hw_updatetxtriglevel(ah, true);
653
654 if (status & ATH9K_INT_MIB) {
ff37e337 655 /*
063d8be3
S		 656 * Disable interrupts until we service the MIB
657 * interrupt; otherwise it will continue to
658 * fire.
ff37e337 659 */
063d8be3
S		 660 ath9k_hw_set_interrupts(ah, 0);
661 /*
662 * Let the hal handle the event. We assume
663 * it will clear whatever condition caused
664 * the interrupt.
665 */
22e66a4c 666 ath9k_hw_procmibevent(ah);
063d8be3
S		 667 ath9k_hw_set_interrupts(ah, sc->imask);
668 }
ff37e337 669
153e080d
VT		 670 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
671 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S		 672 /* Clear RxAbort bit so that we can
673 * receive frames */
9ecdef4b 674 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 675 ath9k_hw_setrxabort(sc->sc_ah, 0);
063d8be3 676 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 677 }
063d8be3
S		 678
679chip_reset:
ff37e337 680
817e11de
S		 681 ath_debug_stat_interrupt(sc, status);
682
ff37e337
S		 683 if (sched) {
684 /* turn off every interrupt except SWBA */
17d7904d 685 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 686 tasklet_schedule(&sc->intr_tq);
687 }
688
689 return IRQ_HANDLED;
063d8be3
S		 690
691#undef SCHED_INTR
ff37e337
S		 692}
693
f078f209 694static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 695 struct ieee80211_channel *chan,
094d05dc 696 enum nl80211_channel_type channel_type)
f078f209
LR		 697{
698 u32 chanmode = 0;
f078f209
LR		 699
700 switch (chan->band) {
701 case IEEE80211_BAND_2GHZ:
094d05dc
S		 702 switch(channel_type) {
703 case NL80211_CHAN_NO_HT:
704 case NL80211_CHAN_HT20:
f078f209 705 chanmode = CHANNEL_G_HT20;
094d05dc
S		 706 break;
707 case NL80211_CHAN_HT40PLUS:
f078f209 708 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 709 break;
710 case NL80211_CHAN_HT40MINUS:
f078f209 711 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 712 break;
713 }
f078f209
LR		 714 break;
715 case IEEE80211_BAND_5GHZ:
094d05dc
S		 716 switch(channel_type) {
717 case NL80211_CHAN_NO_HT:
718 case NL80211_CHAN_HT20:
f078f209 719 chanmode = CHANNEL_A_HT20;
094d05dc
S		 720 break;
721 case NL80211_CHAN_HT40PLUS:
f078f209 722 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 723 break;
724 case NL80211_CHAN_HT40MINUS:
f078f209 725 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 726 break;
727 }
f078f209
LR		 728 break;
729 default:
730 break;
731 }
732
733 return chanmode;
734}
735
6ace2891 736static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 737 struct ath9k_keyval *hk, const u8 *addr,
738 bool authenticator)
f078f209 739{
6ace2891
JM		 740 const u8 *key_rxmic;
741 const u8 *key_txmic;
f078f209 742
6ace2891
JM		 743 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
744 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 745
746 if (addr == NULL) {
d216aaa6
JM		 747 /*
748 * Group key installation - only two key cache entries are used
749 * regardless of splitmic capability since group key is only
750 * used either for TX or RX.
751 */
3f53dd64
JM		 752 if (authenticator) {
753 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
754 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
755 } else {
756 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
757 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
758 }
d216aaa6 759 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 760 }
17d7904d 761 if (!sc->splitmic) {
d216aaa6 762 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 763 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
764 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 765 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 766 }
d216aaa6
JM		 767
768 /* Separate key cache entries for TX and RX */
769
770 /* TX key goes at first index, RX key at +32. */
f078f209 771 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 772 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
773 /* TX MIC entry failed. No need to proceed further */
c46917bb
LR		 774 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
775 "Setting TX MIC Key Failed\n");
f078f209
LR		 776 return 0;
777 }
778
779 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
780 /* XXX delete tx key on failure? */
d216aaa6 781 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 782}
783
784static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
785{
786 int i;
787
17d7904d
S		 788 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
789 if (test_bit(i, sc->keymap) ||
790 test_bit(i + 64, sc->keymap))
6ace2891 791 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 792 if (sc->splitmic &&
793 (test_bit(i + 32, sc->keymap) ||
794 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 795 continue; /* At least one part of TKIP key allocated */
796
797 /* Found a free slot for a TKIP key */
798 return i;
799 }
800 return -1;
801}
802
803static int ath_reserve_key_cache_slot(struct ath_softc *sc)
804{
805 int i;
806
807 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 808 if (sc->splitmic) {
809 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
810 if (!test_bit(i, sc->keymap) &&
811 (test_bit(i + 32, sc->keymap) ||
812 test_bit(i + 64, sc->keymap) ||
813 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 814 return i;
17d7904d
S		 815 if (!test_bit(i + 32, sc->keymap) &&
816 (test_bit(i, sc->keymap) ||
817 test_bit(i + 64, sc->keymap) ||
818 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 819 return i + 32;
17d7904d
S		 820 if (!test_bit(i + 64, sc->keymap) &&
821 (test_bit(i , sc->keymap) ||
822 test_bit(i + 32, sc->keymap) ||
823 test_bit(i + 64 + 32, sc->keymap)))
ea612132 824 return i + 64;
17d7904d
S		 825 if (!test_bit(i + 64 + 32, sc->keymap) &&
826 (test_bit(i, sc->keymap) ||
827 test_bit(i + 32, sc->keymap) ||
828 test_bit(i + 64, sc->keymap)))
ea612132 829 return i + 64 + 32;
6ace2891
JM		 830 }
831 } else {
17d7904d
S		 832 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
833 if (!test_bit(i, sc->keymap) &&
834 test_bit(i + 64, sc->keymap))
6ace2891 835 return i;
17d7904d
S		 836 if (test_bit(i, sc->keymap) &&
837 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 838 return i + 64;
839 }
840 }
841
842 /* No partially used TKIP slots, pick any available slot */
17d7904d 843 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 844 /* Do not allow slots that could be needed for TKIP group keys
845 * to be used. This limitation could be removed if we know that
846 * TKIP will not be used. */
847 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
848 continue;
17d7904d 849 if (sc->splitmic) {
be2864cf
JM		 850 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
851 continue;
852 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
853 continue;
854 }
855
17d7904d 856 if (!test_bit(i, sc->keymap))
6ace2891
JM		 857 return i; /* Found a free slot for a key */
858 }
859
860 /* No free slot found */
861 return -1;
f078f209
LR		 862}
863
864static int ath_key_config(struct ath_softc *sc,
3f53dd64 865 struct ieee80211_vif *vif,
dc822b5d 866 struct ieee80211_sta *sta,
f078f209
LR		 867 struct ieee80211_key_conf *key)
868{
f078f209
LR		 869 struct ath9k_keyval hk;
870 const u8 *mac = NULL;
871 int ret = 0;
6ace2891 872 int idx;
f078f209
LR		 873
874 memset(&hk, 0, sizeof(hk));
875
876 switch (key->alg) {
877 case ALG_WEP:
878 hk.kv_type = ATH9K_CIPHER_WEP;
879 break;
880 case ALG_TKIP:
881 hk.kv_type = ATH9K_CIPHER_TKIP;
882 break;
883 case ALG_CCMP:
884 hk.kv_type = ATH9K_CIPHER_AES_CCM;
885 break;
886 default:
ca470b29 887 return -EOPNOTSUPP;
f078f209
LR		 888 }
889
6ace2891 890 hk.kv_len = key->keylen;
f078f209
LR		 891 memcpy(hk.kv_val, key->key, key->keylen);
892
6ace2891
JM		 893 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
894 /* For now, use the default keys for broadcast keys. This may
895 * need to change with virtual interfaces. */
896 idx = key->keyidx;
897 } else if (key->keyidx) {
dc822b5d
JB		 898 if (WARN_ON(!sta))
899 return -EOPNOTSUPP;
900 mac = sta->addr;
901
6ace2891
JM		 902 if (vif->type != NL80211_IFTYPE_AP) {
903 /* Only keyidx 0 should be used with unicast key, but
904 * allow this for client mode for now. */
905 idx = key->keyidx;
906 } else
907 return -EIO;
f078f209 908 } else {
dc822b5d
JB		 909 if (WARN_ON(!sta))
910 return -EOPNOTSUPP;
911 mac = sta->addr;
912
6ace2891
JM		 913 if (key->alg == ALG_TKIP)
914 idx = ath_reserve_key_cache_slot_tkip(sc);
915 else
916 idx = ath_reserve_key_cache_slot(sc);
917 if (idx < 0)
ca470b29 918 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 919 }
920
921 if (key->alg == ALG_TKIP)
3f53dd64
JM		 922 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
923 vif->type == NL80211_IFTYPE_AP);
f078f209 924 else
d216aaa6 925 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 926
927 if (!ret)
928 return -EIO;
929
17d7904d 930 set_bit(idx, sc->keymap);
6ace2891 931 if (key->alg == ALG_TKIP) {
17d7904d
S		 932 set_bit(idx + 64, sc->keymap);
933 if (sc->splitmic) {
934 set_bit(idx + 32, sc->keymap);
935 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 936 }
937 }
938
939 return idx;
f078f209
LR		 940}
941
942static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
943{
6ace2891
JM		 944 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
945 if (key->hw_key_idx < IEEE80211_WEP_NKID)
946 return;
947
17d7904d 948 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 949 if (key->alg != ALG_TKIP)
950 return;
f078f209 951
17d7904d
S		 952 clear_bit(key->hw_key_idx + 64, sc->keymap);
953 if (sc->splitmic) {
954 clear_bit(key->hw_key_idx + 32, sc->keymap);
955 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 956 }
f078f209
LR		 957}
958
eb2599ca
S		 959static void setup_ht_cap(struct ath_softc *sc,
960 struct ieee80211_sta_ht_cap *ht_info)
f078f209 961{
43c27613 962 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
140add21 963 u8 tx_streams, rx_streams;
f078f209 964
d9fe60de
JB		 965 ht_info->ht_supported = true;
966 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
967 IEEE80211_HT_CAP_SM_PS |
968 IEEE80211_HT_CAP_SGI_40 |
969 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 970
9e98ac65
S		 971 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
972 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
eb2599ca 973
d9fe60de
JB		 974 /* set up supported mcs set */
975 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
43c27613
LR		 976 tx_streams = !(common->tx_chainmask & (common->tx_chainmask - 1)) ?
977 1 : 2;
978 rx_streams = !(common->rx_chainmask & (common->rx_chainmask - 1)) ?
979 1 : 2;
140add21
SB		 980
981 if (tx_streams != rx_streams) {
43c27613 982 ath_print(common, ATH_DBG_CONFIG,
c46917bb
LR		 983 "TX streams %d, RX streams: %d\n",
984 tx_streams, rx_streams);
140add21
SB		 985 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
986 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
987 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
988 }
eb2599ca 989
140add21
SB		 990 ht_info->mcs.rx_mask[0] = 0xff;
991 if (rx_streams >= 2)
eb2599ca 992 ht_info->mcs.rx_mask[1] = 0xff;
eb2599ca 993
140add21 994 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 995}
996
8feceb67 997static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 998 struct ieee80211_vif *vif,
8feceb67 999 struct ieee80211_bss_conf *bss_conf)
f078f209 1000{
f2b2143e 1001 struct ath_hw *ah = sc->sc_ah;
1510718d 1002 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1003
8feceb67 1004 if (bss_conf->assoc) {
c46917bb
LR		 1005 ath_print(common, ATH_DBG_CONFIG,
1006 "Bss Info ASSOC %d, bssid: %pM\n",
1007 bss_conf->aid, common->curbssid);
f078f209 1008
8feceb67 1009 /* New association, store aid */
1510718d 1010 common->curaid = bss_conf->aid;
f2b2143e 1011 ath9k_hw_write_associd(ah);
2664f201
SB		 1012
1013 /*
1014 * Request a re-configuration of Beacon related timers
1015 * on the receipt of the first Beacon frame (i.e.,
1016 * after time sync with the AP).
1017 */
1018 sc->sc_flags |= SC_OP_BEACON_SYNC;
f078f209 1019
8feceb67 1020 /* Configure the beacon */
2c3db3d5 1021 ath_beacon_config(sc, vif);
f078f209 1022
8feceb67 1023 /* Reset rssi stats */
22e66a4c 1024 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 1025
415f738e 1026 ath_start_ani(sc);
8feceb67 1027 } else {
c46917bb 1028 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1510718d 1029 common->curaid = 0;
f38faa31
SB		 1030 /* Stop ANI */
1031 del_timer_sync(&sc->ani.timer);
f078f209 1032 }
8feceb67 1033}
f078f209 1034
8feceb67
VT		 1035/********************************/
1036/* LED functions */
1037/********************************/
f078f209 1038
f2bffa7e
VT		 1039static void ath_led_blink_work(struct work_struct *work)
1040{
1041 struct ath_softc *sc = container_of(work, struct ath_softc,
1042 ath_led_blink_work.work);
1043
1044 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
1045 return;
85067c06
VT		 1046
1047 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
1048 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
08fc5c1b 1049 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
85067c06 1050 else
08fc5c1b 1051 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
85067c06 1052 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e 1053
42935eca
LR		 1054 ieee80211_queue_delayed_work(sc->hw,
1055 &sc->ath_led_blink_work,
1056 (sc->sc_flags & SC_OP_LED_ON) ?
1057 msecs_to_jiffies(sc->led_off_duration) :
1058 msecs_to_jiffies(sc->led_on_duration));
f2bffa7e 1059
85067c06
VT		 1060 sc->led_on_duration = sc->led_on_cnt ?
1061 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
1062 ATH_LED_ON_DURATION_IDLE;
1063 sc->led_off_duration = sc->led_off_cnt ?
1064 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
1065 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 1066 sc->led_on_cnt = sc->led_off_cnt = 0;
1067 if (sc->sc_flags & SC_OP_LED_ON)
1068 sc->sc_flags &= ~SC_OP_LED_ON;
1069 else
1070 sc->sc_flags |= SC_OP_LED_ON;
1071}
1072
8feceb67
VT		 1073static void ath_led_brightness(struct led_classdev *led_cdev,
1074 enum led_brightness brightness)
1075{
1076 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1077 struct ath_softc *sc = led->sc;
f078f209 1078
8feceb67
VT		 1079 switch (brightness) {
1080 case LED_OFF:
1081 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e 1082 led->led_type == ATH_LED_RADIO) {
08fc5c1b 1083 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
f2bffa7e 1084 (led->led_type == ATH_LED_RADIO));
8feceb67 1085 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1086 if (led->led_type == ATH_LED_RADIO)
1087 sc->sc_flags &= ~SC_OP_LED_ON;
1088 } else {
1089 sc->led_off_cnt++;
1090 }
8feceb67
VT		 1091 break;
1092 case LED_FULL:
f2bffa7e 1093 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 1094 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
42935eca
LR		 1095 ieee80211_queue_delayed_work(sc->hw,
1096 &sc->ath_led_blink_work, 0);
f2bffa7e 1097 } else if (led->led_type == ATH_LED_RADIO) {
08fc5c1b 1098 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
f2bffa7e
VT		 1099 sc->sc_flags |= SC_OP_LED_ON;
1100 } else {
1101 sc->led_on_cnt++;
1102 }
8feceb67
VT		 1103 break;
1104 default:
1105 break;
f078f209 1106 }
8feceb67 1107}
f078f209 1108
8feceb67
VT		 1109static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1110 char *trigger)
1111{
1112 int ret;
f078f209 1113
8feceb67
VT		 1114 led->sc = sc;
1115 led->led_cdev.name = led->name;
1116 led->led_cdev.default_trigger = trigger;
1117 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1118
8feceb67
VT		 1119 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1120 if (ret)
c46917bb
LR		 1121 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1122 "Failed to register led:%s", led->name);
8feceb67
VT		 1123 else
1124 led->registered = 1;
1125 return ret;
1126}
f078f209 1127
8feceb67
VT		 1128static void ath_unregister_led(struct ath_led *led)
1129{
1130 if (led->registered) {
1131 led_classdev_unregister(&led->led_cdev);
1132 led->registered = 0;
f078f209 1133 }
f078f209
LR		 1134}
1135
8feceb67 1136static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1137{
8feceb67
VT		 1138 ath_unregister_led(&sc->assoc_led);
1139 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1140 ath_unregister_led(&sc->tx_led);
1141 ath_unregister_led(&sc->rx_led);
1142 ath_unregister_led(&sc->radio_led);
08fc5c1b 1143 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
8feceb67 1144}
f078f209 1145
8feceb67
VT		 1146static void ath_init_leds(struct ath_softc *sc)
1147{
1148 char *trigger;
1149 int ret;
f078f209 1150
08fc5c1b
VN		 1151 if (AR_SREV_9287(sc->sc_ah))
1152 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1153 else
1154 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1155
8feceb67 1156 /* Configure gpio 1 for output */
08fc5c1b 1157 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
8feceb67
VT		 1158 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1159 /* LED off, active low */
08fc5c1b 1160 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
7dcfdcd9 1161
f2bffa7e
VT		 1162 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1163
8feceb67
VT		 1164 trigger = ieee80211_get_radio_led_name(sc->hw);
1165 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1166 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1167 ret = ath_register_led(sc, &sc->radio_led, trigger);
1168 sc->radio_led.led_type = ATH_LED_RADIO;
1169 if (ret)
1170 goto fail;
7dcfdcd9 1171
8feceb67
VT		 1172 trigger = ieee80211_get_assoc_led_name(sc->hw);
1173 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1174 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1175 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1176 sc->assoc_led.led_type = ATH_LED_ASSOC;
1177 if (ret)
1178 goto fail;
f078f209 1179
8feceb67
VT		 1180 trigger = ieee80211_get_tx_led_name(sc->hw);
1181 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1182 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1183 ret = ath_register_led(sc, &sc->tx_led, trigger);
1184 sc->tx_led.led_type = ATH_LED_TX;
1185 if (ret)
1186 goto fail;
f078f209 1187
8feceb67
VT		 1188 trigger = ieee80211_get_rx_led_name(sc->hw);
1189 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1190 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1191 ret = ath_register_led(sc, &sc->rx_led, trigger);
1192 sc->rx_led.led_type = ATH_LED_RX;
1193 if (ret)
1194 goto fail;
f078f209 1195
8feceb67
VT		 1196 return;
1197
1198fail:
35c95ab9 1199 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67 1200 ath_deinit_leds(sc);
f078f209
LR		 1201}
1202
68a89116 1203void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 1204{
cbe61d8a 1205 struct ath_hw *ah = sc->sc_ah;
c46917bb 1206 struct ath_common *common = ath9k_hw_common(ah);
68a89116 1207 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 1208 int r;
500c064d 1209
3cbb5dd7 1210 ath9k_ps_wakeup(sc);
93b1b37f 1211 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 1212
159cd468
VT		 1213 if (!ah->curchan)
1214 ah->curchan = ath_get_curchannel(sc, sc->hw);
1215
d2f5b3a6 1216 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1217 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1218 if (r) {
c46917bb
LR		 1219 ath_print(common, ATH_DBG_FATAL,
1220 "Unable to reset channel %u (%uMhz) ",
1221 "reset status %d\n",
1222 channel->center_freq, r);
500c064d
VT		 1223 }
1224 spin_unlock_bh(&sc->sc_resetlock);
1225
1226 ath_update_txpow(sc);
1227 if (ath_startrecv(sc) != 0) {
c46917bb
LR		 1228 ath_print(common, ATH_DBG_FATAL,
1229 "Unable to restart recv logic\n");
500c064d
VT		 1230 return;
1231 }
1232
1233 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1234 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1235
1236 /* Re-Enable interrupts */
17d7904d 1237 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1238
1239 /* Enable LED */
08fc5c1b 1240 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 1241 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 1242 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 1243
68a89116 1244 ieee80211_wake_queues(hw);
3cbb5dd7 1245 ath9k_ps_restore(sc);
500c064d
VT		 1246}
1247
68a89116 1248void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 1249{
cbe61d8a 1250 struct ath_hw *ah = sc->sc_ah;
68a89116 1251 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 1252 int r;
500c064d 1253
3cbb5dd7 1254 ath9k_ps_wakeup(sc);
68a89116 1255 ieee80211_stop_queues(hw);
500c064d
VT		 1256
1257 /* Disable LED */
08fc5c1b
VN		 1258 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1259 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
500c064d
VT		 1260
1261 /* Disable interrupts */
1262 ath9k_hw_set_interrupts(ah, 0);
1263
043a0405 1264 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1265 ath_stoprecv(sc); /* turn off frame recv */
1266 ath_flushrecv(sc); /* flush recv queue */
1267
159cd468 1268 if (!ah->curchan)
68a89116 1269 ah->curchan = ath_get_curchannel(sc, hw);
159cd468 1270
500c064d 1271 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1272 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1273 if (r) {
c46917bb
LR		 1274 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1275 "Unable to reset channel %u (%uMhz) "
1276 "reset status %d\n",
1277 channel->center_freq, r);
500c064d
VT		 1278 }
1279 spin_unlock_bh(&sc->sc_resetlock);
1280
1281 ath9k_hw_phy_disable(ah);
93b1b37f 1282 ath9k_hw_configpcipowersave(ah, 1, 1);
3cbb5dd7 1283 ath9k_ps_restore(sc);
9ecdef4b 1284 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
500c064d
VT		 1285}
1286
5077fd35
GJ		 1287/*******************/
1288/* Rfkill */
1289/*******************/
1290
500c064d
VT		 1291static bool ath_is_rfkill_set(struct ath_softc *sc)
1292{
cbe61d8a 1293 struct ath_hw *ah = sc->sc_ah;
500c064d 1294
2660b81a
S		 1295 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1296 ah->rfkill_polarity;
500c064d
VT		 1297}
1298
3b319aae 1299static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
500c064d 1300{
3b319aae
JB		 1301 struct ath_wiphy *aphy = hw->priv;
1302 struct ath_softc *sc = aphy->sc;
19d337df 1303 bool blocked = !!ath_is_rfkill_set(sc);
500c064d 1304
3b319aae 1305 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
500c064d
VT		 1306}
1307
3b319aae 1308static void ath_start_rfkill_poll(struct ath_softc *sc)
500c064d 1309{
3b319aae 1310 struct ath_hw *ah = sc->sc_ah;
9c84b797 1311
3b319aae
JB		 1312 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1313 wiphy_rfkill_start_polling(sc->hw->wiphy);
9c84b797 1314}
500c064d 1315
7fda1666
LR		 1316static void ath9k_uninit_hw(struct ath_softc *sc)
1317{
1318 struct ath_hw *ah = sc->sc_ah;
1319
1320 BUG_ON(!ah);
1321
1322 ath9k_exit_debug(ah);
1323 ath9k_hw_detach(ah);
1324 sc->sc_ah = NULL;
1325}
1326
2568835c 1327static void ath_clean_core(struct ath_softc *sc)
f078f209 1328{
8feceb67 1329 struct ieee80211_hw *hw = sc->hw;
4d6b228d 1330 struct ath_hw *ah = sc->sc_ah;
9c84b797 1331 int i = 0;
f078f209 1332
3cbb5dd7
VN		 1333 ath9k_ps_wakeup(sc);
1334
4d6b228d 1335 dev_dbg(sc->dev, "Detach ATH hw\n");
f078f209 1336
35c95ab9 1337 ath_deinit_leds(sc);
e31f7b96 1338 wiphy_rfkill_stop_polling(sc->hw->wiphy);
35c95ab9 1339
c52f33d0
JM		 1340 for (i = 0; i < sc->num_sec_wiphy; i++) {
1341 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1342 if (aphy == NULL)
1343 continue;
1344 sc->sec_wiphy[i] = NULL;
1345 ieee80211_unregister_hw(aphy->hw);
1346 ieee80211_free_hw(aphy->hw);
1347 }
3fcdfb4b 1348 ieee80211_unregister_hw(hw);
8feceb67
VT		 1349 ath_rx_cleanup(sc);
1350 ath_tx_cleanup(sc);
f078f209 1351
9c84b797
S		 1352 tasklet_kill(&sc->intr_tq);
1353 tasklet_kill(&sc->bcon_tasklet);
f078f209 1354
9c84b797 1355 if (!(sc->sc_flags & SC_OP_INVALID))
9ecdef4b 1356 ath9k_setpower(sc, ATH9K_PM_AWAKE);
8feceb67 1357
9c84b797
S		 1358 /* cleanup tx queues */
1359 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1360 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1361 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797 1362
75d7839f 1363 if ((sc->btcoex.no_stomp_timer) &&
766ec4a9 1364 ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1365 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
2568835c 1366}
1773912b 1367
2568835c
LR		 1368void ath_detach(struct ath_softc *sc)
1369{
1370 ath_clean_core(sc);
7fda1666 1371 ath9k_uninit_hw(sc);
f078f209
LR		 1372}
1373
bd96d390
LR		 1374void ath_cleanup(struct ath_softc *sc)
1375{
1376 struct ath_hw *ah = sc->sc_ah;
1377 struct ath_common *common = ath9k_hw_common(ah);
1378
1379 ath_clean_core(sc);
1380 free_irq(sc->irq, sc);
1381 ath_bus_cleanup(common);
1382 kfree(sc->sec_wiphy);
1383 ieee80211_free_hw(sc->hw);
1384
1385 ath9k_uninit_hw(sc);
1386}
1387
e3bb249b
BC		 1388static int ath9k_reg_notifier(struct wiphy *wiphy,
1389 struct regulatory_request *request)
1390{
1391 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1392 struct ath_wiphy *aphy = hw->priv;
1393 struct ath_softc *sc = aphy->sc;
27c51f1a 1394 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
e3bb249b
BC		 1395
1396 return ath_reg_notifier_apply(wiphy, request, reg);
1397}
1398
75d7839f
LR		 1399/*
1400 * Detects if there is any priority bt traffic
1401 */
1402static void ath_detect_bt_priority(struct ath_softc *sc)
1403{
1404 struct ath_btcoex *btcoex = &sc->btcoex;
1405 struct ath_hw *ah = sc->sc_ah;
1406
766ec4a9 1407 if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
75d7839f
LR		 1408 btcoex->bt_priority_cnt++;
1409
1410 if (time_after(jiffies, btcoex->bt_priority_time +
1411 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1412 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
c46917bb
LR		 1413 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
1414 "BT priority traffic detected");
75d7839f
LR		 1415 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1416 } else {
1417 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1418 }
1419
1420 btcoex->bt_priority_cnt = 0;
1421 btcoex->bt_priority_time = jiffies;
1422 }
1423}
1424
75d7839f
LR		 1425/*
1426 * Configures appropriate weight based on stomp type.
1427 */
269ad812
LR		 1428static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1429 enum ath_stomp_type stomp_type)
75d7839f 1430{
269ad812 1431 struct ath_hw *ah = sc->sc_ah;
75d7839f
LR		 1432
1433 switch (stomp_type) {
1434 case ATH_BTCOEX_STOMP_ALL:
269ad812
LR		 1435 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1436 AR_STOMP_ALL_WLAN_WGHT);
75d7839f
LR		 1437 break;
1438 case ATH_BTCOEX_STOMP_LOW:
269ad812
LR		 1439 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1440 AR_STOMP_LOW_WLAN_WGHT);
75d7839f
LR		 1441 break;
1442 case ATH_BTCOEX_STOMP_NONE:
269ad812
LR		 1443 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1444 AR_STOMP_NONE_WLAN_WGHT);
75d7839f
LR		 1445 break;
1446 default:
c46917bb
LR		 1447 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1448 "Invalid Stomptype\n");
75d7839f
LR		 1449 break;
1450 }
1451
269ad812 1452 ath9k_hw_btcoex_enable(ah);
75d7839f
LR		 1453}
1454
cd9bf689
LR		 1455static void ath9k_gen_timer_start(struct ath_hw *ah,
1456 struct ath_gen_timer *timer,
1457 u32 timer_next,
1458 u32 timer_period)
1459{
bc974f4a
LR		 1460 struct ath_common *common = ath9k_hw_common(ah);
1461 struct ath_softc *sc = (struct ath_softc *) common->priv;
1462
cd9bf689
LR		 1463 ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
1464
bc974f4a 1465 if ((sc->imask & ATH9K_INT_GENTIMER) == 0) {
cd9bf689 1466 ath9k_hw_set_interrupts(ah, 0);
bc974f4a
LR		 1467 sc->imask |= ATH9K_INT_GENTIMER;
1468 ath9k_hw_set_interrupts(ah, sc->imask);
cd9bf689
LR		 1469 }
1470}
1471
1472static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
1473{
bc974f4a
LR		 1474 struct ath_common *common = ath9k_hw_common(ah);
1475 struct ath_softc *sc = (struct ath_softc *) common->priv;
cd9bf689
LR		 1476 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1477
1478 ath9k_hw_gen_timer_stop(ah, timer);
1479
1480 /* if no timer is enabled, turn off interrupt mask */
1481 if (timer_table->timer_mask.val == 0) {
1482 ath9k_hw_set_interrupts(ah, 0);
bc974f4a
LR		 1483 sc->imask &= ~ATH9K_INT_GENTIMER;
1484 ath9k_hw_set_interrupts(ah, sc->imask);
cd9bf689
LR		 1485 }
1486}
1487
75d7839f
LR		 1488/*
1489 * This is the master bt coex timer which runs for every
1490 * 45ms, bt traffic will be given priority during 55% of this
1491 * period while wlan gets remaining 45%
1492 */
1493static void ath_btcoex_period_timer(unsigned long data)
1494{
1495 struct ath_softc *sc = (struct ath_softc *) data;
1496 struct ath_hw *ah = sc->sc_ah;
1497 struct ath_btcoex *btcoex = &sc->btcoex;
75d7839f
LR		 1498
1499 ath_detect_bt_priority(sc);
1500
1501 spin_lock_bh(&btcoex->btcoex_lock);
1502
269ad812 1503 ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
75d7839f
LR		 1504
1505 spin_unlock_bh(&btcoex->btcoex_lock);
1506
1507 if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1508 if (btcoex->hw_timer_enabled)
cd9bf689 1509 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
75d7839f 1510
cd9bf689
LR		 1511 ath9k_gen_timer_start(ah,
1512 btcoex->no_stomp_timer,
1513 (ath9k_hw_gettsf32(ah) +
1514 btcoex->btcoex_no_stomp),
1515 btcoex->btcoex_no_stomp * 10);
75d7839f
LR		 1516 btcoex->hw_timer_enabled = true;
1517 }
1518
1519 mod_timer(&btcoex->period_timer, jiffies +
1520 msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1521}
1522
1523/*
1524 * Generic tsf based hw timer which configures weight
1525 * registers to time slice between wlan and bt traffic
1526 */
1527static void ath_btcoex_no_stomp_timer(void *arg)
1528{
1529 struct ath_softc *sc = (struct ath_softc *)arg;
1530 struct ath_hw *ah = sc->sc_ah;
1531 struct ath_btcoex *btcoex = &sc->btcoex;
75d7839f 1532
c46917bb
LR		 1533 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1534 "no stomp timer running \n");
75d7839f
LR		 1535
1536 spin_lock_bh(&btcoex->btcoex_lock);
1537
e08a6ace 1538 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
269ad812 1539 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
e08a6ace 1540 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
269ad812 1541 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
75d7839f
LR		 1542
1543 spin_unlock_bh(&btcoex->btcoex_lock);
1544}
1545
1546static int ath_init_btcoex_timer(struct ath_softc *sc)
1547{
1548 struct ath_btcoex *btcoex = &sc->btcoex;
1549
1550 btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1551 btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1552 btcoex->btcoex_period / 100;
1553
1554 setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1555 (unsigned long) sc);
1556
1557 spin_lock_init(&btcoex->btcoex_lock);
1558
1559 btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1560 ath_btcoex_no_stomp_timer,
1561 ath_btcoex_no_stomp_timer,
1562 (void *) sc, AR_FIRST_NDP_TIMER);
1563
1564 if (!btcoex->no_stomp_timer)
1565 return -ENOMEM;
1566
1567 return 0;
1568}
1569
9e4bffd2
LR		 1570/*
1571 * Read and write, they both share the same lock. We do this to serialize
1572 * reads and writes on Atheros 802.11n PCI devices only. This is required
1573 * as the FIFO on these devices can only accept sanely 2 requests. After
1574 * that the device goes bananas. Serializing the reads/writes prevents this
1575 * from happening.
1576 */
1577
1578static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
1579{
1580 struct ath_hw *ah = (struct ath_hw *) hw_priv;
bc974f4a
LR		 1581 struct ath_common *common = ath9k_hw_common(ah);
1582 struct ath_softc *sc = (struct ath_softc *) common->priv;
9e4bffd2
LR		 1583
1584 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1585 unsigned long flags;
bc974f4a
LR		 1586 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1587 iowrite32(val, sc->mem + reg_offset);
1588 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
9e4bffd2 1589 } else
bc974f4a 1590 iowrite32(val, sc->mem + reg_offset);
9e4bffd2
LR		 1591}
1592
1593static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
1594{
1595 struct ath_hw *ah = (struct ath_hw *) hw_priv;
bc974f4a
LR		 1596 struct ath_common *common = ath9k_hw_common(ah);
1597 struct ath_softc *sc = (struct ath_softc *) common->priv;
9e4bffd2
LR		 1598 u32 val;
1599
1600 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1601 unsigned long flags;
bc974f4a
LR		 1602 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1603 val = ioread32(sc->mem + reg_offset);
1604 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
9e4bffd2 1605 } else
bc974f4a 1606 val = ioread32(sc->mem + reg_offset);
9e4bffd2
LR		 1607 return val;
1608}
1609
2ddb5c8b 1610static const struct ath_ops ath9k_common_ops = {
9e4bffd2
LR		 1611 .read = ath9k_ioread32,
1612 .write = ath9k_iowrite32,
1613};
1614
1e40bcfa
LR		 1615/*
1616 * Initialize and fill ath_softc, ath_sofct is the
1617 * "Software Carrier" struct. Historically it has existed
1618 * to allow the separation between hardware specific
1619 * variables (now in ath_hw) and driver specific variables.
1620 */
5bb12791
LR		 1621static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
1622 const struct ath_bus_ops *bus_ops)
ff37e337 1623{
cbe61d8a 1624 struct ath_hw *ah = NULL;
1510718d 1625 struct ath_common *common;
4f3acf81 1626 int r = 0, i;
ff37e337 1627 int csz = 0;
75d7839f 1628 int qnum;
ff37e337
S		 1629
1630 /* XXX: hardware will not be ready until ath_open() being called */
1631 sc->sc_flags |= SC_OP_INVALID;
88b126af 1632
c52f33d0 1633 spin_lock_init(&sc->wiphy_lock);
ff37e337 1634 spin_lock_init(&sc->sc_resetlock);
6158425b 1635 spin_lock_init(&sc->sc_serial_rw);
e5f0921a 1636 spin_lock_init(&sc->ani_lock);
04717ccd 1637 spin_lock_init(&sc->sc_pm_lock);
aa33de09 1638 mutex_init(&sc->mutex);
ff37e337 1639 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1640 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1641 (unsigned long)sc);
1642
4f3acf81 1643 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
211f5859
LR		 1644 if (!ah)
1645 return -ENOMEM;
4f3acf81 1646
8df5d1b7 1647 ah->hw_version.devid = devid;
aeac355d 1648 ah->hw_version.subsysid = subsysid;
e1e2f93f 1649 sc->sc_ah = ah;
4f3acf81 1650
27c51f1a 1651 common = ath9k_hw_common(ah);
9e4bffd2 1652 common->ops = &ath9k_common_ops;
5bb12791 1653 common->bus_ops = bus_ops;
13b81559 1654 common->ah = ah;
b002a4a9 1655 common->hw = sc->hw;
bc974f4a 1656 common->priv = sc;
faa27fae 1657 common->debug_mask = ath9k_debug;
27c51f1a
LR		 1658
1659 /*
1660 * Cache line size is used to size and align various
1661 * structures used to communicate with the hardware.
1662 */
5bb12791 1663 ath_read_cachesize(common, &csz);
27c51f1a
LR		 1664 /* XXX assert csz is non-zero */
1665 common->cachelsz = csz << 2; /* convert to bytes */
1666
f637cfd6 1667 r = ath9k_hw_init(ah);
4f3acf81 1668 if (r) {
c46917bb
LR		 1669 ath_print(common, ATH_DBG_FATAL,
1670 "Unable to initialize hardware; "
1671 "initialization status: %d\n", r);
211f5859
LR		 1672 goto bad_free_hw;
1673 }
1674
1675 if (ath9k_init_debug(ah) < 0) {
1676 ath_print(common, ATH_DBG_FATAL,
1677 "Unable to create debugfs files\n");
1678 goto bad_free_hw;
ff37e337 1679 }
ff37e337
S		 1680
1681 /* Get the hardware key cache size. */
2660b81a 1682 sc->keymax = ah->caps.keycache_size;
17d7904d 1683 if (sc->keymax > ATH_KEYMAX) {
c46917bb
LR		 1684 ath_print(common, ATH_DBG_ANY,
1685 "Warning, using only %u entries in %u key cache\n",
1686 ATH_KEYMAX, sc->keymax);
17d7904d 1687 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1688 }
1689
1690 /*
1691 * Reset the key cache since some parts do not
1692 * reset the contents on initial power up.
1693 */
17d7904d 1694 for (i = 0; i < sc->keymax; i++)
ff37e337 1695 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1696
ff37e337 1697 /* default to MONITOR mode */
2660b81a 1698 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1699
ff37e337
S		 1700 /* Setup rate tables */
1701
1702 ath_rate_attach(sc);
1703 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1704 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1705
1706 /*
1707 * Allocate hardware transmit queues: one queue for
1708 * beacon frames and one data queue for each QoS
1709 * priority. Note that the hal handles reseting
1710 * these queues at the needed time.
1711 */
536b3a7a 1712 sc->beacon.beaconq = ath9k_hw_beaconq_setup(ah);
b77f483f 1713 if (sc->beacon.beaconq == -1) {
c46917bb
LR		 1714 ath_print(common, ATH_DBG_FATAL,
1715 "Unable to setup a beacon xmit queue\n");
4f3acf81 1716 r = -EIO;
ff37e337
S		 1717 goto bad2;
1718 }
b77f483f
S		 1719 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1720 if (sc->beacon.cabq == NULL) {
c46917bb
LR		 1721 ath_print(common, ATH_DBG_FATAL,
1722 "Unable to setup CAB xmit queue\n");
4f3acf81 1723 r = -EIO;
ff37e337
S		 1724 goto bad2;
1725 }
1726
17d7904d 1727 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1728 ath_cabq_update(sc);
1729
b77f483f
S		 1730 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1731 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1732
1733 /* Setup data queues */
1734 /* NB: ensure BK queue is the lowest priority h/w queue */
1735 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
c46917bb
LR		 1736 ath_print(common, ATH_DBG_FATAL,
1737 "Unable to setup xmit queue for BK traffic\n");
4f3acf81 1738 r = -EIO;
ff37e337
S		 1739 goto bad2;
1740 }
1741
1742 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
c46917bb
LR		 1743 ath_print(common, ATH_DBG_FATAL,
1744 "Unable to setup xmit queue for BE traffic\n");
4f3acf81 1745 r = -EIO;
ff37e337
S		 1746 goto bad2;
1747 }
1748 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
c46917bb
LR		 1749 ath_print(common, ATH_DBG_FATAL,
1750 "Unable to setup xmit queue for VI traffic\n");
4f3acf81 1751 r = -EIO;
ff37e337
S		 1752 goto bad2;
1753 }
1754 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
c46917bb
LR		 1755 ath_print(common, ATH_DBG_FATAL,
1756 "Unable to setup xmit queue for VO traffic\n");
4f3acf81 1757 r = -EIO;
ff37e337
S		 1758 goto bad2;
1759 }
1760
1761 /* Initializes the noise floor to a reasonable default value.
1762 * Later on this will be updated during ANI processing. */
1763
17d7904d
S		 1764 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1765 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1766
1767 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1768 ATH9K_CIPHER_TKIP, NULL)) {
1769 /*
1770 * Whether we should enable h/w TKIP MIC.
1771 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1772 * report WMM capable, so it's always safe to turn on
1773 * TKIP MIC in this case.
1774 */
1775 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1776 0, 1, NULL);
1777 }
1778
1779 /*
1780 * Check whether the separate key cache entries
1781 * are required to handle both tx+rx MIC keys.
1782 * With split mic keys the number of stations is limited
1783 * to 27 otherwise 59.
1784 */
1785 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1786 ATH9K_CIPHER_TKIP, NULL)
1787 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1788 ATH9K_CIPHER_MIC, NULL)
1789 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1790 0, NULL))
17d7904d 1791 sc->splitmic = 1;
ff37e337
S		 1792
1793 /* turn on mcast key search if possible */
1794 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1795 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1796 1, NULL);
1797
17d7904d 1798 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1799
1800 /* 11n Capabilities */
2660b81a 1801 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1802 sc->sc_flags |= SC_OP_TXAGGR;
1803 sc->sc_flags |= SC_OP_RXAGGR;
1804 }
1805
43c27613
LR		 1806 common->tx_chainmask = ah->caps.tx_chainmask;
1807 common->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1808
1809 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1810 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1811
8ca21f01 1812 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1510718d 1813 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1814
b77f483f 1815 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1816
1817 /* initialize beacon slots */
c52f33d0 1818 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1819 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1820 sc->beacon.bslot_aphy[i] = NULL;
1821 }
ff37e337 1822
ff37e337
S		 1823 /* setup channels and rates */
1824
5f8e077c 1825 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1826 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1827 sc->rates[IEEE80211_BAND_2GHZ];
1828 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1829 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1830 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1831
2660b81a 1832 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1833 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1834 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1835 sc->rates[IEEE80211_BAND_5GHZ];
1836 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1837 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1838 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1839 }
1840
766ec4a9 1841 switch (ah->btcoex_hw.scheme) {
75d7839f
LR		 1842 case ATH_BTCOEX_CFG_NONE:
1843 break;
1844 case ATH_BTCOEX_CFG_2WIRE:
1845 ath9k_hw_btcoex_init_2wire(ah);
1846 break;
1847 case ATH_BTCOEX_CFG_3WIRE:
1848 ath9k_hw_btcoex_init_3wire(ah);
1849 r = ath_init_btcoex_timer(sc);
1773912b
VT		 1850 if (r)
1851 goto bad2;
75d7839f 1852 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
766ec4a9 1853 ath9k_hw_init_btcoex_hw(ah, qnum);
e08a6ace 1854 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
75d7839f
LR		 1855 break;
1856 default:
1857 WARN_ON(1);
1858 break;
1773912b 1859 }
c97c92d9 1860
ff37e337
S		 1861 return 0;
1862bad2:
1863 /* cleanup tx queues */
1864 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1865 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1866 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
211f5859 1867
211f5859 1868bad_free_hw:
7fda1666 1869 ath9k_uninit_hw(sc);
4f3acf81 1870 return r;
ff37e337
S		 1871}
1872
c52f33d0 1873void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1874{
9c84b797
S		 1875 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1876 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1877 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1878 IEEE80211_HW_AMPDU_AGGREGATION |
1879 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1880 IEEE80211_HW_PS_NULLFUNC_STACK |
1881 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1882
b3bd89ce 1883 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1884 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1885
9c84b797
S		 1886 hw->wiphy->interface_modes =
1887 BIT(NL80211_IFTYPE_AP) |
1888 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1889 BIT(NL80211_IFTYPE_ADHOC) |
1890 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1891
8feceb67 1892 hw->queues = 4;
e63835b0 1893 hw->max_rates = 4;
171387ef 1894 hw->channel_change_time = 5000;
465ca84d 1895 hw->max_listen_interval = 10;
dd190183
LR		 1896 /* Hardware supports 10 but we use 4 */
1897 hw->max_rate_tries = 4;
528f0c6b 1898 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1899 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1900
8feceb67 1901 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1902
c52f33d0
JM		 1903 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1904 &sc->sbands[IEEE80211_BAND_2GHZ];
1905 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1906 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1907 &sc->sbands[IEEE80211_BAND_5GHZ];
1908}
1909
1e40bcfa 1910/* Device driver core initialization */
5bb12791
LR		 1911int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
1912 const struct ath_bus_ops *bus_ops)
c52f33d0
JM		 1913{
1914 struct ieee80211_hw *hw = sc->hw;
1510718d 1915 struct ath_common *common;
4d6b228d 1916 struct ath_hw *ah;
c52f33d0 1917 int error = 0, i;
3a702e49 1918 struct ath_regulatory *reg;
c52f33d0 1919
4d6b228d 1920 dev_dbg(sc->dev, "Attach ATH hw\n");
c52f33d0 1921
5bb12791 1922 error = ath_init_softc(devid, sc, subsysid, bus_ops);
c52f33d0
JM		 1923 if (error != 0)
1924 return error;
1925
4d6b228d 1926 ah = sc->sc_ah;
1510718d 1927 common = ath9k_hw_common(ah);
4d6b228d 1928
c52f33d0
JM		 1929 /* get mac address from hardware and set in mac80211 */
1930
1510718d 1931 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
c52f33d0
JM		 1932
1933 ath_set_hw_capab(sc, hw);
1934
1510718d 1935 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
c26c2e57
LR		 1936 ath9k_reg_notifier);
1937 if (error)
1938 return error;
1939
1510718d 1940 reg = &common->regulatory;
c26c2e57 1941
4d6b228d 1942 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1943 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
4d6b228d 1944 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
eb2599ca 1945 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1946 }
1947
db93e7b5
SB		 1948 /* initialize tx/rx engine */
1949 error = ath_tx_init(sc, ATH_TXBUF);
1950 if (error != 0)
40b130a9 1951 goto error_attach;
8feceb67 1952
db93e7b5
SB		 1953 error = ath_rx_init(sc, ATH_RXBUF);
1954 if (error != 0)
40b130a9 1955 goto error_attach;
8feceb67 1956
0e2dedf9 1957 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1958 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1959 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1960
db93e7b5 1961 error = ieee80211_register_hw(hw);
8feceb67 1962
3a702e49 1963 if (!ath_is_world_regd(reg)) {
c02cf373 1964 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1965 if (error)
1966 goto error_attach;
1967 }
5f8e077c 1968
db93e7b5
SB		 1969 /* Initialize LED control */
1970 ath_init_leds(sc);
8feceb67 1971
3b319aae 1972 ath_start_rfkill_poll(sc);
5f8e077c 1973
8feceb67 1974 return 0;
40b130a9
VT		 1975
1976error_attach:
1977 /* cleanup tx queues */
1978 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1979 if (ATH_TXQ_SETUP(sc, i))
1980 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1981
7fda1666 1982 ath9k_uninit_hw(sc);
40b130a9 1983
8feceb67 1984 return error;
f078f209
LR		 1985}
1986
ff37e337
S		 1987int ath_reset(struct ath_softc *sc, bool retry_tx)
1988{
cbe61d8a 1989 struct ath_hw *ah = sc->sc_ah;
c46917bb 1990 struct ath_common *common = ath9k_hw_common(ah);
030bb495 1991 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1992 int r;
ff37e337
S		 1993
1994 ath9k_hw_set_interrupts(ah, 0);
043a0405 1995 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1996 ath_stoprecv(sc);
1997 ath_flushrecv(sc);
1998
1999 spin_lock_bh(&sc->sc_resetlock);
2660b81a 2000 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 2001 if (r)
c46917bb
LR		 2002 ath_print(common, ATH_DBG_FATAL,
2003 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 2004 spin_unlock_bh(&sc->sc_resetlock);
2005
2006 if (ath_startrecv(sc) != 0)
c46917bb
LR		 2007 ath_print(common, ATH_DBG_FATAL,
2008 "Unable to start recv logic\n");
ff37e337
S		 2009
2010 /*
2011 * We may be doing a reset in response to a request
2012 * that changes the channel so update any state that
2013 * might change as a result.
2014 */
ce111bad 2015 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2016
2017 ath_update_txpow(sc);
2018
2019 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 2020 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 2021
17d7904d 2022 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 2023
2024 if (retry_tx) {
2025 int i;
2026 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2027 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 2028 spin_lock_bh(&sc->tx.txq[i].axq_lock);
2029 ath_txq_schedule(sc, &sc->tx.txq[i]);
2030 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 2031 }
2032 }
2033 }
2034
ae8d2858 2035 return r;
ff37e337
S		 2036}
2037
2038/*
2039 * This function will allocate both the DMA descriptor structure, and the
2040 * buffers it contains. These are used to contain the descriptors used
2041 * by the system.
2042*/
2043int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
2044 struct list_head *head, const char *name,
2045 int nbuf, int ndesc)
2046{
2047#define DS2PHYS(_dd, _ds) \
2048 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2049#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
2050#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
c46917bb 2051 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
ff37e337
S		 2052 struct ath_desc *ds;
2053 struct ath_buf *bf;
2054 int i, bsize, error;
2055
c46917bb
LR		 2056 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
2057 name, nbuf, ndesc);
ff37e337 2058
b03a9db9 2059 INIT_LIST_HEAD(head);
ff37e337
S		 2060 /* ath_desc must be a multiple of DWORDs */
2061 if ((sizeof(struct ath_desc) % 4) != 0) {
c46917bb
LR		 2062 ath_print(common, ATH_DBG_FATAL,
2063 "ath_desc not DWORD aligned\n");
9680e8a3 2064 BUG_ON((sizeof(struct ath_desc) % 4) != 0);
ff37e337
S		 2065 error = -ENOMEM;
2066 goto fail;
2067 }
2068
ff37e337
S		 2069 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2070
2071 /*
2072 * Need additional DMA memory because we can't use
2073 * descriptors that cross the 4K page boundary. Assume
2074 * one skipped descriptor per 4K page.
2075 */
2660b81a 2076 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 2077 u32 ndesc_skipped =
2078 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
2079 u32 dma_len;
2080
2081 while (ndesc_skipped) {
2082 dma_len = ndesc_skipped * sizeof(struct ath_desc);
2083 dd->dd_desc_len += dma_len;
2084
2085 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
2086 };
2087 }
2088
2089 /* allocate descriptors */
7da3c55c 2090 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 2091 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 2092 if (dd->dd_desc == NULL) {
2093 error = -ENOMEM;
2094 goto fail;
2095 }
2096 ds = dd->dd_desc;
c46917bb
LR		 2097 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
2098 name, ds, (u32) dd->dd_desc_len,
2099 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
ff37e337
S		 2100
2101 /* allocate buffers */
2102 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 2103 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 2104 if (bf == NULL) {
2105 error = -ENOMEM;
2106 goto fail2;
2107 }
ff37e337
S		 2108 dd->dd_bufptr = bf;
2109
ff37e337
S		 2110 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2111 bf->bf_desc = ds;
2112 bf->bf_daddr = DS2PHYS(dd, ds);
2113
2660b81a 2114 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 2115 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2116 /*
2117 * Skip descriptor addresses which can cause 4KB
2118 * boundary crossing (addr + length) with a 32 dword
2119 * descriptor fetch.
2120 */
2121 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
9680e8a3 2122 BUG_ON((caddr_t) bf->bf_desc >=
ff37e337
S		 2123 ((caddr_t) dd->dd_desc +
2124 dd->dd_desc_len));
2125
2126 ds += ndesc;
2127 bf->bf_desc = ds;
2128 bf->bf_daddr = DS2PHYS(dd, ds);
2129 }
2130 }
2131 list_add_tail(&bf->list, head);
2132 }
2133 return 0;
2134fail2:
7da3c55c
GJ		 2135 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2136 dd->dd_desc_paddr);
ff37e337
S		 2137fail:
2138 memset(dd, 0, sizeof(*dd));
2139 return error;
2140#undef ATH_DESC_4KB_BOUND_CHECK
2141#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
2142#undef DS2PHYS
2143}
2144
2145void ath_descdma_cleanup(struct ath_softc *sc,
2146 struct ath_descdma *dd,
2147 struct list_head *head)
2148{
7da3c55c
GJ		 2149 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2150 dd->dd_desc_paddr);
ff37e337
S		 2151
2152 INIT_LIST_HEAD(head);
2153 kfree(dd->dd_bufptr);
2154 memset(dd, 0, sizeof(*dd));
2155}
2156
2157int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
2158{
2159 int qnum;
2160
2161 switch (queue) {
2162 case 0:
b77f483f 2163 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 2164 break;
2165 case 1:
b77f483f 2166 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 2167 break;
2168 case 2:
b77f483f 2169 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 2170 break;
2171 case 3:
b77f483f 2172 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 2173 break;
2174 default:
b77f483f 2175 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 2176 break;
2177 }
2178
2179 return qnum;
2180}
2181
2182int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2183{
2184 int qnum;
2185
2186 switch (queue) {
2187 case ATH9K_WME_AC_VO:
2188 qnum = 0;
2189 break;
2190 case ATH9K_WME_AC_VI:
2191 qnum = 1;
2192 break;
2193 case ATH9K_WME_AC_BE:
2194 qnum = 2;
2195 break;
2196 case ATH9K_WME_AC_BK:
2197 qnum = 3;
2198 break;
2199 default:
2200 qnum = -1;
2201 break;
2202 }
2203
2204 return qnum;
2205}
2206
5f8e077c
LR		 2207/* XXX: Remove me once we don't depend on ath9k_channel for all
2208 * this redundant data */
0e2dedf9
JM		 2209void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2210 struct ath9k_channel *ichan)
5f8e077c 2211{
5f8e077c
LR		 2212 struct ieee80211_channel *chan = hw->conf.channel;
2213 struct ieee80211_conf *conf = &hw->conf;
2214
2215 ichan->channel = chan->center_freq;
2216 ichan->chan = chan;
2217
2218 if (chan->band == IEEE80211_BAND_2GHZ) {
2219 ichan->chanmode = CHANNEL_G;
8813262e 2220 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
5f8e077c
LR		 2221 } else {
2222 ichan->chanmode = CHANNEL_A;
2223 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2224 }
2225
25c56eec 2226 if (conf_is_ht(conf))
5f8e077c
LR		 2227 ichan->chanmode = ath_get_extchanmode(sc, chan,
2228 conf->channel_type);
5f8e077c
LR		 2229}
2230
ff37e337
S		 2231/**********************/
2232/* mac80211 callbacks */
2233/**********************/
2234
75d7839f
LR		 2235/*
2236 * (Re)start btcoex timers
2237 */
2238static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2239{
2240 struct ath_btcoex *btcoex = &sc->btcoex;
2241 struct ath_hw *ah = sc->sc_ah;
2242
c46917bb
LR		 2243 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
2244 "Starting btcoex timers");
75d7839f
LR		 2245
2246 /* make sure duty cycle timer is also stopped when resuming */
2247 if (btcoex->hw_timer_enabled)
cd9bf689 2248 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
75d7839f
LR		 2249
2250 btcoex->bt_priority_cnt = 0;
2251 btcoex->bt_priority_time = jiffies;
2252 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2253
2254 mod_timer(&btcoex->period_timer, jiffies);
2255}
2256
8feceb67 2257static int ath9k_start(struct ieee80211_hw *hw)
f078f209 2258{
bce048d7
JM		 2259 struct ath_wiphy *aphy = hw->priv;
2260 struct ath_softc *sc = aphy->sc;
af03abec 2261 struct ath_hw *ah = sc->sc_ah;
c46917bb 2262 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 2263 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 2264 struct ath9k_channel *init_channel;
82880a7c 2265 int r;
f078f209 2266
c46917bb
LR		 2267 ath_print(common, ATH_DBG_CONFIG,
2268 "Starting driver with initial channel: %d MHz\n",
2269 curchan->center_freq);
f078f209 2270
141b38b6
S		 2271 mutex_lock(&sc->mutex);
2272
9580a222
JM		 2273 if (ath9k_wiphy_started(sc)) {
2274 if (sc->chan_idx == curchan->hw_value) {
2275 /*
2276 * Already on the operational channel, the new wiphy
2277 * can be marked active.
2278 */
2279 aphy->state = ATH_WIPHY_ACTIVE;
2280 ieee80211_wake_queues(hw);
2281 } else {
2282 /*
2283 * Another wiphy is on another channel, start the new
2284 * wiphy in paused state.
2285 */
2286 aphy->state = ATH_WIPHY_PAUSED;
2287 ieee80211_stop_queues(hw);
2288 }
2289 mutex_unlock(&sc->mutex);
2290 return 0;
2291 }
2292 aphy->state = ATH_WIPHY_ACTIVE;
2293
8feceb67 2294 /* setup initial channel */
f078f209 2295
82880a7c 2296 sc->chan_idx = curchan->hw_value;
f078f209 2297
82880a7c 2298 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S		 2299
2300 /* Reset SERDES registers */
af03abec 2301 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S		 2302
2303 /*
2304 * The basic interface to setting the hardware in a good
2305 * state is ``reset''. On return the hardware is known to
2306 * be powered up and with interrupts disabled. This must
2307 * be followed by initialization of the appropriate bits
2308 * and then setup of the interrupt mask.
2309 */
2310 spin_lock_bh(&sc->sc_resetlock);
af03abec 2311 r = ath9k_hw_reset(ah, init_channel, false);
ae8d2858 2312 if (r) {
c46917bb
LR		 2313 ath_print(common, ATH_DBG_FATAL,
2314 "Unable to reset hardware; reset status %d "
2315 "(freq %u MHz)\n", r,
2316 curchan->center_freq);
ff37e337 2317 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 2318 goto mutex_unlock;
ff37e337
S		 2319 }
2320 spin_unlock_bh(&sc->sc_resetlock);
2321
2322 /*
2323 * This is needed only to setup initial state
2324 * but it's best done after a reset.
2325 */
2326 ath_update_txpow(sc);
8feceb67 2327
ff37e337
S		 2328 /*
2329 * Setup the hardware after reset:
2330 * The receive engine is set going.
2331 * Frame transmit is handled entirely
2332 * in the frame output path; there's nothing to do
2333 * here except setup the interrupt mask.
2334 */
2335 if (ath_startrecv(sc) != 0) {
c46917bb
LR		 2336 ath_print(common, ATH_DBG_FATAL,
2337 "Unable to start recv logic\n");
141b38b6
S		 2338 r = -EIO;
2339 goto mutex_unlock;
f078f209 2340 }
8feceb67 2341
ff37e337 2342 /* Setup our intr mask. */
17d7904d 2343 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 2344 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2345 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2346
af03abec 2347 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2348 sc->imask |= ATH9K_INT_GTT;
ff37e337 2349
af03abec 2350 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2351 sc->imask |= ATH9K_INT_CST;
ff37e337 2352
ce111bad 2353 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2354
2355 sc->sc_flags &= ~SC_OP_INVALID;
2356
2357 /* Disable BMISS interrupt when we're not associated */
17d7904d 2358 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
af03abec 2359 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337 2360
bce048d7 2361 ieee80211_wake_queues(hw);
ff37e337 2362
42935eca 2363 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 2364
766ec4a9
LR		 2365 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2366 !ah->btcoex_hw.enabled) {
5e197292
LR		 2367 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2368 AR_STOMP_LOW_WLAN_WGHT);
af03abec 2369 ath9k_hw_btcoex_enable(ah);
f985ad12 2370
5bb12791
LR		 2371 if (common->bus_ops->bt_coex_prep)
2372 common->bus_ops->bt_coex_prep(common);
766ec4a9 2373 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 2374 ath9k_btcoex_timer_resume(sc);
1773912b
VT		 2375 }
2376
141b38b6
S		 2377mutex_unlock:
2378 mutex_unlock(&sc->mutex);
2379
ae8d2858 2380 return r;
f078f209
LR		 2381}
2382
8feceb67
VT		 2383static int ath9k_tx(struct ieee80211_hw *hw,
2384 struct sk_buff *skb)
f078f209 2385{
528f0c6b 2386 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 2387 struct ath_wiphy *aphy = hw->priv;
2388 struct ath_softc *sc = aphy->sc;
c46917bb 2389 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 2390 struct ath_tx_control txctl;
8feceb67 2391 int hdrlen, padsize;
528f0c6b 2392
8089cc47 2393 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
c46917bb
LR		 2394 ath_print(common, ATH_DBG_XMIT,
2395 "ath9k: %s: TX in unexpected wiphy state "
2396 "%d\n", wiphy_name(hw->wiphy), aphy->state);
ee166a0e
JM		 2397 goto exit;
2398 }
2399
96148326 2400 if (sc->ps_enabled) {
dc8c4585
JM		 2401 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2402 /*
2403 * mac80211 does not set PM field for normal data frames, so we
2404 * need to update that based on the current PS mode.
2405 */
2406 if (ieee80211_is_data(hdr->frame_control) &&
2407 !ieee80211_is_nullfunc(hdr->frame_control) &&
2408 !ieee80211_has_pm(hdr->frame_control)) {
c46917bb
LR		 2409 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
2410 "while in PS mode\n");
dc8c4585
JM		 2411 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2412 }
2413 }
2414
9a23f9ca
JM		 2415 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2416 /*
2417 * We are using PS-Poll and mac80211 can request TX while in
2418 * power save mode. Need to wake up hardware for the TX to be
2419 * completed and if needed, also for RX of buffered frames.
2420 */
2421 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2422 ath9k_ps_wakeup(sc);
2423 ath9k_hw_setrxabort(sc->sc_ah, 0);
2424 if (ieee80211_is_pspoll(hdr->frame_control)) {
c46917bb
LR		 2425 ath_print(common, ATH_DBG_PS,
2426 "Sending PS-Poll to pick a buffered frame\n");
9a23f9ca
JM		 2427 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2428 } else {
c46917bb
LR		 2429 ath_print(common, ATH_DBG_PS,
2430 "Wake up to complete TX\n");
9a23f9ca
JM		 2431 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2432 }
2433 /*
2434 * The actual restore operation will happen only after
2435 * the sc_flags bit is cleared. We are just dropping
2436 * the ps_usecount here.
2437 */
2438 ath9k_ps_restore(sc);
2439 }
2440
528f0c6b 2441 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2442
8feceb67
VT		 2443 /*
2444 * As a temporary workaround, assign seq# here; this will likely need
2445 * to be cleaned up to work better with Beacon transmission and virtual
2446 * BSSes.
2447 */
2448 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2449 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2450 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2451 sc->tx.seq_no += 0x10;
8feceb67 2452 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2453 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2454 }
f078f209 2455
8feceb67
VT		 2456 /* Add the padding after the header if this is not already done */
2457 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2458 if (hdrlen & 3) {
2459 padsize = hdrlen % 4;
2460 if (skb_headroom(skb) < padsize)
2461 return -1;
2462 skb_push(skb, padsize);
2463 memmove(skb->data, skb->data + padsize, hdrlen);
2464 }
2465
528f0c6b
S		 2466 /* Check if a tx queue is available */
2467
2468 txctl.txq = ath_test_get_txq(sc, skb);
2469 if (!txctl.txq)
2470 goto exit;
2471
c46917bb 2472 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2473
c52f33d0 2474 if (ath_tx_start(hw, skb, &txctl) != 0) {
c46917bb 2475 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2476 goto exit;
8feceb67
VT		 2477 }
2478
528f0c6b
S		 2479 return 0;
2480exit:
2481 dev_kfree_skb_any(skb);
8feceb67 2482 return 0;
f078f209
LR		 2483}
2484
75d7839f
LR		 2485/*
2486 * Pause btcoex timer and bt duty cycle timer
2487 */
2488static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2489{
2490 struct ath_btcoex *btcoex = &sc->btcoex;
2491 struct ath_hw *ah = sc->sc_ah;
2492
2493 del_timer_sync(&btcoex->period_timer);
2494
2495 if (btcoex->hw_timer_enabled)
cd9bf689 2496 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
75d7839f
LR		 2497
2498 btcoex->hw_timer_enabled = false;
2499}
2500
8feceb67 2501static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2502{
bce048d7
JM		 2503 struct ath_wiphy *aphy = hw->priv;
2504 struct ath_softc *sc = aphy->sc;
af03abec 2505 struct ath_hw *ah = sc->sc_ah;
c46917bb 2506 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2507
4c483817
S		 2508 mutex_lock(&sc->mutex);
2509
9580a222
JM		 2510 aphy->state = ATH_WIPHY_INACTIVE;
2511
c94dbff7
LR		 2512 cancel_delayed_work_sync(&sc->ath_led_blink_work);
2513 cancel_delayed_work_sync(&sc->tx_complete_work);
2514
2515 if (!sc->num_sec_wiphy) {
2516 cancel_delayed_work_sync(&sc->wiphy_work);
2517 cancel_work_sync(&sc->chan_work);
2518 }
2519
9c84b797 2520 if (sc->sc_flags & SC_OP_INVALID) {
c46917bb 2521 ath_print(common, ATH_DBG_ANY, "Device not present\n");
4c483817 2522 mutex_unlock(&sc->mutex);
9c84b797
S		 2523 return;
2524 }
8feceb67 2525
9580a222
JM		 2526 if (ath9k_wiphy_started(sc)) {
2527 mutex_unlock(&sc->mutex);
2528 return; /* another wiphy still in use */
2529 }
2530
766ec4a9 2531 if (ah->btcoex_hw.enabled) {
af03abec 2532 ath9k_hw_btcoex_disable(ah);
766ec4a9 2533 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 2534 ath9k_btcoex_timer_pause(sc);
1773912b
VT		 2535 }
2536
ff37e337
S		 2537 /* make sure h/w will not generate any interrupt
2538 * before setting the invalid flag. */
af03abec 2539 ath9k_hw_set_interrupts(ah, 0);
ff37e337
S		 2540
2541 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2542 ath_drain_all_txq(sc, false);
ff37e337 2543 ath_stoprecv(sc);
af03abec 2544 ath9k_hw_phy_disable(ah);
ff37e337 2545 } else
b77f483f 2546 sc->rx.rxlink = NULL;
ff37e337 2547
ff37e337 2548 /* disable HAL and put h/w to sleep */
af03abec
LR		 2549 ath9k_hw_disable(ah);
2550 ath9k_hw_configpcipowersave(ah, 1, 1);
9ecdef4b 2551 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
ff37e337
S		 2552
2553 sc->sc_flags |= SC_OP_INVALID;
500c064d 2554
141b38b6
S		 2555 mutex_unlock(&sc->mutex);
2556
c46917bb 2557 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2558}
2559
8feceb67
VT		 2560static int ath9k_add_interface(struct ieee80211_hw *hw,
2561 struct ieee80211_if_init_conf *conf)
f078f209 2562{
bce048d7
JM		 2563 struct ath_wiphy *aphy = hw->priv;
2564 struct ath_softc *sc = aphy->sc;
c46917bb 2565 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
17d7904d 2566 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2567 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2568 int ret = 0;
8feceb67 2569
141b38b6
S		 2570 mutex_lock(&sc->mutex);
2571
8ca21f01
JM		 2572 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2573 sc->nvifs > 0) {
2574 ret = -ENOBUFS;
2575 goto out;
2576 }
2577
8feceb67 2578 switch (conf->type) {
05c914fe 2579 case NL80211_IFTYPE_STATION:
d97809db 2580 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2581 break;
05c914fe 2582 case NL80211_IFTYPE_ADHOC:
05c914fe 2583 case NL80211_IFTYPE_AP:
9cb5412b 2584 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2585 if (sc->nbcnvifs >= ATH_BCBUF) {
2586 ret = -ENOBUFS;
2587 goto out;
2588 }
9cb5412b 2589 ic_opmode = conf->type;
f078f209
LR		 2590 break;
2591 default:
c46917bb 2592 ath_print(common, ATH_DBG_FATAL,
04bd4638 2593 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2594 ret = -EOPNOTSUPP;
2595 goto out;
f078f209
LR		 2596 }
2597
c46917bb
LR		 2598 ath_print(common, ATH_DBG_CONFIG,
2599 "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2600
17d7904d 2601 /* Set the VIF opmode */
5640b08e
S		 2602 avp->av_opmode = ic_opmode;
2603 avp->av_bslot = -1;
2604
2c3db3d5 2605 sc->nvifs++;
8ca21f01
JM		 2606
2607 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2608 ath9k_set_bssid_mask(hw);
2609
2c3db3d5
JM		 2610 if (sc->nvifs > 1)
2611 goto out; /* skip global settings for secondary vif */
2612
b238e90e 2613 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2614 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2615 sc->sc_flags |= SC_OP_TSF_RESET;
2616 }
5640b08e 2617
5640b08e 2618 /* Set the device opmode */
2660b81a 2619 sc->sc_ah->opmode = ic_opmode;
5640b08e 2620
4e30ffa2
VN		 2621 /*
2622 * Enable MIB interrupts when there are hardware phy counters.
2623 * Note we only do this (at the moment) for station mode.
2624 */
4af9cf4f 2625 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2626 (conf->type == NL80211_IFTYPE_ADHOC) ||
2627 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
1aa8e847 2628 sc->imask |= ATH9K_INT_MIB;
4af9cf4f
S		 2629 sc->imask |= ATH9K_INT_TSFOOR;
2630 }
2631
17d7904d 2632 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2633
f38faa31
SB		 2634 if (conf->type == NL80211_IFTYPE_AP ||
2635 conf->type == NL80211_IFTYPE_ADHOC ||
2636 conf->type == NL80211_IFTYPE_MONITOR)
415f738e 2637 ath_start_ani(sc);
6f255425 2638
2c3db3d5 2639out:
141b38b6 2640 mutex_unlock(&sc->mutex);
2c3db3d5 2641 return ret;
f078f209
LR		 2642}
2643
8feceb67
VT		 2644static void ath9k_remove_interface(struct ieee80211_hw *hw,
2645 struct ieee80211_if_init_conf *conf)
f078f209 2646{
bce048d7
JM		 2647 struct ath_wiphy *aphy = hw->priv;
2648 struct ath_softc *sc = aphy->sc;
c46917bb 2649 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
17d7904d 2650 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2651 int i;
f078f209 2652
c46917bb 2653 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2654
141b38b6
S		 2655 mutex_lock(&sc->mutex);
2656
6f255425 2657 /* Stop ANI */
17d7904d 2658 del_timer_sync(&sc->ani.timer);
580f0b8a 2659
8feceb67 2660 /* Reclaim beacon resources */
9cb5412b
PE		 2661 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2662 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2663 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2664 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2665 ath_beacon_return(sc, avp);
580f0b8a 2666 }
f078f209 2667
8feceb67 2668 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2669
2c3db3d5
JM		 2670 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2671 if (sc->beacon.bslot[i] == conf->vif) {
2672 printk(KERN_DEBUG "%s: vif had allocated beacon "
2673 "slot\n", __func__);
2674 sc->beacon.bslot[i] = NULL;
c52f33d0 2675 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2676 }
2677 }
2678
17d7904d 2679 sc->nvifs--;
141b38b6
S		 2680
2681 mutex_unlock(&sc->mutex);
f078f209
LR		 2682}
2683
e8975581 2684static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2685{
bce048d7
JM		 2686 struct ath_wiphy *aphy = hw->priv;
2687 struct ath_softc *sc = aphy->sc;
c46917bb 2688 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
e8975581 2689 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2690 struct ath_hw *ah = sc->sc_ah;
194b7c13 2691 bool disable_radio;
f078f209 2692
aa33de09 2693 mutex_lock(&sc->mutex);
141b38b6 2694
194b7c13
LR		 2695 /*
2696 * Leave this as the first check because we need to turn on the
2697 * radio if it was disabled before prior to processing the rest
2698 * of the changes. Likewise we must only disable the radio towards
2699 * the end.
2700 */
64839170 2701 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
194b7c13
LR		 2702 bool enable_radio;
2703 bool all_wiphys_idle;
2704 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
64839170
LR		 2705
2706 spin_lock_bh(&sc->wiphy_lock);
2707 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
194b7c13
LR		 2708 ath9k_set_wiphy_idle(aphy, idle);
2709
2710 if (!idle && all_wiphys_idle)
2711 enable_radio = true;
2712
2713 /*
2714 * After we unlock here its possible another wiphy
2715 * can be re-renabled so to account for that we will
2716 * only disable the radio toward the end of this routine
2717 * if by then all wiphys are still idle.
2718 */
64839170
LR		 2719 spin_unlock_bh(&sc->wiphy_lock);
2720
194b7c13 2721 if (enable_radio) {
68a89116 2722 ath_radio_enable(sc, hw);
c46917bb
LR		 2723 ath_print(common, ATH_DBG_CONFIG,
2724 "not-idle: enabling radio\n");
64839170
LR		 2725 }
2726 }
2727
3cbb5dd7
VN		 2728 if (changed & IEEE80211_CONF_CHANGE_PS) {
2729 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2730 if (!(ah->caps.hw_caps &
2731 ATH9K_HW_CAP_AUTOSLEEP)) {
2732 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2733 sc->imask |= ATH9K_INT_TIM_TIMER;
2734 ath9k_hw_set_interrupts(sc->sc_ah,
2735 sc->imask);
2736 }
2737 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2738 }
96148326 2739 sc->ps_enabled = true;
3cbb5dd7 2740 } else {
96148326 2741 sc->ps_enabled = false;
9ecdef4b 2742 ath9k_setpower(sc, ATH9K_PM_AWAKE);
8782b41d
VN		 2743 if (!(ah->caps.hw_caps &
2744 ATH9K_HW_CAP_AUTOSLEEP)) {
2745 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca
JM		 2746 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2747 SC_OP_WAIT_FOR_CAB |
2748 SC_OP_WAIT_FOR_PSPOLL_DATA |
2749 SC_OP_WAIT_FOR_TX_ACK);
8782b41d
VN		 2750 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2751 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2752 ath9k_hw_set_interrupts(sc->sc_ah,
2753 sc->imask);
2754 }
3cbb5dd7
VN		 2755 }
2756 }
2757 }
2758
4797938c 2759 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2760 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2761 int pos = curchan->hw_value;
ae5eb026 2762
0e2dedf9
JM		 2763 aphy->chan_idx = pos;
2764 aphy->chan_is_ht = conf_is_ht(conf);
2765
8089cc47
JM		 2766 if (aphy->state == ATH_WIPHY_SCAN ||
2767 aphy->state == ATH_WIPHY_ACTIVE)
2768 ath9k_wiphy_pause_all_forced(sc, aphy);
2769 else {
2770 /*
2771 * Do not change operational channel based on a paused
2772 * wiphy changes.
2773 */
2774 goto skip_chan_change;
2775 }
0e2dedf9 2776
c46917bb
LR		 2777 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2778 curchan->center_freq);
f078f209 2779
5f8e077c 2780 /* XXX: remove me eventualy */
0e2dedf9 2781 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2782
ecf70441 2783 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2784
0e2dedf9 2785 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
c46917bb
LR		 2786 ath_print(common, ATH_DBG_FATAL,
2787 "Unable to set channel\n");
aa33de09 2788 mutex_unlock(&sc->mutex);
e11602b7
S		 2789 return -EINVAL;
2790 }
094d05dc 2791 }
f078f209 2792
8089cc47 2793skip_chan_change:
5c020dc6 2794 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2795 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2796
194b7c13
LR		 2797 spin_lock_bh(&sc->wiphy_lock);
2798 disable_radio = ath9k_all_wiphys_idle(sc);
2799 spin_unlock_bh(&sc->wiphy_lock);
2800
64839170 2801 if (disable_radio) {
c46917bb 2802 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
68a89116 2803 ath_radio_disable(sc, hw);
64839170
LR		 2804 }
2805
aa33de09 2806 mutex_unlock(&sc->mutex);
141b38b6 2807
f078f209
LR		 2808 return 0;
2809}
2810
8feceb67
VT		 2811#define SUPPORTED_FILTERS \
2812 (FIF_PROMISC_IN_BSS | \
2813 FIF_ALLMULTI | \
2814 FIF_CONTROL | \
af6a3fc7 2815 FIF_PSPOLL | \
8feceb67
VT		 2816 FIF_OTHER_BSS | \
2817 FIF_BCN_PRBRESP_PROMISC | \
2818 FIF_FCSFAIL)
c83be688 2819
8feceb67
VT		 2820/* FIXME: sc->sc_full_reset ? */
2821static void ath9k_configure_filter(struct ieee80211_hw *hw,
2822 unsigned int changed_flags,
2823 unsigned int *total_flags,
3ac64bee 2824 u64 multicast)
8feceb67 2825{
bce048d7
JM		 2826 struct ath_wiphy *aphy = hw->priv;
2827 struct ath_softc *sc = aphy->sc;
8feceb67 2828 u32 rfilt;
f078f209 2829
8feceb67
VT		 2830 changed_flags &= SUPPORTED_FILTERS;
2831 *total_flags &= SUPPORTED_FILTERS;
f078f209 2832
b77f483f 2833 sc->rx.rxfilter = *total_flags;
aa68aeaa 2834 ath9k_ps_wakeup(sc);
8feceb67
VT		 2835 rfilt = ath_calcrxfilter(sc);
2836 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 2837 ath9k_ps_restore(sc);
f078f209 2838
c46917bb
LR		 2839 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
2840 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 2841}
f078f209 2842
8feceb67
VT		 2843static void ath9k_sta_notify(struct ieee80211_hw *hw,
2844 struct ieee80211_vif *vif,
2845 enum sta_notify_cmd cmd,
17741cdc 2846 struct ieee80211_sta *sta)
8feceb67 2847{
bce048d7
JM		 2848 struct ath_wiphy *aphy = hw->priv;
2849 struct ath_softc *sc = aphy->sc;
f078f209 2850
8feceb67
VT		 2851 switch (cmd) {
2852 case STA_NOTIFY_ADD:
5640b08e 2853 ath_node_attach(sc, sta);
8feceb67
VT		 2854 break;
2855 case STA_NOTIFY_REMOVE:
b5aa9bf9 2856 ath_node_detach(sc, sta);
8feceb67
VT		 2857 break;
2858 default:
2859 break;
2860 }
f078f209
LR		 2861}
2862
141b38b6 2863static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2864 const struct ieee80211_tx_queue_params *params)
f078f209 2865{
bce048d7
JM		 2866 struct ath_wiphy *aphy = hw->priv;
2867 struct ath_softc *sc = aphy->sc;
c46917bb 2868 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67
VT		 2869 struct ath9k_tx_queue_info qi;
2870 int ret = 0, qnum;
f078f209 2871
8feceb67
VT		 2872 if (queue >= WME_NUM_AC)
2873 return 0;
f078f209 2874
141b38b6
S		 2875 mutex_lock(&sc->mutex);
2876
1ffb0610
S		 2877 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2878
8feceb67
VT		 2879 qi.tqi_aifs = params->aifs;
2880 qi.tqi_cwmin = params->cw_min;
2881 qi.tqi_cwmax = params->cw_max;
2882 qi.tqi_burstTime = params->txop;
2883 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2884
c46917bb
LR		 2885 ath_print(common, ATH_DBG_CONFIG,
2886 "Configure tx [queue/halq] [%d/%d], "
2887 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2888 queue, qnum, params->aifs, params->cw_min,
2889 params->cw_max, params->txop);
f078f209 2890
8feceb67
VT		 2891 ret = ath_txq_update(sc, qnum, &qi);
2892 if (ret)
c46917bb 2893 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2894
141b38b6
S		 2895 mutex_unlock(&sc->mutex);
2896
8feceb67
VT		 2897 return ret;
2898}
f078f209 2899
8feceb67
VT		 2900static int ath9k_set_key(struct ieee80211_hw *hw,
2901 enum set_key_cmd cmd,
dc822b5d
JB		 2902 struct ieee80211_vif *vif,
2903 struct ieee80211_sta *sta,
8feceb67
VT		 2904 struct ieee80211_key_conf *key)
2905{
bce048d7
JM		 2906 struct ath_wiphy *aphy = hw->priv;
2907 struct ath_softc *sc = aphy->sc;
c46917bb 2908 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 2909 int ret = 0;
f078f209 2910
b3bd89ce
JM		 2911 if (modparam_nohwcrypt)
2912 return -ENOSPC;
2913
141b38b6 2914 mutex_lock(&sc->mutex);
3cbb5dd7 2915 ath9k_ps_wakeup(sc);
c46917bb 2916 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2917
8feceb67
VT		 2918 switch (cmd) {
2919 case SET_KEY:
3f53dd64 2920 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2921 if (ret >= 0) {
2922 key->hw_key_idx = ret;
8feceb67
VT		 2923 /* push IV and Michael MIC generation to stack */
2924 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2925 if (key->alg == ALG_TKIP)
2926 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2927 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2928 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2929 ret = 0;
8feceb67
VT		 2930 }
2931 break;
2932 case DISABLE_KEY:
2933 ath_key_delete(sc, key);
8feceb67
VT		 2934 break;
2935 default:
2936 ret = -EINVAL;
2937 }
f078f209 2938
3cbb5dd7 2939 ath9k_ps_restore(sc);
141b38b6
S		 2940 mutex_unlock(&sc->mutex);
2941
8feceb67
VT		 2942 return ret;
2943}
f078f209 2944
8feceb67
VT		 2945static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2946 struct ieee80211_vif *vif,
2947 struct ieee80211_bss_conf *bss_conf,
2948 u32 changed)
2949{
bce048d7
JM		 2950 struct ath_wiphy *aphy = hw->priv;
2951 struct ath_softc *sc = aphy->sc;
2d0ddec5 2952 struct ath_hw *ah = sc->sc_ah;
1510718d 2953 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5
JB		 2954 struct ath_vif *avp = (void *)vif->drv_priv;
2955 u32 rfilt = 0;
2956 int error, i;
f078f209 2957
141b38b6
S		 2958 mutex_lock(&sc->mutex);
2959
2d0ddec5
JB		 2960 /*
2961 * TODO: Need to decide which hw opmode to use for
2962 * multi-interface cases
2963 * XXX: This belongs into add_interface!
2964 */
2965 if (vif->type == NL80211_IFTYPE_AP &&
2966 ah->opmode != NL80211_IFTYPE_AP) {
2967 ah->opmode = NL80211_IFTYPE_STATION;
2968 ath9k_hw_setopmode(ah);
1510718d
LR		 2969 memcpy(common->curbssid, common->macaddr, ETH_ALEN);
2970 common->curaid = 0;
f2b2143e 2971 ath9k_hw_write_associd(ah);
2d0ddec5
JB		 2972 /* Request full reset to get hw opmode changed properly */
2973 sc->sc_flags |= SC_OP_FULL_RESET;
2974 }
2975
2976 if ((changed & BSS_CHANGED_BSSID) &&
2977 !is_zero_ether_addr(bss_conf->bssid)) {
2978 switch (vif->type) {
2979 case NL80211_IFTYPE_STATION:
2980 case NL80211_IFTYPE_ADHOC:
2981 case NL80211_IFTYPE_MESH_POINT:
2982 /* Set BSSID */
1510718d 2983 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2d0ddec5 2984 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1510718d 2985 common->curaid = 0;
f2b2143e 2986 ath9k_hw_write_associd(ah);
2d0ddec5
JB		 2987
2988 /* Set aggregation protection mode parameters */
2989 sc->config.ath_aggr_prot = 0;
2990
c46917bb
LR		 2991 ath_print(common, ATH_DBG_CONFIG,
2992 "RX filter 0x%x bssid %pM aid 0x%x\n",
2993 rfilt, common->curbssid, common->curaid);
2d0ddec5
JB		 2994
2995 /* need to reconfigure the beacon */
2996 sc->sc_flags &= ~SC_OP_BEACONS ;
2997
2998 break;
2999 default:
3000 break;
3001 }
3002 }
3003
3004 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
3005 (vif->type == NL80211_IFTYPE_AP) ||
3006 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
3007 if ((changed & BSS_CHANGED_BEACON) ||
3008 (changed & BSS_CHANGED_BEACON_ENABLED &&
3009 bss_conf->enable_beacon)) {
3010 /*
3011 * Allocate and setup the beacon frame.
3012 *
3013 * Stop any previous beacon DMA. This may be
3014 * necessary, for example, when an ibss merge
3015 * causes reconfiguration; we may be called
3016 * with beacon transmission active.
3017 */
3018 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
3019
3020 error = ath_beacon_alloc(aphy, vif);
3021 if (!error)
3022 ath_beacon_config(sc, vif);
3023 }
3024 }
3025
3026 /* Check for WLAN_CAPABILITY_PRIVACY ? */
3027 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
3028 for (i = 0; i < IEEE80211_WEP_NKID; i++)
3029 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
3030 ath9k_hw_keysetmac(sc->sc_ah,
3031 (u16)i,
1510718d 3032 common->curbssid);
2d0ddec5
JB		 3033 }
3034
3035 /* Only legacy IBSS for now */
3036 if (vif->type == NL80211_IFTYPE_ADHOC)
3037 ath_update_chainmask(sc, 0);
3038
8feceb67 3039 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
c46917bb
LR		 3040 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
3041 bss_conf->use_short_preamble);
8feceb67
VT		 3042 if (bss_conf->use_short_preamble)
3043 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
3044 else
3045 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
3046 }
f078f209 3047
8feceb67 3048 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
c46917bb
LR		 3049 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
3050 bss_conf->use_cts_prot);
8feceb67
VT		 3051 if (bss_conf->use_cts_prot &&
3052 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
3053 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
3054 else
3055 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
3056 }
f078f209 3057
8feceb67 3058 if (changed & BSS_CHANGED_ASSOC) {
c46917bb 3059 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 3060 bss_conf->assoc);
5640b08e 3061 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 3062 }
141b38b6 3063
57c4d7b4
JB		 3064 /*
3065 * The HW TSF has to be reset when the beacon interval changes.
3066 * We set the flag here, and ath_beacon_config_ap() would take this
3067 * into account when it gets called through the subsequent
3068 * config_interface() call - with IFCC_BEACON in the changed field.
3069 */
3070
3071 if (changed & BSS_CHANGED_BEACON_INT) {
3072 sc->sc_flags |= SC_OP_TSF_RESET;
3073 sc->beacon_interval = bss_conf->beacon_int;
3074 }
3075
141b38b6 3076 mutex_unlock(&sc->mutex);
8feceb67 3077}
f078f209 3078
8feceb67
VT		 3079static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
3080{
3081 u64 tsf;
bce048d7
JM		 3082 struct ath_wiphy *aphy = hw->priv;
3083 struct ath_softc *sc = aphy->sc;
f078f209 3084
141b38b6
S		 3085 mutex_lock(&sc->mutex);
3086 tsf = ath9k_hw_gettsf64(sc->sc_ah);
3087 mutex_unlock(&sc->mutex);
f078f209 3088
8feceb67
VT		 3089 return tsf;
3090}
f078f209 3091
3b5d665b
AF		 3092static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3093{
bce048d7
JM		 3094 struct ath_wiphy *aphy = hw->priv;
3095 struct ath_softc *sc = aphy->sc;
3b5d665b 3096
141b38b6
S		 3097 mutex_lock(&sc->mutex);
3098 ath9k_hw_settsf64(sc->sc_ah, tsf);
3099 mutex_unlock(&sc->mutex);
3b5d665b
AF		 3100}
3101
8feceb67
VT		 3102static void ath9k_reset_tsf(struct ieee80211_hw *hw)
3103{
bce048d7
JM		 3104 struct ath_wiphy *aphy = hw->priv;
3105 struct ath_softc *sc = aphy->sc;
c83be688 3106
141b38b6 3107 mutex_lock(&sc->mutex);
21526d57
LR		 3108
3109 ath9k_ps_wakeup(sc);
141b38b6 3110 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR		 3111 ath9k_ps_restore(sc);
3112
141b38b6 3113 mutex_unlock(&sc->mutex);
8feceb67 3114}
f078f209 3115
8feceb67 3116static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 3117 enum ieee80211_ampdu_mlme_action action,
3118 struct ieee80211_sta *sta,
3119 u16 tid, u16 *ssn)
8feceb67 3120{
bce048d7
JM		 3121 struct ath_wiphy *aphy = hw->priv;
3122 struct ath_softc *sc = aphy->sc;
8feceb67 3123 int ret = 0;
f078f209 3124
8feceb67
VT		 3125 switch (action) {
3126 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 3127 if (!(sc->sc_flags & SC_OP_RXAGGR))
3128 ret = -ENOTSUPP;
8feceb67
VT		 3129 break;
3130 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 3131 break;
3132 case IEEE80211_AMPDU_TX_START:
f83da965
S		 3133 ath_tx_aggr_start(sc, sta, tid, ssn);
3134 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 3135 break;
3136 case IEEE80211_AMPDU_TX_STOP:
f83da965 3137 ath_tx_aggr_stop(sc, sta, tid);
17741cdc 3138 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 3139 break;
b1720231 3140 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 3141 ath_tx_aggr_resume(sc, sta, tid);
3142 break;
8feceb67 3143 default:
c46917bb
LR		 3144 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
3145 "Unknown AMPDU action\n");
8feceb67
VT		 3146 }
3147
3148 return ret;
f078f209
LR		 3149}
3150
0c98de65
S		 3151static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
3152{
bce048d7
JM		 3153 struct ath_wiphy *aphy = hw->priv;
3154 struct ath_softc *sc = aphy->sc;
0c98de65 3155
3d832611 3156 mutex_lock(&sc->mutex);
8089cc47
JM		 3157 if (ath9k_wiphy_scanning(sc)) {
3158 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
3159 "same time\n");
3160 /*
3161 * Do not allow the concurrent scanning state for now. This
3162 * could be improved with scanning control moved into ath9k.
3163 */
3d832611 3164 mutex_unlock(&sc->mutex);
8089cc47
JM		 3165 return;
3166 }
3167
3168 aphy->state = ATH_WIPHY_SCAN;
3169 ath9k_wiphy_pause_all_forced(sc, aphy);
3170
e5f0921a 3171 spin_lock_bh(&sc->ani_lock);
0c98de65 3172 sc->sc_flags |= SC_OP_SCANNING;
e5f0921a 3173 spin_unlock_bh(&sc->ani_lock);
3d832611 3174 mutex_unlock(&sc->mutex);
0c98de65
S		 3175}
3176
3177static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
3178{
bce048d7
JM		 3179 struct ath_wiphy *aphy = hw->priv;
3180 struct ath_softc *sc = aphy->sc;
0c98de65 3181
3d832611 3182 mutex_lock(&sc->mutex);
e5f0921a 3183 spin_lock_bh(&sc->ani_lock);
8089cc47 3184 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 3185 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 3186 sc->sc_flags |= SC_OP_FULL_RESET;
e5f0921a 3187 spin_unlock_bh(&sc->ani_lock);
d0bec342 3188 ath_beacon_config(sc, NULL);
3d832611 3189 mutex_unlock(&sc->mutex);
0c98de65
S		 3190}
3191
6baff7f9 3192struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 3193 .tx = ath9k_tx,
3194 .start = ath9k_start,
3195 .stop = ath9k_stop,
3196 .add_interface = ath9k_add_interface,
3197 .remove_interface = ath9k_remove_interface,
3198 .config = ath9k_config,
8feceb67 3199 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 3200 .sta_notify = ath9k_sta_notify,
3201 .conf_tx = ath9k_conf_tx,
8feceb67 3202 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 3203 .set_key = ath9k_set_key,
8feceb67 3204 .get_tsf = ath9k_get_tsf,
3b5d665b 3205 .set_tsf = ath9k_set_tsf,
8feceb67 3206 .reset_tsf = ath9k_reset_tsf,
4233df6b 3207 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 3208 .sw_scan_start = ath9k_sw_scan_start,
3209 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 3210 .rfkill_poll = ath9k_rfkill_poll_state,
8feceb67
VT		 3211};
3212
6baff7f9 3213static int __init ath9k_init(void)
f078f209 3214{
ca8a8560
VT		 3215 int error;
3216
ca8a8560
VT		 3217 /* Register rate control algorithm */
3218 error = ath_rate_control_register();
3219 if (error != 0) {
3220 printk(KERN_ERR
b51bb3cd
LR		 3221 "ath9k: Unable to register rate control "
3222 "algorithm: %d\n",
ca8a8560 3223 error);
6baff7f9 3224 goto err_out;
ca8a8560
VT		 3225 }
3226
19d8bc22
GJ		 3227 error = ath9k_debug_create_root();
3228 if (error) {
3229 printk(KERN_ERR
3230 "ath9k: Unable to create debugfs root: %d\n",
3231 error);
3232 goto err_rate_unregister;
3233 }
3234
6baff7f9
GJ		 3235 error = ath_pci_init();
3236 if (error < 0) {
f078f209 3237 printk(KERN_ERR
b51bb3cd 3238 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 3239 error = -ENODEV;
19d8bc22 3240 goto err_remove_root;
f078f209
LR		 3241 }
3242
09329d37
GJ		 3243 error = ath_ahb_init();
3244 if (error < 0) {
3245 error = -ENODEV;
3246 goto err_pci_exit;
3247 }
3248
f078f209 3249 return 0;
6baff7f9 3250
09329d37
GJ		 3251 err_pci_exit:
3252 ath_pci_exit();
3253
19d8bc22
GJ		 3254 err_remove_root:
3255 ath9k_debug_remove_root();
6baff7f9
GJ		 3256 err_rate_unregister:
3257 ath_rate_control_unregister();
3258 err_out:
3259 return error;
f078f209 3260}
6baff7f9 3261module_init(ath9k_init);
f078f209 3262
6baff7f9 3263static void __exit ath9k_exit(void)
f078f209 3264{
09329d37 3265 ath_ahb_exit();
6baff7f9 3266 ath_pci_exit();
19d8bc22 3267 ath9k_debug_remove_root();
ca8a8560 3268 ath_rate_control_unregister();
04bd4638 3269 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 3270}
6baff7f9 3271module_exit(ath9k_exit);
Linux kernel - Deliverables
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