ath9k: remove the virtual wiphy debugfs interface
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
af03abec 19#include "btcoex.h"
f078f209 20
ff37e337
S
21static void ath_update_txpow(struct ath_softc *sc)
22{
cbe61d8a 23 struct ath_hw *ah = sc->sc_ah;
ff37e337 24
17d7904d 25 if (sc->curtxpow != sc->config.txpowlimit) {
de40f316 26 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
ff37e337 27 /* read back in case value is clamped */
9cc3271f 28 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
ff37e337
S
29 }
30}
31
32static u8 parse_mpdudensity(u8 mpdudensity)
33{
34 /*
35 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
36 * 0 for no restriction
37 * 1 for 1/4 us
38 * 2 for 1/2 us
39 * 3 for 1 us
40 * 4 for 2 us
41 * 5 for 4 us
42 * 6 for 8 us
43 * 7 for 16 us
44 */
45 switch (mpdudensity) {
46 case 0:
47 return 0;
48 case 1:
49 case 2:
50 case 3:
51 /* Our lower layer calculations limit our precision to
52 1 microsecond */
53 return 1;
54 case 4:
55 return 2;
56 case 5:
57 return 4;
58 case 6:
59 return 8;
60 case 7:
61 return 16;
62 default:
63 return 0;
64 }
65}
66
82880a7c
VT
67static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
68 struct ieee80211_hw *hw)
69{
70 struct ieee80211_channel *curchan = hw->conf.channel;
71 struct ath9k_channel *channel;
72 u8 chan_idx;
73
74 chan_idx = curchan->hw_value;
75 channel = &sc->sc_ah->channels[chan_idx];
76 ath9k_update_ichannel(sc, hw, channel);
77 return channel;
78}
79
55624204 80bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
81{
82 unsigned long flags;
83 bool ret;
84
9ecdef4b
LR
85 spin_lock_irqsave(&sc->sc_pm_lock, flags);
86 ret = ath9k_hw_setpower(sc->sc_ah, mode);
87 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
88
89 return ret;
90}
91
a91d75ae
LR
92void ath9k_ps_wakeup(struct ath_softc *sc)
93{
898c914a 94 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 95 unsigned long flags;
fbb078fc 96 enum ath9k_power_mode power_mode;
a91d75ae
LR
97
98 spin_lock_irqsave(&sc->sc_pm_lock, flags);
99 if (++sc->ps_usecount != 1)
100 goto unlock;
101
fbb078fc 102 power_mode = sc->sc_ah->power_mode;
9ecdef4b 103 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 104
898c914a
FF
105 /*
106 * While the hardware is asleep, the cycle counters contain no
107 * useful data. Better clear them now so that they don't mess up
108 * survey data results.
109 */
fbb078fc
FF
110 if (power_mode != ATH9K_PM_AWAKE) {
111 spin_lock(&common->cc_lock);
112 ath_hw_cycle_counters_update(common);
113 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
114 spin_unlock(&common->cc_lock);
115 }
898c914a 116
a91d75ae
LR
117 unlock:
118 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
119}
120
121void ath9k_ps_restore(struct ath_softc *sc)
122{
898c914a 123 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae
LR
124 unsigned long flags;
125
126 spin_lock_irqsave(&sc->sc_pm_lock, flags);
127 if (--sc->ps_usecount != 0)
128 goto unlock;
129
898c914a
FF
130 spin_lock(&common->cc_lock);
131 ath_hw_cycle_counters_update(common);
132 spin_unlock(&common->cc_lock);
133
1dbfd9d4
VN
134 if (sc->ps_idle)
135 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
136 else if (sc->ps_enabled &&
137 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1b04b930
S
138 PS_WAIT_FOR_CAB |
139 PS_WAIT_FOR_PSPOLL_DATA |
140 PS_WAIT_FOR_TX_ACK)))
9ecdef4b 141 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR
142
143 unlock:
144 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
145}
146
5ee08656
FF
147static void ath_start_ani(struct ath_common *common)
148{
149 struct ath_hw *ah = common->ah;
150 unsigned long timestamp = jiffies_to_msecs(jiffies);
151 struct ath_softc *sc = (struct ath_softc *) common->priv;
152
153 if (!(sc->sc_flags & SC_OP_ANI_RUN))
154 return;
155
156 if (sc->sc_flags & SC_OP_OFFCHANNEL)
157 return;
158
159 common->ani.longcal_timer = timestamp;
160 common->ani.shortcal_timer = timestamp;
161 common->ani.checkani_timer = timestamp;
162
163 mod_timer(&common->ani.timer,
164 jiffies +
165 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
166}
167
3430098a
FF
168static void ath_update_survey_nf(struct ath_softc *sc, int channel)
169{
170 struct ath_hw *ah = sc->sc_ah;
171 struct ath9k_channel *chan = &ah->channels[channel];
172 struct survey_info *survey = &sc->survey[channel];
173
174 if (chan->noisefloor) {
175 survey->filled |= SURVEY_INFO_NOISE_DBM;
176 survey->noise = chan->noisefloor;
177 }
178}
179
180static void ath_update_survey_stats(struct ath_softc *sc)
181{
182 struct ath_hw *ah = sc->sc_ah;
183 struct ath_common *common = ath9k_hw_common(ah);
184 int pos = ah->curchan - &ah->channels[0];
185 struct survey_info *survey = &sc->survey[pos];
186 struct ath_cycle_counters *cc = &common->cc_survey;
187 unsigned int div = common->clockrate * 1000;
188
0845735e
FF
189 if (!ah->curchan)
190 return;
191
898c914a
FF
192 if (ah->power_mode == ATH9K_PM_AWAKE)
193 ath_hw_cycle_counters_update(common);
3430098a
FF
194
195 if (cc->cycles > 0) {
196 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
197 SURVEY_INFO_CHANNEL_TIME_BUSY |
198 SURVEY_INFO_CHANNEL_TIME_RX |
199 SURVEY_INFO_CHANNEL_TIME_TX;
200 survey->channel_time += cc->cycles / div;
201 survey->channel_time_busy += cc->rx_busy / div;
202 survey->channel_time_rx += cc->rx_frame / div;
203 survey->channel_time_tx += cc->tx_frame / div;
204 }
205 memset(cc, 0, sizeof(*cc));
206
207 ath_update_survey_nf(sc, pos);
208}
209
ff37e337
S
210/*
211 * Set/change channels. If the channel is really being changed, it's done
212 * by reseting the chip. To accomplish this we must first cleanup any pending
213 * DMA, then restart stuff.
214*/
0e2dedf9
JM
215int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
216 struct ath9k_channel *hchan)
ff37e337 217{
20bd2a09 218 struct ath_wiphy *aphy = hw->priv;
cbe61d8a 219 struct ath_hw *ah = sc->sc_ah;
c46917bb 220 struct ath_common *common = ath9k_hw_common(ah);
25c56eec 221 struct ieee80211_conf *conf = &common->hw->conf;
ff37e337 222 bool fastcc = true, stopped;
ae8d2858 223 struct ieee80211_channel *channel = hw->conf.channel;
20bd2a09 224 struct ath9k_hw_cal_data *caldata = NULL;
ae8d2858 225 int r;
ff37e337
S
226
227 if (sc->sc_flags & SC_OP_INVALID)
228 return -EIO;
229
5ee08656
FF
230 del_timer_sync(&common->ani.timer);
231 cancel_work_sync(&sc->paprd_work);
232 cancel_work_sync(&sc->hw_check_work);
233 cancel_delayed_work_sync(&sc->tx_complete_work);
234
3cbb5dd7
VN
235 ath9k_ps_wakeup(sc);
236
6a6733f2
LR
237 spin_lock_bh(&sc->sc_pcu_lock);
238
c0d7c7af
LR
239 /*
240 * This is only performed if the channel settings have
241 * actually changed.
242 *
243 * To switch channels clear any pending DMA operations;
244 * wait long enough for the RX fifo to drain, reset the
245 * hardware at the new frequency, and then re-enable
246 * the relevant bits of the h/w.
247 */
4df3071e 248 ath9k_hw_disable_interrupts(ah);
080e1a25 249 stopped = ath_drain_all_txq(sc, false);
5e848f78 250
080e1a25
FF
251 if (!ath_stoprecv(sc))
252 stopped = false;
ff37e337 253
8b3f4616
FF
254 if (!ath9k_hw_check_alive(ah))
255 stopped = false;
256
c0d7c7af
LR
257 /* XXX: do not flush receive queue here. We don't want
258 * to flush data frames already in queue because of
259 * changing channel. */
ff37e337 260
5ee08656 261 if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
c0d7c7af
LR
262 fastcc = false;
263
20bd2a09
FF
264 if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
265 caldata = &aphy->caldata;
266
226afe68
JP
267 ath_dbg(common, ATH_DBG_CONFIG,
268 "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
269 sc->sc_ah->curchan->channel,
270 channel->center_freq, conf_is_ht40(conf),
271 fastcc);
ff37e337 272
20bd2a09 273 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
c0d7c7af 274 if (r) {
3800276a
JP
275 ath_err(common,
276 "Unable to reset channel (%u MHz), reset status %d\n",
277 channel->center_freq, r);
3989279c 278 goto ps_restore;
ff37e337 279 }
c0d7c7af 280
c0d7c7af 281 if (ath_startrecv(sc) != 0) {
3800276a 282 ath_err(common, "Unable to restart recv logic\n");
3989279c
GJ
283 r = -EIO;
284 goto ps_restore;
c0d7c7af
LR
285 }
286
c0d7c7af 287 ath_update_txpow(sc);
3069168c 288 ath9k_hw_set_interrupts(ah, ah->imask);
3989279c 289
48a6a468 290 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
1186488b
RM
291 if (sc->sc_flags & SC_OP_BEACONS)
292 ath_beacon_config(sc, NULL);
5ee08656 293 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
48a6a468 294 ath_start_ani(common);
5ee08656
FF
295 }
296
3989279c 297 ps_restore:
92460412
FF
298 ieee80211_wake_queues(hw);
299
6a6733f2
LR
300 spin_unlock_bh(&sc->sc_pcu_lock);
301
3cbb5dd7 302 ath9k_ps_restore(sc);
3989279c 303 return r;
ff37e337
S
304}
305
9f42c2b6
FF
306static void ath_paprd_activate(struct ath_softc *sc)
307{
308 struct ath_hw *ah = sc->sc_ah;
20bd2a09 309 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 310 struct ath_common *common = ath9k_hw_common(ah);
9f42c2b6
FF
311 int chain;
312
20bd2a09 313 if (!caldata || !caldata->paprd_done)
9f42c2b6
FF
314 return;
315
316 ath9k_ps_wakeup(sc);
ddfef792 317 ar9003_paprd_enable(ah, false);
9f42c2b6 318 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
9094537c 319 if (!(common->tx_chainmask & BIT(chain)))
9f42c2b6
FF
320 continue;
321
20bd2a09 322 ar9003_paprd_populate_single_table(ah, caldata, chain);
9f42c2b6
FF
323 }
324
325 ar9003_paprd_enable(ah, true);
326 ath9k_ps_restore(sc);
327}
328
7607cbe2
FF
329static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
330{
331 struct ieee80211_hw *hw = sc->hw;
332 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
333 struct ath_tx_control txctl;
334 int time_left;
335
336 memset(&txctl, 0, sizeof(txctl));
337 txctl.txq = sc->tx.txq_map[WME_AC_BE];
338
339 memset(tx_info, 0, sizeof(*tx_info));
340 tx_info->band = hw->conf.channel->band;
341 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
342 tx_info->control.rates[0].idx = 0;
343 tx_info->control.rates[0].count = 1;
344 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
345 tx_info->control.rates[1].idx = -1;
346
347 init_completion(&sc->paprd_complete);
348 sc->paprd_pending = true;
349 txctl.paprd = BIT(chain);
350 if (ath_tx_start(hw, skb, &txctl) != 0)
351 return false;
352
353 time_left = wait_for_completion_timeout(&sc->paprd_complete,
354 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
355 sc->paprd_pending = false;
356
357 if (!time_left)
358 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE,
359 "Timeout waiting for paprd training on TX chain %d\n",
360 chain);
361
362 return !!time_left;
363}
364
9f42c2b6
FF
365void ath_paprd_calibrate(struct work_struct *work)
366{
367 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
368 struct ieee80211_hw *hw = sc->hw;
369 struct ath_hw *ah = sc->sc_ah;
370 struct ieee80211_hdr *hdr;
371 struct sk_buff *skb = NULL;
20bd2a09 372 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 373 struct ath_common *common = ath9k_hw_common(ah);
066dae93 374 int ftype;
9f42c2b6
FF
375 int chain_ok = 0;
376 int chain;
377 int len = 1800;
9f42c2b6 378
20bd2a09
FF
379 if (!caldata)
380 return;
381
1bf38661
FF
382 if (ar9003_paprd_init_table(ah) < 0)
383 return;
384
9f42c2b6
FF
385 skb = alloc_skb(len, GFP_KERNEL);
386 if (!skb)
387 return;
388
9f42c2b6
FF
389 skb_put(skb, len);
390 memset(skb->data, 0, len);
391 hdr = (struct ieee80211_hdr *)skb->data;
392 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
393 hdr->frame_control = cpu_to_le16(ftype);
a3d3da14 394 hdr->duration_id = cpu_to_le16(10);
9f42c2b6
FF
395 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
396 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
397 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
398
47399f1a 399 ath9k_ps_wakeup(sc);
9f42c2b6 400 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
9094537c 401 if (!(common->tx_chainmask & BIT(chain)))
9f42c2b6
FF
402 continue;
403
404 chain_ok = 0;
9f42c2b6 405
7607cbe2
FF
406 ath_dbg(common, ATH_DBG_CALIBRATE,
407 "Sending PAPRD frame for thermal measurement "
408 "on chain %d\n", chain);
409 if (!ath_paprd_send_frame(sc, skb, chain))
410 goto fail_paprd;
9f42c2b6 411
9f42c2b6 412 ar9003_paprd_setup_gain_table(ah, chain);
9f42c2b6 413
7607cbe2
FF
414 ath_dbg(common, ATH_DBG_CALIBRATE,
415 "Sending PAPRD training frame on chain %d\n", chain);
416 if (!ath_paprd_send_frame(sc, skb, chain))
ca369eb4 417 goto fail_paprd;
9f42c2b6
FF
418
419 if (!ar9003_paprd_is_done(ah))
420 break;
421
20bd2a09 422 if (ar9003_paprd_create_curve(ah, caldata, chain) != 0)
9f42c2b6
FF
423 break;
424
425 chain_ok = 1;
426 }
427 kfree_skb(skb);
428
429 if (chain_ok) {
20bd2a09 430 caldata->paprd_done = true;
9f42c2b6
FF
431 ath_paprd_activate(sc);
432 }
433
ca369eb4 434fail_paprd:
9f42c2b6
FF
435 ath9k_ps_restore(sc);
436}
437
ff37e337
S
438/*
439 * This routine performs the periodic noise floor calibration function
440 * that is used to adjust and optimize the chip performance. This
441 * takes environmental changes (location, temperature) into account.
442 * When the task is complete, it reschedules itself depending on the
443 * appropriate interval that was calculated.
444 */
55624204 445void ath_ani_calibrate(unsigned long data)
ff37e337 446{
20977d3e
S
447 struct ath_softc *sc = (struct ath_softc *)data;
448 struct ath_hw *ah = sc->sc_ah;
c46917bb 449 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
450 bool longcal = false;
451 bool shortcal = false;
452 bool aniflag = false;
453 unsigned int timestamp = jiffies_to_msecs(jiffies);
6044474e 454 u32 cal_interval, short_cal_interval, long_cal_interval;
b5bfc568 455 unsigned long flags;
6044474e
FF
456
457 if (ah->caldata && ah->caldata->nfcal_interference)
458 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
459 else
460 long_cal_interval = ATH_LONG_CALINTERVAL;
ff37e337 461
20977d3e
S
462 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
463 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 464
1ffc1c61
JM
465 /* Only calibrate if awake */
466 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
467 goto set_timer;
468
469 ath9k_ps_wakeup(sc);
470
ff37e337 471 /* Long calibration runs independently of short calibration. */
6044474e 472 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
ff37e337 473 longcal = true;
226afe68 474 ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
3d536acf 475 common->ani.longcal_timer = timestamp;
ff37e337
S
476 }
477
17d7904d 478 /* Short calibration applies only while caldone is false */
3d536acf
LR
479 if (!common->ani.caldone) {
480 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 481 shortcal = true;
226afe68
JP
482 ath_dbg(common, ATH_DBG_ANI,
483 "shortcal @%lu\n", jiffies);
3d536acf
LR
484 common->ani.shortcal_timer = timestamp;
485 common->ani.resetcal_timer = timestamp;
ff37e337
S
486 }
487 } else {
3d536acf 488 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 489 ATH_RESTART_CALINTERVAL) {
3d536acf
LR
490 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
491 if (common->ani.caldone)
492 common->ani.resetcal_timer = timestamp;
ff37e337
S
493 }
494 }
495
496 /* Verify whether we must check ANI */
e36b27af
LR
497 if ((timestamp - common->ani.checkani_timer) >=
498 ah->config.ani_poll_interval) {
ff37e337 499 aniflag = true;
3d536acf 500 common->ani.checkani_timer = timestamp;
ff37e337
S
501 }
502
503 /* Skip all processing if there's nothing to do. */
504 if (longcal || shortcal || aniflag) {
505 /* Call ANI routine if necessary */
b5bfc568
FF
506 if (aniflag) {
507 spin_lock_irqsave(&common->cc_lock, flags);
22e66a4c 508 ath9k_hw_ani_monitor(ah, ah->curchan);
3430098a 509 ath_update_survey_stats(sc);
b5bfc568
FF
510 spin_unlock_irqrestore(&common->cc_lock, flags);
511 }
ff37e337
S
512
513 /* Perform calibration if necessary */
514 if (longcal || shortcal) {
3d536acf 515 common->ani.caldone =
43c27613
LR
516 ath9k_hw_calibrate(ah,
517 ah->curchan,
518 common->rx_chainmask,
519 longcal);
ff37e337
S
520 }
521 }
522
1ffc1c61
JM
523 ath9k_ps_restore(sc);
524
20977d3e 525set_timer:
ff37e337
S
526 /*
527 * Set timer interval based on previous results.
528 * The interval must be the shortest necessary to satisfy ANI,
529 * short calibration and long calibration.
530 */
aac9207e 531 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 532 if (sc->sc_ah->config.enable_ani)
e36b27af
LR
533 cal_interval = min(cal_interval,
534 (u32)ah->config.ani_poll_interval);
3d536acf 535 if (!common->ani.caldone)
20977d3e 536 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 537
3d536acf 538 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
20bd2a09
FF
539 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
540 if (!ah->caldata->paprd_done)
9f42c2b6 541 ieee80211_queue_work(sc->hw, &sc->paprd_work);
45ef6a0b 542 else if (!ah->paprd_table_write_done)
9f42c2b6
FF
543 ath_paprd_activate(sc);
544 }
ff37e337
S
545}
546
ff37e337
S
547static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
548{
549 struct ath_node *an;
ea066d5a 550 struct ath_hw *ah = sc->sc_ah;
ff37e337
S
551 an = (struct ath_node *)sta->drv_priv;
552
7f010c93
BG
553#ifdef CONFIG_ATH9K_DEBUGFS
554 spin_lock(&sc->nodes_lock);
555 list_add(&an->list, &sc->nodes);
556 spin_unlock(&sc->nodes_lock);
557 an->sta = sta;
558#endif
ea066d5a
MSS
559 if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM)
560 sc->sc_flags |= SC_OP_ENABLE_APM;
561
87792efc 562 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 563 ath_tx_node_init(sc, an);
9e98ac65 564 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S
565 sta->ht_cap.ampdu_factor);
566 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
567 }
ff37e337
S
568}
569
570static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
571{
572 struct ath_node *an = (struct ath_node *)sta->drv_priv;
573
7f010c93
BG
574#ifdef CONFIG_ATH9K_DEBUGFS
575 spin_lock(&sc->nodes_lock);
576 list_del(&an->list);
577 spin_unlock(&sc->nodes_lock);
578 an->sta = NULL;
579#endif
580
ff37e337
S
581 if (sc->sc_flags & SC_OP_TXAGGR)
582 ath_tx_node_cleanup(sc, an);
583}
584
347809fc
FF
585void ath_hw_check(struct work_struct *work)
586{
587 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
588 int i;
589
590 ath9k_ps_wakeup(sc);
591
592 for (i = 0; i < 3; i++) {
593 if (ath9k_hw_check_alive(sc->sc_ah))
594 goto out;
595
596 msleep(1);
597 }
fac6b6a0 598 ath_reset(sc, true);
347809fc
FF
599
600out:
601 ath9k_ps_restore(sc);
602}
603
55624204 604void ath9k_tasklet(unsigned long data)
ff37e337
S
605{
606 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 607 struct ath_hw *ah = sc->sc_ah;
c46917bb 608 struct ath_common *common = ath9k_hw_common(ah);
af03abec 609
17d7904d 610 u32 status = sc->intrstatus;
b5c80475 611 u32 rxmask;
ff37e337 612
153e080d
VT
613 ath9k_ps_wakeup(sc);
614
347809fc 615 if (status & ATH9K_INT_FATAL) {
fac6b6a0 616 ath_reset(sc, true);
153e080d 617 ath9k_ps_restore(sc);
ff37e337 618 return;
063d8be3 619 }
ff37e337 620
52671e43 621 spin_lock(&sc->sc_pcu_lock);
6a6733f2 622
8b3f4616
FF
623 /*
624 * Only run the baseband hang check if beacons stop working in AP or
625 * IBSS mode, because it has a high false positive rate. For station
626 * mode it should not be necessary, since the upper layers will detect
627 * this through a beacon miss automatically and the following channel
628 * change will trigger a hardware reset anyway
629 */
630 if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
631 !ath9k_hw_check_alive(ah))
347809fc
FF
632 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
633
b5c80475
FF
634 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
635 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
636 ATH9K_INT_RXORN);
637 else
638 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
639
640 if (status & rxmask) {
b5c80475
FF
641 /* Check for high priority Rx first */
642 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
643 (status & ATH9K_INT_RXHP))
644 ath_rx_tasklet(sc, 0, true);
645
646 ath_rx_tasklet(sc, 0, false);
ff37e337
S
647 }
648
e5003249
VT
649 if (status & ATH9K_INT_TX) {
650 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
651 ath_tx_edma_tasklet(sc);
652 else
653 ath_tx_tasklet(sc);
654 }
063d8be3 655
96148326 656 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM
657 /*
658 * TSF sync does not look correct; remain awake to sync with
659 * the next Beacon.
660 */
226afe68
JP
661 ath_dbg(common, ATH_DBG_PS,
662 "TSFOOR - Sync with next Beacon\n");
1b04b930 663 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
54ce846e
JM
664 }
665
766ec4a9 666 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT
667 if (status & ATH9K_INT_GENTIMER)
668 ath_gen_timer_isr(sc->sc_ah);
669
ff37e337 670 /* re-enable hardware interrupt */
4df3071e 671 ath9k_hw_enable_interrupts(ah);
6a6733f2 672
52671e43 673 spin_unlock(&sc->sc_pcu_lock);
153e080d 674 ath9k_ps_restore(sc);
ff37e337
S
675}
676
6baff7f9 677irqreturn_t ath_isr(int irq, void *dev)
ff37e337 678{
063d8be3
S
679#define SCHED_INTR ( \
680 ATH9K_INT_FATAL | \
681 ATH9K_INT_RXORN | \
682 ATH9K_INT_RXEOL | \
683 ATH9K_INT_RX | \
b5c80475
FF
684 ATH9K_INT_RXLP | \
685 ATH9K_INT_RXHP | \
063d8be3
S
686 ATH9K_INT_TX | \
687 ATH9K_INT_BMISS | \
688 ATH9K_INT_CST | \
ebb8e1d7
VT
689 ATH9K_INT_TSFOOR | \
690 ATH9K_INT_GENTIMER)
063d8be3 691
ff37e337 692 struct ath_softc *sc = dev;
cbe61d8a 693 struct ath_hw *ah = sc->sc_ah;
b5bfc568 694 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
695 enum ath9k_int status;
696 bool sched = false;
697
063d8be3
S
698 /*
699 * The hardware is not ready/present, don't
700 * touch anything. Note this can happen early
701 * on if the IRQ is shared.
702 */
703 if (sc->sc_flags & SC_OP_INVALID)
704 return IRQ_NONE;
ff37e337 705
063d8be3
S
706
707 /* shared irq, not for us */
708
153e080d 709 if (!ath9k_hw_intrpend(ah))
063d8be3 710 return IRQ_NONE;
063d8be3
S
711
712 /*
713 * Figure out the reason(s) for the interrupt. Note
714 * that the hal returns a pseudo-ISR that may include
715 * bits we haven't explicitly enabled so we mask the
716 * value to insure we only process bits we requested.
717 */
718 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 719 status &= ah->imask; /* discard unasked-for bits */
ff37e337 720
063d8be3
S
721 /*
722 * If there are no status bits set, then this interrupt was not
723 * for me (should have been caught above).
724 */
153e080d 725 if (!status)
063d8be3 726 return IRQ_NONE;
ff37e337 727
063d8be3
S
728 /* Cache the status */
729 sc->intrstatus = status;
730
731 if (status & SCHED_INTR)
732 sched = true;
733
734 /*
735 * If a FATAL or RXORN interrupt is received, we have to reset the
736 * chip immediately.
737 */
b5c80475
FF
738 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
739 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S
740 goto chip_reset;
741
08578b8f
LR
742 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
743 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF
744
745 spin_lock(&common->cc_lock);
746 ath_hw_cycle_counters_update(common);
08578b8f 747 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF
748 spin_unlock(&common->cc_lock);
749
08578b8f
LR
750 goto chip_reset;
751 }
752
063d8be3
S
753 if (status & ATH9K_INT_SWBA)
754 tasklet_schedule(&sc->bcon_tasklet);
755
756 if (status & ATH9K_INT_TXURN)
757 ath9k_hw_updatetxtriglevel(ah, true);
758
b5c80475
FF
759 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
760 if (status & ATH9K_INT_RXEOL) {
761 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
762 ath9k_hw_set_interrupts(ah, ah->imask);
763 }
764 }
765
063d8be3 766 if (status & ATH9K_INT_MIB) {
ff37e337 767 /*
063d8be3
S
768 * Disable interrupts until we service the MIB
769 * interrupt; otherwise it will continue to
770 * fire.
ff37e337 771 */
4df3071e 772 ath9k_hw_disable_interrupts(ah);
063d8be3
S
773 /*
774 * Let the hal handle the event. We assume
775 * it will clear whatever condition caused
776 * the interrupt.
777 */
88eac2da 778 spin_lock(&common->cc_lock);
bfc472bb 779 ath9k_hw_proc_mib_event(ah);
88eac2da 780 spin_unlock(&common->cc_lock);
4df3071e 781 ath9k_hw_enable_interrupts(ah);
063d8be3 782 }
ff37e337 783
153e080d
VT
784 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
785 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR
786 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
787 goto chip_reset;
063d8be3
S
788 /* Clear RxAbort bit so that we can
789 * receive frames */
9ecdef4b 790 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 791 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 792 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 793 }
063d8be3
S
794
795chip_reset:
ff37e337 796
817e11de
S
797 ath_debug_stat_interrupt(sc, status);
798
ff37e337 799 if (sched) {
4df3071e
FF
800 /* turn off every interrupt */
801 ath9k_hw_disable_interrupts(ah);
ff37e337
S
802 tasklet_schedule(&sc->intr_tq);
803 }
804
805 return IRQ_HANDLED;
063d8be3
S
806
807#undef SCHED_INTR
ff37e337
S
808}
809
f078f209 810static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 811 struct ieee80211_channel *chan,
094d05dc 812 enum nl80211_channel_type channel_type)
f078f209
LR
813{
814 u32 chanmode = 0;
f078f209
LR
815
816 switch (chan->band) {
817 case IEEE80211_BAND_2GHZ:
094d05dc
S
818 switch(channel_type) {
819 case NL80211_CHAN_NO_HT:
820 case NL80211_CHAN_HT20:
f078f209 821 chanmode = CHANNEL_G_HT20;
094d05dc
S
822 break;
823 case NL80211_CHAN_HT40PLUS:
f078f209 824 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S
825 break;
826 case NL80211_CHAN_HT40MINUS:
f078f209 827 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S
828 break;
829 }
f078f209
LR
830 break;
831 case IEEE80211_BAND_5GHZ:
094d05dc
S
832 switch(channel_type) {
833 case NL80211_CHAN_NO_HT:
834 case NL80211_CHAN_HT20:
f078f209 835 chanmode = CHANNEL_A_HT20;
094d05dc
S
836 break;
837 case NL80211_CHAN_HT40PLUS:
f078f209 838 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S
839 break;
840 case NL80211_CHAN_HT40MINUS:
f078f209 841 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S
842 break;
843 }
f078f209
LR
844 break;
845 default:
846 break;
847 }
848
849 return chanmode;
850}
851
8feceb67 852static void ath9k_bss_assoc_info(struct ath_softc *sc,
9fa23e17 853 struct ieee80211_hw *hw,
5640b08e 854 struct ieee80211_vif *vif,
8feceb67 855 struct ieee80211_bss_conf *bss_conf)
f078f209 856{
9fa23e17 857 struct ath_wiphy *aphy = hw->priv;
f2b2143e 858 struct ath_hw *ah = sc->sc_ah;
1510718d 859 struct ath_common *common = ath9k_hw_common(ah);
f078f209 860
8feceb67 861 if (bss_conf->assoc) {
226afe68
JP
862 ath_dbg(common, ATH_DBG_CONFIG,
863 "Bss Info ASSOC %d, bssid: %pM\n",
864 bss_conf->aid, common->curbssid);
f078f209 865
8feceb67 866 /* New association, store aid */
1510718d 867 common->curaid = bss_conf->aid;
f2b2143e 868 ath9k_hw_write_associd(ah);
2664f201
SB
869
870 /*
871 * Request a re-configuration of Beacon related timers
872 * on the receipt of the first Beacon frame (i.e.,
873 * after time sync with the AP).
874 */
1b04b930 875 sc->ps_flags |= PS_BEACON_SYNC;
f078f209 876
8feceb67 877 /* Configure the beacon */
2c3db3d5 878 ath_beacon_config(sc, vif);
f078f209 879
8feceb67 880 /* Reset rssi stats */
9fa23e17 881 aphy->last_rssi = ATH_RSSI_DUMMY_MARKER;
22e66a4c 882 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 883
6c3118e2 884 sc->sc_flags |= SC_OP_ANI_RUN;
3d536acf 885 ath_start_ani(common);
8feceb67 886 } else {
226afe68 887 ath_dbg(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1510718d 888 common->curaid = 0;
f38faa31 889 /* Stop ANI */
6c3118e2 890 sc->sc_flags &= ~SC_OP_ANI_RUN;
3d536acf 891 del_timer_sync(&common->ani.timer);
f078f209 892 }
8feceb67 893}
f078f209 894
68a89116 895void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 896{
cbe61d8a 897 struct ath_hw *ah = sc->sc_ah;
c46917bb 898 struct ath_common *common = ath9k_hw_common(ah);
68a89116 899 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 900 int r;
500c064d 901
3cbb5dd7 902 ath9k_ps_wakeup(sc);
6a6733f2
LR
903 spin_lock_bh(&sc->sc_pcu_lock);
904
93b1b37f 905 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 906
159cd468
VT
907 if (!ah->curchan)
908 ah->curchan = ath_get_curchannel(sc, sc->hw);
909
20bd2a09 910 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 911 if (r) {
3800276a
JP
912 ath_err(common,
913 "Unable to reset channel (%u MHz), reset status %d\n",
914 channel->center_freq, r);
500c064d 915 }
500c064d
VT
916
917 ath_update_txpow(sc);
918 if (ath_startrecv(sc) != 0) {
3800276a 919 ath_err(common, "Unable to restart recv logic\n");
c2731b81 920 goto out;
500c064d 921 }
500c064d 922 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 923 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT
924
925 /* Re-Enable interrupts */
3069168c 926 ath9k_hw_set_interrupts(ah, ah->imask);
500c064d
VT
927
928 /* Enable LED */
08fc5c1b 929 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 930 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 931 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 932
68a89116 933 ieee80211_wake_queues(hw);
c2731b81 934out:
6a6733f2
LR
935 spin_unlock_bh(&sc->sc_pcu_lock);
936
3cbb5dd7 937 ath9k_ps_restore(sc);
500c064d
VT
938}
939
68a89116 940void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 941{
cbe61d8a 942 struct ath_hw *ah = sc->sc_ah;
68a89116 943 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 944 int r;
500c064d 945
3cbb5dd7 946 ath9k_ps_wakeup(sc);
6a6733f2
LR
947 spin_lock_bh(&sc->sc_pcu_lock);
948
68a89116 949 ieee80211_stop_queues(hw);
500c064d 950
982723df
VN
951 /*
952 * Keep the LED on when the radio is disabled
953 * during idle unassociated state.
954 */
955 if (!sc->ps_idle) {
956 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
957 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
958 }
500c064d
VT
959
960 /* Disable interrupts */
4df3071e 961 ath9k_hw_disable_interrupts(ah);
500c064d 962
043a0405 963 ath_drain_all_txq(sc, false); /* clear pending tx frames */
5e848f78 964
500c064d
VT
965 ath_stoprecv(sc); /* turn off frame recv */
966 ath_flushrecv(sc); /* flush recv queue */
967
159cd468 968 if (!ah->curchan)
68a89116 969 ah->curchan = ath_get_curchannel(sc, hw);
159cd468 970
20bd2a09 971 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 972 if (r) {
3800276a
JP
973 ath_err(ath9k_hw_common(sc->sc_ah),
974 "Unable to reset channel (%u MHz), reset status %d\n",
975 channel->center_freq, r);
500c064d 976 }
500c064d
VT
977
978 ath9k_hw_phy_disable(ah);
5e848f78 979
93b1b37f 980 ath9k_hw_configpcipowersave(ah, 1, 1);
6a6733f2
LR
981
982 spin_unlock_bh(&sc->sc_pcu_lock);
3cbb5dd7 983 ath9k_ps_restore(sc);
6a6733f2 984
9ecdef4b 985 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
500c064d
VT
986}
987
ff37e337
S
988int ath_reset(struct ath_softc *sc, bool retry_tx)
989{
cbe61d8a 990 struct ath_hw *ah = sc->sc_ah;
c46917bb 991 struct ath_common *common = ath9k_hw_common(ah);
030bb495 992 struct ieee80211_hw *hw = sc->hw;
ae8d2858 993 int r;
ff37e337 994
2ab81d4a
S
995 /* Stop ANI */
996 del_timer_sync(&common->ani.timer);
997
6a6733f2
LR
998 spin_lock_bh(&sc->sc_pcu_lock);
999
cc9c378a
S
1000 ieee80211_stop_queues(hw);
1001
4df3071e 1002 ath9k_hw_disable_interrupts(ah);
043a0405 1003 ath_drain_all_txq(sc, retry_tx);
5e848f78 1004
ff37e337
S
1005 ath_stoprecv(sc);
1006 ath_flushrecv(sc);
1007
20bd2a09 1008 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
ae8d2858 1009 if (r)
3800276a
JP
1010 ath_err(common,
1011 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S
1012
1013 if (ath_startrecv(sc) != 0)
3800276a 1014 ath_err(common, "Unable to start recv logic\n");
ff37e337
S
1015
1016 /*
1017 * We may be doing a reset in response to a request
1018 * that changes the channel so update any state that
1019 * might change as a result.
1020 */
ff37e337
S
1021 ath_update_txpow(sc);
1022
52b8ac92 1023 if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
2c3db3d5 1024 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1025
3069168c 1026 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337
S
1027
1028 if (retry_tx) {
1029 int i;
1030 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1031 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
1032 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1033 ath_txq_schedule(sc, &sc->tx.txq[i]);
1034 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
1035 }
1036 }
1037 }
1038
cc9c378a 1039 ieee80211_wake_queues(hw);
6a6733f2 1040 spin_unlock_bh(&sc->sc_pcu_lock);
cc9c378a 1041
2ab81d4a
S
1042 /* Start ANI */
1043 ath_start_ani(common);
1044
ae8d2858 1045 return r;
ff37e337
S
1046}
1047
5f8e077c
LR
1048/* XXX: Remove me once we don't depend on ath9k_channel for all
1049 * this redundant data */
0e2dedf9
JM
1050void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1051 struct ath9k_channel *ichan)
5f8e077c 1052{
5f8e077c
LR
1053 struct ieee80211_channel *chan = hw->conf.channel;
1054 struct ieee80211_conf *conf = &hw->conf;
1055
1056 ichan->channel = chan->center_freq;
1057 ichan->chan = chan;
1058
1059 if (chan->band == IEEE80211_BAND_2GHZ) {
1060 ichan->chanmode = CHANNEL_G;
8813262e 1061 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
5f8e077c
LR
1062 } else {
1063 ichan->chanmode = CHANNEL_A;
1064 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1065 }
1066
25c56eec 1067 if (conf_is_ht(conf))
5f8e077c
LR
1068 ichan->chanmode = ath_get_extchanmode(sc, chan,
1069 conf->channel_type);
5f8e077c
LR
1070}
1071
ff37e337
S
1072/**********************/
1073/* mac80211 callbacks */
1074/**********************/
1075
8feceb67 1076static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1077{
bce048d7
JM
1078 struct ath_wiphy *aphy = hw->priv;
1079 struct ath_softc *sc = aphy->sc;
af03abec 1080 struct ath_hw *ah = sc->sc_ah;
c46917bb 1081 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1082 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1083 struct ath9k_channel *init_channel;
82880a7c 1084 int r;
f078f209 1085
226afe68
JP
1086 ath_dbg(common, ATH_DBG_CONFIG,
1087 "Starting driver with initial channel: %d MHz\n",
1088 curchan->center_freq);
f078f209 1089
141b38b6
S
1090 mutex_lock(&sc->mutex);
1091
9580a222
JM
1092 if (ath9k_wiphy_started(sc)) {
1093 if (sc->chan_idx == curchan->hw_value) {
1094 /*
1095 * Already on the operational channel, the new wiphy
1096 * can be marked active.
1097 */
1098 aphy->state = ATH_WIPHY_ACTIVE;
1099 ieee80211_wake_queues(hw);
1100 } else {
1101 /*
1102 * Another wiphy is on another channel, start the new
1103 * wiphy in paused state.
1104 */
1105 aphy->state = ATH_WIPHY_PAUSED;
1106 ieee80211_stop_queues(hw);
1107 }
1108 mutex_unlock(&sc->mutex);
1109 return 0;
1110 }
1111 aphy->state = ATH_WIPHY_ACTIVE;
1112
8feceb67 1113 /* setup initial channel */
f078f209 1114
82880a7c 1115 sc->chan_idx = curchan->hw_value;
f078f209 1116
82880a7c 1117 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S
1118
1119 /* Reset SERDES registers */
af03abec 1120 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S
1121
1122 /*
1123 * The basic interface to setting the hardware in a good
1124 * state is ``reset''. On return the hardware is known to
1125 * be powered up and with interrupts disabled. This must
1126 * be followed by initialization of the appropriate bits
1127 * and then setup of the interrupt mask.
1128 */
4bdd1e97 1129 spin_lock_bh(&sc->sc_pcu_lock);
20bd2a09 1130 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 1131 if (r) {
3800276a
JP
1132 ath_err(common,
1133 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1134 r, curchan->center_freq);
4bdd1e97 1135 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1136 goto mutex_unlock;
ff37e337 1137 }
ff37e337
S
1138
1139 /*
1140 * This is needed only to setup initial state
1141 * but it's best done after a reset.
1142 */
1143 ath_update_txpow(sc);
8feceb67 1144
ff37e337
S
1145 /*
1146 * Setup the hardware after reset:
1147 * The receive engine is set going.
1148 * Frame transmit is handled entirely
1149 * in the frame output path; there's nothing to do
1150 * here except setup the interrupt mask.
1151 */
1152 if (ath_startrecv(sc) != 0) {
3800276a 1153 ath_err(common, "Unable to start recv logic\n");
141b38b6 1154 r = -EIO;
4bdd1e97 1155 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1156 goto mutex_unlock;
f078f209 1157 }
4bdd1e97 1158 spin_unlock_bh(&sc->sc_pcu_lock);
8feceb67 1159
ff37e337 1160 /* Setup our intr mask. */
b5c80475
FF
1161 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1162 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1163 ATH9K_INT_GLOBAL;
1164
1165 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR
1166 ah->imask |= ATH9K_INT_RXHP |
1167 ATH9K_INT_RXLP |
1168 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF
1169 else
1170 ah->imask |= ATH9K_INT_RX;
ff37e337 1171
364734fa 1172 ah->imask |= ATH9K_INT_GTT;
ff37e337 1173
af03abec 1174 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 1175 ah->imask |= ATH9K_INT_CST;
ff37e337 1176
ff37e337 1177 sc->sc_flags &= ~SC_OP_INVALID;
5f841b41 1178 sc->sc_ah->is_monitoring = false;
ff37e337
S
1179
1180 /* Disable BMISS interrupt when we're not associated */
3069168c
PR
1181 ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1182 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337 1183
bce048d7 1184 ieee80211_wake_queues(hw);
ff37e337 1185
42935eca 1186 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 1187
766ec4a9
LR
1188 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1189 !ah->btcoex_hw.enabled) {
5e197292
LR
1190 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1191 AR_STOMP_LOW_WLAN_WGHT);
af03abec 1192 ath9k_hw_btcoex_enable(ah);
f985ad12 1193
5bb12791
LR
1194 if (common->bus_ops->bt_coex_prep)
1195 common->bus_ops->bt_coex_prep(common);
766ec4a9 1196 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1197 ath9k_btcoex_timer_resume(sc);
1773912b
VT
1198 }
1199
2b7e6bce
MSS
1200 /* User has the option to provide pm-qos value as a module
1201 * parameter rather than using the default value of
1202 * 'ATH9K_PM_QOS_DEFAULT_VALUE'.
1203 */
4dc3530d 1204 pm_qos_update_request(&sc->pm_qos_req, ath9k_pm_qos_value);
10598c12 1205
8060e169
VT
1206 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1207 common->bus_ops->extn_synch_en(common);
1208
141b38b6
S
1209mutex_unlock:
1210 mutex_unlock(&sc->mutex);
1211
ae8d2858 1212 return r;
f078f209
LR
1213}
1214
8feceb67
VT
1215static int ath9k_tx(struct ieee80211_hw *hw,
1216 struct sk_buff *skb)
f078f209 1217{
bce048d7
JM
1218 struct ath_wiphy *aphy = hw->priv;
1219 struct ath_softc *sc = aphy->sc;
c46917bb 1220 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 1221 struct ath_tx_control txctl;
1bc14880 1222 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
528f0c6b 1223
8089cc47 1224 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
226afe68
JP
1225 ath_dbg(common, ATH_DBG_XMIT,
1226 "ath9k: %s: TX in unexpected wiphy state %d\n",
1227 wiphy_name(hw->wiphy), aphy->state);
ee166a0e
JM
1228 goto exit;
1229 }
1230
96148326 1231 if (sc->ps_enabled) {
dc8c4585
JM
1232 /*
1233 * mac80211 does not set PM field for normal data frames, so we
1234 * need to update that based on the current PS mode.
1235 */
1236 if (ieee80211_is_data(hdr->frame_control) &&
1237 !ieee80211_is_nullfunc(hdr->frame_control) &&
1238 !ieee80211_has_pm(hdr->frame_control)) {
226afe68
JP
1239 ath_dbg(common, ATH_DBG_PS,
1240 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM
1241 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1242 }
1243 }
1244
9a23f9ca
JM
1245 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1246 /*
1247 * We are using PS-Poll and mac80211 can request TX while in
1248 * power save mode. Need to wake up hardware for the TX to be
1249 * completed and if needed, also for RX of buffered frames.
1250 */
9a23f9ca 1251 ath9k_ps_wakeup(sc);
fdf76622
VT
1252 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1253 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 1254 if (ieee80211_is_pspoll(hdr->frame_control)) {
226afe68
JP
1255 ath_dbg(common, ATH_DBG_PS,
1256 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 1257 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 1258 } else {
226afe68
JP
1259 ath_dbg(common, ATH_DBG_PS,
1260 "Wake up to complete TX\n");
1b04b930 1261 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
1262 }
1263 /*
1264 * The actual restore operation will happen only after
1265 * the sc_flags bit is cleared. We are just dropping
1266 * the ps_usecount here.
1267 */
1268 ath9k_ps_restore(sc);
1269 }
1270
528f0c6b 1271 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 1272 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
528f0c6b 1273
226afe68 1274 ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1275
c52f33d0 1276 if (ath_tx_start(hw, skb, &txctl) != 0) {
226afe68 1277 ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1278 goto exit;
8feceb67
VT
1279 }
1280
528f0c6b
S
1281 return 0;
1282exit:
1283 dev_kfree_skb_any(skb);
8feceb67 1284 return 0;
f078f209
LR
1285}
1286
8feceb67 1287static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 1288{
bce048d7
JM
1289 struct ath_wiphy *aphy = hw->priv;
1290 struct ath_softc *sc = aphy->sc;
af03abec 1291 struct ath_hw *ah = sc->sc_ah;
c46917bb 1292 struct ath_common *common = ath9k_hw_common(ah);
447a42c2 1293 int i;
f078f209 1294
4c483817
S
1295 mutex_lock(&sc->mutex);
1296
9580a222
JM
1297 aphy->state = ATH_WIPHY_INACTIVE;
1298
9a75c2ff
VN
1299 if (led_blink)
1300 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1301
c94dbff7 1302 cancel_delayed_work_sync(&sc->tx_complete_work);
9f42c2b6 1303 cancel_work_sync(&sc->paprd_work);
347809fc 1304 cancel_work_sync(&sc->hw_check_work);
c94dbff7 1305
447a42c2
RM
1306 for (i = 0; i < sc->num_sec_wiphy; i++) {
1307 if (sc->sec_wiphy[i])
1308 break;
1309 }
1310
1311 if (i == sc->num_sec_wiphy) {
c94dbff7
LR
1312 cancel_delayed_work_sync(&sc->wiphy_work);
1313 cancel_work_sync(&sc->chan_work);
1314 }
1315
9c84b797 1316 if (sc->sc_flags & SC_OP_INVALID) {
226afe68 1317 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
4c483817 1318 mutex_unlock(&sc->mutex);
9c84b797
S
1319 return;
1320 }
8feceb67 1321
9580a222
JM
1322 if (ath9k_wiphy_started(sc)) {
1323 mutex_unlock(&sc->mutex);
1324 return; /* another wiphy still in use */
1325 }
1326
3867cf6a
S
1327 /* Ensure HW is awake when we try to shut it down. */
1328 ath9k_ps_wakeup(sc);
1329
766ec4a9 1330 if (ah->btcoex_hw.enabled) {
af03abec 1331 ath9k_hw_btcoex_disable(ah);
766ec4a9 1332 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1333 ath9k_btcoex_timer_pause(sc);
1773912b
VT
1334 }
1335
6a6733f2
LR
1336 spin_lock_bh(&sc->sc_pcu_lock);
1337
ff37e337
S
1338 /* make sure h/w will not generate any interrupt
1339 * before setting the invalid flag. */
4df3071e 1340 ath9k_hw_disable_interrupts(ah);
ff37e337
S
1341
1342 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 1343 ath_drain_all_txq(sc, false);
ff37e337 1344 ath_stoprecv(sc);
af03abec 1345 ath9k_hw_phy_disable(ah);
6a6733f2 1346 } else
b77f483f 1347 sc->rx.rxlink = NULL;
ff37e337 1348
ff37e337 1349 /* disable HAL and put h/w to sleep */
af03abec
LR
1350 ath9k_hw_disable(ah);
1351 ath9k_hw_configpcipowersave(ah, 1, 1);
6a6733f2
LR
1352
1353 spin_unlock_bh(&sc->sc_pcu_lock);
1354
3867cf6a
S
1355 ath9k_ps_restore(sc);
1356
a08e7ade 1357 sc->ps_idle = true;
afe68d0a 1358 ath9k_set_wiphy_idle(aphy, true);
a08e7ade 1359 ath_radio_disable(sc, hw);
ff37e337
S
1360
1361 sc->sc_flags |= SC_OP_INVALID;
500c064d 1362
98c316e3 1363 pm_qos_update_request(&sc->pm_qos_req, PM_QOS_DEFAULT_VALUE);
10598c12 1364
141b38b6
S
1365 mutex_unlock(&sc->mutex);
1366
226afe68 1367 ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR
1368}
1369
4801416c
BG
1370bool ath9k_uses_beacons(int type)
1371{
1372 switch (type) {
1373 case NL80211_IFTYPE_AP:
1374 case NL80211_IFTYPE_ADHOC:
1375 case NL80211_IFTYPE_MESH_POINT:
1376 return true;
1377 default:
1378 return false;
1379 }
1380}
1381
1382static void ath9k_reclaim_beacon(struct ath_softc *sc,
1383 struct ieee80211_vif *vif)
f078f209 1384{
1ed32e4f 1385 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67 1386
4801416c
BG
1387 /* Disable SWBA interrupt */
1388 sc->sc_ah->imask &= ~ATH9K_INT_SWBA;
1389 ath9k_ps_wakeup(sc);
1390 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
1391 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1392 tasklet_kill(&sc->bcon_tasklet);
1393 ath9k_ps_restore(sc);
1394
1395 ath_beacon_return(sc, avp);
1396 sc->sc_flags &= ~SC_OP_BEACONS;
1397
1398 if (sc->nbcnvifs > 0) {
1399 /* Re-enable beaconing */
1400 sc->sc_ah->imask |= ATH9K_INT_SWBA;
1401 ath9k_ps_wakeup(sc);
1402 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
1403 ath9k_ps_restore(sc);
1404 }
1405}
1406
1407static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1408{
1409 struct ath9k_vif_iter_data *iter_data = data;
1410 int i;
1411
1412 if (iter_data->hw_macaddr)
1413 for (i = 0; i < ETH_ALEN; i++)
1414 iter_data->mask[i] &=
1415 ~(iter_data->hw_macaddr[i] ^ mac[i]);
141b38b6 1416
1ed32e4f 1417 switch (vif->type) {
4801416c
BG
1418 case NL80211_IFTYPE_AP:
1419 iter_data->naps++;
f078f209 1420 break;
4801416c
BG
1421 case NL80211_IFTYPE_STATION:
1422 iter_data->nstations++;
e51f3eff 1423 break;
05c914fe 1424 case NL80211_IFTYPE_ADHOC:
4801416c
BG
1425 iter_data->nadhocs++;
1426 break;
9cb5412b 1427 case NL80211_IFTYPE_MESH_POINT:
4801416c
BG
1428 iter_data->nmeshes++;
1429 break;
1430 case NL80211_IFTYPE_WDS:
1431 iter_data->nwds++;
f078f209
LR
1432 break;
1433 default:
4801416c
BG
1434 iter_data->nothers++;
1435 break;
f078f209 1436 }
4801416c 1437}
f078f209 1438
4801416c
BG
1439/* Called with sc->mutex held. */
1440void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1441 struct ieee80211_vif *vif,
1442 struct ath9k_vif_iter_data *iter_data)
1443{
1444 struct ath_wiphy *aphy = hw->priv;
1445 struct ath_softc *sc = aphy->sc;
1446 struct ath_hw *ah = sc->sc_ah;
1447 struct ath_common *common = ath9k_hw_common(ah);
1448 int i;
8feceb67 1449
4801416c
BG
1450 /*
1451 * Use the hardware MAC address as reference, the hardware uses it
1452 * together with the BSSID mask when matching addresses.
1453 */
1454 memset(iter_data, 0, sizeof(*iter_data));
1455 iter_data->hw_macaddr = common->macaddr;
1456 memset(&iter_data->mask, 0xff, ETH_ALEN);
5640b08e 1457
4801416c
BG
1458 if (vif)
1459 ath9k_vif_iter(iter_data, vif->addr, vif);
1460
1461 /* Get list of all active MAC addresses */
1462 spin_lock_bh(&sc->wiphy_lock);
1463 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
1464 iter_data);
1465 for (i = 0; i < sc->num_sec_wiphy; i++) {
1466 if (sc->sec_wiphy[i] == NULL)
1467 continue;
1468 ieee80211_iterate_active_interfaces_atomic(
1469 sc->sec_wiphy[i]->hw, ath9k_vif_iter, iter_data);
1470 }
1471 spin_unlock_bh(&sc->wiphy_lock);
1472}
8ca21f01 1473
4801416c
BG
1474/* Called with sc->mutex held. */
1475static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1476 struct ieee80211_vif *vif)
1477{
1478 struct ath_wiphy *aphy = hw->priv;
1479 struct ath_softc *sc = aphy->sc;
1480 struct ath_hw *ah = sc->sc_ah;
1481 struct ath_common *common = ath9k_hw_common(ah);
1482 struct ath9k_vif_iter_data iter_data;
8ca21f01 1483
4801416c 1484 ath9k_calculate_iter_data(hw, vif, &iter_data);
2c3db3d5 1485
4801416c
BG
1486 /* Set BSSID mask. */
1487 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1488 ath_hw_setbssidmask(common);
1489
1490 /* Set op-mode & TSF */
1491 if (iter_data.naps > 0) {
3069168c 1492 ath9k_hw_set_tsfadjust(ah, 1);
b238e90e 1493 sc->sc_flags |= SC_OP_TSF_RESET;
4801416c
BG
1494 ah->opmode = NL80211_IFTYPE_AP;
1495 } else {
1496 ath9k_hw_set_tsfadjust(ah, 0);
1497 sc->sc_flags &= ~SC_OP_TSF_RESET;
5640b08e 1498
4801416c
BG
1499 if (iter_data.nwds + iter_data.nmeshes)
1500 ah->opmode = NL80211_IFTYPE_AP;
1501 else if (iter_data.nadhocs)
1502 ah->opmode = NL80211_IFTYPE_ADHOC;
1503 else
1504 ah->opmode = NL80211_IFTYPE_STATION;
1505 }
5640b08e 1506
4e30ffa2
VN
1507 /*
1508 * Enable MIB interrupts when there are hardware phy counters.
4e30ffa2 1509 */
4801416c 1510 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
3448f912
LR
1511 if (ah->config.enable_ani)
1512 ah->imask |= ATH9K_INT_MIB;
3069168c 1513 ah->imask |= ATH9K_INT_TSFOOR;
4801416c
BG
1514 } else {
1515 ah->imask &= ~ATH9K_INT_MIB;
1516 ah->imask &= ~ATH9K_INT_TSFOOR;
4af9cf4f
S
1517 }
1518
3069168c 1519 ath9k_hw_set_interrupts(ah, ah->imask);
4e30ffa2 1520
4801416c
BG
1521 /* Set up ANI */
1522 if ((iter_data.naps + iter_data.nadhocs) > 0) {
6c3118e2 1523 sc->sc_flags |= SC_OP_ANI_RUN;
3d536acf 1524 ath_start_ani(common);
4801416c
BG
1525 } else {
1526 sc->sc_flags &= ~SC_OP_ANI_RUN;
1527 del_timer_sync(&common->ani.timer);
6c3118e2 1528 }
4801416c 1529}
6f255425 1530
4801416c
BG
1531/* Called with sc->mutex held, vif counts set up properly. */
1532static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
1533 struct ieee80211_vif *vif)
1534{
1535 struct ath_wiphy *aphy = hw->priv;
1536 struct ath_softc *sc = aphy->sc;
1537
1538 ath9k_calculate_summary_state(hw, vif);
1539
1540 if (ath9k_uses_beacons(vif->type)) {
1541 int error;
1542 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1543 /* This may fail because upper levels do not have beacons
1544 * properly configured yet. That's OK, we assume it
1545 * will be properly configured and then we will be notified
1546 * in the info_changed method and set up beacons properly
1547 * there.
1548 */
1549 error = ath_beacon_alloc(aphy, vif);
1550 if (error)
1551 ath9k_reclaim_beacon(sc, vif);
1552 else
1553 ath_beacon_config(sc, vif);
1554 }
f078f209
LR
1555}
1556
4801416c
BG
1557
1558static int ath9k_add_interface(struct ieee80211_hw *hw,
1559 struct ieee80211_vif *vif)
6b3b991d 1560{
4801416c
BG
1561 struct ath_wiphy *aphy = hw->priv;
1562 struct ath_softc *sc = aphy->sc;
1563 struct ath_hw *ah = sc->sc_ah;
1564 struct ath_common *common = ath9k_hw_common(ah);
6b3b991d 1565 struct ath_vif *avp = (void *)vif->drv_priv;
4801416c 1566 int ret = 0;
6b3b991d 1567
4801416c 1568 mutex_lock(&sc->mutex);
6b3b991d 1569
4801416c
BG
1570 switch (vif->type) {
1571 case NL80211_IFTYPE_STATION:
1572 case NL80211_IFTYPE_WDS:
1573 case NL80211_IFTYPE_ADHOC:
1574 case NL80211_IFTYPE_AP:
1575 case NL80211_IFTYPE_MESH_POINT:
1576 break;
1577 default:
1578 ath_err(common, "Interface type %d not yet supported\n",
1579 vif->type);
1580 ret = -EOPNOTSUPP;
1581 goto out;
1582 }
6b3b991d 1583
4801416c
BG
1584 if (ath9k_uses_beacons(vif->type)) {
1585 if (sc->nbcnvifs >= ATH_BCBUF) {
1586 ath_err(common, "Not enough beacon buffers when adding"
1587 " new interface of type: %i\n",
1588 vif->type);
1589 ret = -ENOBUFS;
1590 goto out;
1591 }
1592 }
1593
1594 if ((vif->type == NL80211_IFTYPE_ADHOC) &&
1595 sc->nvifs > 0) {
1596 ath_err(common, "Cannot create ADHOC interface when other"
1597 " interfaces already exist.\n");
1598 ret = -EINVAL;
1599 goto out;
6b3b991d 1600 }
4801416c
BG
1601
1602 ath_dbg(common, ATH_DBG_CONFIG,
1603 "Attach a VIF of type: %d\n", vif->type);
1604
1605 /* Set the VIF opmode */
1606 avp->av_opmode = vif->type;
1607 avp->av_bslot = -1;
1608
1609 sc->nvifs++;
1610
1611 ath9k_do_vif_add_setup(hw, vif);
1612out:
1613 mutex_unlock(&sc->mutex);
1614 return ret;
6b3b991d
RM
1615}
1616
1617static int ath9k_change_interface(struct ieee80211_hw *hw,
1618 struct ieee80211_vif *vif,
1619 enum nl80211_iftype new_type,
1620 bool p2p)
1621{
1622 struct ath_wiphy *aphy = hw->priv;
1623 struct ath_softc *sc = aphy->sc;
1624 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
6dab55bf 1625 int ret = 0;
6b3b991d
RM
1626
1627 ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
1628 mutex_lock(&sc->mutex);
1629
4801416c
BG
1630 /* See if new interface type is valid. */
1631 if ((new_type == NL80211_IFTYPE_ADHOC) &&
1632 (sc->nvifs > 1)) {
1633 ath_err(common, "When using ADHOC, it must be the only"
1634 " interface.\n");
1635 ret = -EINVAL;
1636 goto out;
1637 }
1638
1639 if (ath9k_uses_beacons(new_type) &&
1640 !ath9k_uses_beacons(vif->type)) {
6b3b991d
RM
1641 if (sc->nbcnvifs >= ATH_BCBUF) {
1642 ath_err(common, "No beacon slot available\n");
6dab55bf
DC
1643 ret = -ENOBUFS;
1644 goto out;
6b3b991d 1645 }
6b3b991d 1646 }
4801416c
BG
1647
1648 /* Clean up old vif stuff */
1649 if (ath9k_uses_beacons(vif->type))
1650 ath9k_reclaim_beacon(sc, vif);
1651
1652 /* Add new settings */
6b3b991d
RM
1653 vif->type = new_type;
1654 vif->p2p = p2p;
1655
4801416c 1656 ath9k_do_vif_add_setup(hw, vif);
6dab55bf 1657out:
6b3b991d 1658 mutex_unlock(&sc->mutex);
6dab55bf 1659 return ret;
6b3b991d
RM
1660}
1661
8feceb67 1662static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1663 struct ieee80211_vif *vif)
f078f209 1664{
bce048d7
JM
1665 struct ath_wiphy *aphy = hw->priv;
1666 struct ath_softc *sc = aphy->sc;
c46917bb 1667 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f078f209 1668
226afe68 1669 ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 1670
141b38b6
S
1671 mutex_lock(&sc->mutex);
1672
4801416c 1673 sc->nvifs--;
580f0b8a 1674
8feceb67 1675 /* Reclaim beacon resources */
4801416c 1676 if (ath9k_uses_beacons(vif->type))
6b3b991d 1677 ath9k_reclaim_beacon(sc, vif);
2c3db3d5 1678
4801416c 1679 ath9k_calculate_summary_state(hw, NULL);
141b38b6
S
1680
1681 mutex_unlock(&sc->mutex);
f078f209
LR
1682}
1683
fbab7390 1684static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1685{
3069168c
PR
1686 struct ath_hw *ah = sc->sc_ah;
1687
3f7c5c10 1688 sc->ps_enabled = true;
3069168c
PR
1689 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1690 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1691 ah->imask |= ATH9K_INT_TIM_TIMER;
1692 ath9k_hw_set_interrupts(ah, ah->imask);
3f7c5c10 1693 }
fdf76622 1694 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1695 }
3f7c5c10
SB
1696}
1697
845d708e
SB
1698static void ath9k_disable_ps(struct ath_softc *sc)
1699{
1700 struct ath_hw *ah = sc->sc_ah;
1701
1702 sc->ps_enabled = false;
1703 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1704 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1705 ath9k_hw_setrxabort(ah, 0);
1706 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1707 PS_WAIT_FOR_CAB |
1708 PS_WAIT_FOR_PSPOLL_DATA |
1709 PS_WAIT_FOR_TX_ACK);
1710 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1711 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1712 ath9k_hw_set_interrupts(ah, ah->imask);
1713 }
1714 }
1715
1716}
1717
e8975581 1718static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1719{
bce048d7
JM
1720 struct ath_wiphy *aphy = hw->priv;
1721 struct ath_softc *sc = aphy->sc;
3430098a
FF
1722 struct ath_hw *ah = sc->sc_ah;
1723 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1724 struct ieee80211_conf *conf = &hw->conf;
194b7c13 1725 bool disable_radio;
f078f209 1726
aa33de09 1727 mutex_lock(&sc->mutex);
141b38b6 1728
194b7c13
LR
1729 /*
1730 * Leave this as the first check because we need to turn on the
1731 * radio if it was disabled before prior to processing the rest
1732 * of the changes. Likewise we must only disable the radio towards
1733 * the end.
1734 */
64839170 1735 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
194b7c13
LR
1736 bool enable_radio;
1737 bool all_wiphys_idle;
1738 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
64839170
LR
1739
1740 spin_lock_bh(&sc->wiphy_lock);
1741 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
194b7c13
LR
1742 ath9k_set_wiphy_idle(aphy, idle);
1743
11446011 1744 enable_radio = (!idle && all_wiphys_idle);
194b7c13
LR
1745
1746 /*
1747 * After we unlock here its possible another wiphy
1748 * can be re-renabled so to account for that we will
1749 * only disable the radio toward the end of this routine
1750 * if by then all wiphys are still idle.
1751 */
64839170
LR
1752 spin_unlock_bh(&sc->wiphy_lock);
1753
194b7c13 1754 if (enable_radio) {
1dbfd9d4 1755 sc->ps_idle = false;
68a89116 1756 ath_radio_enable(sc, hw);
226afe68
JP
1757 ath_dbg(common, ATH_DBG_CONFIG,
1758 "not-idle: enabling radio\n");
64839170
LR
1759 }
1760 }
1761
e7824a50
LR
1762 /*
1763 * We just prepare to enable PS. We have to wait until our AP has
1764 * ACK'd our null data frame to disable RX otherwise we'll ignore
1765 * those ACKs and end up retransmitting the same null data frames.
1766 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1767 */
3cbb5dd7 1768 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR
1769 unsigned long flags;
1770 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB
1771 if (conf->flags & IEEE80211_CONF_PS)
1772 ath9k_enable_ps(sc);
845d708e
SB
1773 else
1774 ath9k_disable_ps(sc);
8ab2cd09 1775 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN
1776 }
1777
199afd9d
S
1778 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1779 if (conf->flags & IEEE80211_CONF_MONITOR) {
226afe68
JP
1780 ath_dbg(common, ATH_DBG_CONFIG,
1781 "Monitor mode is enabled\n");
5f841b41
RM
1782 sc->sc_ah->is_monitoring = true;
1783 } else {
226afe68
JP
1784 ath_dbg(common, ATH_DBG_CONFIG,
1785 "Monitor mode is disabled\n");
5f841b41 1786 sc->sc_ah->is_monitoring = false;
199afd9d
S
1787 }
1788 }
1789
4797938c 1790 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 1791 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1792 int pos = curchan->hw_value;
3430098a
FF
1793 int old_pos = -1;
1794 unsigned long flags;
1795
1796 if (ah->curchan)
1797 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1798
0e2dedf9
JM
1799 aphy->chan_idx = pos;
1800 aphy->chan_is_ht = conf_is_ht(conf);
5ee08656
FF
1801 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1802 sc->sc_flags |= SC_OP_OFFCHANNEL;
1803 else
1804 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
0e2dedf9 1805
8089cc47
JM
1806 if (aphy->state == ATH_WIPHY_SCAN ||
1807 aphy->state == ATH_WIPHY_ACTIVE)
1808 ath9k_wiphy_pause_all_forced(sc, aphy);
1809 else {
1810 /*
1811 * Do not change operational channel based on a paused
1812 * wiphy changes.
1813 */
1814 goto skip_chan_change;
1815 }
0e2dedf9 1816
226afe68
JP
1817 ath_dbg(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
1818 curchan->center_freq);
f078f209 1819
5f8e077c 1820 /* XXX: remove me eventualy */
0e2dedf9 1821 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 1822
3430098a
FF
1823 /* update survey stats for the old channel before switching */
1824 spin_lock_irqsave(&common->cc_lock, flags);
1825 ath_update_survey_stats(sc);
1826 spin_unlock_irqrestore(&common->cc_lock, flags);
1827
1828 /*
1829 * If the operating channel changes, change the survey in-use flags
1830 * along with it.
1831 * Reset the survey data for the new channel, unless we're switching
1832 * back to the operating channel from an off-channel operation.
1833 */
1834 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1835 sc->cur_survey != &sc->survey[pos]) {
1836
1837 if (sc->cur_survey)
1838 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1839
1840 sc->cur_survey = &sc->survey[pos];
1841
1842 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1843 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1844 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1845 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1846 }
1847
0e2dedf9 1848 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
3800276a 1849 ath_err(common, "Unable to set channel\n");
aa33de09 1850 mutex_unlock(&sc->mutex);
e11602b7
S
1851 return -EINVAL;
1852 }
3430098a
FF
1853
1854 /*
1855 * The most recent snapshot of channel->noisefloor for the old
1856 * channel is only available after the hardware reset. Copy it to
1857 * the survey stats now.
1858 */
1859 if (old_pos >= 0)
1860 ath_update_survey_nf(sc, old_pos);
094d05dc 1861 }
f078f209 1862
8089cc47 1863skip_chan_change:
c9f6a656 1864 if (changed & IEEE80211_CONF_CHANGE_POWER) {
17d7904d 1865 sc->config.txpowlimit = 2 * conf->power_level;
c9f6a656
LR
1866 ath_update_txpow(sc);
1867 }
f078f209 1868
194b7c13
LR
1869 spin_lock_bh(&sc->wiphy_lock);
1870 disable_radio = ath9k_all_wiphys_idle(sc);
1871 spin_unlock_bh(&sc->wiphy_lock);
1872
64839170 1873 if (disable_radio) {
226afe68 1874 ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
1dbfd9d4 1875 sc->ps_idle = true;
68a89116 1876 ath_radio_disable(sc, hw);
64839170
LR
1877 }
1878
aa33de09 1879 mutex_unlock(&sc->mutex);
141b38b6 1880
f078f209
LR
1881 return 0;
1882}
1883
8feceb67
VT
1884#define SUPPORTED_FILTERS \
1885 (FIF_PROMISC_IN_BSS | \
1886 FIF_ALLMULTI | \
1887 FIF_CONTROL | \
af6a3fc7 1888 FIF_PSPOLL | \
8feceb67
VT
1889 FIF_OTHER_BSS | \
1890 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1891 FIF_PROBE_REQ | \
8feceb67 1892 FIF_FCSFAIL)
c83be688 1893
8feceb67
VT
1894/* FIXME: sc->sc_full_reset ? */
1895static void ath9k_configure_filter(struct ieee80211_hw *hw,
1896 unsigned int changed_flags,
1897 unsigned int *total_flags,
3ac64bee 1898 u64 multicast)
8feceb67 1899{
bce048d7
JM
1900 struct ath_wiphy *aphy = hw->priv;
1901 struct ath_softc *sc = aphy->sc;
8feceb67 1902 u32 rfilt;
f078f209 1903
8feceb67
VT
1904 changed_flags &= SUPPORTED_FILTERS;
1905 *total_flags &= SUPPORTED_FILTERS;
f078f209 1906
b77f483f 1907 sc->rx.rxfilter = *total_flags;
aa68aeaa 1908 ath9k_ps_wakeup(sc);
8feceb67
VT
1909 rfilt = ath_calcrxfilter(sc);
1910 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1911 ath9k_ps_restore(sc);
f078f209 1912
226afe68
JP
1913 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1914 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 1915}
f078f209 1916
4ca77860
JB
1917static int ath9k_sta_add(struct ieee80211_hw *hw,
1918 struct ieee80211_vif *vif,
1919 struct ieee80211_sta *sta)
8feceb67 1920{
bce048d7
JM
1921 struct ath_wiphy *aphy = hw->priv;
1922 struct ath_softc *sc = aphy->sc;
f078f209 1923
4ca77860
JB
1924 ath_node_attach(sc, sta);
1925
1926 return 0;
1927}
1928
1929static int ath9k_sta_remove(struct ieee80211_hw *hw,
1930 struct ieee80211_vif *vif,
1931 struct ieee80211_sta *sta)
1932{
1933 struct ath_wiphy *aphy = hw->priv;
1934 struct ath_softc *sc = aphy->sc;
1935
1936 ath_node_detach(sc, sta);
1937
1938 return 0;
f078f209
LR
1939}
1940
141b38b6 1941static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 1942 const struct ieee80211_tx_queue_params *params)
f078f209 1943{
bce048d7
JM
1944 struct ath_wiphy *aphy = hw->priv;
1945 struct ath_softc *sc = aphy->sc;
c46917bb 1946 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1947 struct ath_txq *txq;
8feceb67 1948 struct ath9k_tx_queue_info qi;
066dae93 1949 int ret = 0;
f078f209 1950
8feceb67
VT
1951 if (queue >= WME_NUM_AC)
1952 return 0;
f078f209 1953
066dae93
FF
1954 txq = sc->tx.txq_map[queue];
1955
141b38b6
S
1956 mutex_lock(&sc->mutex);
1957
1ffb0610
S
1958 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1959
8feceb67
VT
1960 qi.tqi_aifs = params->aifs;
1961 qi.tqi_cwmin = params->cw_min;
1962 qi.tqi_cwmax = params->cw_max;
1963 qi.tqi_burstTime = params->txop;
f078f209 1964
226afe68
JP
1965 ath_dbg(common, ATH_DBG_CONFIG,
1966 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1967 queue, txq->axq_qnum, params->aifs, params->cw_min,
1968 params->cw_max, params->txop);
f078f209 1969
066dae93 1970 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1971 if (ret)
3800276a 1972 ath_err(common, "TXQ Update failed\n");
f078f209 1973
94db2936 1974 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
066dae93 1975 if (queue == WME_AC_BE && !ret)
94db2936
VN
1976 ath_beaconq_config(sc);
1977
141b38b6
S
1978 mutex_unlock(&sc->mutex);
1979
8feceb67
VT
1980 return ret;
1981}
f078f209 1982
8feceb67
VT
1983static int ath9k_set_key(struct ieee80211_hw *hw,
1984 enum set_key_cmd cmd,
dc822b5d
JB
1985 struct ieee80211_vif *vif,
1986 struct ieee80211_sta *sta,
8feceb67
VT
1987 struct ieee80211_key_conf *key)
1988{
bce048d7
JM
1989 struct ath_wiphy *aphy = hw->priv;
1990 struct ath_softc *sc = aphy->sc;
c46917bb 1991 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1992 int ret = 0;
f078f209 1993
3e6109c5 1994 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM
1995 return -ENOSPC;
1996
141b38b6 1997 mutex_lock(&sc->mutex);
3cbb5dd7 1998 ath9k_ps_wakeup(sc);
226afe68 1999 ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2000
8feceb67
VT
2001 switch (cmd) {
2002 case SET_KEY:
040e539e 2003 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
2004 if (ret >= 0) {
2005 key->hw_key_idx = ret;
8feceb67
VT
2006 /* push IV and Michael MIC generation to stack */
2007 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 2008 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 2009 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB
2010 if (sc->sc_ah->sw_mgmt_crypto &&
2011 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 2012 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2013 ret = 0;
8feceb67
VT
2014 }
2015 break;
2016 case DISABLE_KEY:
040e539e 2017 ath_key_delete(common, key);
8feceb67
VT
2018 break;
2019 default:
2020 ret = -EINVAL;
2021 }
f078f209 2022
3cbb5dd7 2023 ath9k_ps_restore(sc);
141b38b6
S
2024 mutex_unlock(&sc->mutex);
2025
8feceb67
VT
2026 return ret;
2027}
f078f209 2028
8feceb67
VT
2029static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2030 struct ieee80211_vif *vif,
2031 struct ieee80211_bss_conf *bss_conf,
2032 u32 changed)
2033{
bce048d7
JM
2034 struct ath_wiphy *aphy = hw->priv;
2035 struct ath_softc *sc = aphy->sc;
2d0ddec5 2036 struct ath_hw *ah = sc->sc_ah;
1510718d 2037 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 2038 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 2039 int slottime;
c6089ccc 2040 int error;
f078f209 2041
141b38b6
S
2042 mutex_lock(&sc->mutex);
2043
c6089ccc
S
2044 if (changed & BSS_CHANGED_BSSID) {
2045 /* Set BSSID */
2046 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2047 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1510718d 2048 common->curaid = 0;
f2b2143e 2049 ath9k_hw_write_associd(ah);
2d0ddec5 2050
c6089ccc
S
2051 /* Set aggregation protection mode parameters */
2052 sc->config.ath_aggr_prot = 0;
2d0ddec5 2053
226afe68
JP
2054 ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
2055 common->curbssid, common->curaid);
2d0ddec5 2056
c6089ccc
S
2057 /* need to reconfigure the beacon */
2058 sc->sc_flags &= ~SC_OP_BEACONS ;
2059 }
2d0ddec5 2060
c6089ccc
S
2061 /* Enable transmission of beacons (AP, IBSS, MESH) */
2062 if ((changed & BSS_CHANGED_BEACON) ||
2063 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
2064 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2065 error = ath_beacon_alloc(aphy, vif);
2066 if (!error)
2067 ath_beacon_config(sc, vif);
0005baf4
FF
2068 }
2069
2070 if (changed & BSS_CHANGED_ERP_SLOT) {
2071 if (bss_conf->use_short_slot)
2072 slottime = 9;
2073 else
2074 slottime = 20;
2075 if (vif->type == NL80211_IFTYPE_AP) {
2076 /*
2077 * Defer update, so that connected stations can adjust
2078 * their settings at the same time.
2079 * See beacon.c for more details
2080 */
2081 sc->beacon.slottime = slottime;
2082 sc->beacon.updateslot = UPDATE;
2083 } else {
2084 ah->slottime = slottime;
2085 ath9k_hw_init_global_settings(ah);
2086 }
2d0ddec5
JB
2087 }
2088
c6089ccc
S
2089 /* Disable transmission of beacons */
2090 if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
2091 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2d0ddec5 2092
c6089ccc
S
2093 if (changed & BSS_CHANGED_BEACON_INT) {
2094 sc->beacon_interval = bss_conf->beacon_int;
2095 /*
2096 * In case of AP mode, the HW TSF has to be reset
2097 * when the beacon interval changes.
2098 */
2099 if (vif->type == NL80211_IFTYPE_AP) {
2100 sc->sc_flags |= SC_OP_TSF_RESET;
2101 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2d0ddec5
JB
2102 error = ath_beacon_alloc(aphy, vif);
2103 if (!error)
2104 ath_beacon_config(sc, vif);
c6089ccc
S
2105 } else {
2106 ath_beacon_config(sc, vif);
2d0ddec5
JB
2107 }
2108 }
2109
8feceb67 2110 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
226afe68
JP
2111 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2112 bss_conf->use_short_preamble);
8feceb67
VT
2113 if (bss_conf->use_short_preamble)
2114 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2115 else
2116 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2117 }
f078f209 2118
8feceb67 2119 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
226afe68
JP
2120 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2121 bss_conf->use_cts_prot);
8feceb67
VT
2122 if (bss_conf->use_cts_prot &&
2123 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2124 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2125 else
2126 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2127 }
f078f209 2128
8feceb67 2129 if (changed & BSS_CHANGED_ASSOC) {
226afe68 2130 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2131 bss_conf->assoc);
9fa23e17 2132 ath9k_bss_assoc_info(sc, hw, vif, bss_conf);
8feceb67 2133 }
141b38b6
S
2134
2135 mutex_unlock(&sc->mutex);
8feceb67 2136}
f078f209 2137
8feceb67
VT
2138static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2139{
2140 u64 tsf;
bce048d7
JM
2141 struct ath_wiphy *aphy = hw->priv;
2142 struct ath_softc *sc = aphy->sc;
f078f209 2143
141b38b6 2144 mutex_lock(&sc->mutex);
9abbfb27 2145 ath9k_ps_wakeup(sc);
141b38b6 2146 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 2147 ath9k_ps_restore(sc);
141b38b6 2148 mutex_unlock(&sc->mutex);
f078f209 2149
8feceb67
VT
2150 return tsf;
2151}
f078f209 2152
3b5d665b
AF
2153static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2154{
bce048d7
JM
2155 struct ath_wiphy *aphy = hw->priv;
2156 struct ath_softc *sc = aphy->sc;
3b5d665b 2157
141b38b6 2158 mutex_lock(&sc->mutex);
9abbfb27 2159 ath9k_ps_wakeup(sc);
141b38b6 2160 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 2161 ath9k_ps_restore(sc);
141b38b6 2162 mutex_unlock(&sc->mutex);
3b5d665b
AF
2163}
2164
8feceb67
VT
2165static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2166{
bce048d7
JM
2167 struct ath_wiphy *aphy = hw->priv;
2168 struct ath_softc *sc = aphy->sc;
c83be688 2169
141b38b6 2170 mutex_lock(&sc->mutex);
21526d57
LR
2171
2172 ath9k_ps_wakeup(sc);
141b38b6 2173 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
2174 ath9k_ps_restore(sc);
2175
141b38b6 2176 mutex_unlock(&sc->mutex);
8feceb67 2177}
f078f209 2178
8feceb67 2179static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2180 struct ieee80211_vif *vif,
141b38b6
S
2181 enum ieee80211_ampdu_mlme_action action,
2182 struct ieee80211_sta *sta,
0b01f030 2183 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 2184{
bce048d7
JM
2185 struct ath_wiphy *aphy = hw->priv;
2186 struct ath_softc *sc = aphy->sc;
8feceb67 2187 int ret = 0;
f078f209 2188
85ad181e
JB
2189 local_bh_disable();
2190
8feceb67
VT
2191 switch (action) {
2192 case IEEE80211_AMPDU_RX_START:
dca3edb8
S
2193 if (!(sc->sc_flags & SC_OP_RXAGGR))
2194 ret = -ENOTSUPP;
8feceb67
VT
2195 break;
2196 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
2197 break;
2198 case IEEE80211_AMPDU_TX_START:
71a3bf3e
FF
2199 if (!(sc->sc_flags & SC_OP_TXAGGR))
2200 return -EOPNOTSUPP;
2201
8b685ba9 2202 ath9k_ps_wakeup(sc);
231c3a1f
FF
2203 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2204 if (!ret)
2205 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2206 ath9k_ps_restore(sc);
8feceb67
VT
2207 break;
2208 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 2209 ath9k_ps_wakeup(sc);
f83da965 2210 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 2211 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2212 ath9k_ps_restore(sc);
8feceb67 2213 break;
b1720231 2214 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 2215 ath9k_ps_wakeup(sc);
8469cdef 2216 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 2217 ath9k_ps_restore(sc);
8469cdef 2218 break;
8feceb67 2219 default:
3800276a 2220 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT
2221 }
2222
85ad181e
JB
2223 local_bh_enable();
2224
8feceb67 2225 return ret;
f078f209
LR
2226}
2227
62dad5b0
BP
2228static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2229 struct survey_info *survey)
2230{
2231 struct ath_wiphy *aphy = hw->priv;
2232 struct ath_softc *sc = aphy->sc;
3430098a 2233 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 2234 struct ieee80211_supported_band *sband;
3430098a
FF
2235 struct ieee80211_channel *chan;
2236 unsigned long flags;
2237 int pos;
2238
2239 spin_lock_irqsave(&common->cc_lock, flags);
2240 if (idx == 0)
2241 ath_update_survey_stats(sc);
39162dbe
FF
2242
2243 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2244 if (sband && idx >= sband->n_channels) {
2245 idx -= sband->n_channels;
2246 sband = NULL;
2247 }
62dad5b0 2248
39162dbe
FF
2249 if (!sband)
2250 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 2251
3430098a
FF
2252 if (!sband || idx >= sband->n_channels) {
2253 spin_unlock_irqrestore(&common->cc_lock, flags);
2254 return -ENOENT;
4f1a5a4b 2255 }
62dad5b0 2256
3430098a
FF
2257 chan = &sband->channels[idx];
2258 pos = chan->hw_value;
2259 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2260 survey->channel = chan;
2261 spin_unlock_irqrestore(&common->cc_lock, flags);
2262
62dad5b0
BP
2263 return 0;
2264}
2265
0c98de65
S
2266static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2267{
bce048d7
JM
2268 struct ath_wiphy *aphy = hw->priv;
2269 struct ath_softc *sc = aphy->sc;
0c98de65 2270
3d832611 2271 mutex_lock(&sc->mutex);
8089cc47 2272 if (ath9k_wiphy_scanning(sc)) {
8089cc47 2273 /*
30888338
LR
2274 * There is a race here in mac80211 but fixing it requires
2275 * we revisit how we handle the scan complete callback.
2276 * After mac80211 fixes we will not have configured hardware
2277 * to the home channel nor would we have configured the RX
2278 * filter yet.
8089cc47 2279 */
3d832611 2280 mutex_unlock(&sc->mutex);
8089cc47
JM
2281 return;
2282 }
2283
2284 aphy->state = ATH_WIPHY_SCAN;
2285 ath9k_wiphy_pause_all_forced(sc, aphy);
3d832611 2286 mutex_unlock(&sc->mutex);
0c98de65
S
2287}
2288
30888338
LR
2289/*
2290 * XXX: this requires a revisit after the driver
2291 * scan_complete gets moved to another place/removed in mac80211.
2292 */
0c98de65
S
2293static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2294{
bce048d7
JM
2295 struct ath_wiphy *aphy = hw->priv;
2296 struct ath_softc *sc = aphy->sc;
0c98de65 2297
3d832611 2298 mutex_lock(&sc->mutex);
8089cc47 2299 aphy->state = ATH_WIPHY_ACTIVE;
3d832611 2300 mutex_unlock(&sc->mutex);
0c98de65
S
2301}
2302
e239d859
FF
2303static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2304{
2305 struct ath_wiphy *aphy = hw->priv;
2306 struct ath_softc *sc = aphy->sc;
2307 struct ath_hw *ah = sc->sc_ah;
2308
2309 mutex_lock(&sc->mutex);
2310 ah->coverage_class = coverage_class;
2311 ath9k_hw_init_global_settings(ah);
2312 mutex_unlock(&sc->mutex);
2313}
2314
6baff7f9 2315struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2316 .tx = ath9k_tx,
2317 .start = ath9k_start,
2318 .stop = ath9k_stop,
2319 .add_interface = ath9k_add_interface,
6b3b991d 2320 .change_interface = ath9k_change_interface,
8feceb67
VT
2321 .remove_interface = ath9k_remove_interface,
2322 .config = ath9k_config,
8feceb67 2323 .configure_filter = ath9k_configure_filter,
4ca77860
JB
2324 .sta_add = ath9k_sta_add,
2325 .sta_remove = ath9k_sta_remove,
8feceb67 2326 .conf_tx = ath9k_conf_tx,
8feceb67 2327 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2328 .set_key = ath9k_set_key,
8feceb67 2329 .get_tsf = ath9k_get_tsf,
3b5d665b 2330 .set_tsf = ath9k_set_tsf,
8feceb67 2331 .reset_tsf = ath9k_reset_tsf,
4233df6b 2332 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2333 .get_survey = ath9k_get_survey,
0c98de65
S
2334 .sw_scan_start = ath9k_sw_scan_start,
2335 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 2336 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2337 .set_coverage_class = ath9k_set_coverage_class,
8feceb67 2338};
This page took 0.626555 seconds and 5 git commands to generate.