Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
394cf0a1 | 18 | #include "ath9k.h" |
f078f209 LR |
19 | |
20 | #define ATH_PCI_VERSION "0.1" | |
21 | ||
f078f209 LR |
22 | static char *dev_info = "ath9k"; |
23 | ||
24 | MODULE_AUTHOR("Atheros Communications"); | |
25 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
26 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
27 | MODULE_LICENSE("Dual BSD/GPL"); | |
28 | ||
b3bd89ce JM |
29 | static int modparam_nohwcrypt; |
30 | module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); | |
31 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); | |
32 | ||
5f8e077c LR |
33 | /* We use the hw_value as an index into our private channel structure */ |
34 | ||
35 | #define CHAN2G(_freq, _idx) { \ | |
36 | .center_freq = (_freq), \ | |
37 | .hw_value = (_idx), \ | |
eeddfd9d | 38 | .max_power = 20, \ |
5f8e077c LR |
39 | } |
40 | ||
41 | #define CHAN5G(_freq, _idx) { \ | |
42 | .band = IEEE80211_BAND_5GHZ, \ | |
43 | .center_freq = (_freq), \ | |
44 | .hw_value = (_idx), \ | |
eeddfd9d | 45 | .max_power = 20, \ |
5f8e077c LR |
46 | } |
47 | ||
48 | /* Some 2 GHz radios are actually tunable on 2312-2732 | |
49 | * on 5 MHz steps, we support the channels which we know | |
50 | * we have calibration data for all cards though to make | |
51 | * this static */ | |
52 | static struct ieee80211_channel ath9k_2ghz_chantable[] = { | |
53 | CHAN2G(2412, 0), /* Channel 1 */ | |
54 | CHAN2G(2417, 1), /* Channel 2 */ | |
55 | CHAN2G(2422, 2), /* Channel 3 */ | |
56 | CHAN2G(2427, 3), /* Channel 4 */ | |
57 | CHAN2G(2432, 4), /* Channel 5 */ | |
58 | CHAN2G(2437, 5), /* Channel 6 */ | |
59 | CHAN2G(2442, 6), /* Channel 7 */ | |
60 | CHAN2G(2447, 7), /* Channel 8 */ | |
61 | CHAN2G(2452, 8), /* Channel 9 */ | |
62 | CHAN2G(2457, 9), /* Channel 10 */ | |
63 | CHAN2G(2462, 10), /* Channel 11 */ | |
64 | CHAN2G(2467, 11), /* Channel 12 */ | |
65 | CHAN2G(2472, 12), /* Channel 13 */ | |
66 | CHAN2G(2484, 13), /* Channel 14 */ | |
67 | }; | |
68 | ||
69 | /* Some 5 GHz radios are actually tunable on XXXX-YYYY | |
70 | * on 5 MHz steps, we support the channels which we know | |
71 | * we have calibration data for all cards though to make | |
72 | * this static */ | |
73 | static struct ieee80211_channel ath9k_5ghz_chantable[] = { | |
74 | /* _We_ call this UNII 1 */ | |
75 | CHAN5G(5180, 14), /* Channel 36 */ | |
76 | CHAN5G(5200, 15), /* Channel 40 */ | |
77 | CHAN5G(5220, 16), /* Channel 44 */ | |
78 | CHAN5G(5240, 17), /* Channel 48 */ | |
79 | /* _We_ call this UNII 2 */ | |
80 | CHAN5G(5260, 18), /* Channel 52 */ | |
81 | CHAN5G(5280, 19), /* Channel 56 */ | |
82 | CHAN5G(5300, 20), /* Channel 60 */ | |
83 | CHAN5G(5320, 21), /* Channel 64 */ | |
84 | /* _We_ call this "Middle band" */ | |
85 | CHAN5G(5500, 22), /* Channel 100 */ | |
86 | CHAN5G(5520, 23), /* Channel 104 */ | |
87 | CHAN5G(5540, 24), /* Channel 108 */ | |
88 | CHAN5G(5560, 25), /* Channel 112 */ | |
89 | CHAN5G(5580, 26), /* Channel 116 */ | |
90 | CHAN5G(5600, 27), /* Channel 120 */ | |
91 | CHAN5G(5620, 28), /* Channel 124 */ | |
92 | CHAN5G(5640, 29), /* Channel 128 */ | |
93 | CHAN5G(5660, 30), /* Channel 132 */ | |
94 | CHAN5G(5680, 31), /* Channel 136 */ | |
95 | CHAN5G(5700, 32), /* Channel 140 */ | |
96 | /* _We_ call this UNII 3 */ | |
97 | CHAN5G(5745, 33), /* Channel 149 */ | |
98 | CHAN5G(5765, 34), /* Channel 153 */ | |
99 | CHAN5G(5785, 35), /* Channel 157 */ | |
100 | CHAN5G(5805, 36), /* Channel 161 */ | |
101 | CHAN5G(5825, 37), /* Channel 165 */ | |
102 | }; | |
103 | ||
ce111bad LR |
104 | static void ath_cache_conf_rate(struct ath_softc *sc, |
105 | struct ieee80211_conf *conf) | |
ff37e337 | 106 | { |
030bb495 LR |
107 | switch (conf->channel->band) { |
108 | case IEEE80211_BAND_2GHZ: | |
109 | if (conf_is_ht20(conf)) | |
110 | sc->cur_rate_table = | |
111 | sc->hw_rate_table[ATH9K_MODE_11NG_HT20]; | |
112 | else if (conf_is_ht40_minus(conf)) | |
113 | sc->cur_rate_table = | |
114 | sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS]; | |
115 | else if (conf_is_ht40_plus(conf)) | |
116 | sc->cur_rate_table = | |
117 | sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS]; | |
96742256 | 118 | else |
030bb495 LR |
119 | sc->cur_rate_table = |
120 | sc->hw_rate_table[ATH9K_MODE_11G]; | |
030bb495 LR |
121 | break; |
122 | case IEEE80211_BAND_5GHZ: | |
123 | if (conf_is_ht20(conf)) | |
124 | sc->cur_rate_table = | |
125 | sc->hw_rate_table[ATH9K_MODE_11NA_HT20]; | |
126 | else if (conf_is_ht40_minus(conf)) | |
127 | sc->cur_rate_table = | |
128 | sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS]; | |
129 | else if (conf_is_ht40_plus(conf)) | |
130 | sc->cur_rate_table = | |
131 | sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS]; | |
132 | else | |
96742256 LR |
133 | sc->cur_rate_table = |
134 | sc->hw_rate_table[ATH9K_MODE_11A]; | |
030bb495 LR |
135 | break; |
136 | default: | |
ce111bad | 137 | BUG_ON(1); |
030bb495 LR |
138 | break; |
139 | } | |
ff37e337 S |
140 | } |
141 | ||
142 | static void ath_update_txpow(struct ath_softc *sc) | |
143 | { | |
cbe61d8a | 144 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
145 | u32 txpow; |
146 | ||
17d7904d S |
147 | if (sc->curtxpow != sc->config.txpowlimit) { |
148 | ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit); | |
ff37e337 S |
149 | /* read back in case value is clamped */ |
150 | ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow); | |
17d7904d | 151 | sc->curtxpow = txpow; |
ff37e337 S |
152 | } |
153 | } | |
154 | ||
155 | static u8 parse_mpdudensity(u8 mpdudensity) | |
156 | { | |
157 | /* | |
158 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
159 | * 0 for no restriction | |
160 | * 1 for 1/4 us | |
161 | * 2 for 1/2 us | |
162 | * 3 for 1 us | |
163 | * 4 for 2 us | |
164 | * 5 for 4 us | |
165 | * 6 for 8 us | |
166 | * 7 for 16 us | |
167 | */ | |
168 | switch (mpdudensity) { | |
169 | case 0: | |
170 | return 0; | |
171 | case 1: | |
172 | case 2: | |
173 | case 3: | |
174 | /* Our lower layer calculations limit our precision to | |
175 | 1 microsecond */ | |
176 | return 1; | |
177 | case 4: | |
178 | return 2; | |
179 | case 5: | |
180 | return 4; | |
181 | case 6: | |
182 | return 8; | |
183 | case 7: | |
184 | return 16; | |
185 | default: | |
186 | return 0; | |
187 | } | |
188 | } | |
189 | ||
190 | static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band) | |
191 | { | |
4f0fc7c3 | 192 | const struct ath_rate_table *rate_table = NULL; |
ff37e337 S |
193 | struct ieee80211_supported_band *sband; |
194 | struct ieee80211_rate *rate; | |
195 | int i, maxrates; | |
196 | ||
197 | switch (band) { | |
198 | case IEEE80211_BAND_2GHZ: | |
199 | rate_table = sc->hw_rate_table[ATH9K_MODE_11G]; | |
200 | break; | |
201 | case IEEE80211_BAND_5GHZ: | |
202 | rate_table = sc->hw_rate_table[ATH9K_MODE_11A]; | |
203 | break; | |
204 | default: | |
205 | break; | |
206 | } | |
207 | ||
208 | if (rate_table == NULL) | |
209 | return; | |
210 | ||
211 | sband = &sc->sbands[band]; | |
212 | rate = sc->rates[band]; | |
213 | ||
214 | if (rate_table->rate_cnt > ATH_RATE_MAX) | |
215 | maxrates = ATH_RATE_MAX; | |
216 | else | |
217 | maxrates = rate_table->rate_cnt; | |
218 | ||
219 | for (i = 0; i < maxrates; i++) { | |
220 | rate[i].bitrate = rate_table->info[i].ratekbps / 100; | |
221 | rate[i].hw_value = rate_table->info[i].ratecode; | |
f46730d1 S |
222 | if (rate_table->info[i].short_preamble) { |
223 | rate[i].hw_value_short = rate_table->info[i].ratecode | | |
224 | rate_table->info[i].short_preamble; | |
225 | rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE; | |
226 | } | |
ff37e337 | 227 | sband->n_bitrates++; |
f46730d1 | 228 | |
04bd4638 S |
229 | DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n", |
230 | rate[i].bitrate / 10, rate[i].hw_value); | |
ff37e337 S |
231 | } |
232 | } | |
233 | ||
82880a7c VT |
234 | static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc, |
235 | struct ieee80211_hw *hw) | |
236 | { | |
237 | struct ieee80211_channel *curchan = hw->conf.channel; | |
238 | struct ath9k_channel *channel; | |
239 | u8 chan_idx; | |
240 | ||
241 | chan_idx = curchan->hw_value; | |
242 | channel = &sc->sc_ah->channels[chan_idx]; | |
243 | ath9k_update_ichannel(sc, hw, channel); | |
244 | return channel; | |
245 | } | |
246 | ||
ff37e337 S |
247 | /* |
248 | * Set/change channels. If the channel is really being changed, it's done | |
249 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
250 | * DMA, then restart stuff. | |
251 | */ | |
0e2dedf9 JM |
252 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, |
253 | struct ath9k_channel *hchan) | |
ff37e337 | 254 | { |
cbe61d8a | 255 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 | 256 | bool fastcc = true, stopped; |
ae8d2858 LR |
257 | struct ieee80211_channel *channel = hw->conf.channel; |
258 | int r; | |
ff37e337 S |
259 | |
260 | if (sc->sc_flags & SC_OP_INVALID) | |
261 | return -EIO; | |
262 | ||
3cbb5dd7 VN |
263 | ath9k_ps_wakeup(sc); |
264 | ||
c0d7c7af LR |
265 | /* |
266 | * This is only performed if the channel settings have | |
267 | * actually changed. | |
268 | * | |
269 | * To switch channels clear any pending DMA operations; | |
270 | * wait long enough for the RX fifo to drain, reset the | |
271 | * hardware at the new frequency, and then re-enable | |
272 | * the relevant bits of the h/w. | |
273 | */ | |
274 | ath9k_hw_set_interrupts(ah, 0); | |
043a0405 | 275 | ath_drain_all_txq(sc, false); |
c0d7c7af | 276 | stopped = ath_stoprecv(sc); |
ff37e337 | 277 | |
c0d7c7af LR |
278 | /* XXX: do not flush receive queue here. We don't want |
279 | * to flush data frames already in queue because of | |
280 | * changing channel. */ | |
ff37e337 | 281 | |
c0d7c7af LR |
282 | if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET)) |
283 | fastcc = false; | |
284 | ||
285 | DPRINTF(sc, ATH_DBG_CONFIG, | |
286 | "(%u MHz) -> (%u MHz), chanwidth: %d\n", | |
2660b81a | 287 | sc->sc_ah->curchan->channel, |
c0d7c7af | 288 | channel->center_freq, sc->tx_chan_width); |
ff37e337 | 289 | |
c0d7c7af LR |
290 | spin_lock_bh(&sc->sc_resetlock); |
291 | ||
292 | r = ath9k_hw_reset(ah, hchan, fastcc); | |
293 | if (r) { | |
294 | DPRINTF(sc, ATH_DBG_FATAL, | |
295 | "Unable to reset channel (%u Mhz) " | |
6b45784f | 296 | "reset status %d\n", |
c0d7c7af LR |
297 | channel->center_freq, r); |
298 | spin_unlock_bh(&sc->sc_resetlock); | |
299 | return r; | |
ff37e337 | 300 | } |
c0d7c7af LR |
301 | spin_unlock_bh(&sc->sc_resetlock); |
302 | ||
c0d7c7af LR |
303 | sc->sc_flags &= ~SC_OP_FULL_RESET; |
304 | ||
305 | if (ath_startrecv(sc) != 0) { | |
306 | DPRINTF(sc, ATH_DBG_FATAL, | |
307 | "Unable to restart recv logic\n"); | |
308 | return -EIO; | |
309 | } | |
310 | ||
311 | ath_cache_conf_rate(sc, &hw->conf); | |
312 | ath_update_txpow(sc); | |
17d7904d | 313 | ath9k_hw_set_interrupts(ah, sc->imask); |
3cbb5dd7 | 314 | ath9k_ps_restore(sc); |
ff37e337 S |
315 | return 0; |
316 | } | |
317 | ||
318 | /* | |
319 | * This routine performs the periodic noise floor calibration function | |
320 | * that is used to adjust and optimize the chip performance. This | |
321 | * takes environmental changes (location, temperature) into account. | |
322 | * When the task is complete, it reschedules itself depending on the | |
323 | * appropriate interval that was calculated. | |
324 | */ | |
325 | static void ath_ani_calibrate(unsigned long data) | |
326 | { | |
20977d3e S |
327 | struct ath_softc *sc = (struct ath_softc *)data; |
328 | struct ath_hw *ah = sc->sc_ah; | |
ff37e337 S |
329 | bool longcal = false; |
330 | bool shortcal = false; | |
331 | bool aniflag = false; | |
332 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
20977d3e | 333 | u32 cal_interval, short_cal_interval; |
ff37e337 | 334 | |
20977d3e S |
335 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
336 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 S |
337 | |
338 | /* | |
339 | * don't calibrate when we're scanning. | |
340 | * we are most likely not on our home channel. | |
341 | */ | |
0c98de65 | 342 | if (sc->sc_flags & SC_OP_SCANNING) |
20977d3e | 343 | goto set_timer; |
ff37e337 | 344 | |
1ffc1c61 JM |
345 | /* Only calibrate if awake */ |
346 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
347 | goto set_timer; | |
348 | ||
349 | ath9k_ps_wakeup(sc); | |
350 | ||
ff37e337 | 351 | /* Long calibration runs independently of short calibration. */ |
17d7904d | 352 | if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { |
ff37e337 | 353 | longcal = true; |
04bd4638 | 354 | DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
17d7904d | 355 | sc->ani.longcal_timer = timestamp; |
ff37e337 S |
356 | } |
357 | ||
17d7904d S |
358 | /* Short calibration applies only while caldone is false */ |
359 | if (!sc->ani.caldone) { | |
20977d3e | 360 | if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) { |
ff37e337 | 361 | shortcal = true; |
04bd4638 | 362 | DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies); |
17d7904d S |
363 | sc->ani.shortcal_timer = timestamp; |
364 | sc->ani.resetcal_timer = timestamp; | |
ff37e337 S |
365 | } |
366 | } else { | |
17d7904d | 367 | if ((timestamp - sc->ani.resetcal_timer) >= |
ff37e337 | 368 | ATH_RESTART_CALINTERVAL) { |
17d7904d S |
369 | sc->ani.caldone = ath9k_hw_reset_calvalid(ah); |
370 | if (sc->ani.caldone) | |
371 | sc->ani.resetcal_timer = timestamp; | |
ff37e337 S |
372 | } |
373 | } | |
374 | ||
375 | /* Verify whether we must check ANI */ | |
20977d3e | 376 | if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) { |
ff37e337 | 377 | aniflag = true; |
17d7904d | 378 | sc->ani.checkani_timer = timestamp; |
ff37e337 S |
379 | } |
380 | ||
381 | /* Skip all processing if there's nothing to do. */ | |
382 | if (longcal || shortcal || aniflag) { | |
383 | /* Call ANI routine if necessary */ | |
384 | if (aniflag) | |
20977d3e | 385 | ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan); |
ff37e337 S |
386 | |
387 | /* Perform calibration if necessary */ | |
388 | if (longcal || shortcal) { | |
379f0440 S |
389 | sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan, |
390 | sc->rx_chainmask, longcal); | |
391 | ||
392 | if (longcal) | |
393 | sc->ani.noise_floor = ath9k_hw_getchan_noise(ah, | |
394 | ah->curchan); | |
395 | ||
396 | DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n", | |
397 | ah->curchan->channel, ah->curchan->channelFlags, | |
398 | sc->ani.noise_floor); | |
ff37e337 S |
399 | } |
400 | } | |
401 | ||
1ffc1c61 JM |
402 | ath9k_ps_restore(sc); |
403 | ||
20977d3e | 404 | set_timer: |
ff37e337 S |
405 | /* |
406 | * Set timer interval based on previous results. | |
407 | * The interval must be the shortest necessary to satisfy ANI, | |
408 | * short calibration and long calibration. | |
409 | */ | |
aac9207e | 410 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 411 | if (sc->sc_ah->config.enable_ani) |
aac9207e | 412 | cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL); |
17d7904d | 413 | if (!sc->ani.caldone) |
20977d3e | 414 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 415 | |
17d7904d | 416 | mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
ff37e337 S |
417 | } |
418 | ||
415f738e S |
419 | static void ath_start_ani(struct ath_softc *sc) |
420 | { | |
421 | unsigned long timestamp = jiffies_to_msecs(jiffies); | |
422 | ||
423 | sc->ani.longcal_timer = timestamp; | |
424 | sc->ani.shortcal_timer = timestamp; | |
425 | sc->ani.checkani_timer = timestamp; | |
426 | ||
427 | mod_timer(&sc->ani.timer, | |
428 | jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL)); | |
429 | } | |
430 | ||
ff37e337 S |
431 | /* |
432 | * Update tx/rx chainmask. For legacy association, | |
433 | * hard code chainmask to 1x1, for 11n association, use | |
c97c92d9 VT |
434 | * the chainmask configuration, for bt coexistence, use |
435 | * the chainmask configuration even in legacy mode. | |
ff37e337 | 436 | */ |
0e2dedf9 | 437 | void ath_update_chainmask(struct ath_softc *sc, int is_ht) |
ff37e337 | 438 | { |
c97c92d9 | 439 | if (is_ht || |
2660b81a S |
440 | (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) { |
441 | sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask; | |
442 | sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask; | |
ff37e337 | 443 | } else { |
17d7904d S |
444 | sc->tx_chainmask = 1; |
445 | sc->rx_chainmask = 1; | |
ff37e337 S |
446 | } |
447 | ||
04bd4638 | 448 | DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n", |
17d7904d | 449 | sc->tx_chainmask, sc->rx_chainmask); |
ff37e337 S |
450 | } |
451 | ||
452 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
453 | { | |
454 | struct ath_node *an; | |
455 | ||
456 | an = (struct ath_node *)sta->drv_priv; | |
457 | ||
87792efc | 458 | if (sc->sc_flags & SC_OP_TXAGGR) { |
ff37e337 | 459 | ath_tx_node_init(sc, an); |
87792efc S |
460 | an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR + |
461 | sta->ht_cap.ampdu_factor); | |
462 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
463 | } | |
ff37e337 S |
464 | } |
465 | ||
466 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
467 | { | |
468 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
469 | ||
470 | if (sc->sc_flags & SC_OP_TXAGGR) | |
471 | ath_tx_node_cleanup(sc, an); | |
472 | } | |
473 | ||
474 | static void ath9k_tasklet(unsigned long data) | |
475 | { | |
476 | struct ath_softc *sc = (struct ath_softc *)data; | |
17d7904d | 477 | u32 status = sc->intrstatus; |
ff37e337 | 478 | |
153e080d VT |
479 | ath9k_ps_wakeup(sc); |
480 | ||
ff37e337 | 481 | if (status & ATH9K_INT_FATAL) { |
ff37e337 | 482 | ath_reset(sc, false); |
153e080d | 483 | ath9k_ps_restore(sc); |
ff37e337 | 484 | return; |
063d8be3 | 485 | } |
ff37e337 | 486 | |
063d8be3 S |
487 | if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) { |
488 | spin_lock_bh(&sc->rx.rxflushlock); | |
489 | ath_rx_tasklet(sc, 0); | |
490 | spin_unlock_bh(&sc->rx.rxflushlock); | |
ff37e337 S |
491 | } |
492 | ||
063d8be3 S |
493 | if (status & ATH9K_INT_TX) |
494 | ath_tx_tasklet(sc); | |
495 | ||
54ce846e JM |
496 | if ((status & ATH9K_INT_TSFOOR) && |
497 | (sc->hw->conf.flags & IEEE80211_CONF_PS)) { | |
498 | /* | |
499 | * TSF sync does not look correct; remain awake to sync with | |
500 | * the next Beacon. | |
501 | */ | |
502 | DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n"); | |
ccdfeab6 | 503 | sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC; |
54ce846e JM |
504 | } |
505 | ||
ff37e337 | 506 | /* re-enable hardware interrupt */ |
17d7904d | 507 | ath9k_hw_set_interrupts(sc->sc_ah, sc->imask); |
153e080d | 508 | ath9k_ps_restore(sc); |
ff37e337 S |
509 | } |
510 | ||
6baff7f9 | 511 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 512 | { |
063d8be3 S |
513 | #define SCHED_INTR ( \ |
514 | ATH9K_INT_FATAL | \ | |
515 | ATH9K_INT_RXORN | \ | |
516 | ATH9K_INT_RXEOL | \ | |
517 | ATH9K_INT_RX | \ | |
518 | ATH9K_INT_TX | \ | |
519 | ATH9K_INT_BMISS | \ | |
520 | ATH9K_INT_CST | \ | |
521 | ATH9K_INT_TSFOOR) | |
522 | ||
ff37e337 | 523 | struct ath_softc *sc = dev; |
cbe61d8a | 524 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
525 | enum ath9k_int status; |
526 | bool sched = false; | |
527 | ||
063d8be3 S |
528 | /* |
529 | * The hardware is not ready/present, don't | |
530 | * touch anything. Note this can happen early | |
531 | * on if the IRQ is shared. | |
532 | */ | |
533 | if (sc->sc_flags & SC_OP_INVALID) | |
534 | return IRQ_NONE; | |
ff37e337 | 535 | |
063d8be3 S |
536 | |
537 | /* shared irq, not for us */ | |
538 | ||
153e080d | 539 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 540 | return IRQ_NONE; |
063d8be3 S |
541 | |
542 | /* | |
543 | * Figure out the reason(s) for the interrupt. Note | |
544 | * that the hal returns a pseudo-ISR that may include | |
545 | * bits we haven't explicitly enabled so we mask the | |
546 | * value to insure we only process bits we requested. | |
547 | */ | |
548 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
549 | status &= sc->imask; /* discard unasked-for bits */ | |
ff37e337 | 550 | |
063d8be3 S |
551 | /* |
552 | * If there are no status bits set, then this interrupt was not | |
553 | * for me (should have been caught above). | |
554 | */ | |
153e080d | 555 | if (!status) |
063d8be3 | 556 | return IRQ_NONE; |
ff37e337 | 557 | |
063d8be3 S |
558 | /* Cache the status */ |
559 | sc->intrstatus = status; | |
560 | ||
561 | if (status & SCHED_INTR) | |
562 | sched = true; | |
563 | ||
564 | /* | |
565 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
566 | * chip immediately. | |
567 | */ | |
568 | if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN)) | |
569 | goto chip_reset; | |
570 | ||
571 | if (status & ATH9K_INT_SWBA) | |
572 | tasklet_schedule(&sc->bcon_tasklet); | |
573 | ||
574 | if (status & ATH9K_INT_TXURN) | |
575 | ath9k_hw_updatetxtriglevel(ah, true); | |
576 | ||
577 | if (status & ATH9K_INT_MIB) { | |
ff37e337 | 578 | /* |
063d8be3 S |
579 | * Disable interrupts until we service the MIB |
580 | * interrupt; otherwise it will continue to | |
581 | * fire. | |
ff37e337 | 582 | */ |
063d8be3 S |
583 | ath9k_hw_set_interrupts(ah, 0); |
584 | /* | |
585 | * Let the hal handle the event. We assume | |
586 | * it will clear whatever condition caused | |
587 | * the interrupt. | |
588 | */ | |
589 | ath9k_hw_procmibevent(ah, &sc->nodestats); | |
590 | ath9k_hw_set_interrupts(ah, sc->imask); | |
591 | } | |
ff37e337 | 592 | |
153e080d VT |
593 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
594 | if (status & ATH9K_INT_TIM_TIMER) { | |
063d8be3 S |
595 | /* Clear RxAbort bit so that we can |
596 | * receive frames */ | |
597 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
153e080d | 598 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
063d8be3 | 599 | sc->sc_flags |= SC_OP_WAIT_FOR_BEACON; |
ff37e337 | 600 | } |
063d8be3 S |
601 | |
602 | chip_reset: | |
ff37e337 | 603 | |
817e11de S |
604 | ath_debug_stat_interrupt(sc, status); |
605 | ||
ff37e337 S |
606 | if (sched) { |
607 | /* turn off every interrupt except SWBA */ | |
17d7904d | 608 | ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA)); |
ff37e337 S |
609 | tasklet_schedule(&sc->intr_tq); |
610 | } | |
611 | ||
612 | return IRQ_HANDLED; | |
063d8be3 S |
613 | |
614 | #undef SCHED_INTR | |
ff37e337 S |
615 | } |
616 | ||
f078f209 | 617 | static u32 ath_get_extchanmode(struct ath_softc *sc, |
99405f93 | 618 | struct ieee80211_channel *chan, |
094d05dc | 619 | enum nl80211_channel_type channel_type) |
f078f209 LR |
620 | { |
621 | u32 chanmode = 0; | |
f078f209 LR |
622 | |
623 | switch (chan->band) { | |
624 | case IEEE80211_BAND_2GHZ: | |
094d05dc S |
625 | switch(channel_type) { |
626 | case NL80211_CHAN_NO_HT: | |
627 | case NL80211_CHAN_HT20: | |
f078f209 | 628 | chanmode = CHANNEL_G_HT20; |
094d05dc S |
629 | break; |
630 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 631 | chanmode = CHANNEL_G_HT40PLUS; |
094d05dc S |
632 | break; |
633 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 634 | chanmode = CHANNEL_G_HT40MINUS; |
094d05dc S |
635 | break; |
636 | } | |
f078f209 LR |
637 | break; |
638 | case IEEE80211_BAND_5GHZ: | |
094d05dc S |
639 | switch(channel_type) { |
640 | case NL80211_CHAN_NO_HT: | |
641 | case NL80211_CHAN_HT20: | |
f078f209 | 642 | chanmode = CHANNEL_A_HT20; |
094d05dc S |
643 | break; |
644 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 645 | chanmode = CHANNEL_A_HT40PLUS; |
094d05dc S |
646 | break; |
647 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 648 | chanmode = CHANNEL_A_HT40MINUS; |
094d05dc S |
649 | break; |
650 | } | |
f078f209 LR |
651 | break; |
652 | default: | |
653 | break; | |
654 | } | |
655 | ||
656 | return chanmode; | |
657 | } | |
658 | ||
6ace2891 | 659 | static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key, |
3f53dd64 JM |
660 | struct ath9k_keyval *hk, const u8 *addr, |
661 | bool authenticator) | |
f078f209 | 662 | { |
6ace2891 JM |
663 | const u8 *key_rxmic; |
664 | const u8 *key_txmic; | |
f078f209 | 665 | |
6ace2891 JM |
666 | key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY; |
667 | key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY; | |
f078f209 LR |
668 | |
669 | if (addr == NULL) { | |
d216aaa6 JM |
670 | /* |
671 | * Group key installation - only two key cache entries are used | |
672 | * regardless of splitmic capability since group key is only | |
673 | * used either for TX or RX. | |
674 | */ | |
3f53dd64 JM |
675 | if (authenticator) { |
676 | memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); | |
677 | memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic)); | |
678 | } else { | |
679 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); | |
680 | memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic)); | |
681 | } | |
d216aaa6 | 682 | return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr); |
f078f209 | 683 | } |
17d7904d | 684 | if (!sc->splitmic) { |
d216aaa6 | 685 | /* TX and RX keys share the same key cache entry. */ |
f078f209 LR |
686 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); |
687 | memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic)); | |
d216aaa6 | 688 | return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr); |
f078f209 | 689 | } |
d216aaa6 JM |
690 | |
691 | /* Separate key cache entries for TX and RX */ | |
692 | ||
693 | /* TX key goes at first index, RX key at +32. */ | |
f078f209 | 694 | memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); |
d216aaa6 JM |
695 | if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) { |
696 | /* TX MIC entry failed. No need to proceed further */ | |
d8baa939 | 697 | DPRINTF(sc, ATH_DBG_FATAL, |
04bd4638 | 698 | "Setting TX MIC Key Failed\n"); |
f078f209 LR |
699 | return 0; |
700 | } | |
701 | ||
702 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); | |
703 | /* XXX delete tx key on failure? */ | |
d216aaa6 | 704 | return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr); |
6ace2891 JM |
705 | } |
706 | ||
707 | static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc) | |
708 | { | |
709 | int i; | |
710 | ||
17d7904d S |
711 | for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) { |
712 | if (test_bit(i, sc->keymap) || | |
713 | test_bit(i + 64, sc->keymap)) | |
6ace2891 | 714 | continue; /* At least one part of TKIP key allocated */ |
17d7904d S |
715 | if (sc->splitmic && |
716 | (test_bit(i + 32, sc->keymap) || | |
717 | test_bit(i + 64 + 32, sc->keymap))) | |
6ace2891 JM |
718 | continue; /* At least one part of TKIP key allocated */ |
719 | ||
720 | /* Found a free slot for a TKIP key */ | |
721 | return i; | |
722 | } | |
723 | return -1; | |
724 | } | |
725 | ||
726 | static int ath_reserve_key_cache_slot(struct ath_softc *sc) | |
727 | { | |
728 | int i; | |
729 | ||
730 | /* First, try to find slots that would not be available for TKIP. */ | |
17d7904d S |
731 | if (sc->splitmic) { |
732 | for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) { | |
733 | if (!test_bit(i, sc->keymap) && | |
734 | (test_bit(i + 32, sc->keymap) || | |
735 | test_bit(i + 64, sc->keymap) || | |
736 | test_bit(i + 64 + 32, sc->keymap))) | |
6ace2891 | 737 | return i; |
17d7904d S |
738 | if (!test_bit(i + 32, sc->keymap) && |
739 | (test_bit(i, sc->keymap) || | |
740 | test_bit(i + 64, sc->keymap) || | |
741 | test_bit(i + 64 + 32, sc->keymap))) | |
6ace2891 | 742 | return i + 32; |
17d7904d S |
743 | if (!test_bit(i + 64, sc->keymap) && |
744 | (test_bit(i , sc->keymap) || | |
745 | test_bit(i + 32, sc->keymap) || | |
746 | test_bit(i + 64 + 32, sc->keymap))) | |
ea612132 | 747 | return i + 64; |
17d7904d S |
748 | if (!test_bit(i + 64 + 32, sc->keymap) && |
749 | (test_bit(i, sc->keymap) || | |
750 | test_bit(i + 32, sc->keymap) || | |
751 | test_bit(i + 64, sc->keymap))) | |
ea612132 | 752 | return i + 64 + 32; |
6ace2891 JM |
753 | } |
754 | } else { | |
17d7904d S |
755 | for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) { |
756 | if (!test_bit(i, sc->keymap) && | |
757 | test_bit(i + 64, sc->keymap)) | |
6ace2891 | 758 | return i; |
17d7904d S |
759 | if (test_bit(i, sc->keymap) && |
760 | !test_bit(i + 64, sc->keymap)) | |
6ace2891 JM |
761 | return i + 64; |
762 | } | |
763 | } | |
764 | ||
765 | /* No partially used TKIP slots, pick any available slot */ | |
17d7904d | 766 | for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) { |
be2864cf JM |
767 | /* Do not allow slots that could be needed for TKIP group keys |
768 | * to be used. This limitation could be removed if we know that | |
769 | * TKIP will not be used. */ | |
770 | if (i >= 64 && i < 64 + IEEE80211_WEP_NKID) | |
771 | continue; | |
17d7904d | 772 | if (sc->splitmic) { |
be2864cf JM |
773 | if (i >= 32 && i < 32 + IEEE80211_WEP_NKID) |
774 | continue; | |
775 | if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID) | |
776 | continue; | |
777 | } | |
778 | ||
17d7904d | 779 | if (!test_bit(i, sc->keymap)) |
6ace2891 JM |
780 | return i; /* Found a free slot for a key */ |
781 | } | |
782 | ||
783 | /* No free slot found */ | |
784 | return -1; | |
f078f209 LR |
785 | } |
786 | ||
787 | static int ath_key_config(struct ath_softc *sc, | |
3f53dd64 | 788 | struct ieee80211_vif *vif, |
dc822b5d | 789 | struct ieee80211_sta *sta, |
f078f209 LR |
790 | struct ieee80211_key_conf *key) |
791 | { | |
f078f209 LR |
792 | struct ath9k_keyval hk; |
793 | const u8 *mac = NULL; | |
794 | int ret = 0; | |
6ace2891 | 795 | int idx; |
f078f209 LR |
796 | |
797 | memset(&hk, 0, sizeof(hk)); | |
798 | ||
799 | switch (key->alg) { | |
800 | case ALG_WEP: | |
801 | hk.kv_type = ATH9K_CIPHER_WEP; | |
802 | break; | |
803 | case ALG_TKIP: | |
804 | hk.kv_type = ATH9K_CIPHER_TKIP; | |
805 | break; | |
806 | case ALG_CCMP: | |
807 | hk.kv_type = ATH9K_CIPHER_AES_CCM; | |
808 | break; | |
809 | default: | |
ca470b29 | 810 | return -EOPNOTSUPP; |
f078f209 LR |
811 | } |
812 | ||
6ace2891 | 813 | hk.kv_len = key->keylen; |
f078f209 LR |
814 | memcpy(hk.kv_val, key->key, key->keylen); |
815 | ||
6ace2891 JM |
816 | if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { |
817 | /* For now, use the default keys for broadcast keys. This may | |
818 | * need to change with virtual interfaces. */ | |
819 | idx = key->keyidx; | |
820 | } else if (key->keyidx) { | |
dc822b5d JB |
821 | if (WARN_ON(!sta)) |
822 | return -EOPNOTSUPP; | |
823 | mac = sta->addr; | |
824 | ||
6ace2891 JM |
825 | if (vif->type != NL80211_IFTYPE_AP) { |
826 | /* Only keyidx 0 should be used with unicast key, but | |
827 | * allow this for client mode for now. */ | |
828 | idx = key->keyidx; | |
829 | } else | |
830 | return -EIO; | |
f078f209 | 831 | } else { |
dc822b5d JB |
832 | if (WARN_ON(!sta)) |
833 | return -EOPNOTSUPP; | |
834 | mac = sta->addr; | |
835 | ||
6ace2891 JM |
836 | if (key->alg == ALG_TKIP) |
837 | idx = ath_reserve_key_cache_slot_tkip(sc); | |
838 | else | |
839 | idx = ath_reserve_key_cache_slot(sc); | |
840 | if (idx < 0) | |
ca470b29 | 841 | return -ENOSPC; /* no free key cache entries */ |
f078f209 LR |
842 | } |
843 | ||
844 | if (key->alg == ALG_TKIP) | |
3f53dd64 JM |
845 | ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac, |
846 | vif->type == NL80211_IFTYPE_AP); | |
f078f209 | 847 | else |
d216aaa6 | 848 | ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac); |
f078f209 LR |
849 | |
850 | if (!ret) | |
851 | return -EIO; | |
852 | ||
17d7904d | 853 | set_bit(idx, sc->keymap); |
6ace2891 | 854 | if (key->alg == ALG_TKIP) { |
17d7904d S |
855 | set_bit(idx + 64, sc->keymap); |
856 | if (sc->splitmic) { | |
857 | set_bit(idx + 32, sc->keymap); | |
858 | set_bit(idx + 64 + 32, sc->keymap); | |
6ace2891 JM |
859 | } |
860 | } | |
861 | ||
862 | return idx; | |
f078f209 LR |
863 | } |
864 | ||
865 | static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key) | |
866 | { | |
6ace2891 JM |
867 | ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx); |
868 | if (key->hw_key_idx < IEEE80211_WEP_NKID) | |
869 | return; | |
870 | ||
17d7904d | 871 | clear_bit(key->hw_key_idx, sc->keymap); |
6ace2891 JM |
872 | if (key->alg != ALG_TKIP) |
873 | return; | |
f078f209 | 874 | |
17d7904d S |
875 | clear_bit(key->hw_key_idx + 64, sc->keymap); |
876 | if (sc->splitmic) { | |
877 | clear_bit(key->hw_key_idx + 32, sc->keymap); | |
878 | clear_bit(key->hw_key_idx + 64 + 32, sc->keymap); | |
6ace2891 | 879 | } |
f078f209 LR |
880 | } |
881 | ||
eb2599ca S |
882 | static void setup_ht_cap(struct ath_softc *sc, |
883 | struct ieee80211_sta_ht_cap *ht_info) | |
f078f209 | 884 | { |
60653678 S |
885 | #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */ |
886 | #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */ | |
f078f209 | 887 | |
d9fe60de JB |
888 | ht_info->ht_supported = true; |
889 | ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | | |
890 | IEEE80211_HT_CAP_SM_PS | | |
891 | IEEE80211_HT_CAP_SGI_40 | | |
892 | IEEE80211_HT_CAP_DSSSCCK40; | |
f078f209 | 893 | |
60653678 S |
894 | ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536; |
895 | ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8; | |
eb2599ca | 896 | |
d9fe60de JB |
897 | /* set up supported mcs set */ |
898 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | |
eb2599ca | 899 | |
17d7904d | 900 | switch(sc->rx_chainmask) { |
eb2599ca S |
901 | case 1: |
902 | ht_info->mcs.rx_mask[0] = 0xff; | |
903 | break; | |
3c457265 | 904 | case 3: |
eb2599ca S |
905 | case 5: |
906 | case 7: | |
907 | default: | |
908 | ht_info->mcs.rx_mask[0] = 0xff; | |
909 | ht_info->mcs.rx_mask[1] = 0xff; | |
910 | break; | |
911 | } | |
912 | ||
d9fe60de | 913 | ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; |
f078f209 LR |
914 | } |
915 | ||
8feceb67 | 916 | static void ath9k_bss_assoc_info(struct ath_softc *sc, |
5640b08e | 917 | struct ieee80211_vif *vif, |
8feceb67 | 918 | struct ieee80211_bss_conf *bss_conf) |
f078f209 | 919 | { |
17d7904d | 920 | struct ath_vif *avp = (void *)vif->drv_priv; |
f078f209 | 921 | |
8feceb67 | 922 | if (bss_conf->assoc) { |
094d05dc | 923 | DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n", |
17d7904d | 924 | bss_conf->aid, sc->curbssid); |
f078f209 | 925 | |
8feceb67 | 926 | /* New association, store aid */ |
d97809db | 927 | if (avp->av_opmode == NL80211_IFTYPE_STATION) { |
17d7904d | 928 | sc->curaid = bss_conf->aid; |
ba52da58 | 929 | ath9k_hw_write_associd(sc); |
ccdfeab6 JM |
930 | |
931 | /* | |
932 | * Request a re-configuration of Beacon related timers | |
933 | * on the receipt of the first Beacon frame (i.e., | |
934 | * after time sync with the AP). | |
935 | */ | |
936 | sc->sc_flags |= SC_OP_BEACON_SYNC; | |
8feceb67 | 937 | } |
f078f209 | 938 | |
8feceb67 | 939 | /* Configure the beacon */ |
2c3db3d5 | 940 | ath_beacon_config(sc, vif); |
f078f209 | 941 | |
8feceb67 | 942 | /* Reset rssi stats */ |
17d7904d S |
943 | sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; |
944 | sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; | |
945 | sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; | |
946 | sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER; | |
f078f209 | 947 | |
415f738e | 948 | ath_start_ani(sc); |
8feceb67 | 949 | } else { |
1ffb0610 | 950 | DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); |
17d7904d | 951 | sc->curaid = 0; |
f078f209 | 952 | } |
8feceb67 | 953 | } |
f078f209 | 954 | |
8feceb67 VT |
955 | /********************************/ |
956 | /* LED functions */ | |
957 | /********************************/ | |
f078f209 | 958 | |
f2bffa7e VT |
959 | static void ath_led_blink_work(struct work_struct *work) |
960 | { | |
961 | struct ath_softc *sc = container_of(work, struct ath_softc, | |
962 | ath_led_blink_work.work); | |
963 | ||
964 | if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED)) | |
965 | return; | |
85067c06 VT |
966 | |
967 | if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) || | |
968 | (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE)) | |
969 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0); | |
970 | else | |
971 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, | |
972 | (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0); | |
f2bffa7e VT |
973 | |
974 | queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work, | |
975 | (sc->sc_flags & SC_OP_LED_ON) ? | |
976 | msecs_to_jiffies(sc->led_off_duration) : | |
977 | msecs_to_jiffies(sc->led_on_duration)); | |
978 | ||
85067c06 VT |
979 | sc->led_on_duration = sc->led_on_cnt ? |
980 | max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) : | |
981 | ATH_LED_ON_DURATION_IDLE; | |
982 | sc->led_off_duration = sc->led_off_cnt ? | |
983 | max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) : | |
984 | ATH_LED_OFF_DURATION_IDLE; | |
f2bffa7e VT |
985 | sc->led_on_cnt = sc->led_off_cnt = 0; |
986 | if (sc->sc_flags & SC_OP_LED_ON) | |
987 | sc->sc_flags &= ~SC_OP_LED_ON; | |
988 | else | |
989 | sc->sc_flags |= SC_OP_LED_ON; | |
990 | } | |
991 | ||
8feceb67 VT |
992 | static void ath_led_brightness(struct led_classdev *led_cdev, |
993 | enum led_brightness brightness) | |
994 | { | |
995 | struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev); | |
996 | struct ath_softc *sc = led->sc; | |
f078f209 | 997 | |
8feceb67 VT |
998 | switch (brightness) { |
999 | case LED_OFF: | |
1000 | if (led->led_type == ATH_LED_ASSOC || | |
f2bffa7e VT |
1001 | led->led_type == ATH_LED_RADIO) { |
1002 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, | |
1003 | (led->led_type == ATH_LED_RADIO)); | |
8feceb67 | 1004 | sc->sc_flags &= ~SC_OP_LED_ASSOCIATED; |
f2bffa7e VT |
1005 | if (led->led_type == ATH_LED_RADIO) |
1006 | sc->sc_flags &= ~SC_OP_LED_ON; | |
1007 | } else { | |
1008 | sc->led_off_cnt++; | |
1009 | } | |
8feceb67 VT |
1010 | break; |
1011 | case LED_FULL: | |
f2bffa7e | 1012 | if (led->led_type == ATH_LED_ASSOC) { |
8feceb67 | 1013 | sc->sc_flags |= SC_OP_LED_ASSOCIATED; |
f2bffa7e VT |
1014 | queue_delayed_work(sc->hw->workqueue, |
1015 | &sc->ath_led_blink_work, 0); | |
1016 | } else if (led->led_type == ATH_LED_RADIO) { | |
1017 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0); | |
1018 | sc->sc_flags |= SC_OP_LED_ON; | |
1019 | } else { | |
1020 | sc->led_on_cnt++; | |
1021 | } | |
8feceb67 VT |
1022 | break; |
1023 | default: | |
1024 | break; | |
f078f209 | 1025 | } |
8feceb67 | 1026 | } |
f078f209 | 1027 | |
8feceb67 VT |
1028 | static int ath_register_led(struct ath_softc *sc, struct ath_led *led, |
1029 | char *trigger) | |
1030 | { | |
1031 | int ret; | |
f078f209 | 1032 | |
8feceb67 VT |
1033 | led->sc = sc; |
1034 | led->led_cdev.name = led->name; | |
1035 | led->led_cdev.default_trigger = trigger; | |
1036 | led->led_cdev.brightness_set = ath_led_brightness; | |
f078f209 | 1037 | |
8feceb67 VT |
1038 | ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev); |
1039 | if (ret) | |
1040 | DPRINTF(sc, ATH_DBG_FATAL, | |
1041 | "Failed to register led:%s", led->name); | |
1042 | else | |
1043 | led->registered = 1; | |
1044 | return ret; | |
1045 | } | |
f078f209 | 1046 | |
8feceb67 VT |
1047 | static void ath_unregister_led(struct ath_led *led) |
1048 | { | |
1049 | if (led->registered) { | |
1050 | led_classdev_unregister(&led->led_cdev); | |
1051 | led->registered = 0; | |
f078f209 | 1052 | } |
f078f209 LR |
1053 | } |
1054 | ||
8feceb67 | 1055 | static void ath_deinit_leds(struct ath_softc *sc) |
f078f209 | 1056 | { |
f2bffa7e | 1057 | cancel_delayed_work_sync(&sc->ath_led_blink_work); |
8feceb67 VT |
1058 | ath_unregister_led(&sc->assoc_led); |
1059 | sc->sc_flags &= ~SC_OP_LED_ASSOCIATED; | |
1060 | ath_unregister_led(&sc->tx_led); | |
1061 | ath_unregister_led(&sc->rx_led); | |
1062 | ath_unregister_led(&sc->radio_led); | |
1063 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1); | |
1064 | } | |
f078f209 | 1065 | |
8feceb67 VT |
1066 | static void ath_init_leds(struct ath_softc *sc) |
1067 | { | |
1068 | char *trigger; | |
1069 | int ret; | |
f078f209 | 1070 | |
8feceb67 VT |
1071 | /* Configure gpio 1 for output */ |
1072 | ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN, | |
1073 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
1074 | /* LED off, active low */ | |
1075 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1); | |
7dcfdcd9 | 1076 | |
f2bffa7e VT |
1077 | INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work); |
1078 | ||
8feceb67 VT |
1079 | trigger = ieee80211_get_radio_led_name(sc->hw); |
1080 | snprintf(sc->radio_led.name, sizeof(sc->radio_led.name), | |
0818cb8a | 1081 | "ath9k-%s::radio", wiphy_name(sc->hw->wiphy)); |
8feceb67 VT |
1082 | ret = ath_register_led(sc, &sc->radio_led, trigger); |
1083 | sc->radio_led.led_type = ATH_LED_RADIO; | |
1084 | if (ret) | |
1085 | goto fail; | |
7dcfdcd9 | 1086 | |
8feceb67 VT |
1087 | trigger = ieee80211_get_assoc_led_name(sc->hw); |
1088 | snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name), | |
0818cb8a | 1089 | "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy)); |
8feceb67 VT |
1090 | ret = ath_register_led(sc, &sc->assoc_led, trigger); |
1091 | sc->assoc_led.led_type = ATH_LED_ASSOC; | |
1092 | if (ret) | |
1093 | goto fail; | |
f078f209 | 1094 | |
8feceb67 VT |
1095 | trigger = ieee80211_get_tx_led_name(sc->hw); |
1096 | snprintf(sc->tx_led.name, sizeof(sc->tx_led.name), | |
0818cb8a | 1097 | "ath9k-%s::tx", wiphy_name(sc->hw->wiphy)); |
8feceb67 VT |
1098 | ret = ath_register_led(sc, &sc->tx_led, trigger); |
1099 | sc->tx_led.led_type = ATH_LED_TX; | |
1100 | if (ret) | |
1101 | goto fail; | |
f078f209 | 1102 | |
8feceb67 VT |
1103 | trigger = ieee80211_get_rx_led_name(sc->hw); |
1104 | snprintf(sc->rx_led.name, sizeof(sc->rx_led.name), | |
0818cb8a | 1105 | "ath9k-%s::rx", wiphy_name(sc->hw->wiphy)); |
8feceb67 VT |
1106 | ret = ath_register_led(sc, &sc->rx_led, trigger); |
1107 | sc->rx_led.led_type = ATH_LED_RX; | |
1108 | if (ret) | |
1109 | goto fail; | |
f078f209 | 1110 | |
8feceb67 VT |
1111 | return; |
1112 | ||
1113 | fail: | |
1114 | ath_deinit_leds(sc); | |
f078f209 LR |
1115 | } |
1116 | ||
7ec3e514 | 1117 | void ath_radio_enable(struct ath_softc *sc) |
500c064d | 1118 | { |
cbe61d8a | 1119 | struct ath_hw *ah = sc->sc_ah; |
ae8d2858 LR |
1120 | struct ieee80211_channel *channel = sc->hw->conf.channel; |
1121 | int r; | |
500c064d | 1122 | |
3cbb5dd7 | 1123 | ath9k_ps_wakeup(sc); |
d2f5b3a6 | 1124 | ath9k_hw_configpcipowersave(ah, 0); |
ae8d2858 | 1125 | |
159cd468 VT |
1126 | if (!ah->curchan) |
1127 | ah->curchan = ath_get_curchannel(sc, sc->hw); | |
1128 | ||
d2f5b3a6 | 1129 | spin_lock_bh(&sc->sc_resetlock); |
2660b81a | 1130 | r = ath9k_hw_reset(ah, ah->curchan, false); |
ae8d2858 | 1131 | if (r) { |
500c064d | 1132 | DPRINTF(sc, ATH_DBG_FATAL, |
ae8d2858 | 1133 | "Unable to reset channel %u (%uMhz) ", |
6b45784f | 1134 | "reset status %d\n", |
ae8d2858 | 1135 | channel->center_freq, r); |
500c064d VT |
1136 | } |
1137 | spin_unlock_bh(&sc->sc_resetlock); | |
1138 | ||
1139 | ath_update_txpow(sc); | |
1140 | if (ath_startrecv(sc) != 0) { | |
1141 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 1142 | "Unable to restart recv logic\n"); |
500c064d VT |
1143 | return; |
1144 | } | |
1145 | ||
1146 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 1147 | ath_beacon_config(sc, NULL); /* restart beacons */ |
500c064d VT |
1148 | |
1149 | /* Re-Enable interrupts */ | |
17d7904d | 1150 | ath9k_hw_set_interrupts(ah, sc->imask); |
500c064d VT |
1151 | |
1152 | /* Enable LED */ | |
1153 | ath9k_hw_cfg_output(ah, ATH_LED_PIN, | |
1154 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
1155 | ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0); | |
1156 | ||
1157 | ieee80211_wake_queues(sc->hw); | |
3cbb5dd7 | 1158 | ath9k_ps_restore(sc); |
500c064d VT |
1159 | } |
1160 | ||
7ec3e514 | 1161 | void ath_radio_disable(struct ath_softc *sc) |
500c064d | 1162 | { |
cbe61d8a | 1163 | struct ath_hw *ah = sc->sc_ah; |
ae8d2858 LR |
1164 | struct ieee80211_channel *channel = sc->hw->conf.channel; |
1165 | int r; | |
500c064d | 1166 | |
3cbb5dd7 | 1167 | ath9k_ps_wakeup(sc); |
500c064d VT |
1168 | ieee80211_stop_queues(sc->hw); |
1169 | ||
1170 | /* Disable LED */ | |
1171 | ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1); | |
1172 | ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN); | |
1173 | ||
1174 | /* Disable interrupts */ | |
1175 | ath9k_hw_set_interrupts(ah, 0); | |
1176 | ||
043a0405 | 1177 | ath_drain_all_txq(sc, false); /* clear pending tx frames */ |
500c064d VT |
1178 | ath_stoprecv(sc); /* turn off frame recv */ |
1179 | ath_flushrecv(sc); /* flush recv queue */ | |
1180 | ||
159cd468 VT |
1181 | if (!ah->curchan) |
1182 | ah->curchan = ath_get_curchannel(sc, sc->hw); | |
1183 | ||
500c064d | 1184 | spin_lock_bh(&sc->sc_resetlock); |
2660b81a | 1185 | r = ath9k_hw_reset(ah, ah->curchan, false); |
ae8d2858 | 1186 | if (r) { |
500c064d | 1187 | DPRINTF(sc, ATH_DBG_FATAL, |
04bd4638 | 1188 | "Unable to reset channel %u (%uMhz) " |
6b45784f | 1189 | "reset status %d\n", |
ae8d2858 | 1190 | channel->center_freq, r); |
500c064d VT |
1191 | } |
1192 | spin_unlock_bh(&sc->sc_resetlock); | |
1193 | ||
1194 | ath9k_hw_phy_disable(ah); | |
d2f5b3a6 | 1195 | ath9k_hw_configpcipowersave(ah, 1); |
500c064d | 1196 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); |
3cbb5dd7 | 1197 | ath9k_ps_restore(sc); |
500c064d VT |
1198 | } |
1199 | ||
5077fd35 GJ |
1200 | /*******************/ |
1201 | /* Rfkill */ | |
1202 | /*******************/ | |
1203 | ||
500c064d VT |
1204 | static bool ath_is_rfkill_set(struct ath_softc *sc) |
1205 | { | |
cbe61d8a | 1206 | struct ath_hw *ah = sc->sc_ah; |
500c064d | 1207 | |
2660b81a S |
1208 | return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) == |
1209 | ah->rfkill_polarity; | |
500c064d VT |
1210 | } |
1211 | ||
3b319aae | 1212 | static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw) |
500c064d | 1213 | { |
3b319aae JB |
1214 | struct ath_wiphy *aphy = hw->priv; |
1215 | struct ath_softc *sc = aphy->sc; | |
19d337df | 1216 | bool blocked = !!ath_is_rfkill_set(sc); |
500c064d | 1217 | |
3b319aae JB |
1218 | wiphy_rfkill_set_hw_state(hw->wiphy, blocked); |
1219 | ||
1220 | if (blocked) | |
19d337df JB |
1221 | ath_radio_disable(sc); |
1222 | else | |
1223 | ath_radio_enable(sc); | |
500c064d VT |
1224 | } |
1225 | ||
3b319aae | 1226 | static void ath_start_rfkill_poll(struct ath_softc *sc) |
500c064d | 1227 | { |
3b319aae | 1228 | struct ath_hw *ah = sc->sc_ah; |
9c84b797 | 1229 | |
3b319aae JB |
1230 | if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) |
1231 | wiphy_rfkill_start_polling(sc->hw->wiphy); | |
9c84b797 | 1232 | } |
500c064d | 1233 | |
6baff7f9 | 1234 | void ath_cleanup(struct ath_softc *sc) |
39c3c2f2 GJ |
1235 | { |
1236 | ath_detach(sc); | |
1237 | free_irq(sc->irq, sc); | |
1238 | ath_bus_cleanup(sc); | |
c52f33d0 | 1239 | kfree(sc->sec_wiphy); |
39c3c2f2 GJ |
1240 | ieee80211_free_hw(sc->hw); |
1241 | } | |
1242 | ||
6baff7f9 | 1243 | void ath_detach(struct ath_softc *sc) |
f078f209 | 1244 | { |
8feceb67 | 1245 | struct ieee80211_hw *hw = sc->hw; |
9c84b797 | 1246 | int i = 0; |
f078f209 | 1247 | |
3cbb5dd7 VN |
1248 | ath9k_ps_wakeup(sc); |
1249 | ||
04bd4638 | 1250 | DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n"); |
f078f209 | 1251 | |
3fcdfb4b | 1252 | ath_deinit_leds(sc); |
0e2dedf9 | 1253 | cancel_work_sync(&sc->chan_work); |
f98c3bd2 | 1254 | cancel_delayed_work_sync(&sc->wiphy_work); |
3fcdfb4b | 1255 | |
c52f33d0 JM |
1256 | for (i = 0; i < sc->num_sec_wiphy; i++) { |
1257 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
1258 | if (aphy == NULL) | |
1259 | continue; | |
1260 | sc->sec_wiphy[i] = NULL; | |
1261 | ieee80211_unregister_hw(aphy->hw); | |
1262 | ieee80211_free_hw(aphy->hw); | |
1263 | } | |
3fcdfb4b | 1264 | ieee80211_unregister_hw(hw); |
8feceb67 VT |
1265 | ath_rx_cleanup(sc); |
1266 | ath_tx_cleanup(sc); | |
f078f209 | 1267 | |
9c84b797 S |
1268 | tasklet_kill(&sc->intr_tq); |
1269 | tasklet_kill(&sc->bcon_tasklet); | |
f078f209 | 1270 | |
9c84b797 S |
1271 | if (!(sc->sc_flags & SC_OP_INVALID)) |
1272 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); | |
8feceb67 | 1273 | |
9c84b797 S |
1274 | /* cleanup tx queues */ |
1275 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
1276 | if (ATH_TXQ_SETUP(sc, i)) | |
b77f483f | 1277 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); |
9c84b797 S |
1278 | |
1279 | ath9k_hw_detach(sc->sc_ah); | |
826d2680 | 1280 | ath9k_exit_debug(sc); |
3cbb5dd7 | 1281 | ath9k_ps_restore(sc); |
f078f209 LR |
1282 | } |
1283 | ||
e3bb249b BC |
1284 | static int ath9k_reg_notifier(struct wiphy *wiphy, |
1285 | struct regulatory_request *request) | |
1286 | { | |
1287 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); | |
1288 | struct ath_wiphy *aphy = hw->priv; | |
1289 | struct ath_softc *sc = aphy->sc; | |
1290 | struct ath_regulatory *reg = &sc->sc_ah->regulatory; | |
1291 | ||
1292 | return ath_reg_notifier_apply(wiphy, request, reg); | |
1293 | } | |
1294 | ||
ff37e337 S |
1295 | static int ath_init(u16 devid, struct ath_softc *sc) |
1296 | { | |
cbe61d8a | 1297 | struct ath_hw *ah = NULL; |
ff37e337 S |
1298 | int status; |
1299 | int error = 0, i; | |
1300 | int csz = 0; | |
1301 | ||
1302 | /* XXX: hardware will not be ready until ath_open() being called */ | |
1303 | sc->sc_flags |= SC_OP_INVALID; | |
88b126af | 1304 | |
826d2680 S |
1305 | if (ath9k_init_debug(sc) < 0) |
1306 | printk(KERN_ERR "Unable to create debugfs files\n"); | |
ff37e337 | 1307 | |
c52f33d0 | 1308 | spin_lock_init(&sc->wiphy_lock); |
ff37e337 | 1309 | spin_lock_init(&sc->sc_resetlock); |
6158425b | 1310 | spin_lock_init(&sc->sc_serial_rw); |
aa33de09 | 1311 | mutex_init(&sc->mutex); |
ff37e337 | 1312 | tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); |
9fc9ab0a | 1313 | tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet, |
ff37e337 S |
1314 | (unsigned long)sc); |
1315 | ||
1316 | /* | |
1317 | * Cache line size is used to size and align various | |
1318 | * structures used to communicate with the hardware. | |
1319 | */ | |
88d15707 | 1320 | ath_read_cachesize(sc, &csz); |
ff37e337 | 1321 | /* XXX assert csz is non-zero */ |
17d7904d | 1322 | sc->cachelsz = csz << 2; /* convert to bytes */ |
ff37e337 | 1323 | |
cbe61d8a | 1324 | ah = ath9k_hw_attach(devid, sc, &status); |
ff37e337 S |
1325 | if (ah == NULL) { |
1326 | DPRINTF(sc, ATH_DBG_FATAL, | |
295834fe | 1327 | "Unable to attach hardware; HAL status %d\n", status); |
ff37e337 S |
1328 | error = -ENXIO; |
1329 | goto bad; | |
1330 | } | |
1331 | sc->sc_ah = ah; | |
1332 | ||
1333 | /* Get the hardware key cache size. */ | |
2660b81a | 1334 | sc->keymax = ah->caps.keycache_size; |
17d7904d | 1335 | if (sc->keymax > ATH_KEYMAX) { |
d8baa939 | 1336 | DPRINTF(sc, ATH_DBG_ANY, |
04bd4638 | 1337 | "Warning, using only %u entries in %u key cache\n", |
17d7904d S |
1338 | ATH_KEYMAX, sc->keymax); |
1339 | sc->keymax = ATH_KEYMAX; | |
ff37e337 S |
1340 | } |
1341 | ||
1342 | /* | |
1343 | * Reset the key cache since some parts do not | |
1344 | * reset the contents on initial power up. | |
1345 | */ | |
17d7904d | 1346 | for (i = 0; i < sc->keymax; i++) |
ff37e337 | 1347 | ath9k_hw_keyreset(ah, (u16) i); |
ff37e337 | 1348 | |
85efc86e | 1349 | if (error) |
ff37e337 S |
1350 | goto bad; |
1351 | ||
1352 | /* default to MONITOR mode */ | |
2660b81a | 1353 | sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR; |
d97809db | 1354 | |
ff37e337 S |
1355 | /* Setup rate tables */ |
1356 | ||
1357 | ath_rate_attach(sc); | |
1358 | ath_setup_rates(sc, IEEE80211_BAND_2GHZ); | |
1359 | ath_setup_rates(sc, IEEE80211_BAND_5GHZ); | |
1360 | ||
1361 | /* | |
1362 | * Allocate hardware transmit queues: one queue for | |
1363 | * beacon frames and one data queue for each QoS | |
1364 | * priority. Note that the hal handles reseting | |
1365 | * these queues at the needed time. | |
1366 | */ | |
b77f483f S |
1367 | sc->beacon.beaconq = ath_beaconq_setup(ah); |
1368 | if (sc->beacon.beaconq == -1) { | |
ff37e337 | 1369 | DPRINTF(sc, ATH_DBG_FATAL, |
04bd4638 | 1370 | "Unable to setup a beacon xmit queue\n"); |
ff37e337 S |
1371 | error = -EIO; |
1372 | goto bad2; | |
1373 | } | |
b77f483f S |
1374 | sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); |
1375 | if (sc->beacon.cabq == NULL) { | |
ff37e337 | 1376 | DPRINTF(sc, ATH_DBG_FATAL, |
04bd4638 | 1377 | "Unable to setup CAB xmit queue\n"); |
ff37e337 S |
1378 | error = -EIO; |
1379 | goto bad2; | |
1380 | } | |
1381 | ||
17d7904d | 1382 | sc->config.cabqReadytime = ATH_CABQ_READY_TIME; |
ff37e337 S |
1383 | ath_cabq_update(sc); |
1384 | ||
b77f483f S |
1385 | for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++) |
1386 | sc->tx.hwq_map[i] = -1; | |
ff37e337 S |
1387 | |
1388 | /* Setup data queues */ | |
1389 | /* NB: ensure BK queue is the lowest priority h/w queue */ | |
1390 | if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) { | |
1391 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 1392 | "Unable to setup xmit queue for BK traffic\n"); |
ff37e337 S |
1393 | error = -EIO; |
1394 | goto bad2; | |
1395 | } | |
1396 | ||
1397 | if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) { | |
1398 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 1399 | "Unable to setup xmit queue for BE traffic\n"); |
ff37e337 S |
1400 | error = -EIO; |
1401 | goto bad2; | |
1402 | } | |
1403 | if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) { | |
1404 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 1405 | "Unable to setup xmit queue for VI traffic\n"); |
ff37e337 S |
1406 | error = -EIO; |
1407 | goto bad2; | |
1408 | } | |
1409 | if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) { | |
1410 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 1411 | "Unable to setup xmit queue for VO traffic\n"); |
ff37e337 S |
1412 | error = -EIO; |
1413 | goto bad2; | |
1414 | } | |
1415 | ||
1416 | /* Initializes the noise floor to a reasonable default value. | |
1417 | * Later on this will be updated during ANI processing. */ | |
1418 | ||
17d7904d S |
1419 | sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR; |
1420 | setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc); | |
ff37e337 S |
1421 | |
1422 | if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, | |
1423 | ATH9K_CIPHER_TKIP, NULL)) { | |
1424 | /* | |
1425 | * Whether we should enable h/w TKIP MIC. | |
1426 | * XXX: if we don't support WME TKIP MIC, then we wouldn't | |
1427 | * report WMM capable, so it's always safe to turn on | |
1428 | * TKIP MIC in this case. | |
1429 | */ | |
1430 | ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC, | |
1431 | 0, 1, NULL); | |
1432 | } | |
1433 | ||
1434 | /* | |
1435 | * Check whether the separate key cache entries | |
1436 | * are required to handle both tx+rx MIC keys. | |
1437 | * With split mic keys the number of stations is limited | |
1438 | * to 27 otherwise 59. | |
1439 | */ | |
1440 | if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, | |
1441 | ATH9K_CIPHER_TKIP, NULL) | |
1442 | && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, | |
1443 | ATH9K_CIPHER_MIC, NULL) | |
1444 | && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT, | |
1445 | 0, NULL)) | |
17d7904d | 1446 | sc->splitmic = 1; |
ff37e337 S |
1447 | |
1448 | /* turn on mcast key search if possible */ | |
1449 | if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL)) | |
1450 | (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1, | |
1451 | 1, NULL); | |
1452 | ||
17d7904d | 1453 | sc->config.txpowlimit = ATH_TXPOWER_MAX; |
ff37e337 S |
1454 | |
1455 | /* 11n Capabilities */ | |
2660b81a | 1456 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
ff37e337 S |
1457 | sc->sc_flags |= SC_OP_TXAGGR; |
1458 | sc->sc_flags |= SC_OP_RXAGGR; | |
1459 | } | |
1460 | ||
2660b81a S |
1461 | sc->tx_chainmask = ah->caps.tx_chainmask; |
1462 | sc->rx_chainmask = ah->caps.rx_chainmask; | |
ff37e337 S |
1463 | |
1464 | ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL); | |
b77f483f | 1465 | sc->rx.defant = ath9k_hw_getdefantenna(ah); |
ff37e337 | 1466 | |
8ca21f01 | 1467 | if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
ba52da58 | 1468 | memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN); |
ff37e337 | 1469 | |
b77f483f | 1470 | sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */ |
ff37e337 S |
1471 | |
1472 | /* initialize beacon slots */ | |
c52f33d0 | 1473 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { |
2c3db3d5 | 1474 | sc->beacon.bslot[i] = NULL; |
c52f33d0 JM |
1475 | sc->beacon.bslot_aphy[i] = NULL; |
1476 | } | |
ff37e337 | 1477 | |
ff37e337 S |
1478 | /* setup channels and rates */ |
1479 | ||
5f8e077c | 1480 | sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable; |
ff37e337 S |
1481 | sc->sbands[IEEE80211_BAND_2GHZ].bitrates = |
1482 | sc->rates[IEEE80211_BAND_2GHZ]; | |
1483 | sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; | |
5f8e077c LR |
1484 | sc->sbands[IEEE80211_BAND_2GHZ].n_channels = |
1485 | ARRAY_SIZE(ath9k_2ghz_chantable); | |
ff37e337 | 1486 | |
2660b81a | 1487 | if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) { |
5f8e077c | 1488 | sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable; |
ff37e337 S |
1489 | sc->sbands[IEEE80211_BAND_5GHZ].bitrates = |
1490 | sc->rates[IEEE80211_BAND_5GHZ]; | |
1491 | sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; | |
5f8e077c LR |
1492 | sc->sbands[IEEE80211_BAND_5GHZ].n_channels = |
1493 | ARRAY_SIZE(ath9k_5ghz_chantable); | |
ff37e337 S |
1494 | } |
1495 | ||
2660b81a | 1496 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX) |
c97c92d9 VT |
1497 | ath9k_hw_btcoex_enable(sc->sc_ah); |
1498 | ||
ff37e337 S |
1499 | return 0; |
1500 | bad2: | |
1501 | /* cleanup tx queues */ | |
1502 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
1503 | if (ATH_TXQ_SETUP(sc, i)) | |
b77f483f | 1504 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); |
ff37e337 S |
1505 | bad: |
1506 | if (ah) | |
1507 | ath9k_hw_detach(ah); | |
40b130a9 | 1508 | ath9k_exit_debug(sc); |
ff37e337 S |
1509 | |
1510 | return error; | |
1511 | } | |
1512 | ||
c52f33d0 | 1513 | void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) |
f078f209 | 1514 | { |
9c84b797 S |
1515 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | |
1516 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | | |
1517 | IEEE80211_HW_SIGNAL_DBM | | |
3cbb5dd7 VN |
1518 | IEEE80211_HW_AMPDU_AGGREGATION | |
1519 | IEEE80211_HW_SUPPORTS_PS | | |
eeee1320 S |
1520 | IEEE80211_HW_PS_NULLFUNC_STACK | |
1521 | IEEE80211_HW_SPECTRUM_MGMT; | |
f078f209 | 1522 | |
b3bd89ce | 1523 | if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt) |
0ced0e17 JM |
1524 | hw->flags |= IEEE80211_HW_MFP_CAPABLE; |
1525 | ||
9c84b797 S |
1526 | hw->wiphy->interface_modes = |
1527 | BIT(NL80211_IFTYPE_AP) | | |
1528 | BIT(NL80211_IFTYPE_STATION) | | |
9cb5412b PE |
1529 | BIT(NL80211_IFTYPE_ADHOC) | |
1530 | BIT(NL80211_IFTYPE_MESH_POINT); | |
f078f209 | 1531 | |
8feceb67 | 1532 | hw->queues = 4; |
e63835b0 | 1533 | hw->max_rates = 4; |
171387ef | 1534 | hw->channel_change_time = 5000; |
465ca84d | 1535 | hw->max_listen_interval = 10; |
e63835b0 | 1536 | hw->max_rate_tries = ATH_11N_TXMAXTRY; |
528f0c6b | 1537 | hw->sta_data_size = sizeof(struct ath_node); |
17d7904d | 1538 | hw->vif_data_size = sizeof(struct ath_vif); |
f078f209 | 1539 | |
8feceb67 | 1540 | hw->rate_control_algorithm = "ath9k_rate_control"; |
f078f209 | 1541 | |
c52f33d0 JM |
1542 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = |
1543 | &sc->sbands[IEEE80211_BAND_2GHZ]; | |
1544 | if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) | |
1545 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
1546 | &sc->sbands[IEEE80211_BAND_5GHZ]; | |
1547 | } | |
1548 | ||
1549 | int ath_attach(u16 devid, struct ath_softc *sc) | |
1550 | { | |
1551 | struct ieee80211_hw *hw = sc->hw; | |
c52f33d0 | 1552 | int error = 0, i; |
3a702e49 | 1553 | struct ath_regulatory *reg; |
c52f33d0 JM |
1554 | |
1555 | DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n"); | |
1556 | ||
1557 | error = ath_init(devid, sc); | |
1558 | if (error != 0) | |
1559 | return error; | |
1560 | ||
1561 | /* get mac address from hardware and set in mac80211 */ | |
1562 | ||
1563 | SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr); | |
1564 | ||
1565 | ath_set_hw_capab(sc, hw); | |
1566 | ||
c26c2e57 LR |
1567 | error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy, |
1568 | ath9k_reg_notifier); | |
1569 | if (error) | |
1570 | return error; | |
1571 | ||
1572 | reg = &sc->sc_ah->regulatory; | |
1573 | ||
2660b81a | 1574 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
eb2599ca | 1575 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); |
2660b81a | 1576 | if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) |
eb2599ca | 1577 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); |
9c84b797 S |
1578 | } |
1579 | ||
db93e7b5 SB |
1580 | /* initialize tx/rx engine */ |
1581 | error = ath_tx_init(sc, ATH_TXBUF); | |
1582 | if (error != 0) | |
40b130a9 | 1583 | goto error_attach; |
8feceb67 | 1584 | |
db93e7b5 SB |
1585 | error = ath_rx_init(sc, ATH_RXBUF); |
1586 | if (error != 0) | |
40b130a9 | 1587 | goto error_attach; |
8feceb67 | 1588 | |
0e2dedf9 | 1589 | INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work); |
f98c3bd2 JM |
1590 | INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work); |
1591 | sc->wiphy_scheduler_int = msecs_to_jiffies(500); | |
0e2dedf9 | 1592 | |
db93e7b5 | 1593 | error = ieee80211_register_hw(hw); |
8feceb67 | 1594 | |
3a702e49 | 1595 | if (!ath_is_world_regd(reg)) { |
c02cf373 | 1596 | error = regulatory_hint(hw->wiphy, reg->alpha2); |
fe33eb39 LR |
1597 | if (error) |
1598 | goto error_attach; | |
1599 | } | |
5f8e077c | 1600 | |
db93e7b5 SB |
1601 | /* Initialize LED control */ |
1602 | ath_init_leds(sc); | |
8feceb67 | 1603 | |
3b319aae | 1604 | ath_start_rfkill_poll(sc); |
5f8e077c | 1605 | |
8feceb67 | 1606 | return 0; |
40b130a9 VT |
1607 | |
1608 | error_attach: | |
1609 | /* cleanup tx queues */ | |
1610 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
1611 | if (ATH_TXQ_SETUP(sc, i)) | |
1612 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
1613 | ||
1614 | ath9k_hw_detach(sc->sc_ah); | |
1615 | ath9k_exit_debug(sc); | |
1616 | ||
8feceb67 | 1617 | return error; |
f078f209 LR |
1618 | } |
1619 | ||
ff37e337 S |
1620 | int ath_reset(struct ath_softc *sc, bool retry_tx) |
1621 | { | |
cbe61d8a | 1622 | struct ath_hw *ah = sc->sc_ah; |
030bb495 | 1623 | struct ieee80211_hw *hw = sc->hw; |
ae8d2858 | 1624 | int r; |
ff37e337 S |
1625 | |
1626 | ath9k_hw_set_interrupts(ah, 0); | |
043a0405 | 1627 | ath_drain_all_txq(sc, retry_tx); |
ff37e337 S |
1628 | ath_stoprecv(sc); |
1629 | ath_flushrecv(sc); | |
1630 | ||
1631 | spin_lock_bh(&sc->sc_resetlock); | |
2660b81a | 1632 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false); |
ae8d2858 | 1633 | if (r) |
ff37e337 | 1634 | DPRINTF(sc, ATH_DBG_FATAL, |
6b45784f | 1635 | "Unable to reset hardware; reset status %d\n", r); |
ff37e337 S |
1636 | spin_unlock_bh(&sc->sc_resetlock); |
1637 | ||
1638 | if (ath_startrecv(sc) != 0) | |
04bd4638 | 1639 | DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n"); |
ff37e337 S |
1640 | |
1641 | /* | |
1642 | * We may be doing a reset in response to a request | |
1643 | * that changes the channel so update any state that | |
1644 | * might change as a result. | |
1645 | */ | |
ce111bad | 1646 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
1647 | |
1648 | ath_update_txpow(sc); | |
1649 | ||
1650 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 1651 | ath_beacon_config(sc, NULL); /* restart beacons */ |
ff37e337 | 1652 | |
17d7904d | 1653 | ath9k_hw_set_interrupts(ah, sc->imask); |
ff37e337 S |
1654 | |
1655 | if (retry_tx) { | |
1656 | int i; | |
1657 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1658 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
1659 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
1660 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
1661 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
1662 | } |
1663 | } | |
1664 | } | |
1665 | ||
ae8d2858 | 1666 | return r; |
ff37e337 S |
1667 | } |
1668 | ||
1669 | /* | |
1670 | * This function will allocate both the DMA descriptor structure, and the | |
1671 | * buffers it contains. These are used to contain the descriptors used | |
1672 | * by the system. | |
1673 | */ | |
1674 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
1675 | struct list_head *head, const char *name, | |
1676 | int nbuf, int ndesc) | |
1677 | { | |
1678 | #define DS2PHYS(_dd, _ds) \ | |
1679 | ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) | |
1680 | #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) | |
1681 | #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) | |
1682 | ||
1683 | struct ath_desc *ds; | |
1684 | struct ath_buf *bf; | |
1685 | int i, bsize, error; | |
1686 | ||
04bd4638 S |
1687 | DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n", |
1688 | name, nbuf, ndesc); | |
ff37e337 | 1689 | |
b03a9db9 | 1690 | INIT_LIST_HEAD(head); |
ff37e337 S |
1691 | /* ath_desc must be a multiple of DWORDs */ |
1692 | if ((sizeof(struct ath_desc) % 4) != 0) { | |
04bd4638 | 1693 | DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n"); |
ff37e337 S |
1694 | ASSERT((sizeof(struct ath_desc) % 4) == 0); |
1695 | error = -ENOMEM; | |
1696 | goto fail; | |
1697 | } | |
1698 | ||
ff37e337 S |
1699 | dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; |
1700 | ||
1701 | /* | |
1702 | * Need additional DMA memory because we can't use | |
1703 | * descriptors that cross the 4K page boundary. Assume | |
1704 | * one skipped descriptor per 4K page. | |
1705 | */ | |
2660b81a | 1706 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { |
ff37e337 S |
1707 | u32 ndesc_skipped = |
1708 | ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); | |
1709 | u32 dma_len; | |
1710 | ||
1711 | while (ndesc_skipped) { | |
1712 | dma_len = ndesc_skipped * sizeof(struct ath_desc); | |
1713 | dd->dd_desc_len += dma_len; | |
1714 | ||
1715 | ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); | |
1716 | }; | |
1717 | } | |
1718 | ||
1719 | /* allocate descriptors */ | |
7da3c55c | 1720 | dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len, |
f0e6ce13 | 1721 | &dd->dd_desc_paddr, GFP_KERNEL); |
ff37e337 S |
1722 | if (dd->dd_desc == NULL) { |
1723 | error = -ENOMEM; | |
1724 | goto fail; | |
1725 | } | |
1726 | ds = dd->dd_desc; | |
04bd4638 | 1727 | DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", |
ae459af1 | 1728 | name, ds, (u32) dd->dd_desc_len, |
ff37e337 S |
1729 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); |
1730 | ||
1731 | /* allocate buffers */ | |
1732 | bsize = sizeof(struct ath_buf) * nbuf; | |
f0e6ce13 | 1733 | bf = kzalloc(bsize, GFP_KERNEL); |
ff37e337 S |
1734 | if (bf == NULL) { |
1735 | error = -ENOMEM; | |
1736 | goto fail2; | |
1737 | } | |
ff37e337 S |
1738 | dd->dd_bufptr = bf; |
1739 | ||
ff37e337 S |
1740 | for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { |
1741 | bf->bf_desc = ds; | |
1742 | bf->bf_daddr = DS2PHYS(dd, ds); | |
1743 | ||
2660b81a | 1744 | if (!(sc->sc_ah->caps.hw_caps & |
ff37e337 S |
1745 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { |
1746 | /* | |
1747 | * Skip descriptor addresses which can cause 4KB | |
1748 | * boundary crossing (addr + length) with a 32 dword | |
1749 | * descriptor fetch. | |
1750 | */ | |
1751 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
1752 | ASSERT((caddr_t) bf->bf_desc < | |
1753 | ((caddr_t) dd->dd_desc + | |
1754 | dd->dd_desc_len)); | |
1755 | ||
1756 | ds += ndesc; | |
1757 | bf->bf_desc = ds; | |
1758 | bf->bf_daddr = DS2PHYS(dd, ds); | |
1759 | } | |
1760 | } | |
1761 | list_add_tail(&bf->list, head); | |
1762 | } | |
1763 | return 0; | |
1764 | fail2: | |
7da3c55c GJ |
1765 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, |
1766 | dd->dd_desc_paddr); | |
ff37e337 S |
1767 | fail: |
1768 | memset(dd, 0, sizeof(*dd)); | |
1769 | return error; | |
1770 | #undef ATH_DESC_4KB_BOUND_CHECK | |
1771 | #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED | |
1772 | #undef DS2PHYS | |
1773 | } | |
1774 | ||
1775 | void ath_descdma_cleanup(struct ath_softc *sc, | |
1776 | struct ath_descdma *dd, | |
1777 | struct list_head *head) | |
1778 | { | |
7da3c55c GJ |
1779 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, |
1780 | dd->dd_desc_paddr); | |
ff37e337 S |
1781 | |
1782 | INIT_LIST_HEAD(head); | |
1783 | kfree(dd->dd_bufptr); | |
1784 | memset(dd, 0, sizeof(*dd)); | |
1785 | } | |
1786 | ||
1787 | int ath_get_hal_qnum(u16 queue, struct ath_softc *sc) | |
1788 | { | |
1789 | int qnum; | |
1790 | ||
1791 | switch (queue) { | |
1792 | case 0: | |
b77f483f | 1793 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO]; |
ff37e337 S |
1794 | break; |
1795 | case 1: | |
b77f483f | 1796 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI]; |
ff37e337 S |
1797 | break; |
1798 | case 2: | |
b77f483f | 1799 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE]; |
ff37e337 S |
1800 | break; |
1801 | case 3: | |
b77f483f | 1802 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK]; |
ff37e337 S |
1803 | break; |
1804 | default: | |
b77f483f | 1805 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE]; |
ff37e337 S |
1806 | break; |
1807 | } | |
1808 | ||
1809 | return qnum; | |
1810 | } | |
1811 | ||
1812 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc) | |
1813 | { | |
1814 | int qnum; | |
1815 | ||
1816 | switch (queue) { | |
1817 | case ATH9K_WME_AC_VO: | |
1818 | qnum = 0; | |
1819 | break; | |
1820 | case ATH9K_WME_AC_VI: | |
1821 | qnum = 1; | |
1822 | break; | |
1823 | case ATH9K_WME_AC_BE: | |
1824 | qnum = 2; | |
1825 | break; | |
1826 | case ATH9K_WME_AC_BK: | |
1827 | qnum = 3; | |
1828 | break; | |
1829 | default: | |
1830 | qnum = -1; | |
1831 | break; | |
1832 | } | |
1833 | ||
1834 | return qnum; | |
1835 | } | |
1836 | ||
5f8e077c LR |
1837 | /* XXX: Remove me once we don't depend on ath9k_channel for all |
1838 | * this redundant data */ | |
0e2dedf9 JM |
1839 | void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, |
1840 | struct ath9k_channel *ichan) | |
5f8e077c | 1841 | { |
5f8e077c LR |
1842 | struct ieee80211_channel *chan = hw->conf.channel; |
1843 | struct ieee80211_conf *conf = &hw->conf; | |
1844 | ||
1845 | ichan->channel = chan->center_freq; | |
1846 | ichan->chan = chan; | |
1847 | ||
1848 | if (chan->band == IEEE80211_BAND_2GHZ) { | |
1849 | ichan->chanmode = CHANNEL_G; | |
1850 | ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM; | |
1851 | } else { | |
1852 | ichan->chanmode = CHANNEL_A; | |
1853 | ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM; | |
1854 | } | |
1855 | ||
1856 | sc->tx_chan_width = ATH9K_HT_MACMODE_20; | |
1857 | ||
1858 | if (conf_is_ht(conf)) { | |
1859 | if (conf_is_ht40(conf)) | |
1860 | sc->tx_chan_width = ATH9K_HT_MACMODE_2040; | |
1861 | ||
1862 | ichan->chanmode = ath_get_extchanmode(sc, chan, | |
1863 | conf->channel_type); | |
1864 | } | |
1865 | } | |
1866 | ||
ff37e337 S |
1867 | /**********************/ |
1868 | /* mac80211 callbacks */ | |
1869 | /**********************/ | |
1870 | ||
8feceb67 | 1871 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 1872 | { |
bce048d7 JM |
1873 | struct ath_wiphy *aphy = hw->priv; |
1874 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 1875 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 1876 | struct ath9k_channel *init_channel; |
82880a7c | 1877 | int r; |
f078f209 | 1878 | |
04bd4638 S |
1879 | DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with " |
1880 | "initial channel: %d MHz\n", curchan->center_freq); | |
f078f209 | 1881 | |
141b38b6 S |
1882 | mutex_lock(&sc->mutex); |
1883 | ||
9580a222 JM |
1884 | if (ath9k_wiphy_started(sc)) { |
1885 | if (sc->chan_idx == curchan->hw_value) { | |
1886 | /* | |
1887 | * Already on the operational channel, the new wiphy | |
1888 | * can be marked active. | |
1889 | */ | |
1890 | aphy->state = ATH_WIPHY_ACTIVE; | |
1891 | ieee80211_wake_queues(hw); | |
1892 | } else { | |
1893 | /* | |
1894 | * Another wiphy is on another channel, start the new | |
1895 | * wiphy in paused state. | |
1896 | */ | |
1897 | aphy->state = ATH_WIPHY_PAUSED; | |
1898 | ieee80211_stop_queues(hw); | |
1899 | } | |
1900 | mutex_unlock(&sc->mutex); | |
1901 | return 0; | |
1902 | } | |
1903 | aphy->state = ATH_WIPHY_ACTIVE; | |
1904 | ||
8feceb67 | 1905 | /* setup initial channel */ |
f078f209 | 1906 | |
82880a7c | 1907 | sc->chan_idx = curchan->hw_value; |
f078f209 | 1908 | |
82880a7c | 1909 | init_channel = ath_get_curchannel(sc, hw); |
ff37e337 S |
1910 | |
1911 | /* Reset SERDES registers */ | |
1912 | ath9k_hw_configpcipowersave(sc->sc_ah, 0); | |
1913 | ||
1914 | /* | |
1915 | * The basic interface to setting the hardware in a good | |
1916 | * state is ``reset''. On return the hardware is known to | |
1917 | * be powered up and with interrupts disabled. This must | |
1918 | * be followed by initialization of the appropriate bits | |
1919 | * and then setup of the interrupt mask. | |
1920 | */ | |
1921 | spin_lock_bh(&sc->sc_resetlock); | |
ae8d2858 LR |
1922 | r = ath9k_hw_reset(sc->sc_ah, init_channel, false); |
1923 | if (r) { | |
ff37e337 | 1924 | DPRINTF(sc, ATH_DBG_FATAL, |
6b45784f | 1925 | "Unable to reset hardware; reset status %d " |
ae8d2858 LR |
1926 | "(freq %u MHz)\n", r, |
1927 | curchan->center_freq); | |
ff37e337 | 1928 | spin_unlock_bh(&sc->sc_resetlock); |
141b38b6 | 1929 | goto mutex_unlock; |
ff37e337 S |
1930 | } |
1931 | spin_unlock_bh(&sc->sc_resetlock); | |
1932 | ||
1933 | /* | |
1934 | * This is needed only to setup initial state | |
1935 | * but it's best done after a reset. | |
1936 | */ | |
1937 | ath_update_txpow(sc); | |
8feceb67 | 1938 | |
ff37e337 S |
1939 | /* |
1940 | * Setup the hardware after reset: | |
1941 | * The receive engine is set going. | |
1942 | * Frame transmit is handled entirely | |
1943 | * in the frame output path; there's nothing to do | |
1944 | * here except setup the interrupt mask. | |
1945 | */ | |
1946 | if (ath_startrecv(sc) != 0) { | |
1ffb0610 | 1947 | DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n"); |
141b38b6 S |
1948 | r = -EIO; |
1949 | goto mutex_unlock; | |
f078f209 | 1950 | } |
8feceb67 | 1951 | |
ff37e337 | 1952 | /* Setup our intr mask. */ |
17d7904d | 1953 | sc->imask = ATH9K_INT_RX | ATH9K_INT_TX |
ff37e337 S |
1954 | | ATH9K_INT_RXEOL | ATH9K_INT_RXORN |
1955 | | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL; | |
1956 | ||
2660b81a | 1957 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT) |
17d7904d | 1958 | sc->imask |= ATH9K_INT_GTT; |
ff37e337 | 1959 | |
2660b81a | 1960 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
17d7904d | 1961 | sc->imask |= ATH9K_INT_CST; |
ff37e337 | 1962 | |
ce111bad | 1963 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
1964 | |
1965 | sc->sc_flags &= ~SC_OP_INVALID; | |
1966 | ||
1967 | /* Disable BMISS interrupt when we're not associated */ | |
17d7904d S |
1968 | sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
1969 | ath9k_hw_set_interrupts(sc->sc_ah, sc->imask); | |
ff37e337 | 1970 | |
bce048d7 | 1971 | ieee80211_wake_queues(hw); |
ff37e337 | 1972 | |
141b38b6 S |
1973 | mutex_unlock: |
1974 | mutex_unlock(&sc->mutex); | |
1975 | ||
ae8d2858 | 1976 | return r; |
f078f209 LR |
1977 | } |
1978 | ||
8feceb67 VT |
1979 | static int ath9k_tx(struct ieee80211_hw *hw, |
1980 | struct sk_buff *skb) | |
f078f209 | 1981 | { |
528f0c6b | 1982 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
bce048d7 JM |
1983 | struct ath_wiphy *aphy = hw->priv; |
1984 | struct ath_softc *sc = aphy->sc; | |
528f0c6b | 1985 | struct ath_tx_control txctl; |
8feceb67 | 1986 | int hdrlen, padsize; |
528f0c6b | 1987 | |
8089cc47 | 1988 | if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { |
ee166a0e JM |
1989 | printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state " |
1990 | "%d\n", wiphy_name(hw->wiphy), aphy->state); | |
1991 | goto exit; | |
1992 | } | |
1993 | ||
dc8c4585 JM |
1994 | if (sc->hw->conf.flags & IEEE80211_CONF_PS) { |
1995 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
1996 | /* | |
1997 | * mac80211 does not set PM field for normal data frames, so we | |
1998 | * need to update that based on the current PS mode. | |
1999 | */ | |
2000 | if (ieee80211_is_data(hdr->frame_control) && | |
2001 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
2002 | !ieee80211_has_pm(hdr->frame_control)) { | |
2003 | DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame " | |
2004 | "while in PS mode\n"); | |
2005 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); | |
2006 | } | |
2007 | } | |
2008 | ||
9a23f9ca JM |
2009 | if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { |
2010 | /* | |
2011 | * We are using PS-Poll and mac80211 can request TX while in | |
2012 | * power save mode. Need to wake up hardware for the TX to be | |
2013 | * completed and if needed, also for RX of buffered frames. | |
2014 | */ | |
2015 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
2016 | ath9k_ps_wakeup(sc); | |
2017 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
2018 | if (ieee80211_is_pspoll(hdr->frame_control)) { | |
2019 | DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a " | |
2020 | "buffered frame\n"); | |
2021 | sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA; | |
2022 | } else { | |
2023 | DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n"); | |
2024 | sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK; | |
2025 | } | |
2026 | /* | |
2027 | * The actual restore operation will happen only after | |
2028 | * the sc_flags bit is cleared. We are just dropping | |
2029 | * the ps_usecount here. | |
2030 | */ | |
2031 | ath9k_ps_restore(sc); | |
2032 | } | |
2033 | ||
528f0c6b | 2034 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 | 2035 | |
8feceb67 VT |
2036 | /* |
2037 | * As a temporary workaround, assign seq# here; this will likely need | |
2038 | * to be cleaned up to work better with Beacon transmission and virtual | |
2039 | * BSSes. | |
2040 | */ | |
2041 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
2042 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
2043 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) | |
b77f483f | 2044 | sc->tx.seq_no += 0x10; |
8feceb67 | 2045 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
b77f483f | 2046 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); |
8feceb67 | 2047 | } |
f078f209 | 2048 | |
8feceb67 VT |
2049 | /* Add the padding after the header if this is not already done */ |
2050 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
2051 | if (hdrlen & 3) { | |
2052 | padsize = hdrlen % 4; | |
2053 | if (skb_headroom(skb) < padsize) | |
2054 | return -1; | |
2055 | skb_push(skb, padsize); | |
2056 | memmove(skb->data, skb->data + padsize, hdrlen); | |
2057 | } | |
2058 | ||
528f0c6b S |
2059 | /* Check if a tx queue is available */ |
2060 | ||
2061 | txctl.txq = ath_test_get_txq(sc, skb); | |
2062 | if (!txctl.txq) | |
2063 | goto exit; | |
2064 | ||
04bd4638 | 2065 | DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 2066 | |
c52f33d0 | 2067 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
04bd4638 | 2068 | DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 2069 | goto exit; |
8feceb67 VT |
2070 | } |
2071 | ||
528f0c6b S |
2072 | return 0; |
2073 | exit: | |
2074 | dev_kfree_skb_any(skb); | |
8feceb67 | 2075 | return 0; |
f078f209 LR |
2076 | } |
2077 | ||
8feceb67 | 2078 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 2079 | { |
bce048d7 JM |
2080 | struct ath_wiphy *aphy = hw->priv; |
2081 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 2082 | |
9580a222 JM |
2083 | aphy->state = ATH_WIPHY_INACTIVE; |
2084 | ||
9c84b797 | 2085 | if (sc->sc_flags & SC_OP_INVALID) { |
04bd4638 | 2086 | DPRINTF(sc, ATH_DBG_ANY, "Device not present\n"); |
9c84b797 S |
2087 | return; |
2088 | } | |
8feceb67 | 2089 | |
141b38b6 | 2090 | mutex_lock(&sc->mutex); |
ff37e337 | 2091 | |
bce048d7 | 2092 | ieee80211_stop_queues(hw); |
ff37e337 | 2093 | |
9580a222 JM |
2094 | if (ath9k_wiphy_started(sc)) { |
2095 | mutex_unlock(&sc->mutex); | |
2096 | return; /* another wiphy still in use */ | |
2097 | } | |
2098 | ||
ff37e337 S |
2099 | /* make sure h/w will not generate any interrupt |
2100 | * before setting the invalid flag. */ | |
2101 | ath9k_hw_set_interrupts(sc->sc_ah, 0); | |
2102 | ||
2103 | if (!(sc->sc_flags & SC_OP_INVALID)) { | |
043a0405 | 2104 | ath_drain_all_txq(sc, false); |
ff37e337 S |
2105 | ath_stoprecv(sc); |
2106 | ath9k_hw_phy_disable(sc->sc_ah); | |
2107 | } else | |
b77f483f | 2108 | sc->rx.rxlink = NULL; |
ff37e337 | 2109 | |
3b319aae | 2110 | wiphy_rfkill_stop_polling(sc->hw->wiphy); |
19d337df | 2111 | |
ff37e337 S |
2112 | /* disable HAL and put h/w to sleep */ |
2113 | ath9k_hw_disable(sc->sc_ah); | |
2114 | ath9k_hw_configpcipowersave(sc->sc_ah, 1); | |
2115 | ||
2116 | sc->sc_flags |= SC_OP_INVALID; | |
500c064d | 2117 | |
141b38b6 S |
2118 | mutex_unlock(&sc->mutex); |
2119 | ||
04bd4638 | 2120 | DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
2121 | } |
2122 | ||
8feceb67 VT |
2123 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
2124 | struct ieee80211_if_init_conf *conf) | |
f078f209 | 2125 | { |
bce048d7 JM |
2126 | struct ath_wiphy *aphy = hw->priv; |
2127 | struct ath_softc *sc = aphy->sc; | |
17d7904d | 2128 | struct ath_vif *avp = (void *)conf->vif->drv_priv; |
d97809db | 2129 | enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; |
2c3db3d5 | 2130 | int ret = 0; |
8feceb67 | 2131 | |
141b38b6 S |
2132 | mutex_lock(&sc->mutex); |
2133 | ||
8ca21f01 JM |
2134 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) && |
2135 | sc->nvifs > 0) { | |
2136 | ret = -ENOBUFS; | |
2137 | goto out; | |
2138 | } | |
2139 | ||
8feceb67 | 2140 | switch (conf->type) { |
05c914fe | 2141 | case NL80211_IFTYPE_STATION: |
d97809db | 2142 | ic_opmode = NL80211_IFTYPE_STATION; |
f078f209 | 2143 | break; |
05c914fe | 2144 | case NL80211_IFTYPE_ADHOC: |
05c914fe | 2145 | case NL80211_IFTYPE_AP: |
9cb5412b | 2146 | case NL80211_IFTYPE_MESH_POINT: |
2c3db3d5 JM |
2147 | if (sc->nbcnvifs >= ATH_BCBUF) { |
2148 | ret = -ENOBUFS; | |
2149 | goto out; | |
2150 | } | |
9cb5412b | 2151 | ic_opmode = conf->type; |
f078f209 LR |
2152 | break; |
2153 | default: | |
2154 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 2155 | "Interface type %d not yet supported\n", conf->type); |
2c3db3d5 JM |
2156 | ret = -EOPNOTSUPP; |
2157 | goto out; | |
f078f209 LR |
2158 | } |
2159 | ||
17d7904d | 2160 | DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode); |
8feceb67 | 2161 | |
17d7904d | 2162 | /* Set the VIF opmode */ |
5640b08e S |
2163 | avp->av_opmode = ic_opmode; |
2164 | avp->av_bslot = -1; | |
2165 | ||
2c3db3d5 | 2166 | sc->nvifs++; |
8ca21f01 JM |
2167 | |
2168 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) | |
2169 | ath9k_set_bssid_mask(hw); | |
2170 | ||
2c3db3d5 JM |
2171 | if (sc->nvifs > 1) |
2172 | goto out; /* skip global settings for secondary vif */ | |
2173 | ||
b238e90e | 2174 | if (ic_opmode == NL80211_IFTYPE_AP) { |
5640b08e | 2175 | ath9k_hw_set_tsfadjust(sc->sc_ah, 1); |
b238e90e S |
2176 | sc->sc_flags |= SC_OP_TSF_RESET; |
2177 | } | |
5640b08e | 2178 | |
5640b08e | 2179 | /* Set the device opmode */ |
2660b81a | 2180 | sc->sc_ah->opmode = ic_opmode; |
5640b08e | 2181 | |
4e30ffa2 VN |
2182 | /* |
2183 | * Enable MIB interrupts when there are hardware phy counters. | |
2184 | * Note we only do this (at the moment) for station mode. | |
2185 | */ | |
4af9cf4f | 2186 | if ((conf->type == NL80211_IFTYPE_STATION) || |
9cb5412b PE |
2187 | (conf->type == NL80211_IFTYPE_ADHOC) || |
2188 | (conf->type == NL80211_IFTYPE_MESH_POINT)) { | |
4af9cf4f S |
2189 | if (ath9k_hw_phycounters(sc->sc_ah)) |
2190 | sc->imask |= ATH9K_INT_MIB; | |
2191 | sc->imask |= ATH9K_INT_TSFOOR; | |
2192 | } | |
2193 | ||
17d7904d | 2194 | ath9k_hw_set_interrupts(sc->sc_ah, sc->imask); |
4e30ffa2 | 2195 | |
415f738e S |
2196 | if (conf->type == NL80211_IFTYPE_AP) |
2197 | ath_start_ani(sc); | |
6f255425 | 2198 | |
2c3db3d5 | 2199 | out: |
141b38b6 | 2200 | mutex_unlock(&sc->mutex); |
2c3db3d5 | 2201 | return ret; |
f078f209 LR |
2202 | } |
2203 | ||
8feceb67 VT |
2204 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
2205 | struct ieee80211_if_init_conf *conf) | |
f078f209 | 2206 | { |
bce048d7 JM |
2207 | struct ath_wiphy *aphy = hw->priv; |
2208 | struct ath_softc *sc = aphy->sc; | |
17d7904d | 2209 | struct ath_vif *avp = (void *)conf->vif->drv_priv; |
2c3db3d5 | 2210 | int i; |
f078f209 | 2211 | |
04bd4638 | 2212 | DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 2213 | |
141b38b6 S |
2214 | mutex_lock(&sc->mutex); |
2215 | ||
6f255425 | 2216 | /* Stop ANI */ |
17d7904d | 2217 | del_timer_sync(&sc->ani.timer); |
580f0b8a | 2218 | |
8feceb67 | 2219 | /* Reclaim beacon resources */ |
9cb5412b PE |
2220 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || |
2221 | (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) || | |
2222 | (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) { | |
b77f483f | 2223 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); |
8feceb67 | 2224 | ath_beacon_return(sc, avp); |
580f0b8a | 2225 | } |
f078f209 | 2226 | |
8feceb67 | 2227 | sc->sc_flags &= ~SC_OP_BEACONS; |
f078f209 | 2228 | |
2c3db3d5 JM |
2229 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { |
2230 | if (sc->beacon.bslot[i] == conf->vif) { | |
2231 | printk(KERN_DEBUG "%s: vif had allocated beacon " | |
2232 | "slot\n", __func__); | |
2233 | sc->beacon.bslot[i] = NULL; | |
c52f33d0 | 2234 | sc->beacon.bslot_aphy[i] = NULL; |
2c3db3d5 JM |
2235 | } |
2236 | } | |
2237 | ||
17d7904d | 2238 | sc->nvifs--; |
141b38b6 S |
2239 | |
2240 | mutex_unlock(&sc->mutex); | |
f078f209 LR |
2241 | } |
2242 | ||
e8975581 | 2243 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 2244 | { |
bce048d7 JM |
2245 | struct ath_wiphy *aphy = hw->priv; |
2246 | struct ath_softc *sc = aphy->sc; | |
e8975581 | 2247 | struct ieee80211_conf *conf = &hw->conf; |
8782b41d | 2248 | struct ath_hw *ah = sc->sc_ah; |
f078f209 | 2249 | |
aa33de09 | 2250 | mutex_lock(&sc->mutex); |
141b38b6 | 2251 | |
3cbb5dd7 VN |
2252 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
2253 | if (conf->flags & IEEE80211_CONF_PS) { | |
8782b41d VN |
2254 | if (!(ah->caps.hw_caps & |
2255 | ATH9K_HW_CAP_AUTOSLEEP)) { | |
2256 | if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
2257 | sc->imask |= ATH9K_INT_TIM_TIMER; | |
2258 | ath9k_hw_set_interrupts(sc->sc_ah, | |
2259 | sc->imask); | |
2260 | } | |
2261 | ath9k_hw_setrxabort(sc->sc_ah, 1); | |
3cbb5dd7 | 2262 | } |
3cbb5dd7 VN |
2263 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); |
2264 | } else { | |
2265 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); | |
8782b41d VN |
2266 | if (!(ah->caps.hw_caps & |
2267 | ATH9K_HW_CAP_AUTOSLEEP)) { | |
2268 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca JM |
2269 | sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON | |
2270 | SC_OP_WAIT_FOR_CAB | | |
2271 | SC_OP_WAIT_FOR_PSPOLL_DATA | | |
2272 | SC_OP_WAIT_FOR_TX_ACK); | |
8782b41d VN |
2273 | if (sc->imask & ATH9K_INT_TIM_TIMER) { |
2274 | sc->imask &= ~ATH9K_INT_TIM_TIMER; | |
2275 | ath9k_hw_set_interrupts(sc->sc_ah, | |
2276 | sc->imask); | |
2277 | } | |
3cbb5dd7 VN |
2278 | } |
2279 | } | |
2280 | } | |
2281 | ||
4797938c | 2282 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
99405f93 | 2283 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 2284 | int pos = curchan->hw_value; |
ae5eb026 | 2285 | |
0e2dedf9 JM |
2286 | aphy->chan_idx = pos; |
2287 | aphy->chan_is_ht = conf_is_ht(conf); | |
2288 | ||
8089cc47 JM |
2289 | if (aphy->state == ATH_WIPHY_SCAN || |
2290 | aphy->state == ATH_WIPHY_ACTIVE) | |
2291 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
2292 | else { | |
2293 | /* | |
2294 | * Do not change operational channel based on a paused | |
2295 | * wiphy changes. | |
2296 | */ | |
2297 | goto skip_chan_change; | |
2298 | } | |
0e2dedf9 | 2299 | |
04bd4638 S |
2300 | DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n", |
2301 | curchan->center_freq); | |
f078f209 | 2302 | |
5f8e077c | 2303 | /* XXX: remove me eventualy */ |
0e2dedf9 | 2304 | ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); |
e11602b7 | 2305 | |
ecf70441 | 2306 | ath_update_chainmask(sc, conf_is_ht(conf)); |
86060f0d | 2307 | |
0e2dedf9 | 2308 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
04bd4638 | 2309 | DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n"); |
aa33de09 | 2310 | mutex_unlock(&sc->mutex); |
e11602b7 S |
2311 | return -EINVAL; |
2312 | } | |
094d05dc | 2313 | } |
f078f209 | 2314 | |
8089cc47 | 2315 | skip_chan_change: |
5c020dc6 | 2316 | if (changed & IEEE80211_CONF_CHANGE_POWER) |
17d7904d | 2317 | sc->config.txpowlimit = 2 * conf->power_level; |
f078f209 | 2318 | |
aa33de09 | 2319 | mutex_unlock(&sc->mutex); |
141b38b6 | 2320 | |
f078f209 LR |
2321 | return 0; |
2322 | } | |
2323 | ||
8feceb67 VT |
2324 | #define SUPPORTED_FILTERS \ |
2325 | (FIF_PROMISC_IN_BSS | \ | |
2326 | FIF_ALLMULTI | \ | |
2327 | FIF_CONTROL | \ | |
2328 | FIF_OTHER_BSS | \ | |
2329 | FIF_BCN_PRBRESP_PROMISC | \ | |
2330 | FIF_FCSFAIL) | |
c83be688 | 2331 | |
8feceb67 VT |
2332 | /* FIXME: sc->sc_full_reset ? */ |
2333 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
2334 | unsigned int changed_flags, | |
2335 | unsigned int *total_flags, | |
2336 | int mc_count, | |
2337 | struct dev_mc_list *mclist) | |
2338 | { | |
bce048d7 JM |
2339 | struct ath_wiphy *aphy = hw->priv; |
2340 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 2341 | u32 rfilt; |
f078f209 | 2342 | |
8feceb67 VT |
2343 | changed_flags &= SUPPORTED_FILTERS; |
2344 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 2345 | |
b77f483f | 2346 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 2347 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
2348 | rfilt = ath_calcrxfilter(sc); |
2349 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 2350 | ath9k_ps_restore(sc); |
f078f209 | 2351 | |
b77f483f | 2352 | DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter); |
8feceb67 | 2353 | } |
f078f209 | 2354 | |
8feceb67 VT |
2355 | static void ath9k_sta_notify(struct ieee80211_hw *hw, |
2356 | struct ieee80211_vif *vif, | |
2357 | enum sta_notify_cmd cmd, | |
17741cdc | 2358 | struct ieee80211_sta *sta) |
8feceb67 | 2359 | { |
bce048d7 JM |
2360 | struct ath_wiphy *aphy = hw->priv; |
2361 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 2362 | |
8feceb67 VT |
2363 | switch (cmd) { |
2364 | case STA_NOTIFY_ADD: | |
5640b08e | 2365 | ath_node_attach(sc, sta); |
8feceb67 VT |
2366 | break; |
2367 | case STA_NOTIFY_REMOVE: | |
b5aa9bf9 | 2368 | ath_node_detach(sc, sta); |
8feceb67 VT |
2369 | break; |
2370 | default: | |
2371 | break; | |
2372 | } | |
f078f209 LR |
2373 | } |
2374 | ||
141b38b6 | 2375 | static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
8feceb67 | 2376 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 2377 | { |
bce048d7 JM |
2378 | struct ath_wiphy *aphy = hw->priv; |
2379 | struct ath_softc *sc = aphy->sc; | |
8feceb67 VT |
2380 | struct ath9k_tx_queue_info qi; |
2381 | int ret = 0, qnum; | |
f078f209 | 2382 | |
8feceb67 VT |
2383 | if (queue >= WME_NUM_AC) |
2384 | return 0; | |
f078f209 | 2385 | |
141b38b6 S |
2386 | mutex_lock(&sc->mutex); |
2387 | ||
1ffb0610 S |
2388 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
2389 | ||
8feceb67 VT |
2390 | qi.tqi_aifs = params->aifs; |
2391 | qi.tqi_cwmin = params->cw_min; | |
2392 | qi.tqi_cwmax = params->cw_max; | |
2393 | qi.tqi_burstTime = params->txop; | |
2394 | qnum = ath_get_hal_qnum(queue, sc); | |
f078f209 | 2395 | |
8feceb67 | 2396 | DPRINTF(sc, ATH_DBG_CONFIG, |
04bd4638 | 2397 | "Configure tx [queue/halq] [%d/%d], " |
8feceb67 | 2398 | "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", |
04bd4638 S |
2399 | queue, qnum, params->aifs, params->cw_min, |
2400 | params->cw_max, params->txop); | |
f078f209 | 2401 | |
8feceb67 VT |
2402 | ret = ath_txq_update(sc, qnum, &qi); |
2403 | if (ret) | |
04bd4638 | 2404 | DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n"); |
f078f209 | 2405 | |
141b38b6 S |
2406 | mutex_unlock(&sc->mutex); |
2407 | ||
8feceb67 VT |
2408 | return ret; |
2409 | } | |
f078f209 | 2410 | |
8feceb67 VT |
2411 | static int ath9k_set_key(struct ieee80211_hw *hw, |
2412 | enum set_key_cmd cmd, | |
dc822b5d JB |
2413 | struct ieee80211_vif *vif, |
2414 | struct ieee80211_sta *sta, | |
8feceb67 VT |
2415 | struct ieee80211_key_conf *key) |
2416 | { | |
bce048d7 JM |
2417 | struct ath_wiphy *aphy = hw->priv; |
2418 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 2419 | int ret = 0; |
f078f209 | 2420 | |
b3bd89ce JM |
2421 | if (modparam_nohwcrypt) |
2422 | return -ENOSPC; | |
2423 | ||
141b38b6 | 2424 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 2425 | ath9k_ps_wakeup(sc); |
d8baa939 | 2426 | DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n"); |
f078f209 | 2427 | |
8feceb67 VT |
2428 | switch (cmd) { |
2429 | case SET_KEY: | |
3f53dd64 | 2430 | ret = ath_key_config(sc, vif, sta, key); |
6ace2891 JM |
2431 | if (ret >= 0) { |
2432 | key->hw_key_idx = ret; | |
8feceb67 VT |
2433 | /* push IV and Michael MIC generation to stack */ |
2434 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
2435 | if (key->alg == ALG_TKIP) | |
2436 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; | |
0ced0e17 JM |
2437 | if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP) |
2438 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; | |
6ace2891 | 2439 | ret = 0; |
8feceb67 VT |
2440 | } |
2441 | break; | |
2442 | case DISABLE_KEY: | |
2443 | ath_key_delete(sc, key); | |
8feceb67 VT |
2444 | break; |
2445 | default: | |
2446 | ret = -EINVAL; | |
2447 | } | |
f078f209 | 2448 | |
3cbb5dd7 | 2449 | ath9k_ps_restore(sc); |
141b38b6 S |
2450 | mutex_unlock(&sc->mutex); |
2451 | ||
8feceb67 VT |
2452 | return ret; |
2453 | } | |
f078f209 | 2454 | |
8feceb67 VT |
2455 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
2456 | struct ieee80211_vif *vif, | |
2457 | struct ieee80211_bss_conf *bss_conf, | |
2458 | u32 changed) | |
2459 | { | |
bce048d7 JM |
2460 | struct ath_wiphy *aphy = hw->priv; |
2461 | struct ath_softc *sc = aphy->sc; | |
2d0ddec5 JB |
2462 | struct ath_hw *ah = sc->sc_ah; |
2463 | struct ath_vif *avp = (void *)vif->drv_priv; | |
2464 | u32 rfilt = 0; | |
2465 | int error, i; | |
f078f209 | 2466 | |
141b38b6 S |
2467 | mutex_lock(&sc->mutex); |
2468 | ||
2d0ddec5 JB |
2469 | /* |
2470 | * TODO: Need to decide which hw opmode to use for | |
2471 | * multi-interface cases | |
2472 | * XXX: This belongs into add_interface! | |
2473 | */ | |
2474 | if (vif->type == NL80211_IFTYPE_AP && | |
2475 | ah->opmode != NL80211_IFTYPE_AP) { | |
2476 | ah->opmode = NL80211_IFTYPE_STATION; | |
2477 | ath9k_hw_setopmode(ah); | |
2478 | memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN); | |
2479 | sc->curaid = 0; | |
2480 | ath9k_hw_write_associd(sc); | |
2481 | /* Request full reset to get hw opmode changed properly */ | |
2482 | sc->sc_flags |= SC_OP_FULL_RESET; | |
2483 | } | |
2484 | ||
2485 | if ((changed & BSS_CHANGED_BSSID) && | |
2486 | !is_zero_ether_addr(bss_conf->bssid)) { | |
2487 | switch (vif->type) { | |
2488 | case NL80211_IFTYPE_STATION: | |
2489 | case NL80211_IFTYPE_ADHOC: | |
2490 | case NL80211_IFTYPE_MESH_POINT: | |
2491 | /* Set BSSID */ | |
2492 | memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN); | |
2493 | memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); | |
2494 | sc->curaid = 0; | |
2495 | ath9k_hw_write_associd(sc); | |
2496 | ||
2497 | /* Set aggregation protection mode parameters */ | |
2498 | sc->config.ath_aggr_prot = 0; | |
2499 | ||
2500 | DPRINTF(sc, ATH_DBG_CONFIG, | |
2501 | "RX filter 0x%x bssid %pM aid 0x%x\n", | |
2502 | rfilt, sc->curbssid, sc->curaid); | |
2503 | ||
2504 | /* need to reconfigure the beacon */ | |
2505 | sc->sc_flags &= ~SC_OP_BEACONS ; | |
2506 | ||
2507 | break; | |
2508 | default: | |
2509 | break; | |
2510 | } | |
2511 | } | |
2512 | ||
2513 | if ((vif->type == NL80211_IFTYPE_ADHOC) || | |
2514 | (vif->type == NL80211_IFTYPE_AP) || | |
2515 | (vif->type == NL80211_IFTYPE_MESH_POINT)) { | |
2516 | if ((changed & BSS_CHANGED_BEACON) || | |
2517 | (changed & BSS_CHANGED_BEACON_ENABLED && | |
2518 | bss_conf->enable_beacon)) { | |
2519 | /* | |
2520 | * Allocate and setup the beacon frame. | |
2521 | * | |
2522 | * Stop any previous beacon DMA. This may be | |
2523 | * necessary, for example, when an ibss merge | |
2524 | * causes reconfiguration; we may be called | |
2525 | * with beacon transmission active. | |
2526 | */ | |
2527 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2528 | ||
2529 | error = ath_beacon_alloc(aphy, vif); | |
2530 | if (!error) | |
2531 | ath_beacon_config(sc, vif); | |
2532 | } | |
2533 | } | |
2534 | ||
2535 | /* Check for WLAN_CAPABILITY_PRIVACY ? */ | |
2536 | if ((avp->av_opmode != NL80211_IFTYPE_STATION)) { | |
2537 | for (i = 0; i < IEEE80211_WEP_NKID; i++) | |
2538 | if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i)) | |
2539 | ath9k_hw_keysetmac(sc->sc_ah, | |
2540 | (u16)i, | |
2541 | sc->curbssid); | |
2542 | } | |
2543 | ||
2544 | /* Only legacy IBSS for now */ | |
2545 | if (vif->type == NL80211_IFTYPE_ADHOC) | |
2546 | ath_update_chainmask(sc, 0); | |
2547 | ||
8feceb67 | 2548 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
04bd4638 | 2549 | DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
8feceb67 VT |
2550 | bss_conf->use_short_preamble); |
2551 | if (bss_conf->use_short_preamble) | |
2552 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
2553 | else | |
2554 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
2555 | } | |
f078f209 | 2556 | |
8feceb67 | 2557 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
04bd4638 | 2558 | DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
8feceb67 VT |
2559 | bss_conf->use_cts_prot); |
2560 | if (bss_conf->use_cts_prot && | |
2561 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
2562 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
2563 | else | |
2564 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
2565 | } | |
f078f209 | 2566 | |
8feceb67 | 2567 | if (changed & BSS_CHANGED_ASSOC) { |
04bd4638 | 2568 | DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", |
8feceb67 | 2569 | bss_conf->assoc); |
5640b08e | 2570 | ath9k_bss_assoc_info(sc, vif, bss_conf); |
8feceb67 | 2571 | } |
141b38b6 | 2572 | |
57c4d7b4 JB |
2573 | /* |
2574 | * The HW TSF has to be reset when the beacon interval changes. | |
2575 | * We set the flag here, and ath_beacon_config_ap() would take this | |
2576 | * into account when it gets called through the subsequent | |
2577 | * config_interface() call - with IFCC_BEACON in the changed field. | |
2578 | */ | |
2579 | ||
2580 | if (changed & BSS_CHANGED_BEACON_INT) { | |
2581 | sc->sc_flags |= SC_OP_TSF_RESET; | |
2582 | sc->beacon_interval = bss_conf->beacon_int; | |
2583 | } | |
2584 | ||
141b38b6 | 2585 | mutex_unlock(&sc->mutex); |
8feceb67 | 2586 | } |
f078f209 | 2587 | |
8feceb67 VT |
2588 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) |
2589 | { | |
2590 | u64 tsf; | |
bce048d7 JM |
2591 | struct ath_wiphy *aphy = hw->priv; |
2592 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 2593 | |
141b38b6 S |
2594 | mutex_lock(&sc->mutex); |
2595 | tsf = ath9k_hw_gettsf64(sc->sc_ah); | |
2596 | mutex_unlock(&sc->mutex); | |
f078f209 | 2597 | |
8feceb67 VT |
2598 | return tsf; |
2599 | } | |
f078f209 | 2600 | |
3b5d665b AF |
2601 | static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) |
2602 | { | |
bce048d7 JM |
2603 | struct ath_wiphy *aphy = hw->priv; |
2604 | struct ath_softc *sc = aphy->sc; | |
3b5d665b | 2605 | |
141b38b6 S |
2606 | mutex_lock(&sc->mutex); |
2607 | ath9k_hw_settsf64(sc->sc_ah, tsf); | |
2608 | mutex_unlock(&sc->mutex); | |
3b5d665b AF |
2609 | } |
2610 | ||
8feceb67 VT |
2611 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) |
2612 | { | |
bce048d7 JM |
2613 | struct ath_wiphy *aphy = hw->priv; |
2614 | struct ath_softc *sc = aphy->sc; | |
c83be688 | 2615 | |
141b38b6 S |
2616 | mutex_lock(&sc->mutex); |
2617 | ath9k_hw_reset_tsf(sc->sc_ah); | |
2618 | mutex_unlock(&sc->mutex); | |
8feceb67 | 2619 | } |
f078f209 | 2620 | |
8feceb67 | 2621 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
141b38b6 S |
2622 | enum ieee80211_ampdu_mlme_action action, |
2623 | struct ieee80211_sta *sta, | |
2624 | u16 tid, u16 *ssn) | |
8feceb67 | 2625 | { |
bce048d7 JM |
2626 | struct ath_wiphy *aphy = hw->priv; |
2627 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 2628 | int ret = 0; |
f078f209 | 2629 | |
8feceb67 VT |
2630 | switch (action) { |
2631 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
2632 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
2633 | ret = -ENOTSUPP; | |
8feceb67 VT |
2634 | break; |
2635 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
2636 | break; |
2637 | case IEEE80211_AMPDU_TX_START: | |
b5aa9bf9 | 2638 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
8feceb67 VT |
2639 | if (ret < 0) |
2640 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 2641 | "Unable to start TX aggregation\n"); |
8feceb67 | 2642 | else |
17741cdc | 2643 | ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid); |
8feceb67 VT |
2644 | break; |
2645 | case IEEE80211_AMPDU_TX_STOP: | |
b5aa9bf9 | 2646 | ret = ath_tx_aggr_stop(sc, sta, tid); |
8feceb67 VT |
2647 | if (ret < 0) |
2648 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 2649 | "Unable to stop TX aggregation\n"); |
f078f209 | 2650 | |
17741cdc | 2651 | ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid); |
8feceb67 | 2652 | break; |
b1720231 | 2653 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8469cdef S |
2654 | ath_tx_aggr_resume(sc, sta, tid); |
2655 | break; | |
8feceb67 | 2656 | default: |
04bd4638 | 2657 | DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n"); |
8feceb67 VT |
2658 | } |
2659 | ||
2660 | return ret; | |
f078f209 LR |
2661 | } |
2662 | ||
0c98de65 S |
2663 | static void ath9k_sw_scan_start(struct ieee80211_hw *hw) |
2664 | { | |
bce048d7 JM |
2665 | struct ath_wiphy *aphy = hw->priv; |
2666 | struct ath_softc *sc = aphy->sc; | |
0c98de65 | 2667 | |
8089cc47 JM |
2668 | if (ath9k_wiphy_scanning(sc)) { |
2669 | printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the " | |
2670 | "same time\n"); | |
2671 | /* | |
2672 | * Do not allow the concurrent scanning state for now. This | |
2673 | * could be improved with scanning control moved into ath9k. | |
2674 | */ | |
2675 | return; | |
2676 | } | |
2677 | ||
2678 | aphy->state = ATH_WIPHY_SCAN; | |
2679 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
2680 | ||
0c98de65 S |
2681 | mutex_lock(&sc->mutex); |
2682 | sc->sc_flags |= SC_OP_SCANNING; | |
2683 | mutex_unlock(&sc->mutex); | |
2684 | } | |
2685 | ||
2686 | static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) | |
2687 | { | |
bce048d7 JM |
2688 | struct ath_wiphy *aphy = hw->priv; |
2689 | struct ath_softc *sc = aphy->sc; | |
0c98de65 S |
2690 | |
2691 | mutex_lock(&sc->mutex); | |
8089cc47 | 2692 | aphy->state = ATH_WIPHY_ACTIVE; |
0c98de65 | 2693 | sc->sc_flags &= ~SC_OP_SCANNING; |
9c07a777 | 2694 | sc->sc_flags |= SC_OP_FULL_RESET; |
0c98de65 S |
2695 | mutex_unlock(&sc->mutex); |
2696 | } | |
2697 | ||
6baff7f9 | 2698 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2699 | .tx = ath9k_tx, |
2700 | .start = ath9k_start, | |
2701 | .stop = ath9k_stop, | |
2702 | .add_interface = ath9k_add_interface, | |
2703 | .remove_interface = ath9k_remove_interface, | |
2704 | .config = ath9k_config, | |
8feceb67 | 2705 | .configure_filter = ath9k_configure_filter, |
8feceb67 VT |
2706 | .sta_notify = ath9k_sta_notify, |
2707 | .conf_tx = ath9k_conf_tx, | |
8feceb67 | 2708 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2709 | .set_key = ath9k_set_key, |
8feceb67 | 2710 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2711 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2712 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2713 | .ampdu_action = ath9k_ampdu_action, |
0c98de65 S |
2714 | .sw_scan_start = ath9k_sw_scan_start, |
2715 | .sw_scan_complete = ath9k_sw_scan_complete, | |
3b319aae | 2716 | .rfkill_poll = ath9k_rfkill_poll_state, |
8feceb67 VT |
2717 | }; |
2718 | ||
392dff83 BP |
2719 | static struct { |
2720 | u32 version; | |
2721 | const char * name; | |
2722 | } ath_mac_bb_names[] = { | |
2723 | { AR_SREV_VERSION_5416_PCI, "5416" }, | |
2724 | { AR_SREV_VERSION_5416_PCIE, "5418" }, | |
2725 | { AR_SREV_VERSION_9100, "9100" }, | |
2726 | { AR_SREV_VERSION_9160, "9160" }, | |
2727 | { AR_SREV_VERSION_9280, "9280" }, | |
2728 | { AR_SREV_VERSION_9285, "9285" } | |
2729 | }; | |
2730 | ||
2731 | static struct { | |
2732 | u16 version; | |
2733 | const char * name; | |
2734 | } ath_rf_names[] = { | |
2735 | { 0, "5133" }, | |
2736 | { AR_RAD5133_SREV_MAJOR, "5133" }, | |
2737 | { AR_RAD5122_SREV_MAJOR, "5122" }, | |
2738 | { AR_RAD2133_SREV_MAJOR, "2133" }, | |
2739 | { AR_RAD2122_SREV_MAJOR, "2122" } | |
2740 | }; | |
2741 | ||
2742 | /* | |
2743 | * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. | |
2744 | */ | |
6baff7f9 | 2745 | const char * |
392dff83 BP |
2746 | ath_mac_bb_name(u32 mac_bb_version) |
2747 | { | |
2748 | int i; | |
2749 | ||
2750 | for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { | |
2751 | if (ath_mac_bb_names[i].version == mac_bb_version) { | |
2752 | return ath_mac_bb_names[i].name; | |
2753 | } | |
2754 | } | |
2755 | ||
2756 | return "????"; | |
2757 | } | |
2758 | ||
2759 | /* | |
2760 | * Return the RF name. "????" is returned if the RF is unknown. | |
2761 | */ | |
6baff7f9 | 2762 | const char * |
392dff83 BP |
2763 | ath_rf_name(u16 rf_version) |
2764 | { | |
2765 | int i; | |
2766 | ||
2767 | for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { | |
2768 | if (ath_rf_names[i].version == rf_version) { | |
2769 | return ath_rf_names[i].name; | |
2770 | } | |
2771 | } | |
2772 | ||
2773 | return "????"; | |
2774 | } | |
2775 | ||
6baff7f9 | 2776 | static int __init ath9k_init(void) |
f078f209 | 2777 | { |
ca8a8560 VT |
2778 | int error; |
2779 | ||
ca8a8560 VT |
2780 | /* Register rate control algorithm */ |
2781 | error = ath_rate_control_register(); | |
2782 | if (error != 0) { | |
2783 | printk(KERN_ERR | |
b51bb3cd LR |
2784 | "ath9k: Unable to register rate control " |
2785 | "algorithm: %d\n", | |
ca8a8560 | 2786 | error); |
6baff7f9 | 2787 | goto err_out; |
ca8a8560 VT |
2788 | } |
2789 | ||
19d8bc22 GJ |
2790 | error = ath9k_debug_create_root(); |
2791 | if (error) { | |
2792 | printk(KERN_ERR | |
2793 | "ath9k: Unable to create debugfs root: %d\n", | |
2794 | error); | |
2795 | goto err_rate_unregister; | |
2796 | } | |
2797 | ||
6baff7f9 GJ |
2798 | error = ath_pci_init(); |
2799 | if (error < 0) { | |
f078f209 | 2800 | printk(KERN_ERR |
b51bb3cd | 2801 | "ath9k: No PCI devices found, driver not installed.\n"); |
6baff7f9 | 2802 | error = -ENODEV; |
19d8bc22 | 2803 | goto err_remove_root; |
f078f209 LR |
2804 | } |
2805 | ||
09329d37 GJ |
2806 | error = ath_ahb_init(); |
2807 | if (error < 0) { | |
2808 | error = -ENODEV; | |
2809 | goto err_pci_exit; | |
2810 | } | |
2811 | ||
f078f209 | 2812 | return 0; |
6baff7f9 | 2813 | |
09329d37 GJ |
2814 | err_pci_exit: |
2815 | ath_pci_exit(); | |
2816 | ||
19d8bc22 GJ |
2817 | err_remove_root: |
2818 | ath9k_debug_remove_root(); | |
6baff7f9 GJ |
2819 | err_rate_unregister: |
2820 | ath_rate_control_unregister(); | |
2821 | err_out: | |
2822 | return error; | |
f078f209 | 2823 | } |
6baff7f9 | 2824 | module_init(ath9k_init); |
f078f209 | 2825 | |
6baff7f9 | 2826 | static void __exit ath9k_exit(void) |
f078f209 | 2827 | { |
09329d37 | 2828 | ath_ahb_exit(); |
6baff7f9 | 2829 | ath_pci_exit(); |
19d8bc22 | 2830 | ath9k_debug_remove_root(); |
ca8a8560 | 2831 | ath_rate_control_unregister(); |
04bd4638 | 2832 | printk(KERN_INFO "%s: Driver unloaded\n", dev_info); |
f078f209 | 2833 | } |
6baff7f9 | 2834 | module_exit(ath9k_exit); |