Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
69081624 | 18 | #include <linux/delay.h> |
394cf0a1 | 19 | #include "ath9k.h" |
af03abec | 20 | #include "btcoex.h" |
f078f209 | 21 | |
6dcc3444 SM |
22 | static void ath9k_set_assoc_state(struct ath_softc *sc, |
23 | struct ieee80211_vif *vif); | |
24 | ||
313eb87f | 25 | u8 ath9k_parse_mpdudensity(u8 mpdudensity) |
ff37e337 S |
26 | { |
27 | /* | |
28 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
29 | * 0 for no restriction | |
30 | * 1 for 1/4 us | |
31 | * 2 for 1/2 us | |
32 | * 3 for 1 us | |
33 | * 4 for 2 us | |
34 | * 5 for 4 us | |
35 | * 6 for 8 us | |
36 | * 7 for 16 us | |
37 | */ | |
38 | switch (mpdudensity) { | |
39 | case 0: | |
40 | return 0; | |
41 | case 1: | |
42 | case 2: | |
43 | case 3: | |
44 | /* Our lower layer calculations limit our precision to | |
45 | 1 microsecond */ | |
46 | return 1; | |
47 | case 4: | |
48 | return 2; | |
49 | case 5: | |
50 | return 4; | |
51 | case 6: | |
52 | return 8; | |
53 | case 7: | |
54 | return 16; | |
55 | default: | |
56 | return 0; | |
57 | } | |
58 | } | |
59 | ||
69081624 VT |
60 | static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) |
61 | { | |
62 | bool pending = false; | |
63 | ||
64 | spin_lock_bh(&txq->axq_lock); | |
65 | ||
66 | if (txq->axq_depth || !list_empty(&txq->axq_acq)) | |
67 | pending = true; | |
69081624 VT |
68 | |
69 | spin_unlock_bh(&txq->axq_lock); | |
70 | return pending; | |
71 | } | |
72 | ||
6d79cb4c | 73 | static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
74 | { |
75 | unsigned long flags; | |
76 | bool ret; | |
77 | ||
9ecdef4b LR |
78 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
79 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
80 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
81 | |
82 | return ret; | |
83 | } | |
84 | ||
bf3dac5a FF |
85 | void ath_ps_full_sleep(unsigned long data) |
86 | { | |
87 | struct ath_softc *sc = (struct ath_softc *) data; | |
88 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
89 | bool reset; | |
90 | ||
91 | spin_lock(&common->cc_lock); | |
92 | ath_hw_cycle_counters_update(common); | |
93 | spin_unlock(&common->cc_lock); | |
94 | ||
95 | ath9k_hw_setrxabort(sc->sc_ah, 1); | |
96 | ath9k_hw_stopdmarecv(sc->sc_ah, &reset); | |
97 | ||
98 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); | |
99 | } | |
100 | ||
a91d75ae LR |
101 | void ath9k_ps_wakeup(struct ath_softc *sc) |
102 | { | |
898c914a | 103 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae | 104 | unsigned long flags; |
fbb078fc | 105 | enum ath9k_power_mode power_mode; |
a91d75ae LR |
106 | |
107 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
108 | if (++sc->ps_usecount != 1) | |
109 | goto unlock; | |
110 | ||
bf3dac5a | 111 | del_timer_sync(&sc->sleep_timer); |
fbb078fc | 112 | power_mode = sc->sc_ah->power_mode; |
9ecdef4b | 113 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae | 114 | |
898c914a FF |
115 | /* |
116 | * While the hardware is asleep, the cycle counters contain no | |
117 | * useful data. Better clear them now so that they don't mess up | |
118 | * survey data results. | |
119 | */ | |
fbb078fc FF |
120 | if (power_mode != ATH9K_PM_AWAKE) { |
121 | spin_lock(&common->cc_lock); | |
122 | ath_hw_cycle_counters_update(common); | |
123 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
c9ae6ab4 | 124 | memset(&common->cc_ani, 0, sizeof(common->cc_ani)); |
fbb078fc FF |
125 | spin_unlock(&common->cc_lock); |
126 | } | |
898c914a | 127 | |
a91d75ae LR |
128 | unlock: |
129 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
130 | } | |
131 | ||
132 | void ath9k_ps_restore(struct ath_softc *sc) | |
133 | { | |
898c914a | 134 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
c6c539f0 | 135 | enum ath9k_power_mode mode; |
a91d75ae LR |
136 | unsigned long flags; |
137 | ||
138 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
139 | if (--sc->ps_usecount != 0) | |
140 | goto unlock; | |
141 | ||
ad128860 | 142 | if (sc->ps_idle) { |
bf3dac5a FF |
143 | mod_timer(&sc->sleep_timer, jiffies + HZ / 10); |
144 | goto unlock; | |
145 | } | |
146 | ||
147 | if (sc->ps_enabled && | |
ad128860 SM |
148 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | |
149 | PS_WAIT_FOR_CAB | | |
150 | PS_WAIT_FOR_PSPOLL_DATA | | |
424749c7 RM |
151 | PS_WAIT_FOR_TX_ACK | |
152 | PS_WAIT_FOR_ANI))) { | |
c6c539f0 | 153 | mode = ATH9K_PM_NETWORK_SLEEP; |
08d4df41 RM |
154 | if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) |
155 | ath9k_btcoex_stop_gen_timer(sc); | |
ad128860 | 156 | } else { |
c6c539f0 | 157 | goto unlock; |
ad128860 | 158 | } |
c6c539f0 FF |
159 | |
160 | spin_lock(&common->cc_lock); | |
161 | ath_hw_cycle_counters_update(common); | |
162 | spin_unlock(&common->cc_lock); | |
163 | ||
1a8f0d39 | 164 | ath9k_hw_setpower(sc->sc_ah, mode); |
a91d75ae LR |
165 | |
166 | unlock: | |
167 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
168 | } | |
169 | ||
9adcf440 | 170 | static void __ath_cancel_work(struct ath_softc *sc) |
ff37e337 | 171 | { |
5ee08656 | 172 | cancel_work_sync(&sc->paprd_work); |
5ee08656 | 173 | cancel_delayed_work_sync(&sc->tx_complete_work); |
181fb18d | 174 | cancel_delayed_work_sync(&sc->hw_pll_work); |
fad29cd2 | 175 | |
bf52592f | 176 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
fad29cd2 SM |
177 | if (ath9k_hw_mci_is_enabled(sc->sc_ah)) |
178 | cancel_work_sync(&sc->mci_work); | |
bf52592f | 179 | #endif |
9adcf440 | 180 | } |
5ee08656 | 181 | |
e60001e7 | 182 | void ath_cancel_work(struct ath_softc *sc) |
9adcf440 FF |
183 | { |
184 | __ath_cancel_work(sc); | |
185 | cancel_work_sync(&sc->hw_reset_work); | |
186 | } | |
3cbb5dd7 | 187 | |
e60001e7 | 188 | void ath_restart_work(struct ath_softc *sc) |
af68abad | 189 | { |
af68abad SM |
190 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
191 | ||
19c36160 | 192 | if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah)) |
af68abad SM |
193 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, |
194 | msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); | |
195 | ||
da0d45f7 | 196 | ath_start_ani(sc); |
af68abad SM |
197 | } |
198 | ||
9ebea382 | 199 | static bool ath_prepare_reset(struct ath_softc *sc) |
9adcf440 FF |
200 | { |
201 | struct ath_hw *ah = sc->sc_ah; | |
ceea2a51 | 202 | bool ret = true; |
6a6733f2 | 203 | |
9adcf440 | 204 | ieee80211_stop_queues(sc->hw); |
da0d45f7 | 205 | ath_stop_ani(sc); |
9adcf440 | 206 | ath9k_hw_disable_interrupts(ah); |
8b3f4616 | 207 | |
1381559b | 208 | if (!ath_drain_all_txq(sc)) |
9adcf440 | 209 | ret = false; |
c0d7c7af | 210 | |
0a62acb1 | 211 | if (!ath_stoprecv(sc)) |
ceea2a51 FF |
212 | ret = false; |
213 | ||
9adcf440 FF |
214 | return ret; |
215 | } | |
ff37e337 | 216 | |
9adcf440 FF |
217 | static bool ath_complete_reset(struct ath_softc *sc, bool start) |
218 | { | |
219 | struct ath_hw *ah = sc->sc_ah; | |
220 | struct ath_common *common = ath9k_hw_common(ah); | |
196fb860 | 221 | unsigned long flags; |
ec30326e | 222 | int i; |
c0d7c7af | 223 | |
c0d7c7af | 224 | if (ath_startrecv(sc) != 0) { |
3800276a | 225 | ath_err(common, "Unable to restart recv logic\n"); |
9adcf440 | 226 | return false; |
c0d7c7af LR |
227 | } |
228 | ||
5048e8c3 RM |
229 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
230 | sc->config.txpowlimit, &sc->curtxpow); | |
b74713d0 SM |
231 | |
232 | clear_bit(SC_OP_HW_RESET, &sc->sc_flags); | |
72d874c6 | 233 | ath9k_hw_set_interrupts(ah); |
b037b693 | 234 | ath9k_hw_enable_interrupts(ah); |
3989279c | 235 | |
4cb54fa3 | 236 | if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) { |
196fb860 SM |
237 | if (!test_bit(SC_OP_BEACONS, &sc->sc_flags)) |
238 | goto work; | |
239 | ||
196fb860 SM |
240 | if (ah->opmode == NL80211_IFTYPE_STATION && |
241 | test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { | |
242 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
243 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
244 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
a6768280 SM |
245 | } else { |
246 | ath9k_set_beacon(sc); | |
196fb860 SM |
247 | } |
248 | work: | |
af68abad | 249 | ath_restart_work(sc); |
ec30326e FF |
250 | |
251 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
252 | if (!ATH_TXQ_SETUP(sc, i)) | |
253 | continue; | |
254 | ||
255 | spin_lock_bh(&sc->tx.txq[i].axq_lock); | |
256 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
257 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
258 | } | |
5ee08656 FF |
259 | } |
260 | ||
071aa9a8 | 261 | sc->gtt_cnt = 0; |
9adcf440 FF |
262 | ieee80211_wake_queues(sc->hw); |
263 | ||
264 | return true; | |
265 | } | |
266 | ||
1381559b | 267 | static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan) |
9adcf440 FF |
268 | { |
269 | struct ath_hw *ah = sc->sc_ah; | |
270 | struct ath_common *common = ath9k_hw_common(ah); | |
271 | struct ath9k_hw_cal_data *caldata = NULL; | |
272 | bool fastcc = true; | |
9adcf440 FF |
273 | int r; |
274 | ||
275 | __ath_cancel_work(sc); | |
276 | ||
4668cce5 | 277 | tasklet_disable(&sc->intr_tq); |
9adcf440 | 278 | spin_lock_bh(&sc->sc_pcu_lock); |
92460412 | 279 | |
4cb54fa3 | 280 | if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) { |
9adcf440 FF |
281 | fastcc = false; |
282 | caldata = &sc->caldata; | |
283 | } | |
284 | ||
285 | if (!hchan) { | |
286 | fastcc = false; | |
9adcf440 FF |
287 | hchan = ah->curchan; |
288 | } | |
289 | ||
9ebea382 | 290 | if (!ath_prepare_reset(sc)) |
9adcf440 FF |
291 | fastcc = false; |
292 | ||
d2182b69 | 293 | ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", |
feced201 | 294 | hchan->channel, IS_CHAN_HT40(hchan), fastcc); |
9adcf440 FF |
295 | |
296 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); | |
297 | if (r) { | |
298 | ath_err(common, | |
299 | "Unable to reset channel, reset status %d\n", r); | |
f50b1cd3 RS |
300 | |
301 | ath9k_hw_enable_interrupts(ah); | |
302 | ath9k_queue_reset(sc, RESET_TYPE_BB_HANG); | |
303 | ||
9adcf440 FF |
304 | goto out; |
305 | } | |
306 | ||
e82cb03f RM |
307 | if (ath9k_hw_mci_is_enabled(sc->sc_ah) && |
308 | (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) | |
309 | ath9k_mci_set_txpower(sc, true, false); | |
310 | ||
9adcf440 FF |
311 | if (!ath_complete_reset(sc, true)) |
312 | r = -EIO; | |
313 | ||
314 | out: | |
6a6733f2 | 315 | spin_unlock_bh(&sc->sc_pcu_lock); |
4668cce5 FF |
316 | tasklet_enable(&sc->intr_tq); |
317 | ||
9adcf440 FF |
318 | return r; |
319 | } | |
320 | ||
321 | ||
322 | /* | |
323 | * Set/change channels. If the channel is really being changed, it's done | |
324 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
325 | * DMA, then restart stuff. | |
326 | */ | |
45c67f6f | 327 | static int ath_set_channel(struct ath_softc *sc, struct cfg80211_chan_def *chandef) |
9adcf440 | 328 | { |
45c67f6f FF |
329 | struct ath_hw *ah = sc->sc_ah; |
330 | struct ath_common *common = ath9k_hw_common(ah); | |
331 | struct ieee80211_hw *hw = sc->hw; | |
332 | struct ath9k_channel *hchan; | |
333 | struct ieee80211_channel *chan = chandef->chan; | |
45c67f6f FF |
334 | bool offchannel; |
335 | int pos = chan->hw_value; | |
336 | int old_pos = -1; | |
9adcf440 FF |
337 | int r; |
338 | ||
781b14a3 | 339 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) |
9adcf440 FF |
340 | return -EIO; |
341 | ||
45c67f6f FF |
342 | offchannel = !!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL); |
343 | ||
344 | if (ah->curchan) | |
345 | old_pos = ah->curchan - &ah->channels[0]; | |
346 | ||
347 | ath_dbg(common, CONFIG, "Set channel: %d MHz width: %d\n", | |
348 | chan->center_freq, chandef->width); | |
349 | ||
350 | /* update survey stats for the old channel before switching */ | |
b7cc9b97 | 351 | spin_lock_bh(&common->cc_lock); |
45c67f6f | 352 | ath_update_survey_stats(sc); |
b7cc9b97 | 353 | spin_unlock_bh(&common->cc_lock); |
45c67f6f FF |
354 | |
355 | ath9k_cmn_get_channel(hw, ah, chandef); | |
356 | ||
357 | /* | |
358 | * If the operating channel changes, change the survey in-use flags | |
359 | * along with it. | |
360 | * Reset the survey data for the new channel, unless we're switching | |
361 | * back to the operating channel from an off-channel operation. | |
362 | */ | |
363 | if (!offchannel && sc->cur_survey != &sc->survey[pos]) { | |
364 | if (sc->cur_survey) | |
365 | sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; | |
366 | ||
367 | sc->cur_survey = &sc->survey[pos]; | |
368 | ||
369 | memset(sc->cur_survey, 0, sizeof(struct survey_info)); | |
370 | sc->cur_survey->filled |= SURVEY_INFO_IN_USE; | |
371 | } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { | |
372 | memset(&sc->survey[pos], 0, sizeof(struct survey_info)); | |
373 | } | |
374 | ||
375 | hchan = &sc->sc_ah->channels[pos]; | |
1381559b | 376 | r = ath_reset_internal(sc, hchan); |
45c67f6f FF |
377 | if (r) |
378 | return r; | |
6a6733f2 | 379 | |
45c67f6f FF |
380 | /* |
381 | * The most recent snapshot of channel->noisefloor for the old | |
382 | * channel is only available after the hardware reset. Copy it to | |
383 | * the survey stats now. | |
384 | */ | |
385 | if (old_pos >= 0) | |
386 | ath_update_survey_nf(sc, old_pos); | |
387 | ||
388 | /* | |
389 | * Enable radar pulse detection if on a DFS channel. Spectral | |
390 | * scanning and radar detection can not be used concurrently. | |
391 | */ | |
392 | if (hw->conf.radar_enabled) { | |
393 | u32 rxfilter; | |
394 | ||
395 | /* set HW specific DFS configuration */ | |
396 | ath9k_hw_set_radar_params(ah); | |
397 | rxfilter = ath9k_hw_getrxfilter(ah); | |
398 | rxfilter |= ATH9K_RX_FILTER_PHYRADAR | | |
399 | ATH9K_RX_FILTER_PHYERR; | |
400 | ath9k_hw_setrxfilter(ah, rxfilter); | |
401 | ath_dbg(common, DFS, "DFS enabled at freq %d\n", | |
402 | chan->center_freq); | |
403 | } else { | |
404 | /* perform spectral scan if requested. */ | |
405 | if (test_bit(SC_OP_SCANNING, &sc->sc_flags) && | |
406 | sc->spectral_mode == SPECTRAL_CHANSCAN) | |
407 | ath9k_spectral_scan_trigger(hw); | |
408 | } | |
409 | ||
410 | return 0; | |
ff37e337 S |
411 | } |
412 | ||
7e1e3864 BG |
413 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, |
414 | struct ieee80211_vif *vif) | |
ff37e337 S |
415 | { |
416 | struct ath_node *an; | |
ff37e337 S |
417 | an = (struct ath_node *)sta->drv_priv; |
418 | ||
a145daf7 | 419 | an->sc = sc; |
7f010c93 | 420 | an->sta = sta; |
7e1e3864 | 421 | an->vif = vif; |
3d4e20f2 | 422 | |
dd5ee59b | 423 | ath_tx_node_init(sc, an); |
ff37e337 S |
424 | } |
425 | ||
426 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
427 | { | |
428 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
dd5ee59b | 429 | ath_tx_node_cleanup(sc, an); |
ff37e337 S |
430 | } |
431 | ||
55624204 | 432 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
433 | { |
434 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 435 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 436 | struct ath_common *common = ath9k_hw_common(ah); |
124b979b | 437 | enum ath_reset_type type; |
07c15a3f | 438 | unsigned long flags; |
17d7904d | 439 | u32 status = sc->intrstatus; |
b5c80475 | 440 | u32 rxmask; |
ff37e337 | 441 | |
e3927007 FF |
442 | ath9k_ps_wakeup(sc); |
443 | spin_lock(&sc->sc_pcu_lock); | |
444 | ||
6549a860 SM |
445 | if (status & ATH9K_INT_FATAL) { |
446 | type = RESET_TYPE_FATAL_INT; | |
124b979b | 447 | ath9k_queue_reset(sc, type); |
c6cc47b1 SM |
448 | |
449 | /* | |
450 | * Increment the ref. counter here so that | |
451 | * interrupts are enabled in the reset routine. | |
452 | */ | |
453 | atomic_inc(&ah->intr_ref_cnt); | |
454 | ath_dbg(common, ANY, "FATAL: Skipping interrupts\n"); | |
e3927007 | 455 | goto out; |
063d8be3 | 456 | } |
ff37e337 | 457 | |
6549a860 SM |
458 | if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && |
459 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
0c759977 SM |
460 | spin_lock(&common->cc_lock); |
461 | ath_hw_cycle_counters_update(common); | |
462 | ar9003_hw_bb_watchdog_dbg_info(ah); | |
463 | spin_unlock(&common->cc_lock); | |
464 | ||
6549a860 SM |
465 | if (ar9003_hw_bb_watchdog_check(ah)) { |
466 | type = RESET_TYPE_BB_WATCHDOG; | |
467 | ath9k_queue_reset(sc, type); | |
468 | ||
469 | /* | |
470 | * Increment the ref. counter here so that | |
471 | * interrupts are enabled in the reset routine. | |
472 | */ | |
473 | atomic_inc(&ah->intr_ref_cnt); | |
474 | ath_dbg(common, ANY, | |
475 | "BB_WATCHDOG: Skipping interrupts\n"); | |
476 | goto out; | |
477 | } | |
478 | } | |
479 | ||
071aa9a8 SM |
480 | if (status & ATH9K_INT_GTT) { |
481 | sc->gtt_cnt++; | |
482 | ||
483 | if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) { | |
484 | type = RESET_TYPE_TX_GTT; | |
485 | ath9k_queue_reset(sc, type); | |
486 | atomic_inc(&ah->intr_ref_cnt); | |
487 | ath_dbg(common, ANY, | |
488 | "GTT: Skipping interrupts\n"); | |
489 | goto out; | |
490 | } | |
491 | } | |
492 | ||
07c15a3f | 493 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
4105f807 RM |
494 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
495 | /* | |
496 | * TSF sync does not look correct; remain awake to sync with | |
497 | * the next Beacon. | |
498 | */ | |
d2182b69 | 499 | ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); |
e8fe7336 | 500 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
4105f807 | 501 | } |
07c15a3f | 502 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
4105f807 | 503 | |
b5c80475 FF |
504 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
505 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
506 | ATH9K_INT_RXORN); | |
507 | else | |
508 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
509 | ||
510 | if (status & rxmask) { | |
b5c80475 FF |
511 | /* Check for high priority Rx first */ |
512 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
513 | (status & ATH9K_INT_RXHP)) | |
514 | ath_rx_tasklet(sc, 0, true); | |
515 | ||
516 | ath_rx_tasklet(sc, 0, false); | |
ff37e337 S |
517 | } |
518 | ||
e5003249 | 519 | if (status & ATH9K_INT_TX) { |
071aa9a8 SM |
520 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
521 | /* | |
522 | * For EDMA chips, TX completion is enabled for the | |
523 | * beacon queue, so if a beacon has been transmitted | |
524 | * successfully after a GTT interrupt, the GTT counter | |
525 | * gets reset to zero here. | |
526 | */ | |
527 | /* sc->gtt_cnt = 0; */ | |
528 | ||
e5003249 | 529 | ath_tx_edma_tasklet(sc); |
071aa9a8 | 530 | } else { |
e5003249 | 531 | ath_tx_tasklet(sc); |
071aa9a8 | 532 | } |
10e23181 FF |
533 | |
534 | wake_up(&sc->tx_wait); | |
e5003249 | 535 | } |
063d8be3 | 536 | |
c67ce339 FF |
537 | if (status & ATH9K_INT_GENTIMER) |
538 | ath_gen_timer_isr(sc->sc_ah); | |
539 | ||
56ca0dba | 540 | ath9k_btcoex_handle_interrupt(sc, status); |
19686ddf | 541 | |
ff37e337 | 542 | /* re-enable hardware interrupt */ |
4df3071e | 543 | ath9k_hw_enable_interrupts(ah); |
c6cc47b1 | 544 | out: |
52671e43 | 545 | spin_unlock(&sc->sc_pcu_lock); |
153e080d | 546 | ath9k_ps_restore(sc); |
ff37e337 S |
547 | } |
548 | ||
6baff7f9 | 549 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 550 | { |
063d8be3 S |
551 | #define SCHED_INTR ( \ |
552 | ATH9K_INT_FATAL | \ | |
a4d86d95 | 553 | ATH9K_INT_BB_WATCHDOG | \ |
063d8be3 S |
554 | ATH9K_INT_RXORN | \ |
555 | ATH9K_INT_RXEOL | \ | |
556 | ATH9K_INT_RX | \ | |
b5c80475 FF |
557 | ATH9K_INT_RXLP | \ |
558 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
559 | ATH9K_INT_TX | \ |
560 | ATH9K_INT_BMISS | \ | |
561 | ATH9K_INT_CST | \ | |
071aa9a8 | 562 | ATH9K_INT_GTT | \ |
ebb8e1d7 | 563 | ATH9K_INT_TSFOOR | \ |
40dc5392 MSS |
564 | ATH9K_INT_GENTIMER | \ |
565 | ATH9K_INT_MCI) | |
063d8be3 | 566 | |
ff37e337 | 567 | struct ath_softc *sc = dev; |
cbe61d8a | 568 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 | 569 | enum ath9k_int status; |
78c8a950 | 570 | u32 sync_cause = 0; |
ff37e337 S |
571 | bool sched = false; |
572 | ||
063d8be3 S |
573 | /* |
574 | * The hardware is not ready/present, don't | |
575 | * touch anything. Note this can happen early | |
576 | * on if the IRQ is shared. | |
577 | */ | |
781b14a3 | 578 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) |
063d8be3 | 579 | return IRQ_NONE; |
ff37e337 | 580 | |
063d8be3 S |
581 | /* shared irq, not for us */ |
582 | ||
153e080d | 583 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 584 | return IRQ_NONE; |
063d8be3 | 585 | |
f41a9b3b FF |
586 | if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) { |
587 | ath9k_hw_kill_interrupts(ah); | |
b74713d0 | 588 | return IRQ_HANDLED; |
f41a9b3b | 589 | } |
b74713d0 | 590 | |
063d8be3 S |
591 | /* |
592 | * Figure out the reason(s) for the interrupt. Note | |
593 | * that the hal returns a pseudo-ISR that may include | |
594 | * bits we haven't explicitly enabled so we mask the | |
595 | * value to insure we only process bits we requested. | |
596 | */ | |
6a4d05dc FF |
597 | ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */ |
598 | ath9k_debug_sync_cause(sc, sync_cause); | |
3069168c | 599 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 600 | |
063d8be3 S |
601 | /* |
602 | * If there are no status bits set, then this interrupt was not | |
603 | * for me (should have been caught above). | |
604 | */ | |
153e080d | 605 | if (!status) |
063d8be3 | 606 | return IRQ_NONE; |
ff37e337 | 607 | |
063d8be3 S |
608 | /* Cache the status */ |
609 | sc->intrstatus = status; | |
610 | ||
611 | if (status & SCHED_INTR) | |
612 | sched = true; | |
613 | ||
614 | /* | |
615 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
616 | * chip immediately. | |
617 | */ | |
b5c80475 FF |
618 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
619 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
620 | goto chip_reset; |
621 | ||
a6bb860b | 622 | if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && |
0c759977 | 623 | (status & ATH9K_INT_BB_WATCHDOG)) |
08578b8f | 624 | goto chip_reset; |
e60001e7 SM |
625 | |
626 | #ifdef CONFIG_ATH9K_WOW | |
ca90ef44 RM |
627 | if (status & ATH9K_INT_BMISS) { |
628 | if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { | |
ca90ef44 RM |
629 | atomic_inc(&sc->wow_got_bmiss_intr); |
630 | atomic_dec(&sc->wow_sleep_proc_intr); | |
631 | } | |
632 | } | |
633 | #endif | |
e60001e7 | 634 | |
063d8be3 S |
635 | if (status & ATH9K_INT_SWBA) |
636 | tasklet_schedule(&sc->bcon_tasklet); | |
637 | ||
638 | if (status & ATH9K_INT_TXURN) | |
639 | ath9k_hw_updatetxtriglevel(ah, true); | |
640 | ||
0682c9b5 RM |
641 | if (status & ATH9K_INT_RXEOL) { |
642 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
72d874c6 | 643 | ath9k_hw_set_interrupts(ah); |
b5c80475 FF |
644 | } |
645 | ||
153e080d VT |
646 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
647 | if (status & ATH9K_INT_TIM_TIMER) { | |
ff9f0b63 LR |
648 | if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) |
649 | goto chip_reset; | |
063d8be3 S |
650 | /* Clear RxAbort bit so that we can |
651 | * receive frames */ | |
9ecdef4b | 652 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
07c15a3f | 653 | spin_lock(&sc->sc_pm_lock); |
153e080d | 654 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 655 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
07c15a3f | 656 | spin_unlock(&sc->sc_pm_lock); |
ff37e337 | 657 | } |
063d8be3 S |
658 | |
659 | chip_reset: | |
ff37e337 | 660 | |
817e11de S |
661 | ath_debug_stat_interrupt(sc, status); |
662 | ||
ff37e337 | 663 | if (sched) { |
4df3071e FF |
664 | /* turn off every interrupt */ |
665 | ath9k_hw_disable_interrupts(ah); | |
ff37e337 S |
666 | tasklet_schedule(&sc->intr_tq); |
667 | } | |
668 | ||
669 | return IRQ_HANDLED; | |
063d8be3 S |
670 | |
671 | #undef SCHED_INTR | |
ff37e337 S |
672 | } |
673 | ||
ef6b19e4 | 674 | int ath_reset(struct ath_softc *sc) |
ff37e337 | 675 | { |
ec30326e | 676 | int r; |
ff37e337 | 677 | |
783cd01e | 678 | ath9k_ps_wakeup(sc); |
1381559b | 679 | r = ath_reset_internal(sc, NULL); |
783cd01e | 680 | ath9k_ps_restore(sc); |
2ab81d4a | 681 | |
ae8d2858 | 682 | return r; |
ff37e337 S |
683 | } |
684 | ||
124b979b RM |
685 | void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) |
686 | { | |
687 | #ifdef CONFIG_ATH9K_DEBUGFS | |
688 | RESET_STAT_INC(sc, type); | |
689 | #endif | |
690 | set_bit(SC_OP_HW_RESET, &sc->sc_flags); | |
691 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); | |
692 | } | |
693 | ||
236de514 FF |
694 | void ath_reset_work(struct work_struct *work) |
695 | { | |
696 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); | |
697 | ||
1381559b | 698 | ath_reset(sc); |
236de514 FF |
699 | } |
700 | ||
ff37e337 S |
701 | /**********************/ |
702 | /* mac80211 callbacks */ | |
703 | /**********************/ | |
704 | ||
8feceb67 | 705 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 706 | { |
9ac58615 | 707 | struct ath_softc *sc = hw->priv; |
af03abec | 708 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 709 | struct ath_common *common = ath9k_hw_common(ah); |
675a0b04 | 710 | struct ieee80211_channel *curchan = hw->conf.chandef.chan; |
ff37e337 | 711 | struct ath9k_channel *init_channel; |
82880a7c | 712 | int r; |
f078f209 | 713 | |
d2182b69 | 714 | ath_dbg(common, CONFIG, |
226afe68 JP |
715 | "Starting driver with initial channel: %d MHz\n", |
716 | curchan->center_freq); | |
f078f209 | 717 | |
f62d816f | 718 | ath9k_ps_wakeup(sc); |
141b38b6 S |
719 | mutex_lock(&sc->mutex); |
720 | ||
2297f1c7 | 721 | init_channel = ath9k_cmn_get_channel(hw, ah, &hw->conf.chandef); |
ff37e337 S |
722 | |
723 | /* Reset SERDES registers */ | |
84c87dc8 | 724 | ath9k_hw_configpcipowersave(ah, false); |
ff37e337 S |
725 | |
726 | /* | |
727 | * The basic interface to setting the hardware in a good | |
728 | * state is ``reset''. On return the hardware is known to | |
729 | * be powered up and with interrupts disabled. This must | |
730 | * be followed by initialization of the appropriate bits | |
731 | * and then setup of the interrupt mask. | |
732 | */ | |
4bdd1e97 | 733 | spin_lock_bh(&sc->sc_pcu_lock); |
c0c11741 FF |
734 | |
735 | atomic_set(&ah->intr_ref_cnt, -1); | |
736 | ||
20bd2a09 | 737 | r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); |
ae8d2858 | 738 | if (r) { |
3800276a JP |
739 | ath_err(common, |
740 | "Unable to reset hardware; reset status %d (freq %u MHz)\n", | |
741 | r, curchan->center_freq); | |
ceb26a60 | 742 | ah->reset_power_on = false; |
ff37e337 | 743 | } |
ff37e337 | 744 | |
ff37e337 | 745 | /* Setup our intr mask. */ |
b5c80475 FF |
746 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
747 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
748 | ATH9K_INT_GLOBAL; | |
749 | ||
750 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f | 751 | ah->imask |= ATH9K_INT_RXHP | |
a6bb860b | 752 | ATH9K_INT_RXLP; |
b5c80475 FF |
753 | else |
754 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 755 | |
a6bb860b SM |
756 | if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) |
757 | ah->imask |= ATH9K_INT_BB_WATCHDOG; | |
758 | ||
071aa9a8 SM |
759 | /* |
760 | * Enable GTT interrupts only for AR9003/AR9004 chips | |
761 | * for now. | |
762 | */ | |
763 | if (AR_SREV_9300_20_OR_LATER(ah)) | |
764 | ah->imask |= ATH9K_INT_GTT; | |
ff37e337 | 765 | |
af03abec | 766 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 767 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 768 | |
e270e776 | 769 | ath_mci_enable(sc); |
40dc5392 | 770 | |
781b14a3 | 771 | clear_bit(SC_OP_INVALID, &sc->sc_flags); |
5f841b41 | 772 | sc->sc_ah->is_monitoring = false; |
ff37e337 | 773 | |
ceb26a60 FF |
774 | if (!ath_complete_reset(sc, false)) |
775 | ah->reset_power_on = false; | |
ff37e337 | 776 | |
c0c11741 FF |
777 | if (ah->led_pin >= 0) { |
778 | ath9k_hw_cfg_output(ah, ah->led_pin, | |
779 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
780 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); | |
781 | } | |
782 | ||
783 | /* | |
784 | * Reset key cache to sane defaults (all entries cleared) instead of | |
785 | * semi-random values after suspend/resume. | |
786 | */ | |
787 | ath9k_cmn_init_crypto(sc->sc_ah); | |
788 | ||
a35051ce FF |
789 | ath9k_hw_reset_tsf(ah); |
790 | ||
9adcf440 | 791 | spin_unlock_bh(&sc->sc_pcu_lock); |
164ace38 | 792 | |
141b38b6 S |
793 | mutex_unlock(&sc->mutex); |
794 | ||
f62d816f FF |
795 | ath9k_ps_restore(sc); |
796 | ||
ceb26a60 | 797 | return 0; |
f078f209 LR |
798 | } |
799 | ||
36323f81 TH |
800 | static void ath9k_tx(struct ieee80211_hw *hw, |
801 | struct ieee80211_tx_control *control, | |
802 | struct sk_buff *skb) | |
f078f209 | 803 | { |
9ac58615 | 804 | struct ath_softc *sc = hw->priv; |
c46917bb | 805 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 806 | struct ath_tx_control txctl; |
1bc14880 | 807 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
07c15a3f | 808 | unsigned long flags; |
528f0c6b | 809 | |
96148326 | 810 | if (sc->ps_enabled) { |
dc8c4585 JM |
811 | /* |
812 | * mac80211 does not set PM field for normal data frames, so we | |
813 | * need to update that based on the current PS mode. | |
814 | */ | |
815 | if (ieee80211_is_data(hdr->frame_control) && | |
816 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
817 | !ieee80211_has_pm(hdr->frame_control)) { | |
d2182b69 | 818 | ath_dbg(common, PS, |
226afe68 | 819 | "Add PM=1 for a TX frame while in PS mode\n"); |
dc8c4585 JM |
820 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
821 | } | |
822 | } | |
823 | ||
ad128860 | 824 | if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { |
9a23f9ca JM |
825 | /* |
826 | * We are using PS-Poll and mac80211 can request TX while in | |
827 | * power save mode. Need to wake up hardware for the TX to be | |
828 | * completed and if needed, also for RX of buffered frames. | |
829 | */ | |
9a23f9ca | 830 | ath9k_ps_wakeup(sc); |
07c15a3f | 831 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
fdf76622 VT |
832 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
833 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 834 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
d2182b69 | 835 | ath_dbg(common, PS, |
226afe68 | 836 | "Sending PS-Poll to pick a buffered frame\n"); |
1b04b930 | 837 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 838 | } else { |
d2182b69 | 839 | ath_dbg(common, PS, "Wake up to complete TX\n"); |
1b04b930 | 840 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
841 | } |
842 | /* | |
843 | * The actual restore operation will happen only after | |
ad128860 | 844 | * the ps_flags bit is cleared. We are just dropping |
9a23f9ca JM |
845 | * the ps_usecount here. |
846 | */ | |
07c15a3f | 847 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
9a23f9ca JM |
848 | ath9k_ps_restore(sc); |
849 | } | |
850 | ||
ad128860 SM |
851 | /* |
852 | * Cannot tx while the hardware is in full sleep, it first needs a full | |
853 | * chip reset to recover from that | |
854 | */ | |
855 | if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { | |
856 | ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); | |
857 | goto exit; | |
858 | } | |
859 | ||
528f0c6b | 860 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
066dae93 | 861 | txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; |
36323f81 | 862 | txctl.sta = control->sta; |
528f0c6b | 863 | |
d2182b69 | 864 | ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 865 | |
c52f33d0 | 866 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
d2182b69 | 867 | ath_dbg(common, XMIT, "TX failed\n"); |
a5a0bca1 | 868 | TX_STAT_INC(txctl.txq->axq_qnum, txfailed); |
528f0c6b | 869 | goto exit; |
8feceb67 VT |
870 | } |
871 | ||
7bb45683 | 872 | return; |
528f0c6b | 873 | exit: |
249ee722 | 874 | ieee80211_free_txskb(hw, skb); |
f078f209 LR |
875 | } |
876 | ||
8feceb67 | 877 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 878 | { |
9ac58615 | 879 | struct ath_softc *sc = hw->priv; |
af03abec | 880 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 881 | struct ath_common *common = ath9k_hw_common(ah); |
c0c11741 | 882 | bool prev_idle; |
f078f209 | 883 | |
4c483817 S |
884 | mutex_lock(&sc->mutex); |
885 | ||
9adcf440 | 886 | ath_cancel_work(sc); |
c94dbff7 | 887 | |
781b14a3 | 888 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { |
d2182b69 | 889 | ath_dbg(common, ANY, "Device not present\n"); |
4c483817 | 890 | mutex_unlock(&sc->mutex); |
9c84b797 S |
891 | return; |
892 | } | |
8feceb67 | 893 | |
3867cf6a S |
894 | /* Ensure HW is awake when we try to shut it down. */ |
895 | ath9k_ps_wakeup(sc); | |
896 | ||
6a6733f2 LR |
897 | spin_lock_bh(&sc->sc_pcu_lock); |
898 | ||
203043f5 SG |
899 | /* prevent tasklets to enable interrupts once we disable them */ |
900 | ah->imask &= ~ATH9K_INT_GLOBAL; | |
901 | ||
ff37e337 S |
902 | /* make sure h/w will not generate any interrupt |
903 | * before setting the invalid flag. */ | |
4df3071e | 904 | ath9k_hw_disable_interrupts(ah); |
ff37e337 | 905 | |
c0c11741 FF |
906 | spin_unlock_bh(&sc->sc_pcu_lock); |
907 | ||
908 | /* we can now sync irq and kill any running tasklets, since we already | |
909 | * disabled interrupts and not holding a spin lock */ | |
910 | synchronize_irq(sc->irq); | |
911 | tasklet_kill(&sc->intr_tq); | |
912 | tasklet_kill(&sc->bcon_tasklet); | |
913 | ||
914 | prev_idle = sc->ps_idle; | |
915 | sc->ps_idle = true; | |
916 | ||
917 | spin_lock_bh(&sc->sc_pcu_lock); | |
918 | ||
919 | if (ah->led_pin >= 0) { | |
920 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); | |
921 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
922 | } | |
923 | ||
9ebea382 | 924 | ath_prepare_reset(sc); |
ff37e337 | 925 | |
0d95521e FF |
926 | if (sc->rx.frag) { |
927 | dev_kfree_skb_any(sc->rx.frag); | |
928 | sc->rx.frag = NULL; | |
929 | } | |
930 | ||
c0c11741 | 931 | if (!ah->curchan) |
2297f1c7 | 932 | ah->curchan = ath9k_cmn_get_channel(hw, ah, &hw->conf.chandef); |
6a6733f2 | 933 | |
c0c11741 FF |
934 | ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
935 | ath9k_hw_phy_disable(ah); | |
6a6733f2 | 936 | |
c0c11741 | 937 | ath9k_hw_configpcipowersave(ah, true); |
203043f5 | 938 | |
c0c11741 | 939 | spin_unlock_bh(&sc->sc_pcu_lock); |
3867cf6a | 940 | |
c0c11741 | 941 | ath9k_ps_restore(sc); |
ff37e337 | 942 | |
781b14a3 | 943 | set_bit(SC_OP_INVALID, &sc->sc_flags); |
c0c11741 | 944 | sc->ps_idle = prev_idle; |
500c064d | 945 | |
141b38b6 S |
946 | mutex_unlock(&sc->mutex); |
947 | ||
d2182b69 | 948 | ath_dbg(common, CONFIG, "Driver halt\n"); |
f078f209 LR |
949 | } |
950 | ||
c648ecb0 | 951 | static bool ath9k_uses_beacons(int type) |
4801416c BG |
952 | { |
953 | switch (type) { | |
954 | case NL80211_IFTYPE_AP: | |
955 | case NL80211_IFTYPE_ADHOC: | |
956 | case NL80211_IFTYPE_MESH_POINT: | |
957 | return true; | |
958 | default: | |
959 | return false; | |
960 | } | |
961 | } | |
962 | ||
4801416c BG |
963 | static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
964 | { | |
965 | struct ath9k_vif_iter_data *iter_data = data; | |
966 | int i; | |
967 | ||
ab11bb28 | 968 | if (iter_data->has_hw_macaddr) { |
4801416c BG |
969 | for (i = 0; i < ETH_ALEN; i++) |
970 | iter_data->mask[i] &= | |
971 | ~(iter_data->hw_macaddr[i] ^ mac[i]); | |
ab11bb28 FF |
972 | } else { |
973 | memcpy(iter_data->hw_macaddr, mac, ETH_ALEN); | |
974 | iter_data->has_hw_macaddr = true; | |
975 | } | |
141b38b6 | 976 | |
1ed32e4f | 977 | switch (vif->type) { |
4801416c BG |
978 | case NL80211_IFTYPE_AP: |
979 | iter_data->naps++; | |
f078f209 | 980 | break; |
4801416c BG |
981 | case NL80211_IFTYPE_STATION: |
982 | iter_data->nstations++; | |
e51f3eff | 983 | break; |
05c914fe | 984 | case NL80211_IFTYPE_ADHOC: |
4801416c BG |
985 | iter_data->nadhocs++; |
986 | break; | |
9cb5412b | 987 | case NL80211_IFTYPE_MESH_POINT: |
4801416c BG |
988 | iter_data->nmeshes++; |
989 | break; | |
990 | case NL80211_IFTYPE_WDS: | |
991 | iter_data->nwds++; | |
f078f209 LR |
992 | break; |
993 | default: | |
4801416c | 994 | break; |
f078f209 | 995 | } |
4801416c | 996 | } |
f078f209 | 997 | |
6dcc3444 SM |
998 | static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
999 | { | |
1000 | struct ath_softc *sc = data; | |
1001 | struct ath_vif *avp = (void *)vif->drv_priv; | |
1002 | ||
1003 | if (vif->type != NL80211_IFTYPE_STATION) | |
1004 | return; | |
1005 | ||
1006 | if (avp->primary_sta_vif) | |
1007 | ath9k_set_assoc_state(sc, vif); | |
1008 | } | |
1009 | ||
4801416c BG |
1010 | /* Called with sc->mutex held. */ |
1011 | void ath9k_calculate_iter_data(struct ieee80211_hw *hw, | |
1012 | struct ieee80211_vif *vif, | |
1013 | struct ath9k_vif_iter_data *iter_data) | |
1014 | { | |
9ac58615 | 1015 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1016 | struct ath_hw *ah = sc->sc_ah; |
1017 | struct ath_common *common = ath9k_hw_common(ah); | |
8feceb67 | 1018 | |
4801416c | 1019 | /* |
657eb17d MV |
1020 | * Pick the MAC address of the first interface as the new hardware |
1021 | * MAC address. The hardware will use it together with the BSSID mask | |
1022 | * when matching addresses. | |
4801416c BG |
1023 | */ |
1024 | memset(iter_data, 0, sizeof(*iter_data)); | |
4801416c | 1025 | memset(&iter_data->mask, 0xff, ETH_ALEN); |
5640b08e | 1026 | |
4801416c BG |
1027 | if (vif) |
1028 | ath9k_vif_iter(iter_data, vif->addr, vif); | |
1029 | ||
1030 | /* Get list of all active MAC addresses */ | |
8b2c9824 JB |
1031 | ieee80211_iterate_active_interfaces_atomic( |
1032 | sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, | |
1033 | ath9k_vif_iter, iter_data); | |
ab11bb28 FF |
1034 | |
1035 | memcpy(common->macaddr, iter_data->hw_macaddr, ETH_ALEN); | |
4801416c | 1036 | } |
8ca21f01 | 1037 | |
4801416c BG |
1038 | /* Called with sc->mutex held. */ |
1039 | static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, | |
1040 | struct ieee80211_vif *vif) | |
1041 | { | |
9ac58615 | 1042 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1043 | struct ath_hw *ah = sc->sc_ah; |
1044 | struct ath_common *common = ath9k_hw_common(ah); | |
1045 | struct ath9k_vif_iter_data iter_data; | |
6dcc3444 | 1046 | enum nl80211_iftype old_opmode = ah->opmode; |
8ca21f01 | 1047 | |
4801416c | 1048 | ath9k_calculate_iter_data(hw, vif, &iter_data); |
2c3db3d5 | 1049 | |
4801416c BG |
1050 | memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); |
1051 | ath_hw_setbssidmask(common); | |
1052 | ||
4801416c | 1053 | if (iter_data.naps > 0) { |
60ca9f87 | 1054 | ath9k_hw_set_tsfadjust(ah, true); |
4801416c BG |
1055 | ah->opmode = NL80211_IFTYPE_AP; |
1056 | } else { | |
60ca9f87 | 1057 | ath9k_hw_set_tsfadjust(ah, false); |
5640b08e | 1058 | |
fd5999cf JC |
1059 | if (iter_data.nmeshes) |
1060 | ah->opmode = NL80211_IFTYPE_MESH_POINT; | |
1061 | else if (iter_data.nwds) | |
4801416c BG |
1062 | ah->opmode = NL80211_IFTYPE_AP; |
1063 | else if (iter_data.nadhocs) | |
1064 | ah->opmode = NL80211_IFTYPE_ADHOC; | |
1065 | else | |
1066 | ah->opmode = NL80211_IFTYPE_STATION; | |
1067 | } | |
5640b08e | 1068 | |
df35d29e SM |
1069 | ath9k_hw_setopmode(ah); |
1070 | ||
198823fd | 1071 | if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) |
3069168c | 1072 | ah->imask |= ATH9K_INT_TSFOOR; |
198823fd | 1073 | else |
4801416c | 1074 | ah->imask &= ~ATH9K_INT_TSFOOR; |
4af9cf4f | 1075 | |
72d874c6 | 1076 | ath9k_hw_set_interrupts(ah); |
6dcc3444 SM |
1077 | |
1078 | /* | |
1079 | * If we are changing the opmode to STATION, | |
1080 | * a beacon sync needs to be done. | |
1081 | */ | |
1082 | if (ah->opmode == NL80211_IFTYPE_STATION && | |
1083 | old_opmode == NL80211_IFTYPE_AP && | |
1084 | test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { | |
8b2c9824 JB |
1085 | ieee80211_iterate_active_interfaces_atomic( |
1086 | sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, | |
1087 | ath9k_sta_vif_iter, sc); | |
6dcc3444 | 1088 | } |
4801416c | 1089 | } |
6f255425 | 1090 | |
4801416c BG |
1091 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
1092 | struct ieee80211_vif *vif) | |
6b3b991d | 1093 | { |
9ac58615 | 1094 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1095 | struct ath_hw *ah = sc->sc_ah; |
1096 | struct ath_common *common = ath9k_hw_common(ah); | |
f89d1bc4 FF |
1097 | struct ath_vif *avp = (void *)vif->drv_priv; |
1098 | struct ath_node *an = &avp->mcast_node; | |
6b3b991d | 1099 | |
4801416c | 1100 | mutex_lock(&sc->mutex); |
6b3b991d | 1101 | |
89f927af LR |
1102 | if (config_enabled(CONFIG_ATH9K_TX99)) { |
1103 | if (sc->nvifs >= 1) { | |
1104 | mutex_unlock(&sc->mutex); | |
1105 | return -EOPNOTSUPP; | |
1106 | } | |
1107 | sc->tx99_vif = vif; | |
1108 | } | |
1109 | ||
d2182b69 | 1110 | ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); |
4801416c BG |
1111 | sc->nvifs++; |
1112 | ||
327967cb | 1113 | ath9k_ps_wakeup(sc); |
130ef6e9 | 1114 | ath9k_calculate_summary_state(hw, vif); |
327967cb MSS |
1115 | ath9k_ps_restore(sc); |
1116 | ||
130ef6e9 SM |
1117 | if (ath9k_uses_beacons(vif->type)) |
1118 | ath9k_beacon_assign_slot(sc, vif); | |
1119 | ||
f89d1bc4 FF |
1120 | an->sc = sc; |
1121 | an->sta = NULL; | |
1122 | an->vif = vif; | |
1123 | an->no_ps_filter = true; | |
1124 | ath_tx_node_init(sc, an); | |
1125 | ||
4801416c | 1126 | mutex_unlock(&sc->mutex); |
327967cb | 1127 | return 0; |
6b3b991d RM |
1128 | } |
1129 | ||
1130 | static int ath9k_change_interface(struct ieee80211_hw *hw, | |
1131 | struct ieee80211_vif *vif, | |
1132 | enum nl80211_iftype new_type, | |
1133 | bool p2p) | |
1134 | { | |
9ac58615 | 1135 | struct ath_softc *sc = hw->priv; |
6b3b991d RM |
1136 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1137 | ||
6b3b991d | 1138 | mutex_lock(&sc->mutex); |
4801416c | 1139 | |
89f927af LR |
1140 | if (config_enabled(CONFIG_ATH9K_TX99)) { |
1141 | mutex_unlock(&sc->mutex); | |
1142 | return -EOPNOTSUPP; | |
1143 | } | |
1144 | ||
1145 | ath_dbg(common, CONFIG, "Change Interface\n"); | |
1146 | ||
4801416c | 1147 | if (ath9k_uses_beacons(vif->type)) |
130ef6e9 | 1148 | ath9k_beacon_remove_slot(sc, vif); |
4801416c | 1149 | |
6b3b991d RM |
1150 | vif->type = new_type; |
1151 | vif->p2p = p2p; | |
1152 | ||
327967cb | 1153 | ath9k_ps_wakeup(sc); |
130ef6e9 | 1154 | ath9k_calculate_summary_state(hw, vif); |
327967cb MSS |
1155 | ath9k_ps_restore(sc); |
1156 | ||
130ef6e9 SM |
1157 | if (ath9k_uses_beacons(vif->type)) |
1158 | ath9k_beacon_assign_slot(sc, vif); | |
1159 | ||
6b3b991d | 1160 | mutex_unlock(&sc->mutex); |
327967cb | 1161 | return 0; |
6b3b991d RM |
1162 | } |
1163 | ||
8feceb67 | 1164 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1165 | struct ieee80211_vif *vif) |
f078f209 | 1166 | { |
9ac58615 | 1167 | struct ath_softc *sc = hw->priv; |
c46917bb | 1168 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
f89d1bc4 | 1169 | struct ath_vif *avp = (void *)vif->drv_priv; |
f078f209 | 1170 | |
d2182b69 | 1171 | ath_dbg(common, CONFIG, "Detach Interface\n"); |
f078f209 | 1172 | |
141b38b6 S |
1173 | mutex_lock(&sc->mutex); |
1174 | ||
4801416c | 1175 | sc->nvifs--; |
89f927af | 1176 | sc->tx99_vif = NULL; |
580f0b8a | 1177 | |
4801416c | 1178 | if (ath9k_uses_beacons(vif->type)) |
130ef6e9 | 1179 | ath9k_beacon_remove_slot(sc, vif); |
2c3db3d5 | 1180 | |
d074e8d5 SW |
1181 | if (sc->csa_vif == vif) |
1182 | sc->csa_vif = NULL; | |
1183 | ||
327967cb | 1184 | ath9k_ps_wakeup(sc); |
4801416c | 1185 | ath9k_calculate_summary_state(hw, NULL); |
327967cb | 1186 | ath9k_ps_restore(sc); |
141b38b6 | 1187 | |
f89d1bc4 FF |
1188 | ath_tx_node_cleanup(sc, &avp->mcast_node); |
1189 | ||
141b38b6 | 1190 | mutex_unlock(&sc->mutex); |
f078f209 LR |
1191 | } |
1192 | ||
fbab7390 | 1193 | static void ath9k_enable_ps(struct ath_softc *sc) |
3f7c5c10 | 1194 | { |
3069168c | 1195 | struct ath_hw *ah = sc->sc_ah; |
ad128860 | 1196 | struct ath_common *common = ath9k_hw_common(ah); |
3069168c | 1197 | |
89f927af LR |
1198 | if (config_enabled(CONFIG_ATH9K_TX99)) |
1199 | return; | |
1200 | ||
3f7c5c10 | 1201 | sc->ps_enabled = true; |
3069168c PR |
1202 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1203 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1204 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
72d874c6 | 1205 | ath9k_hw_set_interrupts(ah); |
3f7c5c10 | 1206 | } |
fdf76622 | 1207 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1208 | } |
ad128860 | 1209 | ath_dbg(common, PS, "PowerSave enabled\n"); |
3f7c5c10 SB |
1210 | } |
1211 | ||
845d708e SB |
1212 | static void ath9k_disable_ps(struct ath_softc *sc) |
1213 | { | |
1214 | struct ath_hw *ah = sc->sc_ah; | |
ad128860 | 1215 | struct ath_common *common = ath9k_hw_common(ah); |
845d708e | 1216 | |
89f927af LR |
1217 | if (config_enabled(CONFIG_ATH9K_TX99)) |
1218 | return; | |
1219 | ||
845d708e SB |
1220 | sc->ps_enabled = false; |
1221 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
1222 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | |
1223 | ath9k_hw_setrxabort(ah, 0); | |
1224 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | | |
1225 | PS_WAIT_FOR_CAB | | |
1226 | PS_WAIT_FOR_PSPOLL_DATA | | |
1227 | PS_WAIT_FOR_TX_ACK); | |
1228 | if (ah->imask & ATH9K_INT_TIM_TIMER) { | |
1229 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
72d874c6 | 1230 | ath9k_hw_set_interrupts(ah); |
845d708e SB |
1231 | } |
1232 | } | |
ad128860 | 1233 | ath_dbg(common, PS, "PowerSave disabled\n"); |
845d708e SB |
1234 | } |
1235 | ||
e93d083f SW |
1236 | void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw) |
1237 | { | |
1238 | struct ath_softc *sc = hw->priv; | |
1239 | struct ath_hw *ah = sc->sc_ah; | |
1240 | struct ath_common *common = ath9k_hw_common(ah); | |
1241 | u32 rxfilter; | |
1242 | ||
89f927af LR |
1243 | if (config_enabled(CONFIG_ATH9K_TX99)) |
1244 | return; | |
1245 | ||
e93d083f SW |
1246 | if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { |
1247 | ath_err(common, "spectrum analyzer not implemented on this hardware\n"); | |
1248 | return; | |
1249 | } | |
1250 | ||
1251 | ath9k_ps_wakeup(sc); | |
1252 | rxfilter = ath9k_hw_getrxfilter(ah); | |
1253 | ath9k_hw_setrxfilter(ah, rxfilter | | |
1254 | ATH9K_RX_FILTER_PHYRADAR | | |
1255 | ATH9K_RX_FILTER_PHYERR); | |
1256 | ||
1257 | /* TODO: usually this should not be neccesary, but for some reason | |
1258 | * (or in some mode?) the trigger must be called after the | |
1259 | * configuration, otherwise the register will have its values reset | |
1260 | * (on my ar9220 to value 0x01002310) | |
1261 | */ | |
1262 | ath9k_spectral_scan_config(hw, sc->spectral_mode); | |
1263 | ath9k_hw_ops(ah)->spectral_scan_trigger(ah); | |
1264 | ath9k_ps_restore(sc); | |
1265 | } | |
1266 | ||
1267 | int ath9k_spectral_scan_config(struct ieee80211_hw *hw, | |
1268 | enum spectral_mode spectral_mode) | |
1269 | { | |
1270 | struct ath_softc *sc = hw->priv; | |
1271 | struct ath_hw *ah = sc->sc_ah; | |
1272 | struct ath_common *common = ath9k_hw_common(ah); | |
e93d083f SW |
1273 | |
1274 | if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { | |
1275 | ath_err(common, "spectrum analyzer not implemented on this hardware\n"); | |
1276 | return -1; | |
1277 | } | |
1278 | ||
e93d083f SW |
1279 | switch (spectral_mode) { |
1280 | case SPECTRAL_DISABLED: | |
04ccd4a1 | 1281 | sc->spec_config.enabled = 0; |
e93d083f SW |
1282 | break; |
1283 | case SPECTRAL_BACKGROUND: | |
1284 | /* send endless samples. | |
1285 | * TODO: is this really useful for "background"? | |
1286 | */ | |
04ccd4a1 SW |
1287 | sc->spec_config.endless = 1; |
1288 | sc->spec_config.enabled = 1; | |
e93d083f SW |
1289 | break; |
1290 | case SPECTRAL_CHANSCAN: | |
e93d083f | 1291 | case SPECTRAL_MANUAL: |
04ccd4a1 SW |
1292 | sc->spec_config.endless = 0; |
1293 | sc->spec_config.enabled = 1; | |
e93d083f SW |
1294 | break; |
1295 | default: | |
1296 | return -1; | |
1297 | } | |
1298 | ||
1299 | ath9k_ps_wakeup(sc); | |
04ccd4a1 | 1300 | ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config); |
e93d083f SW |
1301 | ath9k_ps_restore(sc); |
1302 | ||
1303 | sc->spectral_mode = spectral_mode; | |
1304 | ||
1305 | return 0; | |
1306 | } | |
1307 | ||
e8975581 | 1308 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1309 | { |
9ac58615 | 1310 | struct ath_softc *sc = hw->priv; |
3430098a FF |
1311 | struct ath_hw *ah = sc->sc_ah; |
1312 | struct ath_common *common = ath9k_hw_common(ah); | |
e8975581 | 1313 | struct ieee80211_conf *conf = &hw->conf; |
75600abf | 1314 | bool reset_channel = false; |
f078f209 | 1315 | |
c0c11741 | 1316 | ath9k_ps_wakeup(sc); |
aa33de09 | 1317 | mutex_lock(&sc->mutex); |
141b38b6 | 1318 | |
daa1b6ee | 1319 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
7545daf4 | 1320 | sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); |
b73f3e78 | 1321 | if (sc->ps_idle) { |
daa1b6ee | 1322 | ath_cancel_work(sc); |
b73f3e78 RM |
1323 | ath9k_stop_btcoex(sc); |
1324 | } else { | |
1325 | ath9k_start_btcoex(sc); | |
75600abf FF |
1326 | /* |
1327 | * The chip needs a reset to properly wake up from | |
1328 | * full sleep | |
1329 | */ | |
1330 | reset_channel = ah->chip_fullsleep; | |
b73f3e78 | 1331 | } |
daa1b6ee | 1332 | } |
64839170 | 1333 | |
e7824a50 LR |
1334 | /* |
1335 | * We just prepare to enable PS. We have to wait until our AP has | |
1336 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1337 | * those ACKs and end up retransmitting the same null data frames. | |
1338 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1339 | */ | |
3cbb5dd7 | 1340 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
8ab2cd09 LR |
1341 | unsigned long flags; |
1342 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
fbab7390 SB |
1343 | if (conf->flags & IEEE80211_CONF_PS) |
1344 | ath9k_enable_ps(sc); | |
845d708e SB |
1345 | else |
1346 | ath9k_disable_ps(sc); | |
8ab2cd09 | 1347 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
3cbb5dd7 VN |
1348 | } |
1349 | ||
199afd9d S |
1350 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1351 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
d2182b69 | 1352 | ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); |
5f841b41 RM |
1353 | sc->sc_ah->is_monitoring = true; |
1354 | } else { | |
d2182b69 | 1355 | ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); |
5f841b41 | 1356 | sc->sc_ah->is_monitoring = false; |
199afd9d S |
1357 | } |
1358 | } | |
1359 | ||
75600abf | 1360 | if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) { |
45c67f6f | 1361 | if (ath_set_channel(sc, &hw->conf.chandef) < 0) { |
3800276a | 1362 | ath_err(common, "Unable to set channel\n"); |
aa33de09 | 1363 | mutex_unlock(&sc->mutex); |
8389fb3f | 1364 | ath9k_ps_restore(sc); |
e11602b7 S |
1365 | return -EINVAL; |
1366 | } | |
094d05dc | 1367 | } |
f078f209 | 1368 | |
c9f6a656 | 1369 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
d2182b69 | 1370 | ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); |
17d7904d | 1371 | sc->config.txpowlimit = 2 * conf->power_level; |
5048e8c3 RM |
1372 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
1373 | sc->config.txpowlimit, &sc->curtxpow); | |
64839170 LR |
1374 | } |
1375 | ||
aa33de09 | 1376 | mutex_unlock(&sc->mutex); |
c0c11741 | 1377 | ath9k_ps_restore(sc); |
141b38b6 | 1378 | |
f078f209 LR |
1379 | return 0; |
1380 | } | |
1381 | ||
8feceb67 VT |
1382 | #define SUPPORTED_FILTERS \ |
1383 | (FIF_PROMISC_IN_BSS | \ | |
1384 | FIF_ALLMULTI | \ | |
1385 | FIF_CONTROL | \ | |
af6a3fc7 | 1386 | FIF_PSPOLL | \ |
8feceb67 VT |
1387 | FIF_OTHER_BSS | \ |
1388 | FIF_BCN_PRBRESP_PROMISC | \ | |
9c1d8e4a | 1389 | FIF_PROBE_REQ | \ |
8feceb67 | 1390 | FIF_FCSFAIL) |
c83be688 | 1391 | |
8feceb67 VT |
1392 | /* FIXME: sc->sc_full_reset ? */ |
1393 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1394 | unsigned int changed_flags, | |
1395 | unsigned int *total_flags, | |
3ac64bee | 1396 | u64 multicast) |
8feceb67 | 1397 | { |
9ac58615 | 1398 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1399 | u32 rfilt; |
f078f209 | 1400 | |
8feceb67 VT |
1401 | changed_flags &= SUPPORTED_FILTERS; |
1402 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1403 | |
b77f483f | 1404 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1405 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1406 | rfilt = ath_calcrxfilter(sc); |
1407 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1408 | ath9k_ps_restore(sc); |
f078f209 | 1409 | |
d2182b69 JP |
1410 | ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", |
1411 | rfilt); | |
8feceb67 | 1412 | } |
f078f209 | 1413 | |
4ca77860 JB |
1414 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1415 | struct ieee80211_vif *vif, | |
1416 | struct ieee80211_sta *sta) | |
8feceb67 | 1417 | { |
9ac58615 | 1418 | struct ath_softc *sc = hw->priv; |
93ae2dd2 FF |
1419 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1420 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1421 | struct ieee80211_key_conf ps_key = { }; | |
4ef69d03 | 1422 | int key; |
f078f209 | 1423 | |
7e1e3864 | 1424 | ath_node_attach(sc, sta, vif); |
f59a59fe FF |
1425 | |
1426 | if (vif->type != NL80211_IFTYPE_AP && | |
1427 | vif->type != NL80211_IFTYPE_AP_VLAN) | |
1428 | return 0; | |
1429 | ||
4ef69d03 FF |
1430 | key = ath_key_config(common, vif, sta, &ps_key); |
1431 | if (key > 0) | |
1432 | an->ps_key = key; | |
4ca77860 JB |
1433 | |
1434 | return 0; | |
1435 | } | |
1436 | ||
93ae2dd2 FF |
1437 | static void ath9k_del_ps_key(struct ath_softc *sc, |
1438 | struct ieee80211_vif *vif, | |
1439 | struct ieee80211_sta *sta) | |
1440 | { | |
1441 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1442 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1443 | struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; | |
1444 | ||
1445 | if (!an->ps_key) | |
1446 | return; | |
1447 | ||
1448 | ath_key_delete(common, &ps_key); | |
4ef69d03 | 1449 | an->ps_key = 0; |
93ae2dd2 FF |
1450 | } |
1451 | ||
4ca77860 JB |
1452 | static int ath9k_sta_remove(struct ieee80211_hw *hw, |
1453 | struct ieee80211_vif *vif, | |
1454 | struct ieee80211_sta *sta) | |
1455 | { | |
9ac58615 | 1456 | struct ath_softc *sc = hw->priv; |
4ca77860 | 1457 | |
93ae2dd2 | 1458 | ath9k_del_ps_key(sc, vif, sta); |
4ca77860 JB |
1459 | ath_node_detach(sc, sta); |
1460 | ||
1461 | return 0; | |
f078f209 LR |
1462 | } |
1463 | ||
5519541d FF |
1464 | static void ath9k_sta_notify(struct ieee80211_hw *hw, |
1465 | struct ieee80211_vif *vif, | |
1466 | enum sta_notify_cmd cmd, | |
1467 | struct ieee80211_sta *sta) | |
1468 | { | |
1469 | struct ath_softc *sc = hw->priv; | |
1470 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1471 | ||
1472 | switch (cmd) { | |
1473 | case STA_NOTIFY_SLEEP: | |
1474 | an->sleeping = true; | |
042ec453 | 1475 | ath_tx_aggr_sleep(sta, sc, an); |
5519541d FF |
1476 | break; |
1477 | case STA_NOTIFY_AWAKE: | |
1478 | an->sleeping = false; | |
1479 | ath_tx_aggr_wakeup(sc, an); | |
1480 | break; | |
1481 | } | |
1482 | } | |
1483 | ||
8a3a3c85 EP |
1484 | static int ath9k_conf_tx(struct ieee80211_hw *hw, |
1485 | struct ieee80211_vif *vif, u16 queue, | |
8feceb67 | 1486 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1487 | { |
9ac58615 | 1488 | struct ath_softc *sc = hw->priv; |
c46917bb | 1489 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
066dae93 | 1490 | struct ath_txq *txq; |
8feceb67 | 1491 | struct ath9k_tx_queue_info qi; |
066dae93 | 1492 | int ret = 0; |
f078f209 | 1493 | |
bea843c7 | 1494 | if (queue >= IEEE80211_NUM_ACS) |
8feceb67 | 1495 | return 0; |
f078f209 | 1496 | |
066dae93 FF |
1497 | txq = sc->tx.txq_map[queue]; |
1498 | ||
96f372c9 | 1499 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1500 | mutex_lock(&sc->mutex); |
1501 | ||
1ffb0610 S |
1502 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1503 | ||
8feceb67 VT |
1504 | qi.tqi_aifs = params->aifs; |
1505 | qi.tqi_cwmin = params->cw_min; | |
1506 | qi.tqi_cwmax = params->cw_max; | |
531bd079 | 1507 | qi.tqi_burstTime = params->txop * 32; |
f078f209 | 1508 | |
d2182b69 | 1509 | ath_dbg(common, CONFIG, |
226afe68 JP |
1510 | "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", |
1511 | queue, txq->axq_qnum, params->aifs, params->cw_min, | |
1512 | params->cw_max, params->txop); | |
f078f209 | 1513 | |
aa5955c3 | 1514 | ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); |
066dae93 | 1515 | ret = ath_txq_update(sc, txq->axq_qnum, &qi); |
8feceb67 | 1516 | if (ret) |
3800276a | 1517 | ath_err(common, "TXQ Update failed\n"); |
f078f209 | 1518 | |
141b38b6 | 1519 | mutex_unlock(&sc->mutex); |
96f372c9 | 1520 | ath9k_ps_restore(sc); |
141b38b6 | 1521 | |
8feceb67 VT |
1522 | return ret; |
1523 | } | |
f078f209 | 1524 | |
8feceb67 VT |
1525 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1526 | enum set_key_cmd cmd, | |
dc822b5d JB |
1527 | struct ieee80211_vif *vif, |
1528 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1529 | struct ieee80211_key_conf *key) |
1530 | { | |
9ac58615 | 1531 | struct ath_softc *sc = hw->priv; |
c46917bb | 1532 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1533 | int ret = 0; |
f078f209 | 1534 | |
3e6109c5 | 1535 | if (ath9k_modparam_nohwcrypt) |
b3bd89ce JM |
1536 | return -ENOSPC; |
1537 | ||
5bd5e9a6 CYY |
1538 | if ((vif->type == NL80211_IFTYPE_ADHOC || |
1539 | vif->type == NL80211_IFTYPE_MESH_POINT) && | |
cfdc9a8b JM |
1540 | (key->cipher == WLAN_CIPHER_SUITE_TKIP || |
1541 | key->cipher == WLAN_CIPHER_SUITE_CCMP) && | |
1542 | !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { | |
1543 | /* | |
1544 | * For now, disable hw crypto for the RSN IBSS group keys. This | |
1545 | * could be optimized in the future to use a modified key cache | |
1546 | * design to support per-STA RX GTK, but until that gets | |
1547 | * implemented, use of software crypto for group addressed | |
1548 | * frames is a acceptable to allow RSN IBSS to be used. | |
1549 | */ | |
1550 | return -EOPNOTSUPP; | |
1551 | } | |
1552 | ||
141b38b6 | 1553 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1554 | ath9k_ps_wakeup(sc); |
d2182b69 | 1555 | ath_dbg(common, CONFIG, "Set HW Key\n"); |
f078f209 | 1556 | |
8feceb67 VT |
1557 | switch (cmd) { |
1558 | case SET_KEY: | |
93ae2dd2 FF |
1559 | if (sta) |
1560 | ath9k_del_ps_key(sc, vif, sta); | |
1561 | ||
040e539e | 1562 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1563 | if (ret >= 0) { |
1564 | key->hw_key_idx = ret; | |
8feceb67 VT |
1565 | /* push IV and Michael MIC generation to stack */ |
1566 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
97359d12 | 1567 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) |
8feceb67 | 1568 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
97359d12 JB |
1569 | if (sc->sc_ah->sw_mgmt_crypto && |
1570 | key->cipher == WLAN_CIPHER_SUITE_CCMP) | |
e548c49e | 1571 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; |
6ace2891 | 1572 | ret = 0; |
8feceb67 VT |
1573 | } |
1574 | break; | |
1575 | case DISABLE_KEY: | |
040e539e | 1576 | ath_key_delete(common, key); |
8feceb67 VT |
1577 | break; |
1578 | default: | |
1579 | ret = -EINVAL; | |
1580 | } | |
f078f209 | 1581 | |
3cbb5dd7 | 1582 | ath9k_ps_restore(sc); |
141b38b6 S |
1583 | mutex_unlock(&sc->mutex); |
1584 | ||
8feceb67 VT |
1585 | return ret; |
1586 | } | |
6c43c090 SM |
1587 | |
1588 | static void ath9k_set_assoc_state(struct ath_softc *sc, | |
1589 | struct ieee80211_vif *vif) | |
4f5ef75b | 1590 | { |
4f5ef75b | 1591 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4f5ef75b | 1592 | struct ath_vif *avp = (void *)vif->drv_priv; |
6c43c090 | 1593 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; |
07c15a3f | 1594 | unsigned long flags; |
6c43c090 SM |
1595 | |
1596 | set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); | |
1597 | avp->primary_sta_vif = true; | |
1598 | ||
2e5ef459 | 1599 | /* |
6c43c090 SM |
1600 | * Set the AID, BSSID and do beacon-sync only when |
1601 | * the HW opmode is STATION. | |
1602 | * | |
1603 | * But the primary bit is set above in any case. | |
2e5ef459 | 1604 | */ |
6c43c090 | 1605 | if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) |
2e5ef459 RM |
1606 | return; |
1607 | ||
6c43c090 SM |
1608 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); |
1609 | common->curaid = bss_conf->aid; | |
1610 | ath9k_hw_write_associd(sc->sc_ah); | |
07c15a3f | 1611 | |
6c43c090 SM |
1612 | sc->last_rssi = ATH_RSSI_DUMMY_MARKER; |
1613 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; | |
99e4d43a | 1614 | |
6c43c090 SM |
1615 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
1616 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
1617 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
05c0be2f | 1618 | |
50072ebc RM |
1619 | if (ath9k_hw_mci_is_enabled(sc->sc_ah)) |
1620 | ath9k_mci_update_wlan_channels(sc, false); | |
1621 | ||
6c43c090 SM |
1622 | ath_dbg(common, CONFIG, |
1623 | "Primary Station interface: %pM, BSSID: %pM\n", | |
1624 | vif->addr, common->curbssid); | |
4f5ef75b RM |
1625 | } |
1626 | ||
6c43c090 | 1627 | static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
4f5ef75b | 1628 | { |
6c43c090 | 1629 | struct ath_softc *sc = data; |
4f5ef75b | 1630 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; |
4f5ef75b | 1631 | |
6c43c090 | 1632 | if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) |
2e5ef459 RM |
1633 | return; |
1634 | ||
6c43c090 SM |
1635 | if (bss_conf->assoc) |
1636 | ath9k_set_assoc_state(sc, vif); | |
4f5ef75b | 1637 | } |
f078f209 | 1638 | |
8feceb67 VT |
1639 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1640 | struct ieee80211_vif *vif, | |
1641 | struct ieee80211_bss_conf *bss_conf, | |
1642 | u32 changed) | |
1643 | { | |
da0d45f7 SM |
1644 | #define CHECK_ANI \ |
1645 | (BSS_CHANGED_ASSOC | \ | |
1646 | BSS_CHANGED_IBSS | \ | |
1647 | BSS_CHANGED_BEACON_ENABLED) | |
1648 | ||
9ac58615 | 1649 | struct ath_softc *sc = hw->priv; |
2d0ddec5 | 1650 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1651 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1652 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1653 | int slottime; |
f078f209 | 1654 | |
96f372c9 | 1655 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1656 | mutex_lock(&sc->mutex); |
1657 | ||
9f61903c | 1658 | if (changed & BSS_CHANGED_ASSOC) { |
6c43c090 SM |
1659 | ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", |
1660 | bss_conf->bssid, bss_conf->assoc); | |
1661 | ||
1662 | if (avp->primary_sta_vif && !bss_conf->assoc) { | |
1663 | clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); | |
1664 | avp->primary_sta_vif = false; | |
1665 | ||
1666 | if (ah->opmode == NL80211_IFTYPE_STATION) | |
1667 | clear_bit(SC_OP_BEACONS, &sc->sc_flags); | |
1668 | } | |
1669 | ||
8b2c9824 JB |
1670 | ieee80211_iterate_active_interfaces_atomic( |
1671 | sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, | |
1672 | ath9k_bss_assoc_iter, sc); | |
2d0ddec5 | 1673 | |
6c43c090 SM |
1674 | if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) && |
1675 | ah->opmode == NL80211_IFTYPE_STATION) { | |
1676 | memset(common->curbssid, 0, ETH_ALEN); | |
1677 | common->curaid = 0; | |
1678 | ath9k_hw_write_associd(sc->sc_ah); | |
50072ebc RM |
1679 | if (ath9k_hw_mci_is_enabled(sc->sc_ah)) |
1680 | ath9k_mci_update_wlan_channels(sc, true); | |
6c43c090 | 1681 | } |
c6089ccc | 1682 | } |
2d0ddec5 | 1683 | |
2e5ef459 | 1684 | if (changed & BSS_CHANGED_IBSS) { |
2e5ef459 RM |
1685 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); |
1686 | common->curaid = bss_conf->aid; | |
1687 | ath9k_hw_write_associd(sc->sc_ah); | |
2e5ef459 RM |
1688 | } |
1689 | ||
ef4ad633 | 1690 | if ((changed & BSS_CHANGED_BEACON_ENABLED) || |
c32e4e51 FF |
1691 | (changed & BSS_CHANGED_BEACON_INT)) |
1692 | ath9k_beacon_config(sc, vif, changed); | |
0005baf4 FF |
1693 | |
1694 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
1695 | if (bss_conf->use_short_slot) | |
1696 | slottime = 9; | |
1697 | else | |
1698 | slottime = 20; | |
1699 | if (vif->type == NL80211_IFTYPE_AP) { | |
1700 | /* | |
1701 | * Defer update, so that connected stations can adjust | |
1702 | * their settings at the same time. | |
1703 | * See beacon.c for more details | |
1704 | */ | |
1705 | sc->beacon.slottime = slottime; | |
1706 | sc->beacon.updateslot = UPDATE; | |
1707 | } else { | |
1708 | ah->slottime = slottime; | |
1709 | ath9k_hw_init_global_settings(ah); | |
1710 | } | |
2d0ddec5 JB |
1711 | } |
1712 | ||
da0d45f7 SM |
1713 | if (changed & CHECK_ANI) |
1714 | ath_check_ani(sc); | |
1715 | ||
141b38b6 | 1716 | mutex_unlock(&sc->mutex); |
96f372c9 | 1717 | ath9k_ps_restore(sc); |
da0d45f7 SM |
1718 | |
1719 | #undef CHECK_ANI | |
8feceb67 | 1720 | } |
f078f209 | 1721 | |
37a41b4a | 1722 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 1723 | { |
9ac58615 | 1724 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1725 | u64 tsf; |
f078f209 | 1726 | |
141b38b6 | 1727 | mutex_lock(&sc->mutex); |
9abbfb27 | 1728 | ath9k_ps_wakeup(sc); |
141b38b6 | 1729 | tsf = ath9k_hw_gettsf64(sc->sc_ah); |
9abbfb27 | 1730 | ath9k_ps_restore(sc); |
141b38b6 | 1731 | mutex_unlock(&sc->mutex); |
f078f209 | 1732 | |
8feceb67 VT |
1733 | return tsf; |
1734 | } | |
f078f209 | 1735 | |
37a41b4a EP |
1736 | static void ath9k_set_tsf(struct ieee80211_hw *hw, |
1737 | struct ieee80211_vif *vif, | |
1738 | u64 tsf) | |
3b5d665b | 1739 | { |
9ac58615 | 1740 | struct ath_softc *sc = hw->priv; |
3b5d665b | 1741 | |
141b38b6 | 1742 | mutex_lock(&sc->mutex); |
9abbfb27 | 1743 | ath9k_ps_wakeup(sc); |
141b38b6 | 1744 | ath9k_hw_settsf64(sc->sc_ah, tsf); |
9abbfb27 | 1745 | ath9k_ps_restore(sc); |
141b38b6 | 1746 | mutex_unlock(&sc->mutex); |
3b5d665b AF |
1747 | } |
1748 | ||
37a41b4a | 1749 | static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 1750 | { |
9ac58615 | 1751 | struct ath_softc *sc = hw->priv; |
c83be688 | 1752 | |
141b38b6 | 1753 | mutex_lock(&sc->mutex); |
21526d57 LR |
1754 | |
1755 | ath9k_ps_wakeup(sc); | |
141b38b6 | 1756 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
1757 | ath9k_ps_restore(sc); |
1758 | ||
141b38b6 | 1759 | mutex_unlock(&sc->mutex); |
8feceb67 | 1760 | } |
f078f209 | 1761 | |
8feceb67 | 1762 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 1763 | struct ieee80211_vif *vif, |
141b38b6 S |
1764 | enum ieee80211_ampdu_mlme_action action, |
1765 | struct ieee80211_sta *sta, | |
0b01f030 | 1766 | u16 tid, u16 *ssn, u8 buf_size) |
8feceb67 | 1767 | { |
9ac58615 | 1768 | struct ath_softc *sc = hw->priv; |
16e23428 | 1769 | bool flush = false; |
8feceb67 | 1770 | int ret = 0; |
f078f209 | 1771 | |
7ca7c776 | 1772 | mutex_lock(&sc->mutex); |
85ad181e | 1773 | |
8feceb67 VT |
1774 | switch (action) { |
1775 | case IEEE80211_AMPDU_RX_START: | |
8feceb67 VT |
1776 | break; |
1777 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
1778 | break; |
1779 | case IEEE80211_AMPDU_TX_START: | |
8b685ba9 | 1780 | ath9k_ps_wakeup(sc); |
231c3a1f FF |
1781 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
1782 | if (!ret) | |
1783 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
8b685ba9 | 1784 | ath9k_ps_restore(sc); |
8feceb67 | 1785 | break; |
18b559d5 JB |
1786 | case IEEE80211_AMPDU_TX_STOP_FLUSH: |
1787 | case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: | |
16e23428 FF |
1788 | flush = true; |
1789 | case IEEE80211_AMPDU_TX_STOP_CONT: | |
8b685ba9 | 1790 | ath9k_ps_wakeup(sc); |
f83da965 | 1791 | ath_tx_aggr_stop(sc, sta, tid); |
08c96abd | 1792 | if (!flush) |
16e23428 | 1793 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1794 | ath9k_ps_restore(sc); |
8feceb67 | 1795 | break; |
b1720231 | 1796 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 1797 | ath9k_ps_wakeup(sc); |
8469cdef | 1798 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 1799 | ath9k_ps_restore(sc); |
8469cdef | 1800 | break; |
8feceb67 | 1801 | default: |
3800276a | 1802 | ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); |
8feceb67 VT |
1803 | } |
1804 | ||
7ca7c776 | 1805 | mutex_unlock(&sc->mutex); |
85ad181e | 1806 | |
8feceb67 | 1807 | return ret; |
f078f209 LR |
1808 | } |
1809 | ||
62dad5b0 BP |
1810 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
1811 | struct survey_info *survey) | |
1812 | { | |
9ac58615 | 1813 | struct ath_softc *sc = hw->priv; |
3430098a | 1814 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39162dbe | 1815 | struct ieee80211_supported_band *sband; |
3430098a | 1816 | struct ieee80211_channel *chan; |
3430098a FF |
1817 | int pos; |
1818 | ||
89f927af LR |
1819 | if (config_enabled(CONFIG_ATH9K_TX99)) |
1820 | return -EOPNOTSUPP; | |
1821 | ||
b7cc9b97 | 1822 | spin_lock_bh(&common->cc_lock); |
3430098a FF |
1823 | if (idx == 0) |
1824 | ath_update_survey_stats(sc); | |
39162dbe FF |
1825 | |
1826 | sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; | |
1827 | if (sband && idx >= sband->n_channels) { | |
1828 | idx -= sband->n_channels; | |
1829 | sband = NULL; | |
1830 | } | |
62dad5b0 | 1831 | |
39162dbe FF |
1832 | if (!sband) |
1833 | sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; | |
62dad5b0 | 1834 | |
3430098a | 1835 | if (!sband || idx >= sband->n_channels) { |
b7cc9b97 | 1836 | spin_unlock_bh(&common->cc_lock); |
3430098a | 1837 | return -ENOENT; |
4f1a5a4b | 1838 | } |
62dad5b0 | 1839 | |
3430098a FF |
1840 | chan = &sband->channels[idx]; |
1841 | pos = chan->hw_value; | |
1842 | memcpy(survey, &sc->survey[pos], sizeof(*survey)); | |
1843 | survey->channel = chan; | |
b7cc9b97 | 1844 | spin_unlock_bh(&common->cc_lock); |
3430098a | 1845 | |
62dad5b0 BP |
1846 | return 0; |
1847 | } | |
1848 | ||
e239d859 FF |
1849 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
1850 | { | |
9ac58615 | 1851 | struct ath_softc *sc = hw->priv; |
e239d859 FF |
1852 | struct ath_hw *ah = sc->sc_ah; |
1853 | ||
89f927af LR |
1854 | if (config_enabled(CONFIG_ATH9K_TX99)) |
1855 | return; | |
1856 | ||
e239d859 FF |
1857 | mutex_lock(&sc->mutex); |
1858 | ah->coverage_class = coverage_class; | |
8b2a3827 MSS |
1859 | |
1860 | ath9k_ps_wakeup(sc); | |
e239d859 | 1861 | ath9k_hw_init_global_settings(ah); |
8b2a3827 MSS |
1862 | ath9k_ps_restore(sc); |
1863 | ||
e239d859 FF |
1864 | mutex_unlock(&sc->mutex); |
1865 | } | |
1866 | ||
10e23181 FF |
1867 | static bool ath9k_has_tx_pending(struct ath_softc *sc) |
1868 | { | |
1869 | int i, npend; | |
1870 | ||
1871 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1872 | if (!ATH_TXQ_SETUP(sc, i)) | |
1873 | continue; | |
1874 | ||
1875 | if (!sc->tx.txq[i].axq_depth) | |
1876 | continue; | |
1877 | ||
1878 | npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); | |
1879 | if (npend) | |
1880 | break; | |
1881 | } | |
1882 | ||
1883 | return !!npend; | |
1884 | } | |
1885 | ||
39ecc01d | 1886 | static void ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop) |
69081624 | 1887 | { |
69081624 | 1888 | struct ath_softc *sc = hw->priv; |
99aa55b6 MSS |
1889 | struct ath_hw *ah = sc->sc_ah; |
1890 | struct ath_common *common = ath9k_hw_common(ah); | |
10e23181 | 1891 | int timeout = HZ / 5; /* 200 ms */ |
2f6fc351 | 1892 | bool drain_txq; |
69081624 VT |
1893 | |
1894 | mutex_lock(&sc->mutex); | |
69081624 VT |
1895 | cancel_delayed_work_sync(&sc->tx_complete_work); |
1896 | ||
6a6b3f3e | 1897 | if (ah->ah_flags & AH_UNPLUGGED) { |
d2182b69 | 1898 | ath_dbg(common, ANY, "Device has been unplugged!\n"); |
6a6b3f3e MSS |
1899 | mutex_unlock(&sc->mutex); |
1900 | return; | |
1901 | } | |
1902 | ||
781b14a3 | 1903 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { |
d2182b69 | 1904 | ath_dbg(common, ANY, "Device not present\n"); |
99aa55b6 MSS |
1905 | mutex_unlock(&sc->mutex); |
1906 | return; | |
1907 | } | |
1908 | ||
10e23181 FF |
1909 | if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc), |
1910 | timeout) > 0) | |
1911 | drop = false; | |
69081624 | 1912 | |
9df0d6a2 FF |
1913 | if (drop) { |
1914 | ath9k_ps_wakeup(sc); | |
1915 | spin_lock_bh(&sc->sc_pcu_lock); | |
1381559b | 1916 | drain_txq = ath_drain_all_txq(sc); |
9df0d6a2 | 1917 | spin_unlock_bh(&sc->sc_pcu_lock); |
9adcf440 | 1918 | |
9df0d6a2 | 1919 | if (!drain_txq) |
1381559b | 1920 | ath_reset(sc); |
9adcf440 | 1921 | |
9df0d6a2 FF |
1922 | ath9k_ps_restore(sc); |
1923 | ieee80211_wake_queues(hw); | |
1924 | } | |
d78f4b3e | 1925 | |
69081624 VT |
1926 | ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); |
1927 | mutex_unlock(&sc->mutex); | |
1928 | } | |
1929 | ||
15b91e83 VN |
1930 | static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) |
1931 | { | |
1932 | struct ath_softc *sc = hw->priv; | |
1933 | int i; | |
1934 | ||
1935 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1936 | if (!ATH_TXQ_SETUP(sc, i)) | |
1937 | continue; | |
1938 | ||
1939 | if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) | |
1940 | return true; | |
1941 | } | |
1942 | return false; | |
1943 | } | |
1944 | ||
5595f119 | 1945 | static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) |
ba4903f9 FF |
1946 | { |
1947 | struct ath_softc *sc = hw->priv; | |
1948 | struct ath_hw *ah = sc->sc_ah; | |
1949 | struct ieee80211_vif *vif; | |
1950 | struct ath_vif *avp; | |
1951 | struct ath_buf *bf; | |
1952 | struct ath_tx_status ts; | |
4286df60 | 1953 | bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); |
ba4903f9 FF |
1954 | int status; |
1955 | ||
1956 | vif = sc->beacon.bslot[0]; | |
1957 | if (!vif) | |
1958 | return 0; | |
1959 | ||
aa45fe96 | 1960 | if (!vif->bss_conf.enable_beacon) |
ba4903f9 FF |
1961 | return 0; |
1962 | ||
aa45fe96 SM |
1963 | avp = (void *)vif->drv_priv; |
1964 | ||
4286df60 | 1965 | if (!sc->beacon.tx_processed && !edma) { |
ba4903f9 FF |
1966 | tasklet_disable(&sc->bcon_tasklet); |
1967 | ||
1968 | bf = avp->av_bcbuf; | |
1969 | if (!bf || !bf->bf_mpdu) | |
1970 | goto skip; | |
1971 | ||
1972 | status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); | |
1973 | if (status == -EINPROGRESS) | |
1974 | goto skip; | |
1975 | ||
1976 | sc->beacon.tx_processed = true; | |
1977 | sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); | |
1978 | ||
1979 | skip: | |
1980 | tasklet_enable(&sc->bcon_tasklet); | |
1981 | } | |
1982 | ||
1983 | return sc->beacon.tx_last; | |
1984 | } | |
1985 | ||
52c94f41 MSS |
1986 | static int ath9k_get_stats(struct ieee80211_hw *hw, |
1987 | struct ieee80211_low_level_stats *stats) | |
1988 | { | |
1989 | struct ath_softc *sc = hw->priv; | |
1990 | struct ath_hw *ah = sc->sc_ah; | |
1991 | struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; | |
1992 | ||
1993 | stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; | |
1994 | stats->dot11RTSFailureCount = mib_stats->rts_bad; | |
1995 | stats->dot11FCSErrorCount = mib_stats->fcs_bad; | |
1996 | stats->dot11RTSSuccessCount = mib_stats->rts_good; | |
1997 | return 0; | |
1998 | } | |
1999 | ||
43c35284 FF |
2000 | static u32 fill_chainmask(u32 cap, u32 new) |
2001 | { | |
2002 | u32 filled = 0; | |
2003 | int i; | |
2004 | ||
2005 | for (i = 0; cap && new; i++, cap >>= 1) { | |
2006 | if (!(cap & BIT(0))) | |
2007 | continue; | |
2008 | ||
2009 | if (new & BIT(0)) | |
2010 | filled |= BIT(i); | |
2011 | ||
2012 | new >>= 1; | |
2013 | } | |
2014 | ||
2015 | return filled; | |
2016 | } | |
2017 | ||
5d9c7e3c FF |
2018 | static bool validate_antenna_mask(struct ath_hw *ah, u32 val) |
2019 | { | |
fea92cbf FF |
2020 | if (AR_SREV_9300_20_OR_LATER(ah)) |
2021 | return true; | |
2022 | ||
5d9c7e3c FF |
2023 | switch (val & 0x7) { |
2024 | case 0x1: | |
2025 | case 0x3: | |
2026 | case 0x7: | |
2027 | return true; | |
2028 | case 0x2: | |
2029 | return (ah->caps.rx_chainmask == 1); | |
2030 | default: | |
2031 | return false; | |
2032 | } | |
2033 | } | |
2034 | ||
43c35284 FF |
2035 | static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) |
2036 | { | |
2037 | struct ath_softc *sc = hw->priv; | |
2038 | struct ath_hw *ah = sc->sc_ah; | |
2039 | ||
5d9c7e3c FF |
2040 | if (ah->caps.rx_chainmask != 1) |
2041 | rx_ant |= tx_ant; | |
2042 | ||
2043 | if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) | |
43c35284 FF |
2044 | return -EINVAL; |
2045 | ||
2046 | sc->ant_rx = rx_ant; | |
2047 | sc->ant_tx = tx_ant; | |
2048 | ||
2049 | if (ah->caps.rx_chainmask == 1) | |
2050 | return 0; | |
2051 | ||
2052 | /* AR9100 runs into calibration issues if not all rx chains are enabled */ | |
2053 | if (AR_SREV_9100(ah)) | |
2054 | ah->rxchainmask = 0x7; | |
2055 | else | |
2056 | ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); | |
2057 | ||
2058 | ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); | |
2059 | ath9k_reload_chainmask_settings(sc); | |
2060 | ||
2061 | return 0; | |
2062 | } | |
2063 | ||
2064 | static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) | |
2065 | { | |
2066 | struct ath_softc *sc = hw->priv; | |
2067 | ||
2068 | *tx_ant = sc->ant_tx; | |
2069 | *rx_ant = sc->ant_rx; | |
2070 | return 0; | |
2071 | } | |
2072 | ||
e93d083f SW |
2073 | static void ath9k_sw_scan_start(struct ieee80211_hw *hw) |
2074 | { | |
2075 | struct ath_softc *sc = hw->priv; | |
73900cb0 | 2076 | set_bit(SC_OP_SCANNING, &sc->sc_flags); |
e93d083f SW |
2077 | } |
2078 | ||
2079 | static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) | |
2080 | { | |
2081 | struct ath_softc *sc = hw->priv; | |
73900cb0 | 2082 | clear_bit(SC_OP_SCANNING, &sc->sc_flags); |
e93d083f | 2083 | } |
b11e640a | 2084 | |
d074e8d5 SW |
2085 | static void ath9k_channel_switch_beacon(struct ieee80211_hw *hw, |
2086 | struct ieee80211_vif *vif, | |
2087 | struct cfg80211_chan_def *chandef) | |
2088 | { | |
2089 | struct ath_softc *sc = hw->priv; | |
2090 | ||
2091 | /* mac80211 does not support CSA in multi-if cases (yet) */ | |
2092 | if (WARN_ON(sc->csa_vif)) | |
2093 | return; | |
2094 | ||
2095 | sc->csa_vif = vif; | |
2096 | } | |
2097 | ||
6baff7f9 | 2098 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2099 | .tx = ath9k_tx, |
2100 | .start = ath9k_start, | |
2101 | .stop = ath9k_stop, | |
2102 | .add_interface = ath9k_add_interface, | |
6b3b991d | 2103 | .change_interface = ath9k_change_interface, |
8feceb67 VT |
2104 | .remove_interface = ath9k_remove_interface, |
2105 | .config = ath9k_config, | |
8feceb67 | 2106 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2107 | .sta_add = ath9k_sta_add, |
2108 | .sta_remove = ath9k_sta_remove, | |
5519541d | 2109 | .sta_notify = ath9k_sta_notify, |
8feceb67 | 2110 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2111 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2112 | .set_key = ath9k_set_key, |
8feceb67 | 2113 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2114 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2115 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2116 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2117 | .get_survey = ath9k_get_survey, |
3b319aae | 2118 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2119 | .set_coverage_class = ath9k_set_coverage_class, |
69081624 | 2120 | .flush = ath9k_flush, |
15b91e83 | 2121 | .tx_frames_pending = ath9k_tx_frames_pending, |
52c94f41 | 2122 | .tx_last_beacon = ath9k_tx_last_beacon, |
86a22acf | 2123 | .release_buffered_frames = ath9k_release_buffered_frames, |
52c94f41 | 2124 | .get_stats = ath9k_get_stats, |
43c35284 FF |
2125 | .set_antenna = ath9k_set_antenna, |
2126 | .get_antenna = ath9k_get_antenna, | |
b90bd9d1 | 2127 | |
e60001e7 | 2128 | #ifdef CONFIG_ATH9K_WOW |
b11e640a MSS |
2129 | .suspend = ath9k_suspend, |
2130 | .resume = ath9k_resume, | |
2131 | .set_wakeup = ath9k_set_wakeup, | |
2132 | #endif | |
2133 | ||
b90bd9d1 BG |
2134 | #ifdef CONFIG_ATH9K_DEBUGFS |
2135 | .get_et_sset_count = ath9k_get_et_sset_count, | |
a145daf7 SM |
2136 | .get_et_stats = ath9k_get_et_stats, |
2137 | .get_et_strings = ath9k_get_et_strings, | |
2138 | #endif | |
2139 | ||
1cdbaf0d | 2140 | #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS) |
a145daf7 | 2141 | .sta_add_debugfs = ath9k_sta_add_debugfs, |
b90bd9d1 | 2142 | #endif |
e93d083f SW |
2143 | .sw_scan_start = ath9k_sw_scan_start, |
2144 | .sw_scan_complete = ath9k_sw_scan_complete, | |
d074e8d5 | 2145 | .channel_switch_beacon = ath9k_channel_switch_beacon, |
8feceb67 | 2146 | }; |