ath9k: content DMA start / stop through the PCU lock
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
af03abec 19#include "btcoex.h"
f078f209 20
ff37e337
S
21static void ath_update_txpow(struct ath_softc *sc)
22{
cbe61d8a 23 struct ath_hw *ah = sc->sc_ah;
ff37e337 24
17d7904d 25 if (sc->curtxpow != sc->config.txpowlimit) {
de40f316 26 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
ff37e337 27 /* read back in case value is clamped */
9cc3271f 28 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
ff37e337
S
29 }
30}
31
32static u8 parse_mpdudensity(u8 mpdudensity)
33{
34 /*
35 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
36 * 0 for no restriction
37 * 1 for 1/4 us
38 * 2 for 1/2 us
39 * 3 for 1 us
40 * 4 for 2 us
41 * 5 for 4 us
42 * 6 for 8 us
43 * 7 for 16 us
44 */
45 switch (mpdudensity) {
46 case 0:
47 return 0;
48 case 1:
49 case 2:
50 case 3:
51 /* Our lower layer calculations limit our precision to
52 1 microsecond */
53 return 1;
54 case 4:
55 return 2;
56 case 5:
57 return 4;
58 case 6:
59 return 8;
60 case 7:
61 return 16;
62 default:
63 return 0;
64 }
65}
66
82880a7c
VT
67static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
68 struct ieee80211_hw *hw)
69{
70 struct ieee80211_channel *curchan = hw->conf.channel;
71 struct ath9k_channel *channel;
72 u8 chan_idx;
73
74 chan_idx = curchan->hw_value;
75 channel = &sc->sc_ah->channels[chan_idx];
76 ath9k_update_ichannel(sc, hw, channel);
77 return channel;
78}
79
55624204 80bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
81{
82 unsigned long flags;
83 bool ret;
84
9ecdef4b
LR
85 spin_lock_irqsave(&sc->sc_pm_lock, flags);
86 ret = ath9k_hw_setpower(sc->sc_ah, mode);
87 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
88
89 return ret;
90}
91
a91d75ae
LR
92void ath9k_ps_wakeup(struct ath_softc *sc)
93{
898c914a 94 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae
LR
95 unsigned long flags;
96
97 spin_lock_irqsave(&sc->sc_pm_lock, flags);
98 if (++sc->ps_usecount != 1)
99 goto unlock;
100
9ecdef4b 101 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 102
898c914a
FF
103 /*
104 * While the hardware is asleep, the cycle counters contain no
105 * useful data. Better clear them now so that they don't mess up
106 * survey data results.
107 */
108 spin_lock(&common->cc_lock);
109 ath_hw_cycle_counters_update(common);
110 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
111 spin_unlock(&common->cc_lock);
112
a91d75ae
LR
113 unlock:
114 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
115}
116
117void ath9k_ps_restore(struct ath_softc *sc)
118{
898c914a 119 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae
LR
120 unsigned long flags;
121
122 spin_lock_irqsave(&sc->sc_pm_lock, flags);
123 if (--sc->ps_usecount != 0)
124 goto unlock;
125
898c914a
FF
126 spin_lock(&common->cc_lock);
127 ath_hw_cycle_counters_update(common);
128 spin_unlock(&common->cc_lock);
129
1dbfd9d4
VN
130 if (sc->ps_idle)
131 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
132 else if (sc->ps_enabled &&
133 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1b04b930
S
134 PS_WAIT_FOR_CAB |
135 PS_WAIT_FOR_PSPOLL_DATA |
136 PS_WAIT_FOR_TX_ACK)))
9ecdef4b 137 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR
138
139 unlock:
140 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
141}
142
5ee08656
FF
143static void ath_start_ani(struct ath_common *common)
144{
145 struct ath_hw *ah = common->ah;
146 unsigned long timestamp = jiffies_to_msecs(jiffies);
147 struct ath_softc *sc = (struct ath_softc *) common->priv;
148
149 if (!(sc->sc_flags & SC_OP_ANI_RUN))
150 return;
151
152 if (sc->sc_flags & SC_OP_OFFCHANNEL)
153 return;
154
155 common->ani.longcal_timer = timestamp;
156 common->ani.shortcal_timer = timestamp;
157 common->ani.checkani_timer = timestamp;
158
159 mod_timer(&common->ani.timer,
160 jiffies +
161 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
162}
163
3430098a
FF
164static void ath_update_survey_nf(struct ath_softc *sc, int channel)
165{
166 struct ath_hw *ah = sc->sc_ah;
167 struct ath9k_channel *chan = &ah->channels[channel];
168 struct survey_info *survey = &sc->survey[channel];
169
170 if (chan->noisefloor) {
171 survey->filled |= SURVEY_INFO_NOISE_DBM;
172 survey->noise = chan->noisefloor;
173 }
174}
175
176static void ath_update_survey_stats(struct ath_softc *sc)
177{
178 struct ath_hw *ah = sc->sc_ah;
179 struct ath_common *common = ath9k_hw_common(ah);
180 int pos = ah->curchan - &ah->channels[0];
181 struct survey_info *survey = &sc->survey[pos];
182 struct ath_cycle_counters *cc = &common->cc_survey;
183 unsigned int div = common->clockrate * 1000;
184
0845735e
FF
185 if (!ah->curchan)
186 return;
187
898c914a
FF
188 if (ah->power_mode == ATH9K_PM_AWAKE)
189 ath_hw_cycle_counters_update(common);
3430098a
FF
190
191 if (cc->cycles > 0) {
192 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
193 SURVEY_INFO_CHANNEL_TIME_BUSY |
194 SURVEY_INFO_CHANNEL_TIME_RX |
195 SURVEY_INFO_CHANNEL_TIME_TX;
196 survey->channel_time += cc->cycles / div;
197 survey->channel_time_busy += cc->rx_busy / div;
198 survey->channel_time_rx += cc->rx_frame / div;
199 survey->channel_time_tx += cc->tx_frame / div;
200 }
201 memset(cc, 0, sizeof(*cc));
202
203 ath_update_survey_nf(sc, pos);
204}
205
ff37e337
S
206/*
207 * Set/change channels. If the channel is really being changed, it's done
208 * by reseting the chip. To accomplish this we must first cleanup any pending
209 * DMA, then restart stuff.
210*/
0e2dedf9
JM
211int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
212 struct ath9k_channel *hchan)
ff37e337 213{
20bd2a09 214 struct ath_wiphy *aphy = hw->priv;
cbe61d8a 215 struct ath_hw *ah = sc->sc_ah;
c46917bb 216 struct ath_common *common = ath9k_hw_common(ah);
25c56eec 217 struct ieee80211_conf *conf = &common->hw->conf;
ff37e337 218 bool fastcc = true, stopped;
ae8d2858 219 struct ieee80211_channel *channel = hw->conf.channel;
20bd2a09 220 struct ath9k_hw_cal_data *caldata = NULL;
ae8d2858 221 int r;
ff37e337
S
222
223 if (sc->sc_flags & SC_OP_INVALID)
224 return -EIO;
225
5ee08656
FF
226 del_timer_sync(&common->ani.timer);
227 cancel_work_sync(&sc->paprd_work);
228 cancel_work_sync(&sc->hw_check_work);
229 cancel_delayed_work_sync(&sc->tx_complete_work);
230
3cbb5dd7
VN
231 ath9k_ps_wakeup(sc);
232
6a6733f2
LR
233 spin_lock_bh(&sc->sc_pcu_lock);
234
c0d7c7af
LR
235 /*
236 * This is only performed if the channel settings have
237 * actually changed.
238 *
239 * To switch channels clear any pending DMA operations;
240 * wait long enough for the RX fifo to drain, reset the
241 * hardware at the new frequency, and then re-enable
242 * the relevant bits of the h/w.
243 */
4df3071e 244 ath9k_hw_disable_interrupts(ah);
043a0405 245 ath_drain_all_txq(sc, false);
5e848f78 246
c0d7c7af 247 stopped = ath_stoprecv(sc);
ff37e337 248
c0d7c7af
LR
249 /* XXX: do not flush receive queue here. We don't want
250 * to flush data frames already in queue because of
251 * changing channel. */
ff37e337 252
5ee08656 253 if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
c0d7c7af
LR
254 fastcc = false;
255
20bd2a09
FF
256 if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
257 caldata = &aphy->caldata;
258
c46917bb 259 ath_print(common, ATH_DBG_CONFIG,
1e51b2ff 260 "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
c46917bb 261 sc->sc_ah->curchan->channel,
1e51b2ff
LR
262 channel->center_freq, conf_is_ht40(conf),
263 fastcc);
ff37e337 264
20bd2a09 265 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
c0d7c7af 266 if (r) {
c46917bb 267 ath_print(common, ATH_DBG_FATAL,
f643e51d 268 "Unable to reset channel (%u MHz), "
c46917bb
LR
269 "reset status %d\n",
270 channel->center_freq, r);
3989279c 271 goto ps_restore;
ff37e337 272 }
c0d7c7af 273
c0d7c7af 274 if (ath_startrecv(sc) != 0) {
c46917bb
LR
275 ath_print(common, ATH_DBG_FATAL,
276 "Unable to restart recv logic\n");
3989279c
GJ
277 r = -EIO;
278 goto ps_restore;
c0d7c7af
LR
279 }
280
c0d7c7af 281 ath_update_txpow(sc);
3069168c 282 ath9k_hw_set_interrupts(ah, ah->imask);
3989279c 283
48a6a468
LR
284 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
285 ath_beacon_config(sc, NULL);
5ee08656 286 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
48a6a468 287 ath_start_ani(common);
5ee08656
FF
288 }
289
3989279c 290 ps_restore:
6a6733f2
LR
291 spin_unlock_bh(&sc->sc_pcu_lock);
292
3cbb5dd7 293 ath9k_ps_restore(sc);
3989279c 294 return r;
ff37e337
S
295}
296
9f42c2b6
FF
297static void ath_paprd_activate(struct ath_softc *sc)
298{
299 struct ath_hw *ah = sc->sc_ah;
20bd2a09 300 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 301 struct ath_common *common = ath9k_hw_common(ah);
9f42c2b6
FF
302 int chain;
303
20bd2a09 304 if (!caldata || !caldata->paprd_done)
9f42c2b6
FF
305 return;
306
307 ath9k_ps_wakeup(sc);
ddfef792 308 ar9003_paprd_enable(ah, false);
9f42c2b6 309 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
9094537c 310 if (!(common->tx_chainmask & BIT(chain)))
9f42c2b6
FF
311 continue;
312
20bd2a09 313 ar9003_paprd_populate_single_table(ah, caldata, chain);
9f42c2b6
FF
314 }
315
316 ar9003_paprd_enable(ah, true);
317 ath9k_ps_restore(sc);
318}
319
320void ath_paprd_calibrate(struct work_struct *work)
321{
322 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
323 struct ieee80211_hw *hw = sc->hw;
324 struct ath_hw *ah = sc->sc_ah;
325 struct ieee80211_hdr *hdr;
326 struct sk_buff *skb = NULL;
327 struct ieee80211_tx_info *tx_info;
328 int band = hw->conf.channel->band;
329 struct ieee80211_supported_band *sband = &sc->sbands[band];
330 struct ath_tx_control txctl;
20bd2a09 331 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 332 struct ath_common *common = ath9k_hw_common(ah);
9f42c2b6
FF
333 int qnum, ftype;
334 int chain_ok = 0;
335 int chain;
336 int len = 1800;
337 int time_left;
338 int i;
339
20bd2a09
FF
340 if (!caldata)
341 return;
342
9f42c2b6
FF
343 skb = alloc_skb(len, GFP_KERNEL);
344 if (!skb)
345 return;
346
347 tx_info = IEEE80211_SKB_CB(skb);
348
349 skb_put(skb, len);
350 memset(skb->data, 0, len);
351 hdr = (struct ieee80211_hdr *)skb->data;
352 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
353 hdr->frame_control = cpu_to_le16(ftype);
a3d3da14 354 hdr->duration_id = cpu_to_le16(10);
9f42c2b6
FF
355 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
356 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
357 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
358
359 memset(&txctl, 0, sizeof(txctl));
360 qnum = sc->tx.hwq_map[WME_AC_BE];
361 txctl.txq = &sc->tx.txq[qnum];
362
47399f1a 363 ath9k_ps_wakeup(sc);
9f42c2b6
FF
364 ar9003_paprd_init_table(ah);
365 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
9094537c 366 if (!(common->tx_chainmask & BIT(chain)))
9f42c2b6
FF
367 continue;
368
369 chain_ok = 0;
370 memset(tx_info, 0, sizeof(*tx_info));
371 tx_info->band = band;
372
373 for (i = 0; i < 4; i++) {
374 tx_info->control.rates[i].idx = sband->n_bitrates - 1;
375 tx_info->control.rates[i].count = 6;
376 }
377
378 init_completion(&sc->paprd_complete);
379 ar9003_paprd_setup_gain_table(ah, chain);
380 txctl.paprd = BIT(chain);
381 if (ath_tx_start(hw, skb, &txctl) != 0)
382 break;
383
384 time_left = wait_for_completion_timeout(&sc->paprd_complete,
ca369eb4 385 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
9f42c2b6
FF
386 if (!time_left) {
387 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
388 "Timeout waiting for paprd training on "
389 "TX chain %d\n",
390 chain);
ca369eb4 391 goto fail_paprd;
9f42c2b6
FF
392 }
393
394 if (!ar9003_paprd_is_done(ah))
395 break;
396
20bd2a09 397 if (ar9003_paprd_create_curve(ah, caldata, chain) != 0)
9f42c2b6
FF
398 break;
399
400 chain_ok = 1;
401 }
402 kfree_skb(skb);
403
404 if (chain_ok) {
20bd2a09 405 caldata->paprd_done = true;
9f42c2b6
FF
406 ath_paprd_activate(sc);
407 }
408
ca369eb4 409fail_paprd:
9f42c2b6
FF
410 ath9k_ps_restore(sc);
411}
412
ff37e337
S
413/*
414 * This routine performs the periodic noise floor calibration function
415 * that is used to adjust and optimize the chip performance. This
416 * takes environmental changes (location, temperature) into account.
417 * When the task is complete, it reschedules itself depending on the
418 * appropriate interval that was calculated.
419 */
55624204 420void ath_ani_calibrate(unsigned long data)
ff37e337 421{
20977d3e
S
422 struct ath_softc *sc = (struct ath_softc *)data;
423 struct ath_hw *ah = sc->sc_ah;
c46917bb 424 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
425 bool longcal = false;
426 bool shortcal = false;
427 bool aniflag = false;
428 unsigned int timestamp = jiffies_to_msecs(jiffies);
6044474e 429 u32 cal_interval, short_cal_interval, long_cal_interval;
b5bfc568 430 unsigned long flags;
6044474e
FF
431
432 if (ah->caldata && ah->caldata->nfcal_interference)
433 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
434 else
435 long_cal_interval = ATH_LONG_CALINTERVAL;
ff37e337 436
20977d3e
S
437 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
438 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 439
1ffc1c61
JM
440 /* Only calibrate if awake */
441 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
442 goto set_timer;
443
444 ath9k_ps_wakeup(sc);
445
ff37e337 446 /* Long calibration runs independently of short calibration. */
6044474e 447 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
ff37e337 448 longcal = true;
c46917bb 449 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
3d536acf 450 common->ani.longcal_timer = timestamp;
ff37e337
S
451 }
452
17d7904d 453 /* Short calibration applies only while caldone is false */
3d536acf
LR
454 if (!common->ani.caldone) {
455 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 456 shortcal = true;
c46917bb
LR
457 ath_print(common, ATH_DBG_ANI,
458 "shortcal @%lu\n", jiffies);
3d536acf
LR
459 common->ani.shortcal_timer = timestamp;
460 common->ani.resetcal_timer = timestamp;
ff37e337
S
461 }
462 } else {
3d536acf 463 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 464 ATH_RESTART_CALINTERVAL) {
3d536acf
LR
465 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
466 if (common->ani.caldone)
467 common->ani.resetcal_timer = timestamp;
ff37e337
S
468 }
469 }
470
471 /* Verify whether we must check ANI */
e36b27af
LR
472 if ((timestamp - common->ani.checkani_timer) >=
473 ah->config.ani_poll_interval) {
ff37e337 474 aniflag = true;
3d536acf 475 common->ani.checkani_timer = timestamp;
ff37e337
S
476 }
477
478 /* Skip all processing if there's nothing to do. */
479 if (longcal || shortcal || aniflag) {
480 /* Call ANI routine if necessary */
b5bfc568
FF
481 if (aniflag) {
482 spin_lock_irqsave(&common->cc_lock, flags);
22e66a4c 483 ath9k_hw_ani_monitor(ah, ah->curchan);
3430098a 484 ath_update_survey_stats(sc);
b5bfc568
FF
485 spin_unlock_irqrestore(&common->cc_lock, flags);
486 }
ff37e337
S
487
488 /* Perform calibration if necessary */
489 if (longcal || shortcal) {
3d536acf 490 common->ani.caldone =
43c27613
LR
491 ath9k_hw_calibrate(ah,
492 ah->curchan,
493 common->rx_chainmask,
494 longcal);
ff37e337
S
495 }
496 }
497
1ffc1c61
JM
498 ath9k_ps_restore(sc);
499
20977d3e 500set_timer:
ff37e337
S
501 /*
502 * Set timer interval based on previous results.
503 * The interval must be the shortest necessary to satisfy ANI,
504 * short calibration and long calibration.
505 */
aac9207e 506 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 507 if (sc->sc_ah->config.enable_ani)
e36b27af
LR
508 cal_interval = min(cal_interval,
509 (u32)ah->config.ani_poll_interval);
3d536acf 510 if (!common->ani.caldone)
20977d3e 511 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 512
3d536acf 513 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
20bd2a09
FF
514 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
515 if (!ah->caldata->paprd_done)
9f42c2b6
FF
516 ieee80211_queue_work(sc->hw, &sc->paprd_work);
517 else
518 ath_paprd_activate(sc);
519 }
ff37e337
S
520}
521
522/*
523 * Update tx/rx chainmask. For legacy association,
524 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT
525 * the chainmask configuration, for bt coexistence, use
526 * the chainmask configuration even in legacy mode.
ff37e337 527 */
0e2dedf9 528void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 529{
af03abec 530 struct ath_hw *ah = sc->sc_ah;
43c27613 531 struct ath_common *common = ath9k_hw_common(ah);
af03abec 532
5ee08656 533 if ((sc->sc_flags & SC_OP_OFFCHANNEL) || is_ht ||
766ec4a9 534 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
43c27613
LR
535 common->tx_chainmask = ah->caps.tx_chainmask;
536 common->rx_chainmask = ah->caps.rx_chainmask;
ff37e337 537 } else {
43c27613
LR
538 common->tx_chainmask = 1;
539 common->rx_chainmask = 1;
ff37e337
S
540 }
541
43c27613 542 ath_print(common, ATH_DBG_CONFIG,
c46917bb 543 "tx chmask: %d, rx chmask: %d\n",
43c27613
LR
544 common->tx_chainmask,
545 common->rx_chainmask);
ff37e337
S
546}
547
548static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
549{
550 struct ath_node *an;
551
552 an = (struct ath_node *)sta->drv_priv;
553
87792efc 554 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 555 ath_tx_node_init(sc, an);
9e98ac65 556 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S
557 sta->ht_cap.ampdu_factor);
558 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
559 }
ff37e337
S
560}
561
562static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
563{
564 struct ath_node *an = (struct ath_node *)sta->drv_priv;
565
566 if (sc->sc_flags & SC_OP_TXAGGR)
567 ath_tx_node_cleanup(sc, an);
568}
569
347809fc
FF
570void ath_hw_check(struct work_struct *work)
571{
572 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
573 int i;
574
575 ath9k_ps_wakeup(sc);
576
577 for (i = 0; i < 3; i++) {
578 if (ath9k_hw_check_alive(sc->sc_ah))
579 goto out;
580
581 msleep(1);
582 }
fac6b6a0 583 ath_reset(sc, true);
347809fc
FF
584
585out:
586 ath9k_ps_restore(sc);
587}
588
55624204 589void ath9k_tasklet(unsigned long data)
ff37e337
S
590{
591 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 592 struct ath_hw *ah = sc->sc_ah;
c46917bb 593 struct ath_common *common = ath9k_hw_common(ah);
af03abec 594
17d7904d 595 u32 status = sc->intrstatus;
b5c80475 596 u32 rxmask;
ff37e337 597
153e080d
VT
598 ath9k_ps_wakeup(sc);
599
347809fc 600 if (status & ATH9K_INT_FATAL) {
fac6b6a0 601 ath_reset(sc, true);
153e080d 602 ath9k_ps_restore(sc);
ff37e337 603 return;
063d8be3 604 }
ff37e337 605
6a6733f2
LR
606 spin_lock_bh(&sc->sc_pcu_lock);
607
347809fc
FF
608 if (!ath9k_hw_check_alive(ah))
609 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
610
b5c80475
FF
611 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
612 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
613 ATH9K_INT_RXORN);
614 else
615 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
616
617 if (status & rxmask) {
b5c80475
FF
618 /* Check for high priority Rx first */
619 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
620 (status & ATH9K_INT_RXHP))
621 ath_rx_tasklet(sc, 0, true);
622
623 ath_rx_tasklet(sc, 0, false);
ff37e337
S
624 }
625
e5003249
VT
626 if (status & ATH9K_INT_TX) {
627 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
628 ath_tx_edma_tasklet(sc);
629 else
630 ath_tx_tasklet(sc);
631 }
063d8be3 632
96148326 633 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM
634 /*
635 * TSF sync does not look correct; remain awake to sync with
636 * the next Beacon.
637 */
c46917bb
LR
638 ath_print(common, ATH_DBG_PS,
639 "TSFOOR - Sync with next Beacon\n");
1b04b930 640 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
54ce846e
JM
641 }
642
766ec4a9 643 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT
644 if (status & ATH9K_INT_GENTIMER)
645 ath_gen_timer_isr(sc->sc_ah);
646
ff37e337 647 /* re-enable hardware interrupt */
4df3071e 648 ath9k_hw_enable_interrupts(ah);
6a6733f2
LR
649
650 spin_unlock_bh(&sc->sc_pcu_lock);
153e080d 651 ath9k_ps_restore(sc);
ff37e337
S
652}
653
6baff7f9 654irqreturn_t ath_isr(int irq, void *dev)
ff37e337 655{
063d8be3
S
656#define SCHED_INTR ( \
657 ATH9K_INT_FATAL | \
658 ATH9K_INT_RXORN | \
659 ATH9K_INT_RXEOL | \
660 ATH9K_INT_RX | \
b5c80475
FF
661 ATH9K_INT_RXLP | \
662 ATH9K_INT_RXHP | \
063d8be3
S
663 ATH9K_INT_TX | \
664 ATH9K_INT_BMISS | \
665 ATH9K_INT_CST | \
ebb8e1d7
VT
666 ATH9K_INT_TSFOOR | \
667 ATH9K_INT_GENTIMER)
063d8be3 668
ff37e337 669 struct ath_softc *sc = dev;
cbe61d8a 670 struct ath_hw *ah = sc->sc_ah;
b5bfc568 671 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
672 enum ath9k_int status;
673 bool sched = false;
674
063d8be3
S
675 /*
676 * The hardware is not ready/present, don't
677 * touch anything. Note this can happen early
678 * on if the IRQ is shared.
679 */
680 if (sc->sc_flags & SC_OP_INVALID)
681 return IRQ_NONE;
ff37e337 682
063d8be3
S
683
684 /* shared irq, not for us */
685
153e080d 686 if (!ath9k_hw_intrpend(ah))
063d8be3 687 return IRQ_NONE;
063d8be3
S
688
689 /*
690 * Figure out the reason(s) for the interrupt. Note
691 * that the hal returns a pseudo-ISR that may include
692 * bits we haven't explicitly enabled so we mask the
693 * value to insure we only process bits we requested.
694 */
695 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 696 status &= ah->imask; /* discard unasked-for bits */
ff37e337 697
063d8be3
S
698 /*
699 * If there are no status bits set, then this interrupt was not
700 * for me (should have been caught above).
701 */
153e080d 702 if (!status)
063d8be3 703 return IRQ_NONE;
ff37e337 704
063d8be3
S
705 /* Cache the status */
706 sc->intrstatus = status;
707
708 if (status & SCHED_INTR)
709 sched = true;
710
711 /*
712 * If a FATAL or RXORN interrupt is received, we have to reset the
713 * chip immediately.
714 */
b5c80475
FF
715 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
716 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S
717 goto chip_reset;
718
08578b8f
LR
719 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
720 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF
721
722 spin_lock(&common->cc_lock);
723 ath_hw_cycle_counters_update(common);
08578b8f 724 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF
725 spin_unlock(&common->cc_lock);
726
08578b8f
LR
727 goto chip_reset;
728 }
729
063d8be3
S
730 if (status & ATH9K_INT_SWBA)
731 tasklet_schedule(&sc->bcon_tasklet);
732
733 if (status & ATH9K_INT_TXURN)
734 ath9k_hw_updatetxtriglevel(ah, true);
735
b5c80475
FF
736 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
737 if (status & ATH9K_INT_RXEOL) {
738 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
739 ath9k_hw_set_interrupts(ah, ah->imask);
740 }
741 }
742
063d8be3 743 if (status & ATH9K_INT_MIB) {
ff37e337 744 /*
063d8be3
S
745 * Disable interrupts until we service the MIB
746 * interrupt; otherwise it will continue to
747 * fire.
ff37e337 748 */
4df3071e 749 ath9k_hw_disable_interrupts(ah);
063d8be3
S
750 /*
751 * Let the hal handle the event. We assume
752 * it will clear whatever condition caused
753 * the interrupt.
754 */
88eac2da 755 spin_lock(&common->cc_lock);
bfc472bb 756 ath9k_hw_proc_mib_event(ah);
88eac2da 757 spin_unlock(&common->cc_lock);
4df3071e 758 ath9k_hw_enable_interrupts(ah);
063d8be3 759 }
ff37e337 760
153e080d
VT
761 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
762 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S
763 /* Clear RxAbort bit so that we can
764 * receive frames */
9ecdef4b 765 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 766 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 767 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 768 }
063d8be3
S
769
770chip_reset:
ff37e337 771
817e11de
S
772 ath_debug_stat_interrupt(sc, status);
773
ff37e337 774 if (sched) {
4df3071e
FF
775 /* turn off every interrupt */
776 ath9k_hw_disable_interrupts(ah);
ff37e337
S
777 tasklet_schedule(&sc->intr_tq);
778 }
779
780 return IRQ_HANDLED;
063d8be3
S
781
782#undef SCHED_INTR
ff37e337
S
783}
784
f078f209 785static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 786 struct ieee80211_channel *chan,
094d05dc 787 enum nl80211_channel_type channel_type)
f078f209
LR
788{
789 u32 chanmode = 0;
f078f209
LR
790
791 switch (chan->band) {
792 case IEEE80211_BAND_2GHZ:
094d05dc
S
793 switch(channel_type) {
794 case NL80211_CHAN_NO_HT:
795 case NL80211_CHAN_HT20:
f078f209 796 chanmode = CHANNEL_G_HT20;
094d05dc
S
797 break;
798 case NL80211_CHAN_HT40PLUS:
f078f209 799 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S
800 break;
801 case NL80211_CHAN_HT40MINUS:
f078f209 802 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S
803 break;
804 }
f078f209
LR
805 break;
806 case IEEE80211_BAND_5GHZ:
094d05dc
S
807 switch(channel_type) {
808 case NL80211_CHAN_NO_HT:
809 case NL80211_CHAN_HT20:
f078f209 810 chanmode = CHANNEL_A_HT20;
094d05dc
S
811 break;
812 case NL80211_CHAN_HT40PLUS:
f078f209 813 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S
814 break;
815 case NL80211_CHAN_HT40MINUS:
f078f209 816 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S
817 break;
818 }
f078f209
LR
819 break;
820 default:
821 break;
822 }
823
824 return chanmode;
825}
826
8feceb67 827static void ath9k_bss_assoc_info(struct ath_softc *sc,
9fa23e17 828 struct ieee80211_hw *hw,
5640b08e 829 struct ieee80211_vif *vif,
8feceb67 830 struct ieee80211_bss_conf *bss_conf)
f078f209 831{
9fa23e17 832 struct ath_wiphy *aphy = hw->priv;
f2b2143e 833 struct ath_hw *ah = sc->sc_ah;
1510718d 834 struct ath_common *common = ath9k_hw_common(ah);
f078f209 835
8feceb67 836 if (bss_conf->assoc) {
c46917bb
LR
837 ath_print(common, ATH_DBG_CONFIG,
838 "Bss Info ASSOC %d, bssid: %pM\n",
839 bss_conf->aid, common->curbssid);
f078f209 840
8feceb67 841 /* New association, store aid */
1510718d 842 common->curaid = bss_conf->aid;
f2b2143e 843 ath9k_hw_write_associd(ah);
2664f201
SB
844
845 /*
846 * Request a re-configuration of Beacon related timers
847 * on the receipt of the first Beacon frame (i.e.,
848 * after time sync with the AP).
849 */
1b04b930 850 sc->ps_flags |= PS_BEACON_SYNC;
f078f209 851
8feceb67 852 /* Configure the beacon */
2c3db3d5 853 ath_beacon_config(sc, vif);
f078f209 854
8feceb67 855 /* Reset rssi stats */
9fa23e17 856 aphy->last_rssi = ATH_RSSI_DUMMY_MARKER;
22e66a4c 857 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 858
6c3118e2 859 sc->sc_flags |= SC_OP_ANI_RUN;
3d536acf 860 ath_start_ani(common);
8feceb67 861 } else {
c46917bb 862 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1510718d 863 common->curaid = 0;
f38faa31 864 /* Stop ANI */
6c3118e2 865 sc->sc_flags &= ~SC_OP_ANI_RUN;
3d536acf 866 del_timer_sync(&common->ani.timer);
f078f209 867 }
8feceb67 868}
f078f209 869
68a89116 870void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 871{
cbe61d8a 872 struct ath_hw *ah = sc->sc_ah;
c46917bb 873 struct ath_common *common = ath9k_hw_common(ah);
68a89116 874 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 875 int r;
500c064d 876
3cbb5dd7 877 ath9k_ps_wakeup(sc);
6a6733f2
LR
878 spin_lock_bh(&sc->sc_pcu_lock);
879
93b1b37f 880 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 881
159cd468
VT
882 if (!ah->curchan)
883 ah->curchan = ath_get_curchannel(sc, sc->hw);
884
20bd2a09 885 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 886 if (r) {
c46917bb 887 ath_print(common, ATH_DBG_FATAL,
f643e51d 888 "Unable to reset channel (%u MHz), "
c46917bb
LR
889 "reset status %d\n",
890 channel->center_freq, r);
500c064d 891 }
500c064d
VT
892
893 ath_update_txpow(sc);
894 if (ath_startrecv(sc) != 0) {
c46917bb
LR
895 ath_print(common, ATH_DBG_FATAL,
896 "Unable to restart recv logic\n");
4bdd1e97 897 spin_unlock_bh(&sc->sc_pcu_lock);
500c064d
VT
898 return;
899 }
500c064d 900 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 901 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT
902
903 /* Re-Enable interrupts */
3069168c 904 ath9k_hw_set_interrupts(ah, ah->imask);
500c064d
VT
905
906 /* Enable LED */
08fc5c1b 907 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 908 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 909 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 910
68a89116 911 ieee80211_wake_queues(hw);
6a6733f2
LR
912 spin_unlock_bh(&sc->sc_pcu_lock);
913
3cbb5dd7 914 ath9k_ps_restore(sc);
500c064d
VT
915}
916
68a89116 917void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 918{
cbe61d8a 919 struct ath_hw *ah = sc->sc_ah;
68a89116 920 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 921 int r;
500c064d 922
3cbb5dd7 923 ath9k_ps_wakeup(sc);
6a6733f2
LR
924 spin_lock_bh(&sc->sc_pcu_lock);
925
68a89116 926 ieee80211_stop_queues(hw);
500c064d 927
982723df
VN
928 /*
929 * Keep the LED on when the radio is disabled
930 * during idle unassociated state.
931 */
932 if (!sc->ps_idle) {
933 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
934 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
935 }
500c064d
VT
936
937 /* Disable interrupts */
4df3071e 938 ath9k_hw_disable_interrupts(ah);
500c064d 939
043a0405 940 ath_drain_all_txq(sc, false); /* clear pending tx frames */
5e848f78 941
500c064d
VT
942 ath_stoprecv(sc); /* turn off frame recv */
943 ath_flushrecv(sc); /* flush recv queue */
944
159cd468 945 if (!ah->curchan)
68a89116 946 ah->curchan = ath_get_curchannel(sc, hw);
159cd468 947
20bd2a09 948 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 949 if (r) {
c46917bb 950 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
f643e51d 951 "Unable to reset channel (%u MHz), "
c46917bb
LR
952 "reset status %d\n",
953 channel->center_freq, r);
500c064d 954 }
500c064d
VT
955
956 ath9k_hw_phy_disable(ah);
5e848f78 957
93b1b37f 958 ath9k_hw_configpcipowersave(ah, 1, 1);
6a6733f2
LR
959
960 spin_unlock_bh(&sc->sc_pcu_lock);
3cbb5dd7 961 ath9k_ps_restore(sc);
6a6733f2 962
9ecdef4b 963 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
500c064d
VT
964}
965
ff37e337
S
966int ath_reset(struct ath_softc *sc, bool retry_tx)
967{
cbe61d8a 968 struct ath_hw *ah = sc->sc_ah;
c46917bb 969 struct ath_common *common = ath9k_hw_common(ah);
030bb495 970 struct ieee80211_hw *hw = sc->hw;
ae8d2858 971 int r;
ff37e337 972
2ab81d4a
S
973 /* Stop ANI */
974 del_timer_sync(&common->ani.timer);
975
6a6733f2
LR
976 spin_lock_bh(&sc->sc_pcu_lock);
977
cc9c378a
S
978 ieee80211_stop_queues(hw);
979
4df3071e 980 ath9k_hw_disable_interrupts(ah);
043a0405 981 ath_drain_all_txq(sc, retry_tx);
5e848f78 982
ff37e337
S
983 ath_stoprecv(sc);
984 ath_flushrecv(sc);
985
20bd2a09 986 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
ae8d2858 987 if (r)
c46917bb
LR
988 ath_print(common, ATH_DBG_FATAL,
989 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S
990
991 if (ath_startrecv(sc) != 0)
c46917bb
LR
992 ath_print(common, ATH_DBG_FATAL,
993 "Unable to start recv logic\n");
ff37e337
S
994
995 /*
996 * We may be doing a reset in response to a request
997 * that changes the channel so update any state that
998 * might change as a result.
999 */
ff37e337
S
1000 ath_update_txpow(sc);
1001
52b8ac92 1002 if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
2c3db3d5 1003 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1004
3069168c 1005 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337
S
1006
1007 if (retry_tx) {
1008 int i;
1009 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1010 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
1011 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1012 ath_txq_schedule(sc, &sc->tx.txq[i]);
1013 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
1014 }
1015 }
1016 }
1017
cc9c378a 1018 ieee80211_wake_queues(hw);
6a6733f2 1019 spin_unlock_bh(&sc->sc_pcu_lock);
cc9c378a 1020
2ab81d4a
S
1021 /* Start ANI */
1022 ath_start_ani(common);
1023
ae8d2858 1024 return r;
ff37e337
S
1025}
1026
ebe297c3 1027static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
ff37e337
S
1028{
1029 int qnum;
1030
1031 switch (queue) {
1032 case 0:
1d2231e2 1033 qnum = sc->tx.hwq_map[WME_AC_VO];
ff37e337
S
1034 break;
1035 case 1:
1d2231e2 1036 qnum = sc->tx.hwq_map[WME_AC_VI];
ff37e337
S
1037 break;
1038 case 2:
1d2231e2 1039 qnum = sc->tx.hwq_map[WME_AC_BE];
ff37e337
S
1040 break;
1041 case 3:
1d2231e2 1042 qnum = sc->tx.hwq_map[WME_AC_BK];
ff37e337
S
1043 break;
1044 default:
1d2231e2 1045 qnum = sc->tx.hwq_map[WME_AC_BE];
ff37e337
S
1046 break;
1047 }
1048
1049 return qnum;
1050}
1051
1052int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1053{
1054 int qnum;
1055
1056 switch (queue) {
1d2231e2 1057 case WME_AC_VO:
ff37e337
S
1058 qnum = 0;
1059 break;
1d2231e2 1060 case WME_AC_VI:
ff37e337
S
1061 qnum = 1;
1062 break;
1d2231e2 1063 case WME_AC_BE:
ff37e337
S
1064 qnum = 2;
1065 break;
1d2231e2 1066 case WME_AC_BK:
ff37e337
S
1067 qnum = 3;
1068 break;
1069 default:
1070 qnum = -1;
1071 break;
1072 }
1073
1074 return qnum;
1075}
1076
5f8e077c
LR
1077/* XXX: Remove me once we don't depend on ath9k_channel for all
1078 * this redundant data */
0e2dedf9
JM
1079void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1080 struct ath9k_channel *ichan)
5f8e077c 1081{
5f8e077c
LR
1082 struct ieee80211_channel *chan = hw->conf.channel;
1083 struct ieee80211_conf *conf = &hw->conf;
1084
1085 ichan->channel = chan->center_freq;
1086 ichan->chan = chan;
1087
1088 if (chan->band == IEEE80211_BAND_2GHZ) {
1089 ichan->chanmode = CHANNEL_G;
8813262e 1090 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
5f8e077c
LR
1091 } else {
1092 ichan->chanmode = CHANNEL_A;
1093 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1094 }
1095
25c56eec 1096 if (conf_is_ht(conf))
5f8e077c
LR
1097 ichan->chanmode = ath_get_extchanmode(sc, chan,
1098 conf->channel_type);
5f8e077c
LR
1099}
1100
ff37e337
S
1101/**********************/
1102/* mac80211 callbacks */
1103/**********************/
1104
8feceb67 1105static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1106{
bce048d7
JM
1107 struct ath_wiphy *aphy = hw->priv;
1108 struct ath_softc *sc = aphy->sc;
af03abec 1109 struct ath_hw *ah = sc->sc_ah;
c46917bb 1110 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1111 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1112 struct ath9k_channel *init_channel;
82880a7c 1113 int r;
f078f209 1114
c46917bb
LR
1115 ath_print(common, ATH_DBG_CONFIG,
1116 "Starting driver with initial channel: %d MHz\n",
1117 curchan->center_freq);
f078f209 1118
141b38b6
S
1119 mutex_lock(&sc->mutex);
1120
9580a222
JM
1121 if (ath9k_wiphy_started(sc)) {
1122 if (sc->chan_idx == curchan->hw_value) {
1123 /*
1124 * Already on the operational channel, the new wiphy
1125 * can be marked active.
1126 */
1127 aphy->state = ATH_WIPHY_ACTIVE;
1128 ieee80211_wake_queues(hw);
1129 } else {
1130 /*
1131 * Another wiphy is on another channel, start the new
1132 * wiphy in paused state.
1133 */
1134 aphy->state = ATH_WIPHY_PAUSED;
1135 ieee80211_stop_queues(hw);
1136 }
1137 mutex_unlock(&sc->mutex);
1138 return 0;
1139 }
1140 aphy->state = ATH_WIPHY_ACTIVE;
1141
8feceb67 1142 /* setup initial channel */
f078f209 1143
82880a7c 1144 sc->chan_idx = curchan->hw_value;
f078f209 1145
82880a7c 1146 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S
1147
1148 /* Reset SERDES registers */
af03abec 1149 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S
1150
1151 /*
1152 * The basic interface to setting the hardware in a good
1153 * state is ``reset''. On return the hardware is known to
1154 * be powered up and with interrupts disabled. This must
1155 * be followed by initialization of the appropriate bits
1156 * and then setup of the interrupt mask.
1157 */
4bdd1e97 1158 spin_lock_bh(&sc->sc_pcu_lock);
20bd2a09 1159 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 1160 if (r) {
c46917bb
LR
1161 ath_print(common, ATH_DBG_FATAL,
1162 "Unable to reset hardware; reset status %d "
1163 "(freq %u MHz)\n", r,
1164 curchan->center_freq);
4bdd1e97 1165 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1166 goto mutex_unlock;
ff37e337 1167 }
ff37e337
S
1168
1169 /*
1170 * This is needed only to setup initial state
1171 * but it's best done after a reset.
1172 */
1173 ath_update_txpow(sc);
8feceb67 1174
ff37e337
S
1175 /*
1176 * Setup the hardware after reset:
1177 * The receive engine is set going.
1178 * Frame transmit is handled entirely
1179 * in the frame output path; there's nothing to do
1180 * here except setup the interrupt mask.
1181 */
1182 if (ath_startrecv(sc) != 0) {
c46917bb
LR
1183 ath_print(common, ATH_DBG_FATAL,
1184 "Unable to start recv logic\n");
141b38b6 1185 r = -EIO;
4bdd1e97 1186 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1187 goto mutex_unlock;
f078f209 1188 }
4bdd1e97 1189 spin_unlock_bh(&sc->sc_pcu_lock);
8feceb67 1190
ff37e337 1191 /* Setup our intr mask. */
b5c80475
FF
1192 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1193 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1194 ATH9K_INT_GLOBAL;
1195
1196 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR
1197 ah->imask |= ATH9K_INT_RXHP |
1198 ATH9K_INT_RXLP |
1199 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF
1200 else
1201 ah->imask |= ATH9K_INT_RX;
ff37e337 1202
364734fa 1203 ah->imask |= ATH9K_INT_GTT;
ff37e337 1204
af03abec 1205 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 1206 ah->imask |= ATH9K_INT_CST;
ff37e337 1207
ff37e337
S
1208 sc->sc_flags &= ~SC_OP_INVALID;
1209
1210 /* Disable BMISS interrupt when we're not associated */
3069168c
PR
1211 ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1212 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337 1213
bce048d7 1214 ieee80211_wake_queues(hw);
ff37e337 1215
42935eca 1216 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 1217
766ec4a9
LR
1218 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1219 !ah->btcoex_hw.enabled) {
5e197292
LR
1220 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1221 AR_STOMP_LOW_WLAN_WGHT);
af03abec 1222 ath9k_hw_btcoex_enable(ah);
f985ad12 1223
5bb12791
LR
1224 if (common->bus_ops->bt_coex_prep)
1225 common->bus_ops->bt_coex_prep(common);
766ec4a9 1226 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1227 ath9k_btcoex_timer_resume(sc);
1773912b
VT
1228 }
1229
141b38b6
S
1230mutex_unlock:
1231 mutex_unlock(&sc->mutex);
1232
ae8d2858 1233 return r;
f078f209
LR
1234}
1235
8feceb67
VT
1236static int ath9k_tx(struct ieee80211_hw *hw,
1237 struct sk_buff *skb)
f078f209 1238{
528f0c6b 1239 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM
1240 struct ath_wiphy *aphy = hw->priv;
1241 struct ath_softc *sc = aphy->sc;
c46917bb 1242 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 1243 struct ath_tx_control txctl;
1bc14880
BP
1244 int padpos, padsize;
1245 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
84642d6b 1246 int qnum;
528f0c6b 1247
8089cc47 1248 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
c46917bb
LR
1249 ath_print(common, ATH_DBG_XMIT,
1250 "ath9k: %s: TX in unexpected wiphy state "
1251 "%d\n", wiphy_name(hw->wiphy), aphy->state);
ee166a0e
JM
1252 goto exit;
1253 }
1254
96148326 1255 if (sc->ps_enabled) {
dc8c4585
JM
1256 /*
1257 * mac80211 does not set PM field for normal data frames, so we
1258 * need to update that based on the current PS mode.
1259 */
1260 if (ieee80211_is_data(hdr->frame_control) &&
1261 !ieee80211_is_nullfunc(hdr->frame_control) &&
1262 !ieee80211_has_pm(hdr->frame_control)) {
c46917bb
LR
1263 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
1264 "while in PS mode\n");
dc8c4585
JM
1265 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1266 }
1267 }
1268
9a23f9ca
JM
1269 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1270 /*
1271 * We are using PS-Poll and mac80211 can request TX while in
1272 * power save mode. Need to wake up hardware for the TX to be
1273 * completed and if needed, also for RX of buffered frames.
1274 */
9a23f9ca 1275 ath9k_ps_wakeup(sc);
fdf76622
VT
1276 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1277 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 1278 if (ieee80211_is_pspoll(hdr->frame_control)) {
c46917bb
LR
1279 ath_print(common, ATH_DBG_PS,
1280 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 1281 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 1282 } else {
c46917bb
LR
1283 ath_print(common, ATH_DBG_PS,
1284 "Wake up to complete TX\n");
1b04b930 1285 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
1286 }
1287 /*
1288 * The actual restore operation will happen only after
1289 * the sc_flags bit is cleared. We are just dropping
1290 * the ps_usecount here.
1291 */
1292 ath9k_ps_restore(sc);
1293 }
1294
528f0c6b 1295 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 1296
8feceb67
VT
1297 /*
1298 * As a temporary workaround, assign seq# here; this will likely need
1299 * to be cleaned up to work better with Beacon transmission and virtual
1300 * BSSes.
1301 */
1302 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
8feceb67 1303 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 1304 sc->tx.seq_no += 0x10;
8feceb67 1305 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 1306 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 1307 }
f078f209 1308
8feceb67 1309 /* Add the padding after the header if this is not already done */
1bc14880
BP
1310 padpos = ath9k_cmn_padpos(hdr->frame_control);
1311 padsize = padpos & 3;
1312 if (padsize && skb->len>padpos) {
8feceb67
VT
1313 if (skb_headroom(skb) < padsize)
1314 return -1;
1315 skb_push(skb, padsize);
1bc14880 1316 memmove(skb->data, skb->data + padsize, padpos);
8feceb67
VT
1317 }
1318
84642d6b
FF
1319 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
1320 txctl.txq = &sc->tx.txq[qnum];
528f0c6b 1321
c46917bb 1322 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1323
c52f33d0 1324 if (ath_tx_start(hw, skb, &txctl) != 0) {
c46917bb 1325 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1326 goto exit;
8feceb67
VT
1327 }
1328
528f0c6b
S
1329 return 0;
1330exit:
1331 dev_kfree_skb_any(skb);
8feceb67 1332 return 0;
f078f209
LR
1333}
1334
8feceb67 1335static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 1336{
bce048d7
JM
1337 struct ath_wiphy *aphy = hw->priv;
1338 struct ath_softc *sc = aphy->sc;
af03abec 1339 struct ath_hw *ah = sc->sc_ah;
c46917bb 1340 struct ath_common *common = ath9k_hw_common(ah);
447a42c2 1341 int i;
f078f209 1342
4c483817
S
1343 mutex_lock(&sc->mutex);
1344
9580a222
JM
1345 aphy->state = ATH_WIPHY_INACTIVE;
1346
9a75c2ff
VN
1347 if (led_blink)
1348 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1349
c94dbff7 1350 cancel_delayed_work_sync(&sc->tx_complete_work);
9f42c2b6 1351 cancel_work_sync(&sc->paprd_work);
347809fc 1352 cancel_work_sync(&sc->hw_check_work);
c94dbff7 1353
447a42c2
RM
1354 for (i = 0; i < sc->num_sec_wiphy; i++) {
1355 if (sc->sec_wiphy[i])
1356 break;
1357 }
1358
1359 if (i == sc->num_sec_wiphy) {
c94dbff7
LR
1360 cancel_delayed_work_sync(&sc->wiphy_work);
1361 cancel_work_sync(&sc->chan_work);
1362 }
1363
9c84b797 1364 if (sc->sc_flags & SC_OP_INVALID) {
c46917bb 1365 ath_print(common, ATH_DBG_ANY, "Device not present\n");
4c483817 1366 mutex_unlock(&sc->mutex);
9c84b797
S
1367 return;
1368 }
8feceb67 1369
9580a222
JM
1370 if (ath9k_wiphy_started(sc)) {
1371 mutex_unlock(&sc->mutex);
1372 return; /* another wiphy still in use */
1373 }
1374
3867cf6a
S
1375 /* Ensure HW is awake when we try to shut it down. */
1376 ath9k_ps_wakeup(sc);
1377
766ec4a9 1378 if (ah->btcoex_hw.enabled) {
af03abec 1379 ath9k_hw_btcoex_disable(ah);
766ec4a9 1380 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1381 ath9k_btcoex_timer_pause(sc);
1773912b
VT
1382 }
1383
6a6733f2
LR
1384 spin_lock_bh(&sc->sc_pcu_lock);
1385
ff37e337
S
1386 /* make sure h/w will not generate any interrupt
1387 * before setting the invalid flag. */
4df3071e 1388 ath9k_hw_disable_interrupts(ah);
ff37e337
S
1389
1390 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 1391 ath_drain_all_txq(sc, false);
ff37e337 1392 ath_stoprecv(sc);
af03abec 1393 ath9k_hw_phy_disable(ah);
6a6733f2 1394 } else
b77f483f 1395 sc->rx.rxlink = NULL;
ff37e337 1396
ff37e337 1397 /* disable HAL and put h/w to sleep */
af03abec
LR
1398 ath9k_hw_disable(ah);
1399 ath9k_hw_configpcipowersave(ah, 1, 1);
6a6733f2
LR
1400
1401 spin_unlock_bh(&sc->sc_pcu_lock);
1402
3867cf6a
S
1403 ath9k_ps_restore(sc);
1404
1405 /* Finally, put the chip in FULL SLEEP mode */
9ecdef4b 1406 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
ff37e337
S
1407
1408 sc->sc_flags |= SC_OP_INVALID;
500c064d 1409
141b38b6
S
1410 mutex_unlock(&sc->mutex);
1411
c46917bb 1412 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR
1413}
1414
8feceb67 1415static int ath9k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 1416 struct ieee80211_vif *vif)
f078f209 1417{
bce048d7
JM
1418 struct ath_wiphy *aphy = hw->priv;
1419 struct ath_softc *sc = aphy->sc;
3069168c
PR
1420 struct ath_hw *ah = sc->sc_ah;
1421 struct ath_common *common = ath9k_hw_common(ah);
1ed32e4f 1422 struct ath_vif *avp = (void *)vif->drv_priv;
d97809db 1423 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 1424 int ret = 0;
8feceb67 1425
141b38b6
S
1426 mutex_lock(&sc->mutex);
1427
1ed32e4f 1428 switch (vif->type) {
05c914fe 1429 case NL80211_IFTYPE_STATION:
d97809db 1430 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 1431 break;
e51f3eff
BJ
1432 case NL80211_IFTYPE_WDS:
1433 ic_opmode = NL80211_IFTYPE_WDS;
1434 break;
05c914fe 1435 case NL80211_IFTYPE_ADHOC:
05c914fe 1436 case NL80211_IFTYPE_AP:
9cb5412b 1437 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM
1438 if (sc->nbcnvifs >= ATH_BCBUF) {
1439 ret = -ENOBUFS;
1440 goto out;
1441 }
1ed32e4f 1442 ic_opmode = vif->type;
f078f209
LR
1443 break;
1444 default:
c46917bb 1445 ath_print(common, ATH_DBG_FATAL,
1ed32e4f 1446 "Interface type %d not yet supported\n", vif->type);
2c3db3d5
JM
1447 ret = -EOPNOTSUPP;
1448 goto out;
f078f209
LR
1449 }
1450
c46917bb
LR
1451 ath_print(common, ATH_DBG_CONFIG,
1452 "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 1453
17d7904d 1454 /* Set the VIF opmode */
5640b08e
S
1455 avp->av_opmode = ic_opmode;
1456 avp->av_bslot = -1;
1457
2c3db3d5 1458 sc->nvifs++;
8ca21f01 1459
364734fa 1460 ath9k_set_bssid_mask(hw, vif);
8ca21f01 1461
2c3db3d5
JM
1462 if (sc->nvifs > 1)
1463 goto out; /* skip global settings for secondary vif */
1464
b238e90e 1465 if (ic_opmode == NL80211_IFTYPE_AP) {
3069168c 1466 ath9k_hw_set_tsfadjust(ah, 1);
b238e90e
S
1467 sc->sc_flags |= SC_OP_TSF_RESET;
1468 }
5640b08e 1469
5640b08e 1470 /* Set the device opmode */
3069168c 1471 ah->opmode = ic_opmode;
5640b08e 1472
4e30ffa2
VN
1473 /*
1474 * Enable MIB interrupts when there are hardware phy counters.
1475 * Note we only do this (at the moment) for station mode.
1476 */
1ed32e4f
JB
1477 if ((vif->type == NL80211_IFTYPE_STATION) ||
1478 (vif->type == NL80211_IFTYPE_ADHOC) ||
1479 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
3448f912
LR
1480 if (ah->config.enable_ani)
1481 ah->imask |= ATH9K_INT_MIB;
3069168c 1482 ah->imask |= ATH9K_INT_TSFOOR;
4af9cf4f
S
1483 }
1484
3069168c 1485 ath9k_hw_set_interrupts(ah, ah->imask);
4e30ffa2 1486
1ed32e4f
JB
1487 if (vif->type == NL80211_IFTYPE_AP ||
1488 vif->type == NL80211_IFTYPE_ADHOC ||
6c3118e2
VT
1489 vif->type == NL80211_IFTYPE_MONITOR) {
1490 sc->sc_flags |= SC_OP_ANI_RUN;
3d536acf 1491 ath_start_ani(common);
6c3118e2 1492 }
6f255425 1493
2c3db3d5 1494out:
141b38b6 1495 mutex_unlock(&sc->mutex);
2c3db3d5 1496 return ret;
f078f209
LR
1497}
1498
8feceb67 1499static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1500 struct ieee80211_vif *vif)
f078f209 1501{
bce048d7
JM
1502 struct ath_wiphy *aphy = hw->priv;
1503 struct ath_softc *sc = aphy->sc;
c46917bb 1504 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1ed32e4f 1505 struct ath_vif *avp = (void *)vif->drv_priv;
2c3db3d5 1506 int i;
f078f209 1507
c46917bb 1508 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 1509
141b38b6
S
1510 mutex_lock(&sc->mutex);
1511
6f255425 1512 /* Stop ANI */
6c3118e2 1513 sc->sc_flags &= ~SC_OP_ANI_RUN;
3d536acf 1514 del_timer_sync(&common->ani.timer);
580f0b8a 1515
8feceb67 1516 /* Reclaim beacon resources */
9cb5412b
PE
1517 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
1518 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
1519 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
5f70a88f 1520 ath9k_ps_wakeup(sc);
b77f483f 1521 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
5f70a88f 1522 ath9k_ps_restore(sc);
580f0b8a 1523 }
f078f209 1524
74401773 1525 ath_beacon_return(sc, avp);
8feceb67 1526 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 1527
2c3db3d5 1528 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1ed32e4f 1529 if (sc->beacon.bslot[i] == vif) {
2c3db3d5
JM
1530 printk(KERN_DEBUG "%s: vif had allocated beacon "
1531 "slot\n", __func__);
1532 sc->beacon.bslot[i] = NULL;
c52f33d0 1533 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM
1534 }
1535 }
1536
17d7904d 1537 sc->nvifs--;
141b38b6
S
1538
1539 mutex_unlock(&sc->mutex);
f078f209
LR
1540}
1541
fbab7390 1542static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1543{
3069168c
PR
1544 struct ath_hw *ah = sc->sc_ah;
1545
3f7c5c10 1546 sc->ps_enabled = true;
3069168c
PR
1547 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1548 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1549 ah->imask |= ATH9K_INT_TIM_TIMER;
1550 ath9k_hw_set_interrupts(ah, ah->imask);
3f7c5c10 1551 }
fdf76622 1552 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1553 }
3f7c5c10
SB
1554}
1555
845d708e
SB
1556static void ath9k_disable_ps(struct ath_softc *sc)
1557{
1558 struct ath_hw *ah = sc->sc_ah;
1559
1560 sc->ps_enabled = false;
1561 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1562 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1563 ath9k_hw_setrxabort(ah, 0);
1564 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1565 PS_WAIT_FOR_CAB |
1566 PS_WAIT_FOR_PSPOLL_DATA |
1567 PS_WAIT_FOR_TX_ACK);
1568 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1569 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1570 ath9k_hw_set_interrupts(ah, ah->imask);
1571 }
1572 }
1573
1574}
1575
e8975581 1576static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1577{
bce048d7
JM
1578 struct ath_wiphy *aphy = hw->priv;
1579 struct ath_softc *sc = aphy->sc;
3430098a
FF
1580 struct ath_hw *ah = sc->sc_ah;
1581 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1582 struct ieee80211_conf *conf = &hw->conf;
194b7c13 1583 bool disable_radio;
f078f209 1584
aa33de09 1585 mutex_lock(&sc->mutex);
141b38b6 1586
194b7c13
LR
1587 /*
1588 * Leave this as the first check because we need to turn on the
1589 * radio if it was disabled before prior to processing the rest
1590 * of the changes. Likewise we must only disable the radio towards
1591 * the end.
1592 */
64839170 1593 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
194b7c13
LR
1594 bool enable_radio;
1595 bool all_wiphys_idle;
1596 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
64839170
LR
1597
1598 spin_lock_bh(&sc->wiphy_lock);
1599 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
194b7c13
LR
1600 ath9k_set_wiphy_idle(aphy, idle);
1601
11446011 1602 enable_radio = (!idle && all_wiphys_idle);
194b7c13
LR
1603
1604 /*
1605 * After we unlock here its possible another wiphy
1606 * can be re-renabled so to account for that we will
1607 * only disable the radio toward the end of this routine
1608 * if by then all wiphys are still idle.
1609 */
64839170
LR
1610 spin_unlock_bh(&sc->wiphy_lock);
1611
194b7c13 1612 if (enable_radio) {
1dbfd9d4 1613 sc->ps_idle = false;
68a89116 1614 ath_radio_enable(sc, hw);
c46917bb
LR
1615 ath_print(common, ATH_DBG_CONFIG,
1616 "not-idle: enabling radio\n");
64839170
LR
1617 }
1618 }
1619
e7824a50
LR
1620 /*
1621 * We just prepare to enable PS. We have to wait until our AP has
1622 * ACK'd our null data frame to disable RX otherwise we'll ignore
1623 * those ACKs and end up retransmitting the same null data frames.
1624 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1625 */
3cbb5dd7 1626 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR
1627 unsigned long flags;
1628 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB
1629 if (conf->flags & IEEE80211_CONF_PS)
1630 ath9k_enable_ps(sc);
845d708e
SB
1631 else
1632 ath9k_disable_ps(sc);
8ab2cd09 1633 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN
1634 }
1635
199afd9d
S
1636 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1637 if (conf->flags & IEEE80211_CONF_MONITOR) {
1638 ath_print(common, ATH_DBG_CONFIG,
1639 "HW opmode set to Monitor mode\n");
1640 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1641 }
1642 }
1643
4797938c 1644 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 1645 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1646 int pos = curchan->hw_value;
3430098a
FF
1647 int old_pos = -1;
1648 unsigned long flags;
1649
1650 if (ah->curchan)
1651 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1652
0e2dedf9
JM
1653 aphy->chan_idx = pos;
1654 aphy->chan_is_ht = conf_is_ht(conf);
5ee08656
FF
1655 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1656 sc->sc_flags |= SC_OP_OFFCHANNEL;
1657 else
1658 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
0e2dedf9 1659
8089cc47
JM
1660 if (aphy->state == ATH_WIPHY_SCAN ||
1661 aphy->state == ATH_WIPHY_ACTIVE)
1662 ath9k_wiphy_pause_all_forced(sc, aphy);
1663 else {
1664 /*
1665 * Do not change operational channel based on a paused
1666 * wiphy changes.
1667 */
1668 goto skip_chan_change;
1669 }
0e2dedf9 1670
c46917bb
LR
1671 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
1672 curchan->center_freq);
f078f209 1673
5f8e077c 1674 /* XXX: remove me eventualy */
0e2dedf9 1675 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 1676
ecf70441 1677 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 1678
3430098a
FF
1679 /* update survey stats for the old channel before switching */
1680 spin_lock_irqsave(&common->cc_lock, flags);
1681 ath_update_survey_stats(sc);
1682 spin_unlock_irqrestore(&common->cc_lock, flags);
1683
1684 /*
1685 * If the operating channel changes, change the survey in-use flags
1686 * along with it.
1687 * Reset the survey data for the new channel, unless we're switching
1688 * back to the operating channel from an off-channel operation.
1689 */
1690 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1691 sc->cur_survey != &sc->survey[pos]) {
1692
1693 if (sc->cur_survey)
1694 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1695
1696 sc->cur_survey = &sc->survey[pos];
1697
1698 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1699 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1700 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1701 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1702 }
1703
0e2dedf9 1704 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
c46917bb
LR
1705 ath_print(common, ATH_DBG_FATAL,
1706 "Unable to set channel\n");
aa33de09 1707 mutex_unlock(&sc->mutex);
e11602b7
S
1708 return -EINVAL;
1709 }
3430098a
FF
1710
1711 /*
1712 * The most recent snapshot of channel->noisefloor for the old
1713 * channel is only available after the hardware reset. Copy it to
1714 * the survey stats now.
1715 */
1716 if (old_pos >= 0)
1717 ath_update_survey_nf(sc, old_pos);
094d05dc 1718 }
f078f209 1719
8089cc47 1720skip_chan_change:
c9f6a656 1721 if (changed & IEEE80211_CONF_CHANGE_POWER) {
17d7904d 1722 sc->config.txpowlimit = 2 * conf->power_level;
c9f6a656
LR
1723 ath_update_txpow(sc);
1724 }
f078f209 1725
194b7c13
LR
1726 spin_lock_bh(&sc->wiphy_lock);
1727 disable_radio = ath9k_all_wiphys_idle(sc);
1728 spin_unlock_bh(&sc->wiphy_lock);
1729
64839170 1730 if (disable_radio) {
c46917bb 1731 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
1dbfd9d4 1732 sc->ps_idle = true;
68a89116 1733 ath_radio_disable(sc, hw);
64839170
LR
1734 }
1735
aa33de09 1736 mutex_unlock(&sc->mutex);
141b38b6 1737
f078f209
LR
1738 return 0;
1739}
1740
8feceb67
VT
1741#define SUPPORTED_FILTERS \
1742 (FIF_PROMISC_IN_BSS | \
1743 FIF_ALLMULTI | \
1744 FIF_CONTROL | \
af6a3fc7 1745 FIF_PSPOLL | \
8feceb67
VT
1746 FIF_OTHER_BSS | \
1747 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1748 FIF_PROBE_REQ | \
8feceb67 1749 FIF_FCSFAIL)
c83be688 1750
8feceb67
VT
1751/* FIXME: sc->sc_full_reset ? */
1752static void ath9k_configure_filter(struct ieee80211_hw *hw,
1753 unsigned int changed_flags,
1754 unsigned int *total_flags,
3ac64bee 1755 u64 multicast)
8feceb67 1756{
bce048d7
JM
1757 struct ath_wiphy *aphy = hw->priv;
1758 struct ath_softc *sc = aphy->sc;
8feceb67 1759 u32 rfilt;
f078f209 1760
8feceb67
VT
1761 changed_flags &= SUPPORTED_FILTERS;
1762 *total_flags &= SUPPORTED_FILTERS;
f078f209 1763
b77f483f 1764 sc->rx.rxfilter = *total_flags;
aa68aeaa 1765 ath9k_ps_wakeup(sc);
8feceb67
VT
1766 rfilt = ath_calcrxfilter(sc);
1767 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1768 ath9k_ps_restore(sc);
f078f209 1769
c46917bb
LR
1770 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1771 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 1772}
f078f209 1773
4ca77860
JB
1774static int ath9k_sta_add(struct ieee80211_hw *hw,
1775 struct ieee80211_vif *vif,
1776 struct ieee80211_sta *sta)
8feceb67 1777{
bce048d7
JM
1778 struct ath_wiphy *aphy = hw->priv;
1779 struct ath_softc *sc = aphy->sc;
f078f209 1780
4ca77860
JB
1781 ath_node_attach(sc, sta);
1782
1783 return 0;
1784}
1785
1786static int ath9k_sta_remove(struct ieee80211_hw *hw,
1787 struct ieee80211_vif *vif,
1788 struct ieee80211_sta *sta)
1789{
1790 struct ath_wiphy *aphy = hw->priv;
1791 struct ath_softc *sc = aphy->sc;
1792
1793 ath_node_detach(sc, sta);
1794
1795 return 0;
f078f209
LR
1796}
1797
141b38b6 1798static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 1799 const struct ieee80211_tx_queue_params *params)
f078f209 1800{
bce048d7
JM
1801 struct ath_wiphy *aphy = hw->priv;
1802 struct ath_softc *sc = aphy->sc;
c46917bb 1803 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67
VT
1804 struct ath9k_tx_queue_info qi;
1805 int ret = 0, qnum;
f078f209 1806
8feceb67
VT
1807 if (queue >= WME_NUM_AC)
1808 return 0;
f078f209 1809
141b38b6
S
1810 mutex_lock(&sc->mutex);
1811
1ffb0610
S
1812 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1813
8feceb67
VT
1814 qi.tqi_aifs = params->aifs;
1815 qi.tqi_cwmin = params->cw_min;
1816 qi.tqi_cwmax = params->cw_max;
1817 qi.tqi_burstTime = params->txop;
1818 qnum = ath_get_hal_qnum(queue, sc);
f078f209 1819
c46917bb
LR
1820 ath_print(common, ATH_DBG_CONFIG,
1821 "Configure tx [queue/halq] [%d/%d], "
1822 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1823 queue, qnum, params->aifs, params->cw_min,
1824 params->cw_max, params->txop);
f078f209 1825
8feceb67
VT
1826 ret = ath_txq_update(sc, qnum, &qi);
1827 if (ret)
c46917bb 1828 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 1829
94db2936 1830 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
1d2231e2 1831 if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret)
94db2936
VN
1832 ath_beaconq_config(sc);
1833
141b38b6
S
1834 mutex_unlock(&sc->mutex);
1835
8feceb67
VT
1836 return ret;
1837}
f078f209 1838
8feceb67
VT
1839static int ath9k_set_key(struct ieee80211_hw *hw,
1840 enum set_key_cmd cmd,
dc822b5d
JB
1841 struct ieee80211_vif *vif,
1842 struct ieee80211_sta *sta,
8feceb67
VT
1843 struct ieee80211_key_conf *key)
1844{
bce048d7
JM
1845 struct ath_wiphy *aphy = hw->priv;
1846 struct ath_softc *sc = aphy->sc;
c46917bb 1847 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1848 int ret = 0;
f078f209 1849
b3bd89ce
JM
1850 if (modparam_nohwcrypt)
1851 return -ENOSPC;
1852
141b38b6 1853 mutex_lock(&sc->mutex);
3cbb5dd7 1854 ath9k_ps_wakeup(sc);
c46917bb 1855 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 1856
8feceb67
VT
1857 switch (cmd) {
1858 case SET_KEY:
040e539e 1859 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1860 if (ret >= 0) {
1861 key->hw_key_idx = ret;
8feceb67
VT
1862 /* push IV and Michael MIC generation to stack */
1863 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1864 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1865 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB
1866 if (sc->sc_ah->sw_mgmt_crypto &&
1867 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 1868 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1869 ret = 0;
8feceb67
VT
1870 }
1871 break;
1872 case DISABLE_KEY:
040e539e 1873 ath_key_delete(common, key);
8feceb67
VT
1874 break;
1875 default:
1876 ret = -EINVAL;
1877 }
f078f209 1878
3cbb5dd7 1879 ath9k_ps_restore(sc);
141b38b6
S
1880 mutex_unlock(&sc->mutex);
1881
8feceb67
VT
1882 return ret;
1883}
f078f209 1884
8feceb67
VT
1885static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1886 struct ieee80211_vif *vif,
1887 struct ieee80211_bss_conf *bss_conf,
1888 u32 changed)
1889{
bce048d7
JM
1890 struct ath_wiphy *aphy = hw->priv;
1891 struct ath_softc *sc = aphy->sc;
2d0ddec5 1892 struct ath_hw *ah = sc->sc_ah;
1510718d 1893 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1894 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 1895 int slottime;
c6089ccc 1896 int error;
f078f209 1897
141b38b6
S
1898 mutex_lock(&sc->mutex);
1899
c6089ccc
S
1900 if (changed & BSS_CHANGED_BSSID) {
1901 /* Set BSSID */
1902 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1903 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1510718d 1904 common->curaid = 0;
f2b2143e 1905 ath9k_hw_write_associd(ah);
2d0ddec5 1906
c6089ccc
S
1907 /* Set aggregation protection mode parameters */
1908 sc->config.ath_aggr_prot = 0;
2d0ddec5 1909
c6089ccc
S
1910 /* Only legacy IBSS for now */
1911 if (vif->type == NL80211_IFTYPE_ADHOC)
1912 ath_update_chainmask(sc, 0);
2d0ddec5 1913
c6089ccc
S
1914 ath_print(common, ATH_DBG_CONFIG,
1915 "BSSID: %pM aid: 0x%x\n",
1916 common->curbssid, common->curaid);
2d0ddec5 1917
c6089ccc
S
1918 /* need to reconfigure the beacon */
1919 sc->sc_flags &= ~SC_OP_BEACONS ;
1920 }
2d0ddec5 1921
c6089ccc
S
1922 /* Enable transmission of beacons (AP, IBSS, MESH) */
1923 if ((changed & BSS_CHANGED_BEACON) ||
1924 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
1925 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1926 error = ath_beacon_alloc(aphy, vif);
1927 if (!error)
1928 ath_beacon_config(sc, vif);
0005baf4
FF
1929 }
1930
1931 if (changed & BSS_CHANGED_ERP_SLOT) {
1932 if (bss_conf->use_short_slot)
1933 slottime = 9;
1934 else
1935 slottime = 20;
1936 if (vif->type == NL80211_IFTYPE_AP) {
1937 /*
1938 * Defer update, so that connected stations can adjust
1939 * their settings at the same time.
1940 * See beacon.c for more details
1941 */
1942 sc->beacon.slottime = slottime;
1943 sc->beacon.updateslot = UPDATE;
1944 } else {
1945 ah->slottime = slottime;
1946 ath9k_hw_init_global_settings(ah);
1947 }
2d0ddec5
JB
1948 }
1949
c6089ccc
S
1950 /* Disable transmission of beacons */
1951 if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
1952 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2d0ddec5 1953
c6089ccc
S
1954 if (changed & BSS_CHANGED_BEACON_INT) {
1955 sc->beacon_interval = bss_conf->beacon_int;
1956 /*
1957 * In case of AP mode, the HW TSF has to be reset
1958 * when the beacon interval changes.
1959 */
1960 if (vif->type == NL80211_IFTYPE_AP) {
1961 sc->sc_flags |= SC_OP_TSF_RESET;
1962 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2d0ddec5
JB
1963 error = ath_beacon_alloc(aphy, vif);
1964 if (!error)
1965 ath_beacon_config(sc, vif);
c6089ccc
S
1966 } else {
1967 ath_beacon_config(sc, vif);
2d0ddec5
JB
1968 }
1969 }
1970
8feceb67 1971 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
c46917bb
LR
1972 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
1973 bss_conf->use_short_preamble);
8feceb67
VT
1974 if (bss_conf->use_short_preamble)
1975 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
1976 else
1977 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
1978 }
f078f209 1979
8feceb67 1980 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
c46917bb
LR
1981 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
1982 bss_conf->use_cts_prot);
8feceb67
VT
1983 if (bss_conf->use_cts_prot &&
1984 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
1985 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
1986 else
1987 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
1988 }
f078f209 1989
8feceb67 1990 if (changed & BSS_CHANGED_ASSOC) {
c46917bb 1991 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 1992 bss_conf->assoc);
9fa23e17 1993 ath9k_bss_assoc_info(sc, hw, vif, bss_conf);
8feceb67 1994 }
141b38b6
S
1995
1996 mutex_unlock(&sc->mutex);
8feceb67 1997}
f078f209 1998
8feceb67
VT
1999static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2000{
2001 u64 tsf;
bce048d7
JM
2002 struct ath_wiphy *aphy = hw->priv;
2003 struct ath_softc *sc = aphy->sc;
f078f209 2004
141b38b6
S
2005 mutex_lock(&sc->mutex);
2006 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2007 mutex_unlock(&sc->mutex);
f078f209 2008
8feceb67
VT
2009 return tsf;
2010}
f078f209 2011
3b5d665b
AF
2012static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2013{
bce048d7
JM
2014 struct ath_wiphy *aphy = hw->priv;
2015 struct ath_softc *sc = aphy->sc;
3b5d665b 2016
141b38b6
S
2017 mutex_lock(&sc->mutex);
2018 ath9k_hw_settsf64(sc->sc_ah, tsf);
2019 mutex_unlock(&sc->mutex);
3b5d665b
AF
2020}
2021
8feceb67
VT
2022static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2023{
bce048d7
JM
2024 struct ath_wiphy *aphy = hw->priv;
2025 struct ath_softc *sc = aphy->sc;
c83be688 2026
141b38b6 2027 mutex_lock(&sc->mutex);
21526d57
LR
2028
2029 ath9k_ps_wakeup(sc);
141b38b6 2030 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
2031 ath9k_ps_restore(sc);
2032
141b38b6 2033 mutex_unlock(&sc->mutex);
8feceb67 2034}
f078f209 2035
8feceb67 2036static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2037 struct ieee80211_vif *vif,
141b38b6
S
2038 enum ieee80211_ampdu_mlme_action action,
2039 struct ieee80211_sta *sta,
2040 u16 tid, u16 *ssn)
8feceb67 2041{
bce048d7
JM
2042 struct ath_wiphy *aphy = hw->priv;
2043 struct ath_softc *sc = aphy->sc;
8feceb67 2044 int ret = 0;
f078f209 2045
85ad181e
JB
2046 local_bh_disable();
2047
8feceb67
VT
2048 switch (action) {
2049 case IEEE80211_AMPDU_RX_START:
dca3edb8
S
2050 if (!(sc->sc_flags & SC_OP_RXAGGR))
2051 ret = -ENOTSUPP;
8feceb67
VT
2052 break;
2053 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
2054 break;
2055 case IEEE80211_AMPDU_TX_START:
8b685ba9 2056 ath9k_ps_wakeup(sc);
231c3a1f
FF
2057 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2058 if (!ret)
2059 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2060 ath9k_ps_restore(sc);
8feceb67
VT
2061 break;
2062 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 2063 ath9k_ps_wakeup(sc);
f83da965 2064 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 2065 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2066 ath9k_ps_restore(sc);
8feceb67 2067 break;
b1720231 2068 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 2069 ath9k_ps_wakeup(sc);
8469cdef 2070 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 2071 ath9k_ps_restore(sc);
8469cdef 2072 break;
8feceb67 2073 default:
c46917bb
LR
2074 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
2075 "Unknown AMPDU action\n");
8feceb67
VT
2076 }
2077
85ad181e
JB
2078 local_bh_enable();
2079
8feceb67 2080 return ret;
f078f209
LR
2081}
2082
62dad5b0
BP
2083static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2084 struct survey_info *survey)
2085{
2086 struct ath_wiphy *aphy = hw->priv;
2087 struct ath_softc *sc = aphy->sc;
3430098a 2088 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 2089 struct ieee80211_supported_band *sband;
3430098a
FF
2090 struct ieee80211_channel *chan;
2091 unsigned long flags;
2092 int pos;
2093
2094 spin_lock_irqsave(&common->cc_lock, flags);
2095 if (idx == 0)
2096 ath_update_survey_stats(sc);
39162dbe
FF
2097
2098 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2099 if (sband && idx >= sband->n_channels) {
2100 idx -= sband->n_channels;
2101 sband = NULL;
2102 }
62dad5b0 2103
39162dbe
FF
2104 if (!sband)
2105 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 2106
3430098a
FF
2107 if (!sband || idx >= sband->n_channels) {
2108 spin_unlock_irqrestore(&common->cc_lock, flags);
2109 return -ENOENT;
4f1a5a4b 2110 }
62dad5b0 2111
3430098a
FF
2112 chan = &sband->channels[idx];
2113 pos = chan->hw_value;
2114 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2115 survey->channel = chan;
2116 spin_unlock_irqrestore(&common->cc_lock, flags);
2117
62dad5b0
BP
2118 return 0;
2119}
2120
0c98de65
S
2121static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2122{
bce048d7
JM
2123 struct ath_wiphy *aphy = hw->priv;
2124 struct ath_softc *sc = aphy->sc;
0c98de65 2125
3d832611 2126 mutex_lock(&sc->mutex);
8089cc47 2127 if (ath9k_wiphy_scanning(sc)) {
8089cc47 2128 /*
30888338
LR
2129 * There is a race here in mac80211 but fixing it requires
2130 * we revisit how we handle the scan complete callback.
2131 * After mac80211 fixes we will not have configured hardware
2132 * to the home channel nor would we have configured the RX
2133 * filter yet.
8089cc47 2134 */
3d832611 2135 mutex_unlock(&sc->mutex);
8089cc47
JM
2136 return;
2137 }
2138
2139 aphy->state = ATH_WIPHY_SCAN;
2140 ath9k_wiphy_pause_all_forced(sc, aphy);
3d832611 2141 mutex_unlock(&sc->mutex);
0c98de65
S
2142}
2143
30888338
LR
2144/*
2145 * XXX: this requires a revisit after the driver
2146 * scan_complete gets moved to another place/removed in mac80211.
2147 */
0c98de65
S
2148static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2149{
bce048d7
JM
2150 struct ath_wiphy *aphy = hw->priv;
2151 struct ath_softc *sc = aphy->sc;
0c98de65 2152
3d832611 2153 mutex_lock(&sc->mutex);
8089cc47 2154 aphy->state = ATH_WIPHY_ACTIVE;
3d832611 2155 mutex_unlock(&sc->mutex);
0c98de65
S
2156}
2157
e239d859
FF
2158static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2159{
2160 struct ath_wiphy *aphy = hw->priv;
2161 struct ath_softc *sc = aphy->sc;
2162 struct ath_hw *ah = sc->sc_ah;
2163
2164 mutex_lock(&sc->mutex);
2165 ah->coverage_class = coverage_class;
2166 ath9k_hw_init_global_settings(ah);
2167 mutex_unlock(&sc->mutex);
2168}
2169
6baff7f9 2170struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2171 .tx = ath9k_tx,
2172 .start = ath9k_start,
2173 .stop = ath9k_stop,
2174 .add_interface = ath9k_add_interface,
2175 .remove_interface = ath9k_remove_interface,
2176 .config = ath9k_config,
8feceb67 2177 .configure_filter = ath9k_configure_filter,
4ca77860
JB
2178 .sta_add = ath9k_sta_add,
2179 .sta_remove = ath9k_sta_remove,
8feceb67 2180 .conf_tx = ath9k_conf_tx,
8feceb67 2181 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2182 .set_key = ath9k_set_key,
8feceb67 2183 .get_tsf = ath9k_get_tsf,
3b5d665b 2184 .set_tsf = ath9k_set_tsf,
8feceb67 2185 .reset_tsf = ath9k_reset_tsf,
4233df6b 2186 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2187 .get_survey = ath9k_get_survey,
0c98de65
S
2188 .sw_scan_start = ath9k_sw_scan_start,
2189 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 2190 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2191 .set_coverage_class = ath9k_set_coverage_class,
8feceb67 2192};
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