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ath9k: rename ath_btcoex_info to ath_btcoex_hw
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
af03abec 19#include "btcoex.h"
f078f209 20
f078f209
LR		 21static char *dev_info = "ath9k";
22
23MODULE_AUTHOR("Atheros Communications");
24MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26MODULE_LICENSE("Dual BSD/GPL");
27
b3bd89ce
JM		 28static int modparam_nohwcrypt;
29module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
30MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
31
5f8e077c
LR		 32/* We use the hw_value as an index into our private channel structure */
33
34#define CHAN2G(_freq, _idx) { \
35 .center_freq = (_freq), \
36 .hw_value = (_idx), \
eeddfd9d 37 .max_power = 20, \
5f8e077c
LR		 38}
39
40#define CHAN5G(_freq, _idx) { \
41 .band = IEEE80211_BAND_5GHZ, \
42 .center_freq = (_freq), \
43 .hw_value = (_idx), \
eeddfd9d 44 .max_power = 20, \
5f8e077c
LR		 45}
46
47/* Some 2 GHz radios are actually tunable on 2312-2732
48 * on 5 MHz steps, we support the channels which we know
49 * we have calibration data for all cards though to make
50 * this static */
51static struct ieee80211_channel ath9k_2ghz_chantable[] = {
52 CHAN2G(2412, 0), /* Channel 1 */
53 CHAN2G(2417, 1), /* Channel 2 */
54 CHAN2G(2422, 2), /* Channel 3 */
55 CHAN2G(2427, 3), /* Channel 4 */
56 CHAN2G(2432, 4), /* Channel 5 */
57 CHAN2G(2437, 5), /* Channel 6 */
58 CHAN2G(2442, 6), /* Channel 7 */
59 CHAN2G(2447, 7), /* Channel 8 */
60 CHAN2G(2452, 8), /* Channel 9 */
61 CHAN2G(2457, 9), /* Channel 10 */
62 CHAN2G(2462, 10), /* Channel 11 */
63 CHAN2G(2467, 11), /* Channel 12 */
64 CHAN2G(2472, 12), /* Channel 13 */
65 CHAN2G(2484, 13), /* Channel 14 */
66};
67
68/* Some 5 GHz radios are actually tunable on XXXX-YYYY
69 * on 5 MHz steps, we support the channels which we know
70 * we have calibration data for all cards though to make
71 * this static */
72static struct ieee80211_channel ath9k_5ghz_chantable[] = {
73 /* _We_ call this UNII 1 */
74 CHAN5G(5180, 14), /* Channel 36 */
75 CHAN5G(5200, 15), /* Channel 40 */
76 CHAN5G(5220, 16), /* Channel 44 */
77 CHAN5G(5240, 17), /* Channel 48 */
78 /* _We_ call this UNII 2 */
79 CHAN5G(5260, 18), /* Channel 52 */
80 CHAN5G(5280, 19), /* Channel 56 */
81 CHAN5G(5300, 20), /* Channel 60 */
82 CHAN5G(5320, 21), /* Channel 64 */
83 /* _We_ call this "Middle band" */
84 CHAN5G(5500, 22), /* Channel 100 */
85 CHAN5G(5520, 23), /* Channel 104 */
86 CHAN5G(5540, 24), /* Channel 108 */
87 CHAN5G(5560, 25), /* Channel 112 */
88 CHAN5G(5580, 26), /* Channel 116 */
89 CHAN5G(5600, 27), /* Channel 120 */
90 CHAN5G(5620, 28), /* Channel 124 */
91 CHAN5G(5640, 29), /* Channel 128 */
92 CHAN5G(5660, 30), /* Channel 132 */
93 CHAN5G(5680, 31), /* Channel 136 */
94 CHAN5G(5700, 32), /* Channel 140 */
95 /* _We_ call this UNII 3 */
96 CHAN5G(5745, 33), /* Channel 149 */
97 CHAN5G(5765, 34), /* Channel 153 */
98 CHAN5G(5785, 35), /* Channel 157 */
99 CHAN5G(5805, 36), /* Channel 161 */
100 CHAN5G(5825, 37), /* Channel 165 */
101};
102
ce111bad
LR		 103static void ath_cache_conf_rate(struct ath_softc *sc,
104 struct ieee80211_conf *conf)
ff37e337 105{
030bb495
LR		 106 switch (conf->channel->band) {
107 case IEEE80211_BAND_2GHZ:
108 if (conf_is_ht20(conf))
109 sc->cur_rate_table =
110 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
111 else if (conf_is_ht40_minus(conf))
112 sc->cur_rate_table =
113 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
114 else if (conf_is_ht40_plus(conf))
115 sc->cur_rate_table =
116 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 117 else
030bb495
LR		 118 sc->cur_rate_table =
119 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 120 break;
121 case IEEE80211_BAND_5GHZ:
122 if (conf_is_ht20(conf))
123 sc->cur_rate_table =
124 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
125 else if (conf_is_ht40_minus(conf))
126 sc->cur_rate_table =
127 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
128 else if (conf_is_ht40_plus(conf))
129 sc->cur_rate_table =
130 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
131 else
96742256
LR		 132 sc->cur_rate_table =
133 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 134 break;
135 default:
ce111bad 136 BUG_ON(1);
030bb495
LR		 137 break;
138 }
ff37e337
S		 139}
140
141static void ath_update_txpow(struct ath_softc *sc)
142{
cbe61d8a 143 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 144 u32 txpow;
145
17d7904d
S		 146 if (sc->curtxpow != sc->config.txpowlimit) {
147 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 148 /* read back in case value is clamped */
149 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 150 sc->curtxpow = txpow;
ff37e337
S		 151 }
152}
153
154static u8 parse_mpdudensity(u8 mpdudensity)
155{
156 /*
157 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
158 * 0 for no restriction
159 * 1 for 1/4 us
160 * 2 for 1/2 us
161 * 3 for 1 us
162 * 4 for 2 us
163 * 5 for 4 us
164 * 6 for 8 us
165 * 7 for 16 us
166 */
167 switch (mpdudensity) {
168 case 0:
169 return 0;
170 case 1:
171 case 2:
172 case 3:
173 /* Our lower layer calculations limit our precision to
174 1 microsecond */
175 return 1;
176 case 4:
177 return 2;
178 case 5:
179 return 4;
180 case 6:
181 return 8;
182 case 7:
183 return 16;
184 default:
185 return 0;
186 }
187}
188
189static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
190{
4f0fc7c3 191 const struct ath_rate_table *rate_table = NULL;
ff37e337
S		 192 struct ieee80211_supported_band *sband;
193 struct ieee80211_rate *rate;
194 int i, maxrates;
195
196 switch (band) {
197 case IEEE80211_BAND_2GHZ:
198 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
199 break;
200 case IEEE80211_BAND_5GHZ:
201 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
202 break;
203 default:
204 break;
205 }
206
207 if (rate_table == NULL)
208 return;
209
210 sband = &sc->sbands[band];
211 rate = sc->rates[band];
212
213 if (rate_table->rate_cnt > ATH_RATE_MAX)
214 maxrates = ATH_RATE_MAX;
215 else
216 maxrates = rate_table->rate_cnt;
217
218 for (i = 0; i < maxrates; i++) {
219 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
220 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 221 if (rate_table->info[i].short_preamble) {
222 rate[i].hw_value_short = rate_table->info[i].ratecode |
223 rate_table->info[i].short_preamble;
224 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
225 }
ff37e337 226 sband->n_bitrates++;
f46730d1 227
4d6b228d 228 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
04bd4638 229 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 230 }
231}
232
82880a7c
VT		 233static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
234 struct ieee80211_hw *hw)
235{
236 struct ieee80211_channel *curchan = hw->conf.channel;
237 struct ath9k_channel *channel;
238 u8 chan_idx;
239
240 chan_idx = curchan->hw_value;
241 channel = &sc->sc_ah->channels[chan_idx];
242 ath9k_update_ichannel(sc, hw, channel);
243 return channel;
244}
245
ff37e337
S		 246/*
247 * Set/change channels. If the channel is really being changed, it's done
248 * by reseting the chip. To accomplish this we must first cleanup any pending
249 * DMA, then restart stuff.
250*/
0e2dedf9
JM		 251int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
252 struct ath9k_channel *hchan)
ff37e337 253{
cbe61d8a 254 struct ath_hw *ah = sc->sc_ah;
ff37e337 255 bool fastcc = true, stopped;
ae8d2858
LR		 256 struct ieee80211_channel *channel = hw->conf.channel;
257 int r;
ff37e337
S		 258
259 if (sc->sc_flags & SC_OP_INVALID)
260 return -EIO;
261
3cbb5dd7
VN		 262 ath9k_ps_wakeup(sc);
263
c0d7c7af
LR		 264 /*
265 * This is only performed if the channel settings have
266 * actually changed.
267 *
268 * To switch channels clear any pending DMA operations;
269 * wait long enough for the RX fifo to drain, reset the
270 * hardware at the new frequency, and then re-enable
271 * the relevant bits of the h/w.
272 */
273 ath9k_hw_set_interrupts(ah, 0);
043a0405 274 ath_drain_all_txq(sc, false);
c0d7c7af 275 stopped = ath_stoprecv(sc);
ff37e337 276
c0d7c7af
LR		 277 /* XXX: do not flush receive queue here. We don't want
278 * to flush data frames already in queue because of
279 * changing channel. */
ff37e337 280
c0d7c7af
LR		 281 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
282 fastcc = false;
283
4d6b228d 284 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
c0d7c7af 285 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 286 sc->sc_ah->curchan->channel,
c0d7c7af 287 channel->center_freq, sc->tx_chan_width);
ff37e337 288
c0d7c7af
LR		 289 spin_lock_bh(&sc->sc_resetlock);
290
291 r = ath9k_hw_reset(ah, hchan, fastcc);
292 if (r) {
4d6b228d 293 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
c0d7c7af 294 "Unable to reset channel (%u Mhz) "
6b45784f 295 "reset status %d\n",
c0d7c7af
LR		 296 channel->center_freq, r);
297 spin_unlock_bh(&sc->sc_resetlock);
3989279c 298 goto ps_restore;
ff37e337 299 }
c0d7c7af
LR		 300 spin_unlock_bh(&sc->sc_resetlock);
301
c0d7c7af
LR		 302 sc->sc_flags &= ~SC_OP_FULL_RESET;
303
304 if (ath_startrecv(sc) != 0) {
4d6b228d 305 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
c0d7c7af 306 "Unable to restart recv logic\n");
3989279c
GJ		 307 r = -EIO;
308 goto ps_restore;
c0d7c7af
LR		 309 }
310
311 ath_cache_conf_rate(sc, &hw->conf);
312 ath_update_txpow(sc);
17d7904d 313 ath9k_hw_set_interrupts(ah, sc->imask);
3989279c
GJ		 314
315 ps_restore:
3cbb5dd7 316 ath9k_ps_restore(sc);
3989279c 317 return r;
ff37e337
S		 318}
319
320/*
321 * This routine performs the periodic noise floor calibration function
322 * that is used to adjust and optimize the chip performance. This
323 * takes environmental changes (location, temperature) into account.
324 * When the task is complete, it reschedules itself depending on the
325 * appropriate interval that was calculated.
326 */
327static void ath_ani_calibrate(unsigned long data)
328{
20977d3e
S		 329 struct ath_softc *sc = (struct ath_softc *)data;
330 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 331 bool longcal = false;
332 bool shortcal = false;
333 bool aniflag = false;
334 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 335 u32 cal_interval, short_cal_interval;
ff37e337 336
20977d3e
S		 337 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
338 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 339
340 /*
341 * don't calibrate when we're scanning.
342 * we are most likely not on our home channel.
343 */
e5f0921a 344 spin_lock(&sc->ani_lock);
0c98de65 345 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 346 goto set_timer;
ff37e337 347
1ffc1c61
JM		 348 /* Only calibrate if awake */
349 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
350 goto set_timer;
351
352 ath9k_ps_wakeup(sc);
353
ff37e337 354 /* Long calibration runs independently of short calibration. */
17d7904d 355 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 356 longcal = true;
4d6b228d 357 DPRINTF(sc->sc_ah, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 358 sc->ani.longcal_timer = timestamp;
ff37e337
S		 359 }
360
17d7904d
S		 361 /* Short calibration applies only while caldone is false */
362 if (!sc->ani.caldone) {
20977d3e 363 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 364 shortcal = true;
4d6b228d 365 DPRINTF(sc->sc_ah, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 366 sc->ani.shortcal_timer = timestamp;
367 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 368 }
369 } else {
17d7904d 370 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 371 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 372 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
373 if (sc->ani.caldone)
374 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 375 }
376 }
377
378 /* Verify whether we must check ANI */
20977d3e 379 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 380 aniflag = true;
17d7904d 381 sc->ani.checkani_timer = timestamp;
ff37e337
S		 382 }
383
384 /* Skip all processing if there's nothing to do. */
385 if (longcal || shortcal || aniflag) {
386 /* Call ANI routine if necessary */
387 if (aniflag)
22e66a4c 388 ath9k_hw_ani_monitor(ah, ah->curchan);
ff37e337
S		 389
390 /* Perform calibration if necessary */
391 if (longcal || shortcal) {
379f0440
S		 392 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
393 sc->rx_chainmask, longcal);
394
395 if (longcal)
396 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
397 ah->curchan);
398
4d6b228d 399 DPRINTF(sc->sc_ah, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
379f0440
S		 400 ah->curchan->channel, ah->curchan->channelFlags,
401 sc->ani.noise_floor);
ff37e337
S		 402 }
403 }
404
1ffc1c61
JM		 405 ath9k_ps_restore(sc);
406
20977d3e 407set_timer:
e5f0921a 408 spin_unlock(&sc->ani_lock);
ff37e337
S		 409 /*
410 * Set timer interval based on previous results.
411 * The interval must be the shortest necessary to satisfy ANI,
412 * short calibration and long calibration.
413 */
aac9207e 414 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 415 if (sc->sc_ah->config.enable_ani)
aac9207e 416 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 417 if (!sc->ani.caldone)
20977d3e 418 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 419
17d7904d 420 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 421}
422
415f738e
S		 423static void ath_start_ani(struct ath_softc *sc)
424{
425 unsigned long timestamp = jiffies_to_msecs(jiffies);
426
427 sc->ani.longcal_timer = timestamp;
428 sc->ani.shortcal_timer = timestamp;
429 sc->ani.checkani_timer = timestamp;
430
431 mod_timer(&sc->ani.timer,
432 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
433}
434
ff37e337
S		 435/*
436 * Update tx/rx chainmask. For legacy association,
437 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 438 * the chainmask configuration, for bt coexistence, use
439 * the chainmask configuration even in legacy mode.
ff37e337 440 */
0e2dedf9 441void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 442{
af03abec
LR		 443 struct ath_hw *ah = sc->sc_ah;
444
3d832611 445 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
766ec4a9 446 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
2660b81a
S		 447 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
448 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 449 } else {
17d7904d
S		 450 sc->tx_chainmask = 1;
451 sc->rx_chainmask = 1;
ff37e337
S		 452 }
453
af03abec 454 DPRINTF(ah, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 455 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 456}
457
458static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
459{
460 struct ath_node *an;
461
462 an = (struct ath_node *)sta->drv_priv;
463
87792efc 464 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 465 ath_tx_node_init(sc, an);
9e98ac65 466 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S		 467 sta->ht_cap.ampdu_factor);
468 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
a59b5a5e 469 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
87792efc 470 }
ff37e337
S		 471}
472
473static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
474{
475 struct ath_node *an = (struct ath_node *)sta->drv_priv;
476
477 if (sc->sc_flags & SC_OP_TXAGGR)
478 ath_tx_node_cleanup(sc, an);
479}
480
481static void ath9k_tasklet(unsigned long data)
482{
483 struct ath_softc *sc = (struct ath_softc *)data;
af03abec
LR		 484 struct ath_hw *ah = sc->sc_ah;
485
17d7904d 486 u32 status = sc->intrstatus;
ff37e337 487
153e080d
VT		 488 ath9k_ps_wakeup(sc);
489
ff37e337 490 if (status & ATH9K_INT_FATAL) {
ff37e337 491 ath_reset(sc, false);
153e080d 492 ath9k_ps_restore(sc);
ff37e337 493 return;
063d8be3 494 }
ff37e337 495
063d8be3
S		 496 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
497 spin_lock_bh(&sc->rx.rxflushlock);
498 ath_rx_tasklet(sc, 0);
499 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 500 }
501
063d8be3
S		 502 if (status & ATH9K_INT_TX)
503 ath_tx_tasklet(sc);
504
96148326 505 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM		 506 /*
507 * TSF sync does not look correct; remain awake to sync with
508 * the next Beacon.
509 */
af03abec 510 DPRINTF(ah, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
ccdfeab6 511 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
54ce846e
JM		 512 }
513
766ec4a9 514 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT		 515 if (status & ATH9K_INT_GENTIMER)
516 ath_gen_timer_isr(sc->sc_ah);
517
ff37e337 518 /* re-enable hardware interrupt */
af03abec 519 ath9k_hw_set_interrupts(ah, sc->imask);
153e080d 520 ath9k_ps_restore(sc);
ff37e337
S		 521}
522
6baff7f9 523irqreturn_t ath_isr(int irq, void *dev)
ff37e337 524{
063d8be3
S		 525#define SCHED_INTR ( \
526 ATH9K_INT_FATAL | \
527 ATH9K_INT_RXORN | \
528 ATH9K_INT_RXEOL | \
529 ATH9K_INT_RX | \
530 ATH9K_INT_TX | \
531 ATH9K_INT_BMISS | \
532 ATH9K_INT_CST | \
ebb8e1d7
VT		 533 ATH9K_INT_TSFOOR | \
534 ATH9K_INT_GENTIMER)
063d8be3 535
ff37e337 536 struct ath_softc *sc = dev;
cbe61d8a 537 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 538 enum ath9k_int status;
539 bool sched = false;
540
063d8be3
S		 541 /*
542 * The hardware is not ready/present, don't
543 * touch anything. Note this can happen early
544 * on if the IRQ is shared.
545 */
546 if (sc->sc_flags & SC_OP_INVALID)
547 return IRQ_NONE;
ff37e337 548
063d8be3
S		 549
550 /* shared irq, not for us */
551
153e080d 552 if (!ath9k_hw_intrpend(ah))
063d8be3 553 return IRQ_NONE;
063d8be3
S		 554
555 /*
556 * Figure out the reason(s) for the interrupt. Note
557 * that the hal returns a pseudo-ISR that may include
558 * bits we haven't explicitly enabled so we mask the
559 * value to insure we only process bits we requested.
560 */
561 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
562 status &= sc->imask; /* discard unasked-for bits */
ff37e337 563
063d8be3
S		 564 /*
565 * If there are no status bits set, then this interrupt was not
566 * for me (should have been caught above).
567 */
153e080d 568 if (!status)
063d8be3 569 return IRQ_NONE;
ff37e337 570
063d8be3
S		 571 /* Cache the status */
572 sc->intrstatus = status;
573
574 if (status & SCHED_INTR)
575 sched = true;
576
577 /*
578 * If a FATAL or RXORN interrupt is received, we have to reset the
579 * chip immediately.
580 */
581 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
582 goto chip_reset;
583
584 if (status & ATH9K_INT_SWBA)
585 tasklet_schedule(&sc->bcon_tasklet);
586
587 if (status & ATH9K_INT_TXURN)
588 ath9k_hw_updatetxtriglevel(ah, true);
589
590 if (status & ATH9K_INT_MIB) {
ff37e337 591 /*
063d8be3
S		 592 * Disable interrupts until we service the MIB
593 * interrupt; otherwise it will continue to
594 * fire.
ff37e337 595 */
063d8be3
S		 596 ath9k_hw_set_interrupts(ah, 0);
597 /*
598 * Let the hal handle the event. We assume
599 * it will clear whatever condition caused
600 * the interrupt.
601 */
22e66a4c 602 ath9k_hw_procmibevent(ah);
063d8be3
S		 603 ath9k_hw_set_interrupts(ah, sc->imask);
604 }
ff37e337 605
153e080d
VT		 606 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
607 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S		 608 /* Clear RxAbort bit so that we can
609 * receive frames */
610 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
153e080d 611 ath9k_hw_setrxabort(sc->sc_ah, 0);
063d8be3 612 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 613 }
063d8be3
S		 614
615chip_reset:
ff37e337 616
817e11de
S		 617 ath_debug_stat_interrupt(sc, status);
618
ff37e337
S		 619 if (sched) {
620 /* turn off every interrupt except SWBA */
17d7904d 621 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 622 tasklet_schedule(&sc->intr_tq);
623 }
624
625 return IRQ_HANDLED;
063d8be3
S		 626
627#undef SCHED_INTR
ff37e337
S		 628}
629
f078f209 630static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 631 struct ieee80211_channel *chan,
094d05dc 632 enum nl80211_channel_type channel_type)
f078f209
LR		 633{
634 u32 chanmode = 0;
f078f209
LR		 635
636 switch (chan->band) {
637 case IEEE80211_BAND_2GHZ:
094d05dc
S		 638 switch(channel_type) {
639 case NL80211_CHAN_NO_HT:
640 case NL80211_CHAN_HT20:
f078f209 641 chanmode = CHANNEL_G_HT20;
094d05dc
S		 642 break;
643 case NL80211_CHAN_HT40PLUS:
f078f209 644 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 645 break;
646 case NL80211_CHAN_HT40MINUS:
f078f209 647 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 648 break;
649 }
f078f209
LR		 650 break;
651 case IEEE80211_BAND_5GHZ:
094d05dc
S		 652 switch(channel_type) {
653 case NL80211_CHAN_NO_HT:
654 case NL80211_CHAN_HT20:
f078f209 655 chanmode = CHANNEL_A_HT20;
094d05dc
S		 656 break;
657 case NL80211_CHAN_HT40PLUS:
f078f209 658 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 659 break;
660 case NL80211_CHAN_HT40MINUS:
f078f209 661 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 662 break;
663 }
f078f209
LR		 664 break;
665 default:
666 break;
667 }
668
669 return chanmode;
670}
671
6ace2891 672static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 673 struct ath9k_keyval *hk, const u8 *addr,
674 bool authenticator)
f078f209 675{
6ace2891
JM		 676 const u8 *key_rxmic;
677 const u8 *key_txmic;
f078f209 678
6ace2891
JM		 679 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
680 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 681
682 if (addr == NULL) {
d216aaa6
JM		 683 /*
684 * Group key installation - only two key cache entries are used
685 * regardless of splitmic capability since group key is only
686 * used either for TX or RX.
687 */
3f53dd64
JM		 688 if (authenticator) {
689 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
690 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
691 } else {
692 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
693 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
694 }
d216aaa6 695 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 696 }
17d7904d 697 if (!sc->splitmic) {
d216aaa6 698 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 699 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
700 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 701 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 702 }
d216aaa6
JM		 703
704 /* Separate key cache entries for TX and RX */
705
706 /* TX key goes at first index, RX key at +32. */
f078f209 707 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 708 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
709 /* TX MIC entry failed. No need to proceed further */
4d6b228d 710 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
04bd4638 711 "Setting TX MIC Key Failed\n");
f078f209
LR		 712 return 0;
713 }
714
715 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
716 /* XXX delete tx key on failure? */
d216aaa6 717 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 718}
719
720static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
721{
722 int i;
723
17d7904d
S		 724 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
725 if (test_bit(i, sc->keymap) ||
726 test_bit(i + 64, sc->keymap))
6ace2891 727 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 728 if (sc->splitmic &&
729 (test_bit(i + 32, sc->keymap) ||
730 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 731 continue; /* At least one part of TKIP key allocated */
732
733 /* Found a free slot for a TKIP key */
734 return i;
735 }
736 return -1;
737}
738
739static int ath_reserve_key_cache_slot(struct ath_softc *sc)
740{
741 int i;
742
743 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 744 if (sc->splitmic) {
745 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
746 if (!test_bit(i, sc->keymap) &&
747 (test_bit(i + 32, sc->keymap) ||
748 test_bit(i + 64, sc->keymap) ||
749 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 750 return i;
17d7904d
S		 751 if (!test_bit(i + 32, sc->keymap) &&
752 (test_bit(i, sc->keymap) ||
753 test_bit(i + 64, sc->keymap) ||
754 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 755 return i + 32;
17d7904d
S		 756 if (!test_bit(i + 64, sc->keymap) &&
757 (test_bit(i , sc->keymap) ||
758 test_bit(i + 32, sc->keymap) ||
759 test_bit(i + 64 + 32, sc->keymap)))
ea612132 760 return i + 64;
17d7904d
S		 761 if (!test_bit(i + 64 + 32, sc->keymap) &&
762 (test_bit(i, sc->keymap) ||
763 test_bit(i + 32, sc->keymap) ||
764 test_bit(i + 64, sc->keymap)))
ea612132 765 return i + 64 + 32;
6ace2891
JM		 766 }
767 } else {
17d7904d
S		 768 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
769 if (!test_bit(i, sc->keymap) &&
770 test_bit(i + 64, sc->keymap))
6ace2891 771 return i;
17d7904d
S		 772 if (test_bit(i, sc->keymap) &&
773 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 774 return i + 64;
775 }
776 }
777
778 /* No partially used TKIP slots, pick any available slot */
17d7904d 779 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 780 /* Do not allow slots that could be needed for TKIP group keys
781 * to be used. This limitation could be removed if we know that
782 * TKIP will not be used. */
783 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
784 continue;
17d7904d 785 if (sc->splitmic) {
be2864cf
JM		 786 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
787 continue;
788 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
789 continue;
790 }
791
17d7904d 792 if (!test_bit(i, sc->keymap))
6ace2891
JM		 793 return i; /* Found a free slot for a key */
794 }
795
796 /* No free slot found */
797 return -1;
f078f209
LR		 798}
799
800static int ath_key_config(struct ath_softc *sc,
3f53dd64 801 struct ieee80211_vif *vif,
dc822b5d 802 struct ieee80211_sta *sta,
f078f209
LR		 803 struct ieee80211_key_conf *key)
804{
f078f209
LR		 805 struct ath9k_keyval hk;
806 const u8 *mac = NULL;
807 int ret = 0;
6ace2891 808 int idx;
f078f209
LR		 809
810 memset(&hk, 0, sizeof(hk));
811
812 switch (key->alg) {
813 case ALG_WEP:
814 hk.kv_type = ATH9K_CIPHER_WEP;
815 break;
816 case ALG_TKIP:
817 hk.kv_type = ATH9K_CIPHER_TKIP;
818 break;
819 case ALG_CCMP:
820 hk.kv_type = ATH9K_CIPHER_AES_CCM;
821 break;
822 default:
ca470b29 823 return -EOPNOTSUPP;
f078f209
LR		 824 }
825
6ace2891 826 hk.kv_len = key->keylen;
f078f209
LR		 827 memcpy(hk.kv_val, key->key, key->keylen);
828
6ace2891
JM		 829 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
830 /* For now, use the default keys for broadcast keys. This may
831 * need to change with virtual interfaces. */
832 idx = key->keyidx;
833 } else if (key->keyidx) {
dc822b5d
JB		 834 if (WARN_ON(!sta))
835 return -EOPNOTSUPP;
836 mac = sta->addr;
837
6ace2891
JM		 838 if (vif->type != NL80211_IFTYPE_AP) {
839 /* Only keyidx 0 should be used with unicast key, but
840 * allow this for client mode for now. */
841 idx = key->keyidx;
842 } else
843 return -EIO;
f078f209 844 } else {
dc822b5d
JB		 845 if (WARN_ON(!sta))
846 return -EOPNOTSUPP;
847 mac = sta->addr;
848
6ace2891
JM		 849 if (key->alg == ALG_TKIP)
850 idx = ath_reserve_key_cache_slot_tkip(sc);
851 else
852 idx = ath_reserve_key_cache_slot(sc);
853 if (idx < 0)
ca470b29 854 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 855 }
856
857 if (key->alg == ALG_TKIP)
3f53dd64
JM		 858 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
859 vif->type == NL80211_IFTYPE_AP);
f078f209 860 else
d216aaa6 861 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 862
863 if (!ret)
864 return -EIO;
865
17d7904d 866 set_bit(idx, sc->keymap);
6ace2891 867 if (key->alg == ALG_TKIP) {
17d7904d
S		 868 set_bit(idx + 64, sc->keymap);
869 if (sc->splitmic) {
870 set_bit(idx + 32, sc->keymap);
871 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 872 }
873 }
874
875 return idx;
f078f209
LR		 876}
877
878static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
879{
6ace2891
JM		 880 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
881 if (key->hw_key_idx < IEEE80211_WEP_NKID)
882 return;
883
17d7904d 884 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 885 if (key->alg != ALG_TKIP)
886 return;
f078f209 887
17d7904d
S		 888 clear_bit(key->hw_key_idx + 64, sc->keymap);
889 if (sc->splitmic) {
890 clear_bit(key->hw_key_idx + 32, sc->keymap);
891 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 892 }
f078f209
LR		 893}
894
eb2599ca
S		 895static void setup_ht_cap(struct ath_softc *sc,
896 struct ieee80211_sta_ht_cap *ht_info)
f078f209 897{
140add21 898 u8 tx_streams, rx_streams;
f078f209 899
d9fe60de
JB		 900 ht_info->ht_supported = true;
901 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
902 IEEE80211_HT_CAP_SM_PS |
903 IEEE80211_HT_CAP_SGI_40 |
904 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 905
9e98ac65
S		 906 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
907 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
eb2599ca 908
d9fe60de
JB		 909 /* set up supported mcs set */
910 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
140add21
SB		 911 tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
912 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
913
914 if (tx_streams != rx_streams) {
4d6b228d 915 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
140add21
SB		 916 tx_streams, rx_streams);
917 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
918 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
919 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
920 }
eb2599ca 921
140add21
SB		 922 ht_info->mcs.rx_mask[0] = 0xff;
923 if (rx_streams >= 2)
eb2599ca 924 ht_info->mcs.rx_mask[1] = 0xff;
eb2599ca 925
140add21 926 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 927}
928
8feceb67 929static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 930 struct ieee80211_vif *vif,
8feceb67 931 struct ieee80211_bss_conf *bss_conf)
f078f209 932{
f078f209 933
8feceb67 934 if (bss_conf->assoc) {
4d6b228d 935 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 936 bss_conf->aid, sc->curbssid);
f078f209 937
8feceb67 938 /* New association, store aid */
2664f201
SB		 939 sc->curaid = bss_conf->aid;
940 ath9k_hw_write_associd(sc);
941
942 /*
943 * Request a re-configuration of Beacon related timers
944 * on the receipt of the first Beacon frame (i.e.,
945 * after time sync with the AP).
946 */
947 sc->sc_flags |= SC_OP_BEACON_SYNC;
f078f209 948
8feceb67 949 /* Configure the beacon */
2c3db3d5 950 ath_beacon_config(sc, vif);
f078f209 951
8feceb67 952 /* Reset rssi stats */
22e66a4c 953 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 954
415f738e 955 ath_start_ani(sc);
8feceb67 956 } else {
4d6b228d 957 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
17d7904d 958 sc->curaid = 0;
f38faa31
SB		 959 /* Stop ANI */
960 del_timer_sync(&sc->ani.timer);
f078f209 961 }
8feceb67 962}
f078f209 963
8feceb67
VT		 964/********************************/
965/* LED functions */
966/********************************/
f078f209 967
f2bffa7e
VT		 968static void ath_led_blink_work(struct work_struct *work)
969{
970 struct ath_softc *sc = container_of(work, struct ath_softc,
971 ath_led_blink_work.work);
972
973 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
974 return;
85067c06
VT		 975
976 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
977 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
08fc5c1b 978 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
85067c06 979 else
08fc5c1b 980 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
85067c06 981 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e 982
42935eca
LR		 983 ieee80211_queue_delayed_work(sc->hw,
984 &sc->ath_led_blink_work,
985 (sc->sc_flags & SC_OP_LED_ON) ?
986 msecs_to_jiffies(sc->led_off_duration) :
987 msecs_to_jiffies(sc->led_on_duration));
f2bffa7e 988
85067c06
VT		 989 sc->led_on_duration = sc->led_on_cnt ?
990 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
991 ATH_LED_ON_DURATION_IDLE;
992 sc->led_off_duration = sc->led_off_cnt ?
993 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
994 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 995 sc->led_on_cnt = sc->led_off_cnt = 0;
996 if (sc->sc_flags & SC_OP_LED_ON)
997 sc->sc_flags &= ~SC_OP_LED_ON;
998 else
999 sc->sc_flags |= SC_OP_LED_ON;
1000}
1001
8feceb67
VT		 1002static void ath_led_brightness(struct led_classdev *led_cdev,
1003 enum led_brightness brightness)
1004{
1005 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1006 struct ath_softc *sc = led->sc;
f078f209 1007
8feceb67
VT		 1008 switch (brightness) {
1009 case LED_OFF:
1010 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e 1011 led->led_type == ATH_LED_RADIO) {
08fc5c1b 1012 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
f2bffa7e 1013 (led->led_type == ATH_LED_RADIO));
8feceb67 1014 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1015 if (led->led_type == ATH_LED_RADIO)
1016 sc->sc_flags &= ~SC_OP_LED_ON;
1017 } else {
1018 sc->led_off_cnt++;
1019 }
8feceb67
VT		 1020 break;
1021 case LED_FULL:
f2bffa7e 1022 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 1023 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
42935eca
LR		 1024 ieee80211_queue_delayed_work(sc->hw,
1025 &sc->ath_led_blink_work, 0);
f2bffa7e 1026 } else if (led->led_type == ATH_LED_RADIO) {
08fc5c1b 1027 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
f2bffa7e
VT		 1028 sc->sc_flags |= SC_OP_LED_ON;
1029 } else {
1030 sc->led_on_cnt++;
1031 }
8feceb67
VT		 1032 break;
1033 default:
1034 break;
f078f209 1035 }
8feceb67 1036}
f078f209 1037
8feceb67
VT		 1038static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1039 char *trigger)
1040{
1041 int ret;
f078f209 1042
8feceb67
VT		 1043 led->sc = sc;
1044 led->led_cdev.name = led->name;
1045 led->led_cdev.default_trigger = trigger;
1046 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1047
8feceb67
VT		 1048 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1049 if (ret)
4d6b228d 1050 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
8feceb67
VT		 1051 "Failed to register led:%s", led->name);
1052 else
1053 led->registered = 1;
1054 return ret;
1055}
f078f209 1056
8feceb67
VT		 1057static void ath_unregister_led(struct ath_led *led)
1058{
1059 if (led->registered) {
1060 led_classdev_unregister(&led->led_cdev);
1061 led->registered = 0;
f078f209 1062 }
f078f209
LR		 1063}
1064
8feceb67 1065static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1066{
8feceb67
VT		 1067 ath_unregister_led(&sc->assoc_led);
1068 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1069 ath_unregister_led(&sc->tx_led);
1070 ath_unregister_led(&sc->rx_led);
1071 ath_unregister_led(&sc->radio_led);
08fc5c1b 1072 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
8feceb67 1073}
f078f209 1074
8feceb67
VT		 1075static void ath_init_leds(struct ath_softc *sc)
1076{
1077 char *trigger;
1078 int ret;
f078f209 1079
08fc5c1b
VN		 1080 if (AR_SREV_9287(sc->sc_ah))
1081 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1082 else
1083 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1084
8feceb67 1085 /* Configure gpio 1 for output */
08fc5c1b 1086 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
8feceb67
VT		 1087 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1088 /* LED off, active low */
08fc5c1b 1089 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
7dcfdcd9 1090
f2bffa7e
VT		 1091 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1092
8feceb67
VT		 1093 trigger = ieee80211_get_radio_led_name(sc->hw);
1094 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1095 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1096 ret = ath_register_led(sc, &sc->radio_led, trigger);
1097 sc->radio_led.led_type = ATH_LED_RADIO;
1098 if (ret)
1099 goto fail;
7dcfdcd9 1100
8feceb67
VT		 1101 trigger = ieee80211_get_assoc_led_name(sc->hw);
1102 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1103 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1104 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1105 sc->assoc_led.led_type = ATH_LED_ASSOC;
1106 if (ret)
1107 goto fail;
f078f209 1108
8feceb67
VT		 1109 trigger = ieee80211_get_tx_led_name(sc->hw);
1110 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1111 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1112 ret = ath_register_led(sc, &sc->tx_led, trigger);
1113 sc->tx_led.led_type = ATH_LED_TX;
1114 if (ret)
1115 goto fail;
f078f209 1116
8feceb67
VT		 1117 trigger = ieee80211_get_rx_led_name(sc->hw);
1118 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1119 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1120 ret = ath_register_led(sc, &sc->rx_led, trigger);
1121 sc->rx_led.led_type = ATH_LED_RX;
1122 if (ret)
1123 goto fail;
f078f209 1124
8feceb67
VT		 1125 return;
1126
1127fail:
35c95ab9 1128 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67 1129 ath_deinit_leds(sc);
f078f209
LR		 1130}
1131
7ec3e514 1132void ath_radio_enable(struct ath_softc *sc)
500c064d 1133{
cbe61d8a 1134 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1135 struct ieee80211_channel *channel = sc->hw->conf.channel;
1136 int r;
500c064d 1137
3cbb5dd7 1138 ath9k_ps_wakeup(sc);
93b1b37f 1139 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 1140
159cd468
VT		 1141 if (!ah->curchan)
1142 ah->curchan = ath_get_curchannel(sc, sc->hw);
1143
d2f5b3a6 1144 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1145 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1146 if (r) {
4d6b228d 1147 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
ae8d2858 1148 "Unable to reset channel %u (%uMhz) ",
6b45784f 1149 "reset status %d\n",
ae8d2858 1150 channel->center_freq, r);
500c064d
VT		 1151 }
1152 spin_unlock_bh(&sc->sc_resetlock);
1153
1154 ath_update_txpow(sc);
1155 if (ath_startrecv(sc) != 0) {
4d6b228d 1156 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
04bd4638 1157 "Unable to restart recv logic\n");
500c064d
VT		 1158 return;
1159 }
1160
1161 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1162 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1163
1164 /* Re-Enable interrupts */
17d7904d 1165 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1166
1167 /* Enable LED */
08fc5c1b 1168 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 1169 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 1170 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d
VT		 1171
1172 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1173 ath9k_ps_restore(sc);
500c064d
VT		 1174}
1175
7ec3e514 1176void ath_radio_disable(struct ath_softc *sc)
500c064d 1177{
cbe61d8a 1178 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1179 struct ieee80211_channel *channel = sc->hw->conf.channel;
1180 int r;
500c064d 1181
3cbb5dd7 1182 ath9k_ps_wakeup(sc);
500c064d
VT		 1183 ieee80211_stop_queues(sc->hw);
1184
1185 /* Disable LED */
08fc5c1b
VN		 1186 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1187 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
500c064d
VT		 1188
1189 /* Disable interrupts */
1190 ath9k_hw_set_interrupts(ah, 0);
1191
043a0405 1192 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1193 ath_stoprecv(sc); /* turn off frame recv */
1194 ath_flushrecv(sc); /* flush recv queue */
1195
159cd468
VT		 1196 if (!ah->curchan)
1197 ah->curchan = ath_get_curchannel(sc, sc->hw);
1198
500c064d 1199 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1200 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1201 if (r) {
4d6b228d 1202 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
04bd4638 1203 "Unable to reset channel %u (%uMhz) "
6b45784f 1204 "reset status %d\n",
ae8d2858 1205 channel->center_freq, r);
500c064d
VT		 1206 }
1207 spin_unlock_bh(&sc->sc_resetlock);
1208
1209 ath9k_hw_phy_disable(ah);
93b1b37f 1210 ath9k_hw_configpcipowersave(ah, 1, 1);
3cbb5dd7 1211 ath9k_ps_restore(sc);
38ab422e 1212 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
500c064d
VT		 1213}
1214
5077fd35
GJ		 1215/*******************/
1216/* Rfkill */
1217/*******************/
1218
500c064d
VT		 1219static bool ath_is_rfkill_set(struct ath_softc *sc)
1220{
cbe61d8a 1221 struct ath_hw *ah = sc->sc_ah;
500c064d 1222
2660b81a
S		 1223 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1224 ah->rfkill_polarity;
500c064d
VT		 1225}
1226
3b319aae 1227static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
500c064d 1228{
3b319aae
JB		 1229 struct ath_wiphy *aphy = hw->priv;
1230 struct ath_softc *sc = aphy->sc;
19d337df 1231 bool blocked = !!ath_is_rfkill_set(sc);
500c064d 1232
3b319aae 1233 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
500c064d
VT		 1234}
1235
3b319aae 1236static void ath_start_rfkill_poll(struct ath_softc *sc)
500c064d 1237{
3b319aae 1238 struct ath_hw *ah = sc->sc_ah;
9c84b797 1239
3b319aae
JB		 1240 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1241 wiphy_rfkill_start_polling(sc->hw->wiphy);
9c84b797 1242}
500c064d 1243
6baff7f9 1244void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1245{
1246 ath_detach(sc);
1247 free_irq(sc->irq, sc);
1248 ath_bus_cleanup(sc);
c52f33d0 1249 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1250 ieee80211_free_hw(sc->hw);
1251}
1252
6baff7f9 1253void ath_detach(struct ath_softc *sc)
f078f209 1254{
8feceb67 1255 struct ieee80211_hw *hw = sc->hw;
4d6b228d 1256 struct ath_hw *ah = sc->sc_ah;
9c84b797 1257 int i = 0;
f078f209 1258
3cbb5dd7
VN		 1259 ath9k_ps_wakeup(sc);
1260
4d6b228d 1261 dev_dbg(sc->dev, "Detach ATH hw\n");
f078f209 1262
35c95ab9 1263 ath_deinit_leds(sc);
e31f7b96 1264 wiphy_rfkill_stop_polling(sc->hw->wiphy);
35c95ab9 1265
c52f33d0
JM		 1266 for (i = 0; i < sc->num_sec_wiphy; i++) {
1267 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1268 if (aphy == NULL)
1269 continue;
1270 sc->sec_wiphy[i] = NULL;
1271 ieee80211_unregister_hw(aphy->hw);
1272 ieee80211_free_hw(aphy->hw);
1273 }
3fcdfb4b 1274 ieee80211_unregister_hw(hw);
8feceb67
VT		 1275 ath_rx_cleanup(sc);
1276 ath_tx_cleanup(sc);
f078f209 1277
9c84b797
S		 1278 tasklet_kill(&sc->intr_tq);
1279 tasklet_kill(&sc->bcon_tasklet);
f078f209 1280
9c84b797 1281 if (!(sc->sc_flags & SC_OP_INVALID))
4d6b228d 1282 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
8feceb67 1283
9c84b797
S		 1284 /* cleanup tx queues */
1285 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1286 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1287 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797 1288
75d7839f 1289 if ((sc->btcoex.no_stomp_timer) &&
766ec4a9 1290 ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1291 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
1773912b 1292
4d6b228d 1293 ath9k_hw_detach(ah);
af03abec 1294 ath9k_exit_debug(ah);
3ce1b1a9 1295 sc->sc_ah = NULL;
f078f209
LR		 1296}
1297
e3bb249b
BC		 1298static int ath9k_reg_notifier(struct wiphy *wiphy,
1299 struct regulatory_request *request)
1300{
1301 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1302 struct ath_wiphy *aphy = hw->priv;
1303 struct ath_softc *sc = aphy->sc;
608b88cb 1304 struct ath_regulatory *reg = &sc->common.regulatory;
e3bb249b
BC		 1305
1306 return ath_reg_notifier_apply(wiphy, request, reg);
1307}
1308
75d7839f
LR		 1309/*
1310 * Detects if there is any priority bt traffic
1311 */
1312static void ath_detect_bt_priority(struct ath_softc *sc)
1313{
1314 struct ath_btcoex *btcoex = &sc->btcoex;
1315 struct ath_hw *ah = sc->sc_ah;
1316
766ec4a9 1317 if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
75d7839f
LR		 1318 btcoex->bt_priority_cnt++;
1319
1320 if (time_after(jiffies, btcoex->bt_priority_time +
1321 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1322 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
1323 DPRINTF(sc->sc_ah, ATH_DBG_BTCOEX,
1324 "BT priority traffic detected");
1325 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1326 } else {
1327 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1328 }
1329
1330 btcoex->bt_priority_cnt = 0;
1331 btcoex->bt_priority_time = jiffies;
1332 }
1333}
1334
766ec4a9 1335static void ath_btcoex_set_weight(struct ath_btcoex_hw *btcoex_hw,
75d7839f
LR		 1336 u32 bt_weight,
1337 u32 wlan_weight)
1338{
766ec4a9 1339 btcoex_hw->bt_coex_weights = SM(bt_weight, AR_BTCOEX_BT_WGHT) |
75d7839f
LR		 1340 SM(wlan_weight, AR_BTCOEX_WL_WGHT);
1341}
1342
1343static void ath9k_hw_btcoex_init_weight(struct ath_hw *ah)
1344{
766ec4a9 1345 ath_btcoex_set_weight(&ah->btcoex_hw, AR_BT_COEX_WGHT,
75d7839f
LR		 1346 AR_STOMP_LOW_WLAN_WGHT);
1347}
1348
1349/*
1350 * Configures appropriate weight based on stomp type.
1351 */
1352static void ath_btcoex_bt_stomp(struct ath_softc *sc,
766ec4a9 1353 struct ath_btcoex_hw *btcoex_hw,
75d7839f
LR		 1354 int stomp_type)
1355{
1356
1357 switch (stomp_type) {
1358 case ATH_BTCOEX_STOMP_ALL:
766ec4a9 1359 ath_btcoex_set_weight(btcoex_hw, AR_BT_COEX_WGHT,
75d7839f
LR		 1360 AR_STOMP_ALL_WLAN_WGHT);
1361 break;
1362 case ATH_BTCOEX_STOMP_LOW:
766ec4a9 1363 ath_btcoex_set_weight(btcoex_hw, AR_BT_COEX_WGHT,
75d7839f
LR		 1364 AR_STOMP_LOW_WLAN_WGHT);
1365 break;
1366 case ATH_BTCOEX_STOMP_NONE:
766ec4a9 1367 ath_btcoex_set_weight(btcoex_hw, AR_BT_COEX_WGHT,
75d7839f
LR		 1368 AR_STOMP_NONE_WLAN_WGHT);
1369 break;
1370 default:
1371 DPRINTF(sc->sc_ah, ATH_DBG_BTCOEX, "Invalid Stomptype\n");
1372 break;
1373 }
1374
1375 ath9k_hw_btcoex_enable(sc->sc_ah);
1376}
1377
1378/*
1379 * This is the master bt coex timer which runs for every
1380 * 45ms, bt traffic will be given priority during 55% of this
1381 * period while wlan gets remaining 45%
1382 */
1383static void ath_btcoex_period_timer(unsigned long data)
1384{
1385 struct ath_softc *sc = (struct ath_softc *) data;
1386 struct ath_hw *ah = sc->sc_ah;
1387 struct ath_btcoex *btcoex = &sc->btcoex;
766ec4a9 1388 struct ath_btcoex_hw *btcoex_hw= &ah->btcoex_hw;
75d7839f
LR		 1389
1390 ath_detect_bt_priority(sc);
1391
1392 spin_lock_bh(&btcoex->btcoex_lock);
1393
766ec4a9 1394 ath_btcoex_bt_stomp(sc, btcoex_hw, btcoex->bt_stomp_type);
75d7839f
LR		 1395
1396 spin_unlock_bh(&btcoex->btcoex_lock);
1397
1398 if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1399 if (btcoex->hw_timer_enabled)
1400 ath_gen_timer_stop(ah, btcoex->no_stomp_timer);
1401
1402 ath_gen_timer_start(ah,
1403 btcoex->no_stomp_timer,
1404 (ath9k_hw_gettsf32(ah) +
1405 btcoex->btcoex_no_stomp),
1406 btcoex->btcoex_no_stomp * 10);
1407 btcoex->hw_timer_enabled = true;
1408 }
1409
1410 mod_timer(&btcoex->period_timer, jiffies +
1411 msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1412}
1413
1414/*
1415 * Generic tsf based hw timer which configures weight
1416 * registers to time slice between wlan and bt traffic
1417 */
1418static void ath_btcoex_no_stomp_timer(void *arg)
1419{
1420 struct ath_softc *sc = (struct ath_softc *)arg;
1421 struct ath_hw *ah = sc->sc_ah;
1422 struct ath_btcoex *btcoex = &sc->btcoex;
766ec4a9 1423 struct ath_btcoex_hw *btcoex_hw= &ah->btcoex_hw;
75d7839f
LR		 1424
1425 DPRINTF(ah, ATH_DBG_BTCOEX, "no stomp timer running \n");
1426
1427 spin_lock_bh(&btcoex->btcoex_lock);
1428
e08a6ace 1429 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
766ec4a9 1430 ath_btcoex_bt_stomp(sc, btcoex_hw, ATH_BTCOEX_STOMP_NONE);
e08a6ace 1431 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
766ec4a9 1432 ath_btcoex_bt_stomp(sc, btcoex_hw, ATH_BTCOEX_STOMP_LOW);
75d7839f
LR		 1433
1434 spin_unlock_bh(&btcoex->btcoex_lock);
1435}
1436
1437static int ath_init_btcoex_timer(struct ath_softc *sc)
1438{
1439 struct ath_btcoex *btcoex = &sc->btcoex;
1440
1441 btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1442 btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1443 btcoex->btcoex_period / 100;
1444
1445 setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1446 (unsigned long) sc);
1447
1448 spin_lock_init(&btcoex->btcoex_lock);
1449
1450 btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1451 ath_btcoex_no_stomp_timer,
1452 ath_btcoex_no_stomp_timer,
1453 (void *) sc, AR_FIRST_NDP_TIMER);
1454
1455 if (!btcoex->no_stomp_timer)
1456 return -ENOMEM;
1457
1458 return 0;
1459}
1460
1e40bcfa
LR		 1461/*
1462 * Initialize and fill ath_softc, ath_sofct is the
1463 * "Software Carrier" struct. Historically it has existed
1464 * to allow the separation between hardware specific
1465 * variables (now in ath_hw) and driver specific variables.
1466 */
aeac355d 1467static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
ff37e337 1468{
cbe61d8a 1469 struct ath_hw *ah = NULL;
4f3acf81 1470 int r = 0, i;
ff37e337 1471 int csz = 0;
75d7839f 1472 int qnum;
ff37e337
S		 1473
1474 /* XXX: hardware will not be ready until ath_open() being called */
1475 sc->sc_flags |= SC_OP_INVALID;
88b126af 1476
c52f33d0 1477 spin_lock_init(&sc->wiphy_lock);
ff37e337 1478 spin_lock_init(&sc->sc_resetlock);
6158425b 1479 spin_lock_init(&sc->sc_serial_rw);
e5f0921a 1480 spin_lock_init(&sc->ani_lock);
04717ccd 1481 spin_lock_init(&sc->sc_pm_lock);
aa33de09 1482 mutex_init(&sc->mutex);
ff37e337 1483 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1484 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1485 (unsigned long)sc);
1486
1487 /*
1488 * Cache line size is used to size and align various
1489 * structures used to communicate with the hardware.
1490 */
88d15707 1491 ath_read_cachesize(sc, &csz);
ff37e337 1492 /* XXX assert csz is non-zero */
d15dd3e5 1493 sc->common.cachelsz = csz << 2; /* convert to bytes */
ff37e337 1494
4f3acf81
LR		 1495 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1496 if (!ah) {
4f3acf81
LR		 1497 r = -ENOMEM;
1498 goto bad_no_ah;
1499 }
1500
1501 ah->ah_sc = sc;
8df5d1b7 1502 ah->hw_version.devid = devid;
aeac355d 1503 ah->hw_version.subsysid = subsysid;
e1e2f93f 1504 sc->sc_ah = ah;
4f3acf81 1505
4d6b228d
LR		 1506 if (ath9k_init_debug(ah) < 0)
1507 dev_err(sc->dev, "Unable to create debugfs files\n");
1508
f637cfd6 1509 r = ath9k_hw_init(ah);
4f3acf81 1510 if (r) {
4d6b228d 1511 DPRINTF(ah, ATH_DBG_FATAL,
f637cfd6 1512 "Unable to initialize hardware; "
4f3acf81 1513 "initialization status: %d\n", r);
ff37e337
S		 1514 goto bad;
1515 }
ff37e337
S		 1516
1517 /* Get the hardware key cache size. */
2660b81a 1518 sc->keymax = ah->caps.keycache_size;
17d7904d 1519 if (sc->keymax > ATH_KEYMAX) {
4d6b228d 1520 DPRINTF(ah, ATH_DBG_ANY,
04bd4638 1521 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1522 ATH_KEYMAX, sc->keymax);
1523 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1524 }
1525
1526 /*
1527 * Reset the key cache since some parts do not
1528 * reset the contents on initial power up.
1529 */
17d7904d 1530 for (i = 0; i < sc->keymax; i++)
ff37e337 1531 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1532
ff37e337 1533 /* default to MONITOR mode */
2660b81a 1534 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1535
ff37e337
S		 1536 /* Setup rate tables */
1537
1538 ath_rate_attach(sc);
1539 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1540 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1541
1542 /*
1543 * Allocate hardware transmit queues: one queue for
1544 * beacon frames and one data queue for each QoS
1545 * priority. Note that the hal handles reseting
1546 * these queues at the needed time.
1547 */
b77f483f
S		 1548 sc->beacon.beaconq = ath_beaconq_setup(ah);
1549 if (sc->beacon.beaconq == -1) {
4d6b228d 1550 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1551 "Unable to setup a beacon xmit queue\n");
4f3acf81 1552 r = -EIO;
ff37e337
S		 1553 goto bad2;
1554 }
b77f483f
S		 1555 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1556 if (sc->beacon.cabq == NULL) {
4d6b228d 1557 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1558 "Unable to setup CAB xmit queue\n");
4f3acf81 1559 r = -EIO;
ff37e337
S		 1560 goto bad2;
1561 }
1562
17d7904d 1563 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1564 ath_cabq_update(sc);
1565
b77f483f
S		 1566 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1567 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1568
1569 /* Setup data queues */
1570 /* NB: ensure BK queue is the lowest priority h/w queue */
1571 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
4d6b228d 1572 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1573 "Unable to setup xmit queue for BK traffic\n");
4f3acf81 1574 r = -EIO;
ff37e337
S		 1575 goto bad2;
1576 }
1577
1578 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
4d6b228d 1579 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1580 "Unable to setup xmit queue for BE traffic\n");
4f3acf81 1581 r = -EIO;
ff37e337
S		 1582 goto bad2;
1583 }
1584 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
4d6b228d 1585 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1586 "Unable to setup xmit queue for VI traffic\n");
4f3acf81 1587 r = -EIO;
ff37e337
S		 1588 goto bad2;
1589 }
1590 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
4d6b228d 1591 DPRINTF(ah, ATH_DBG_FATAL,
04bd4638 1592 "Unable to setup xmit queue for VO traffic\n");
4f3acf81 1593 r = -EIO;
ff37e337
S		 1594 goto bad2;
1595 }
1596
1597 /* Initializes the noise floor to a reasonable default value.
1598 * Later on this will be updated during ANI processing. */
1599
17d7904d
S		 1600 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1601 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1602
1603 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1604 ATH9K_CIPHER_TKIP, NULL)) {
1605 /*
1606 * Whether we should enable h/w TKIP MIC.
1607 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1608 * report WMM capable, so it's always safe to turn on
1609 * TKIP MIC in this case.
1610 */
1611 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1612 0, 1, NULL);
1613 }
1614
1615 /*
1616 * Check whether the separate key cache entries
1617 * are required to handle both tx+rx MIC keys.
1618 * With split mic keys the number of stations is limited
1619 * to 27 otherwise 59.
1620 */
1621 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1622 ATH9K_CIPHER_TKIP, NULL)
1623 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1624 ATH9K_CIPHER_MIC, NULL)
1625 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1626 0, NULL))
17d7904d 1627 sc->splitmic = 1;
ff37e337
S		 1628
1629 /* turn on mcast key search if possible */
1630 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1631 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1632 1, NULL);
1633
17d7904d 1634 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1635
1636 /* 11n Capabilities */
2660b81a 1637 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1638 sc->sc_flags |= SC_OP_TXAGGR;
1639 sc->sc_flags |= SC_OP_RXAGGR;
1640 }
1641
2660b81a
S		 1642 sc->tx_chainmask = ah->caps.tx_chainmask;
1643 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1644
1645 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1646 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1647
8ca21f01 1648 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1649 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1650
b77f483f 1651 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1652
1653 /* initialize beacon slots */
c52f33d0 1654 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1655 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1656 sc->beacon.bslot_aphy[i] = NULL;
1657 }
ff37e337 1658
ff37e337
S		 1659 /* setup channels and rates */
1660
5f8e077c 1661 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1662 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1663 sc->rates[IEEE80211_BAND_2GHZ];
1664 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1665 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1666 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1667
2660b81a 1668 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1669 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1670 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1671 sc->rates[IEEE80211_BAND_5GHZ];
1672 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1673 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1674 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1675 }
1676
766ec4a9 1677 switch (ah->btcoex_hw.scheme) {
75d7839f
LR		 1678 case ATH_BTCOEX_CFG_NONE:
1679 break;
1680 case ATH_BTCOEX_CFG_2WIRE:
1681 ath9k_hw_btcoex_init_2wire(ah);
1682 break;
1683 case ATH_BTCOEX_CFG_3WIRE:
1684 ath9k_hw_btcoex_init_3wire(ah);
1685 r = ath_init_btcoex_timer(sc);
1773912b
VT		 1686 if (r)
1687 goto bad2;
75d7839f 1688 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
766ec4a9 1689 ath9k_hw_init_btcoex_hw(ah, qnum);
e08a6ace 1690 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
75d7839f
LR		 1691 break;
1692 default:
1693 WARN_ON(1);
1694 break;
1773912b 1695 }
c97c92d9 1696
ff37e337
S		 1697 return 0;
1698bad2:
1699 /* cleanup tx queues */
1700 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1701 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1702 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337 1703bad:
95fafca2 1704 ath9k_hw_detach(ah);
4f3acf81 1705bad_no_ah:
4d6b228d
LR		 1706 ath9k_exit_debug(sc->sc_ah);
1707 sc->sc_ah = NULL;
ff37e337 1708
4f3acf81 1709 return r;
ff37e337
S		 1710}
1711
c52f33d0 1712void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1713{
9c84b797
S		 1714 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1715 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1716 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1717 IEEE80211_HW_AMPDU_AGGREGATION |
1718 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1719 IEEE80211_HW_PS_NULLFUNC_STACK |
1720 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1721
b3bd89ce 1722 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1723 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1724
9c84b797
S		 1725 hw->wiphy->interface_modes =
1726 BIT(NL80211_IFTYPE_AP) |
1727 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1728 BIT(NL80211_IFTYPE_ADHOC) |
1729 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1730
8feceb67 1731 hw->queues = 4;
e63835b0 1732 hw->max_rates = 4;
171387ef 1733 hw->channel_change_time = 5000;
465ca84d 1734 hw->max_listen_interval = 10;
dd190183
LR		 1735 /* Hardware supports 10 but we use 4 */
1736 hw->max_rate_tries = 4;
528f0c6b 1737 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1738 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1739
8feceb67 1740 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1741
c52f33d0
JM		 1742 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1743 &sc->sbands[IEEE80211_BAND_2GHZ];
1744 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1745 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1746 &sc->sbands[IEEE80211_BAND_5GHZ];
1747}
1748
1e40bcfa 1749/* Device driver core initialization */
aeac355d 1750int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid)
c52f33d0
JM		 1751{
1752 struct ieee80211_hw *hw = sc->hw;
4d6b228d 1753 struct ath_hw *ah;
c52f33d0 1754 int error = 0, i;
3a702e49 1755 struct ath_regulatory *reg;
c52f33d0 1756
4d6b228d 1757 dev_dbg(sc->dev, "Attach ATH hw\n");
c52f33d0 1758
aeac355d 1759 error = ath_init_softc(devid, sc, subsysid);
c52f33d0
JM		 1760 if (error != 0)
1761 return error;
1762
4d6b228d
LR		 1763 ah = sc->sc_ah;
1764
c52f33d0
JM		 1765 /* get mac address from hardware and set in mac80211 */
1766
4d6b228d 1767 SET_IEEE80211_PERM_ADDR(hw, ah->macaddr);
c52f33d0
JM		 1768
1769 ath_set_hw_capab(sc, hw);
1770
608b88cb 1771 error = ath_regd_init(&sc->common.regulatory, sc->hw->wiphy,
c26c2e57
LR		 1772 ath9k_reg_notifier);
1773 if (error)
1774 return error;
1775
608b88cb 1776 reg = &sc->common.regulatory;
c26c2e57 1777
4d6b228d 1778 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1779 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
4d6b228d 1780 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
eb2599ca 1781 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1782 }
1783
db93e7b5
SB		 1784 /* initialize tx/rx engine */
1785 error = ath_tx_init(sc, ATH_TXBUF);
1786 if (error != 0)
40b130a9 1787 goto error_attach;
8feceb67 1788
db93e7b5
SB		 1789 error = ath_rx_init(sc, ATH_RXBUF);
1790 if (error != 0)
40b130a9 1791 goto error_attach;
8feceb67 1792
0e2dedf9 1793 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1794 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1795 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1796
db93e7b5 1797 error = ieee80211_register_hw(hw);
8feceb67 1798
3a702e49 1799 if (!ath_is_world_regd(reg)) {
c02cf373 1800 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1801 if (error)
1802 goto error_attach;
1803 }
5f8e077c 1804
db93e7b5
SB		 1805 /* Initialize LED control */
1806 ath_init_leds(sc);
8feceb67 1807
3b319aae 1808 ath_start_rfkill_poll(sc);
5f8e077c 1809
8feceb67 1810 return 0;
40b130a9
VT		 1811
1812error_attach:
1813 /* cleanup tx queues */
1814 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1815 if (ATH_TXQ_SETUP(sc, i))
1816 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1817
4d6b228d
LR		 1818 ath9k_hw_detach(ah);
1819 ath9k_exit_debug(ah);
3ce1b1a9 1820 sc->sc_ah = NULL;
40b130a9 1821
8feceb67 1822 return error;
f078f209
LR		 1823}
1824
ff37e337
S		 1825int ath_reset(struct ath_softc *sc, bool retry_tx)
1826{
cbe61d8a 1827 struct ath_hw *ah = sc->sc_ah;
030bb495 1828 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1829 int r;
ff37e337
S		 1830
1831 ath9k_hw_set_interrupts(ah, 0);
043a0405 1832 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1833 ath_stoprecv(sc);
1834 ath_flushrecv(sc);
1835
1836 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1837 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1838 if (r)
4d6b228d 1839 DPRINTF(ah, ATH_DBG_FATAL,
6b45784f 1840 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 1841 spin_unlock_bh(&sc->sc_resetlock);
1842
1843 if (ath_startrecv(sc) != 0)
4d6b228d 1844 DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1845
1846 /*
1847 * We may be doing a reset in response to a request
1848 * that changes the channel so update any state that
1849 * might change as a result.
1850 */
ce111bad 1851 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1852
1853 ath_update_txpow(sc);
1854
1855 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1856 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1857
17d7904d 1858 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1859
1860 if (retry_tx) {
1861 int i;
1862 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1863 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1864 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1865 ath_txq_schedule(sc, &sc->tx.txq[i]);
1866 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1867 }
1868 }
1869 }
1870
ae8d2858 1871 return r;
ff37e337
S		 1872}
1873
1874/*
1875 * This function will allocate both the DMA descriptor structure, and the
1876 * buffers it contains. These are used to contain the descriptors used
1877 * by the system.
1878*/
1879int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1880 struct list_head *head, const char *name,
1881 int nbuf, int ndesc)
1882{
1883#define DS2PHYS(_dd, _ds) \
1884 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1885#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1886#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1887
1888 struct ath_desc *ds;
1889 struct ath_buf *bf;
1890 int i, bsize, error;
1891
4d6b228d 1892 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
04bd4638 1893 name, nbuf, ndesc);
ff37e337 1894
b03a9db9 1895 INIT_LIST_HEAD(head);
ff37e337
S		 1896 /* ath_desc must be a multiple of DWORDs */
1897 if ((sizeof(struct ath_desc) % 4) != 0) {
4d6b228d 1898 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1899 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1900 error = -ENOMEM;
1901 goto fail;
1902 }
1903
ff37e337
S		 1904 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1905
1906 /*
1907 * Need additional DMA memory because we can't use
1908 * descriptors that cross the 4K page boundary. Assume
1909 * one skipped descriptor per 4K page.
1910 */
2660b81a 1911 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1912 u32 ndesc_skipped =
1913 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1914 u32 dma_len;
1915
1916 while (ndesc_skipped) {
1917 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1918 dd->dd_desc_len += dma_len;
1919
1920 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1921 };
1922 }
1923
1924 /* allocate descriptors */
7da3c55c 1925 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 1926 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 1927 if (dd->dd_desc == NULL) {
1928 error = -ENOMEM;
1929 goto fail;
1930 }
1931 ds = dd->dd_desc;
4d6b228d 1932 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
ae459af1 1933 name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1934 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1935
1936 /* allocate buffers */
1937 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 1938 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 1939 if (bf == NULL) {
1940 error = -ENOMEM;
1941 goto fail2;
1942 }
ff37e337
S		 1943 dd->dd_bufptr = bf;
1944
ff37e337
S		 1945 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1946 bf->bf_desc = ds;
1947 bf->bf_daddr = DS2PHYS(dd, ds);
1948
2660b81a 1949 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1950 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1951 /*
1952 * Skip descriptor addresses which can cause 4KB
1953 * boundary crossing (addr + length) with a 32 dword
1954 * descriptor fetch.
1955 */
1956 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1957 ASSERT((caddr_t) bf->bf_desc <
1958 ((caddr_t) dd->dd_desc +
1959 dd->dd_desc_len));
1960
1961 ds += ndesc;
1962 bf->bf_desc = ds;
1963 bf->bf_daddr = DS2PHYS(dd, ds);
1964 }
1965 }
1966 list_add_tail(&bf->list, head);
1967 }
1968 return 0;
1969fail2:
7da3c55c
GJ		 1970 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1971 dd->dd_desc_paddr);
ff37e337
S		 1972fail:
1973 memset(dd, 0, sizeof(*dd));
1974 return error;
1975#undef ATH_DESC_4KB_BOUND_CHECK
1976#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1977#undef DS2PHYS
1978}
1979
1980void ath_descdma_cleanup(struct ath_softc *sc,
1981 struct ath_descdma *dd,
1982 struct list_head *head)
1983{
7da3c55c
GJ		 1984 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1985 dd->dd_desc_paddr);
ff37e337
S		 1986
1987 INIT_LIST_HEAD(head);
1988 kfree(dd->dd_bufptr);
1989 memset(dd, 0, sizeof(*dd));
1990}
1991
1992int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1993{
1994 int qnum;
1995
1996 switch (queue) {
1997 case 0:
b77f483f 1998 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1999 break;
2000 case 1:
b77f483f 2001 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 2002 break;
2003 case 2:
b77f483f 2004 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 2005 break;
2006 case 3:
b77f483f 2007 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 2008 break;
2009 default:
b77f483f 2010 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 2011 break;
2012 }
2013
2014 return qnum;
2015}
2016
2017int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2018{
2019 int qnum;
2020
2021 switch (queue) {
2022 case ATH9K_WME_AC_VO:
2023 qnum = 0;
2024 break;
2025 case ATH9K_WME_AC_VI:
2026 qnum = 1;
2027 break;
2028 case ATH9K_WME_AC_BE:
2029 qnum = 2;
2030 break;
2031 case ATH9K_WME_AC_BK:
2032 qnum = 3;
2033 break;
2034 default:
2035 qnum = -1;
2036 break;
2037 }
2038
2039 return qnum;
2040}
2041
5f8e077c
LR		 2042/* XXX: Remove me once we don't depend on ath9k_channel for all
2043 * this redundant data */
0e2dedf9
JM		 2044void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2045 struct ath9k_channel *ichan)
5f8e077c 2046{
5f8e077c
LR		 2047 struct ieee80211_channel *chan = hw->conf.channel;
2048 struct ieee80211_conf *conf = &hw->conf;
2049
2050 ichan->channel = chan->center_freq;
2051 ichan->chan = chan;
2052
2053 if (chan->band == IEEE80211_BAND_2GHZ) {
2054 ichan->chanmode = CHANNEL_G;
8813262e 2055 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
5f8e077c
LR		 2056 } else {
2057 ichan->chanmode = CHANNEL_A;
2058 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2059 }
2060
2061 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2062
2063 if (conf_is_ht(conf)) {
2064 if (conf_is_ht40(conf))
2065 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
2066
2067 ichan->chanmode = ath_get_extchanmode(sc, chan,
2068 conf->channel_type);
2069 }
2070}
2071
ff37e337
S		 2072/**********************/
2073/* mac80211 callbacks */
2074/**********************/
2075
75d7839f
LR		 2076/*
2077 * (Re)start btcoex timers
2078 */
2079static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2080{
2081 struct ath_btcoex *btcoex = &sc->btcoex;
2082 struct ath_hw *ah = sc->sc_ah;
2083
2084 DPRINTF(ah, ATH_DBG_BTCOEX, "Starting btcoex timers");
2085
2086 /* make sure duty cycle timer is also stopped when resuming */
2087 if (btcoex->hw_timer_enabled)
2088 ath_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
2089
2090 btcoex->bt_priority_cnt = 0;
2091 btcoex->bt_priority_time = jiffies;
2092 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2093
2094 mod_timer(&btcoex->period_timer, jiffies);
2095}
2096
8feceb67 2097static int ath9k_start(struct ieee80211_hw *hw)
f078f209 2098{
bce048d7
JM		 2099 struct ath_wiphy *aphy = hw->priv;
2100 struct ath_softc *sc = aphy->sc;
af03abec 2101 struct ath_hw *ah = sc->sc_ah;
8feceb67 2102 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 2103 struct ath9k_channel *init_channel;
82880a7c 2104 int r;
f078f209 2105
af03abec 2106 DPRINTF(ah, ATH_DBG_CONFIG, "Starting driver with "
04bd4638 2107 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 2108
141b38b6
S		 2109 mutex_lock(&sc->mutex);
2110
9580a222
JM		 2111 if (ath9k_wiphy_started(sc)) {
2112 if (sc->chan_idx == curchan->hw_value) {
2113 /*
2114 * Already on the operational channel, the new wiphy
2115 * can be marked active.
2116 */
2117 aphy->state = ATH_WIPHY_ACTIVE;
2118 ieee80211_wake_queues(hw);
2119 } else {
2120 /*
2121 * Another wiphy is on another channel, start the new
2122 * wiphy in paused state.
2123 */
2124 aphy->state = ATH_WIPHY_PAUSED;
2125 ieee80211_stop_queues(hw);
2126 }
2127 mutex_unlock(&sc->mutex);
2128 return 0;
2129 }
2130 aphy->state = ATH_WIPHY_ACTIVE;
2131
8feceb67 2132 /* setup initial channel */
f078f209 2133
82880a7c 2134 sc->chan_idx = curchan->hw_value;
f078f209 2135
82880a7c 2136 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S		 2137
2138 /* Reset SERDES registers */
af03abec 2139 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S		 2140
2141 /*
2142 * The basic interface to setting the hardware in a good
2143 * state is ``reset''. On return the hardware is known to
2144 * be powered up and with interrupts disabled. This must
2145 * be followed by initialization of the appropriate bits
2146 * and then setup of the interrupt mask.
2147 */
2148 spin_lock_bh(&sc->sc_resetlock);
af03abec 2149 r = ath9k_hw_reset(ah, init_channel, false);
ae8d2858 2150 if (r) {
af03abec 2151 DPRINTF(ah, ATH_DBG_FATAL,
6b45784f 2152 "Unable to reset hardware; reset status %d "
ae8d2858
LR		 2153 "(freq %u MHz)\n", r,
2154 curchan->center_freq);
ff37e337 2155 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 2156 goto mutex_unlock;
ff37e337
S		 2157 }
2158 spin_unlock_bh(&sc->sc_resetlock);
2159
2160 /*
2161 * This is needed only to setup initial state
2162 * but it's best done after a reset.
2163 */
2164 ath_update_txpow(sc);
8feceb67 2165
ff37e337
S		 2166 /*
2167 * Setup the hardware after reset:
2168 * The receive engine is set going.
2169 * Frame transmit is handled entirely
2170 * in the frame output path; there's nothing to do
2171 * here except setup the interrupt mask.
2172 */
2173 if (ath_startrecv(sc) != 0) {
af03abec 2174 DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n");
141b38b6
S		 2175 r = -EIO;
2176 goto mutex_unlock;
f078f209 2177 }
8feceb67 2178
ff37e337 2179 /* Setup our intr mask. */
17d7904d 2180 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 2181 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2182 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2183
af03abec 2184 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2185 sc->imask |= ATH9K_INT_GTT;
ff37e337 2186
af03abec 2187 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2188 sc->imask |= ATH9K_INT_CST;
ff37e337 2189
ce111bad 2190 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2191
2192 sc->sc_flags &= ~SC_OP_INVALID;
2193
2194 /* Disable BMISS interrupt when we're not associated */
17d7904d 2195 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
af03abec 2196 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337 2197
bce048d7 2198 ieee80211_wake_queues(hw);
ff37e337 2199
42935eca 2200 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 2201
766ec4a9
LR		 2202 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2203 !ah->btcoex_hw.enabled) {
af03abec
LR		 2204 ath9k_hw_btcoex_init_weight(ah);
2205 ath9k_hw_btcoex_enable(ah);
f985ad12 2206
7b6840ab 2207 ath_pcie_aspm_disable(sc);
766ec4a9 2208 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 2209 ath9k_btcoex_timer_resume(sc);
1773912b
VT		 2210 }
2211
141b38b6
S		 2212mutex_unlock:
2213 mutex_unlock(&sc->mutex);
2214
ae8d2858 2215 return r;
f078f209
LR		 2216}
2217
8feceb67
VT		 2218static int ath9k_tx(struct ieee80211_hw *hw,
2219 struct sk_buff *skb)
f078f209 2220{
528f0c6b 2221 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 2222 struct ath_wiphy *aphy = hw->priv;
2223 struct ath_softc *sc = aphy->sc;
528f0c6b 2224 struct ath_tx_control txctl;
8feceb67 2225 int hdrlen, padsize;
528f0c6b 2226
8089cc47 2227 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
ee166a0e
JM		 2228 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2229 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2230 goto exit;
2231 }
2232
96148326 2233 if (sc->ps_enabled) {
dc8c4585
JM		 2234 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2235 /*
2236 * mac80211 does not set PM field for normal data frames, so we
2237 * need to update that based on the current PS mode.
2238 */
2239 if (ieee80211_is_data(hdr->frame_control) &&
2240 !ieee80211_is_nullfunc(hdr->frame_control) &&
2241 !ieee80211_has_pm(hdr->frame_control)) {
4d6b228d 2242 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Add PM=1 for a TX frame "
dc8c4585
JM		 2243 "while in PS mode\n");
2244 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2245 }
2246 }
2247
9a23f9ca
JM		 2248 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2249 /*
2250 * We are using PS-Poll and mac80211 can request TX while in
2251 * power save mode. Need to wake up hardware for the TX to be
2252 * completed and if needed, also for RX of buffered frames.
2253 */
2254 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2255 ath9k_ps_wakeup(sc);
2256 ath9k_hw_setrxabort(sc->sc_ah, 0);
2257 if (ieee80211_is_pspoll(hdr->frame_control)) {
4d6b228d 2258 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Sending PS-Poll to pick a "
9a23f9ca
JM		 2259 "buffered frame\n");
2260 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2261 } else {
4d6b228d 2262 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Wake up to complete TX\n");
9a23f9ca
JM		 2263 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2264 }
2265 /*
2266 * The actual restore operation will happen only after
2267 * the sc_flags bit is cleared. We are just dropping
2268 * the ps_usecount here.
2269 */
2270 ath9k_ps_restore(sc);
2271 }
2272
528f0c6b 2273 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2274
8feceb67
VT		 2275 /*
2276 * As a temporary workaround, assign seq# here; this will likely need
2277 * to be cleaned up to work better with Beacon transmission and virtual
2278 * BSSes.
2279 */
2280 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2281 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2282 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2283 sc->tx.seq_no += 0x10;
8feceb67 2284 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2285 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2286 }
f078f209 2287
8feceb67
VT		 2288 /* Add the padding after the header if this is not already done */
2289 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2290 if (hdrlen & 3) {
2291 padsize = hdrlen % 4;
2292 if (skb_headroom(skb) < padsize)
2293 return -1;
2294 skb_push(skb, padsize);
2295 memmove(skb->data, skb->data + padsize, hdrlen);
2296 }
2297
528f0c6b
S		 2298 /* Check if a tx queue is available */
2299
2300 txctl.txq = ath_test_get_txq(sc, skb);
2301 if (!txctl.txq)
2302 goto exit;
2303
4d6b228d 2304 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2305
c52f33d0 2306 if (ath_tx_start(hw, skb, &txctl) != 0) {
4d6b228d 2307 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2308 goto exit;
8feceb67
VT		 2309 }
2310
528f0c6b
S		 2311 return 0;
2312exit:
2313 dev_kfree_skb_any(skb);
8feceb67 2314 return 0;
f078f209
LR		 2315}
2316
75d7839f
LR		 2317/*
2318 * Pause btcoex timer and bt duty cycle timer
2319 */
2320static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2321{
2322 struct ath_btcoex *btcoex = &sc->btcoex;
2323 struct ath_hw *ah = sc->sc_ah;
2324
2325 del_timer_sync(&btcoex->period_timer);
2326
2327 if (btcoex->hw_timer_enabled)
2328 ath_gen_timer_stop(ah, btcoex->no_stomp_timer);
2329
2330 btcoex->hw_timer_enabled = false;
2331}
2332
8feceb67 2333static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2334{
bce048d7
JM		 2335 struct ath_wiphy *aphy = hw->priv;
2336 struct ath_softc *sc = aphy->sc;
af03abec 2337 struct ath_hw *ah = sc->sc_ah;
f078f209 2338
4c483817
S		 2339 mutex_lock(&sc->mutex);
2340
9580a222
JM		 2341 aphy->state = ATH_WIPHY_INACTIVE;
2342
c94dbff7
LR		 2343 cancel_delayed_work_sync(&sc->ath_led_blink_work);
2344 cancel_delayed_work_sync(&sc->tx_complete_work);
2345
2346 if (!sc->num_sec_wiphy) {
2347 cancel_delayed_work_sync(&sc->wiphy_work);
2348 cancel_work_sync(&sc->chan_work);
2349 }
2350
9c84b797 2351 if (sc->sc_flags & SC_OP_INVALID) {
af03abec 2352 DPRINTF(ah, ATH_DBG_ANY, "Device not present\n");
4c483817 2353 mutex_unlock(&sc->mutex);
9c84b797
S		 2354 return;
2355 }
8feceb67 2356
9580a222
JM		 2357 if (ath9k_wiphy_started(sc)) {
2358 mutex_unlock(&sc->mutex);
2359 return; /* another wiphy still in use */
2360 }
2361
766ec4a9 2362 if (ah->btcoex_hw.enabled) {
af03abec 2363 ath9k_hw_btcoex_disable(ah);
766ec4a9 2364 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 2365 ath9k_btcoex_timer_pause(sc);
1773912b
VT		 2366 }
2367
ff37e337
S		 2368 /* make sure h/w will not generate any interrupt
2369 * before setting the invalid flag. */
af03abec 2370 ath9k_hw_set_interrupts(ah, 0);
ff37e337
S		 2371
2372 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2373 ath_drain_all_txq(sc, false);
ff37e337 2374 ath_stoprecv(sc);
af03abec 2375 ath9k_hw_phy_disable(ah);
ff37e337 2376 } else
b77f483f 2377 sc->rx.rxlink = NULL;
ff37e337 2378
ff37e337 2379 /* disable HAL and put h/w to sleep */
af03abec
LR		 2380 ath9k_hw_disable(ah);
2381 ath9k_hw_configpcipowersave(ah, 1, 1);
2382 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
ff37e337
S		 2383
2384 sc->sc_flags |= SC_OP_INVALID;
500c064d 2385
141b38b6
S		 2386 mutex_unlock(&sc->mutex);
2387
af03abec 2388 DPRINTF(ah, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2389}
2390
8feceb67
VT		 2391static int ath9k_add_interface(struct ieee80211_hw *hw,
2392 struct ieee80211_if_init_conf *conf)
f078f209 2393{
bce048d7
JM		 2394 struct ath_wiphy *aphy = hw->priv;
2395 struct ath_softc *sc = aphy->sc;
17d7904d 2396 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2397 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2398 int ret = 0;
8feceb67 2399
141b38b6
S		 2400 mutex_lock(&sc->mutex);
2401
8ca21f01
JM		 2402 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2403 sc->nvifs > 0) {
2404 ret = -ENOBUFS;
2405 goto out;
2406 }
2407
8feceb67 2408 switch (conf->type) {
05c914fe 2409 case NL80211_IFTYPE_STATION:
d97809db 2410 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2411 break;
05c914fe 2412 case NL80211_IFTYPE_ADHOC:
05c914fe 2413 case NL80211_IFTYPE_AP:
9cb5412b 2414 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2415 if (sc->nbcnvifs >= ATH_BCBUF) {
2416 ret = -ENOBUFS;
2417 goto out;
2418 }
9cb5412b 2419 ic_opmode = conf->type;
f078f209
LR		 2420 break;
2421 default:
4d6b228d 2422 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
04bd4638 2423 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2424 ret = -EOPNOTSUPP;
2425 goto out;
f078f209
LR		 2426 }
2427
4d6b228d 2428 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2429
17d7904d 2430 /* Set the VIF opmode */
5640b08e
S		 2431 avp->av_opmode = ic_opmode;
2432 avp->av_bslot = -1;
2433
2c3db3d5 2434 sc->nvifs++;
8ca21f01
JM		 2435
2436 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2437 ath9k_set_bssid_mask(hw);
2438
2c3db3d5
JM		 2439 if (sc->nvifs > 1)
2440 goto out; /* skip global settings for secondary vif */
2441
b238e90e 2442 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2443 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2444 sc->sc_flags |= SC_OP_TSF_RESET;
2445 }
5640b08e 2446
5640b08e 2447 /* Set the device opmode */
2660b81a 2448 sc->sc_ah->opmode = ic_opmode;
5640b08e 2449
4e30ffa2
VN		 2450 /*
2451 * Enable MIB interrupts when there are hardware phy counters.
2452 * Note we only do this (at the moment) for station mode.
2453 */
4af9cf4f 2454 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2455 (conf->type == NL80211_IFTYPE_ADHOC) ||
2456 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
1aa8e847 2457 sc->imask |= ATH9K_INT_MIB;
4af9cf4f
S		 2458 sc->imask |= ATH9K_INT_TSFOOR;
2459 }
2460
17d7904d 2461 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2462
f38faa31
SB		 2463 if (conf->type == NL80211_IFTYPE_AP ||
2464 conf->type == NL80211_IFTYPE_ADHOC ||
2465 conf->type == NL80211_IFTYPE_MONITOR)
415f738e 2466 ath_start_ani(sc);
6f255425 2467
2c3db3d5 2468out:
141b38b6 2469 mutex_unlock(&sc->mutex);
2c3db3d5 2470 return ret;
f078f209
LR		 2471}
2472
8feceb67
VT		 2473static void ath9k_remove_interface(struct ieee80211_hw *hw,
2474 struct ieee80211_if_init_conf *conf)
f078f209 2475{
bce048d7
JM		 2476 struct ath_wiphy *aphy = hw->priv;
2477 struct ath_softc *sc = aphy->sc;
17d7904d 2478 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2479 int i;
f078f209 2480
4d6b228d 2481 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2482
141b38b6
S		 2483 mutex_lock(&sc->mutex);
2484
6f255425 2485 /* Stop ANI */
17d7904d 2486 del_timer_sync(&sc->ani.timer);
580f0b8a 2487
8feceb67 2488 /* Reclaim beacon resources */
9cb5412b
PE		 2489 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2490 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2491 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2492 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2493 ath_beacon_return(sc, avp);
580f0b8a 2494 }
f078f209 2495
8feceb67 2496 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2497
2c3db3d5
JM		 2498 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2499 if (sc->beacon.bslot[i] == conf->vif) {
2500 printk(KERN_DEBUG "%s: vif had allocated beacon "
2501 "slot\n", __func__);
2502 sc->beacon.bslot[i] = NULL;
c52f33d0 2503 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2504 }
2505 }
2506
17d7904d 2507 sc->nvifs--;
141b38b6
S		 2508
2509 mutex_unlock(&sc->mutex);
f078f209
LR		 2510}
2511
e8975581 2512static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2513{
bce048d7
JM		 2514 struct ath_wiphy *aphy = hw->priv;
2515 struct ath_softc *sc = aphy->sc;
e8975581 2516 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2517 struct ath_hw *ah = sc->sc_ah;
64839170 2518 bool all_wiphys_idle = false, disable_radio = false;
f078f209 2519
aa33de09 2520 mutex_lock(&sc->mutex);
141b38b6 2521
64839170
LR		 2522 /* Leave this as the first check */
2523 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2524
2525 spin_lock_bh(&sc->wiphy_lock);
2526 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2527 spin_unlock_bh(&sc->wiphy_lock);
2528
2529 if (conf->flags & IEEE80211_CONF_IDLE){
2530 if (all_wiphys_idle)
2531 disable_radio = true;
2532 }
2533 else if (all_wiphys_idle) {
2534 ath_radio_enable(sc);
4d6b228d 2535 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
64839170
LR		 2536 "not-idle: enabling radio\n");
2537 }
2538 }
2539
3cbb5dd7
VN		 2540 if (changed & IEEE80211_CONF_CHANGE_PS) {
2541 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2542 if (!(ah->caps.hw_caps &
2543 ATH9K_HW_CAP_AUTOSLEEP)) {
2544 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2545 sc->imask |= ATH9K_INT_TIM_TIMER;
2546 ath9k_hw_set_interrupts(sc->sc_ah,
2547 sc->imask);
2548 }
2549 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2550 }
96148326 2551 sc->ps_enabled = true;
3cbb5dd7 2552 } else {
96148326 2553 sc->ps_enabled = false;
3cbb5dd7 2554 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8782b41d
VN		 2555 if (!(ah->caps.hw_caps &
2556 ATH9K_HW_CAP_AUTOSLEEP)) {
2557 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca
JM		 2558 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2559 SC_OP_WAIT_FOR_CAB |
2560 SC_OP_WAIT_FOR_PSPOLL_DATA |
2561 SC_OP_WAIT_FOR_TX_ACK);
8782b41d
VN		 2562 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2563 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2564 ath9k_hw_set_interrupts(sc->sc_ah,
2565 sc->imask);
2566 }
3cbb5dd7
VN		 2567 }
2568 }
2569 }
2570
4797938c 2571 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2572 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2573 int pos = curchan->hw_value;
ae5eb026 2574
0e2dedf9
JM		 2575 aphy->chan_idx = pos;
2576 aphy->chan_is_ht = conf_is_ht(conf);
2577
8089cc47
JM		 2578 if (aphy->state == ATH_WIPHY_SCAN ||
2579 aphy->state == ATH_WIPHY_ACTIVE)
2580 ath9k_wiphy_pause_all_forced(sc, aphy);
2581 else {
2582 /*
2583 * Do not change operational channel based on a paused
2584 * wiphy changes.
2585 */
2586 goto skip_chan_change;
2587 }
0e2dedf9 2588
4d6b228d 2589 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
04bd4638 2590 curchan->center_freq);
f078f209 2591
5f8e077c 2592 /* XXX: remove me eventualy */
0e2dedf9 2593 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2594
ecf70441 2595 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2596
0e2dedf9 2597 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
4d6b228d 2598 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2599 mutex_unlock(&sc->mutex);
e11602b7
S		 2600 return -EINVAL;
2601 }
094d05dc 2602 }
f078f209 2603
8089cc47 2604skip_chan_change:
5c020dc6 2605 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2606 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2607
64839170 2608 if (disable_radio) {
4d6b228d 2609 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "idle: disabling radio\n");
64839170
LR		 2610 ath_radio_disable(sc);
2611 }
2612
aa33de09 2613 mutex_unlock(&sc->mutex);
141b38b6 2614
f078f209
LR		 2615 return 0;
2616}
2617
8feceb67
VT		 2618#define SUPPORTED_FILTERS \
2619 (FIF_PROMISC_IN_BSS | \
2620 FIF_ALLMULTI | \
2621 FIF_CONTROL | \
af6a3fc7 2622 FIF_PSPOLL | \
8feceb67
VT		 2623 FIF_OTHER_BSS | \
2624 FIF_BCN_PRBRESP_PROMISC | \
2625 FIF_FCSFAIL)
c83be688 2626
8feceb67
VT		 2627/* FIXME: sc->sc_full_reset ? */
2628static void ath9k_configure_filter(struct ieee80211_hw *hw,
2629 unsigned int changed_flags,
2630 unsigned int *total_flags,
3ac64bee 2631 u64 multicast)
8feceb67 2632{
bce048d7
JM		 2633 struct ath_wiphy *aphy = hw->priv;
2634 struct ath_softc *sc = aphy->sc;
8feceb67 2635 u32 rfilt;
f078f209 2636
8feceb67
VT		 2637 changed_flags &= SUPPORTED_FILTERS;
2638 *total_flags &= SUPPORTED_FILTERS;
f078f209 2639
b77f483f 2640 sc->rx.rxfilter = *total_flags;
aa68aeaa 2641 ath9k_ps_wakeup(sc);
8feceb67
VT		 2642 rfilt = ath_calcrxfilter(sc);
2643 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 2644 ath9k_ps_restore(sc);
f078f209 2645
4d6b228d 2646 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 2647}
f078f209 2648
8feceb67
VT		 2649static void ath9k_sta_notify(struct ieee80211_hw *hw,
2650 struct ieee80211_vif *vif,
2651 enum sta_notify_cmd cmd,
17741cdc 2652 struct ieee80211_sta *sta)
8feceb67 2653{
bce048d7
JM		 2654 struct ath_wiphy *aphy = hw->priv;
2655 struct ath_softc *sc = aphy->sc;
f078f209 2656
8feceb67
VT		 2657 switch (cmd) {
2658 case STA_NOTIFY_ADD:
5640b08e 2659 ath_node_attach(sc, sta);
8feceb67
VT		 2660 break;
2661 case STA_NOTIFY_REMOVE:
b5aa9bf9 2662 ath_node_detach(sc, sta);
8feceb67
VT		 2663 break;
2664 default:
2665 break;
2666 }
f078f209
LR		 2667}
2668
141b38b6 2669static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2670 const struct ieee80211_tx_queue_params *params)
f078f209 2671{
bce048d7
JM		 2672 struct ath_wiphy *aphy = hw->priv;
2673 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2674 struct ath9k_tx_queue_info qi;
2675 int ret = 0, qnum;
f078f209 2676
8feceb67
VT		 2677 if (queue >= WME_NUM_AC)
2678 return 0;
f078f209 2679
141b38b6
S		 2680 mutex_lock(&sc->mutex);
2681
1ffb0610
S		 2682 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2683
8feceb67
VT		 2684 qi.tqi_aifs = params->aifs;
2685 qi.tqi_cwmin = params->cw_min;
2686 qi.tqi_cwmax = params->cw_max;
2687 qi.tqi_burstTime = params->txop;
2688 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2689
4d6b228d 2690 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
04bd4638 2691 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2692 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2693 queue, qnum, params->aifs, params->cw_min,
2694 params->cw_max, params->txop);
f078f209 2695
8feceb67
VT		 2696 ret = ath_txq_update(sc, qnum, &qi);
2697 if (ret)
4d6b228d 2698 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2699
141b38b6
S		 2700 mutex_unlock(&sc->mutex);
2701
8feceb67
VT		 2702 return ret;
2703}
f078f209 2704
8feceb67
VT		 2705static int ath9k_set_key(struct ieee80211_hw *hw,
2706 enum set_key_cmd cmd,
dc822b5d
JB		 2707 struct ieee80211_vif *vif,
2708 struct ieee80211_sta *sta,
8feceb67
VT		 2709 struct ieee80211_key_conf *key)
2710{
bce048d7
JM		 2711 struct ath_wiphy *aphy = hw->priv;
2712 struct ath_softc *sc = aphy->sc;
8feceb67 2713 int ret = 0;
f078f209 2714
b3bd89ce
JM		 2715 if (modparam_nohwcrypt)
2716 return -ENOSPC;
2717
141b38b6 2718 mutex_lock(&sc->mutex);
3cbb5dd7 2719 ath9k_ps_wakeup(sc);
4d6b228d 2720 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2721
8feceb67
VT		 2722 switch (cmd) {
2723 case SET_KEY:
3f53dd64 2724 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2725 if (ret >= 0) {
2726 key->hw_key_idx = ret;
8feceb67
VT		 2727 /* push IV and Michael MIC generation to stack */
2728 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2729 if (key->alg == ALG_TKIP)
2730 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2731 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2732 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2733 ret = 0;
8feceb67
VT		 2734 }
2735 break;
2736 case DISABLE_KEY:
2737 ath_key_delete(sc, key);
8feceb67
VT		 2738 break;
2739 default:
2740 ret = -EINVAL;
2741 }
f078f209 2742
3cbb5dd7 2743 ath9k_ps_restore(sc);
141b38b6
S		 2744 mutex_unlock(&sc->mutex);
2745
8feceb67
VT		 2746 return ret;
2747}
f078f209 2748
8feceb67
VT		 2749static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2750 struct ieee80211_vif *vif,
2751 struct ieee80211_bss_conf *bss_conf,
2752 u32 changed)
2753{
bce048d7
JM		 2754 struct ath_wiphy *aphy = hw->priv;
2755 struct ath_softc *sc = aphy->sc;
2d0ddec5
JB		 2756 struct ath_hw *ah = sc->sc_ah;
2757 struct ath_vif *avp = (void *)vif->drv_priv;
2758 u32 rfilt = 0;
2759 int error, i;
f078f209 2760
141b38b6
S		 2761 mutex_lock(&sc->mutex);
2762
2d0ddec5
JB		 2763 /*
2764 * TODO: Need to decide which hw opmode to use for
2765 * multi-interface cases
2766 * XXX: This belongs into add_interface!
2767 */
2768 if (vif->type == NL80211_IFTYPE_AP &&
2769 ah->opmode != NL80211_IFTYPE_AP) {
2770 ah->opmode = NL80211_IFTYPE_STATION;
2771 ath9k_hw_setopmode(ah);
2772 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2773 sc->curaid = 0;
2774 ath9k_hw_write_associd(sc);
2775 /* Request full reset to get hw opmode changed properly */
2776 sc->sc_flags |= SC_OP_FULL_RESET;
2777 }
2778
2779 if ((changed & BSS_CHANGED_BSSID) &&
2780 !is_zero_ether_addr(bss_conf->bssid)) {
2781 switch (vif->type) {
2782 case NL80211_IFTYPE_STATION:
2783 case NL80211_IFTYPE_ADHOC:
2784 case NL80211_IFTYPE_MESH_POINT:
2785 /* Set BSSID */
2786 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2787 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2788 sc->curaid = 0;
2789 ath9k_hw_write_associd(sc);
2790
2791 /* Set aggregation protection mode parameters */
2792 sc->config.ath_aggr_prot = 0;
2793
4d6b228d 2794 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2d0ddec5
JB		 2795 "RX filter 0x%x bssid %pM aid 0x%x\n",
2796 rfilt, sc->curbssid, sc->curaid);
2797
2798 /* need to reconfigure the beacon */
2799 sc->sc_flags &= ~SC_OP_BEACONS ;
2800
2801 break;
2802 default:
2803 break;
2804 }
2805 }
2806
2807 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2808 (vif->type == NL80211_IFTYPE_AP) ||
2809 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2810 if ((changed & BSS_CHANGED_BEACON) ||
2811 (changed & BSS_CHANGED_BEACON_ENABLED &&
2812 bss_conf->enable_beacon)) {
2813 /*
2814 * Allocate and setup the beacon frame.
2815 *
2816 * Stop any previous beacon DMA. This may be
2817 * necessary, for example, when an ibss merge
2818 * causes reconfiguration; we may be called
2819 * with beacon transmission active.
2820 */
2821 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2822
2823 error = ath_beacon_alloc(aphy, vif);
2824 if (!error)
2825 ath_beacon_config(sc, vif);
2826 }
2827 }
2828
2829 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2830 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2831 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2832 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2833 ath9k_hw_keysetmac(sc->sc_ah,
2834 (u16)i,
2835 sc->curbssid);
2836 }
2837
2838 /* Only legacy IBSS for now */
2839 if (vif->type == NL80211_IFTYPE_ADHOC)
2840 ath_update_chainmask(sc, 0);
2841
8feceb67 2842 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4d6b228d 2843 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2844 bss_conf->use_short_preamble);
2845 if (bss_conf->use_short_preamble)
2846 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2847 else
2848 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2849 }
f078f209 2850
8feceb67 2851 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
4d6b228d 2852 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2853 bss_conf->use_cts_prot);
2854 if (bss_conf->use_cts_prot &&
2855 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2856 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2857 else
2858 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2859 }
f078f209 2860
8feceb67 2861 if (changed & BSS_CHANGED_ASSOC) {
4d6b228d 2862 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2863 bss_conf->assoc);
5640b08e 2864 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2865 }
141b38b6 2866
57c4d7b4
JB		 2867 /*
2868 * The HW TSF has to be reset when the beacon interval changes.
2869 * We set the flag here, and ath_beacon_config_ap() would take this
2870 * into account when it gets called through the subsequent
2871 * config_interface() call - with IFCC_BEACON in the changed field.
2872 */
2873
2874 if (changed & BSS_CHANGED_BEACON_INT) {
2875 sc->sc_flags |= SC_OP_TSF_RESET;
2876 sc->beacon_interval = bss_conf->beacon_int;
2877 }
2878
141b38b6 2879 mutex_unlock(&sc->mutex);
8feceb67 2880}
f078f209 2881
8feceb67
VT		 2882static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2883{
2884 u64 tsf;
bce048d7
JM		 2885 struct ath_wiphy *aphy = hw->priv;
2886 struct ath_softc *sc = aphy->sc;
f078f209 2887
141b38b6
S		 2888 mutex_lock(&sc->mutex);
2889 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2890 mutex_unlock(&sc->mutex);
f078f209 2891
8feceb67
VT		 2892 return tsf;
2893}
f078f209 2894
3b5d665b
AF		 2895static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2896{
bce048d7
JM		 2897 struct ath_wiphy *aphy = hw->priv;
2898 struct ath_softc *sc = aphy->sc;
3b5d665b 2899
141b38b6
S		 2900 mutex_lock(&sc->mutex);
2901 ath9k_hw_settsf64(sc->sc_ah, tsf);
2902 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2903}
2904
8feceb67
VT		 2905static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2906{
bce048d7
JM		 2907 struct ath_wiphy *aphy = hw->priv;
2908 struct ath_softc *sc = aphy->sc;
c83be688 2909
141b38b6
S		 2910 mutex_lock(&sc->mutex);
2911 ath9k_hw_reset_tsf(sc->sc_ah);
2912 mutex_unlock(&sc->mutex);
8feceb67 2913}
f078f209 2914
8feceb67 2915static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2916 enum ieee80211_ampdu_mlme_action action,
2917 struct ieee80211_sta *sta,
2918 u16 tid, u16 *ssn)
8feceb67 2919{
bce048d7
JM		 2920 struct ath_wiphy *aphy = hw->priv;
2921 struct ath_softc *sc = aphy->sc;
8feceb67 2922 int ret = 0;
f078f209 2923
8feceb67
VT		 2924 switch (action) {
2925 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2926 if (!(sc->sc_flags & SC_OP_RXAGGR))
2927 ret = -ENOTSUPP;
8feceb67
VT		 2928 break;
2929 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2930 break;
2931 case IEEE80211_AMPDU_TX_START:
f83da965
S		 2932 ath_tx_aggr_start(sc, sta, tid, ssn);
2933 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2934 break;
2935 case IEEE80211_AMPDU_TX_STOP:
f83da965 2936 ath_tx_aggr_stop(sc, sta, tid);
17741cdc 2937 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2938 break;
b1720231 2939 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 2940 ath_tx_aggr_resume(sc, sta, tid);
2941 break;
8feceb67 2942 default:
4d6b228d 2943 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2944 }
2945
2946 return ret;
f078f209
LR		 2947}
2948
0c98de65
S		 2949static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2950{
bce048d7
JM		 2951 struct ath_wiphy *aphy = hw->priv;
2952 struct ath_softc *sc = aphy->sc;
0c98de65 2953
3d832611 2954 mutex_lock(&sc->mutex);
8089cc47
JM		 2955 if (ath9k_wiphy_scanning(sc)) {
2956 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2957 "same time\n");
2958 /*
2959 * Do not allow the concurrent scanning state for now. This
2960 * could be improved with scanning control moved into ath9k.
2961 */
3d832611 2962 mutex_unlock(&sc->mutex);
8089cc47
JM		 2963 return;
2964 }
2965
2966 aphy->state = ATH_WIPHY_SCAN;
2967 ath9k_wiphy_pause_all_forced(sc, aphy);
2968
e5f0921a 2969 spin_lock_bh(&sc->ani_lock);
0c98de65 2970 sc->sc_flags |= SC_OP_SCANNING;
e5f0921a 2971 spin_unlock_bh(&sc->ani_lock);
3d832611 2972 mutex_unlock(&sc->mutex);
0c98de65
S		 2973}
2974
2975static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2976{
bce048d7
JM		 2977 struct ath_wiphy *aphy = hw->priv;
2978 struct ath_softc *sc = aphy->sc;
0c98de65 2979
3d832611 2980 mutex_lock(&sc->mutex);
e5f0921a 2981 spin_lock_bh(&sc->ani_lock);
8089cc47 2982 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 2983 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 2984 sc->sc_flags |= SC_OP_FULL_RESET;
e5f0921a 2985 spin_unlock_bh(&sc->ani_lock);
d0bec342 2986 ath_beacon_config(sc, NULL);
3d832611 2987 mutex_unlock(&sc->mutex);
0c98de65
S		 2988}
2989
6baff7f9 2990struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2991 .tx = ath9k_tx,
2992 .start = ath9k_start,
2993 .stop = ath9k_stop,
2994 .add_interface = ath9k_add_interface,
2995 .remove_interface = ath9k_remove_interface,
2996 .config = ath9k_config,
8feceb67 2997 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2998 .sta_notify = ath9k_sta_notify,
2999 .conf_tx = ath9k_conf_tx,
8feceb67 3000 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 3001 .set_key = ath9k_set_key,
8feceb67 3002 .get_tsf = ath9k_get_tsf,
3b5d665b 3003 .set_tsf = ath9k_set_tsf,
8feceb67 3004 .reset_tsf = ath9k_reset_tsf,
4233df6b 3005 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 3006 .sw_scan_start = ath9k_sw_scan_start,
3007 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 3008 .rfkill_poll = ath9k_rfkill_poll_state,
8feceb67
VT		 3009};
3010
392dff83
BP		 3011static struct {
3012 u32 version;
3013 const char * name;
3014} ath_mac_bb_names[] = {
3015 { AR_SREV_VERSION_5416_PCI, "5416" },
3016 { AR_SREV_VERSION_5416_PCIE, "5418" },
3017 { AR_SREV_VERSION_9100, "9100" },
3018 { AR_SREV_VERSION_9160, "9160" },
3019 { AR_SREV_VERSION_9280, "9280" },
ac88b6ec
VN		 3020 { AR_SREV_VERSION_9285, "9285" },
3021 { AR_SREV_VERSION_9287, "9287" }
392dff83
BP		 3022};
3023
3024static struct {
3025 u16 version;
3026 const char * name;
3027} ath_rf_names[] = {
3028 { 0, "5133" },
3029 { AR_RAD5133_SREV_MAJOR, "5133" },
3030 { AR_RAD5122_SREV_MAJOR, "5122" },
3031 { AR_RAD2133_SREV_MAJOR, "2133" },
3032 { AR_RAD2122_SREV_MAJOR, "2122" }
3033};
3034
3035/*
3036 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3037 */
6baff7f9 3038const char *
392dff83
BP		 3039ath_mac_bb_name(u32 mac_bb_version)
3040{
3041 int i;
3042
3043 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3044 if (ath_mac_bb_names[i].version == mac_bb_version) {
3045 return ath_mac_bb_names[i].name;
3046 }
3047 }
3048
3049 return "????";
3050}
3051
3052/*
3053 * Return the RF name. "????" is returned if the RF is unknown.
3054 */
6baff7f9 3055const char *
392dff83
BP		 3056ath_rf_name(u16 rf_version)
3057{
3058 int i;
3059
3060 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3061 if (ath_rf_names[i].version == rf_version) {
3062 return ath_rf_names[i].name;
3063 }
3064 }
3065
3066 return "????";
3067}
3068
6baff7f9 3069static int __init ath9k_init(void)
f078f209 3070{
ca8a8560
VT		 3071 int error;
3072
ca8a8560
VT		 3073 /* Register rate control algorithm */
3074 error = ath_rate_control_register();
3075 if (error != 0) {
3076 printk(KERN_ERR
b51bb3cd
LR		 3077 "ath9k: Unable to register rate control "
3078 "algorithm: %d\n",
ca8a8560 3079 error);
6baff7f9 3080 goto err_out;
ca8a8560
VT		 3081 }
3082
19d8bc22
GJ		 3083 error = ath9k_debug_create_root();
3084 if (error) {
3085 printk(KERN_ERR
3086 "ath9k: Unable to create debugfs root: %d\n",
3087 error);
3088 goto err_rate_unregister;
3089 }
3090
6baff7f9
GJ		 3091 error = ath_pci_init();
3092 if (error < 0) {
f078f209 3093 printk(KERN_ERR
b51bb3cd 3094 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 3095 error = -ENODEV;
19d8bc22 3096 goto err_remove_root;
f078f209
LR		 3097 }
3098
09329d37
GJ		 3099 error = ath_ahb_init();
3100 if (error < 0) {
3101 error = -ENODEV;
3102 goto err_pci_exit;
3103 }
3104
f078f209 3105 return 0;
6baff7f9 3106
09329d37
GJ		 3107 err_pci_exit:
3108 ath_pci_exit();
3109
19d8bc22
GJ		 3110 err_remove_root:
3111 ath9k_debug_remove_root();
6baff7f9
GJ		 3112 err_rate_unregister:
3113 ath_rate_control_unregister();
3114 err_out:
3115 return error;
f078f209 3116}
6baff7f9 3117module_init(ath9k_init);
f078f209 3118
6baff7f9 3119static void __exit ath9k_exit(void)
f078f209 3120{
09329d37 3121 ath_ahb_exit();
6baff7f9 3122 ath_pci_exit();
19d8bc22 3123 ath9k_debug_remove_root();
ca8a8560 3124 ath_rate_control_unregister();
04bd4638 3125 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 3126}
6baff7f9 3127module_exit(ath9k_exit);
Linux kernel - Deliverables
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