Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
69081624 | 18 | #include <linux/delay.h> |
394cf0a1 | 19 | #include "ath9k.h" |
af03abec | 20 | #include "btcoex.h" |
f078f209 | 21 | |
313eb87f | 22 | u8 ath9k_parse_mpdudensity(u8 mpdudensity) |
ff37e337 S |
23 | { |
24 | /* | |
25 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
26 | * 0 for no restriction | |
27 | * 1 for 1/4 us | |
28 | * 2 for 1/2 us | |
29 | * 3 for 1 us | |
30 | * 4 for 2 us | |
31 | * 5 for 4 us | |
32 | * 6 for 8 us | |
33 | * 7 for 16 us | |
34 | */ | |
35 | switch (mpdudensity) { | |
36 | case 0: | |
37 | return 0; | |
38 | case 1: | |
39 | case 2: | |
40 | case 3: | |
41 | /* Our lower layer calculations limit our precision to | |
42 | 1 microsecond */ | |
43 | return 1; | |
44 | case 4: | |
45 | return 2; | |
46 | case 5: | |
47 | return 4; | |
48 | case 6: | |
49 | return 8; | |
50 | case 7: | |
51 | return 16; | |
52 | default: | |
53 | return 0; | |
54 | } | |
55 | } | |
56 | ||
69081624 VT |
57 | static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) |
58 | { | |
59 | bool pending = false; | |
60 | ||
61 | spin_lock_bh(&txq->axq_lock); | |
62 | ||
0453531e | 63 | if (txq->axq_depth) |
69081624 | 64 | pending = true; |
69081624 | 65 | |
0453531e FF |
66 | if (txq->mac80211_qnum >= 0) { |
67 | struct list_head *list; | |
68 | ||
69 | list = &sc->cur_chan->acq[txq->mac80211_qnum]; | |
70 | if (!list_empty(list)) | |
71 | pending = true; | |
72 | } | |
69081624 VT |
73 | spin_unlock_bh(&txq->axq_lock); |
74 | return pending; | |
75 | } | |
76 | ||
6d79cb4c | 77 | static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
78 | { |
79 | unsigned long flags; | |
80 | bool ret; | |
81 | ||
9ecdef4b LR |
82 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
83 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
84 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
85 | |
86 | return ret; | |
87 | } | |
88 | ||
bf3dac5a FF |
89 | void ath_ps_full_sleep(unsigned long data) |
90 | { | |
91 | struct ath_softc *sc = (struct ath_softc *) data; | |
92 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
93 | bool reset; | |
94 | ||
95 | spin_lock(&common->cc_lock); | |
96 | ath_hw_cycle_counters_update(common); | |
97 | spin_unlock(&common->cc_lock); | |
98 | ||
99 | ath9k_hw_setrxabort(sc->sc_ah, 1); | |
100 | ath9k_hw_stopdmarecv(sc->sc_ah, &reset); | |
101 | ||
102 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); | |
103 | } | |
104 | ||
a91d75ae LR |
105 | void ath9k_ps_wakeup(struct ath_softc *sc) |
106 | { | |
898c914a | 107 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae | 108 | unsigned long flags; |
fbb078fc | 109 | enum ath9k_power_mode power_mode; |
a91d75ae LR |
110 | |
111 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
112 | if (++sc->ps_usecount != 1) | |
113 | goto unlock; | |
114 | ||
bf3dac5a | 115 | del_timer_sync(&sc->sleep_timer); |
fbb078fc | 116 | power_mode = sc->sc_ah->power_mode; |
9ecdef4b | 117 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae | 118 | |
898c914a FF |
119 | /* |
120 | * While the hardware is asleep, the cycle counters contain no | |
121 | * useful data. Better clear them now so that they don't mess up | |
122 | * survey data results. | |
123 | */ | |
fbb078fc FF |
124 | if (power_mode != ATH9K_PM_AWAKE) { |
125 | spin_lock(&common->cc_lock); | |
126 | ath_hw_cycle_counters_update(common); | |
127 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
c9ae6ab4 | 128 | memset(&common->cc_ani, 0, sizeof(common->cc_ani)); |
fbb078fc FF |
129 | spin_unlock(&common->cc_lock); |
130 | } | |
898c914a | 131 | |
a91d75ae LR |
132 | unlock: |
133 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
134 | } | |
135 | ||
136 | void ath9k_ps_restore(struct ath_softc *sc) | |
137 | { | |
898c914a | 138 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
c6c539f0 | 139 | enum ath9k_power_mode mode; |
a91d75ae LR |
140 | unsigned long flags; |
141 | ||
142 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
143 | if (--sc->ps_usecount != 0) | |
144 | goto unlock; | |
145 | ||
ad128860 | 146 | if (sc->ps_idle) { |
bf3dac5a FF |
147 | mod_timer(&sc->sleep_timer, jiffies + HZ / 10); |
148 | goto unlock; | |
149 | } | |
150 | ||
151 | if (sc->ps_enabled && | |
ad128860 SM |
152 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | |
153 | PS_WAIT_FOR_CAB | | |
154 | PS_WAIT_FOR_PSPOLL_DATA | | |
424749c7 RM |
155 | PS_WAIT_FOR_TX_ACK | |
156 | PS_WAIT_FOR_ANI))) { | |
c6c539f0 | 157 | mode = ATH9K_PM_NETWORK_SLEEP; |
08d4df41 RM |
158 | if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) |
159 | ath9k_btcoex_stop_gen_timer(sc); | |
ad128860 | 160 | } else { |
c6c539f0 | 161 | goto unlock; |
ad128860 | 162 | } |
c6c539f0 FF |
163 | |
164 | spin_lock(&common->cc_lock); | |
165 | ath_hw_cycle_counters_update(common); | |
166 | spin_unlock(&common->cc_lock); | |
167 | ||
1a8f0d39 | 168 | ath9k_hw_setpower(sc->sc_ah, mode); |
a91d75ae LR |
169 | |
170 | unlock: | |
171 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
172 | } | |
173 | ||
9adcf440 | 174 | static void __ath_cancel_work(struct ath_softc *sc) |
ff37e337 | 175 | { |
5ee08656 | 176 | cancel_work_sync(&sc->paprd_work); |
5ee08656 | 177 | cancel_delayed_work_sync(&sc->tx_complete_work); |
181fb18d | 178 | cancel_delayed_work_sync(&sc->hw_pll_work); |
fad29cd2 | 179 | |
bf52592f | 180 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
fad29cd2 SM |
181 | if (ath9k_hw_mci_is_enabled(sc->sc_ah)) |
182 | cancel_work_sync(&sc->mci_work); | |
bf52592f | 183 | #endif |
9adcf440 | 184 | } |
5ee08656 | 185 | |
e60001e7 | 186 | void ath_cancel_work(struct ath_softc *sc) |
9adcf440 FF |
187 | { |
188 | __ath_cancel_work(sc); | |
189 | cancel_work_sync(&sc->hw_reset_work); | |
190 | } | |
3cbb5dd7 | 191 | |
e60001e7 | 192 | void ath_restart_work(struct ath_softc *sc) |
af68abad | 193 | { |
af68abad SM |
194 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
195 | ||
19c36160 | 196 | if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah)) |
af68abad SM |
197 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, |
198 | msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); | |
199 | ||
da0d45f7 | 200 | ath_start_ani(sc); |
af68abad SM |
201 | } |
202 | ||
9ebea382 | 203 | static bool ath_prepare_reset(struct ath_softc *sc) |
9adcf440 FF |
204 | { |
205 | struct ath_hw *ah = sc->sc_ah; | |
ceea2a51 | 206 | bool ret = true; |
6a6733f2 | 207 | |
9adcf440 | 208 | ieee80211_stop_queues(sc->hw); |
da0d45f7 | 209 | ath_stop_ani(sc); |
9adcf440 | 210 | ath9k_hw_disable_interrupts(ah); |
8b3f4616 | 211 | |
1381559b | 212 | if (!ath_drain_all_txq(sc)) |
9adcf440 | 213 | ret = false; |
c0d7c7af | 214 | |
0a62acb1 | 215 | if (!ath_stoprecv(sc)) |
ceea2a51 FF |
216 | ret = false; |
217 | ||
9adcf440 FF |
218 | return ret; |
219 | } | |
ff37e337 | 220 | |
9adcf440 FF |
221 | static bool ath_complete_reset(struct ath_softc *sc, bool start) |
222 | { | |
223 | struct ath_hw *ah = sc->sc_ah; | |
224 | struct ath_common *common = ath9k_hw_common(ah); | |
196fb860 | 225 | unsigned long flags; |
c0d7c7af | 226 | |
9019f646 | 227 | ath9k_calculate_summary_state(sc, sc->cur_chan); |
19ec477f | 228 | ath_startrecv(sc); |
5048e8c3 | 229 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
bc7e1be7 | 230 | sc->cur_chan->txpower, &sc->curtxpow); |
eefa01dd | 231 | clear_bit(ATH_OP_HW_RESET, &common->op_flags); |
3989279c | 232 | |
fbbcd146 | 233 | if (!sc->cur_chan->offchannel && start) { |
8d7e09dd FF |
234 | /* restore per chanctx TSF timer */ |
235 | if (sc->cur_chan->tsf_val) { | |
236 | u32 offset; | |
237 | ||
238 | offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, | |
239 | NULL); | |
240 | ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset); | |
241 | } | |
242 | ||
243 | ||
eefa01dd | 244 | if (!test_bit(ATH_OP_BEACONS, &common->op_flags)) |
196fb860 SM |
245 | goto work; |
246 | ||
196fb860 | 247 | if (ah->opmode == NL80211_IFTYPE_STATION && |
eefa01dd | 248 | test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) { |
196fb860 SM |
249 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
250 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
251 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
a6768280 SM |
252 | } else { |
253 | ath9k_set_beacon(sc); | |
196fb860 SM |
254 | } |
255 | work: | |
af68abad | 256 | ath_restart_work(sc); |
0453531e | 257 | ath_txq_schedule_all(sc); |
5ee08656 FF |
258 | } |
259 | ||
071aa9a8 | 260 | sc->gtt_cnt = 0; |
9a9c4fbc RM |
261 | |
262 | ath9k_hw_set_interrupts(ah); | |
263 | ath9k_hw_enable_interrupts(ah); | |
264 | ||
499afacc | 265 | if (!ath9k_is_chanctx_enabled()) |
3ad9c386 | 266 | ieee80211_wake_queues(sc->hw); |
0e08b5fb SM |
267 | else |
268 | ath9k_chanctx_wake_queues(sc); | |
9adcf440 | 269 | |
d463af4a FF |
270 | ath9k_p2p_ps_timer(sc); |
271 | ||
9adcf440 FF |
272 | return true; |
273 | } | |
274 | ||
fbbcd146 | 275 | int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan) |
9adcf440 FF |
276 | { |
277 | struct ath_hw *ah = sc->sc_ah; | |
278 | struct ath_common *common = ath9k_hw_common(ah); | |
279 | struct ath9k_hw_cal_data *caldata = NULL; | |
280 | bool fastcc = true; | |
9adcf440 FF |
281 | int r; |
282 | ||
283 | __ath_cancel_work(sc); | |
284 | ||
4668cce5 | 285 | tasklet_disable(&sc->intr_tq); |
9adcf440 | 286 | spin_lock_bh(&sc->sc_pcu_lock); |
92460412 | 287 | |
fbbcd146 | 288 | if (!sc->cur_chan->offchannel) { |
9adcf440 | 289 | fastcc = false; |
b01459e8 | 290 | caldata = &sc->cur_chan->caldata; |
9adcf440 FF |
291 | } |
292 | ||
293 | if (!hchan) { | |
294 | fastcc = false; | |
9adcf440 FF |
295 | hchan = ah->curchan; |
296 | } | |
297 | ||
9ebea382 | 298 | if (!ath_prepare_reset(sc)) |
9adcf440 FF |
299 | fastcc = false; |
300 | ||
9ea3598b SM |
301 | if (ath9k_is_chanctx_enabled()) |
302 | fastcc = false; | |
303 | ||
d6067f0e RM |
304 | spin_lock_bh(&sc->chan_lock); |
305 | sc->cur_chandef = sc->cur_chan->chandef; | |
306 | spin_unlock_bh(&sc->chan_lock); | |
bff11766 | 307 | |
d2182b69 | 308 | ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", |
feced201 | 309 | hchan->channel, IS_CHAN_HT40(hchan), fastcc); |
9adcf440 FF |
310 | |
311 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); | |
312 | if (r) { | |
313 | ath_err(common, | |
314 | "Unable to reset channel, reset status %d\n", r); | |
f50b1cd3 RS |
315 | |
316 | ath9k_hw_enable_interrupts(ah); | |
317 | ath9k_queue_reset(sc, RESET_TYPE_BB_HANG); | |
318 | ||
9adcf440 FF |
319 | goto out; |
320 | } | |
321 | ||
e82cb03f | 322 | if (ath9k_hw_mci_is_enabled(sc->sc_ah) && |
fbbcd146 | 323 | sc->cur_chan->offchannel) |
e82cb03f RM |
324 | ath9k_mci_set_txpower(sc, true, false); |
325 | ||
9adcf440 FF |
326 | if (!ath_complete_reset(sc, true)) |
327 | r = -EIO; | |
328 | ||
329 | out: | |
6a6733f2 | 330 | spin_unlock_bh(&sc->sc_pcu_lock); |
4668cce5 FF |
331 | tasklet_enable(&sc->intr_tq); |
332 | ||
9adcf440 FF |
333 | return r; |
334 | } | |
335 | ||
7e1e3864 BG |
336 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, |
337 | struct ieee80211_vif *vif) | |
ff37e337 S |
338 | { |
339 | struct ath_node *an; | |
ff37e337 S |
340 | an = (struct ath_node *)sta->drv_priv; |
341 | ||
a145daf7 | 342 | an->sc = sc; |
7f010c93 | 343 | an->sta = sta; |
7e1e3864 | 344 | an->vif = vif; |
4bbf4414 | 345 | memset(&an->key_idx, 0, sizeof(an->key_idx)); |
3d4e20f2 | 346 | |
dd5ee59b | 347 | ath_tx_node_init(sc, an); |
ff37e337 S |
348 | } |
349 | ||
350 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
351 | { | |
352 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
dd5ee59b | 353 | ath_tx_node_cleanup(sc, an); |
ff37e337 S |
354 | } |
355 | ||
55624204 | 356 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
357 | { |
358 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 359 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 360 | struct ath_common *common = ath9k_hw_common(ah); |
124b979b | 361 | enum ath_reset_type type; |
07c15a3f | 362 | unsigned long flags; |
17d7904d | 363 | u32 status = sc->intrstatus; |
b5c80475 | 364 | u32 rxmask; |
ff37e337 | 365 | |
e3927007 FF |
366 | ath9k_ps_wakeup(sc); |
367 | spin_lock(&sc->sc_pcu_lock); | |
368 | ||
6549a860 SM |
369 | if (status & ATH9K_INT_FATAL) { |
370 | type = RESET_TYPE_FATAL_INT; | |
124b979b | 371 | ath9k_queue_reset(sc, type); |
c6cc47b1 SM |
372 | |
373 | /* | |
374 | * Increment the ref. counter here so that | |
375 | * interrupts are enabled in the reset routine. | |
376 | */ | |
377 | atomic_inc(&ah->intr_ref_cnt); | |
affad456 | 378 | ath_dbg(common, RESET, "FATAL: Skipping interrupts\n"); |
e3927007 | 379 | goto out; |
063d8be3 | 380 | } |
ff37e337 | 381 | |
6549a860 SM |
382 | if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && |
383 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
0c759977 SM |
384 | spin_lock(&common->cc_lock); |
385 | ath_hw_cycle_counters_update(common); | |
386 | ar9003_hw_bb_watchdog_dbg_info(ah); | |
387 | spin_unlock(&common->cc_lock); | |
388 | ||
6549a860 SM |
389 | if (ar9003_hw_bb_watchdog_check(ah)) { |
390 | type = RESET_TYPE_BB_WATCHDOG; | |
391 | ath9k_queue_reset(sc, type); | |
392 | ||
393 | /* | |
394 | * Increment the ref. counter here so that | |
395 | * interrupts are enabled in the reset routine. | |
396 | */ | |
397 | atomic_inc(&ah->intr_ref_cnt); | |
affad456 | 398 | ath_dbg(common, RESET, |
6549a860 SM |
399 | "BB_WATCHDOG: Skipping interrupts\n"); |
400 | goto out; | |
401 | } | |
402 | } | |
403 | ||
071aa9a8 SM |
404 | if (status & ATH9K_INT_GTT) { |
405 | sc->gtt_cnt++; | |
406 | ||
407 | if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) { | |
408 | type = RESET_TYPE_TX_GTT; | |
409 | ath9k_queue_reset(sc, type); | |
410 | atomic_inc(&ah->intr_ref_cnt); | |
affad456 | 411 | ath_dbg(common, RESET, |
071aa9a8 SM |
412 | "GTT: Skipping interrupts\n"); |
413 | goto out; | |
414 | } | |
415 | } | |
416 | ||
07c15a3f | 417 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
4105f807 RM |
418 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
419 | /* | |
420 | * TSF sync does not look correct; remain awake to sync with | |
421 | * the next Beacon. | |
422 | */ | |
d2182b69 | 423 | ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); |
e8fe7336 | 424 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
4105f807 | 425 | } |
07c15a3f | 426 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
4105f807 | 427 | |
b5c80475 FF |
428 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
429 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
430 | ATH9K_INT_RXORN); | |
431 | else | |
432 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
433 | ||
434 | if (status & rxmask) { | |
b5c80475 FF |
435 | /* Check for high priority Rx first */ |
436 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
437 | (status & ATH9K_INT_RXHP)) | |
438 | ath_rx_tasklet(sc, 0, true); | |
439 | ||
440 | ath_rx_tasklet(sc, 0, false); | |
ff37e337 S |
441 | } |
442 | ||
e5003249 | 443 | if (status & ATH9K_INT_TX) { |
071aa9a8 SM |
444 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
445 | /* | |
446 | * For EDMA chips, TX completion is enabled for the | |
447 | * beacon queue, so if a beacon has been transmitted | |
448 | * successfully after a GTT interrupt, the GTT counter | |
449 | * gets reset to zero here. | |
450 | */ | |
3b745c7b | 451 | sc->gtt_cnt = 0; |
071aa9a8 | 452 | |
e5003249 | 453 | ath_tx_edma_tasklet(sc); |
071aa9a8 | 454 | } else { |
e5003249 | 455 | ath_tx_tasklet(sc); |
071aa9a8 | 456 | } |
10e23181 FF |
457 | |
458 | wake_up(&sc->tx_wait); | |
e5003249 | 459 | } |
063d8be3 | 460 | |
c67ce339 FF |
461 | if (status & ATH9K_INT_GENTIMER) |
462 | ath_gen_timer_isr(sc->sc_ah); | |
463 | ||
56ca0dba | 464 | ath9k_btcoex_handle_interrupt(sc, status); |
19686ddf | 465 | |
ff37e337 | 466 | /* re-enable hardware interrupt */ |
4df3071e | 467 | ath9k_hw_enable_interrupts(ah); |
c6cc47b1 | 468 | out: |
52671e43 | 469 | spin_unlock(&sc->sc_pcu_lock); |
153e080d | 470 | ath9k_ps_restore(sc); |
ff37e337 S |
471 | } |
472 | ||
6baff7f9 | 473 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 474 | { |
063d8be3 S |
475 | #define SCHED_INTR ( \ |
476 | ATH9K_INT_FATAL | \ | |
a4d86d95 | 477 | ATH9K_INT_BB_WATCHDOG | \ |
063d8be3 S |
478 | ATH9K_INT_RXORN | \ |
479 | ATH9K_INT_RXEOL | \ | |
480 | ATH9K_INT_RX | \ | |
b5c80475 FF |
481 | ATH9K_INT_RXLP | \ |
482 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
483 | ATH9K_INT_TX | \ |
484 | ATH9K_INT_BMISS | \ | |
485 | ATH9K_INT_CST | \ | |
071aa9a8 | 486 | ATH9K_INT_GTT | \ |
ebb8e1d7 | 487 | ATH9K_INT_TSFOOR | \ |
40dc5392 MSS |
488 | ATH9K_INT_GENTIMER | \ |
489 | ATH9K_INT_MCI) | |
063d8be3 | 490 | |
ff37e337 | 491 | struct ath_softc *sc = dev; |
cbe61d8a | 492 | struct ath_hw *ah = sc->sc_ah; |
eefa01dd | 493 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 | 494 | enum ath9k_int status; |
78c8a950 | 495 | u32 sync_cause = 0; |
ff37e337 S |
496 | bool sched = false; |
497 | ||
063d8be3 S |
498 | /* |
499 | * The hardware is not ready/present, don't | |
500 | * touch anything. Note this can happen early | |
501 | * on if the IRQ is shared. | |
502 | */ | |
eefa01dd | 503 | if (test_bit(ATH_OP_INVALID, &common->op_flags)) |
063d8be3 | 504 | return IRQ_NONE; |
ff37e337 | 505 | |
063d8be3 S |
506 | /* shared irq, not for us */ |
507 | ||
153e080d | 508 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 509 | return IRQ_NONE; |
063d8be3 | 510 | |
eefa01dd | 511 | if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) { |
f41a9b3b | 512 | ath9k_hw_kill_interrupts(ah); |
b74713d0 | 513 | return IRQ_HANDLED; |
f41a9b3b | 514 | } |
b74713d0 | 515 | |
063d8be3 S |
516 | /* |
517 | * Figure out the reason(s) for the interrupt. Note | |
518 | * that the hal returns a pseudo-ISR that may include | |
519 | * bits we haven't explicitly enabled so we mask the | |
520 | * value to insure we only process bits we requested. | |
521 | */ | |
6a4d05dc FF |
522 | ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */ |
523 | ath9k_debug_sync_cause(sc, sync_cause); | |
3069168c | 524 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 525 | |
063d8be3 S |
526 | /* |
527 | * If there are no status bits set, then this interrupt was not | |
528 | * for me (should have been caught above). | |
529 | */ | |
153e080d | 530 | if (!status) |
063d8be3 | 531 | return IRQ_NONE; |
ff37e337 | 532 | |
063d8be3 S |
533 | /* Cache the status */ |
534 | sc->intrstatus = status; | |
535 | ||
536 | if (status & SCHED_INTR) | |
537 | sched = true; | |
538 | ||
539 | /* | |
540 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
541 | * chip immediately. | |
542 | */ | |
b5c80475 FF |
543 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
544 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
545 | goto chip_reset; |
546 | ||
a6bb860b | 547 | if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && |
0c759977 | 548 | (status & ATH9K_INT_BB_WATCHDOG)) |
08578b8f | 549 | goto chip_reset; |
e60001e7 SM |
550 | |
551 | #ifdef CONFIG_ATH9K_WOW | |
ca90ef44 RM |
552 | if (status & ATH9K_INT_BMISS) { |
553 | if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { | |
ca90ef44 RM |
554 | atomic_inc(&sc->wow_got_bmiss_intr); |
555 | atomic_dec(&sc->wow_sleep_proc_intr); | |
556 | } | |
557 | } | |
558 | #endif | |
e60001e7 | 559 | |
063d8be3 S |
560 | if (status & ATH9K_INT_SWBA) |
561 | tasklet_schedule(&sc->bcon_tasklet); | |
562 | ||
563 | if (status & ATH9K_INT_TXURN) | |
564 | ath9k_hw_updatetxtriglevel(ah, true); | |
565 | ||
0682c9b5 RM |
566 | if (status & ATH9K_INT_RXEOL) { |
567 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
72d874c6 | 568 | ath9k_hw_set_interrupts(ah); |
b5c80475 FF |
569 | } |
570 | ||
153e080d VT |
571 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
572 | if (status & ATH9K_INT_TIM_TIMER) { | |
ff9f0b63 LR |
573 | if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) |
574 | goto chip_reset; | |
063d8be3 S |
575 | /* Clear RxAbort bit so that we can |
576 | * receive frames */ | |
9ecdef4b | 577 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
07c15a3f | 578 | spin_lock(&sc->sc_pm_lock); |
153e080d | 579 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 580 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
07c15a3f | 581 | spin_unlock(&sc->sc_pm_lock); |
ff37e337 | 582 | } |
063d8be3 S |
583 | |
584 | chip_reset: | |
ff37e337 | 585 | |
817e11de S |
586 | ath_debug_stat_interrupt(sc, status); |
587 | ||
ff37e337 | 588 | if (sched) { |
4df3071e FF |
589 | /* turn off every interrupt */ |
590 | ath9k_hw_disable_interrupts(ah); | |
ff37e337 S |
591 | tasklet_schedule(&sc->intr_tq); |
592 | } | |
593 | ||
594 | return IRQ_HANDLED; | |
063d8be3 S |
595 | |
596 | #undef SCHED_INTR | |
ff37e337 S |
597 | } |
598 | ||
ef6b19e4 | 599 | int ath_reset(struct ath_softc *sc) |
ff37e337 | 600 | { |
ec30326e | 601 | int r; |
ff37e337 | 602 | |
783cd01e | 603 | ath9k_ps_wakeup(sc); |
1381559b | 604 | r = ath_reset_internal(sc, NULL); |
783cd01e | 605 | ath9k_ps_restore(sc); |
2ab81d4a | 606 | |
ae8d2858 | 607 | return r; |
ff37e337 S |
608 | } |
609 | ||
124b979b RM |
610 | void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) |
611 | { | |
eefa01dd | 612 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
124b979b RM |
613 | #ifdef CONFIG_ATH9K_DEBUGFS |
614 | RESET_STAT_INC(sc, type); | |
615 | #endif | |
eefa01dd | 616 | set_bit(ATH_OP_HW_RESET, &common->op_flags); |
124b979b RM |
617 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
618 | } | |
619 | ||
236de514 FF |
620 | void ath_reset_work(struct work_struct *work) |
621 | { | |
622 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); | |
623 | ||
1381559b | 624 | ath_reset(sc); |
236de514 FF |
625 | } |
626 | ||
ff37e337 S |
627 | /**********************/ |
628 | /* mac80211 callbacks */ | |
629 | /**********************/ | |
630 | ||
8feceb67 | 631 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 632 | { |
9ac58615 | 633 | struct ath_softc *sc = hw->priv; |
af03abec | 634 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 635 | struct ath_common *common = ath9k_hw_common(ah); |
39305635 | 636 | struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan; |
fbbcd146 | 637 | struct ath_chanctx *ctx = sc->cur_chan; |
ff37e337 | 638 | struct ath9k_channel *init_channel; |
82880a7c | 639 | int r; |
f078f209 | 640 | |
d2182b69 | 641 | ath_dbg(common, CONFIG, |
226afe68 JP |
642 | "Starting driver with initial channel: %d MHz\n", |
643 | curchan->center_freq); | |
f078f209 | 644 | |
f62d816f | 645 | ath9k_ps_wakeup(sc); |
141b38b6 S |
646 | mutex_lock(&sc->mutex); |
647 | ||
fbbcd146 | 648 | init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef); |
bff11766 | 649 | sc->cur_chandef = hw->conf.chandef; |
ff37e337 S |
650 | |
651 | /* Reset SERDES registers */ | |
84c87dc8 | 652 | ath9k_hw_configpcipowersave(ah, false); |
ff37e337 S |
653 | |
654 | /* | |
655 | * The basic interface to setting the hardware in a good | |
656 | * state is ``reset''. On return the hardware is known to | |
657 | * be powered up and with interrupts disabled. This must | |
658 | * be followed by initialization of the appropriate bits | |
659 | * and then setup of the interrupt mask. | |
660 | */ | |
4bdd1e97 | 661 | spin_lock_bh(&sc->sc_pcu_lock); |
c0c11741 FF |
662 | |
663 | atomic_set(&ah->intr_ref_cnt, -1); | |
664 | ||
20bd2a09 | 665 | r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); |
ae8d2858 | 666 | if (r) { |
3800276a JP |
667 | ath_err(common, |
668 | "Unable to reset hardware; reset status %d (freq %u MHz)\n", | |
669 | r, curchan->center_freq); | |
ceb26a60 | 670 | ah->reset_power_on = false; |
ff37e337 | 671 | } |
ff37e337 | 672 | |
ff37e337 | 673 | /* Setup our intr mask. */ |
b5c80475 FF |
674 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
675 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
676 | ATH9K_INT_GLOBAL; | |
677 | ||
678 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f | 679 | ah->imask |= ATH9K_INT_RXHP | |
a6bb860b | 680 | ATH9K_INT_RXLP; |
b5c80475 FF |
681 | else |
682 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 683 | |
a6bb860b SM |
684 | if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) |
685 | ah->imask |= ATH9K_INT_BB_WATCHDOG; | |
686 | ||
071aa9a8 SM |
687 | /* |
688 | * Enable GTT interrupts only for AR9003/AR9004 chips | |
689 | * for now. | |
690 | */ | |
691 | if (AR_SREV_9300_20_OR_LATER(ah)) | |
692 | ah->imask |= ATH9K_INT_GTT; | |
ff37e337 | 693 | |
af03abec | 694 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 695 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 696 | |
e270e776 | 697 | ath_mci_enable(sc); |
40dc5392 | 698 | |
eefa01dd | 699 | clear_bit(ATH_OP_INVALID, &common->op_flags); |
5f841b41 | 700 | sc->sc_ah->is_monitoring = false; |
ff37e337 | 701 | |
ceb26a60 FF |
702 | if (!ath_complete_reset(sc, false)) |
703 | ah->reset_power_on = false; | |
ff37e337 | 704 | |
c0c11741 FF |
705 | if (ah->led_pin >= 0) { |
706 | ath9k_hw_cfg_output(ah, ah->led_pin, | |
707 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
708 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); | |
709 | } | |
710 | ||
711 | /* | |
712 | * Reset key cache to sane defaults (all entries cleared) instead of | |
713 | * semi-random values after suspend/resume. | |
714 | */ | |
715 | ath9k_cmn_init_crypto(sc->sc_ah); | |
716 | ||
a35051ce FF |
717 | ath9k_hw_reset_tsf(ah); |
718 | ||
9adcf440 | 719 | spin_unlock_bh(&sc->sc_pcu_lock); |
164ace38 | 720 | |
141b38b6 S |
721 | mutex_unlock(&sc->mutex); |
722 | ||
f62d816f FF |
723 | ath9k_ps_restore(sc); |
724 | ||
ceb26a60 | 725 | return 0; |
f078f209 LR |
726 | } |
727 | ||
36323f81 TH |
728 | static void ath9k_tx(struct ieee80211_hw *hw, |
729 | struct ieee80211_tx_control *control, | |
730 | struct sk_buff *skb) | |
f078f209 | 731 | { |
9ac58615 | 732 | struct ath_softc *sc = hw->priv; |
c46917bb | 733 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 734 | struct ath_tx_control txctl; |
1bc14880 | 735 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
07c15a3f | 736 | unsigned long flags; |
528f0c6b | 737 | |
96148326 | 738 | if (sc->ps_enabled) { |
dc8c4585 JM |
739 | /* |
740 | * mac80211 does not set PM field for normal data frames, so we | |
741 | * need to update that based on the current PS mode. | |
742 | */ | |
743 | if (ieee80211_is_data(hdr->frame_control) && | |
744 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
745 | !ieee80211_has_pm(hdr->frame_control)) { | |
d2182b69 | 746 | ath_dbg(common, PS, |
226afe68 | 747 | "Add PM=1 for a TX frame while in PS mode\n"); |
dc8c4585 JM |
748 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
749 | } | |
750 | } | |
751 | ||
ad128860 | 752 | if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { |
9a23f9ca JM |
753 | /* |
754 | * We are using PS-Poll and mac80211 can request TX while in | |
755 | * power save mode. Need to wake up hardware for the TX to be | |
756 | * completed and if needed, also for RX of buffered frames. | |
757 | */ | |
9a23f9ca | 758 | ath9k_ps_wakeup(sc); |
07c15a3f | 759 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
fdf76622 VT |
760 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
761 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 762 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
d2182b69 | 763 | ath_dbg(common, PS, |
226afe68 | 764 | "Sending PS-Poll to pick a buffered frame\n"); |
1b04b930 | 765 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 766 | } else { |
d2182b69 | 767 | ath_dbg(common, PS, "Wake up to complete TX\n"); |
1b04b930 | 768 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
769 | } |
770 | /* | |
771 | * The actual restore operation will happen only after | |
ad128860 | 772 | * the ps_flags bit is cleared. We are just dropping |
9a23f9ca JM |
773 | * the ps_usecount here. |
774 | */ | |
07c15a3f | 775 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
9a23f9ca JM |
776 | ath9k_ps_restore(sc); |
777 | } | |
778 | ||
ad128860 SM |
779 | /* |
780 | * Cannot tx while the hardware is in full sleep, it first needs a full | |
781 | * chip reset to recover from that | |
782 | */ | |
783 | if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { | |
784 | ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); | |
785 | goto exit; | |
786 | } | |
787 | ||
528f0c6b | 788 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
066dae93 | 789 | txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; |
36323f81 | 790 | txctl.sta = control->sta; |
528f0c6b | 791 | |
d2182b69 | 792 | ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 793 | |
c52f33d0 | 794 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
d2182b69 | 795 | ath_dbg(common, XMIT, "TX failed\n"); |
a5a0bca1 | 796 | TX_STAT_INC(txctl.txq->axq_qnum, txfailed); |
528f0c6b | 797 | goto exit; |
8feceb67 VT |
798 | } |
799 | ||
7bb45683 | 800 | return; |
528f0c6b | 801 | exit: |
249ee722 | 802 | ieee80211_free_txskb(hw, skb); |
f078f209 LR |
803 | } |
804 | ||
8feceb67 | 805 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 806 | { |
9ac58615 | 807 | struct ath_softc *sc = hw->priv; |
af03abec | 808 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 809 | struct ath_common *common = ath9k_hw_common(ah); |
c0c11741 | 810 | bool prev_idle; |
f078f209 | 811 | |
ea22df29 SM |
812 | ath9k_deinit_channel_context(sc); |
813 | ||
4c483817 S |
814 | mutex_lock(&sc->mutex); |
815 | ||
9adcf440 | 816 | ath_cancel_work(sc); |
c94dbff7 | 817 | |
eefa01dd | 818 | if (test_bit(ATH_OP_INVALID, &common->op_flags)) { |
d2182b69 | 819 | ath_dbg(common, ANY, "Device not present\n"); |
4c483817 | 820 | mutex_unlock(&sc->mutex); |
9c84b797 S |
821 | return; |
822 | } | |
8feceb67 | 823 | |
3867cf6a S |
824 | /* Ensure HW is awake when we try to shut it down. */ |
825 | ath9k_ps_wakeup(sc); | |
826 | ||
6a6733f2 LR |
827 | spin_lock_bh(&sc->sc_pcu_lock); |
828 | ||
203043f5 SG |
829 | /* prevent tasklets to enable interrupts once we disable them */ |
830 | ah->imask &= ~ATH9K_INT_GLOBAL; | |
831 | ||
ff37e337 S |
832 | /* make sure h/w will not generate any interrupt |
833 | * before setting the invalid flag. */ | |
4df3071e | 834 | ath9k_hw_disable_interrupts(ah); |
ff37e337 | 835 | |
c0c11741 FF |
836 | spin_unlock_bh(&sc->sc_pcu_lock); |
837 | ||
838 | /* we can now sync irq and kill any running tasklets, since we already | |
839 | * disabled interrupts and not holding a spin lock */ | |
840 | synchronize_irq(sc->irq); | |
841 | tasklet_kill(&sc->intr_tq); | |
842 | tasklet_kill(&sc->bcon_tasklet); | |
843 | ||
844 | prev_idle = sc->ps_idle; | |
845 | sc->ps_idle = true; | |
846 | ||
847 | spin_lock_bh(&sc->sc_pcu_lock); | |
848 | ||
849 | if (ah->led_pin >= 0) { | |
850 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); | |
851 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
852 | } | |
853 | ||
9ebea382 | 854 | ath_prepare_reset(sc); |
ff37e337 | 855 | |
0d95521e FF |
856 | if (sc->rx.frag) { |
857 | dev_kfree_skb_any(sc->rx.frag); | |
858 | sc->rx.frag = NULL; | |
859 | } | |
860 | ||
c0c11741 | 861 | if (!ah->curchan) |
fbbcd146 FF |
862 | ah->curchan = ath9k_cmn_get_channel(hw, ah, |
863 | &sc->cur_chan->chandef); | |
6a6733f2 | 864 | |
c0c11741 FF |
865 | ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
866 | ath9k_hw_phy_disable(ah); | |
6a6733f2 | 867 | |
c0c11741 | 868 | ath9k_hw_configpcipowersave(ah, true); |
203043f5 | 869 | |
c0c11741 | 870 | spin_unlock_bh(&sc->sc_pcu_lock); |
3867cf6a | 871 | |
c0c11741 | 872 | ath9k_ps_restore(sc); |
ff37e337 | 873 | |
eefa01dd | 874 | set_bit(ATH_OP_INVALID, &common->op_flags); |
c0c11741 | 875 | sc->ps_idle = prev_idle; |
500c064d | 876 | |
141b38b6 S |
877 | mutex_unlock(&sc->mutex); |
878 | ||
d2182b69 | 879 | ath_dbg(common, CONFIG, "Driver halt\n"); |
f078f209 LR |
880 | } |
881 | ||
c648ecb0 | 882 | static bool ath9k_uses_beacons(int type) |
4801416c BG |
883 | { |
884 | switch (type) { | |
885 | case NL80211_IFTYPE_AP: | |
886 | case NL80211_IFTYPE_ADHOC: | |
887 | case NL80211_IFTYPE_MESH_POINT: | |
888 | return true; | |
889 | default: | |
890 | return false; | |
891 | } | |
892 | } | |
893 | ||
4b93fd29 SM |
894 | static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data, |
895 | u8 *mac, struct ieee80211_vif *vif) | |
4801416c | 896 | { |
4801416c BG |
897 | int i; |
898 | ||
ab11bb28 | 899 | if (iter_data->has_hw_macaddr) { |
4801416c BG |
900 | for (i = 0; i < ETH_ALEN; i++) |
901 | iter_data->mask[i] &= | |
902 | ~(iter_data->hw_macaddr[i] ^ mac[i]); | |
ab11bb28 FF |
903 | } else { |
904 | memcpy(iter_data->hw_macaddr, mac, ETH_ALEN); | |
905 | iter_data->has_hw_macaddr = true; | |
906 | } | |
141b38b6 | 907 | |
9a9c4fbc RM |
908 | if (!vif->bss_conf.use_short_slot) |
909 | iter_data->slottime = ATH9K_SLOT_TIME_20; | |
910 | ||
1ed32e4f | 911 | switch (vif->type) { |
4801416c BG |
912 | case NL80211_IFTYPE_AP: |
913 | iter_data->naps++; | |
f078f209 | 914 | break; |
4801416c BG |
915 | case NL80211_IFTYPE_STATION: |
916 | iter_data->nstations++; | |
9a9c4fbc RM |
917 | if (vif->bss_conf.assoc && !iter_data->primary_sta) |
918 | iter_data->primary_sta = vif; | |
e51f3eff | 919 | break; |
05c914fe | 920 | case NL80211_IFTYPE_ADHOC: |
4801416c | 921 | iter_data->nadhocs++; |
9a9c4fbc RM |
922 | if (vif->bss_conf.enable_beacon) |
923 | iter_data->beacons = true; | |
4801416c | 924 | break; |
9cb5412b | 925 | case NL80211_IFTYPE_MESH_POINT: |
4801416c | 926 | iter_data->nmeshes++; |
9a9c4fbc RM |
927 | if (vif->bss_conf.enable_beacon) |
928 | iter_data->beacons = true; | |
4801416c BG |
929 | break; |
930 | case NL80211_IFTYPE_WDS: | |
931 | iter_data->nwds++; | |
f078f209 LR |
932 | break; |
933 | default: | |
4801416c | 934 | break; |
f078f209 | 935 | } |
4801416c | 936 | } |
f078f209 | 937 | |
4801416c | 938 | /* Called with sc->mutex held. */ |
9a9c4fbc RM |
939 | void ath9k_calculate_iter_data(struct ath_softc *sc, |
940 | struct ath_chanctx *ctx, | |
4801416c BG |
941 | struct ath9k_vif_iter_data *iter_data) |
942 | { | |
9a9c4fbc | 943 | struct ath_vif *avp; |
8feceb67 | 944 | |
4801416c | 945 | /* |
657eb17d MV |
946 | * Pick the MAC address of the first interface as the new hardware |
947 | * MAC address. The hardware will use it together with the BSSID mask | |
948 | * when matching addresses. | |
4801416c BG |
949 | */ |
950 | memset(iter_data, 0, sizeof(*iter_data)); | |
4801416c | 951 | memset(&iter_data->mask, 0xff, ETH_ALEN); |
9a9c4fbc RM |
952 | iter_data->slottime = ATH9K_SLOT_TIME_9; |
953 | ||
954 | list_for_each_entry(avp, &ctx->vifs, list) | |
955 | ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif); | |
9a9c4fbc RM |
956 | } |
957 | ||
958 | static void ath9k_set_assoc_state(struct ath_softc *sc, | |
959 | struct ieee80211_vif *vif, bool changed) | |
960 | { | |
961 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
962 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; | |
963 | unsigned long flags; | |
964 | ||
965 | set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); | |
9a9c4fbc RM |
966 | |
967 | ether_addr_copy(common->curbssid, bss_conf->bssid); | |
968 | common->curaid = bss_conf->aid; | |
969 | ath9k_hw_write_associd(sc->sc_ah); | |
970 | ||
971 | if (changed) { | |
972 | common->last_rssi = ATH_RSSI_DUMMY_MARKER; | |
973 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; | |
5640b08e | 974 | |
9a9c4fbc RM |
975 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
976 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
977 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
978 | } | |
4801416c | 979 | |
9a9c4fbc RM |
980 | if (ath9k_hw_mci_is_enabled(sc->sc_ah)) |
981 | ath9k_mci_update_wlan_channels(sc, false); | |
ab11bb28 | 982 | |
9a9c4fbc RM |
983 | ath_dbg(common, CONFIG, |
984 | "Primary Station interface: %pM, BSSID: %pM\n", | |
985 | vif->addr, common->curbssid); | |
4801416c | 986 | } |
8ca21f01 | 987 | |
4ee26de1 SM |
988 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
989 | static void ath9k_set_offchannel_state(struct ath_softc *sc) | |
990 | { | |
991 | struct ath_hw *ah = sc->sc_ah; | |
992 | struct ath_common *common = ath9k_hw_common(ah); | |
993 | struct ieee80211_vif *vif = NULL; | |
994 | ||
995 | ath9k_ps_wakeup(sc); | |
996 | ||
997 | if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START) | |
998 | vif = sc->offchannel.scan_vif; | |
999 | else | |
1000 | vif = sc->offchannel.roc_vif; | |
1001 | ||
1002 | if (WARN_ON(!vif)) | |
1003 | goto exit; | |
1004 | ||
1005 | eth_zero_addr(common->curbssid); | |
1006 | eth_broadcast_addr(common->bssidmask); | |
1007 | ether_addr_copy(common->macaddr, vif->addr); | |
1008 | common->curaid = 0; | |
1009 | ah->opmode = vif->type; | |
1010 | ah->imask &= ~ATH9K_INT_SWBA; | |
1011 | ah->imask &= ~ATH9K_INT_TSFOOR; | |
1012 | ah->slottime = ATH9K_SLOT_TIME_9; | |
1013 | ||
1014 | ath_hw_setbssidmask(common); | |
1015 | ath9k_hw_setopmode(ah); | |
1016 | ath9k_hw_write_associd(sc->sc_ah); | |
1017 | ath9k_hw_set_interrupts(ah); | |
1018 | ath9k_hw_init_global_settings(ah); | |
1019 | ||
1020 | exit: | |
1021 | ath9k_ps_restore(sc); | |
1022 | } | |
1023 | #endif | |
1024 | ||
4801416c | 1025 | /* Called with sc->mutex held. */ |
9a9c4fbc RM |
1026 | void ath9k_calculate_summary_state(struct ath_softc *sc, |
1027 | struct ath_chanctx *ctx) | |
4801416c | 1028 | { |
4801416c BG |
1029 | struct ath_hw *ah = sc->sc_ah; |
1030 | struct ath_common *common = ath9k_hw_common(ah); | |
1031 | struct ath9k_vif_iter_data iter_data; | |
9bf30ff9 | 1032 | struct ath_beacon_config *cur_conf; |
8ca21f01 | 1033 | |
9a9c4fbc RM |
1034 | ath_chanctx_check_active(sc, ctx); |
1035 | ||
1036 | if (ctx != sc->cur_chan) | |
1037 | return; | |
1038 | ||
4ee26de1 SM |
1039 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
1040 | if (ctx == &sc->offchannel.chan) | |
1041 | return ath9k_set_offchannel_state(sc); | |
1042 | #endif | |
1043 | ||
9a9c4fbc RM |
1044 | ath9k_ps_wakeup(sc); |
1045 | ath9k_calculate_iter_data(sc, ctx, &iter_data); | |
1046 | ||
1047 | if (iter_data.has_hw_macaddr) | |
1048 | ether_addr_copy(common->macaddr, iter_data.hw_macaddr); | |
2c3db3d5 | 1049 | |
4801416c BG |
1050 | memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); |
1051 | ath_hw_setbssidmask(common); | |
1052 | ||
4801416c | 1053 | if (iter_data.naps > 0) { |
9bf30ff9 | 1054 | cur_conf = &ctx->beacon; |
60ca9f87 | 1055 | ath9k_hw_set_tsfadjust(ah, true); |
4801416c | 1056 | ah->opmode = NL80211_IFTYPE_AP; |
9bf30ff9 SM |
1057 | if (cur_conf->enable_beacon) |
1058 | iter_data.beacons = true; | |
4801416c | 1059 | } else { |
60ca9f87 | 1060 | ath9k_hw_set_tsfadjust(ah, false); |
5640b08e | 1061 | |
fd5999cf JC |
1062 | if (iter_data.nmeshes) |
1063 | ah->opmode = NL80211_IFTYPE_MESH_POINT; | |
1064 | else if (iter_data.nwds) | |
4801416c BG |
1065 | ah->opmode = NL80211_IFTYPE_AP; |
1066 | else if (iter_data.nadhocs) | |
1067 | ah->opmode = NL80211_IFTYPE_ADHOC; | |
1068 | else | |
1069 | ah->opmode = NL80211_IFTYPE_STATION; | |
1070 | } | |
5640b08e | 1071 | |
df35d29e SM |
1072 | ath9k_hw_setopmode(ah); |
1073 | ||
748299f2 | 1074 | ctx->switch_after_beacon = false; |
198823fd | 1075 | if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) |
3069168c | 1076 | ah->imask |= ATH9K_INT_TSFOOR; |
748299f2 | 1077 | else { |
4801416c | 1078 | ah->imask &= ~ATH9K_INT_TSFOOR; |
748299f2 FF |
1079 | if (iter_data.naps == 1 && iter_data.beacons) |
1080 | ctx->switch_after_beacon = true; | |
1081 | } | |
4af9cf4f | 1082 | |
9a9c4fbc RM |
1083 | ah->imask &= ~ATH9K_INT_SWBA; |
1084 | if (ah->opmode == NL80211_IFTYPE_STATION) { | |
1085 | bool changed = (iter_data.primary_sta != ctx->primary_sta); | |
1086 | ||
9a9c4fbc | 1087 | if (iter_data.primary_sta) { |
602607b6 | 1088 | iter_data.beacons = true; |
9a9c4fbc RM |
1089 | ath9k_set_assoc_state(sc, iter_data.primary_sta, |
1090 | changed); | |
1030f9fe | 1091 | ctx->primary_sta = iter_data.primary_sta; |
9a9c4fbc RM |
1092 | } else { |
1093 | ctx->primary_sta = NULL; | |
1094 | memset(common->curbssid, 0, ETH_ALEN); | |
1095 | common->curaid = 0; | |
1096 | ath9k_hw_write_associd(sc->sc_ah); | |
1097 | if (ath9k_hw_mci_is_enabled(sc->sc_ah)) | |
1098 | ath9k_mci_update_wlan_channels(sc, true); | |
1099 | } | |
1100 | } else if (iter_data.beacons) { | |
1101 | ah->imask |= ATH9K_INT_SWBA; | |
1102 | } | |
72d874c6 | 1103 | ath9k_hw_set_interrupts(ah); |
6dcc3444 | 1104 | |
9a9c4fbc RM |
1105 | if (iter_data.beacons) |
1106 | set_bit(ATH_OP_BEACONS, &common->op_flags); | |
1107 | else | |
1108 | clear_bit(ATH_OP_BEACONS, &common->op_flags); | |
1109 | ||
1110 | if (ah->slottime != iter_data.slottime) { | |
1111 | ah->slottime = iter_data.slottime; | |
1112 | ath9k_hw_init_global_settings(ah); | |
6dcc3444 | 1113 | } |
9a9c4fbc RM |
1114 | |
1115 | if (iter_data.primary_sta) | |
1116 | set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); | |
1117 | else | |
1118 | clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); | |
1119 | ||
9a9c4fbc | 1120 | ath9k_ps_restore(sc); |
4801416c | 1121 | } |
6f255425 | 1122 | |
a4027644 SM |
1123 | static void ath9k_assign_hw_queues(struct ieee80211_hw *hw, |
1124 | struct ieee80211_vif *vif) | |
1125 | { | |
1126 | int i; | |
1127 | ||
1128 | for (i = 0; i < IEEE80211_NUM_ACS; i++) | |
1129 | vif->hw_queue[i] = i; | |
1130 | ||
1131 | if (vif->type == NL80211_IFTYPE_AP) | |
1132 | vif->cab_queue = hw->queues - 2; | |
1133 | else | |
1134 | vif->cab_queue = IEEE80211_INVAL_HW_QUEUE; | |
1135 | } | |
1136 | ||
4801416c BG |
1137 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
1138 | struct ieee80211_vif *vif) | |
6b3b991d | 1139 | { |
9ac58615 | 1140 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1141 | struct ath_hw *ah = sc->sc_ah; |
1142 | struct ath_common *common = ath9k_hw_common(ah); | |
f89d1bc4 FF |
1143 | struct ath_vif *avp = (void *)vif->drv_priv; |
1144 | struct ath_node *an = &avp->mcast_node; | |
6b3b991d | 1145 | |
4801416c | 1146 | mutex_lock(&sc->mutex); |
6b3b991d | 1147 | |
89f927af | 1148 | if (config_enabled(CONFIG_ATH9K_TX99)) { |
ca529c93 | 1149 | if (sc->cur_chan->nvifs >= 1) { |
89f927af LR |
1150 | mutex_unlock(&sc->mutex); |
1151 | return -EOPNOTSUPP; | |
1152 | } | |
1153 | sc->tx99_vif = vif; | |
1154 | } | |
1155 | ||
d2182b69 | 1156 | ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); |
ca529c93 | 1157 | sc->cur_chan->nvifs++; |
4801416c | 1158 | |
130ef6e9 SM |
1159 | if (ath9k_uses_beacons(vif->type)) |
1160 | ath9k_beacon_assign_slot(sc, vif); | |
1161 | ||
d463af4a | 1162 | avp->vif = vif; |
499afacc | 1163 | if (!ath9k_is_chanctx_enabled()) { |
39305635 | 1164 | avp->chanctx = sc->cur_chan; |
9a9c4fbc RM |
1165 | list_add_tail(&avp->list, &avp->chanctx->vifs); |
1166 | } | |
a4027644 SM |
1167 | |
1168 | ath9k_assign_hw_queues(hw, vif); | |
0453531e | 1169 | |
f89d1bc4 FF |
1170 | an->sc = sc; |
1171 | an->sta = NULL; | |
1172 | an->vif = vif; | |
1173 | an->no_ps_filter = true; | |
1174 | ath_tx_node_init(sc, an); | |
1175 | ||
4801416c | 1176 | mutex_unlock(&sc->mutex); |
327967cb | 1177 | return 0; |
6b3b991d RM |
1178 | } |
1179 | ||
1180 | static int ath9k_change_interface(struct ieee80211_hw *hw, | |
1181 | struct ieee80211_vif *vif, | |
1182 | enum nl80211_iftype new_type, | |
1183 | bool p2p) | |
1184 | { | |
9ac58615 | 1185 | struct ath_softc *sc = hw->priv; |
6b3b991d | 1186 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
c083ce99 | 1187 | struct ath_vif *avp = (void *)vif->drv_priv; |
6b3b991d | 1188 | |
6b3b991d | 1189 | mutex_lock(&sc->mutex); |
4801416c | 1190 | |
89f927af LR |
1191 | if (config_enabled(CONFIG_ATH9K_TX99)) { |
1192 | mutex_unlock(&sc->mutex); | |
1193 | return -EOPNOTSUPP; | |
1194 | } | |
1195 | ||
1196 | ath_dbg(common, CONFIG, "Change Interface\n"); | |
1197 | ||
4801416c | 1198 | if (ath9k_uses_beacons(vif->type)) |
130ef6e9 | 1199 | ath9k_beacon_remove_slot(sc, vif); |
4801416c | 1200 | |
6b3b991d RM |
1201 | vif->type = new_type; |
1202 | vif->p2p = p2p; | |
1203 | ||
130ef6e9 SM |
1204 | if (ath9k_uses_beacons(vif->type)) |
1205 | ath9k_beacon_assign_slot(sc, vif); | |
9a9c4fbc | 1206 | |
a4027644 | 1207 | ath9k_assign_hw_queues(hw, vif); |
9a9c4fbc | 1208 | ath9k_calculate_summary_state(sc, avp->chanctx); |
130ef6e9 | 1209 | |
6b3b991d | 1210 | mutex_unlock(&sc->mutex); |
327967cb | 1211 | return 0; |
6b3b991d RM |
1212 | } |
1213 | ||
8feceb67 | 1214 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1215 | struct ieee80211_vif *vif) |
f078f209 | 1216 | { |
9ac58615 | 1217 | struct ath_softc *sc = hw->priv; |
c46917bb | 1218 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
f89d1bc4 | 1219 | struct ath_vif *avp = (void *)vif->drv_priv; |
f078f209 | 1220 | |
d2182b69 | 1221 | ath_dbg(common, CONFIG, "Detach Interface\n"); |
f078f209 | 1222 | |
141b38b6 S |
1223 | mutex_lock(&sc->mutex); |
1224 | ||
c7dd40c9 | 1225 | ath9k_p2p_remove_vif(sc, vif); |
d463af4a | 1226 | |
ca529c93 | 1227 | sc->cur_chan->nvifs--; |
89f927af | 1228 | sc->tx99_vif = NULL; |
499afacc | 1229 | if (!ath9k_is_chanctx_enabled()) |
9a9c4fbc | 1230 | list_del(&avp->list); |
580f0b8a | 1231 | |
4801416c | 1232 | if (ath9k_uses_beacons(vif->type)) |
130ef6e9 | 1233 | ath9k_beacon_remove_slot(sc, vif); |
2c3db3d5 | 1234 | |
f89d1bc4 FF |
1235 | ath_tx_node_cleanup(sc, &avp->mcast_node); |
1236 | ||
141b38b6 | 1237 | mutex_unlock(&sc->mutex); |
f078f209 LR |
1238 | } |
1239 | ||
fbab7390 | 1240 | static void ath9k_enable_ps(struct ath_softc *sc) |
3f7c5c10 | 1241 | { |
3069168c | 1242 | struct ath_hw *ah = sc->sc_ah; |
ad128860 | 1243 | struct ath_common *common = ath9k_hw_common(ah); |
3069168c | 1244 | |
89f927af LR |
1245 | if (config_enabled(CONFIG_ATH9K_TX99)) |
1246 | return; | |
1247 | ||
3f7c5c10 | 1248 | sc->ps_enabled = true; |
3069168c PR |
1249 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1250 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1251 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
72d874c6 | 1252 | ath9k_hw_set_interrupts(ah); |
3f7c5c10 | 1253 | } |
fdf76622 | 1254 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1255 | } |
ad128860 | 1256 | ath_dbg(common, PS, "PowerSave enabled\n"); |
3f7c5c10 SB |
1257 | } |
1258 | ||
845d708e SB |
1259 | static void ath9k_disable_ps(struct ath_softc *sc) |
1260 | { | |
1261 | struct ath_hw *ah = sc->sc_ah; | |
ad128860 | 1262 | struct ath_common *common = ath9k_hw_common(ah); |
845d708e | 1263 | |
89f927af LR |
1264 | if (config_enabled(CONFIG_ATH9K_TX99)) |
1265 | return; | |
1266 | ||
845d708e SB |
1267 | sc->ps_enabled = false; |
1268 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
1269 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | |
1270 | ath9k_hw_setrxabort(ah, 0); | |
1271 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | | |
1272 | PS_WAIT_FOR_CAB | | |
1273 | PS_WAIT_FOR_PSPOLL_DATA | | |
1274 | PS_WAIT_FOR_TX_ACK); | |
1275 | if (ah->imask & ATH9K_INT_TIM_TIMER) { | |
1276 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
72d874c6 | 1277 | ath9k_hw_set_interrupts(ah); |
845d708e SB |
1278 | } |
1279 | } | |
ad128860 | 1280 | ath_dbg(common, PS, "PowerSave disabled\n"); |
845d708e SB |
1281 | } |
1282 | ||
e93d083f SW |
1283 | void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw) |
1284 | { | |
1285 | struct ath_softc *sc = hw->priv; | |
1286 | struct ath_hw *ah = sc->sc_ah; | |
1287 | struct ath_common *common = ath9k_hw_common(ah); | |
1288 | u32 rxfilter; | |
1289 | ||
89f927af LR |
1290 | if (config_enabled(CONFIG_ATH9K_TX99)) |
1291 | return; | |
1292 | ||
e93d083f SW |
1293 | if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { |
1294 | ath_err(common, "spectrum analyzer not implemented on this hardware\n"); | |
1295 | return; | |
1296 | } | |
1297 | ||
1298 | ath9k_ps_wakeup(sc); | |
1299 | rxfilter = ath9k_hw_getrxfilter(ah); | |
1300 | ath9k_hw_setrxfilter(ah, rxfilter | | |
1301 | ATH9K_RX_FILTER_PHYRADAR | | |
1302 | ATH9K_RX_FILTER_PHYERR); | |
1303 | ||
1304 | /* TODO: usually this should not be neccesary, but for some reason | |
1305 | * (or in some mode?) the trigger must be called after the | |
1306 | * configuration, otherwise the register will have its values reset | |
1307 | * (on my ar9220 to value 0x01002310) | |
1308 | */ | |
1309 | ath9k_spectral_scan_config(hw, sc->spectral_mode); | |
1310 | ath9k_hw_ops(ah)->spectral_scan_trigger(ah); | |
1311 | ath9k_ps_restore(sc); | |
1312 | } | |
1313 | ||
1314 | int ath9k_spectral_scan_config(struct ieee80211_hw *hw, | |
1315 | enum spectral_mode spectral_mode) | |
1316 | { | |
1317 | struct ath_softc *sc = hw->priv; | |
1318 | struct ath_hw *ah = sc->sc_ah; | |
1319 | struct ath_common *common = ath9k_hw_common(ah); | |
e93d083f SW |
1320 | |
1321 | if (!ath9k_hw_ops(ah)->spectral_scan_trigger) { | |
1322 | ath_err(common, "spectrum analyzer not implemented on this hardware\n"); | |
1323 | return -1; | |
1324 | } | |
1325 | ||
e93d083f SW |
1326 | switch (spectral_mode) { |
1327 | case SPECTRAL_DISABLED: | |
04ccd4a1 | 1328 | sc->spec_config.enabled = 0; |
e93d083f SW |
1329 | break; |
1330 | case SPECTRAL_BACKGROUND: | |
1331 | /* send endless samples. | |
1332 | * TODO: is this really useful for "background"? | |
1333 | */ | |
04ccd4a1 SW |
1334 | sc->spec_config.endless = 1; |
1335 | sc->spec_config.enabled = 1; | |
e93d083f SW |
1336 | break; |
1337 | case SPECTRAL_CHANSCAN: | |
e93d083f | 1338 | case SPECTRAL_MANUAL: |
04ccd4a1 SW |
1339 | sc->spec_config.endless = 0; |
1340 | sc->spec_config.enabled = 1; | |
e93d083f SW |
1341 | break; |
1342 | default: | |
1343 | return -1; | |
1344 | } | |
1345 | ||
1346 | ath9k_ps_wakeup(sc); | |
04ccd4a1 | 1347 | ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config); |
e93d083f SW |
1348 | ath9k_ps_restore(sc); |
1349 | ||
1350 | sc->spectral_mode = spectral_mode; | |
1351 | ||
1352 | return 0; | |
1353 | } | |
1354 | ||
e8975581 | 1355 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1356 | { |
9ac58615 | 1357 | struct ath_softc *sc = hw->priv; |
3430098a FF |
1358 | struct ath_hw *ah = sc->sc_ah; |
1359 | struct ath_common *common = ath9k_hw_common(ah); | |
e8975581 | 1360 | struct ieee80211_conf *conf = &hw->conf; |
fbbcd146 | 1361 | struct ath_chanctx *ctx = sc->cur_chan; |
f078f209 | 1362 | |
c0c11741 | 1363 | ath9k_ps_wakeup(sc); |
aa33de09 | 1364 | mutex_lock(&sc->mutex); |
141b38b6 | 1365 | |
daa1b6ee | 1366 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
7545daf4 | 1367 | sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); |
b73f3e78 | 1368 | if (sc->ps_idle) { |
daa1b6ee | 1369 | ath_cancel_work(sc); |
b73f3e78 RM |
1370 | ath9k_stop_btcoex(sc); |
1371 | } else { | |
1372 | ath9k_start_btcoex(sc); | |
75600abf FF |
1373 | /* |
1374 | * The chip needs a reset to properly wake up from | |
1375 | * full sleep | |
1376 | */ | |
39305635 | 1377 | ath_chanctx_set_channel(sc, ctx, &ctx->chandef); |
b73f3e78 | 1378 | } |
daa1b6ee | 1379 | } |
64839170 | 1380 | |
e7824a50 LR |
1381 | /* |
1382 | * We just prepare to enable PS. We have to wait until our AP has | |
1383 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1384 | * those ACKs and end up retransmitting the same null data frames. | |
1385 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1386 | */ | |
3cbb5dd7 | 1387 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
8ab2cd09 LR |
1388 | unsigned long flags; |
1389 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
fbab7390 SB |
1390 | if (conf->flags & IEEE80211_CONF_PS) |
1391 | ath9k_enable_ps(sc); | |
845d708e SB |
1392 | else |
1393 | ath9k_disable_ps(sc); | |
8ab2cd09 | 1394 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
3cbb5dd7 VN |
1395 | } |
1396 | ||
199afd9d S |
1397 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1398 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
d2182b69 | 1399 | ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); |
5f841b41 RM |
1400 | sc->sc_ah->is_monitoring = true; |
1401 | } else { | |
d2182b69 | 1402 | ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); |
5f841b41 | 1403 | sc->sc_ah->is_monitoring = false; |
199afd9d S |
1404 | } |
1405 | } | |
1406 | ||
499afacc | 1407 | if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) { |
fbbcd146 | 1408 | ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL); |
bff11766 | 1409 | ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef); |
094d05dc | 1410 | } |
f078f209 | 1411 | |
c9f6a656 | 1412 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
d2182b69 | 1413 | ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); |
bc7e1be7 | 1414 | sc->cur_chan->txpower = 2 * conf->power_level; |
5048e8c3 | 1415 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
bc7e1be7 | 1416 | sc->cur_chan->txpower, &sc->curtxpow); |
64839170 LR |
1417 | } |
1418 | ||
aa33de09 | 1419 | mutex_unlock(&sc->mutex); |
c0c11741 | 1420 | ath9k_ps_restore(sc); |
141b38b6 | 1421 | |
f078f209 LR |
1422 | return 0; |
1423 | } | |
1424 | ||
8feceb67 VT |
1425 | #define SUPPORTED_FILTERS \ |
1426 | (FIF_PROMISC_IN_BSS | \ | |
1427 | FIF_ALLMULTI | \ | |
1428 | FIF_CONTROL | \ | |
af6a3fc7 | 1429 | FIF_PSPOLL | \ |
8feceb67 VT |
1430 | FIF_OTHER_BSS | \ |
1431 | FIF_BCN_PRBRESP_PROMISC | \ | |
9c1d8e4a | 1432 | FIF_PROBE_REQ | \ |
8feceb67 | 1433 | FIF_FCSFAIL) |
c83be688 | 1434 | |
8feceb67 VT |
1435 | /* FIXME: sc->sc_full_reset ? */ |
1436 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1437 | unsigned int changed_flags, | |
1438 | unsigned int *total_flags, | |
3ac64bee | 1439 | u64 multicast) |
8feceb67 | 1440 | { |
9ac58615 | 1441 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1442 | u32 rfilt; |
f078f209 | 1443 | |
8feceb67 VT |
1444 | changed_flags &= SUPPORTED_FILTERS; |
1445 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1446 | |
fce34430 SM |
1447 | spin_lock_bh(&sc->chan_lock); |
1448 | sc->cur_chan->rxfilter = *total_flags; | |
1449 | spin_unlock_bh(&sc->chan_lock); | |
1450 | ||
aa68aeaa | 1451 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1452 | rfilt = ath_calcrxfilter(sc); |
1453 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1454 | ath9k_ps_restore(sc); |
f078f209 | 1455 | |
d2182b69 JP |
1456 | ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", |
1457 | rfilt); | |
8feceb67 | 1458 | } |
f078f209 | 1459 | |
4ca77860 JB |
1460 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1461 | struct ieee80211_vif *vif, | |
1462 | struct ieee80211_sta *sta) | |
8feceb67 | 1463 | { |
9ac58615 | 1464 | struct ath_softc *sc = hw->priv; |
93ae2dd2 FF |
1465 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1466 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1467 | struct ieee80211_key_conf ps_key = { }; | |
4ef69d03 | 1468 | int key; |
f078f209 | 1469 | |
7e1e3864 | 1470 | ath_node_attach(sc, sta, vif); |
f59a59fe FF |
1471 | |
1472 | if (vif->type != NL80211_IFTYPE_AP && | |
1473 | vif->type != NL80211_IFTYPE_AP_VLAN) | |
1474 | return 0; | |
1475 | ||
4ef69d03 | 1476 | key = ath_key_config(common, vif, sta, &ps_key); |
4bbf4414 | 1477 | if (key > 0) { |
4ef69d03 | 1478 | an->ps_key = key; |
4bbf4414 RM |
1479 | an->key_idx[0] = key; |
1480 | } | |
4ca77860 JB |
1481 | |
1482 | return 0; | |
1483 | } | |
1484 | ||
93ae2dd2 FF |
1485 | static void ath9k_del_ps_key(struct ath_softc *sc, |
1486 | struct ieee80211_vif *vif, | |
1487 | struct ieee80211_sta *sta) | |
1488 | { | |
1489 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1490 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1491 | struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; | |
1492 | ||
1493 | if (!an->ps_key) | |
1494 | return; | |
1495 | ||
1496 | ath_key_delete(common, &ps_key); | |
4ef69d03 | 1497 | an->ps_key = 0; |
4bbf4414 | 1498 | an->key_idx[0] = 0; |
93ae2dd2 FF |
1499 | } |
1500 | ||
4ca77860 JB |
1501 | static int ath9k_sta_remove(struct ieee80211_hw *hw, |
1502 | struct ieee80211_vif *vif, | |
1503 | struct ieee80211_sta *sta) | |
1504 | { | |
9ac58615 | 1505 | struct ath_softc *sc = hw->priv; |
4ca77860 | 1506 | |
93ae2dd2 | 1507 | ath9k_del_ps_key(sc, vif, sta); |
4ca77860 JB |
1508 | ath_node_detach(sc, sta); |
1509 | ||
1510 | return 0; | |
f078f209 LR |
1511 | } |
1512 | ||
4bbf4414 RM |
1513 | static void ath9k_sta_set_tx_filter(struct ath_hw *ah, |
1514 | struct ath_node *an, | |
1515 | bool set) | |
1516 | { | |
1517 | int i; | |
1518 | ||
1519 | for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { | |
1520 | if (!an->key_idx[i]) | |
1521 | continue; | |
1522 | ath9k_hw_set_tx_filter(ah, an->key_idx[i], set); | |
1523 | } | |
1524 | } | |
1525 | ||
5519541d FF |
1526 | static void ath9k_sta_notify(struct ieee80211_hw *hw, |
1527 | struct ieee80211_vif *vif, | |
1528 | enum sta_notify_cmd cmd, | |
1529 | struct ieee80211_sta *sta) | |
1530 | { | |
1531 | struct ath_softc *sc = hw->priv; | |
1532 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1533 | ||
1534 | switch (cmd) { | |
1535 | case STA_NOTIFY_SLEEP: | |
1536 | an->sleeping = true; | |
042ec453 | 1537 | ath_tx_aggr_sleep(sta, sc, an); |
4bbf4414 | 1538 | ath9k_sta_set_tx_filter(sc->sc_ah, an, true); |
5519541d FF |
1539 | break; |
1540 | case STA_NOTIFY_AWAKE: | |
4bbf4414 | 1541 | ath9k_sta_set_tx_filter(sc->sc_ah, an, false); |
5519541d FF |
1542 | an->sleeping = false; |
1543 | ath_tx_aggr_wakeup(sc, an); | |
1544 | break; | |
1545 | } | |
1546 | } | |
1547 | ||
8a3a3c85 EP |
1548 | static int ath9k_conf_tx(struct ieee80211_hw *hw, |
1549 | struct ieee80211_vif *vif, u16 queue, | |
8feceb67 | 1550 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1551 | { |
9ac58615 | 1552 | struct ath_softc *sc = hw->priv; |
c46917bb | 1553 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
066dae93 | 1554 | struct ath_txq *txq; |
8feceb67 | 1555 | struct ath9k_tx_queue_info qi; |
066dae93 | 1556 | int ret = 0; |
f078f209 | 1557 | |
bea843c7 | 1558 | if (queue >= IEEE80211_NUM_ACS) |
8feceb67 | 1559 | return 0; |
f078f209 | 1560 | |
066dae93 FF |
1561 | txq = sc->tx.txq_map[queue]; |
1562 | ||
96f372c9 | 1563 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1564 | mutex_lock(&sc->mutex); |
1565 | ||
1ffb0610 S |
1566 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1567 | ||
8feceb67 VT |
1568 | qi.tqi_aifs = params->aifs; |
1569 | qi.tqi_cwmin = params->cw_min; | |
1570 | qi.tqi_cwmax = params->cw_max; | |
531bd079 | 1571 | qi.tqi_burstTime = params->txop * 32; |
f078f209 | 1572 | |
d2182b69 | 1573 | ath_dbg(common, CONFIG, |
226afe68 JP |
1574 | "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", |
1575 | queue, txq->axq_qnum, params->aifs, params->cw_min, | |
1576 | params->cw_max, params->txop); | |
f078f209 | 1577 | |
aa5955c3 | 1578 | ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); |
066dae93 | 1579 | ret = ath_txq_update(sc, txq->axq_qnum, &qi); |
8feceb67 | 1580 | if (ret) |
3800276a | 1581 | ath_err(common, "TXQ Update failed\n"); |
f078f209 | 1582 | |
141b38b6 | 1583 | mutex_unlock(&sc->mutex); |
96f372c9 | 1584 | ath9k_ps_restore(sc); |
141b38b6 | 1585 | |
8feceb67 VT |
1586 | return ret; |
1587 | } | |
f078f209 | 1588 | |
8feceb67 VT |
1589 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1590 | enum set_key_cmd cmd, | |
dc822b5d JB |
1591 | struct ieee80211_vif *vif, |
1592 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1593 | struct ieee80211_key_conf *key) |
1594 | { | |
9ac58615 | 1595 | struct ath_softc *sc = hw->priv; |
c46917bb | 1596 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4bbf4414 RM |
1597 | struct ath_node *an = NULL; |
1598 | int ret = 0, i; | |
f078f209 | 1599 | |
3e6109c5 | 1600 | if (ath9k_modparam_nohwcrypt) |
b3bd89ce JM |
1601 | return -ENOSPC; |
1602 | ||
5bd5e9a6 CYY |
1603 | if ((vif->type == NL80211_IFTYPE_ADHOC || |
1604 | vif->type == NL80211_IFTYPE_MESH_POINT) && | |
cfdc9a8b JM |
1605 | (key->cipher == WLAN_CIPHER_SUITE_TKIP || |
1606 | key->cipher == WLAN_CIPHER_SUITE_CCMP) && | |
1607 | !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { | |
1608 | /* | |
1609 | * For now, disable hw crypto for the RSN IBSS group keys. This | |
1610 | * could be optimized in the future to use a modified key cache | |
1611 | * design to support per-STA RX GTK, but until that gets | |
1612 | * implemented, use of software crypto for group addressed | |
1613 | * frames is a acceptable to allow RSN IBSS to be used. | |
1614 | */ | |
1615 | return -EOPNOTSUPP; | |
1616 | } | |
1617 | ||
141b38b6 | 1618 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1619 | ath9k_ps_wakeup(sc); |
4bbf4414 RM |
1620 | ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd); |
1621 | if (sta) | |
1622 | an = (struct ath_node *)sta->drv_priv; | |
f078f209 | 1623 | |
8feceb67 VT |
1624 | switch (cmd) { |
1625 | case SET_KEY: | |
93ae2dd2 FF |
1626 | if (sta) |
1627 | ath9k_del_ps_key(sc, vif, sta); | |
1628 | ||
4bbf4414 | 1629 | key->hw_key_idx = 0; |
040e539e | 1630 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1631 | if (ret >= 0) { |
1632 | key->hw_key_idx = ret; | |
8feceb67 VT |
1633 | /* push IV and Michael MIC generation to stack */ |
1634 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
97359d12 | 1635 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) |
8feceb67 | 1636 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
97359d12 JB |
1637 | if (sc->sc_ah->sw_mgmt_crypto && |
1638 | key->cipher == WLAN_CIPHER_SUITE_CCMP) | |
e548c49e | 1639 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; |
6ace2891 | 1640 | ret = 0; |
8feceb67 | 1641 | } |
4bbf4414 RM |
1642 | if (an && key->hw_key_idx) { |
1643 | for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { | |
1644 | if (an->key_idx[i]) | |
1645 | continue; | |
1646 | an->key_idx[i] = key->hw_key_idx; | |
1647 | break; | |
1648 | } | |
1649 | WARN_ON(i == ARRAY_SIZE(an->key_idx)); | |
1650 | } | |
8feceb67 VT |
1651 | break; |
1652 | case DISABLE_KEY: | |
040e539e | 1653 | ath_key_delete(common, key); |
4bbf4414 RM |
1654 | if (an) { |
1655 | for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { | |
1656 | if (an->key_idx[i] != key->hw_key_idx) | |
1657 | continue; | |
1658 | an->key_idx[i] = 0; | |
1659 | break; | |
1660 | } | |
1661 | } | |
1662 | key->hw_key_idx = 0; | |
8feceb67 VT |
1663 | break; |
1664 | default: | |
1665 | ret = -EINVAL; | |
1666 | } | |
f078f209 | 1667 | |
3cbb5dd7 | 1668 | ath9k_ps_restore(sc); |
141b38b6 S |
1669 | mutex_unlock(&sc->mutex); |
1670 | ||
8feceb67 VT |
1671 | return ret; |
1672 | } | |
6c43c090 | 1673 | |
8feceb67 VT |
1674 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1675 | struct ieee80211_vif *vif, | |
1676 | struct ieee80211_bss_conf *bss_conf, | |
1677 | u32 changed) | |
1678 | { | |
da0d45f7 SM |
1679 | #define CHECK_ANI \ |
1680 | (BSS_CHANGED_ASSOC | \ | |
1681 | BSS_CHANGED_IBSS | \ | |
1682 | BSS_CHANGED_BEACON_ENABLED) | |
1683 | ||
9ac58615 | 1684 | struct ath_softc *sc = hw->priv; |
2d0ddec5 | 1685 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1686 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1687 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1688 | int slottime; |
f078f209 | 1689 | |
96f372c9 | 1690 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1691 | mutex_lock(&sc->mutex); |
1692 | ||
9f61903c | 1693 | if (changed & BSS_CHANGED_ASSOC) { |
6c43c090 SM |
1694 | ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", |
1695 | bss_conf->bssid, bss_conf->assoc); | |
1696 | ||
9a9c4fbc | 1697 | ath9k_calculate_summary_state(sc, avp->chanctx); |
27babf9f SM |
1698 | |
1699 | if (ath9k_is_chanctx_enabled()) { | |
1700 | if (bss_conf->assoc) | |
1701 | ath_chanctx_event(sc, vif, | |
1702 | ATH_CHANCTX_EVENT_ASSOC); | |
1703 | } | |
c6089ccc | 1704 | } |
2d0ddec5 | 1705 | |
2e5ef459 | 1706 | if (changed & BSS_CHANGED_IBSS) { |
2e5ef459 RM |
1707 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); |
1708 | common->curaid = bss_conf->aid; | |
1709 | ath9k_hw_write_associd(sc->sc_ah); | |
2e5ef459 RM |
1710 | } |
1711 | ||
ef4ad633 | 1712 | if ((changed & BSS_CHANGED_BEACON_ENABLED) || |
9198cf4a RM |
1713 | (changed & BSS_CHANGED_BEACON_INT) || |
1714 | (changed & BSS_CHANGED_BEACON_INFO)) { | |
9bf30ff9 | 1715 | ath9k_beacon_config(sc, vif, changed); |
9a9c4fbc RM |
1716 | if (changed & BSS_CHANGED_BEACON_ENABLED) |
1717 | ath9k_calculate_summary_state(sc, avp->chanctx); | |
9a9c4fbc | 1718 | } |
0005baf4 | 1719 | |
9a9c4fbc RM |
1720 | if ((avp->chanctx == sc->cur_chan) && |
1721 | (changed & BSS_CHANGED_ERP_SLOT)) { | |
0005baf4 FF |
1722 | if (bss_conf->use_short_slot) |
1723 | slottime = 9; | |
1724 | else | |
1725 | slottime = 20; | |
1726 | if (vif->type == NL80211_IFTYPE_AP) { | |
1727 | /* | |
1728 | * Defer update, so that connected stations can adjust | |
1729 | * their settings at the same time. | |
1730 | * See beacon.c for more details | |
1731 | */ | |
1732 | sc->beacon.slottime = slottime; | |
1733 | sc->beacon.updateslot = UPDATE; | |
1734 | } else { | |
1735 | ah->slottime = slottime; | |
1736 | ath9k_hw_init_global_settings(ah); | |
1737 | } | |
2d0ddec5 JB |
1738 | } |
1739 | ||
c7dd40c9 SM |
1740 | if (changed & BSS_CHANGED_P2P_PS) |
1741 | ath9k_p2p_bss_info_changed(sc, vif); | |
d463af4a | 1742 | |
da0d45f7 SM |
1743 | if (changed & CHECK_ANI) |
1744 | ath_check_ani(sc); | |
1745 | ||
141b38b6 | 1746 | mutex_unlock(&sc->mutex); |
96f372c9 | 1747 | ath9k_ps_restore(sc); |
da0d45f7 SM |
1748 | |
1749 | #undef CHECK_ANI | |
8feceb67 | 1750 | } |
f078f209 | 1751 | |
37a41b4a | 1752 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 1753 | { |
9ac58615 | 1754 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1755 | u64 tsf; |
f078f209 | 1756 | |
141b38b6 | 1757 | mutex_lock(&sc->mutex); |
9abbfb27 | 1758 | ath9k_ps_wakeup(sc); |
141b38b6 | 1759 | tsf = ath9k_hw_gettsf64(sc->sc_ah); |
9abbfb27 | 1760 | ath9k_ps_restore(sc); |
141b38b6 | 1761 | mutex_unlock(&sc->mutex); |
f078f209 | 1762 | |
8feceb67 VT |
1763 | return tsf; |
1764 | } | |
f078f209 | 1765 | |
37a41b4a EP |
1766 | static void ath9k_set_tsf(struct ieee80211_hw *hw, |
1767 | struct ieee80211_vif *vif, | |
1768 | u64 tsf) | |
3b5d665b | 1769 | { |
9ac58615 | 1770 | struct ath_softc *sc = hw->priv; |
3b5d665b | 1771 | |
141b38b6 | 1772 | mutex_lock(&sc->mutex); |
9abbfb27 | 1773 | ath9k_ps_wakeup(sc); |
141b38b6 | 1774 | ath9k_hw_settsf64(sc->sc_ah, tsf); |
9abbfb27 | 1775 | ath9k_ps_restore(sc); |
141b38b6 | 1776 | mutex_unlock(&sc->mutex); |
3b5d665b AF |
1777 | } |
1778 | ||
37a41b4a | 1779 | static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 1780 | { |
9ac58615 | 1781 | struct ath_softc *sc = hw->priv; |
c83be688 | 1782 | |
141b38b6 | 1783 | mutex_lock(&sc->mutex); |
21526d57 LR |
1784 | |
1785 | ath9k_ps_wakeup(sc); | |
141b38b6 | 1786 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
1787 | ath9k_ps_restore(sc); |
1788 | ||
141b38b6 | 1789 | mutex_unlock(&sc->mutex); |
8feceb67 | 1790 | } |
f078f209 | 1791 | |
8feceb67 | 1792 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 1793 | struct ieee80211_vif *vif, |
141b38b6 S |
1794 | enum ieee80211_ampdu_mlme_action action, |
1795 | struct ieee80211_sta *sta, | |
0b01f030 | 1796 | u16 tid, u16 *ssn, u8 buf_size) |
8feceb67 | 1797 | { |
9ac58615 | 1798 | struct ath_softc *sc = hw->priv; |
16e23428 | 1799 | bool flush = false; |
8feceb67 | 1800 | int ret = 0; |
f078f209 | 1801 | |
7ca7c776 | 1802 | mutex_lock(&sc->mutex); |
85ad181e | 1803 | |
8feceb67 VT |
1804 | switch (action) { |
1805 | case IEEE80211_AMPDU_RX_START: | |
8feceb67 VT |
1806 | break; |
1807 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
1808 | break; |
1809 | case IEEE80211_AMPDU_TX_START: | |
8b685ba9 | 1810 | ath9k_ps_wakeup(sc); |
231c3a1f FF |
1811 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
1812 | if (!ret) | |
1813 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
8b685ba9 | 1814 | ath9k_ps_restore(sc); |
8feceb67 | 1815 | break; |
18b559d5 JB |
1816 | case IEEE80211_AMPDU_TX_STOP_FLUSH: |
1817 | case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: | |
16e23428 FF |
1818 | flush = true; |
1819 | case IEEE80211_AMPDU_TX_STOP_CONT: | |
8b685ba9 | 1820 | ath9k_ps_wakeup(sc); |
f83da965 | 1821 | ath_tx_aggr_stop(sc, sta, tid); |
08c96abd | 1822 | if (!flush) |
16e23428 | 1823 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1824 | ath9k_ps_restore(sc); |
8feceb67 | 1825 | break; |
b1720231 | 1826 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 1827 | ath9k_ps_wakeup(sc); |
8469cdef | 1828 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 1829 | ath9k_ps_restore(sc); |
8469cdef | 1830 | break; |
8feceb67 | 1831 | default: |
3800276a | 1832 | ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); |
8feceb67 VT |
1833 | } |
1834 | ||
7ca7c776 | 1835 | mutex_unlock(&sc->mutex); |
85ad181e | 1836 | |
8feceb67 | 1837 | return ret; |
f078f209 LR |
1838 | } |
1839 | ||
62dad5b0 BP |
1840 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
1841 | struct survey_info *survey) | |
1842 | { | |
9ac58615 | 1843 | struct ath_softc *sc = hw->priv; |
3430098a | 1844 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39162dbe | 1845 | struct ieee80211_supported_band *sband; |
3430098a | 1846 | struct ieee80211_channel *chan; |
3430098a FF |
1847 | int pos; |
1848 | ||
89f927af LR |
1849 | if (config_enabled(CONFIG_ATH9K_TX99)) |
1850 | return -EOPNOTSUPP; | |
1851 | ||
b7cc9b97 | 1852 | spin_lock_bh(&common->cc_lock); |
3430098a FF |
1853 | if (idx == 0) |
1854 | ath_update_survey_stats(sc); | |
39162dbe FF |
1855 | |
1856 | sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; | |
1857 | if (sband && idx >= sband->n_channels) { | |
1858 | idx -= sband->n_channels; | |
1859 | sband = NULL; | |
1860 | } | |
62dad5b0 | 1861 | |
39162dbe FF |
1862 | if (!sband) |
1863 | sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; | |
62dad5b0 | 1864 | |
3430098a | 1865 | if (!sband || idx >= sband->n_channels) { |
b7cc9b97 | 1866 | spin_unlock_bh(&common->cc_lock); |
3430098a | 1867 | return -ENOENT; |
4f1a5a4b | 1868 | } |
62dad5b0 | 1869 | |
3430098a FF |
1870 | chan = &sband->channels[idx]; |
1871 | pos = chan->hw_value; | |
1872 | memcpy(survey, &sc->survey[pos], sizeof(*survey)); | |
1873 | survey->channel = chan; | |
b7cc9b97 | 1874 | spin_unlock_bh(&common->cc_lock); |
3430098a | 1875 | |
62dad5b0 BP |
1876 | return 0; |
1877 | } | |
1878 | ||
a4bcaf55 LB |
1879 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, |
1880 | s16 coverage_class) | |
e239d859 | 1881 | { |
9ac58615 | 1882 | struct ath_softc *sc = hw->priv; |
e239d859 FF |
1883 | struct ath_hw *ah = sc->sc_ah; |
1884 | ||
89f927af LR |
1885 | if (config_enabled(CONFIG_ATH9K_TX99)) |
1886 | return; | |
1887 | ||
e239d859 FF |
1888 | mutex_lock(&sc->mutex); |
1889 | ah->coverage_class = coverage_class; | |
8b2a3827 MSS |
1890 | |
1891 | ath9k_ps_wakeup(sc); | |
e239d859 | 1892 | ath9k_hw_init_global_settings(ah); |
8b2a3827 MSS |
1893 | ath9k_ps_restore(sc); |
1894 | ||
e239d859 FF |
1895 | mutex_unlock(&sc->mutex); |
1896 | } | |
1897 | ||
10e23181 FF |
1898 | static bool ath9k_has_tx_pending(struct ath_softc *sc) |
1899 | { | |
f7838073 | 1900 | int i, npend = 0; |
10e23181 FF |
1901 | |
1902 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1903 | if (!ATH_TXQ_SETUP(sc, i)) | |
1904 | continue; | |
1905 | ||
1906 | if (!sc->tx.txq[i].axq_depth) | |
1907 | continue; | |
1908 | ||
1909 | npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); | |
1910 | if (npend) | |
1911 | break; | |
1912 | } | |
1913 | ||
1914 | return !!npend; | |
1915 | } | |
1916 | ||
77be2c54 EG |
1917 | static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
1918 | u32 queues, bool drop) | |
bff11766 FF |
1919 | { |
1920 | struct ath_softc *sc = hw->priv; | |
1921 | ||
1922 | mutex_lock(&sc->mutex); | |
1923 | __ath9k_flush(hw, queues, drop); | |
1924 | mutex_unlock(&sc->mutex); | |
1925 | } | |
1926 | ||
1927 | void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop) | |
69081624 | 1928 | { |
69081624 | 1929 | struct ath_softc *sc = hw->priv; |
99aa55b6 MSS |
1930 | struct ath_hw *ah = sc->sc_ah; |
1931 | struct ath_common *common = ath9k_hw_common(ah); | |
10e23181 | 1932 | int timeout = HZ / 5; /* 200 ms */ |
2f6fc351 | 1933 | bool drain_txq; |
3ad9c386 | 1934 | int i; |
69081624 | 1935 | |
69081624 VT |
1936 | cancel_delayed_work_sync(&sc->tx_complete_work); |
1937 | ||
6a6b3f3e | 1938 | if (ah->ah_flags & AH_UNPLUGGED) { |
d2182b69 | 1939 | ath_dbg(common, ANY, "Device has been unplugged!\n"); |
6a6b3f3e MSS |
1940 | return; |
1941 | } | |
1942 | ||
eefa01dd | 1943 | if (test_bit(ATH_OP_INVALID, &common->op_flags)) { |
d2182b69 | 1944 | ath_dbg(common, ANY, "Device not present\n"); |
99aa55b6 MSS |
1945 | return; |
1946 | } | |
1947 | ||
10e23181 FF |
1948 | if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc), |
1949 | timeout) > 0) | |
1950 | drop = false; | |
69081624 | 1951 | |
9df0d6a2 FF |
1952 | if (drop) { |
1953 | ath9k_ps_wakeup(sc); | |
1954 | spin_lock_bh(&sc->sc_pcu_lock); | |
1381559b | 1955 | drain_txq = ath_drain_all_txq(sc); |
9df0d6a2 | 1956 | spin_unlock_bh(&sc->sc_pcu_lock); |
9adcf440 | 1957 | |
9df0d6a2 | 1958 | if (!drain_txq) |
1381559b | 1959 | ath_reset(sc); |
9adcf440 | 1960 | |
9df0d6a2 | 1961 | ath9k_ps_restore(sc); |
3ad9c386 RM |
1962 | for (i = 0; i < IEEE80211_NUM_ACS; i++) { |
1963 | ieee80211_wake_queue(sc->hw, | |
1964 | sc->cur_chan->hw_queue_base + i); | |
1965 | } | |
9df0d6a2 | 1966 | } |
d78f4b3e | 1967 | |
69081624 | 1968 | ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); |
69081624 VT |
1969 | } |
1970 | ||
15b91e83 VN |
1971 | static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) |
1972 | { | |
1973 | struct ath_softc *sc = hw->priv; | |
1974 | int i; | |
1975 | ||
1976 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1977 | if (!ATH_TXQ_SETUP(sc, i)) | |
1978 | continue; | |
1979 | ||
1980 | if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) | |
1981 | return true; | |
1982 | } | |
1983 | return false; | |
1984 | } | |
1985 | ||
5595f119 | 1986 | static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) |
ba4903f9 FF |
1987 | { |
1988 | struct ath_softc *sc = hw->priv; | |
1989 | struct ath_hw *ah = sc->sc_ah; | |
1990 | struct ieee80211_vif *vif; | |
1991 | struct ath_vif *avp; | |
1992 | struct ath_buf *bf; | |
1993 | struct ath_tx_status ts; | |
4286df60 | 1994 | bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); |
ba4903f9 FF |
1995 | int status; |
1996 | ||
1997 | vif = sc->beacon.bslot[0]; | |
1998 | if (!vif) | |
1999 | return 0; | |
2000 | ||
aa45fe96 | 2001 | if (!vif->bss_conf.enable_beacon) |
ba4903f9 FF |
2002 | return 0; |
2003 | ||
aa45fe96 SM |
2004 | avp = (void *)vif->drv_priv; |
2005 | ||
4286df60 | 2006 | if (!sc->beacon.tx_processed && !edma) { |
ba4903f9 FF |
2007 | tasklet_disable(&sc->bcon_tasklet); |
2008 | ||
2009 | bf = avp->av_bcbuf; | |
2010 | if (!bf || !bf->bf_mpdu) | |
2011 | goto skip; | |
2012 | ||
2013 | status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); | |
2014 | if (status == -EINPROGRESS) | |
2015 | goto skip; | |
2016 | ||
2017 | sc->beacon.tx_processed = true; | |
2018 | sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); | |
2019 | ||
2020 | skip: | |
2021 | tasklet_enable(&sc->bcon_tasklet); | |
2022 | } | |
2023 | ||
2024 | return sc->beacon.tx_last; | |
2025 | } | |
2026 | ||
52c94f41 MSS |
2027 | static int ath9k_get_stats(struct ieee80211_hw *hw, |
2028 | struct ieee80211_low_level_stats *stats) | |
2029 | { | |
2030 | struct ath_softc *sc = hw->priv; | |
2031 | struct ath_hw *ah = sc->sc_ah; | |
2032 | struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; | |
2033 | ||
2034 | stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; | |
2035 | stats->dot11RTSFailureCount = mib_stats->rts_bad; | |
2036 | stats->dot11FCSErrorCount = mib_stats->fcs_bad; | |
2037 | stats->dot11RTSSuccessCount = mib_stats->rts_good; | |
2038 | return 0; | |
2039 | } | |
2040 | ||
43c35284 FF |
2041 | static u32 fill_chainmask(u32 cap, u32 new) |
2042 | { | |
2043 | u32 filled = 0; | |
2044 | int i; | |
2045 | ||
2046 | for (i = 0; cap && new; i++, cap >>= 1) { | |
2047 | if (!(cap & BIT(0))) | |
2048 | continue; | |
2049 | ||
2050 | if (new & BIT(0)) | |
2051 | filled |= BIT(i); | |
2052 | ||
2053 | new >>= 1; | |
2054 | } | |
2055 | ||
2056 | return filled; | |
2057 | } | |
2058 | ||
5d9c7e3c FF |
2059 | static bool validate_antenna_mask(struct ath_hw *ah, u32 val) |
2060 | { | |
fea92cbf FF |
2061 | if (AR_SREV_9300_20_OR_LATER(ah)) |
2062 | return true; | |
2063 | ||
5d9c7e3c FF |
2064 | switch (val & 0x7) { |
2065 | case 0x1: | |
2066 | case 0x3: | |
2067 | case 0x7: | |
2068 | return true; | |
2069 | case 0x2: | |
2070 | return (ah->caps.rx_chainmask == 1); | |
2071 | default: | |
2072 | return false; | |
2073 | } | |
2074 | } | |
2075 | ||
43c35284 FF |
2076 | static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) |
2077 | { | |
2078 | struct ath_softc *sc = hw->priv; | |
2079 | struct ath_hw *ah = sc->sc_ah; | |
2080 | ||
5d9c7e3c FF |
2081 | if (ah->caps.rx_chainmask != 1) |
2082 | rx_ant |= tx_ant; | |
2083 | ||
2084 | if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) | |
43c35284 FF |
2085 | return -EINVAL; |
2086 | ||
2087 | sc->ant_rx = rx_ant; | |
2088 | sc->ant_tx = tx_ant; | |
2089 | ||
2090 | if (ah->caps.rx_chainmask == 1) | |
2091 | return 0; | |
2092 | ||
2093 | /* AR9100 runs into calibration issues if not all rx chains are enabled */ | |
2094 | if (AR_SREV_9100(ah)) | |
2095 | ah->rxchainmask = 0x7; | |
2096 | else | |
2097 | ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); | |
2098 | ||
2099 | ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); | |
b57ba3b2 | 2100 | ath9k_cmn_reload_chainmask(ah); |
43c35284 FF |
2101 | |
2102 | return 0; | |
2103 | } | |
2104 | ||
2105 | static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) | |
2106 | { | |
2107 | struct ath_softc *sc = hw->priv; | |
2108 | ||
2109 | *tx_ant = sc->ant_tx; | |
2110 | *rx_ant = sc->ant_rx; | |
2111 | return 0; | |
2112 | } | |
2113 | ||
e93d083f SW |
2114 | static void ath9k_sw_scan_start(struct ieee80211_hw *hw) |
2115 | { | |
2116 | struct ath_softc *sc = hw->priv; | |
eefa01dd OR |
2117 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
2118 | set_bit(ATH_OP_SCANNING, &common->op_flags); | |
e93d083f SW |
2119 | } |
2120 | ||
2121 | static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) | |
2122 | { | |
2123 | struct ath_softc *sc = hw->priv; | |
eefa01dd OR |
2124 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
2125 | clear_bit(ATH_OP_SCANNING, &common->op_flags); | |
e93d083f | 2126 | } |
b11e640a | 2127 | |
499afacc SM |
2128 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
2129 | ||
78b21949 | 2130 | static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
855df36d | 2131 | struct ieee80211_scan_request *hw_req) |
78b21949 | 2132 | { |
855df36d | 2133 | struct cfg80211_scan_request *req = &hw_req->req; |
78b21949 FF |
2134 | struct ath_softc *sc = hw->priv; |
2135 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
2136 | int ret = 0; | |
2137 | ||
2138 | mutex_lock(&sc->mutex); | |
2139 | ||
2140 | if (WARN_ON(sc->offchannel.scan_req)) { | |
2141 | ret = -EBUSY; | |
2142 | goto out; | |
2143 | } | |
2144 | ||
2145 | ath9k_ps_wakeup(sc); | |
2146 | set_bit(ATH_OP_SCANNING, &common->op_flags); | |
2147 | sc->offchannel.scan_vif = vif; | |
2148 | sc->offchannel.scan_req = req; | |
2149 | sc->offchannel.scan_idx = 0; | |
78b21949 | 2150 | |
bc81d43a SM |
2151 | ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n", |
2152 | vif->addr); | |
2153 | ||
2154 | if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) { | |
2155 | ath_dbg(common, CHAN_CTX, "Starting HW scan\n"); | |
405393cf | 2156 | ath_offchannel_next(sc); |
bc81d43a | 2157 | } |
78b21949 FF |
2158 | |
2159 | out: | |
2160 | mutex_unlock(&sc->mutex); | |
2161 | ||
2162 | return ret; | |
2163 | } | |
2164 | ||
2165 | static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw, | |
2166 | struct ieee80211_vif *vif) | |
2167 | { | |
2168 | struct ath_softc *sc = hw->priv; | |
bc81d43a SM |
2169 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
2170 | ||
2171 | ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr); | |
78b21949 FF |
2172 | |
2173 | mutex_lock(&sc->mutex); | |
2174 | del_timer_sync(&sc->offchannel.timer); | |
2175 | ath_scan_complete(sc, true); | |
2176 | mutex_unlock(&sc->mutex); | |
2177 | } | |
2178 | ||
405393cf FF |
2179 | static int ath9k_remain_on_channel(struct ieee80211_hw *hw, |
2180 | struct ieee80211_vif *vif, | |
2181 | struct ieee80211_channel *chan, int duration, | |
2182 | enum ieee80211_roc_type type) | |
2183 | { | |
2184 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2185 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
405393cf FF |
2186 | int ret = 0; |
2187 | ||
2188 | mutex_lock(&sc->mutex); | |
2189 | ||
2190 | if (WARN_ON(sc->offchannel.roc_vif)) { | |
2191 | ret = -EBUSY; | |
2192 | goto out; | |
2193 | } | |
2194 | ||
2195 | ath9k_ps_wakeup(sc); | |
2196 | sc->offchannel.roc_vif = vif; | |
2197 | sc->offchannel.roc_chan = chan; | |
2198 | sc->offchannel.roc_duration = duration; | |
2199 | ||
bc81d43a SM |
2200 | ath_dbg(common, CHAN_CTX, |
2201 | "RoC request on vif: %pM, type: %d duration: %d\n", | |
2202 | vif->addr, type, duration); | |
2203 | ||
2204 | if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) { | |
2205 | ath_dbg(common, CHAN_CTX, "Starting RoC period\n"); | |
405393cf | 2206 | ath_offchannel_next(sc); |
bc81d43a | 2207 | } |
405393cf FF |
2208 | |
2209 | out: | |
2210 | mutex_unlock(&sc->mutex); | |
2211 | ||
2212 | return ret; | |
2213 | } | |
2214 | ||
2215 | static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw) | |
2216 | { | |
2217 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2218 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
405393cf FF |
2219 | |
2220 | mutex_lock(&sc->mutex); | |
2221 | ||
bc81d43a | 2222 | ath_dbg(common, CHAN_CTX, "Cancel RoC\n"); |
405393cf FF |
2223 | del_timer_sync(&sc->offchannel.timer); |
2224 | ||
2225 | if (sc->offchannel.roc_vif) { | |
2226 | if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START) | |
2227 | ath_roc_complete(sc, true); | |
2228 | } | |
2229 | ||
2230 | mutex_unlock(&sc->mutex); | |
2231 | ||
2232 | return 0; | |
2233 | } | |
2234 | ||
39305635 FF |
2235 | static int ath9k_add_chanctx(struct ieee80211_hw *hw, |
2236 | struct ieee80211_chanctx_conf *conf) | |
2237 | { | |
2238 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2239 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39305635 | 2240 | struct ath_chanctx *ctx, **ptr; |
3ad9c386 | 2241 | int pos; |
39305635 FF |
2242 | |
2243 | mutex_lock(&sc->mutex); | |
c4dc0d04 RM |
2244 | |
2245 | ath_for_each_chanctx(sc, ctx) { | |
2246 | if (ctx->assigned) | |
2247 | continue; | |
2248 | ||
2249 | ptr = (void *) conf->drv_priv; | |
2250 | *ptr = ctx; | |
2251 | ctx->assigned = true; | |
3ad9c386 RM |
2252 | pos = ctx - &sc->chanctx[0]; |
2253 | ctx->hw_queue_base = pos * IEEE80211_NUM_ACS; | |
bc81d43a SM |
2254 | |
2255 | ath_dbg(common, CHAN_CTX, | |
2256 | "Add channel context: %d MHz\n", | |
2257 | conf->def.chan->center_freq); | |
2258 | ||
c4dc0d04 | 2259 | ath_chanctx_set_channel(sc, ctx, &conf->def); |
4c7e9aee SM |
2260 | ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_ASSIGN); |
2261 | ||
39305635 | 2262 | mutex_unlock(&sc->mutex); |
c4dc0d04 | 2263 | return 0; |
39305635 | 2264 | } |
bc81d43a | 2265 | |
39305635 | 2266 | mutex_unlock(&sc->mutex); |
c4dc0d04 | 2267 | return -ENOSPC; |
39305635 FF |
2268 | } |
2269 | ||
2270 | ||
2271 | static void ath9k_remove_chanctx(struct ieee80211_hw *hw, | |
2272 | struct ieee80211_chanctx_conf *conf) | |
2273 | { | |
2274 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2275 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39305635 FF |
2276 | struct ath_chanctx *ctx = ath_chanctx_get(conf); |
2277 | ||
2278 | mutex_lock(&sc->mutex); | |
bc81d43a SM |
2279 | |
2280 | ath_dbg(common, CHAN_CTX, | |
2281 | "Remove channel context: %d MHz\n", | |
2282 | conf->def.chan->center_freq); | |
2283 | ||
39305635 | 2284 | ctx->assigned = false; |
3ad9c386 | 2285 | ctx->hw_queue_base = -1; |
73fa2f26 | 2286 | ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN); |
bc81d43a | 2287 | |
39305635 FF |
2288 | mutex_unlock(&sc->mutex); |
2289 | } | |
2290 | ||
2291 | static void ath9k_change_chanctx(struct ieee80211_hw *hw, | |
2292 | struct ieee80211_chanctx_conf *conf, | |
2293 | u32 changed) | |
2294 | { | |
2295 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2296 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39305635 FF |
2297 | struct ath_chanctx *ctx = ath_chanctx_get(conf); |
2298 | ||
2299 | mutex_lock(&sc->mutex); | |
bc81d43a SM |
2300 | ath_dbg(common, CHAN_CTX, |
2301 | "Change channel context: %d MHz\n", | |
2302 | conf->def.chan->center_freq); | |
39305635 FF |
2303 | ath_chanctx_set_channel(sc, ctx, &conf->def); |
2304 | mutex_unlock(&sc->mutex); | |
2305 | } | |
2306 | ||
2307 | static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw, | |
2308 | struct ieee80211_vif *vif, | |
2309 | struct ieee80211_chanctx_conf *conf) | |
2310 | { | |
2311 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2312 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39305635 FF |
2313 | struct ath_vif *avp = (void *)vif->drv_priv; |
2314 | struct ath_chanctx *ctx = ath_chanctx_get(conf); | |
3ad9c386 | 2315 | int i; |
39305635 FF |
2316 | |
2317 | mutex_lock(&sc->mutex); | |
bc81d43a SM |
2318 | |
2319 | ath_dbg(common, CHAN_CTX, | |
2320 | "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n", | |
2321 | vif->addr, vif->type, vif->p2p, | |
2322 | conf->def.chan->center_freq); | |
2323 | ||
39305635 FF |
2324 | avp->chanctx = ctx; |
2325 | list_add_tail(&avp->list, &ctx->vifs); | |
9a9c4fbc | 2326 | ath9k_calculate_summary_state(sc, ctx); |
3ad9c386 RM |
2327 | for (i = 0; i < IEEE80211_NUM_ACS; i++) |
2328 | vif->hw_queue[i] = ctx->hw_queue_base + i; | |
bc81d43a | 2329 | |
39305635 FF |
2330 | mutex_unlock(&sc->mutex); |
2331 | ||
2332 | return 0; | |
2333 | } | |
2334 | ||
2335 | static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw, | |
2336 | struct ieee80211_vif *vif, | |
2337 | struct ieee80211_chanctx_conf *conf) | |
2338 | { | |
2339 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2340 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39305635 FF |
2341 | struct ath_vif *avp = (void *)vif->drv_priv; |
2342 | struct ath_chanctx *ctx = ath_chanctx_get(conf); | |
3ad9c386 | 2343 | int ac; |
39305635 FF |
2344 | |
2345 | mutex_lock(&sc->mutex); | |
bc81d43a SM |
2346 | |
2347 | ath_dbg(common, CHAN_CTX, | |
2348 | "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n", | |
2349 | vif->addr, vif->type, vif->p2p, | |
2350 | conf->def.chan->center_freq); | |
2351 | ||
39305635 FF |
2352 | avp->chanctx = NULL; |
2353 | list_del(&avp->list); | |
9a9c4fbc | 2354 | ath9k_calculate_summary_state(sc, ctx); |
3ad9c386 RM |
2355 | for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) |
2356 | vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE; | |
bc81d43a | 2357 | |
39305635 FF |
2358 | mutex_unlock(&sc->mutex); |
2359 | } | |
2360 | ||
e20a854e SM |
2361 | static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw, |
2362 | struct ieee80211_vif *vif) | |
2363 | { | |
2364 | struct ath_softc *sc = hw->priv; | |
2365 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
2366 | struct ath_vif *avp = (struct ath_vif *) vif->drv_priv; | |
2367 | bool changed = false; | |
2368 | ||
2369 | if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags)) | |
2370 | return; | |
2371 | ||
2372 | if (!avp->chanctx) | |
2373 | return; | |
2374 | ||
2375 | mutex_lock(&sc->mutex); | |
2376 | ||
2377 | spin_lock_bh(&sc->chan_lock); | |
2378 | if (sc->next_chan || (sc->cur_chan != avp->chanctx)) { | |
2379 | sc->next_chan = avp->chanctx; | |
2380 | changed = true; | |
2381 | } | |
878066e7 SM |
2382 | ath_dbg(common, CHAN_CTX, |
2383 | "%s: Set chanctx state to FORCE_ACTIVE, changed: %d\n", | |
2384 | __func__, changed); | |
e20a854e SM |
2385 | sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE; |
2386 | spin_unlock_bh(&sc->chan_lock); | |
2387 | ||
2388 | if (changed) | |
2389 | ath_chanctx_set_next(sc, true); | |
2390 | ||
2391 | mutex_unlock(&sc->mutex); | |
2392 | } | |
2393 | ||
78b21949 FF |
2394 | void ath9k_fill_chanctx_ops(void) |
2395 | { | |
499afacc | 2396 | if (!ath9k_is_chanctx_enabled()) |
78b21949 FF |
2397 | return; |
2398 | ||
bc81d43a SM |
2399 | ath9k_ops.hw_scan = ath9k_hw_scan; |
2400 | ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan; | |
2401 | ath9k_ops.remain_on_channel = ath9k_remain_on_channel; | |
405393cf | 2402 | ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel; |
bc81d43a SM |
2403 | ath9k_ops.add_chanctx = ath9k_add_chanctx; |
2404 | ath9k_ops.remove_chanctx = ath9k_remove_chanctx; | |
2405 | ath9k_ops.change_chanctx = ath9k_change_chanctx; | |
2406 | ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx; | |
2407 | ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx; | |
e20a854e | 2408 | ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx; |
78b21949 FF |
2409 | } |
2410 | ||
499afacc SM |
2411 | #endif |
2412 | ||
6baff7f9 | 2413 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2414 | .tx = ath9k_tx, |
2415 | .start = ath9k_start, | |
2416 | .stop = ath9k_stop, | |
2417 | .add_interface = ath9k_add_interface, | |
6b3b991d | 2418 | .change_interface = ath9k_change_interface, |
8feceb67 VT |
2419 | .remove_interface = ath9k_remove_interface, |
2420 | .config = ath9k_config, | |
8feceb67 | 2421 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2422 | .sta_add = ath9k_sta_add, |
2423 | .sta_remove = ath9k_sta_remove, | |
5519541d | 2424 | .sta_notify = ath9k_sta_notify, |
8feceb67 | 2425 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2426 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2427 | .set_key = ath9k_set_key, |
8feceb67 | 2428 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2429 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2430 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2431 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2432 | .get_survey = ath9k_get_survey, |
3b319aae | 2433 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2434 | .set_coverage_class = ath9k_set_coverage_class, |
69081624 | 2435 | .flush = ath9k_flush, |
15b91e83 | 2436 | .tx_frames_pending = ath9k_tx_frames_pending, |
52c94f41 | 2437 | .tx_last_beacon = ath9k_tx_last_beacon, |
86a22acf | 2438 | .release_buffered_frames = ath9k_release_buffered_frames, |
52c94f41 | 2439 | .get_stats = ath9k_get_stats, |
43c35284 FF |
2440 | .set_antenna = ath9k_set_antenna, |
2441 | .get_antenna = ath9k_get_antenna, | |
b90bd9d1 | 2442 | |
e60001e7 | 2443 | #ifdef CONFIG_ATH9K_WOW |
b11e640a MSS |
2444 | .suspend = ath9k_suspend, |
2445 | .resume = ath9k_resume, | |
2446 | .set_wakeup = ath9k_set_wakeup, | |
2447 | #endif | |
2448 | ||
b90bd9d1 BG |
2449 | #ifdef CONFIG_ATH9K_DEBUGFS |
2450 | .get_et_sset_count = ath9k_get_et_sset_count, | |
a145daf7 SM |
2451 | .get_et_stats = ath9k_get_et_stats, |
2452 | .get_et_strings = ath9k_get_et_strings, | |
2453 | #endif | |
2454 | ||
1cdbaf0d | 2455 | #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS) |
a145daf7 | 2456 | .sta_add_debugfs = ath9k_sta_add_debugfs, |
b90bd9d1 | 2457 | #endif |
e93d083f SW |
2458 | .sw_scan_start = ath9k_sw_scan_start, |
2459 | .sw_scan_complete = ath9k_sw_scan_complete, | |
8feceb67 | 2460 | }; |