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ath9k: add helper to un-init the hw properly
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
af03abec 19#include "btcoex.h"
f078f209 20
f078f209
LR		 21static char *dev_info = "ath9k";
22
23MODULE_AUTHOR("Atheros Communications");
24MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26MODULE_LICENSE("Dual BSD/GPL");
27
b3bd89ce
JM		 28static int modparam_nohwcrypt;
29module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
30MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
31
faa27fae
LR		 32static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
33module_param_named(debug, ath9k_debug, uint, 0);
34MODULE_PARM_DESC(ath9k_debug, "Debugging mask");
35
5f8e077c
LR		 36/* We use the hw_value as an index into our private channel structure */
37
38#define CHAN2G(_freq, _idx) { \
39 .center_freq = (_freq), \
40 .hw_value = (_idx), \
eeddfd9d 41 .max_power = 20, \
5f8e077c
LR		 42}
43
44#define CHAN5G(_freq, _idx) { \
45 .band = IEEE80211_BAND_5GHZ, \
46 .center_freq = (_freq), \
47 .hw_value = (_idx), \
eeddfd9d 48 .max_power = 20, \
5f8e077c
LR		 49}
50
51/* Some 2 GHz radios are actually tunable on 2312-2732
52 * on 5 MHz steps, we support the channels which we know
53 * we have calibration data for all cards though to make
54 * this static */
55static struct ieee80211_channel ath9k_2ghz_chantable[] = {
56 CHAN2G(2412, 0), /* Channel 1 */
57 CHAN2G(2417, 1), /* Channel 2 */
58 CHAN2G(2422, 2), /* Channel 3 */
59 CHAN2G(2427, 3), /* Channel 4 */
60 CHAN2G(2432, 4), /* Channel 5 */
61 CHAN2G(2437, 5), /* Channel 6 */
62 CHAN2G(2442, 6), /* Channel 7 */
63 CHAN2G(2447, 7), /* Channel 8 */
64 CHAN2G(2452, 8), /* Channel 9 */
65 CHAN2G(2457, 9), /* Channel 10 */
66 CHAN2G(2462, 10), /* Channel 11 */
67 CHAN2G(2467, 11), /* Channel 12 */
68 CHAN2G(2472, 12), /* Channel 13 */
69 CHAN2G(2484, 13), /* Channel 14 */
70};
71
72/* Some 5 GHz radios are actually tunable on XXXX-YYYY
73 * on 5 MHz steps, we support the channels which we know
74 * we have calibration data for all cards though to make
75 * this static */
76static struct ieee80211_channel ath9k_5ghz_chantable[] = {
77 /* _We_ call this UNII 1 */
78 CHAN5G(5180, 14), /* Channel 36 */
79 CHAN5G(5200, 15), /* Channel 40 */
80 CHAN5G(5220, 16), /* Channel 44 */
81 CHAN5G(5240, 17), /* Channel 48 */
82 /* _We_ call this UNII 2 */
83 CHAN5G(5260, 18), /* Channel 52 */
84 CHAN5G(5280, 19), /* Channel 56 */
85 CHAN5G(5300, 20), /* Channel 60 */
86 CHAN5G(5320, 21), /* Channel 64 */
87 /* _We_ call this "Middle band" */
88 CHAN5G(5500, 22), /* Channel 100 */
89 CHAN5G(5520, 23), /* Channel 104 */
90 CHAN5G(5540, 24), /* Channel 108 */
91 CHAN5G(5560, 25), /* Channel 112 */
92 CHAN5G(5580, 26), /* Channel 116 */
93 CHAN5G(5600, 27), /* Channel 120 */
94 CHAN5G(5620, 28), /* Channel 124 */
95 CHAN5G(5640, 29), /* Channel 128 */
96 CHAN5G(5660, 30), /* Channel 132 */
97 CHAN5G(5680, 31), /* Channel 136 */
98 CHAN5G(5700, 32), /* Channel 140 */
99 /* _We_ call this UNII 3 */
100 CHAN5G(5745, 33), /* Channel 149 */
101 CHAN5G(5765, 34), /* Channel 153 */
102 CHAN5G(5785, 35), /* Channel 157 */
103 CHAN5G(5805, 36), /* Channel 161 */
104 CHAN5G(5825, 37), /* Channel 165 */
105};
106
ce111bad
LR		 107static void ath_cache_conf_rate(struct ath_softc *sc,
108 struct ieee80211_conf *conf)
ff37e337 109{
030bb495
LR		 110 switch (conf->channel->band) {
111 case IEEE80211_BAND_2GHZ:
112 if (conf_is_ht20(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
115 else if (conf_is_ht40_minus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
118 else if (conf_is_ht40_plus(conf))
119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 121 else
030bb495
LR		 122 sc->cur_rate_table =
123 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 124 break;
125 case IEEE80211_BAND_5GHZ:
126 if (conf_is_ht20(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
129 else if (conf_is_ht40_minus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
132 else if (conf_is_ht40_plus(conf))
133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
135 else
96742256
LR		 136 sc->cur_rate_table =
137 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 138 break;
139 default:
ce111bad 140 BUG_ON(1);
030bb495
LR		 141 break;
142 }
ff37e337
S		 143}
144
145static void ath_update_txpow(struct ath_softc *sc)
146{
cbe61d8a 147 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 148 u32 txpow;
149
17d7904d
S		 150 if (sc->curtxpow != sc->config.txpowlimit) {
151 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 152 /* read back in case value is clamped */
153 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 154 sc->curtxpow = txpow;
ff37e337
S		 155 }
156}
157
158static u8 parse_mpdudensity(u8 mpdudensity)
159{
160 /*
161 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
162 * 0 for no restriction
163 * 1 for 1/4 us
164 * 2 for 1/2 us
165 * 3 for 1 us
166 * 4 for 2 us
167 * 5 for 4 us
168 * 6 for 8 us
169 * 7 for 16 us
170 */
171 switch (mpdudensity) {
172 case 0:
173 return 0;
174 case 1:
175 case 2:
176 case 3:
177 /* Our lower layer calculations limit our precision to
178 1 microsecond */
179 return 1;
180 case 4:
181 return 2;
182 case 5:
183 return 4;
184 case 6:
185 return 8;
186 case 7:
187 return 16;
188 default:
189 return 0;
190 }
191}
192
193static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
194{
4f0fc7c3 195 const struct ath_rate_table *rate_table = NULL;
ff37e337
S		 196 struct ieee80211_supported_band *sband;
197 struct ieee80211_rate *rate;
198 int i, maxrates;
199
200 switch (band) {
201 case IEEE80211_BAND_2GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
203 break;
204 case IEEE80211_BAND_5GHZ:
205 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
206 break;
207 default:
208 break;
209 }
210
211 if (rate_table == NULL)
212 return;
213
214 sband = &sc->sbands[band];
215 rate = sc->rates[band];
216
217 if (rate_table->rate_cnt > ATH_RATE_MAX)
218 maxrates = ATH_RATE_MAX;
219 else
220 maxrates = rate_table->rate_cnt;
221
222 for (i = 0; i < maxrates; i++) {
223 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
224 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 225 if (rate_table->info[i].short_preamble) {
226 rate[i].hw_value_short = rate_table->info[i].ratecode |
227 rate_table->info[i].short_preamble;
228 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
229 }
ff37e337 230 sband->n_bitrates++;
f46730d1 231
c46917bb
LR		 232 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
233 "Rate: %2dMbps, ratecode: %2d\n",
234 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 235 }
236}
237
82880a7c
VT		 238static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
239 struct ieee80211_hw *hw)
240{
241 struct ieee80211_channel *curchan = hw->conf.channel;
242 struct ath9k_channel *channel;
243 u8 chan_idx;
244
245 chan_idx = curchan->hw_value;
246 channel = &sc->sc_ah->channels[chan_idx];
247 ath9k_update_ichannel(sc, hw, channel);
248 return channel;
249}
250
9ecdef4b 251static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR		 252{
253 unsigned long flags;
254 bool ret;
255
9ecdef4b
LR		 256 spin_lock_irqsave(&sc->sc_pm_lock, flags);
257 ret = ath9k_hw_setpower(sc->sc_ah, mode);
258 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR		 259
260 return ret;
261}
262
a91d75ae
LR		 263void ath9k_ps_wakeup(struct ath_softc *sc)
264{
265 unsigned long flags;
266
267 spin_lock_irqsave(&sc->sc_pm_lock, flags);
268 if (++sc->ps_usecount != 1)
269 goto unlock;
270
9ecdef4b 271 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae
LR		 272
273 unlock:
274 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
275}
276
277void ath9k_ps_restore(struct ath_softc *sc)
278{
279 unsigned long flags;
280
281 spin_lock_irqsave(&sc->sc_pm_lock, flags);
282 if (--sc->ps_usecount != 0)
283 goto unlock;
284
285 if (sc->ps_enabled &&
286 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
287 SC_OP_WAIT_FOR_CAB |
288 SC_OP_WAIT_FOR_PSPOLL_DATA |
289 SC_OP_WAIT_FOR_TX_ACK)))
9ecdef4b 290 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR		 291
292 unlock:
293 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
294}
295
ff37e337
S		 296/*
297 * Set/change channels. If the channel is really being changed, it's done
298 * by reseting the chip. To accomplish this we must first cleanup any pending
299 * DMA, then restart stuff.
300*/
0e2dedf9
JM		 301int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
302 struct ath9k_channel *hchan)
ff37e337 303{
cbe61d8a 304 struct ath_hw *ah = sc->sc_ah;
c46917bb 305 struct ath_common *common = ath9k_hw_common(ah);
25c56eec 306 struct ieee80211_conf *conf = &common->hw->conf;
ff37e337 307 bool fastcc = true, stopped;
ae8d2858
LR		 308 struct ieee80211_channel *channel = hw->conf.channel;
309 int r;
ff37e337
S		 310
311 if (sc->sc_flags & SC_OP_INVALID)
312 return -EIO;
313
3cbb5dd7
VN		 314 ath9k_ps_wakeup(sc);
315
c0d7c7af
LR		 316 /*
317 * This is only performed if the channel settings have
318 * actually changed.
319 *
320 * To switch channels clear any pending DMA operations;
321 * wait long enough for the RX fifo to drain, reset the
322 * hardware at the new frequency, and then re-enable
323 * the relevant bits of the h/w.
324 */
325 ath9k_hw_set_interrupts(ah, 0);
043a0405 326 ath_drain_all_txq(sc, false);
c0d7c7af 327 stopped = ath_stoprecv(sc);
ff37e337 328
c0d7c7af
LR		 329 /* XXX: do not flush receive queue here. We don't want
330 * to flush data frames already in queue because of
331 * changing channel. */
ff37e337 332
c0d7c7af
LR		 333 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
334 fastcc = false;
335
c46917bb 336 ath_print(common, ATH_DBG_CONFIG,
25c56eec 337 "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
c46917bb 338 sc->sc_ah->curchan->channel,
25c56eec 339 channel->center_freq, conf_is_ht40(conf));
ff37e337 340
c0d7c7af
LR		 341 spin_lock_bh(&sc->sc_resetlock);
342
343 r = ath9k_hw_reset(ah, hchan, fastcc);
344 if (r) {
c46917bb
LR		 345 ath_print(common, ATH_DBG_FATAL,
346 "Unable to reset channel (%u Mhz) "
347 "reset status %d\n",
348 channel->center_freq, r);
c0d7c7af 349 spin_unlock_bh(&sc->sc_resetlock);
3989279c 350 goto ps_restore;
ff37e337 351 }
c0d7c7af
LR		 352 spin_unlock_bh(&sc->sc_resetlock);
353
c0d7c7af
LR		 354 sc->sc_flags &= ~SC_OP_FULL_RESET;
355
356 if (ath_startrecv(sc) != 0) {
c46917bb
LR		 357 ath_print(common, ATH_DBG_FATAL,
358 "Unable to restart recv logic\n");
3989279c
GJ		 359 r = -EIO;
360 goto ps_restore;
c0d7c7af
LR		 361 }
362
363 ath_cache_conf_rate(sc, &hw->conf);
364 ath_update_txpow(sc);
17d7904d 365 ath9k_hw_set_interrupts(ah, sc->imask);
3989279c
GJ		 366
367 ps_restore:
3cbb5dd7 368 ath9k_ps_restore(sc);
3989279c 369 return r;
ff37e337
S		 370}
371
372/*
373 * This routine performs the periodic noise floor calibration function
374 * that is used to adjust and optimize the chip performance. This
375 * takes environmental changes (location, temperature) into account.
376 * When the task is complete, it reschedules itself depending on the
377 * appropriate interval that was calculated.
378 */
379static void ath_ani_calibrate(unsigned long data)
380{
20977d3e
S		 381 struct ath_softc *sc = (struct ath_softc *)data;
382 struct ath_hw *ah = sc->sc_ah;
c46917bb 383 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S		 384 bool longcal = false;
385 bool shortcal = false;
386 bool aniflag = false;
387 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 388 u32 cal_interval, short_cal_interval;
ff37e337 389
20977d3e
S		 390 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
391 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 392
393 /*
394 * don't calibrate when we're scanning.
395 * we are most likely not on our home channel.
396 */
e5f0921a 397 spin_lock(&sc->ani_lock);
0c98de65 398 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 399 goto set_timer;
ff37e337 400
1ffc1c61
JM		 401 /* Only calibrate if awake */
402 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
403 goto set_timer;
404
405 ath9k_ps_wakeup(sc);
406
ff37e337 407 /* Long calibration runs independently of short calibration. */
17d7904d 408 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 409 longcal = true;
c46917bb 410 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 411 sc->ani.longcal_timer = timestamp;
ff37e337
S		 412 }
413
17d7904d
S		 414 /* Short calibration applies only while caldone is false */
415 if (!sc->ani.caldone) {
20977d3e 416 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 417 shortcal = true;
c46917bb
LR		 418 ath_print(common, ATH_DBG_ANI,
419 "shortcal @%lu\n", jiffies);
17d7904d
S		 420 sc->ani.shortcal_timer = timestamp;
421 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 422 }
423 } else {
17d7904d 424 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 425 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 426 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
427 if (sc->ani.caldone)
428 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 429 }
430 }
431
432 /* Verify whether we must check ANI */
20977d3e 433 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 434 aniflag = true;
17d7904d 435 sc->ani.checkani_timer = timestamp;
ff37e337
S		 436 }
437
438 /* Skip all processing if there's nothing to do. */
439 if (longcal || shortcal || aniflag) {
440 /* Call ANI routine if necessary */
441 if (aniflag)
22e66a4c 442 ath9k_hw_ani_monitor(ah, ah->curchan);
ff37e337
S		 443
444 /* Perform calibration if necessary */
445 if (longcal || shortcal) {
43c27613
LR		 446 sc->ani.caldone =
447 ath9k_hw_calibrate(ah,
448 ah->curchan,
449 common->rx_chainmask,
450 longcal);
379f0440
S		 451
452 if (longcal)
453 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
454 ah->curchan);
455
c46917bb
LR		 456 ath_print(common, ATH_DBG_ANI,
457 " calibrate chan %u/%x nf: %d\n",
458 ah->curchan->channel,
459 ah->curchan->channelFlags,
460 sc->ani.noise_floor);
ff37e337
S		 461 }
462 }
463
1ffc1c61
JM		 464 ath9k_ps_restore(sc);
465
20977d3e 466set_timer:
e5f0921a 467 spin_unlock(&sc->ani_lock);
ff37e337
S		 468 /*
469 * Set timer interval based on previous results.
470 * The interval must be the shortest necessary to satisfy ANI,
471 * short calibration and long calibration.
472 */
aac9207e 473 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 474 if (sc->sc_ah->config.enable_ani)
aac9207e 475 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 476 if (!sc->ani.caldone)
20977d3e 477 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 478
17d7904d 479 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 480}
481
415f738e
S		 482static void ath_start_ani(struct ath_softc *sc)
483{
484 unsigned long timestamp = jiffies_to_msecs(jiffies);
485
486 sc->ani.longcal_timer = timestamp;
487 sc->ani.shortcal_timer = timestamp;
488 sc->ani.checkani_timer = timestamp;
489
490 mod_timer(&sc->ani.timer,
491 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
492}
493
ff37e337
S		 494/*
495 * Update tx/rx chainmask. For legacy association,
496 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 497 * the chainmask configuration, for bt coexistence, use
498 * the chainmask configuration even in legacy mode.
ff37e337 499 */
0e2dedf9 500void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 501{
af03abec 502 struct ath_hw *ah = sc->sc_ah;
43c27613 503 struct ath_common *common = ath9k_hw_common(ah);
af03abec 504
3d832611 505 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
766ec4a9 506 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
43c27613
LR		 507 common->tx_chainmask = ah->caps.tx_chainmask;
508 common->rx_chainmask = ah->caps.rx_chainmask;
ff37e337 509 } else {
43c27613
LR		 510 common->tx_chainmask = 1;
511 common->rx_chainmask = 1;
ff37e337
S		 512 }
513
43c27613 514 ath_print(common, ATH_DBG_CONFIG,
c46917bb 515 "tx chmask: %d, rx chmask: %d\n",
43c27613
LR		 516 common->tx_chainmask,
517 common->rx_chainmask);
ff37e337
S		 518}
519
520static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
521{
522 struct ath_node *an;
523
524 an = (struct ath_node *)sta->drv_priv;
525
87792efc 526 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 527 ath_tx_node_init(sc, an);
9e98ac65 528 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S		 529 sta->ht_cap.ampdu_factor);
530 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
a59b5a5e 531 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
87792efc 532 }
ff37e337
S		 533}
534
535static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
536{
537 struct ath_node *an = (struct ath_node *)sta->drv_priv;
538
539 if (sc->sc_flags & SC_OP_TXAGGR)
540 ath_tx_node_cleanup(sc, an);
541}
542
543static void ath9k_tasklet(unsigned long data)
544{
545 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 546 struct ath_hw *ah = sc->sc_ah;
c46917bb 547 struct ath_common *common = ath9k_hw_common(ah);
af03abec 548
17d7904d 549 u32 status = sc->intrstatus;
ff37e337 550
153e080d
VT		 551 ath9k_ps_wakeup(sc);
552
ff37e337 553 if (status & ATH9K_INT_FATAL) {
ff37e337 554 ath_reset(sc, false);
153e080d 555 ath9k_ps_restore(sc);
ff37e337 556 return;
063d8be3 557 }
ff37e337 558
063d8be3
S		 559 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
560 spin_lock_bh(&sc->rx.rxflushlock);
561 ath_rx_tasklet(sc, 0);
562 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 563 }
564
063d8be3
S		 565 if (status & ATH9K_INT_TX)
566 ath_tx_tasklet(sc);
567
96148326 568 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM		 569 /*
570 * TSF sync does not look correct; remain awake to sync with
571 * the next Beacon.
572 */
c46917bb
LR		 573 ath_print(common, ATH_DBG_PS,
574 "TSFOOR - Sync with next Beacon\n");
ccdfeab6 575 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
54ce846e
JM		 576 }
577
766ec4a9 578 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT		 579 if (status & ATH9K_INT_GENTIMER)
580 ath_gen_timer_isr(sc->sc_ah);
581
ff37e337 582 /* re-enable hardware interrupt */
af03abec 583 ath9k_hw_set_interrupts(ah, sc->imask);
153e080d 584 ath9k_ps_restore(sc);
ff37e337
S		 585}
586
6baff7f9 587irqreturn_t ath_isr(int irq, void *dev)
ff37e337 588{
063d8be3
S		 589#define SCHED_INTR ( \
590 ATH9K_INT_FATAL | \
591 ATH9K_INT_RXORN | \
592 ATH9K_INT_RXEOL | \
593 ATH9K_INT_RX | \
594 ATH9K_INT_TX | \
595 ATH9K_INT_BMISS | \
596 ATH9K_INT_CST | \
ebb8e1d7
VT		 597 ATH9K_INT_TSFOOR | \
598 ATH9K_INT_GENTIMER)
063d8be3 599
ff37e337 600 struct ath_softc *sc = dev;
cbe61d8a 601 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 602 enum ath9k_int status;
603 bool sched = false;
604
063d8be3
S		 605 /*
606 * The hardware is not ready/present, don't
607 * touch anything. Note this can happen early
608 * on if the IRQ is shared.
609 */
610 if (sc->sc_flags & SC_OP_INVALID)
611 return IRQ_NONE;
ff37e337 612
063d8be3
S		 613
614 /* shared irq, not for us */
615
153e080d 616 if (!ath9k_hw_intrpend(ah))
063d8be3 617 return IRQ_NONE;
063d8be3
S		 618
619 /*
620 * Figure out the reason(s) for the interrupt. Note
621 * that the hal returns a pseudo-ISR that may include
622 * bits we haven't explicitly enabled so we mask the
623 * value to insure we only process bits we requested.
624 */
625 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
626 status &= sc->imask; /* discard unasked-for bits */
ff37e337 627
063d8be3
S		 628 /*
629 * If there are no status bits set, then this interrupt was not
630 * for me (should have been caught above).
631 */
153e080d 632 if (!status)
063d8be3 633 return IRQ_NONE;
ff37e337 634
063d8be3
S		 635 /* Cache the status */
636 sc->intrstatus = status;
637
638 if (status & SCHED_INTR)
639 sched = true;
640
641 /*
642 * If a FATAL or RXORN interrupt is received, we have to reset the
643 * chip immediately.
644 */
645 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
646 goto chip_reset;
647
648 if (status & ATH9K_INT_SWBA)
649 tasklet_schedule(&sc->bcon_tasklet);
650
651 if (status & ATH9K_INT_TXURN)
652 ath9k_hw_updatetxtriglevel(ah, true);
653
654 if (status & ATH9K_INT_MIB) {
ff37e337 655 /*
063d8be3
S		 656 * Disable interrupts until we service the MIB
657 * interrupt; otherwise it will continue to
658 * fire.
ff37e337 659 */
063d8be3
S		 660 ath9k_hw_set_interrupts(ah, 0);
661 /*
662 * Let the hal handle the event. We assume
663 * it will clear whatever condition caused
664 * the interrupt.
665 */
22e66a4c 666 ath9k_hw_procmibevent(ah);
063d8be3
S		 667 ath9k_hw_set_interrupts(ah, sc->imask);
668 }
ff37e337 669
153e080d
VT		 670 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
671 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S		 672 /* Clear RxAbort bit so that we can
673 * receive frames */
9ecdef4b 674 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 675 ath9k_hw_setrxabort(sc->sc_ah, 0);
063d8be3 676 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 677 }
063d8be3
S		 678
679chip_reset:
ff37e337 680
817e11de
S		 681 ath_debug_stat_interrupt(sc, status);
682
ff37e337
S		 683 if (sched) {
684 /* turn off every interrupt except SWBA */
17d7904d 685 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 686 tasklet_schedule(&sc->intr_tq);
687 }
688
689 return IRQ_HANDLED;
063d8be3
S		 690
691#undef SCHED_INTR
ff37e337
S		 692}
693
f078f209 694static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 695 struct ieee80211_channel *chan,
094d05dc 696 enum nl80211_channel_type channel_type)
f078f209
LR		 697{
698 u32 chanmode = 0;
f078f209
LR		 699
700 switch (chan->band) {
701 case IEEE80211_BAND_2GHZ:
094d05dc
S		 702 switch(channel_type) {
703 case NL80211_CHAN_NO_HT:
704 case NL80211_CHAN_HT20:
f078f209 705 chanmode = CHANNEL_G_HT20;
094d05dc
S		 706 break;
707 case NL80211_CHAN_HT40PLUS:
f078f209 708 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 709 break;
710 case NL80211_CHAN_HT40MINUS:
f078f209 711 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 712 break;
713 }
f078f209
LR		 714 break;
715 case IEEE80211_BAND_5GHZ:
094d05dc
S		 716 switch(channel_type) {
717 case NL80211_CHAN_NO_HT:
718 case NL80211_CHAN_HT20:
f078f209 719 chanmode = CHANNEL_A_HT20;
094d05dc
S		 720 break;
721 case NL80211_CHAN_HT40PLUS:
f078f209 722 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 723 break;
724 case NL80211_CHAN_HT40MINUS:
f078f209 725 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 726 break;
727 }
f078f209
LR		 728 break;
729 default:
730 break;
731 }
732
733 return chanmode;
734}
735
6ace2891 736static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 737 struct ath9k_keyval *hk, const u8 *addr,
738 bool authenticator)
f078f209 739{
6ace2891
JM		 740 const u8 *key_rxmic;
741 const u8 *key_txmic;
f078f209 742
6ace2891
JM		 743 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
744 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 745
746 if (addr == NULL) {
d216aaa6
JM		 747 /*
748 * Group key installation - only two key cache entries are used
749 * regardless of splitmic capability since group key is only
750 * used either for TX or RX.
751 */
3f53dd64
JM		 752 if (authenticator) {
753 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
754 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
755 } else {
756 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
757 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
758 }
d216aaa6 759 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 760 }
17d7904d 761 if (!sc->splitmic) {
d216aaa6 762 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 763 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
764 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 765 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 766 }
d216aaa6
JM		 767
768 /* Separate key cache entries for TX and RX */
769
770 /* TX key goes at first index, RX key at +32. */
f078f209 771 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 772 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
773 /* TX MIC entry failed. No need to proceed further */
c46917bb
LR		 774 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
775 "Setting TX MIC Key Failed\n");
f078f209
LR		 776 return 0;
777 }
778
779 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
780 /* XXX delete tx key on failure? */
d216aaa6 781 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 782}
783
784static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
785{
786 int i;
787
17d7904d
S		 788 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
789 if (test_bit(i, sc->keymap) ||
790 test_bit(i + 64, sc->keymap))
6ace2891 791 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 792 if (sc->splitmic &&
793 (test_bit(i + 32, sc->keymap) ||
794 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 795 continue; /* At least one part of TKIP key allocated */
796
797 /* Found a free slot for a TKIP key */
798 return i;
799 }
800 return -1;
801}
802
803static int ath_reserve_key_cache_slot(struct ath_softc *sc)
804{
805 int i;
806
807 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 808 if (sc->splitmic) {
809 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
810 if (!test_bit(i, sc->keymap) &&
811 (test_bit(i + 32, sc->keymap) ||
812 test_bit(i + 64, sc->keymap) ||
813 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 814 return i;
17d7904d
S		 815 if (!test_bit(i + 32, sc->keymap) &&
816 (test_bit(i, sc->keymap) ||
817 test_bit(i + 64, sc->keymap) ||
818 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 819 return i + 32;
17d7904d
S		 820 if (!test_bit(i + 64, sc->keymap) &&
821 (test_bit(i , sc->keymap) ||
822 test_bit(i + 32, sc->keymap) ||
823 test_bit(i + 64 + 32, sc->keymap)))
ea612132 824 return i + 64;
17d7904d
S		 825 if (!test_bit(i + 64 + 32, sc->keymap) &&
826 (test_bit(i, sc->keymap) ||
827 test_bit(i + 32, sc->keymap) ||
828 test_bit(i + 64, sc->keymap)))
ea612132 829 return i + 64 + 32;
6ace2891
JM		 830 }
831 } else {
17d7904d
S		 832 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
833 if (!test_bit(i, sc->keymap) &&
834 test_bit(i + 64, sc->keymap))
6ace2891 835 return i;
17d7904d
S		 836 if (test_bit(i, sc->keymap) &&
837 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 838 return i + 64;
839 }
840 }
841
842 /* No partially used TKIP slots, pick any available slot */
17d7904d 843 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 844 /* Do not allow slots that could be needed for TKIP group keys
845 * to be used. This limitation could be removed if we know that
846 * TKIP will not be used. */
847 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
848 continue;
17d7904d 849 if (sc->splitmic) {
be2864cf
JM		 850 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
851 continue;
852 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
853 continue;
854 }
855
17d7904d 856 if (!test_bit(i, sc->keymap))
6ace2891
JM		 857 return i; /* Found a free slot for a key */
858 }
859
860 /* No free slot found */
861 return -1;
f078f209
LR		 862}
863
864static int ath_key_config(struct ath_softc *sc,
3f53dd64 865 struct ieee80211_vif *vif,
dc822b5d 866 struct ieee80211_sta *sta,
f078f209
LR		 867 struct ieee80211_key_conf *key)
868{
f078f209
LR		 869 struct ath9k_keyval hk;
870 const u8 *mac = NULL;
871 int ret = 0;
6ace2891 872 int idx;
f078f209
LR		 873
874 memset(&hk, 0, sizeof(hk));
875
876 switch (key->alg) {
877 case ALG_WEP:
878 hk.kv_type = ATH9K_CIPHER_WEP;
879 break;
880 case ALG_TKIP:
881 hk.kv_type = ATH9K_CIPHER_TKIP;
882 break;
883 case ALG_CCMP:
884 hk.kv_type = ATH9K_CIPHER_AES_CCM;
885 break;
886 default:
ca470b29 887 return -EOPNOTSUPP;
f078f209
LR		 888 }
889
6ace2891 890 hk.kv_len = key->keylen;
f078f209
LR		 891 memcpy(hk.kv_val, key->key, key->keylen);
892
6ace2891
JM		 893 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
894 /* For now, use the default keys for broadcast keys. This may
895 * need to change with virtual interfaces. */
896 idx = key->keyidx;
897 } else if (key->keyidx) {
dc822b5d
JB		 898 if (WARN_ON(!sta))
899 return -EOPNOTSUPP;
900 mac = sta->addr;
901
6ace2891
JM		 902 if (vif->type != NL80211_IFTYPE_AP) {
903 /* Only keyidx 0 should be used with unicast key, but
904 * allow this for client mode for now. */
905 idx = key->keyidx;
906 } else
907 return -EIO;
f078f209 908 } else {
dc822b5d
JB		 909 if (WARN_ON(!sta))
910 return -EOPNOTSUPP;
911 mac = sta->addr;
912
6ace2891
JM		 913 if (key->alg == ALG_TKIP)
914 idx = ath_reserve_key_cache_slot_tkip(sc);
915 else
916 idx = ath_reserve_key_cache_slot(sc);
917 if (idx < 0)
ca470b29 918 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 919 }
920
921 if (key->alg == ALG_TKIP)
3f53dd64
JM		 922 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
923 vif->type == NL80211_IFTYPE_AP);
f078f209 924 else
d216aaa6 925 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 926
927 if (!ret)
928 return -EIO;
929
17d7904d 930 set_bit(idx, sc->keymap);
6ace2891 931 if (key->alg == ALG_TKIP) {
17d7904d
S		 932 set_bit(idx + 64, sc->keymap);
933 if (sc->splitmic) {
934 set_bit(idx + 32, sc->keymap);
935 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 936 }
937 }
938
939 return idx;
f078f209
LR		 940}
941
942static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
943{
6ace2891
JM		 944 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
945 if (key->hw_key_idx < IEEE80211_WEP_NKID)
946 return;
947
17d7904d 948 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 949 if (key->alg != ALG_TKIP)
950 return;
f078f209 951
17d7904d
S		 952 clear_bit(key->hw_key_idx + 64, sc->keymap);
953 if (sc->splitmic) {
954 clear_bit(key->hw_key_idx + 32, sc->keymap);
955 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 956 }
f078f209
LR		 957}
958
eb2599ca
S		 959static void setup_ht_cap(struct ath_softc *sc,
960 struct ieee80211_sta_ht_cap *ht_info)
f078f209 961{
43c27613 962 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
140add21 963 u8 tx_streams, rx_streams;
f078f209 964
d9fe60de
JB		 965 ht_info->ht_supported = true;
966 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
967 IEEE80211_HT_CAP_SM_PS |
968 IEEE80211_HT_CAP_SGI_40 |
969 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 970
9e98ac65
S		 971 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
972 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
eb2599ca 973
d9fe60de
JB		 974 /* set up supported mcs set */
975 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
43c27613
LR		 976 tx_streams = !(common->tx_chainmask & (common->tx_chainmask - 1)) ?
977 1 : 2;
978 rx_streams = !(common->rx_chainmask & (common->rx_chainmask - 1)) ?
979 1 : 2;
140add21
SB		 980
981 if (tx_streams != rx_streams) {
43c27613 982 ath_print(common, ATH_DBG_CONFIG,
c46917bb
LR		 983 "TX streams %d, RX streams: %d\n",
984 tx_streams, rx_streams);
140add21
SB		 985 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
986 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
987 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
988 }
eb2599ca 989
140add21
SB		 990 ht_info->mcs.rx_mask[0] = 0xff;
991 if (rx_streams >= 2)
eb2599ca 992 ht_info->mcs.rx_mask[1] = 0xff;
eb2599ca 993
140add21 994 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 995}
996
8feceb67 997static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 998 struct ieee80211_vif *vif,
8feceb67 999 struct ieee80211_bss_conf *bss_conf)
f078f209 1000{
f2b2143e 1001 struct ath_hw *ah = sc->sc_ah;
1510718d 1002 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1003
8feceb67 1004 if (bss_conf->assoc) {
c46917bb
LR		 1005 ath_print(common, ATH_DBG_CONFIG,
1006 "Bss Info ASSOC %d, bssid: %pM\n",
1007 bss_conf->aid, common->curbssid);
f078f209 1008
8feceb67 1009 /* New association, store aid */
1510718d 1010 common->curaid = bss_conf->aid;
f2b2143e 1011 ath9k_hw_write_associd(ah);
2664f201
SB		 1012
1013 /*
1014 * Request a re-configuration of Beacon related timers
1015 * on the receipt of the first Beacon frame (i.e.,
1016 * after time sync with the AP).
1017 */
1018 sc->sc_flags |= SC_OP_BEACON_SYNC;
f078f209 1019
8feceb67 1020 /* Configure the beacon */
2c3db3d5 1021 ath_beacon_config(sc, vif);
f078f209 1022
8feceb67 1023 /* Reset rssi stats */
22e66a4c 1024 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 1025
415f738e 1026 ath_start_ani(sc);
8feceb67 1027 } else {
c46917bb 1028 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1510718d 1029 common->curaid = 0;
f38faa31
SB		 1030 /* Stop ANI */
1031 del_timer_sync(&sc->ani.timer);
f078f209 1032 }
8feceb67 1033}
f078f209 1034
8feceb67
VT		 1035/********************************/
1036/* LED functions */
1037/********************************/
f078f209 1038
f2bffa7e
VT		 1039static void ath_led_blink_work(struct work_struct *work)
1040{
1041 struct ath_softc *sc = container_of(work, struct ath_softc,
1042 ath_led_blink_work.work);
1043
1044 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
1045 return;
85067c06
VT		 1046
1047 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
1048 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
08fc5c1b 1049 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
85067c06 1050 else
08fc5c1b 1051 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
85067c06 1052 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e 1053
42935eca
LR		 1054 ieee80211_queue_delayed_work(sc->hw,
1055 &sc->ath_led_blink_work,
1056 (sc->sc_flags & SC_OP_LED_ON) ?
1057 msecs_to_jiffies(sc->led_off_duration) :
1058 msecs_to_jiffies(sc->led_on_duration));
f2bffa7e 1059
85067c06
VT		 1060 sc->led_on_duration = sc->led_on_cnt ?
1061 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
1062 ATH_LED_ON_DURATION_IDLE;
1063 sc->led_off_duration = sc->led_off_cnt ?
1064 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
1065 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 1066 sc->led_on_cnt = sc->led_off_cnt = 0;
1067 if (sc->sc_flags & SC_OP_LED_ON)
1068 sc->sc_flags &= ~SC_OP_LED_ON;
1069 else
1070 sc->sc_flags |= SC_OP_LED_ON;
1071}
1072
8feceb67
VT		 1073static void ath_led_brightness(struct led_classdev *led_cdev,
1074 enum led_brightness brightness)
1075{
1076 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1077 struct ath_softc *sc = led->sc;
f078f209 1078
8feceb67
VT		 1079 switch (brightness) {
1080 case LED_OFF:
1081 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e 1082 led->led_type == ATH_LED_RADIO) {
08fc5c1b 1083 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
f2bffa7e 1084 (led->led_type == ATH_LED_RADIO));
8feceb67 1085 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1086 if (led->led_type == ATH_LED_RADIO)
1087 sc->sc_flags &= ~SC_OP_LED_ON;
1088 } else {
1089 sc->led_off_cnt++;
1090 }
8feceb67
VT		 1091 break;
1092 case LED_FULL:
f2bffa7e 1093 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 1094 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
42935eca
LR		 1095 ieee80211_queue_delayed_work(sc->hw,
1096 &sc->ath_led_blink_work, 0);
f2bffa7e 1097 } else if (led->led_type == ATH_LED_RADIO) {
08fc5c1b 1098 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
f2bffa7e
VT		 1099 sc->sc_flags |= SC_OP_LED_ON;
1100 } else {
1101 sc->led_on_cnt++;
1102 }
8feceb67
VT		 1103 break;
1104 default:
1105 break;
f078f209 1106 }
8feceb67 1107}
f078f209 1108
8feceb67
VT		 1109static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1110 char *trigger)
1111{
1112 int ret;
f078f209 1113
8feceb67
VT		 1114 led->sc = sc;
1115 led->led_cdev.name = led->name;
1116 led->led_cdev.default_trigger = trigger;
1117 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1118
8feceb67
VT		 1119 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1120 if (ret)
c46917bb
LR		 1121 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1122 "Failed to register led:%s", led->name);
8feceb67
VT		 1123 else
1124 led->registered = 1;
1125 return ret;
1126}
f078f209 1127
8feceb67
VT		 1128static void ath_unregister_led(struct ath_led *led)
1129{
1130 if (led->registered) {
1131 led_classdev_unregister(&led->led_cdev);
1132 led->registered = 0;
f078f209 1133 }
f078f209
LR		 1134}
1135
8feceb67 1136static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1137{
8feceb67
VT		 1138 ath_unregister_led(&sc->assoc_led);
1139 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1140 ath_unregister_led(&sc->tx_led);
1141 ath_unregister_led(&sc->rx_led);
1142 ath_unregister_led(&sc->radio_led);
08fc5c1b 1143 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
8feceb67 1144}
f078f209 1145
8feceb67
VT		 1146static void ath_init_leds(struct ath_softc *sc)
1147{
1148 char *trigger;
1149 int ret;
f078f209 1150
08fc5c1b
VN		 1151 if (AR_SREV_9287(sc->sc_ah))
1152 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1153 else
1154 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1155
8feceb67 1156 /* Configure gpio 1 for output */
08fc5c1b 1157 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
8feceb67
VT		 1158 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1159 /* LED off, active low */
08fc5c1b 1160 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
7dcfdcd9 1161
f2bffa7e
VT		 1162 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1163
8feceb67
VT		 1164 trigger = ieee80211_get_radio_led_name(sc->hw);
1165 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1166 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1167 ret = ath_register_led(sc, &sc->radio_led, trigger);
1168 sc->radio_led.led_type = ATH_LED_RADIO;
1169 if (ret)
1170 goto fail;
7dcfdcd9 1171
8feceb67
VT		 1172 trigger = ieee80211_get_assoc_led_name(sc->hw);
1173 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1174 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1175 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1176 sc->assoc_led.led_type = ATH_LED_ASSOC;
1177 if (ret)
1178 goto fail;
f078f209 1179
8feceb67
VT		 1180 trigger = ieee80211_get_tx_led_name(sc->hw);
1181 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1182 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1183 ret = ath_register_led(sc, &sc->tx_led, trigger);
1184 sc->tx_led.led_type = ATH_LED_TX;
1185 if (ret)
1186 goto fail;
f078f209 1187
8feceb67
VT		 1188 trigger = ieee80211_get_rx_led_name(sc->hw);
1189 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1190 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1191 ret = ath_register_led(sc, &sc->rx_led, trigger);
1192 sc->rx_led.led_type = ATH_LED_RX;
1193 if (ret)
1194 goto fail;
f078f209 1195
8feceb67
VT		 1196 return;
1197
1198fail:
35c95ab9 1199 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67 1200 ath_deinit_leds(sc);
f078f209
LR		 1201}
1202
7ec3e514 1203void ath_radio_enable(struct ath_softc *sc)
500c064d 1204{
cbe61d8a 1205 struct ath_hw *ah = sc->sc_ah;
c46917bb 1206 struct ath_common *common = ath9k_hw_common(ah);
ae8d2858
LR		 1207 struct ieee80211_channel *channel = sc->hw->conf.channel;
1208 int r;
500c064d 1209
3cbb5dd7 1210 ath9k_ps_wakeup(sc);
93b1b37f 1211 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 1212
159cd468
VT		 1213 if (!ah->curchan)
1214 ah->curchan = ath_get_curchannel(sc, sc->hw);
1215
d2f5b3a6 1216 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1217 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1218 if (r) {
c46917bb
LR		 1219 ath_print(common, ATH_DBG_FATAL,
1220 "Unable to reset channel %u (%uMhz) ",
1221 "reset status %d\n",
1222 channel->center_freq, r);
500c064d
VT		 1223 }
1224 spin_unlock_bh(&sc->sc_resetlock);
1225
1226 ath_update_txpow(sc);
1227 if (ath_startrecv(sc) != 0) {
c46917bb
LR		 1228 ath_print(common, ATH_DBG_FATAL,
1229 "Unable to restart recv logic\n");
500c064d
VT		 1230 return;
1231 }
1232
1233 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1234 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1235
1236 /* Re-Enable interrupts */
17d7904d 1237 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1238
1239 /* Enable LED */
08fc5c1b 1240 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 1241 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 1242 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d
VT		 1243
1244 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1245 ath9k_ps_restore(sc);
500c064d
VT		 1246}
1247
7ec3e514 1248void ath_radio_disable(struct ath_softc *sc)
500c064d 1249{
cbe61d8a 1250 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1251 struct ieee80211_channel *channel = sc->hw->conf.channel;
1252 int r;
500c064d 1253
3cbb5dd7 1254 ath9k_ps_wakeup(sc);
500c064d
VT		 1255 ieee80211_stop_queues(sc->hw);
1256
1257 /* Disable LED */
08fc5c1b
VN		 1258 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1259 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
500c064d
VT		 1260
1261 /* Disable interrupts */
1262 ath9k_hw_set_interrupts(ah, 0);
1263
043a0405 1264 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1265 ath_stoprecv(sc); /* turn off frame recv */
1266 ath_flushrecv(sc); /* flush recv queue */
1267
159cd468
VT		 1268 if (!ah->curchan)
1269 ah->curchan = ath_get_curchannel(sc, sc->hw);
1270
500c064d 1271 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1272 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1273 if (r) {
c46917bb
LR		 1274 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1275 "Unable to reset channel %u (%uMhz) "
1276 "reset status %d\n",
1277 channel->center_freq, r);
500c064d
VT		 1278 }
1279 spin_unlock_bh(&sc->sc_resetlock);
1280
1281 ath9k_hw_phy_disable(ah);
93b1b37f 1282 ath9k_hw_configpcipowersave(ah, 1, 1);
3cbb5dd7 1283 ath9k_ps_restore(sc);
9ecdef4b 1284 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
500c064d
VT		 1285}
1286
5077fd35
GJ		 1287/*******************/
1288/* Rfkill */
1289/*******************/
1290
500c064d
VT		 1291static bool ath_is_rfkill_set(struct ath_softc *sc)
1292{
cbe61d8a 1293 struct ath_hw *ah = sc->sc_ah;
500c064d 1294
2660b81a
S		 1295 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1296 ah->rfkill_polarity;
500c064d
VT		 1297}
1298
3b319aae 1299static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
500c064d 1300{
3b319aae
JB		 1301 struct ath_wiphy *aphy = hw->priv;
1302 struct ath_softc *sc = aphy->sc;
19d337df 1303 bool blocked = !!ath_is_rfkill_set(sc);
500c064d 1304
3b319aae 1305 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
500c064d
VT		 1306}
1307
3b319aae 1308static void ath_start_rfkill_poll(struct ath_softc *sc)
500c064d 1309{
3b319aae 1310 struct ath_hw *ah = sc->sc_ah;
9c84b797 1311
3b319aae
JB		 1312 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1313 wiphy_rfkill_start_polling(sc->hw->wiphy);
9c84b797 1314}
500c064d 1315
6baff7f9 1316void ath_cleanup(struct ath_softc *sc)
39c3c2f2 1317{
5bb12791
LR		 1318 struct ath_hw *ah = sc->sc_ah;
1319 struct ath_common *common = ath9k_hw_common(ah);
1320
39c3c2f2
GJ		 1321 ath_detach(sc);
1322 free_irq(sc->irq, sc);
5bb12791 1323 ath_bus_cleanup(common);
c52f33d0 1324 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1325 ieee80211_free_hw(sc->hw);
1326}
1327
7fda1666
LR		 1328static void ath9k_uninit_hw(struct ath_softc *sc)
1329{
1330 struct ath_hw *ah = sc->sc_ah;
1331
1332 BUG_ON(!ah);
1333
1334 ath9k_exit_debug(ah);
1335 ath9k_hw_detach(ah);
1336 sc->sc_ah = NULL;
1337}
1338
6baff7f9 1339void ath_detach(struct ath_softc *sc)
f078f209 1340{
8feceb67 1341 struct ieee80211_hw *hw = sc->hw;
4d6b228d 1342 struct ath_hw *ah = sc->sc_ah;
9c84b797 1343 int i = 0;
f078f209 1344
3cbb5dd7
VN		 1345 ath9k_ps_wakeup(sc);
1346
4d6b228d 1347 dev_dbg(sc->dev, "Detach ATH hw\n");
f078f209 1348
35c95ab9 1349 ath_deinit_leds(sc);
e31f7b96 1350 wiphy_rfkill_stop_polling(sc->hw->wiphy);
35c95ab9 1351
c52f33d0
JM		 1352 for (i = 0; i < sc->num_sec_wiphy; i++) {
1353 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1354 if (aphy == NULL)
1355 continue;
1356 sc->sec_wiphy[i] = NULL;
1357 ieee80211_unregister_hw(aphy->hw);
1358 ieee80211_free_hw(aphy->hw);
1359 }
3fcdfb4b 1360 ieee80211_unregister_hw(hw);
8feceb67
VT		 1361 ath_rx_cleanup(sc);
1362 ath_tx_cleanup(sc);
f078f209 1363
9c84b797
S		 1364 tasklet_kill(&sc->intr_tq);
1365 tasklet_kill(&sc->bcon_tasklet);
f078f209 1366
9c84b797 1367 if (!(sc->sc_flags & SC_OP_INVALID))
9ecdef4b 1368 ath9k_setpower(sc, ATH9K_PM_AWAKE);
8feceb67 1369
9c84b797
S		 1370 /* cleanup tx queues */
1371 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1372 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1373 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797 1374
75d7839f 1375 if ((sc->btcoex.no_stomp_timer) &&
766ec4a9 1376 ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1377 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
1773912b 1378
7fda1666 1379 ath9k_uninit_hw(sc);
f078f209
LR		 1380}
1381
e3bb249b
BC		 1382static int ath9k_reg_notifier(struct wiphy *wiphy,
1383 struct regulatory_request *request)
1384{
1385 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1386 struct ath_wiphy *aphy = hw->priv;
1387 struct ath_softc *sc = aphy->sc;
27c51f1a 1388 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
e3bb249b
BC		 1389
1390 return ath_reg_notifier_apply(wiphy, request, reg);
1391}
1392
75d7839f
LR		 1393/*
1394 * Detects if there is any priority bt traffic
1395 */
1396static void ath_detect_bt_priority(struct ath_softc *sc)
1397{
1398 struct ath_btcoex *btcoex = &sc->btcoex;
1399 struct ath_hw *ah = sc->sc_ah;
1400
766ec4a9 1401 if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
75d7839f
LR		 1402 btcoex->bt_priority_cnt++;
1403
1404 if (time_after(jiffies, btcoex->bt_priority_time +
1405 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1406 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
c46917bb
LR		 1407 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
1408 "BT priority traffic detected");
75d7839f
LR		 1409 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1410 } else {
1411 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1412 }
1413
1414 btcoex->bt_priority_cnt = 0;
1415 btcoex->bt_priority_time = jiffies;
1416 }
1417}
1418
75d7839f
LR		 1419/*
1420 * Configures appropriate weight based on stomp type.
1421 */
269ad812
LR		 1422static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1423 enum ath_stomp_type stomp_type)
75d7839f 1424{
269ad812 1425 struct ath_hw *ah = sc->sc_ah;
75d7839f
LR		 1426
1427 switch (stomp_type) {
1428 case ATH_BTCOEX_STOMP_ALL:
269ad812
LR		 1429 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1430 AR_STOMP_ALL_WLAN_WGHT);
75d7839f
LR		 1431 break;
1432 case ATH_BTCOEX_STOMP_LOW:
269ad812
LR		 1433 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1434 AR_STOMP_LOW_WLAN_WGHT);
75d7839f
LR		 1435 break;
1436 case ATH_BTCOEX_STOMP_NONE:
269ad812
LR		 1437 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1438 AR_STOMP_NONE_WLAN_WGHT);
75d7839f
LR		 1439 break;
1440 default:
c46917bb
LR		 1441 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1442 "Invalid Stomptype\n");
75d7839f
LR		 1443 break;
1444 }
1445
269ad812 1446 ath9k_hw_btcoex_enable(ah);
75d7839f
LR		 1447}
1448
cd9bf689
LR		 1449static void ath9k_gen_timer_start(struct ath_hw *ah,
1450 struct ath_gen_timer *timer,
1451 u32 timer_next,
1452 u32 timer_period)
1453{
bc974f4a
LR		 1454 struct ath_common *common = ath9k_hw_common(ah);
1455 struct ath_softc *sc = (struct ath_softc *) common->priv;
1456
cd9bf689
LR		 1457 ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
1458
bc974f4a 1459 if ((sc->imask & ATH9K_INT_GENTIMER) == 0) {
cd9bf689 1460 ath9k_hw_set_interrupts(ah, 0);
bc974f4a
LR		 1461 sc->imask |= ATH9K_INT_GENTIMER;
1462 ath9k_hw_set_interrupts(ah, sc->imask);
cd9bf689
LR		 1463 }
1464}
1465
1466static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
1467{
bc974f4a
LR		 1468 struct ath_common *common = ath9k_hw_common(ah);
1469 struct ath_softc *sc = (struct ath_softc *) common->priv;
cd9bf689
LR		 1470 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1471
1472 ath9k_hw_gen_timer_stop(ah, timer);
1473
1474 /* if no timer is enabled, turn off interrupt mask */
1475 if (timer_table->timer_mask.val == 0) {
1476 ath9k_hw_set_interrupts(ah, 0);
bc974f4a
LR		 1477 sc->imask &= ~ATH9K_INT_GENTIMER;
1478 ath9k_hw_set_interrupts(ah, sc->imask);
cd9bf689
LR		 1479 }
1480}
1481
75d7839f
LR		 1482/*
1483 * This is the master bt coex timer which runs for every
1484 * 45ms, bt traffic will be given priority during 55% of this
1485 * period while wlan gets remaining 45%
1486 */
1487static void ath_btcoex_period_timer(unsigned long data)
1488{
1489 struct ath_softc *sc = (struct ath_softc *) data;
1490 struct ath_hw *ah = sc->sc_ah;
1491 struct ath_btcoex *btcoex = &sc->btcoex;
75d7839f
LR		 1492
1493 ath_detect_bt_priority(sc);
1494
1495 spin_lock_bh(&btcoex->btcoex_lock);
1496
269ad812 1497 ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
75d7839f
LR		 1498
1499 spin_unlock_bh(&btcoex->btcoex_lock);
1500
1501 if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1502 if (btcoex->hw_timer_enabled)
cd9bf689 1503 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
75d7839f 1504
cd9bf689
LR		 1505 ath9k_gen_timer_start(ah,
1506 btcoex->no_stomp_timer,
1507 (ath9k_hw_gettsf32(ah) +
1508 btcoex->btcoex_no_stomp),
1509 btcoex->btcoex_no_stomp * 10);
75d7839f
LR		 1510 btcoex->hw_timer_enabled = true;
1511 }
1512
1513 mod_timer(&btcoex->period_timer, jiffies +
1514 msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1515}
1516
1517/*
1518 * Generic tsf based hw timer which configures weight
1519 * registers to time slice between wlan and bt traffic
1520 */
1521static void ath_btcoex_no_stomp_timer(void *arg)
1522{
1523 struct ath_softc *sc = (struct ath_softc *)arg;
1524 struct ath_hw *ah = sc->sc_ah;
1525 struct ath_btcoex *btcoex = &sc->btcoex;
75d7839f 1526
c46917bb
LR		 1527 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1528 "no stomp timer running \n");
75d7839f
LR		 1529
1530 spin_lock_bh(&btcoex->btcoex_lock);
1531
e08a6ace 1532 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
269ad812 1533 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
e08a6ace 1534 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
269ad812 1535 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
75d7839f
LR		 1536
1537 spin_unlock_bh(&btcoex->btcoex_lock);
1538}
1539
1540static int ath_init_btcoex_timer(struct ath_softc *sc)
1541{
1542 struct ath_btcoex *btcoex = &sc->btcoex;
1543
1544 btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1545 btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1546 btcoex->btcoex_period / 100;
1547
1548 setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1549 (unsigned long) sc);
1550
1551 spin_lock_init(&btcoex->btcoex_lock);
1552
1553 btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1554 ath_btcoex_no_stomp_timer,
1555 ath_btcoex_no_stomp_timer,
1556 (void *) sc, AR_FIRST_NDP_TIMER);
1557
1558 if (!btcoex->no_stomp_timer)
1559 return -ENOMEM;
1560
1561 return 0;
1562}
1563
9e4bffd2
LR		 1564/*
1565 * Read and write, they both share the same lock. We do this to serialize
1566 * reads and writes on Atheros 802.11n PCI devices only. This is required
1567 * as the FIFO on these devices can only accept sanely 2 requests. After
1568 * that the device goes bananas. Serializing the reads/writes prevents this
1569 * from happening.
1570 */
1571
1572static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
1573{
1574 struct ath_hw *ah = (struct ath_hw *) hw_priv;
bc974f4a
LR		 1575 struct ath_common *common = ath9k_hw_common(ah);
1576 struct ath_softc *sc = (struct ath_softc *) common->priv;
9e4bffd2
LR		 1577
1578 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1579 unsigned long flags;
bc974f4a
LR		 1580 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1581 iowrite32(val, sc->mem + reg_offset);
1582 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
9e4bffd2 1583 } else
bc974f4a 1584 iowrite32(val, sc->mem + reg_offset);
9e4bffd2
LR		 1585}
1586
1587static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
1588{
1589 struct ath_hw *ah = (struct ath_hw *) hw_priv;
bc974f4a
LR		 1590 struct ath_common *common = ath9k_hw_common(ah);
1591 struct ath_softc *sc = (struct ath_softc *) common->priv;
9e4bffd2
LR		 1592 u32 val;
1593
1594 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1595 unsigned long flags;
bc974f4a
LR		 1596 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1597 val = ioread32(sc->mem + reg_offset);
1598 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
9e4bffd2 1599 } else
bc974f4a 1600 val = ioread32(sc->mem + reg_offset);
9e4bffd2
LR		 1601 return val;
1602}
1603
2ddb5c8b 1604static const struct ath_ops ath9k_common_ops = {
9e4bffd2
LR		 1605 .read = ath9k_ioread32,
1606 .write = ath9k_iowrite32,
1607};
1608
1e40bcfa
LR		 1609/*
1610 * Initialize and fill ath_softc, ath_sofct is the
1611 * "Software Carrier" struct. Historically it has existed
1612 * to allow the separation between hardware specific
1613 * variables (now in ath_hw) and driver specific variables.
1614 */
5bb12791
LR		 1615static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
1616 const struct ath_bus_ops *bus_ops)
ff37e337 1617{
cbe61d8a 1618 struct ath_hw *ah = NULL;
1510718d 1619 struct ath_common *common;
4f3acf81 1620 int r = 0, i;
ff37e337 1621 int csz = 0;
75d7839f 1622 int qnum;
ff37e337
S		 1623
1624 /* XXX: hardware will not be ready until ath_open() being called */
1625 sc->sc_flags |= SC_OP_INVALID;
88b126af 1626
c52f33d0 1627 spin_lock_init(&sc->wiphy_lock);
ff37e337 1628 spin_lock_init(&sc->sc_resetlock);
6158425b 1629 spin_lock_init(&sc->sc_serial_rw);
e5f0921a 1630 spin_lock_init(&sc->ani_lock);
04717ccd 1631 spin_lock_init(&sc->sc_pm_lock);
aa33de09 1632 mutex_init(&sc->mutex);
ff37e337 1633 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1634 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1635 (unsigned long)sc);
1636
4f3acf81 1637 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
211f5859
LR		 1638 if (!ah)
1639 return -ENOMEM;
4f3acf81 1640
8df5d1b7 1641 ah->hw_version.devid = devid;
aeac355d 1642 ah->hw_version.subsysid = subsysid;
e1e2f93f 1643 sc->sc_ah = ah;
4f3acf81 1644
27c51f1a 1645 common = ath9k_hw_common(ah);
9e4bffd2 1646 common->ops = &ath9k_common_ops;
5bb12791 1647 common->bus_ops = bus_ops;
13b81559 1648 common->ah = ah;
b002a4a9 1649 common->hw = sc->hw;
bc974f4a 1650 common->priv = sc;
faa27fae 1651 common->debug_mask = ath9k_debug;
27c51f1a
LR		 1652
1653 /*
1654 * Cache line size is used to size and align various
1655 * structures used to communicate with the hardware.
1656 */
5bb12791 1657 ath_read_cachesize(common, &csz);
27c51f1a
LR		 1658 /* XXX assert csz is non-zero */
1659 common->cachelsz = csz << 2; /* convert to bytes */
1660
f637cfd6 1661 r = ath9k_hw_init(ah);
4f3acf81 1662 if (r) {
c46917bb
LR		 1663 ath_print(common, ATH_DBG_FATAL,
1664 "Unable to initialize hardware; "
1665 "initialization status: %d\n", r);
211f5859
LR		 1666 goto bad_free_hw;
1667 }
1668
1669 if (ath9k_init_debug(ah) < 0) {
1670 ath_print(common, ATH_DBG_FATAL,
1671 "Unable to create debugfs files\n");
1672 goto bad_free_hw;
ff37e337 1673 }
ff37e337
S		 1674
1675 /* Get the hardware key cache size. */
2660b81a 1676 sc->keymax = ah->caps.keycache_size;
17d7904d 1677 if (sc->keymax > ATH_KEYMAX) {
c46917bb
LR		 1678 ath_print(common, ATH_DBG_ANY,
1679 "Warning, using only %u entries in %u key cache\n",
1680 ATH_KEYMAX, sc->keymax);
17d7904d 1681 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1682 }
1683
1684 /*
1685 * Reset the key cache since some parts do not
1686 * reset the contents on initial power up.
1687 */
17d7904d 1688 for (i = 0; i < sc->keymax; i++)
ff37e337 1689 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1690
ff37e337 1691 /* default to MONITOR mode */
2660b81a 1692 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1693
ff37e337
S		 1694 /* Setup rate tables */
1695
1696 ath_rate_attach(sc);
1697 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1698 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1699
1700 /*
1701 * Allocate hardware transmit queues: one queue for
1702 * beacon frames and one data queue for each QoS
1703 * priority. Note that the hal handles reseting
1704 * these queues at the needed time.
1705 */
b77f483f
S		 1706 sc->beacon.beaconq = ath_beaconq_setup(ah);
1707 if (sc->beacon.beaconq == -1) {
c46917bb
LR		 1708 ath_print(common, ATH_DBG_FATAL,
1709 "Unable to setup a beacon xmit queue\n");
4f3acf81 1710 r = -EIO;
ff37e337
S		 1711 goto bad2;
1712 }
b77f483f
S		 1713 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1714 if (sc->beacon.cabq == NULL) {
c46917bb
LR		 1715 ath_print(common, ATH_DBG_FATAL,
1716 "Unable to setup CAB xmit queue\n");
4f3acf81 1717 r = -EIO;
ff37e337
S		 1718 goto bad2;
1719 }
1720
17d7904d 1721 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1722 ath_cabq_update(sc);
1723
b77f483f
S		 1724 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1725 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1726
1727 /* Setup data queues */
1728 /* NB: ensure BK queue is the lowest priority h/w queue */
1729 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
c46917bb
LR		 1730 ath_print(common, ATH_DBG_FATAL,
1731 "Unable to setup xmit queue for BK traffic\n");
4f3acf81 1732 r = -EIO;
ff37e337
S		 1733 goto bad2;
1734 }
1735
1736 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
c46917bb
LR		 1737 ath_print(common, ATH_DBG_FATAL,
1738 "Unable to setup xmit queue for BE traffic\n");
4f3acf81 1739 r = -EIO;
ff37e337
S		 1740 goto bad2;
1741 }
1742 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
c46917bb
LR		 1743 ath_print(common, ATH_DBG_FATAL,
1744 "Unable to setup xmit queue for VI traffic\n");
4f3acf81 1745 r = -EIO;
ff37e337
S		 1746 goto bad2;
1747 }
1748 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
c46917bb
LR		 1749 ath_print(common, ATH_DBG_FATAL,
1750 "Unable to setup xmit queue for VO traffic\n");
4f3acf81 1751 r = -EIO;
ff37e337
S		 1752 goto bad2;
1753 }
1754
1755 /* Initializes the noise floor to a reasonable default value.
1756 * Later on this will be updated during ANI processing. */
1757
17d7904d
S		 1758 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1759 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1760
1761 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1762 ATH9K_CIPHER_TKIP, NULL)) {
1763 /*
1764 * Whether we should enable h/w TKIP MIC.
1765 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1766 * report WMM capable, so it's always safe to turn on
1767 * TKIP MIC in this case.
1768 */
1769 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1770 0, 1, NULL);
1771 }
1772
1773 /*
1774 * Check whether the separate key cache entries
1775 * are required to handle both tx+rx MIC keys.
1776 * With split mic keys the number of stations is limited
1777 * to 27 otherwise 59.
1778 */
1779 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1780 ATH9K_CIPHER_TKIP, NULL)
1781 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1782 ATH9K_CIPHER_MIC, NULL)
1783 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1784 0, NULL))
17d7904d 1785 sc->splitmic = 1;
ff37e337
S		 1786
1787 /* turn on mcast key search if possible */
1788 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1789 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1790 1, NULL);
1791
17d7904d 1792 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1793
1794 /* 11n Capabilities */
2660b81a 1795 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1796 sc->sc_flags |= SC_OP_TXAGGR;
1797 sc->sc_flags |= SC_OP_RXAGGR;
1798 }
1799
43c27613
LR		 1800 common->tx_chainmask = ah->caps.tx_chainmask;
1801 common->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1802
1803 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1804 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1805
8ca21f01 1806 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1510718d 1807 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1808
b77f483f 1809 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1810
1811 /* initialize beacon slots */
c52f33d0 1812 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1813 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1814 sc->beacon.bslot_aphy[i] = NULL;
1815 }
ff37e337 1816
ff37e337
S		 1817 /* setup channels and rates */
1818
5f8e077c 1819 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1820 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1821 sc->rates[IEEE80211_BAND_2GHZ];
1822 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1823 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1824 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1825
2660b81a 1826 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1827 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1828 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1829 sc->rates[IEEE80211_BAND_5GHZ];
1830 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1831 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1832 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1833 }
1834
766ec4a9 1835 switch (ah->btcoex_hw.scheme) {
75d7839f
LR		 1836 case ATH_BTCOEX_CFG_NONE:
1837 break;
1838 case ATH_BTCOEX_CFG_2WIRE:
1839 ath9k_hw_btcoex_init_2wire(ah);
1840 break;
1841 case ATH_BTCOEX_CFG_3WIRE:
1842 ath9k_hw_btcoex_init_3wire(ah);
1843 r = ath_init_btcoex_timer(sc);
1773912b
VT		 1844 if (r)
1845 goto bad2;
75d7839f 1846 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
766ec4a9 1847 ath9k_hw_init_btcoex_hw(ah, qnum);
e08a6ace 1848 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
75d7839f
LR		 1849 break;
1850 default:
1851 WARN_ON(1);
1852 break;
1773912b 1853 }
c97c92d9 1854
ff37e337
S		 1855 return 0;
1856bad2:
1857 /* cleanup tx queues */
1858 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1859 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1860 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
211f5859 1861
211f5859 1862bad_free_hw:
7fda1666 1863 ath9k_uninit_hw(sc);
4f3acf81 1864 return r;
ff37e337
S		 1865}
1866
c52f33d0 1867void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1868{
9c84b797
S		 1869 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1870 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1871 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1872 IEEE80211_HW_AMPDU_AGGREGATION |
1873 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1874 IEEE80211_HW_PS_NULLFUNC_STACK |
1875 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1876
b3bd89ce 1877 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1878 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1879
9c84b797
S		 1880 hw->wiphy->interface_modes =
1881 BIT(NL80211_IFTYPE_AP) |
1882 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1883 BIT(NL80211_IFTYPE_ADHOC) |
1884 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1885
8feceb67 1886 hw->queues = 4;
e63835b0 1887 hw->max_rates = 4;
171387ef 1888 hw->channel_change_time = 5000;
465ca84d 1889 hw->max_listen_interval = 10;
dd190183
LR		 1890 /* Hardware supports 10 but we use 4 */
1891 hw->max_rate_tries = 4;
528f0c6b 1892 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1893 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1894
8feceb67 1895 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1896
c52f33d0
JM		 1897 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1898 &sc->sbands[IEEE80211_BAND_2GHZ];
1899 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1900 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1901 &sc->sbands[IEEE80211_BAND_5GHZ];
1902}
1903
1e40bcfa 1904/* Device driver core initialization */
5bb12791
LR		 1905int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
1906 const struct ath_bus_ops *bus_ops)
c52f33d0
JM		 1907{
1908 struct ieee80211_hw *hw = sc->hw;
1510718d 1909 struct ath_common *common;
4d6b228d 1910 struct ath_hw *ah;
c52f33d0 1911 int error = 0, i;
3a702e49 1912 struct ath_regulatory *reg;
c52f33d0 1913
4d6b228d 1914 dev_dbg(sc->dev, "Attach ATH hw\n");
c52f33d0 1915
5bb12791 1916 error = ath_init_softc(devid, sc, subsysid, bus_ops);
c52f33d0
JM		 1917 if (error != 0)
1918 return error;
1919
4d6b228d 1920 ah = sc->sc_ah;
1510718d 1921 common = ath9k_hw_common(ah);
4d6b228d 1922
c52f33d0
JM		 1923 /* get mac address from hardware and set in mac80211 */
1924
1510718d 1925 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
c52f33d0
JM		 1926
1927 ath_set_hw_capab(sc, hw);
1928
1510718d 1929 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
c26c2e57
LR		 1930 ath9k_reg_notifier);
1931 if (error)
1932 return error;
1933
1510718d 1934 reg = &common->regulatory;
c26c2e57 1935
4d6b228d 1936 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1937 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
4d6b228d 1938 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
eb2599ca 1939 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1940 }
1941
db93e7b5
SB		 1942 /* initialize tx/rx engine */
1943 error = ath_tx_init(sc, ATH_TXBUF);
1944 if (error != 0)
40b130a9 1945 goto error_attach;
8feceb67 1946
db93e7b5
SB		 1947 error = ath_rx_init(sc, ATH_RXBUF);
1948 if (error != 0)
40b130a9 1949 goto error_attach;
8feceb67 1950
0e2dedf9 1951 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1952 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1953 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1954
db93e7b5 1955 error = ieee80211_register_hw(hw);
8feceb67 1956
3a702e49 1957 if (!ath_is_world_regd(reg)) {
c02cf373 1958 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1959 if (error)
1960 goto error_attach;
1961 }
5f8e077c 1962
db93e7b5
SB		 1963 /* Initialize LED control */
1964 ath_init_leds(sc);
8feceb67 1965
3b319aae 1966 ath_start_rfkill_poll(sc);
5f8e077c 1967
8feceb67 1968 return 0;
40b130a9
VT		 1969
1970error_attach:
1971 /* cleanup tx queues */
1972 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1973 if (ATH_TXQ_SETUP(sc, i))
1974 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1975
7fda1666 1976 ath9k_uninit_hw(sc);
40b130a9 1977
8feceb67 1978 return error;
f078f209
LR		 1979}
1980
ff37e337
S		 1981int ath_reset(struct ath_softc *sc, bool retry_tx)
1982{
cbe61d8a 1983 struct ath_hw *ah = sc->sc_ah;
c46917bb 1984 struct ath_common *common = ath9k_hw_common(ah);
030bb495 1985 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1986 int r;
ff37e337
S		 1987
1988 ath9k_hw_set_interrupts(ah, 0);
043a0405 1989 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1990 ath_stoprecv(sc);
1991 ath_flushrecv(sc);
1992
1993 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1994 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1995 if (r)
c46917bb
LR		 1996 ath_print(common, ATH_DBG_FATAL,
1997 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 1998 spin_unlock_bh(&sc->sc_resetlock);
1999
2000 if (ath_startrecv(sc) != 0)
c46917bb
LR		 2001 ath_print(common, ATH_DBG_FATAL,
2002 "Unable to start recv logic\n");
ff37e337
S		 2003
2004 /*
2005 * We may be doing a reset in response to a request
2006 * that changes the channel so update any state that
2007 * might change as a result.
2008 */
ce111bad 2009 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2010
2011 ath_update_txpow(sc);
2012
2013 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 2014 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 2015
17d7904d 2016 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 2017
2018 if (retry_tx) {
2019 int i;
2020 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2021 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 2022 spin_lock_bh(&sc->tx.txq[i].axq_lock);
2023 ath_txq_schedule(sc, &sc->tx.txq[i]);
2024 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 2025 }
2026 }
2027 }
2028
ae8d2858 2029 return r;
ff37e337
S		 2030}
2031
2032/*
2033 * This function will allocate both the DMA descriptor structure, and the
2034 * buffers it contains. These are used to contain the descriptors used
2035 * by the system.
2036*/
2037int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
2038 struct list_head *head, const char *name,
2039 int nbuf, int ndesc)
2040{
2041#define DS2PHYS(_dd, _ds) \
2042 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2043#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
2044#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
c46917bb 2045 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
ff37e337
S		 2046 struct ath_desc *ds;
2047 struct ath_buf *bf;
2048 int i, bsize, error;
2049
c46917bb
LR		 2050 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
2051 name, nbuf, ndesc);
ff37e337 2052
b03a9db9 2053 INIT_LIST_HEAD(head);
ff37e337
S		 2054 /* ath_desc must be a multiple of DWORDs */
2055 if ((sizeof(struct ath_desc) % 4) != 0) {
c46917bb
LR		 2056 ath_print(common, ATH_DBG_FATAL,
2057 "ath_desc not DWORD aligned\n");
9680e8a3 2058 BUG_ON((sizeof(struct ath_desc) % 4) != 0);
ff37e337
S		 2059 error = -ENOMEM;
2060 goto fail;
2061 }
2062
ff37e337
S		 2063 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2064
2065 /*
2066 * Need additional DMA memory because we can't use
2067 * descriptors that cross the 4K page boundary. Assume
2068 * one skipped descriptor per 4K page.
2069 */
2660b81a 2070 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 2071 u32 ndesc_skipped =
2072 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
2073 u32 dma_len;
2074
2075 while (ndesc_skipped) {
2076 dma_len = ndesc_skipped * sizeof(struct ath_desc);
2077 dd->dd_desc_len += dma_len;
2078
2079 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
2080 };
2081 }
2082
2083 /* allocate descriptors */
7da3c55c 2084 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 2085 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 2086 if (dd->dd_desc == NULL) {
2087 error = -ENOMEM;
2088 goto fail;
2089 }
2090 ds = dd->dd_desc;
c46917bb
LR		 2091 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
2092 name, ds, (u32) dd->dd_desc_len,
2093 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
ff37e337
S		 2094
2095 /* allocate buffers */
2096 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 2097 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 2098 if (bf == NULL) {
2099 error = -ENOMEM;
2100 goto fail2;
2101 }
ff37e337
S		 2102 dd->dd_bufptr = bf;
2103
ff37e337
S		 2104 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2105 bf->bf_desc = ds;
2106 bf->bf_daddr = DS2PHYS(dd, ds);
2107
2660b81a 2108 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 2109 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2110 /*
2111 * Skip descriptor addresses which can cause 4KB
2112 * boundary crossing (addr + length) with a 32 dword
2113 * descriptor fetch.
2114 */
2115 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
9680e8a3 2116 BUG_ON((caddr_t) bf->bf_desc >=
ff37e337
S		 2117 ((caddr_t) dd->dd_desc +
2118 dd->dd_desc_len));
2119
2120 ds += ndesc;
2121 bf->bf_desc = ds;
2122 bf->bf_daddr = DS2PHYS(dd, ds);
2123 }
2124 }
2125 list_add_tail(&bf->list, head);
2126 }
2127 return 0;
2128fail2:
7da3c55c
GJ		 2129 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2130 dd->dd_desc_paddr);
ff37e337
S		 2131fail:
2132 memset(dd, 0, sizeof(*dd));
2133 return error;
2134#undef ATH_DESC_4KB_BOUND_CHECK
2135#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
2136#undef DS2PHYS
2137}
2138
2139void ath_descdma_cleanup(struct ath_softc *sc,
2140 struct ath_descdma *dd,
2141 struct list_head *head)
2142{
7da3c55c
GJ		 2143 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2144 dd->dd_desc_paddr);
ff37e337
S		 2145
2146 INIT_LIST_HEAD(head);
2147 kfree(dd->dd_bufptr);
2148 memset(dd, 0, sizeof(*dd));
2149}
2150
2151int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
2152{
2153 int qnum;
2154
2155 switch (queue) {
2156 case 0:
b77f483f 2157 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 2158 break;
2159 case 1:
b77f483f 2160 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 2161 break;
2162 case 2:
b77f483f 2163 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 2164 break;
2165 case 3:
b77f483f 2166 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 2167 break;
2168 default:
b77f483f 2169 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 2170 break;
2171 }
2172
2173 return qnum;
2174}
2175
2176int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2177{
2178 int qnum;
2179
2180 switch (queue) {
2181 case ATH9K_WME_AC_VO:
2182 qnum = 0;
2183 break;
2184 case ATH9K_WME_AC_VI:
2185 qnum = 1;
2186 break;
2187 case ATH9K_WME_AC_BE:
2188 qnum = 2;
2189 break;
2190 case ATH9K_WME_AC_BK:
2191 qnum = 3;
2192 break;
2193 default:
2194 qnum = -1;
2195 break;
2196 }
2197
2198 return qnum;
2199}
2200
5f8e077c
LR		 2201/* XXX: Remove me once we don't depend on ath9k_channel for all
2202 * this redundant data */
0e2dedf9
JM		 2203void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2204 struct ath9k_channel *ichan)
5f8e077c 2205{
5f8e077c
LR		 2206 struct ieee80211_channel *chan = hw->conf.channel;
2207 struct ieee80211_conf *conf = &hw->conf;
2208
2209 ichan->channel = chan->center_freq;
2210 ichan->chan = chan;
2211
2212 if (chan->band == IEEE80211_BAND_2GHZ) {
2213 ichan->chanmode = CHANNEL_G;
8813262e 2214 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
5f8e077c
LR		 2215 } else {
2216 ichan->chanmode = CHANNEL_A;
2217 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2218 }
2219
25c56eec 2220 if (conf_is_ht(conf))
5f8e077c
LR		 2221 ichan->chanmode = ath_get_extchanmode(sc, chan,
2222 conf->channel_type);
5f8e077c
LR		 2223}
2224
ff37e337
S		 2225/**********************/
2226/* mac80211 callbacks */
2227/**********************/
2228
75d7839f
LR		 2229/*
2230 * (Re)start btcoex timers
2231 */
2232static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2233{
2234 struct ath_btcoex *btcoex = &sc->btcoex;
2235 struct ath_hw *ah = sc->sc_ah;
2236
c46917bb
LR		 2237 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
2238 "Starting btcoex timers");
75d7839f
LR		 2239
2240 /* make sure duty cycle timer is also stopped when resuming */
2241 if (btcoex->hw_timer_enabled)
cd9bf689 2242 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
75d7839f
LR		 2243
2244 btcoex->bt_priority_cnt = 0;
2245 btcoex->bt_priority_time = jiffies;
2246 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2247
2248 mod_timer(&btcoex->period_timer, jiffies);
2249}
2250
8feceb67 2251static int ath9k_start(struct ieee80211_hw *hw)
f078f209 2252{
bce048d7
JM		 2253 struct ath_wiphy *aphy = hw->priv;
2254 struct ath_softc *sc = aphy->sc;
af03abec 2255 struct ath_hw *ah = sc->sc_ah;
c46917bb 2256 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 2257 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 2258 struct ath9k_channel *init_channel;
82880a7c 2259 int r;
f078f209 2260
c46917bb
LR		 2261 ath_print(common, ATH_DBG_CONFIG,
2262 "Starting driver with initial channel: %d MHz\n",
2263 curchan->center_freq);
f078f209 2264
141b38b6
S		 2265 mutex_lock(&sc->mutex);
2266
9580a222
JM		 2267 if (ath9k_wiphy_started(sc)) {
2268 if (sc->chan_idx == curchan->hw_value) {
2269 /*
2270 * Already on the operational channel, the new wiphy
2271 * can be marked active.
2272 */
2273 aphy->state = ATH_WIPHY_ACTIVE;
2274 ieee80211_wake_queues(hw);
2275 } else {
2276 /*
2277 * Another wiphy is on another channel, start the new
2278 * wiphy in paused state.
2279 */
2280 aphy->state = ATH_WIPHY_PAUSED;
2281 ieee80211_stop_queues(hw);
2282 }
2283 mutex_unlock(&sc->mutex);
2284 return 0;
2285 }
2286 aphy->state = ATH_WIPHY_ACTIVE;
2287
8feceb67 2288 /* setup initial channel */
f078f209 2289
82880a7c 2290 sc->chan_idx = curchan->hw_value;
f078f209 2291
82880a7c 2292 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S		 2293
2294 /* Reset SERDES registers */
af03abec 2295 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S		 2296
2297 /*
2298 * The basic interface to setting the hardware in a good
2299 * state is ``reset''. On return the hardware is known to
2300 * be powered up and with interrupts disabled. This must
2301 * be followed by initialization of the appropriate bits
2302 * and then setup of the interrupt mask.
2303 */
2304 spin_lock_bh(&sc->sc_resetlock);
af03abec 2305 r = ath9k_hw_reset(ah, init_channel, false);
ae8d2858 2306 if (r) {
c46917bb
LR		 2307 ath_print(common, ATH_DBG_FATAL,
2308 "Unable to reset hardware; reset status %d "
2309 "(freq %u MHz)\n", r,
2310 curchan->center_freq);
ff37e337 2311 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 2312 goto mutex_unlock;
ff37e337
S		 2313 }
2314 spin_unlock_bh(&sc->sc_resetlock);
2315
2316 /*
2317 * This is needed only to setup initial state
2318 * but it's best done after a reset.
2319 */
2320 ath_update_txpow(sc);
8feceb67 2321
ff37e337
S		 2322 /*
2323 * Setup the hardware after reset:
2324 * The receive engine is set going.
2325 * Frame transmit is handled entirely
2326 * in the frame output path; there's nothing to do
2327 * here except setup the interrupt mask.
2328 */
2329 if (ath_startrecv(sc) != 0) {
c46917bb
LR		 2330 ath_print(common, ATH_DBG_FATAL,
2331 "Unable to start recv logic\n");
141b38b6
S		 2332 r = -EIO;
2333 goto mutex_unlock;
f078f209 2334 }
8feceb67 2335
ff37e337 2336 /* Setup our intr mask. */
17d7904d 2337 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 2338 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2339 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2340
af03abec 2341 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2342 sc->imask |= ATH9K_INT_GTT;
ff37e337 2343
af03abec 2344 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2345 sc->imask |= ATH9K_INT_CST;
ff37e337 2346
ce111bad 2347 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2348
2349 sc->sc_flags &= ~SC_OP_INVALID;
2350
2351 /* Disable BMISS interrupt when we're not associated */
17d7904d 2352 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
af03abec 2353 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337 2354
bce048d7 2355 ieee80211_wake_queues(hw);
ff37e337 2356
42935eca 2357 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 2358
766ec4a9
LR		 2359 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2360 !ah->btcoex_hw.enabled) {
5e197292
LR		 2361 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2362 AR_STOMP_LOW_WLAN_WGHT);
af03abec 2363 ath9k_hw_btcoex_enable(ah);
f985ad12 2364
5bb12791
LR		 2365 if (common->bus_ops->bt_coex_prep)
2366 common->bus_ops->bt_coex_prep(common);
766ec4a9 2367 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 2368 ath9k_btcoex_timer_resume(sc);
1773912b
VT		 2369 }
2370
141b38b6
S		 2371mutex_unlock:
2372 mutex_unlock(&sc->mutex);
2373
ae8d2858 2374 return r;
f078f209
LR		 2375}
2376
8feceb67
VT		 2377static int ath9k_tx(struct ieee80211_hw *hw,
2378 struct sk_buff *skb)
f078f209 2379{
528f0c6b 2380 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 2381 struct ath_wiphy *aphy = hw->priv;
2382 struct ath_softc *sc = aphy->sc;
c46917bb 2383 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 2384 struct ath_tx_control txctl;
8feceb67 2385 int hdrlen, padsize;
528f0c6b 2386
8089cc47 2387 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
c46917bb
LR		 2388 ath_print(common, ATH_DBG_XMIT,
2389 "ath9k: %s: TX in unexpected wiphy state "
2390 "%d\n", wiphy_name(hw->wiphy), aphy->state);
ee166a0e
JM		 2391 goto exit;
2392 }
2393
96148326 2394 if (sc->ps_enabled) {
dc8c4585
JM		 2395 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2396 /*
2397 * mac80211 does not set PM field for normal data frames, so we
2398 * need to update that based on the current PS mode.
2399 */
2400 if (ieee80211_is_data(hdr->frame_control) &&
2401 !ieee80211_is_nullfunc(hdr->frame_control) &&
2402 !ieee80211_has_pm(hdr->frame_control)) {
c46917bb
LR		 2403 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
2404 "while in PS mode\n");
dc8c4585
JM		 2405 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2406 }
2407 }
2408
9a23f9ca
JM		 2409 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2410 /*
2411 * We are using PS-Poll and mac80211 can request TX while in
2412 * power save mode. Need to wake up hardware for the TX to be
2413 * completed and if needed, also for RX of buffered frames.
2414 */
2415 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2416 ath9k_ps_wakeup(sc);
2417 ath9k_hw_setrxabort(sc->sc_ah, 0);
2418 if (ieee80211_is_pspoll(hdr->frame_control)) {
c46917bb
LR		 2419 ath_print(common, ATH_DBG_PS,
2420 "Sending PS-Poll to pick a buffered frame\n");
9a23f9ca
JM		 2421 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2422 } else {
c46917bb
LR		 2423 ath_print(common, ATH_DBG_PS,
2424 "Wake up to complete TX\n");
9a23f9ca
JM		 2425 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2426 }
2427 /*
2428 * The actual restore operation will happen only after
2429 * the sc_flags bit is cleared. We are just dropping
2430 * the ps_usecount here.
2431 */
2432 ath9k_ps_restore(sc);
2433 }
2434
528f0c6b 2435 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2436
8feceb67
VT		 2437 /*
2438 * As a temporary workaround, assign seq# here; this will likely need
2439 * to be cleaned up to work better with Beacon transmission and virtual
2440 * BSSes.
2441 */
2442 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2443 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2444 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2445 sc->tx.seq_no += 0x10;
8feceb67 2446 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2447 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2448 }
f078f209 2449
8feceb67
VT		 2450 /* Add the padding after the header if this is not already done */
2451 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2452 if (hdrlen & 3) {
2453 padsize = hdrlen % 4;
2454 if (skb_headroom(skb) < padsize)
2455 return -1;
2456 skb_push(skb, padsize);
2457 memmove(skb->data, skb->data + padsize, hdrlen);
2458 }
2459
528f0c6b
S		 2460 /* Check if a tx queue is available */
2461
2462 txctl.txq = ath_test_get_txq(sc, skb);
2463 if (!txctl.txq)
2464 goto exit;
2465
c46917bb 2466 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2467
c52f33d0 2468 if (ath_tx_start(hw, skb, &txctl) != 0) {
c46917bb 2469 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2470 goto exit;
8feceb67
VT		 2471 }
2472
528f0c6b
S		 2473 return 0;
2474exit:
2475 dev_kfree_skb_any(skb);
8feceb67 2476 return 0;
f078f209
LR		 2477}
2478
75d7839f
LR		 2479/*
2480 * Pause btcoex timer and bt duty cycle timer
2481 */
2482static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2483{
2484 struct ath_btcoex *btcoex = &sc->btcoex;
2485 struct ath_hw *ah = sc->sc_ah;
2486
2487 del_timer_sync(&btcoex->period_timer);
2488
2489 if (btcoex->hw_timer_enabled)
cd9bf689 2490 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
75d7839f
LR		 2491
2492 btcoex->hw_timer_enabled = false;
2493}
2494
8feceb67 2495static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2496{
bce048d7
JM		 2497 struct ath_wiphy *aphy = hw->priv;
2498 struct ath_softc *sc = aphy->sc;
af03abec 2499 struct ath_hw *ah = sc->sc_ah;
c46917bb 2500 struct ath_common *common = ath9k_hw_common(ah);
f078f209 2501
4c483817
S		 2502 mutex_lock(&sc->mutex);
2503
9580a222
JM		 2504 aphy->state = ATH_WIPHY_INACTIVE;
2505
c94dbff7
LR		 2506 cancel_delayed_work_sync(&sc->ath_led_blink_work);
2507 cancel_delayed_work_sync(&sc->tx_complete_work);
2508
2509 if (!sc->num_sec_wiphy) {
2510 cancel_delayed_work_sync(&sc->wiphy_work);
2511 cancel_work_sync(&sc->chan_work);
2512 }
2513
9c84b797 2514 if (sc->sc_flags & SC_OP_INVALID) {
c46917bb 2515 ath_print(common, ATH_DBG_ANY, "Device not present\n");
4c483817 2516 mutex_unlock(&sc->mutex);
9c84b797
S		 2517 return;
2518 }
8feceb67 2519
9580a222
JM		 2520 if (ath9k_wiphy_started(sc)) {
2521 mutex_unlock(&sc->mutex);
2522 return; /* another wiphy still in use */
2523 }
2524
766ec4a9 2525 if (ah->btcoex_hw.enabled) {
af03abec 2526 ath9k_hw_btcoex_disable(ah);
766ec4a9 2527 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 2528 ath9k_btcoex_timer_pause(sc);
1773912b
VT		 2529 }
2530
ff37e337
S		 2531 /* make sure h/w will not generate any interrupt
2532 * before setting the invalid flag. */
af03abec 2533 ath9k_hw_set_interrupts(ah, 0);
ff37e337
S		 2534
2535 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2536 ath_drain_all_txq(sc, false);
ff37e337 2537 ath_stoprecv(sc);
af03abec 2538 ath9k_hw_phy_disable(ah);
ff37e337 2539 } else
b77f483f 2540 sc->rx.rxlink = NULL;
ff37e337 2541
ff37e337 2542 /* disable HAL and put h/w to sleep */
af03abec
LR		 2543 ath9k_hw_disable(ah);
2544 ath9k_hw_configpcipowersave(ah, 1, 1);
9ecdef4b 2545 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
ff37e337
S		 2546
2547 sc->sc_flags |= SC_OP_INVALID;
500c064d 2548
141b38b6
S		 2549 mutex_unlock(&sc->mutex);
2550
c46917bb 2551 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2552}
2553
8feceb67
VT		 2554static int ath9k_add_interface(struct ieee80211_hw *hw,
2555 struct ieee80211_if_init_conf *conf)
f078f209 2556{
bce048d7
JM		 2557 struct ath_wiphy *aphy = hw->priv;
2558 struct ath_softc *sc = aphy->sc;
c46917bb 2559 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
17d7904d 2560 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2561 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2562 int ret = 0;
8feceb67 2563
141b38b6
S		 2564 mutex_lock(&sc->mutex);
2565
8ca21f01
JM		 2566 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2567 sc->nvifs > 0) {
2568 ret = -ENOBUFS;
2569 goto out;
2570 }
2571
8feceb67 2572 switch (conf->type) {
05c914fe 2573 case NL80211_IFTYPE_STATION:
d97809db 2574 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2575 break;
05c914fe 2576 case NL80211_IFTYPE_ADHOC:
05c914fe 2577 case NL80211_IFTYPE_AP:
9cb5412b 2578 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2579 if (sc->nbcnvifs >= ATH_BCBUF) {
2580 ret = -ENOBUFS;
2581 goto out;
2582 }
9cb5412b 2583 ic_opmode = conf->type;
f078f209
LR		 2584 break;
2585 default:
c46917bb 2586 ath_print(common, ATH_DBG_FATAL,
04bd4638 2587 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2588 ret = -EOPNOTSUPP;
2589 goto out;
f078f209
LR		 2590 }
2591
c46917bb
LR		 2592 ath_print(common, ATH_DBG_CONFIG,
2593 "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2594
17d7904d 2595 /* Set the VIF opmode */
5640b08e
S		 2596 avp->av_opmode = ic_opmode;
2597 avp->av_bslot = -1;
2598
2c3db3d5 2599 sc->nvifs++;
8ca21f01
JM		 2600
2601 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2602 ath9k_set_bssid_mask(hw);
2603
2c3db3d5
JM		 2604 if (sc->nvifs > 1)
2605 goto out; /* skip global settings for secondary vif */
2606
b238e90e 2607 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2608 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2609 sc->sc_flags |= SC_OP_TSF_RESET;
2610 }
5640b08e 2611
5640b08e 2612 /* Set the device opmode */
2660b81a 2613 sc->sc_ah->opmode = ic_opmode;
5640b08e 2614
4e30ffa2
VN		 2615 /*
2616 * Enable MIB interrupts when there are hardware phy counters.
2617 * Note we only do this (at the moment) for station mode.
2618 */
4af9cf4f 2619 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2620 (conf->type == NL80211_IFTYPE_ADHOC) ||
2621 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
1aa8e847 2622 sc->imask |= ATH9K_INT_MIB;
4af9cf4f
S		 2623 sc->imask |= ATH9K_INT_TSFOOR;
2624 }
2625
17d7904d 2626 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2627
f38faa31
SB		 2628 if (conf->type == NL80211_IFTYPE_AP ||
2629 conf->type == NL80211_IFTYPE_ADHOC ||
2630 conf->type == NL80211_IFTYPE_MONITOR)
415f738e 2631 ath_start_ani(sc);
6f255425 2632
2c3db3d5 2633out:
141b38b6 2634 mutex_unlock(&sc->mutex);
2c3db3d5 2635 return ret;
f078f209
LR		 2636}
2637
8feceb67
VT		 2638static void ath9k_remove_interface(struct ieee80211_hw *hw,
2639 struct ieee80211_if_init_conf *conf)
f078f209 2640{
bce048d7
JM		 2641 struct ath_wiphy *aphy = hw->priv;
2642 struct ath_softc *sc = aphy->sc;
c46917bb 2643 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
17d7904d 2644 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2645 int i;
f078f209 2646
c46917bb 2647 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2648
141b38b6
S		 2649 mutex_lock(&sc->mutex);
2650
6f255425 2651 /* Stop ANI */
17d7904d 2652 del_timer_sync(&sc->ani.timer);
580f0b8a 2653
8feceb67 2654 /* Reclaim beacon resources */
9cb5412b
PE		 2655 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2656 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2657 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2658 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2659 ath_beacon_return(sc, avp);
580f0b8a 2660 }
f078f209 2661
8feceb67 2662 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2663
2c3db3d5
JM		 2664 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2665 if (sc->beacon.bslot[i] == conf->vif) {
2666 printk(KERN_DEBUG "%s: vif had allocated beacon "
2667 "slot\n", __func__);
2668 sc->beacon.bslot[i] = NULL;
c52f33d0 2669 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2670 }
2671 }
2672
17d7904d 2673 sc->nvifs--;
141b38b6
S		 2674
2675 mutex_unlock(&sc->mutex);
f078f209
LR		 2676}
2677
e8975581 2678static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2679{
bce048d7
JM		 2680 struct ath_wiphy *aphy = hw->priv;
2681 struct ath_softc *sc = aphy->sc;
c46917bb 2682 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
e8975581 2683 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2684 struct ath_hw *ah = sc->sc_ah;
64839170 2685 bool all_wiphys_idle = false, disable_radio = false;
f078f209 2686
aa33de09 2687 mutex_lock(&sc->mutex);
141b38b6 2688
64839170
LR		 2689 /* Leave this as the first check */
2690 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2691
2692 spin_lock_bh(&sc->wiphy_lock);
2693 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2694 spin_unlock_bh(&sc->wiphy_lock);
2695
2696 if (conf->flags & IEEE80211_CONF_IDLE){
2697 if (all_wiphys_idle)
2698 disable_radio = true;
2699 }
2700 else if (all_wiphys_idle) {
2701 ath_radio_enable(sc);
c46917bb
LR		 2702 ath_print(common, ATH_DBG_CONFIG,
2703 "not-idle: enabling radio\n");
64839170
LR		 2704 }
2705 }
2706
3cbb5dd7
VN		 2707 if (changed & IEEE80211_CONF_CHANGE_PS) {
2708 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2709 if (!(ah->caps.hw_caps &
2710 ATH9K_HW_CAP_AUTOSLEEP)) {
2711 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2712 sc->imask |= ATH9K_INT_TIM_TIMER;
2713 ath9k_hw_set_interrupts(sc->sc_ah,
2714 sc->imask);
2715 }
2716 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2717 }
96148326 2718 sc->ps_enabled = true;
3cbb5dd7 2719 } else {
96148326 2720 sc->ps_enabled = false;
9ecdef4b 2721 ath9k_setpower(sc, ATH9K_PM_AWAKE);
8782b41d
VN		 2722 if (!(ah->caps.hw_caps &
2723 ATH9K_HW_CAP_AUTOSLEEP)) {
2724 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca
JM		 2725 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2726 SC_OP_WAIT_FOR_CAB |
2727 SC_OP_WAIT_FOR_PSPOLL_DATA |
2728 SC_OP_WAIT_FOR_TX_ACK);
8782b41d
VN		 2729 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2730 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2731 ath9k_hw_set_interrupts(sc->sc_ah,
2732 sc->imask);
2733 }
3cbb5dd7
VN		 2734 }
2735 }
2736 }
2737
4797938c 2738 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2739 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2740 int pos = curchan->hw_value;
ae5eb026 2741
0e2dedf9
JM		 2742 aphy->chan_idx = pos;
2743 aphy->chan_is_ht = conf_is_ht(conf);
2744
8089cc47
JM		 2745 if (aphy->state == ATH_WIPHY_SCAN ||
2746 aphy->state == ATH_WIPHY_ACTIVE)
2747 ath9k_wiphy_pause_all_forced(sc, aphy);
2748 else {
2749 /*
2750 * Do not change operational channel based on a paused
2751 * wiphy changes.
2752 */
2753 goto skip_chan_change;
2754 }
0e2dedf9 2755
c46917bb
LR		 2756 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2757 curchan->center_freq);
f078f209 2758
5f8e077c 2759 /* XXX: remove me eventualy */
0e2dedf9 2760 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2761
ecf70441 2762 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2763
0e2dedf9 2764 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
c46917bb
LR		 2765 ath_print(common, ATH_DBG_FATAL,
2766 "Unable to set channel\n");
aa33de09 2767 mutex_unlock(&sc->mutex);
e11602b7
S		 2768 return -EINVAL;
2769 }
094d05dc 2770 }
f078f209 2771
8089cc47 2772skip_chan_change:
5c020dc6 2773 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2774 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2775
64839170 2776 if (disable_radio) {
c46917bb 2777 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
64839170
LR		 2778 ath_radio_disable(sc);
2779 }
2780
aa33de09 2781 mutex_unlock(&sc->mutex);
141b38b6 2782
f078f209
LR		 2783 return 0;
2784}
2785
8feceb67
VT		 2786#define SUPPORTED_FILTERS \
2787 (FIF_PROMISC_IN_BSS | \
2788 FIF_ALLMULTI | \
2789 FIF_CONTROL | \
af6a3fc7 2790 FIF_PSPOLL | \
8feceb67
VT		 2791 FIF_OTHER_BSS | \
2792 FIF_BCN_PRBRESP_PROMISC | \
2793 FIF_FCSFAIL)
c83be688 2794
8feceb67
VT		 2795/* FIXME: sc->sc_full_reset ? */
2796static void ath9k_configure_filter(struct ieee80211_hw *hw,
2797 unsigned int changed_flags,
2798 unsigned int *total_flags,
3ac64bee 2799 u64 multicast)
8feceb67 2800{
bce048d7
JM		 2801 struct ath_wiphy *aphy = hw->priv;
2802 struct ath_softc *sc = aphy->sc;
8feceb67 2803 u32 rfilt;
f078f209 2804
8feceb67
VT		 2805 changed_flags &= SUPPORTED_FILTERS;
2806 *total_flags &= SUPPORTED_FILTERS;
f078f209 2807
b77f483f 2808 sc->rx.rxfilter = *total_flags;
aa68aeaa 2809 ath9k_ps_wakeup(sc);
8feceb67
VT		 2810 rfilt = ath_calcrxfilter(sc);
2811 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 2812 ath9k_ps_restore(sc);
f078f209 2813
c46917bb
LR		 2814 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
2815 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 2816}
f078f209 2817
8feceb67
VT		 2818static void ath9k_sta_notify(struct ieee80211_hw *hw,
2819 struct ieee80211_vif *vif,
2820 enum sta_notify_cmd cmd,
17741cdc 2821 struct ieee80211_sta *sta)
8feceb67 2822{
bce048d7
JM		 2823 struct ath_wiphy *aphy = hw->priv;
2824 struct ath_softc *sc = aphy->sc;
f078f209 2825
8feceb67
VT		 2826 switch (cmd) {
2827 case STA_NOTIFY_ADD:
5640b08e 2828 ath_node_attach(sc, sta);
8feceb67
VT		 2829 break;
2830 case STA_NOTIFY_REMOVE:
b5aa9bf9 2831 ath_node_detach(sc, sta);
8feceb67
VT		 2832 break;
2833 default:
2834 break;
2835 }
f078f209
LR		 2836}
2837
141b38b6 2838static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2839 const struct ieee80211_tx_queue_params *params)
f078f209 2840{
bce048d7
JM		 2841 struct ath_wiphy *aphy = hw->priv;
2842 struct ath_softc *sc = aphy->sc;
c46917bb 2843 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67
VT		 2844 struct ath9k_tx_queue_info qi;
2845 int ret = 0, qnum;
f078f209 2846
8feceb67
VT		 2847 if (queue >= WME_NUM_AC)
2848 return 0;
f078f209 2849
141b38b6
S		 2850 mutex_lock(&sc->mutex);
2851
1ffb0610
S		 2852 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2853
8feceb67
VT		 2854 qi.tqi_aifs = params->aifs;
2855 qi.tqi_cwmin = params->cw_min;
2856 qi.tqi_cwmax = params->cw_max;
2857 qi.tqi_burstTime = params->txop;
2858 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2859
c46917bb
LR		 2860 ath_print(common, ATH_DBG_CONFIG,
2861 "Configure tx [queue/halq] [%d/%d], "
2862 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2863 queue, qnum, params->aifs, params->cw_min,
2864 params->cw_max, params->txop);
f078f209 2865
8feceb67
VT		 2866 ret = ath_txq_update(sc, qnum, &qi);
2867 if (ret)
c46917bb 2868 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2869
141b38b6
S		 2870 mutex_unlock(&sc->mutex);
2871
8feceb67
VT		 2872 return ret;
2873}
f078f209 2874
8feceb67
VT		 2875static int ath9k_set_key(struct ieee80211_hw *hw,
2876 enum set_key_cmd cmd,
dc822b5d
JB		 2877 struct ieee80211_vif *vif,
2878 struct ieee80211_sta *sta,
8feceb67
VT		 2879 struct ieee80211_key_conf *key)
2880{
bce048d7
JM		 2881 struct ath_wiphy *aphy = hw->priv;
2882 struct ath_softc *sc = aphy->sc;
c46917bb 2883 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 2884 int ret = 0;
f078f209 2885
b3bd89ce
JM		 2886 if (modparam_nohwcrypt)
2887 return -ENOSPC;
2888
141b38b6 2889 mutex_lock(&sc->mutex);
3cbb5dd7 2890 ath9k_ps_wakeup(sc);
c46917bb 2891 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2892
8feceb67
VT		 2893 switch (cmd) {
2894 case SET_KEY:
3f53dd64 2895 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2896 if (ret >= 0) {
2897 key->hw_key_idx = ret;
8feceb67
VT		 2898 /* push IV and Michael MIC generation to stack */
2899 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2900 if (key->alg == ALG_TKIP)
2901 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2902 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2903 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2904 ret = 0;
8feceb67
VT		 2905 }
2906 break;
2907 case DISABLE_KEY:
2908 ath_key_delete(sc, key);
8feceb67
VT		 2909 break;
2910 default:
2911 ret = -EINVAL;
2912 }
f078f209 2913
3cbb5dd7 2914 ath9k_ps_restore(sc);
141b38b6
S		 2915 mutex_unlock(&sc->mutex);
2916
8feceb67
VT		 2917 return ret;
2918}
f078f209 2919
8feceb67
VT		 2920static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2921 struct ieee80211_vif *vif,
2922 struct ieee80211_bss_conf *bss_conf,
2923 u32 changed)
2924{
bce048d7
JM		 2925 struct ath_wiphy *aphy = hw->priv;
2926 struct ath_softc *sc = aphy->sc;
2d0ddec5 2927 struct ath_hw *ah = sc->sc_ah;
1510718d 2928 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5
JB		 2929 struct ath_vif *avp = (void *)vif->drv_priv;
2930 u32 rfilt = 0;
2931 int error, i;
f078f209 2932
141b38b6
S		 2933 mutex_lock(&sc->mutex);
2934
2d0ddec5
JB		 2935 /*
2936 * TODO: Need to decide which hw opmode to use for
2937 * multi-interface cases
2938 * XXX: This belongs into add_interface!
2939 */
2940 if (vif->type == NL80211_IFTYPE_AP &&
2941 ah->opmode != NL80211_IFTYPE_AP) {
2942 ah->opmode = NL80211_IFTYPE_STATION;
2943 ath9k_hw_setopmode(ah);
1510718d
LR		 2944 memcpy(common->curbssid, common->macaddr, ETH_ALEN);
2945 common->curaid = 0;
f2b2143e 2946 ath9k_hw_write_associd(ah);
2d0ddec5
JB		 2947 /* Request full reset to get hw opmode changed properly */
2948 sc->sc_flags |= SC_OP_FULL_RESET;
2949 }
2950
2951 if ((changed & BSS_CHANGED_BSSID) &&
2952 !is_zero_ether_addr(bss_conf->bssid)) {
2953 switch (vif->type) {
2954 case NL80211_IFTYPE_STATION:
2955 case NL80211_IFTYPE_ADHOC:
2956 case NL80211_IFTYPE_MESH_POINT:
2957 /* Set BSSID */
1510718d 2958 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2d0ddec5 2959 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1510718d 2960 common->curaid = 0;
f2b2143e 2961 ath9k_hw_write_associd(ah);
2d0ddec5
JB		 2962
2963 /* Set aggregation protection mode parameters */
2964 sc->config.ath_aggr_prot = 0;
2965
c46917bb
LR		 2966 ath_print(common, ATH_DBG_CONFIG,
2967 "RX filter 0x%x bssid %pM aid 0x%x\n",
2968 rfilt, common->curbssid, common->curaid);
2d0ddec5
JB		 2969
2970 /* need to reconfigure the beacon */
2971 sc->sc_flags &= ~SC_OP_BEACONS ;
2972
2973 break;
2974 default:
2975 break;
2976 }
2977 }
2978
2979 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2980 (vif->type == NL80211_IFTYPE_AP) ||
2981 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2982 if ((changed & BSS_CHANGED_BEACON) ||
2983 (changed & BSS_CHANGED_BEACON_ENABLED &&
2984 bss_conf->enable_beacon)) {
2985 /*
2986 * Allocate and setup the beacon frame.
2987 *
2988 * Stop any previous beacon DMA. This may be
2989 * necessary, for example, when an ibss merge
2990 * causes reconfiguration; we may be called
2991 * with beacon transmission active.
2992 */
2993 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2994
2995 error = ath_beacon_alloc(aphy, vif);
2996 if (!error)
2997 ath_beacon_config(sc, vif);
2998 }
2999 }
3000
3001 /* Check for WLAN_CAPABILITY_PRIVACY ? */
3002 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
3003 for (i = 0; i < IEEE80211_WEP_NKID; i++)
3004 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
3005 ath9k_hw_keysetmac(sc->sc_ah,
3006 (u16)i,
1510718d 3007 common->curbssid);
2d0ddec5
JB		 3008 }
3009
3010 /* Only legacy IBSS for now */
3011 if (vif->type == NL80211_IFTYPE_ADHOC)
3012 ath_update_chainmask(sc, 0);
3013
8feceb67 3014 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
c46917bb
LR		 3015 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
3016 bss_conf->use_short_preamble);
8feceb67
VT		 3017 if (bss_conf->use_short_preamble)
3018 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
3019 else
3020 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
3021 }
f078f209 3022
8feceb67 3023 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
c46917bb
LR		 3024 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
3025 bss_conf->use_cts_prot);
8feceb67
VT		 3026 if (bss_conf->use_cts_prot &&
3027 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
3028 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
3029 else
3030 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
3031 }
f078f209 3032
8feceb67 3033 if (changed & BSS_CHANGED_ASSOC) {
c46917bb 3034 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 3035 bss_conf->assoc);
5640b08e 3036 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 3037 }
141b38b6 3038
57c4d7b4
JB		 3039 /*
3040 * The HW TSF has to be reset when the beacon interval changes.
3041 * We set the flag here, and ath_beacon_config_ap() would take this
3042 * into account when it gets called through the subsequent
3043 * config_interface() call - with IFCC_BEACON in the changed field.
3044 */
3045
3046 if (changed & BSS_CHANGED_BEACON_INT) {
3047 sc->sc_flags |= SC_OP_TSF_RESET;
3048 sc->beacon_interval = bss_conf->beacon_int;
3049 }
3050
141b38b6 3051 mutex_unlock(&sc->mutex);
8feceb67 3052}
f078f209 3053
8feceb67
VT		 3054static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
3055{
3056 u64 tsf;
bce048d7
JM		 3057 struct ath_wiphy *aphy = hw->priv;
3058 struct ath_softc *sc = aphy->sc;
f078f209 3059
141b38b6
S		 3060 mutex_lock(&sc->mutex);
3061 tsf = ath9k_hw_gettsf64(sc->sc_ah);
3062 mutex_unlock(&sc->mutex);
f078f209 3063
8feceb67
VT		 3064 return tsf;
3065}
f078f209 3066
3b5d665b
AF		 3067static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3068{
bce048d7
JM		 3069 struct ath_wiphy *aphy = hw->priv;
3070 struct ath_softc *sc = aphy->sc;
3b5d665b 3071
141b38b6
S		 3072 mutex_lock(&sc->mutex);
3073 ath9k_hw_settsf64(sc->sc_ah, tsf);
3074 mutex_unlock(&sc->mutex);
3b5d665b
AF		 3075}
3076
8feceb67
VT		 3077static void ath9k_reset_tsf(struct ieee80211_hw *hw)
3078{
bce048d7
JM		 3079 struct ath_wiphy *aphy = hw->priv;
3080 struct ath_softc *sc = aphy->sc;
c83be688 3081
141b38b6 3082 mutex_lock(&sc->mutex);
21526d57
LR		 3083
3084 ath9k_ps_wakeup(sc);
141b38b6 3085 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR		 3086 ath9k_ps_restore(sc);
3087
141b38b6 3088 mutex_unlock(&sc->mutex);
8feceb67 3089}
f078f209 3090
8feceb67 3091static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 3092 enum ieee80211_ampdu_mlme_action action,
3093 struct ieee80211_sta *sta,
3094 u16 tid, u16 *ssn)
8feceb67 3095{
bce048d7
JM		 3096 struct ath_wiphy *aphy = hw->priv;
3097 struct ath_softc *sc = aphy->sc;
8feceb67 3098 int ret = 0;
f078f209 3099
8feceb67
VT		 3100 switch (action) {
3101 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 3102 if (!(sc->sc_flags & SC_OP_RXAGGR))
3103 ret = -ENOTSUPP;
8feceb67
VT		 3104 break;
3105 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 3106 break;
3107 case IEEE80211_AMPDU_TX_START:
f83da965
S		 3108 ath_tx_aggr_start(sc, sta, tid, ssn);
3109 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 3110 break;
3111 case IEEE80211_AMPDU_TX_STOP:
f83da965 3112 ath_tx_aggr_stop(sc, sta, tid);
17741cdc 3113 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 3114 break;
b1720231 3115 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 3116 ath_tx_aggr_resume(sc, sta, tid);
3117 break;
8feceb67 3118 default:
c46917bb
LR		 3119 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
3120 "Unknown AMPDU action\n");
8feceb67
VT		 3121 }
3122
3123 return ret;
f078f209
LR		 3124}
3125
0c98de65
S		 3126static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
3127{
bce048d7
JM		 3128 struct ath_wiphy *aphy = hw->priv;
3129 struct ath_softc *sc = aphy->sc;
0c98de65 3130
3d832611 3131 mutex_lock(&sc->mutex);
8089cc47
JM		 3132 if (ath9k_wiphy_scanning(sc)) {
3133 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
3134 "same time\n");
3135 /*
3136 * Do not allow the concurrent scanning state for now. This
3137 * could be improved with scanning control moved into ath9k.
3138 */
3d832611 3139 mutex_unlock(&sc->mutex);
8089cc47
JM		 3140 return;
3141 }
3142
3143 aphy->state = ATH_WIPHY_SCAN;
3144 ath9k_wiphy_pause_all_forced(sc, aphy);
3145
e5f0921a 3146 spin_lock_bh(&sc->ani_lock);
0c98de65 3147 sc->sc_flags |= SC_OP_SCANNING;
e5f0921a 3148 spin_unlock_bh(&sc->ani_lock);
3d832611 3149 mutex_unlock(&sc->mutex);
0c98de65
S		 3150}
3151
3152static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
3153{
bce048d7
JM		 3154 struct ath_wiphy *aphy = hw->priv;
3155 struct ath_softc *sc = aphy->sc;
0c98de65 3156
3d832611 3157 mutex_lock(&sc->mutex);
e5f0921a 3158 spin_lock_bh(&sc->ani_lock);
8089cc47 3159 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 3160 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 3161 sc->sc_flags |= SC_OP_FULL_RESET;
e5f0921a 3162 spin_unlock_bh(&sc->ani_lock);
d0bec342 3163 ath_beacon_config(sc, NULL);
3d832611 3164 mutex_unlock(&sc->mutex);
0c98de65
S		 3165}
3166
6baff7f9 3167struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 3168 .tx = ath9k_tx,
3169 .start = ath9k_start,
3170 .stop = ath9k_stop,
3171 .add_interface = ath9k_add_interface,
3172 .remove_interface = ath9k_remove_interface,
3173 .config = ath9k_config,
8feceb67 3174 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 3175 .sta_notify = ath9k_sta_notify,
3176 .conf_tx = ath9k_conf_tx,
8feceb67 3177 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 3178 .set_key = ath9k_set_key,
8feceb67 3179 .get_tsf = ath9k_get_tsf,
3b5d665b 3180 .set_tsf = ath9k_set_tsf,
8feceb67 3181 .reset_tsf = ath9k_reset_tsf,
4233df6b 3182 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 3183 .sw_scan_start = ath9k_sw_scan_start,
3184 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 3185 .rfkill_poll = ath9k_rfkill_poll_state,
8feceb67
VT		 3186};
3187
392dff83
BP		 3188static struct {
3189 u32 version;
3190 const char * name;
3191} ath_mac_bb_names[] = {
3192 { AR_SREV_VERSION_5416_PCI, "5416" },
3193 { AR_SREV_VERSION_5416_PCIE, "5418" },
3194 { AR_SREV_VERSION_9100, "9100" },
3195 { AR_SREV_VERSION_9160, "9160" },
3196 { AR_SREV_VERSION_9280, "9280" },
ac88b6ec
VN		 3197 { AR_SREV_VERSION_9285, "9285" },
3198 { AR_SREV_VERSION_9287, "9287" }
392dff83
BP		 3199};
3200
3201static struct {
3202 u16 version;
3203 const char * name;
3204} ath_rf_names[] = {
3205 { 0, "5133" },
3206 { AR_RAD5133_SREV_MAJOR, "5133" },
3207 { AR_RAD5122_SREV_MAJOR, "5122" },
3208 { AR_RAD2133_SREV_MAJOR, "2133" },
3209 { AR_RAD2122_SREV_MAJOR, "2122" }
3210};
3211
3212/*
3213 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3214 */
6baff7f9 3215const char *
392dff83
BP		 3216ath_mac_bb_name(u32 mac_bb_version)
3217{
3218 int i;
3219
3220 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3221 if (ath_mac_bb_names[i].version == mac_bb_version) {
3222 return ath_mac_bb_names[i].name;
3223 }
3224 }
3225
3226 return "????";
3227}
3228
3229/*
3230 * Return the RF name. "????" is returned if the RF is unknown.
3231 */
6baff7f9 3232const char *
392dff83
BP		 3233ath_rf_name(u16 rf_version)
3234{
3235 int i;
3236
3237 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3238 if (ath_rf_names[i].version == rf_version) {
3239 return ath_rf_names[i].name;
3240 }
3241 }
3242
3243 return "????";
3244}
3245
6baff7f9 3246static int __init ath9k_init(void)
f078f209 3247{
ca8a8560
VT		 3248 int error;
3249
ca8a8560
VT		 3250 /* Register rate control algorithm */
3251 error = ath_rate_control_register();
3252 if (error != 0) {
3253 printk(KERN_ERR
b51bb3cd
LR		 3254 "ath9k: Unable to register rate control "
3255 "algorithm: %d\n",
ca8a8560 3256 error);
6baff7f9 3257 goto err_out;
ca8a8560
VT		 3258 }
3259
19d8bc22
GJ		 3260 error = ath9k_debug_create_root();
3261 if (error) {
3262 printk(KERN_ERR
3263 "ath9k: Unable to create debugfs root: %d\n",
3264 error);
3265 goto err_rate_unregister;
3266 }
3267
6baff7f9
GJ		 3268 error = ath_pci_init();
3269 if (error < 0) {
f078f209 3270 printk(KERN_ERR
b51bb3cd 3271 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 3272 error = -ENODEV;
19d8bc22 3273 goto err_remove_root;
f078f209
LR		 3274 }
3275
09329d37
GJ		 3276 error = ath_ahb_init();
3277 if (error < 0) {
3278 error = -ENODEV;
3279 goto err_pci_exit;
3280 }
3281
f078f209 3282 return 0;
6baff7f9 3283
09329d37
GJ		 3284 err_pci_exit:
3285 ath_pci_exit();
3286
19d8bc22
GJ		 3287 err_remove_root:
3288 ath9k_debug_remove_root();
6baff7f9
GJ		 3289 err_rate_unregister:
3290 ath_rate_control_unregister();
3291 err_out:
3292 return error;
f078f209 3293}
6baff7f9 3294module_init(ath9k_init);
f078f209 3295
6baff7f9 3296static void __exit ath9k_exit(void)
f078f209 3297{
09329d37 3298 ath_ahb_exit();
6baff7f9 3299 ath_pci_exit();
19d8bc22 3300 ath9k_debug_remove_root();
ca8a8560 3301 ath_rate_control_unregister();
04bd4638 3302 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 3303}
6baff7f9 3304module_exit(ath9k_exit);
Linux kernel - Deliverables
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