ath9k_hw: use register name in place of magic value
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
ff37e337
S
22static u8 parse_mpdudensity(u8 mpdudensity)
23{
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55}
56
69081624
VT
57static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
58{
59 bool pending = false;
60
61 spin_lock_bh(&txq->axq_lock);
62
63 if (txq->axq_depth || !list_empty(&txq->axq_acq))
64 pending = true;
69081624
VT
65
66 spin_unlock_bh(&txq->axq_lock);
67 return pending;
68}
69
6d79cb4c 70static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
71{
72 unsigned long flags;
73 bool ret;
74
9ecdef4b
LR
75 spin_lock_irqsave(&sc->sc_pm_lock, flags);
76 ret = ath9k_hw_setpower(sc->sc_ah, mode);
77 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
78
79 return ret;
80}
81
a91d75ae
LR
82void ath9k_ps_wakeup(struct ath_softc *sc)
83{
898c914a 84 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 85 unsigned long flags;
fbb078fc 86 enum ath9k_power_mode power_mode;
a91d75ae
LR
87
88 spin_lock_irqsave(&sc->sc_pm_lock, flags);
89 if (++sc->ps_usecount != 1)
90 goto unlock;
91
fbb078fc 92 power_mode = sc->sc_ah->power_mode;
9ecdef4b 93 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 94
898c914a
FF
95 /*
96 * While the hardware is asleep, the cycle counters contain no
97 * useful data. Better clear them now so that they don't mess up
98 * survey data results.
99 */
fbb078fc
FF
100 if (power_mode != ATH9K_PM_AWAKE) {
101 spin_lock(&common->cc_lock);
102 ath_hw_cycle_counters_update(common);
103 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
104 spin_unlock(&common->cc_lock);
105 }
898c914a 106
a91d75ae
LR
107 unlock:
108 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
109}
110
111void ath9k_ps_restore(struct ath_softc *sc)
112{
898c914a 113 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae
LR
114 unsigned long flags;
115
116 spin_lock_irqsave(&sc->sc_pm_lock, flags);
117 if (--sc->ps_usecount != 0)
118 goto unlock;
119
898c914a
FF
120 spin_lock(&common->cc_lock);
121 ath_hw_cycle_counters_update(common);
122 spin_unlock(&common->cc_lock);
123
1dbfd9d4
VN
124 if (sc->ps_idle)
125 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
126 else if (sc->ps_enabled &&
127 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1b04b930
S
128 PS_WAIT_FOR_CAB |
129 PS_WAIT_FOR_PSPOLL_DATA |
130 PS_WAIT_FOR_TX_ACK)))
9ecdef4b 131 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR
132
133 unlock:
134 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
135}
136
05c0be2f 137void ath_start_ani(struct ath_common *common)
5ee08656
FF
138{
139 struct ath_hw *ah = common->ah;
140 unsigned long timestamp = jiffies_to_msecs(jiffies);
141 struct ath_softc *sc = (struct ath_softc *) common->priv;
142
143 if (!(sc->sc_flags & SC_OP_ANI_RUN))
144 return;
145
146 if (sc->sc_flags & SC_OP_OFFCHANNEL)
147 return;
148
149 common->ani.longcal_timer = timestamp;
150 common->ani.shortcal_timer = timestamp;
151 common->ani.checkani_timer = timestamp;
152
153 mod_timer(&common->ani.timer,
154 jiffies +
155 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
156}
157
3430098a
FF
158static void ath_update_survey_nf(struct ath_softc *sc, int channel)
159{
160 struct ath_hw *ah = sc->sc_ah;
161 struct ath9k_channel *chan = &ah->channels[channel];
162 struct survey_info *survey = &sc->survey[channel];
163
164 if (chan->noisefloor) {
165 survey->filled |= SURVEY_INFO_NOISE_DBM;
f749b946 166 survey->noise = ath9k_hw_getchan_noise(ah, chan);
3430098a
FF
167 }
168}
169
cb8d61de
FF
170/*
171 * Updates the survey statistics and returns the busy time since last
172 * update in %, if the measurement duration was long enough for the
173 * result to be useful, -1 otherwise.
174 */
175static int ath_update_survey_stats(struct ath_softc *sc)
3430098a
FF
176{
177 struct ath_hw *ah = sc->sc_ah;
178 struct ath_common *common = ath9k_hw_common(ah);
179 int pos = ah->curchan - &ah->channels[0];
180 struct survey_info *survey = &sc->survey[pos];
181 struct ath_cycle_counters *cc = &common->cc_survey;
182 unsigned int div = common->clockrate * 1000;
cb8d61de 183 int ret = 0;
3430098a 184
0845735e 185 if (!ah->curchan)
cb8d61de 186 return -1;
0845735e 187
898c914a
FF
188 if (ah->power_mode == ATH9K_PM_AWAKE)
189 ath_hw_cycle_counters_update(common);
3430098a
FF
190
191 if (cc->cycles > 0) {
192 survey->filled |= SURVEY_INFO_CHANNEL_TIME |
193 SURVEY_INFO_CHANNEL_TIME_BUSY |
194 SURVEY_INFO_CHANNEL_TIME_RX |
195 SURVEY_INFO_CHANNEL_TIME_TX;
196 survey->channel_time += cc->cycles / div;
197 survey->channel_time_busy += cc->rx_busy / div;
198 survey->channel_time_rx += cc->rx_frame / div;
199 survey->channel_time_tx += cc->tx_frame / div;
200 }
cb8d61de
FF
201
202 if (cc->cycles < div)
203 return -1;
204
205 if (cc->cycles > 0)
206 ret = cc->rx_busy * 100 / cc->cycles;
207
3430098a
FF
208 memset(cc, 0, sizeof(*cc));
209
210 ath_update_survey_nf(sc, pos);
cb8d61de
FF
211
212 return ret;
3430098a
FF
213}
214
ff37e337
S
215/*
216 * Set/change channels. If the channel is really being changed, it's done
217 * by reseting the chip. To accomplish this we must first cleanup any pending
218 * DMA, then restart stuff.
219*/
5595f119 220static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
0e2dedf9 221 struct ath9k_channel *hchan)
ff37e337 222{
cbe61d8a 223 struct ath_hw *ah = sc->sc_ah;
c46917bb 224 struct ath_common *common = ath9k_hw_common(ah);
25c56eec 225 struct ieee80211_conf *conf = &common->hw->conf;
ff37e337 226 bool fastcc = true, stopped;
ae8d2858 227 struct ieee80211_channel *channel = hw->conf.channel;
20bd2a09 228 struct ath9k_hw_cal_data *caldata = NULL;
ae8d2858 229 int r;
ff37e337
S
230
231 if (sc->sc_flags & SC_OP_INVALID)
232 return -EIO;
233
cb8d61de
FF
234 sc->hw_busy_count = 0;
235
5ee08656
FF
236 del_timer_sync(&common->ani.timer);
237 cancel_work_sync(&sc->paprd_work);
238 cancel_work_sync(&sc->hw_check_work);
239 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 240 cancel_delayed_work_sync(&sc->hw_pll_work);
5ee08656 241
3cbb5dd7
VN
242 ath9k_ps_wakeup(sc);
243
6a6733f2
LR
244 spin_lock_bh(&sc->sc_pcu_lock);
245
c0d7c7af
LR
246 /*
247 * This is only performed if the channel settings have
248 * actually changed.
249 *
250 * To switch channels clear any pending DMA operations;
251 * wait long enough for the RX fifo to drain, reset the
252 * hardware at the new frequency, and then re-enable
253 * the relevant bits of the h/w.
254 */
4df3071e 255 ath9k_hw_disable_interrupts(ah);
080e1a25 256 stopped = ath_drain_all_txq(sc, false);
5e848f78 257
080e1a25
FF
258 if (!ath_stoprecv(sc))
259 stopped = false;
ff37e337 260
8b3f4616
FF
261 if (!ath9k_hw_check_alive(ah))
262 stopped = false;
263
c0d7c7af
LR
264 /* XXX: do not flush receive queue here. We don't want
265 * to flush data frames already in queue because of
266 * changing channel. */
ff37e337 267
5ee08656 268 if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
c0d7c7af
LR
269 fastcc = false;
270
20bd2a09 271 if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
9ac58615 272 caldata = &sc->caldata;
20bd2a09 273
226afe68
JP
274 ath_dbg(common, ATH_DBG_CONFIG,
275 "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
276 sc->sc_ah->curchan->channel,
277 channel->center_freq, conf_is_ht40(conf),
278 fastcc);
ff37e337 279
20bd2a09 280 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
c0d7c7af 281 if (r) {
3800276a
JP
282 ath_err(common,
283 "Unable to reset channel (%u MHz), reset status %d\n",
284 channel->center_freq, r);
3989279c 285 goto ps_restore;
ff37e337 286 }
c0d7c7af 287
c0d7c7af 288 if (ath_startrecv(sc) != 0) {
3800276a 289 ath_err(common, "Unable to restart recv logic\n");
3989279c
GJ
290 r = -EIO;
291 goto ps_restore;
c0d7c7af
LR
292 }
293
5048e8c3
RM
294 ath9k_cmn_update_txpow(ah, sc->curtxpow,
295 sc->config.txpowlimit, &sc->curtxpow);
3069168c 296 ath9k_hw_set_interrupts(ah, ah->imask);
3989279c 297
48a6a468 298 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
1186488b 299 if (sc->sc_flags & SC_OP_BEACONS)
99e4d43a 300 ath_set_beacon(sc);
5ee08656 301 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
181fb18d 302 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2);
05c0be2f
MSS
303 if (!common->disable_ani)
304 ath_start_ani(common);
5ee08656
FF
305 }
306
3989279c 307 ps_restore:
92460412
FF
308 ieee80211_wake_queues(hw);
309
6a6733f2
LR
310 spin_unlock_bh(&sc->sc_pcu_lock);
311
3cbb5dd7 312 ath9k_ps_restore(sc);
3989279c 313 return r;
ff37e337
S
314}
315
9f42c2b6
FF
316static void ath_paprd_activate(struct ath_softc *sc)
317{
318 struct ath_hw *ah = sc->sc_ah;
20bd2a09 319 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 320 struct ath_common *common = ath9k_hw_common(ah);
9f42c2b6
FF
321 int chain;
322
20bd2a09 323 if (!caldata || !caldata->paprd_done)
9f42c2b6
FF
324 return;
325
326 ath9k_ps_wakeup(sc);
ddfef792 327 ar9003_paprd_enable(ah, false);
9f42c2b6 328 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
9094537c 329 if (!(common->tx_chainmask & BIT(chain)))
9f42c2b6
FF
330 continue;
331
20bd2a09 332 ar9003_paprd_populate_single_table(ah, caldata, chain);
9f42c2b6
FF
333 }
334
335 ar9003_paprd_enable(ah, true);
336 ath9k_ps_restore(sc);
337}
338
7607cbe2
FF
339static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
340{
341 struct ieee80211_hw *hw = sc->hw;
342 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
47960077
MSS
343 struct ath_hw *ah = sc->sc_ah;
344 struct ath_common *common = ath9k_hw_common(ah);
7607cbe2
FF
345 struct ath_tx_control txctl;
346 int time_left;
347
348 memset(&txctl, 0, sizeof(txctl));
349 txctl.txq = sc->tx.txq_map[WME_AC_BE];
350
351 memset(tx_info, 0, sizeof(*tx_info));
352 tx_info->band = hw->conf.channel->band;
353 tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
354 tx_info->control.rates[0].idx = 0;
355 tx_info->control.rates[0].count = 1;
356 tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
357 tx_info->control.rates[1].idx = -1;
358
359 init_completion(&sc->paprd_complete);
7607cbe2 360 txctl.paprd = BIT(chain);
47960077
MSS
361
362 if (ath_tx_start(hw, skb, &txctl) != 0) {
d4bb17c4 363 ath_dbg(common, ATH_DBG_CALIBRATE, "PAPRD TX failed\n");
47960077 364 dev_kfree_skb_any(skb);
7607cbe2 365 return false;
47960077 366 }
7607cbe2
FF
367
368 time_left = wait_for_completion_timeout(&sc->paprd_complete,
369 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
7607cbe2
FF
370
371 if (!time_left)
d4bb17c4 372 ath_dbg(common, ATH_DBG_CALIBRATE,
7607cbe2
FF
373 "Timeout waiting for paprd training on TX chain %d\n",
374 chain);
375
376 return !!time_left;
377}
378
9f42c2b6
FF
379void ath_paprd_calibrate(struct work_struct *work)
380{
381 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
382 struct ieee80211_hw *hw = sc->hw;
383 struct ath_hw *ah = sc->sc_ah;
384 struct ieee80211_hdr *hdr;
385 struct sk_buff *skb = NULL;
20bd2a09 386 struct ath9k_hw_cal_data *caldata = ah->caldata;
9094537c 387 struct ath_common *common = ath9k_hw_common(ah);
066dae93 388 int ftype;
9f42c2b6
FF
389 int chain_ok = 0;
390 int chain;
391 int len = 1800;
9f42c2b6 392
20bd2a09
FF
393 if (!caldata)
394 return;
395
b942471b
MSS
396 ath9k_ps_wakeup(sc);
397
1bf38661 398 if (ar9003_paprd_init_table(ah) < 0)
b942471b 399 goto fail_paprd;
1bf38661 400
9f42c2b6
FF
401 skb = alloc_skb(len, GFP_KERNEL);
402 if (!skb)
b942471b 403 goto fail_paprd;
9f42c2b6 404
9f42c2b6
FF
405 skb_put(skb, len);
406 memset(skb->data, 0, len);
407 hdr = (struct ieee80211_hdr *)skb->data;
408 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
409 hdr->frame_control = cpu_to_le16(ftype);
a3d3da14 410 hdr->duration_id = cpu_to_le16(10);
9f42c2b6
FF
411 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
412 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
413 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
414
9f42c2b6 415 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
9094537c 416 if (!(common->tx_chainmask & BIT(chain)))
9f42c2b6
FF
417 continue;
418
419 chain_ok = 0;
9f42c2b6 420
7607cbe2
FF
421 ath_dbg(common, ATH_DBG_CALIBRATE,
422 "Sending PAPRD frame for thermal measurement "
423 "on chain %d\n", chain);
424 if (!ath_paprd_send_frame(sc, skb, chain))
425 goto fail_paprd;
9f42c2b6 426
9f42c2b6 427 ar9003_paprd_setup_gain_table(ah, chain);
9f42c2b6 428
7607cbe2
FF
429 ath_dbg(common, ATH_DBG_CALIBRATE,
430 "Sending PAPRD training frame on chain %d\n", chain);
431 if (!ath_paprd_send_frame(sc, skb, chain))
ca369eb4 432 goto fail_paprd;
9f42c2b6 433
d4bb17c4
MSS
434 if (!ar9003_paprd_is_done(ah)) {
435 ath_dbg(common, ATH_DBG_CALIBRATE,
436 "PAPRD not yet done on chain %d\n", chain);
9f42c2b6 437 break;
d4bb17c4 438 }
9f42c2b6 439
d4bb17c4
MSS
440 if (ar9003_paprd_create_curve(ah, caldata, chain)) {
441 ath_dbg(common, ATH_DBG_CALIBRATE,
442 "PAPRD create curve failed on chain %d\n",
443 chain);
9f42c2b6 444 break;
d4bb17c4 445 }
9f42c2b6
FF
446
447 chain_ok = 1;
448 }
449 kfree_skb(skb);
450
451 if (chain_ok) {
20bd2a09 452 caldata->paprd_done = true;
9f42c2b6
FF
453 ath_paprd_activate(sc);
454 }
455
ca369eb4 456fail_paprd:
9f42c2b6
FF
457 ath9k_ps_restore(sc);
458}
459
ff37e337
S
460/*
461 * This routine performs the periodic noise floor calibration function
462 * that is used to adjust and optimize the chip performance. This
463 * takes environmental changes (location, temperature) into account.
464 * When the task is complete, it reschedules itself depending on the
465 * appropriate interval that was calculated.
466 */
55624204 467void ath_ani_calibrate(unsigned long data)
ff37e337 468{
20977d3e
S
469 struct ath_softc *sc = (struct ath_softc *)data;
470 struct ath_hw *ah = sc->sc_ah;
c46917bb 471 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
472 bool longcal = false;
473 bool shortcal = false;
474 bool aniflag = false;
475 unsigned int timestamp = jiffies_to_msecs(jiffies);
6044474e 476 u32 cal_interval, short_cal_interval, long_cal_interval;
b5bfc568 477 unsigned long flags;
6044474e
FF
478
479 if (ah->caldata && ah->caldata->nfcal_interference)
480 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
481 else
482 long_cal_interval = ATH_LONG_CALINTERVAL;
ff37e337 483
20977d3e
S
484 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
485 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 486
1ffc1c61
JM
487 /* Only calibrate if awake */
488 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
489 goto set_timer;
490
491 ath9k_ps_wakeup(sc);
492
ff37e337 493 /* Long calibration runs independently of short calibration. */
6044474e 494 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
ff37e337 495 longcal = true;
226afe68 496 ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
3d536acf 497 common->ani.longcal_timer = timestamp;
ff37e337
S
498 }
499
17d7904d 500 /* Short calibration applies only while caldone is false */
3d536acf
LR
501 if (!common->ani.caldone) {
502 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 503 shortcal = true;
226afe68
JP
504 ath_dbg(common, ATH_DBG_ANI,
505 "shortcal @%lu\n", jiffies);
3d536acf
LR
506 common->ani.shortcal_timer = timestamp;
507 common->ani.resetcal_timer = timestamp;
ff37e337
S
508 }
509 } else {
3d536acf 510 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 511 ATH_RESTART_CALINTERVAL) {
3d536acf
LR
512 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
513 if (common->ani.caldone)
514 common->ani.resetcal_timer = timestamp;
ff37e337
S
515 }
516 }
517
518 /* Verify whether we must check ANI */
e36b27af
LR
519 if ((timestamp - common->ani.checkani_timer) >=
520 ah->config.ani_poll_interval) {
ff37e337 521 aniflag = true;
3d536acf 522 common->ani.checkani_timer = timestamp;
ff37e337
S
523 }
524
e62ddec9
MSS
525 /* Call ANI routine if necessary */
526 if (aniflag) {
527 spin_lock_irqsave(&common->cc_lock, flags);
528 ath9k_hw_ani_monitor(ah, ah->curchan);
529 ath_update_survey_stats(sc);
530 spin_unlock_irqrestore(&common->cc_lock, flags);
531 }
ff37e337 532
e62ddec9
MSS
533 /* Perform calibration if necessary */
534 if (longcal || shortcal) {
535 common->ani.caldone =
536 ath9k_hw_calibrate(ah, ah->curchan,
537 common->rx_chainmask, longcal);
ff37e337
S
538 }
539
1ffc1c61
JM
540 ath9k_ps_restore(sc);
541
20977d3e 542set_timer:
ff37e337
S
543 /*
544 * Set timer interval based on previous results.
545 * The interval must be the shortest necessary to satisfy ANI,
546 * short calibration and long calibration.
547 */
aac9207e 548 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 549 if (sc->sc_ah->config.enable_ani)
e36b27af
LR
550 cal_interval = min(cal_interval,
551 (u32)ah->config.ani_poll_interval);
3d536acf 552 if (!common->ani.caldone)
20977d3e 553 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 554
3d536acf 555 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
20bd2a09
FF
556 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
557 if (!ah->caldata->paprd_done)
9f42c2b6 558 ieee80211_queue_work(sc->hw, &sc->paprd_work);
45ef6a0b 559 else if (!ah->paprd_table_write_done)
9f42c2b6
FF
560 ath_paprd_activate(sc);
561 }
ff37e337
S
562}
563
ff37e337
S
564static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
565{
566 struct ath_node *an;
ea066d5a 567 struct ath_hw *ah = sc->sc_ah;
ff37e337
S
568 an = (struct ath_node *)sta->drv_priv;
569
7f010c93
BG
570#ifdef CONFIG_ATH9K_DEBUGFS
571 spin_lock(&sc->nodes_lock);
572 list_add(&an->list, &sc->nodes);
573 spin_unlock(&sc->nodes_lock);
574 an->sta = sta;
575#endif
ea066d5a
MSS
576 if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM)
577 sc->sc_flags |= SC_OP_ENABLE_APM;
578
87792efc 579 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 580 ath_tx_node_init(sc, an);
9e98ac65 581 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S
582 sta->ht_cap.ampdu_factor);
583 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
584 }
ff37e337
S
585}
586
587static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
588{
589 struct ath_node *an = (struct ath_node *)sta->drv_priv;
590
7f010c93
BG
591#ifdef CONFIG_ATH9K_DEBUGFS
592 spin_lock(&sc->nodes_lock);
593 list_del(&an->list);
594 spin_unlock(&sc->nodes_lock);
595 an->sta = NULL;
596#endif
597
ff37e337
S
598 if (sc->sc_flags & SC_OP_TXAGGR)
599 ath_tx_node_cleanup(sc, an);
600}
601
347809fc
FF
602void ath_hw_check(struct work_struct *work)
603{
604 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
cb8d61de
FF
605 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
606 unsigned long flags;
607 int busy;
347809fc
FF
608
609 ath9k_ps_wakeup(sc);
cb8d61de
FF
610 if (ath9k_hw_check_alive(sc->sc_ah))
611 goto out;
347809fc 612
cb8d61de
FF
613 spin_lock_irqsave(&common->cc_lock, flags);
614 busy = ath_update_survey_stats(sc);
615 spin_unlock_irqrestore(&common->cc_lock, flags);
347809fc 616
cb8d61de
FF
617 ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, "
618 "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1);
619 if (busy >= 99) {
f6b4e4d4
RM
620 if (++sc->hw_busy_count >= 3) {
621 spin_lock_bh(&sc->sc_pcu_lock);
cb8d61de 622 ath_reset(sc, true);
f6b4e4d4
RM
623 spin_unlock_bh(&sc->sc_pcu_lock);
624 }
cb8d61de
FF
625 } else if (busy >= 0)
626 sc->hw_busy_count = 0;
347809fc
FF
627
628out:
629 ath9k_ps_restore(sc);
630}
631
b84628eb
SB
632static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum)
633{
634 static int count;
635 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
636
637 if (pll_sqsum >= 0x40000) {
638 count++;
639 if (count == 3) {
640 /* Rx is hung for more than 500ms. Reset it */
641 ath_dbg(common, ATH_DBG_RESET,
642 "Possible RX hang, resetting");
f6b4e4d4 643 spin_lock_bh(&sc->sc_pcu_lock);
b84628eb 644 ath_reset(sc, true);
f6b4e4d4 645 spin_unlock_bh(&sc->sc_pcu_lock);
b84628eb
SB
646 count = 0;
647 }
648 } else
649 count = 0;
650}
651
9eab61c2
SB
652void ath_hw_pll_work(struct work_struct *work)
653{
654 struct ath_softc *sc = container_of(work, struct ath_softc,
655 hw_pll_work.work);
b84628eb 656 u32 pll_sqsum;
9eab61c2
SB
657
658 if (AR_SREV_9485(sc->sc_ah)) {
b84628eb
SB
659
660 ath9k_ps_wakeup(sc);
661 pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah);
662 ath9k_ps_restore(sc);
663
664 ath_hw_pll_rx_hang_check(sc, pll_sqsum);
9eab61c2
SB
665
666 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5);
667 }
668}
669
670
55624204 671void ath9k_tasklet(unsigned long data)
ff37e337
S
672{
673 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 674 struct ath_hw *ah = sc->sc_ah;
c46917bb 675 struct ath_common *common = ath9k_hw_common(ah);
af03abec 676
17d7904d 677 u32 status = sc->intrstatus;
b5c80475 678 u32 rxmask;
ff37e337 679
a4d86d95
RM
680 if ((status & ATH9K_INT_FATAL) ||
681 (status & ATH9K_INT_BB_WATCHDOG)) {
f6b4e4d4 682 spin_lock(&sc->sc_pcu_lock);
fac6b6a0 683 ath_reset(sc, true);
f6b4e4d4 684 spin_unlock(&sc->sc_pcu_lock);
ff37e337 685 return;
063d8be3 686 }
ff37e337 687
783cd01e 688 ath9k_ps_wakeup(sc);
52671e43 689 spin_lock(&sc->sc_pcu_lock);
6a6733f2 690
8b3f4616
FF
691 /*
692 * Only run the baseband hang check if beacons stop working in AP or
693 * IBSS mode, because it has a high false positive rate. For station
694 * mode it should not be necessary, since the upper layers will detect
695 * this through a beacon miss automatically and the following channel
696 * change will trigger a hardware reset anyway
697 */
698 if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 &&
699 !ath9k_hw_check_alive(ah))
347809fc
FF
700 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
701
4105f807
RM
702 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
703 /*
704 * TSF sync does not look correct; remain awake to sync with
705 * the next Beacon.
706 */
707 ath_dbg(common, ATH_DBG_PS,
708 "TSFOOR - Sync with next Beacon\n");
709 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC |
710 PS_TSFOOR_SYNC;
711 }
712
b5c80475
FF
713 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
714 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
715 ATH9K_INT_RXORN);
716 else
717 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
718
719 if (status & rxmask) {
b5c80475
FF
720 /* Check for high priority Rx first */
721 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
722 (status & ATH9K_INT_RXHP))
723 ath_rx_tasklet(sc, 0, true);
724
725 ath_rx_tasklet(sc, 0, false);
ff37e337
S
726 }
727
e5003249
VT
728 if (status & ATH9K_INT_TX) {
729 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
730 ath_tx_edma_tasklet(sc);
731 else
732 ath_tx_tasklet(sc);
733 }
063d8be3 734
766ec4a9 735 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT
736 if (status & ATH9K_INT_GENTIMER)
737 ath_gen_timer_isr(sc->sc_ah);
738
ff37e337 739 /* re-enable hardware interrupt */
4df3071e 740 ath9k_hw_enable_interrupts(ah);
6a6733f2 741
52671e43 742 spin_unlock(&sc->sc_pcu_lock);
153e080d 743 ath9k_ps_restore(sc);
ff37e337
S
744}
745
6baff7f9 746irqreturn_t ath_isr(int irq, void *dev)
ff37e337 747{
063d8be3
S
748#define SCHED_INTR ( \
749 ATH9K_INT_FATAL | \
a4d86d95 750 ATH9K_INT_BB_WATCHDOG | \
063d8be3
S
751 ATH9K_INT_RXORN | \
752 ATH9K_INT_RXEOL | \
753 ATH9K_INT_RX | \
b5c80475
FF
754 ATH9K_INT_RXLP | \
755 ATH9K_INT_RXHP | \
063d8be3
S
756 ATH9K_INT_TX | \
757 ATH9K_INT_BMISS | \
758 ATH9K_INT_CST | \
ebb8e1d7
VT
759 ATH9K_INT_TSFOOR | \
760 ATH9K_INT_GENTIMER)
063d8be3 761
ff37e337 762 struct ath_softc *sc = dev;
cbe61d8a 763 struct ath_hw *ah = sc->sc_ah;
b5bfc568 764 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
765 enum ath9k_int status;
766 bool sched = false;
767
063d8be3
S
768 /*
769 * The hardware is not ready/present, don't
770 * touch anything. Note this can happen early
771 * on if the IRQ is shared.
772 */
773 if (sc->sc_flags & SC_OP_INVALID)
774 return IRQ_NONE;
ff37e337 775
063d8be3
S
776
777 /* shared irq, not for us */
778
153e080d 779 if (!ath9k_hw_intrpend(ah))
063d8be3 780 return IRQ_NONE;
063d8be3
S
781
782 /*
783 * Figure out the reason(s) for the interrupt. Note
784 * that the hal returns a pseudo-ISR that may include
785 * bits we haven't explicitly enabled so we mask the
786 * value to insure we only process bits we requested.
787 */
788 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 789 status &= ah->imask; /* discard unasked-for bits */
ff37e337 790
063d8be3
S
791 /*
792 * If there are no status bits set, then this interrupt was not
793 * for me (should have been caught above).
794 */
153e080d 795 if (!status)
063d8be3 796 return IRQ_NONE;
ff37e337 797
063d8be3
S
798 /* Cache the status */
799 sc->intrstatus = status;
800
801 if (status & SCHED_INTR)
802 sched = true;
803
804 /*
805 * If a FATAL or RXORN interrupt is received, we have to reset the
806 * chip immediately.
807 */
b5c80475
FF
808 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
809 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S
810 goto chip_reset;
811
08578b8f
LR
812 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
813 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF
814
815 spin_lock(&common->cc_lock);
816 ath_hw_cycle_counters_update(common);
08578b8f 817 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF
818 spin_unlock(&common->cc_lock);
819
08578b8f
LR
820 goto chip_reset;
821 }
822
063d8be3
S
823 if (status & ATH9K_INT_SWBA)
824 tasklet_schedule(&sc->bcon_tasklet);
825
826 if (status & ATH9K_INT_TXURN)
827 ath9k_hw_updatetxtriglevel(ah, true);
828
b5c80475
FF
829 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
830 if (status & ATH9K_INT_RXEOL) {
831 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
832 ath9k_hw_set_interrupts(ah, ah->imask);
833 }
834 }
835
063d8be3 836 if (status & ATH9K_INT_MIB) {
ff37e337 837 /*
063d8be3
S
838 * Disable interrupts until we service the MIB
839 * interrupt; otherwise it will continue to
840 * fire.
ff37e337 841 */
4df3071e 842 ath9k_hw_disable_interrupts(ah);
063d8be3
S
843 /*
844 * Let the hal handle the event. We assume
845 * it will clear whatever condition caused
846 * the interrupt.
847 */
88eac2da 848 spin_lock(&common->cc_lock);
bfc472bb 849 ath9k_hw_proc_mib_event(ah);
88eac2da 850 spin_unlock(&common->cc_lock);
4df3071e 851 ath9k_hw_enable_interrupts(ah);
063d8be3 852 }
ff37e337 853
153e080d
VT
854 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
855 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR
856 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
857 goto chip_reset;
063d8be3
S
858 /* Clear RxAbort bit so that we can
859 * receive frames */
9ecdef4b 860 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 861 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 862 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 863 }
063d8be3
S
864
865chip_reset:
ff37e337 866
817e11de
S
867 ath_debug_stat_interrupt(sc, status);
868
ff37e337 869 if (sched) {
4df3071e
FF
870 /* turn off every interrupt */
871 ath9k_hw_disable_interrupts(ah);
ff37e337
S
872 tasklet_schedule(&sc->intr_tq);
873 }
874
875 return IRQ_HANDLED;
063d8be3
S
876
877#undef SCHED_INTR
ff37e337
S
878}
879
5595f119 880static void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 881{
cbe61d8a 882 struct ath_hw *ah = sc->sc_ah;
c46917bb 883 struct ath_common *common = ath9k_hw_common(ah);
68a89116 884 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 885 int r;
500c064d 886
3cbb5dd7 887 ath9k_ps_wakeup(sc);
6a6733f2
LR
888 spin_lock_bh(&sc->sc_pcu_lock);
889
93b1b37f 890 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 891
159cd468 892 if (!ah->curchan)
c344c9cb 893 ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah);
159cd468 894
20bd2a09 895 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 896 if (r) {
3800276a
JP
897 ath_err(common,
898 "Unable to reset channel (%u MHz), reset status %d\n",
899 channel->center_freq, r);
500c064d 900 }
500c064d 901
5048e8c3
RM
902 ath9k_cmn_update_txpow(ah, sc->curtxpow,
903 sc->config.txpowlimit, &sc->curtxpow);
500c064d 904 if (ath_startrecv(sc) != 0) {
3800276a 905 ath_err(common, "Unable to restart recv logic\n");
c2731b81 906 goto out;
500c064d 907 }
500c064d 908 if (sc->sc_flags & SC_OP_BEACONS)
99e4d43a 909 ath_set_beacon(sc); /* restart beacons */
500c064d
VT
910
911 /* Re-Enable interrupts */
3069168c 912 ath9k_hw_set_interrupts(ah, ah->imask);
500c064d
VT
913
914 /* Enable LED */
08fc5c1b 915 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 916 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 917 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 918
68a89116 919 ieee80211_wake_queues(hw);
7e3514fd
VN
920 ieee80211_queue_delayed_work(hw, &sc->hw_pll_work, HZ/2);
921
c2731b81 922out:
6a6733f2
LR
923 spin_unlock_bh(&sc->sc_pcu_lock);
924
3cbb5dd7 925 ath9k_ps_restore(sc);
500c064d
VT
926}
927
68a89116 928void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 929{
cbe61d8a 930 struct ath_hw *ah = sc->sc_ah;
68a89116 931 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 932 int r;
500c064d 933
3cbb5dd7 934 ath9k_ps_wakeup(sc);
7e3514fd
VN
935 cancel_delayed_work_sync(&sc->hw_pll_work);
936
6a6733f2
LR
937 spin_lock_bh(&sc->sc_pcu_lock);
938
68a89116 939 ieee80211_stop_queues(hw);
500c064d 940
982723df
VN
941 /*
942 * Keep the LED on when the radio is disabled
943 * during idle unassociated state.
944 */
945 if (!sc->ps_idle) {
946 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
947 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
948 }
500c064d
VT
949
950 /* Disable interrupts */
4df3071e 951 ath9k_hw_disable_interrupts(ah);
500c064d 952
043a0405 953 ath_drain_all_txq(sc, false); /* clear pending tx frames */
5e848f78 954
500c064d
VT
955 ath_stoprecv(sc); /* turn off frame recv */
956 ath_flushrecv(sc); /* flush recv queue */
957
159cd468 958 if (!ah->curchan)
c344c9cb 959 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
159cd468 960
20bd2a09 961 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 962 if (r) {
3800276a
JP
963 ath_err(ath9k_hw_common(sc->sc_ah),
964 "Unable to reset channel (%u MHz), reset status %d\n",
965 channel->center_freq, r);
500c064d 966 }
500c064d
VT
967
968 ath9k_hw_phy_disable(ah);
5e848f78 969
93b1b37f 970 ath9k_hw_configpcipowersave(ah, 1, 1);
6a6733f2
LR
971
972 spin_unlock_bh(&sc->sc_pcu_lock);
3cbb5dd7 973 ath9k_ps_restore(sc);
500c064d
VT
974}
975
ff37e337
S
976int ath_reset(struct ath_softc *sc, bool retry_tx)
977{
cbe61d8a 978 struct ath_hw *ah = sc->sc_ah;
c46917bb 979 struct ath_common *common = ath9k_hw_common(ah);
030bb495 980 struct ieee80211_hw *hw = sc->hw;
ae8d2858 981 int r;
ff37e337 982
cb8d61de
FF
983 sc->hw_busy_count = 0;
984
2ab81d4a 985 /* Stop ANI */
05c0be2f 986
2ab81d4a
S
987 del_timer_sync(&common->ani.timer);
988
783cd01e 989 ath9k_ps_wakeup(sc);
6a6733f2 990
cc9c378a
S
991 ieee80211_stop_queues(hw);
992
4df3071e 993 ath9k_hw_disable_interrupts(ah);
043a0405 994 ath_drain_all_txq(sc, retry_tx);
5e848f78 995
ff37e337
S
996 ath_stoprecv(sc);
997 ath_flushrecv(sc);
998
20bd2a09 999 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
ae8d2858 1000 if (r)
3800276a
JP
1001 ath_err(common,
1002 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S
1003
1004 if (ath_startrecv(sc) != 0)
3800276a 1005 ath_err(common, "Unable to start recv logic\n");
ff37e337
S
1006
1007 /*
1008 * We may be doing a reset in response to a request
1009 * that changes the channel so update any state that
1010 * might change as a result.
1011 */
5048e8c3
RM
1012 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1013 sc->config.txpowlimit, &sc->curtxpow);
ff37e337 1014
52b8ac92 1015 if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
99e4d43a 1016 ath_set_beacon(sc); /* restart beacons */
ff37e337 1017
3069168c 1018 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337
S
1019
1020 if (retry_tx) {
1021 int i;
1022 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1023 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
1024 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1025 ath_txq_schedule(sc, &sc->tx.txq[i]);
1026 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
1027 }
1028 }
1029 }
1030
cc9c378a
S
1031 ieee80211_wake_queues(hw);
1032
2ab81d4a 1033 /* Start ANI */
05c0be2f
MSS
1034 if (!common->disable_ani)
1035 ath_start_ani(common);
1036
783cd01e 1037 ath9k_ps_restore(sc);
2ab81d4a 1038
ae8d2858 1039 return r;
ff37e337
S
1040}
1041
ff37e337
S
1042/**********************/
1043/* mac80211 callbacks */
1044/**********************/
1045
8feceb67 1046static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1047{
9ac58615 1048 struct ath_softc *sc = hw->priv;
af03abec 1049 struct ath_hw *ah = sc->sc_ah;
c46917bb 1050 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1051 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1052 struct ath9k_channel *init_channel;
82880a7c 1053 int r;
f078f209 1054
226afe68
JP
1055 ath_dbg(common, ATH_DBG_CONFIG,
1056 "Starting driver with initial channel: %d MHz\n",
1057 curchan->center_freq);
f078f209 1058
f62d816f
FF
1059 ath9k_ps_wakeup(sc);
1060
141b38b6
S
1061 mutex_lock(&sc->mutex);
1062
8feceb67 1063 /* setup initial channel */
82880a7c 1064 sc->chan_idx = curchan->hw_value;
f078f209 1065
c344c9cb 1066 init_channel = ath9k_cmn_get_curchannel(hw, ah);
ff37e337
S
1067
1068 /* Reset SERDES registers */
af03abec 1069 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S
1070
1071 /*
1072 * The basic interface to setting the hardware in a good
1073 * state is ``reset''. On return the hardware is known to
1074 * be powered up and with interrupts disabled. This must
1075 * be followed by initialization of the appropriate bits
1076 * and then setup of the interrupt mask.
1077 */
4bdd1e97 1078 spin_lock_bh(&sc->sc_pcu_lock);
20bd2a09 1079 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 1080 if (r) {
3800276a
JP
1081 ath_err(common,
1082 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
1083 r, curchan->center_freq);
4bdd1e97 1084 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1085 goto mutex_unlock;
ff37e337 1086 }
ff37e337
S
1087
1088 /*
1089 * This is needed only to setup initial state
1090 * but it's best done after a reset.
1091 */
5048e8c3
RM
1092 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1093 sc->config.txpowlimit, &sc->curtxpow);
8feceb67 1094
ff37e337
S
1095 /*
1096 * Setup the hardware after reset:
1097 * The receive engine is set going.
1098 * Frame transmit is handled entirely
1099 * in the frame output path; there's nothing to do
1100 * here except setup the interrupt mask.
1101 */
1102 if (ath_startrecv(sc) != 0) {
3800276a 1103 ath_err(common, "Unable to start recv logic\n");
141b38b6 1104 r = -EIO;
4bdd1e97 1105 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 1106 goto mutex_unlock;
f078f209 1107 }
4bdd1e97 1108 spin_unlock_bh(&sc->sc_pcu_lock);
8feceb67 1109
ff37e337 1110 /* Setup our intr mask. */
b5c80475
FF
1111 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1112 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1113 ATH9K_INT_GLOBAL;
1114
1115 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR
1116 ah->imask |= ATH9K_INT_RXHP |
1117 ATH9K_INT_RXLP |
1118 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF
1119 else
1120 ah->imask |= ATH9K_INT_RX;
ff37e337 1121
364734fa 1122 ah->imask |= ATH9K_INT_GTT;
ff37e337 1123
af03abec 1124 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 1125 ah->imask |= ATH9K_INT_CST;
ff37e337 1126
ff37e337 1127 sc->sc_flags &= ~SC_OP_INVALID;
5f841b41 1128 sc->sc_ah->is_monitoring = false;
ff37e337
S
1129
1130 /* Disable BMISS interrupt when we're not associated */
3069168c
PR
1131 ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1132 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337 1133
bce048d7 1134 ieee80211_wake_queues(hw);
ff37e337 1135
42935eca 1136 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 1137
766ec4a9
LR
1138 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1139 !ah->btcoex_hw.enabled) {
5e197292
LR
1140 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1141 AR_STOMP_LOW_WLAN_WGHT);
af03abec 1142 ath9k_hw_btcoex_enable(ah);
f985ad12 1143
5bb12791
LR
1144 if (common->bus_ops->bt_coex_prep)
1145 common->bus_ops->bt_coex_prep(common);
766ec4a9 1146 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1147 ath9k_btcoex_timer_resume(sc);
1773912b
VT
1148 }
1149
8060e169
VT
1150 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
1151 common->bus_ops->extn_synch_en(common);
1152
141b38b6
S
1153mutex_unlock:
1154 mutex_unlock(&sc->mutex);
1155
f62d816f
FF
1156 ath9k_ps_restore(sc);
1157
ae8d2858 1158 return r;
f078f209
LR
1159}
1160
7bb45683 1161static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
f078f209 1162{
9ac58615 1163 struct ath_softc *sc = hw->priv;
c46917bb 1164 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 1165 struct ath_tx_control txctl;
1bc14880 1166 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
528f0c6b 1167
96148326 1168 if (sc->ps_enabled) {
dc8c4585
JM
1169 /*
1170 * mac80211 does not set PM field for normal data frames, so we
1171 * need to update that based on the current PS mode.
1172 */
1173 if (ieee80211_is_data(hdr->frame_control) &&
1174 !ieee80211_is_nullfunc(hdr->frame_control) &&
1175 !ieee80211_has_pm(hdr->frame_control)) {
226afe68
JP
1176 ath_dbg(common, ATH_DBG_PS,
1177 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM
1178 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1179 }
1180 }
1181
9a23f9ca
JM
1182 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1183 /*
1184 * We are using PS-Poll and mac80211 can request TX while in
1185 * power save mode. Need to wake up hardware for the TX to be
1186 * completed and if needed, also for RX of buffered frames.
1187 */
9a23f9ca 1188 ath9k_ps_wakeup(sc);
fdf76622
VT
1189 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1190 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 1191 if (ieee80211_is_pspoll(hdr->frame_control)) {
226afe68
JP
1192 ath_dbg(common, ATH_DBG_PS,
1193 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 1194 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 1195 } else {
226afe68
JP
1196 ath_dbg(common, ATH_DBG_PS,
1197 "Wake up to complete TX\n");
1b04b930 1198 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
1199 }
1200 /*
1201 * The actual restore operation will happen only after
1202 * the sc_flags bit is cleared. We are just dropping
1203 * the ps_usecount here.
1204 */
1205 ath9k_ps_restore(sc);
1206 }
1207
528f0c6b 1208 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 1209 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
528f0c6b 1210
226afe68 1211 ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1212
c52f33d0 1213 if (ath_tx_start(hw, skb, &txctl) != 0) {
226afe68 1214 ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1215 goto exit;
8feceb67
VT
1216 }
1217
7bb45683 1218 return;
528f0c6b
S
1219exit:
1220 dev_kfree_skb_any(skb);
f078f209
LR
1221}
1222
8feceb67 1223static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 1224{
9ac58615 1225 struct ath_softc *sc = hw->priv;
af03abec 1226 struct ath_hw *ah = sc->sc_ah;
c46917bb 1227 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1228
4c483817
S
1229 mutex_lock(&sc->mutex);
1230
c94dbff7 1231 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 1232 cancel_delayed_work_sync(&sc->hw_pll_work);
9f42c2b6 1233 cancel_work_sync(&sc->paprd_work);
347809fc 1234 cancel_work_sync(&sc->hw_check_work);
c94dbff7 1235
9c84b797 1236 if (sc->sc_flags & SC_OP_INVALID) {
226afe68 1237 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
4c483817 1238 mutex_unlock(&sc->mutex);
9c84b797
S
1239 return;
1240 }
8feceb67 1241
3867cf6a
S
1242 /* Ensure HW is awake when we try to shut it down. */
1243 ath9k_ps_wakeup(sc);
1244
766ec4a9 1245 if (ah->btcoex_hw.enabled) {
af03abec 1246 ath9k_hw_btcoex_disable(ah);
766ec4a9 1247 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1248 ath9k_btcoex_timer_pause(sc);
1773912b
VT
1249 }
1250
6a6733f2
LR
1251 spin_lock_bh(&sc->sc_pcu_lock);
1252
203043f5
SG
1253 /* prevent tasklets to enable interrupts once we disable them */
1254 ah->imask &= ~ATH9K_INT_GLOBAL;
1255
ff37e337
S
1256 /* make sure h/w will not generate any interrupt
1257 * before setting the invalid flag. */
4df3071e 1258 ath9k_hw_disable_interrupts(ah);
ff37e337
S
1259
1260 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 1261 ath_drain_all_txq(sc, false);
ff37e337 1262 ath_stoprecv(sc);
af03abec 1263 ath9k_hw_phy_disable(ah);
6a6733f2 1264 } else
b77f483f 1265 sc->rx.rxlink = NULL;
ff37e337 1266
0d95521e
FF
1267 if (sc->rx.frag) {
1268 dev_kfree_skb_any(sc->rx.frag);
1269 sc->rx.frag = NULL;
1270 }
1271
ff37e337 1272 /* disable HAL and put h/w to sleep */
af03abec 1273 ath9k_hw_disable(ah);
6a6733f2
LR
1274
1275 spin_unlock_bh(&sc->sc_pcu_lock);
1276
203043f5
SG
1277 /* we can now sync irq and kill any running tasklets, since we already
1278 * disabled interrupts and not holding a spin lock */
1279 synchronize_irq(sc->irq);
1280 tasklet_kill(&sc->intr_tq);
1281 tasklet_kill(&sc->bcon_tasklet);
1282
3867cf6a
S
1283 ath9k_ps_restore(sc);
1284
a08e7ade
LR
1285 sc->ps_idle = true;
1286 ath_radio_disable(sc, hw);
ff37e337
S
1287
1288 sc->sc_flags |= SC_OP_INVALID;
500c064d 1289
141b38b6
S
1290 mutex_unlock(&sc->mutex);
1291
226afe68 1292 ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR
1293}
1294
4801416c
BG
1295bool ath9k_uses_beacons(int type)
1296{
1297 switch (type) {
1298 case NL80211_IFTYPE_AP:
1299 case NL80211_IFTYPE_ADHOC:
1300 case NL80211_IFTYPE_MESH_POINT:
1301 return true;
1302 default:
1303 return false;
1304 }
1305}
1306
1307static void ath9k_reclaim_beacon(struct ath_softc *sc,
1308 struct ieee80211_vif *vif)
f078f209 1309{
1ed32e4f 1310 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67 1311
014cf3bb 1312 ath9k_set_beaconing_status(sc, false);
4801416c 1313 ath_beacon_return(sc, avp);
014cf3bb 1314 ath9k_set_beaconing_status(sc, true);
4801416c 1315 sc->sc_flags &= ~SC_OP_BEACONS;
4801416c
BG
1316}
1317
1318static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1319{
1320 struct ath9k_vif_iter_data *iter_data = data;
1321 int i;
1322
1323 if (iter_data->hw_macaddr)
1324 for (i = 0; i < ETH_ALEN; i++)
1325 iter_data->mask[i] &=
1326 ~(iter_data->hw_macaddr[i] ^ mac[i]);
141b38b6 1327
1ed32e4f 1328 switch (vif->type) {
4801416c
BG
1329 case NL80211_IFTYPE_AP:
1330 iter_data->naps++;
f078f209 1331 break;
4801416c
BG
1332 case NL80211_IFTYPE_STATION:
1333 iter_data->nstations++;
e51f3eff 1334 break;
05c914fe 1335 case NL80211_IFTYPE_ADHOC:
4801416c
BG
1336 iter_data->nadhocs++;
1337 break;
9cb5412b 1338 case NL80211_IFTYPE_MESH_POINT:
4801416c
BG
1339 iter_data->nmeshes++;
1340 break;
1341 case NL80211_IFTYPE_WDS:
1342 iter_data->nwds++;
f078f209
LR
1343 break;
1344 default:
4801416c
BG
1345 iter_data->nothers++;
1346 break;
f078f209 1347 }
4801416c 1348}
f078f209 1349
4801416c
BG
1350/* Called with sc->mutex held. */
1351void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1352 struct ieee80211_vif *vif,
1353 struct ath9k_vif_iter_data *iter_data)
1354{
9ac58615 1355 struct ath_softc *sc = hw->priv;
4801416c
BG
1356 struct ath_hw *ah = sc->sc_ah;
1357 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1358
4801416c
BG
1359 /*
1360 * Use the hardware MAC address as reference, the hardware uses it
1361 * together with the BSSID mask when matching addresses.
1362 */
1363 memset(iter_data, 0, sizeof(*iter_data));
1364 iter_data->hw_macaddr = common->macaddr;
1365 memset(&iter_data->mask, 0xff, ETH_ALEN);
5640b08e 1366
4801416c
BG
1367 if (vif)
1368 ath9k_vif_iter(iter_data, vif->addr, vif);
1369
1370 /* Get list of all active MAC addresses */
4801416c
BG
1371 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
1372 iter_data);
4801416c 1373}
8ca21f01 1374
4801416c
BG
1375/* Called with sc->mutex held. */
1376static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1377 struct ieee80211_vif *vif)
1378{
9ac58615 1379 struct ath_softc *sc = hw->priv;
4801416c
BG
1380 struct ath_hw *ah = sc->sc_ah;
1381 struct ath_common *common = ath9k_hw_common(ah);
1382 struct ath9k_vif_iter_data iter_data;
8ca21f01 1383
4801416c 1384 ath9k_calculate_iter_data(hw, vif, &iter_data);
2c3db3d5 1385
4801416c
BG
1386 /* Set BSSID mask. */
1387 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1388 ath_hw_setbssidmask(common);
1389
1390 /* Set op-mode & TSF */
1391 if (iter_data.naps > 0) {
3069168c 1392 ath9k_hw_set_tsfadjust(ah, 1);
b238e90e 1393 sc->sc_flags |= SC_OP_TSF_RESET;
4801416c
BG
1394 ah->opmode = NL80211_IFTYPE_AP;
1395 } else {
1396 ath9k_hw_set_tsfadjust(ah, 0);
1397 sc->sc_flags &= ~SC_OP_TSF_RESET;
5640b08e 1398
fd5999cf
JC
1399 if (iter_data.nmeshes)
1400 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1401 else if (iter_data.nwds)
4801416c
BG
1402 ah->opmode = NL80211_IFTYPE_AP;
1403 else if (iter_data.nadhocs)
1404 ah->opmode = NL80211_IFTYPE_ADHOC;
1405 else
1406 ah->opmode = NL80211_IFTYPE_STATION;
1407 }
5640b08e 1408
4e30ffa2
VN
1409 /*
1410 * Enable MIB interrupts when there are hardware phy counters.
4e30ffa2 1411 */
4801416c 1412 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) {
3448f912
LR
1413 if (ah->config.enable_ani)
1414 ah->imask |= ATH9K_INT_MIB;
3069168c 1415 ah->imask |= ATH9K_INT_TSFOOR;
4801416c
BG
1416 } else {
1417 ah->imask &= ~ATH9K_INT_MIB;
1418 ah->imask &= ~ATH9K_INT_TSFOOR;
4af9cf4f
S
1419 }
1420
3069168c 1421 ath9k_hw_set_interrupts(ah, ah->imask);
4e30ffa2 1422
4801416c 1423 /* Set up ANI */
2e5ef459 1424 if (iter_data.naps > 0) {
729da390 1425 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
05c0be2f
MSS
1426
1427 if (!common->disable_ani) {
1428 sc->sc_flags |= SC_OP_ANI_RUN;
1429 ath_start_ani(common);
1430 }
1431
f60c49b6
RM
1432 } else {
1433 sc->sc_flags &= ~SC_OP_ANI_RUN;
1434 del_timer_sync(&common->ani.timer);
6c3118e2 1435 }
4801416c 1436}
6f255425 1437
4801416c
BG
1438/* Called with sc->mutex held, vif counts set up properly. */
1439static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw,
1440 struct ieee80211_vif *vif)
1441{
9ac58615 1442 struct ath_softc *sc = hw->priv;
4801416c
BG
1443
1444 ath9k_calculate_summary_state(hw, vif);
1445
1446 if (ath9k_uses_beacons(vif->type)) {
1447 int error;
4801416c
BG
1448 /* This may fail because upper levels do not have beacons
1449 * properly configured yet. That's OK, we assume it
1450 * will be properly configured and then we will be notified
1451 * in the info_changed method and set up beacons properly
1452 * there.
1453 */
014cf3bb 1454 ath9k_set_beaconing_status(sc, false);
9ac58615 1455 error = ath_beacon_alloc(sc, vif);
391bd1c4 1456 if (!error)
4801416c 1457 ath_beacon_config(sc, vif);
014cf3bb 1458 ath9k_set_beaconing_status(sc, true);
4801416c 1459 }
f078f209
LR
1460}
1461
4801416c
BG
1462
1463static int ath9k_add_interface(struct ieee80211_hw *hw,
1464 struct ieee80211_vif *vif)
6b3b991d 1465{
9ac58615 1466 struct ath_softc *sc = hw->priv;
4801416c
BG
1467 struct ath_hw *ah = sc->sc_ah;
1468 struct ath_common *common = ath9k_hw_common(ah);
4801416c 1469 int ret = 0;
6b3b991d 1470
96f372c9 1471 ath9k_ps_wakeup(sc);
4801416c 1472 mutex_lock(&sc->mutex);
6b3b991d 1473
4801416c
BG
1474 switch (vif->type) {
1475 case NL80211_IFTYPE_STATION:
1476 case NL80211_IFTYPE_WDS:
1477 case NL80211_IFTYPE_ADHOC:
1478 case NL80211_IFTYPE_AP:
1479 case NL80211_IFTYPE_MESH_POINT:
1480 break;
1481 default:
1482 ath_err(common, "Interface type %d not yet supported\n",
1483 vif->type);
1484 ret = -EOPNOTSUPP;
1485 goto out;
1486 }
6b3b991d 1487
4801416c
BG
1488 if (ath9k_uses_beacons(vif->type)) {
1489 if (sc->nbcnvifs >= ATH_BCBUF) {
1490 ath_err(common, "Not enough beacon buffers when adding"
1491 " new interface of type: %i\n",
1492 vif->type);
1493 ret = -ENOBUFS;
1494 goto out;
1495 }
1496 }
1497
59575d1c
RM
1498 if ((ah->opmode == NL80211_IFTYPE_ADHOC) ||
1499 ((vif->type == NL80211_IFTYPE_ADHOC) &&
1500 sc->nvifs > 0)) {
4801416c
BG
1501 ath_err(common, "Cannot create ADHOC interface when other"
1502 " interfaces already exist.\n");
1503 ret = -EINVAL;
1504 goto out;
6b3b991d 1505 }
4801416c
BG
1506
1507 ath_dbg(common, ATH_DBG_CONFIG,
1508 "Attach a VIF of type: %d\n", vif->type);
1509
4801416c
BG
1510 sc->nvifs++;
1511
1512 ath9k_do_vif_add_setup(hw, vif);
1513out:
1514 mutex_unlock(&sc->mutex);
96f372c9 1515 ath9k_ps_restore(sc);
4801416c 1516 return ret;
6b3b991d
RM
1517}
1518
1519static int ath9k_change_interface(struct ieee80211_hw *hw,
1520 struct ieee80211_vif *vif,
1521 enum nl80211_iftype new_type,
1522 bool p2p)
1523{
9ac58615 1524 struct ath_softc *sc = hw->priv;
6b3b991d 1525 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
6dab55bf 1526 int ret = 0;
6b3b991d
RM
1527
1528 ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
1529 mutex_lock(&sc->mutex);
96f372c9 1530 ath9k_ps_wakeup(sc);
6b3b991d 1531
4801416c
BG
1532 /* See if new interface type is valid. */
1533 if ((new_type == NL80211_IFTYPE_ADHOC) &&
1534 (sc->nvifs > 1)) {
1535 ath_err(common, "When using ADHOC, it must be the only"
1536 " interface.\n");
1537 ret = -EINVAL;
1538 goto out;
1539 }
1540
1541 if (ath9k_uses_beacons(new_type) &&
1542 !ath9k_uses_beacons(vif->type)) {
6b3b991d
RM
1543 if (sc->nbcnvifs >= ATH_BCBUF) {
1544 ath_err(common, "No beacon slot available\n");
6dab55bf
DC
1545 ret = -ENOBUFS;
1546 goto out;
6b3b991d 1547 }
6b3b991d 1548 }
4801416c
BG
1549
1550 /* Clean up old vif stuff */
1551 if (ath9k_uses_beacons(vif->type))
1552 ath9k_reclaim_beacon(sc, vif);
1553
1554 /* Add new settings */
6b3b991d
RM
1555 vif->type = new_type;
1556 vif->p2p = p2p;
1557
4801416c 1558 ath9k_do_vif_add_setup(hw, vif);
6dab55bf 1559out:
96f372c9 1560 ath9k_ps_restore(sc);
6b3b991d 1561 mutex_unlock(&sc->mutex);
6dab55bf 1562 return ret;
6b3b991d
RM
1563}
1564
8feceb67 1565static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1566 struct ieee80211_vif *vif)
f078f209 1567{
9ac58615 1568 struct ath_softc *sc = hw->priv;
c46917bb 1569 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f078f209 1570
226afe68 1571 ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 1572
96f372c9 1573 ath9k_ps_wakeup(sc);
141b38b6
S
1574 mutex_lock(&sc->mutex);
1575
4801416c 1576 sc->nvifs--;
580f0b8a 1577
8feceb67 1578 /* Reclaim beacon resources */
4801416c 1579 if (ath9k_uses_beacons(vif->type))
6b3b991d 1580 ath9k_reclaim_beacon(sc, vif);
2c3db3d5 1581
4801416c 1582 ath9k_calculate_summary_state(hw, NULL);
141b38b6
S
1583
1584 mutex_unlock(&sc->mutex);
96f372c9 1585 ath9k_ps_restore(sc);
f078f209
LR
1586}
1587
fbab7390 1588static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1589{
3069168c
PR
1590 struct ath_hw *ah = sc->sc_ah;
1591
3f7c5c10 1592 sc->ps_enabled = true;
3069168c
PR
1593 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1594 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1595 ah->imask |= ATH9K_INT_TIM_TIMER;
1596 ath9k_hw_set_interrupts(ah, ah->imask);
3f7c5c10 1597 }
fdf76622 1598 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1599 }
3f7c5c10
SB
1600}
1601
845d708e
SB
1602static void ath9k_disable_ps(struct ath_softc *sc)
1603{
1604 struct ath_hw *ah = sc->sc_ah;
1605
1606 sc->ps_enabled = false;
1607 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1608 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1609 ath9k_hw_setrxabort(ah, 0);
1610 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1611 PS_WAIT_FOR_CAB |
1612 PS_WAIT_FOR_PSPOLL_DATA |
1613 PS_WAIT_FOR_TX_ACK);
1614 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1615 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1616 ath9k_hw_set_interrupts(ah, ah->imask);
1617 }
1618 }
1619
1620}
1621
e8975581 1622static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1623{
9ac58615 1624 struct ath_softc *sc = hw->priv;
3430098a
FF
1625 struct ath_hw *ah = sc->sc_ah;
1626 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1627 struct ieee80211_conf *conf = &hw->conf;
7545daf4 1628 bool disable_radio = false;
f078f209 1629
aa33de09 1630 mutex_lock(&sc->mutex);
141b38b6 1631
194b7c13
LR
1632 /*
1633 * Leave this as the first check because we need to turn on the
1634 * radio if it was disabled before prior to processing the rest
1635 * of the changes. Likewise we must only disable the radio towards
1636 * the end.
1637 */
64839170 1638 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4
FF
1639 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1640 if (!sc->ps_idle) {
68a89116 1641 ath_radio_enable(sc, hw);
226afe68
JP
1642 ath_dbg(common, ATH_DBG_CONFIG,
1643 "not-idle: enabling radio\n");
7545daf4
FF
1644 } else {
1645 disable_radio = true;
64839170
LR
1646 }
1647 }
1648
e7824a50
LR
1649 /*
1650 * We just prepare to enable PS. We have to wait until our AP has
1651 * ACK'd our null data frame to disable RX otherwise we'll ignore
1652 * those ACKs and end up retransmitting the same null data frames.
1653 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1654 */
3cbb5dd7 1655 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR
1656 unsigned long flags;
1657 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB
1658 if (conf->flags & IEEE80211_CONF_PS)
1659 ath9k_enable_ps(sc);
845d708e
SB
1660 else
1661 ath9k_disable_ps(sc);
8ab2cd09 1662 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN
1663 }
1664
199afd9d
S
1665 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1666 if (conf->flags & IEEE80211_CONF_MONITOR) {
226afe68
JP
1667 ath_dbg(common, ATH_DBG_CONFIG,
1668 "Monitor mode is enabled\n");
5f841b41
RM
1669 sc->sc_ah->is_monitoring = true;
1670 } else {
226afe68
JP
1671 ath_dbg(common, ATH_DBG_CONFIG,
1672 "Monitor mode is disabled\n");
5f841b41 1673 sc->sc_ah->is_monitoring = false;
199afd9d
S
1674 }
1675 }
1676
4797938c 1677 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 1678 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1679 int pos = curchan->hw_value;
3430098a
FF
1680 int old_pos = -1;
1681 unsigned long flags;
1682
1683 if (ah->curchan)
1684 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1685
5ee08656
FF
1686 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1687 sc->sc_flags |= SC_OP_OFFCHANNEL;
1688 else
1689 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
0e2dedf9 1690
8c79a610
BG
1691 ath_dbg(common, ATH_DBG_CONFIG,
1692 "Set channel: %d MHz type: %d\n",
1693 curchan->center_freq, conf->channel_type);
f078f209 1694
de87f736
RM
1695 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1696 curchan, conf->channel_type);
e11602b7 1697
3430098a
FF
1698 /* update survey stats for the old channel before switching */
1699 spin_lock_irqsave(&common->cc_lock, flags);
1700 ath_update_survey_stats(sc);
1701 spin_unlock_irqrestore(&common->cc_lock, flags);
1702
1703 /*
1704 * If the operating channel changes, change the survey in-use flags
1705 * along with it.
1706 * Reset the survey data for the new channel, unless we're switching
1707 * back to the operating channel from an off-channel operation.
1708 */
1709 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1710 sc->cur_survey != &sc->survey[pos]) {
1711
1712 if (sc->cur_survey)
1713 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1714
1715 sc->cur_survey = &sc->survey[pos];
1716
1717 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1718 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1719 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1720 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1721 }
1722
0e2dedf9 1723 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
3800276a 1724 ath_err(common, "Unable to set channel\n");
aa33de09 1725 mutex_unlock(&sc->mutex);
e11602b7
S
1726 return -EINVAL;
1727 }
3430098a
FF
1728
1729 /*
1730 * The most recent snapshot of channel->noisefloor for the old
1731 * channel is only available after the hardware reset. Copy it to
1732 * the survey stats now.
1733 */
1734 if (old_pos >= 0)
1735 ath_update_survey_nf(sc, old_pos);
094d05dc 1736 }
f078f209 1737
c9f6a656 1738 if (changed & IEEE80211_CONF_CHANGE_POWER) {
603b3eef
BG
1739 ath_dbg(common, ATH_DBG_CONFIG,
1740 "Set power: %d\n", conf->power_level);
17d7904d 1741 sc->config.txpowlimit = 2 * conf->power_level;
783cd01e 1742 ath9k_ps_wakeup(sc);
5048e8c3
RM
1743 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1744 sc->config.txpowlimit, &sc->curtxpow);
783cd01e 1745 ath9k_ps_restore(sc);
c9f6a656 1746 }
f078f209 1747
64839170 1748 if (disable_radio) {
226afe68 1749 ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
68a89116 1750 ath_radio_disable(sc, hw);
64839170
LR
1751 }
1752
aa33de09 1753 mutex_unlock(&sc->mutex);
141b38b6 1754
f078f209
LR
1755 return 0;
1756}
1757
8feceb67
VT
1758#define SUPPORTED_FILTERS \
1759 (FIF_PROMISC_IN_BSS | \
1760 FIF_ALLMULTI | \
1761 FIF_CONTROL | \
af6a3fc7 1762 FIF_PSPOLL | \
8feceb67
VT
1763 FIF_OTHER_BSS | \
1764 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1765 FIF_PROBE_REQ | \
8feceb67 1766 FIF_FCSFAIL)
c83be688 1767
8feceb67
VT
1768/* FIXME: sc->sc_full_reset ? */
1769static void ath9k_configure_filter(struct ieee80211_hw *hw,
1770 unsigned int changed_flags,
1771 unsigned int *total_flags,
3ac64bee 1772 u64 multicast)
8feceb67 1773{
9ac58615 1774 struct ath_softc *sc = hw->priv;
8feceb67 1775 u32 rfilt;
f078f209 1776
8feceb67
VT
1777 changed_flags &= SUPPORTED_FILTERS;
1778 *total_flags &= SUPPORTED_FILTERS;
f078f209 1779
b77f483f 1780 sc->rx.rxfilter = *total_flags;
aa68aeaa 1781 ath9k_ps_wakeup(sc);
8feceb67
VT
1782 rfilt = ath_calcrxfilter(sc);
1783 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1784 ath9k_ps_restore(sc);
f078f209 1785
226afe68
JP
1786 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1787 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 1788}
f078f209 1789
4ca77860
JB
1790static int ath9k_sta_add(struct ieee80211_hw *hw,
1791 struct ieee80211_vif *vif,
1792 struct ieee80211_sta *sta)
8feceb67 1793{
9ac58615 1794 struct ath_softc *sc = hw->priv;
93ae2dd2
FF
1795 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1796 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1797 struct ieee80211_key_conf ps_key = { };
f078f209 1798
4ca77860 1799 ath_node_attach(sc, sta);
f59a59fe
FF
1800
1801 if (vif->type != NL80211_IFTYPE_AP &&
1802 vif->type != NL80211_IFTYPE_AP_VLAN)
1803 return 0;
1804
93ae2dd2 1805 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
4ca77860
JB
1806
1807 return 0;
1808}
1809
93ae2dd2
FF
1810static void ath9k_del_ps_key(struct ath_softc *sc,
1811 struct ieee80211_vif *vif,
1812 struct ieee80211_sta *sta)
1813{
1814 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1815 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1816 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1817
1818 if (!an->ps_key)
1819 return;
1820
1821 ath_key_delete(common, &ps_key);
1822}
1823
4ca77860
JB
1824static int ath9k_sta_remove(struct ieee80211_hw *hw,
1825 struct ieee80211_vif *vif,
1826 struct ieee80211_sta *sta)
1827{
9ac58615 1828 struct ath_softc *sc = hw->priv;
4ca77860 1829
93ae2dd2 1830 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB
1831 ath_node_detach(sc, sta);
1832
1833 return 0;
f078f209
LR
1834}
1835
5519541d
FF
1836static void ath9k_sta_notify(struct ieee80211_hw *hw,
1837 struct ieee80211_vif *vif,
1838 enum sta_notify_cmd cmd,
1839 struct ieee80211_sta *sta)
1840{
1841 struct ath_softc *sc = hw->priv;
1842 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1843
1844 switch (cmd) {
1845 case STA_NOTIFY_SLEEP:
1846 an->sleeping = true;
1847 if (ath_tx_aggr_sleep(sc, an))
1848 ieee80211_sta_set_tim(sta);
1849 break;
1850 case STA_NOTIFY_AWAKE:
1851 an->sleeping = false;
1852 ath_tx_aggr_wakeup(sc, an);
1853 break;
1854 }
1855}
1856
141b38b6 1857static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 1858 const struct ieee80211_tx_queue_params *params)
f078f209 1859{
9ac58615 1860 struct ath_softc *sc = hw->priv;
c46917bb 1861 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1862 struct ath_txq *txq;
8feceb67 1863 struct ath9k_tx_queue_info qi;
066dae93 1864 int ret = 0;
f078f209 1865
8feceb67
VT
1866 if (queue >= WME_NUM_AC)
1867 return 0;
f078f209 1868
066dae93
FF
1869 txq = sc->tx.txq_map[queue];
1870
96f372c9 1871 ath9k_ps_wakeup(sc);
141b38b6
S
1872 mutex_lock(&sc->mutex);
1873
1ffb0610
S
1874 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1875
8feceb67
VT
1876 qi.tqi_aifs = params->aifs;
1877 qi.tqi_cwmin = params->cw_min;
1878 qi.tqi_cwmax = params->cw_max;
1879 qi.tqi_burstTime = params->txop;
f078f209 1880
226afe68
JP
1881 ath_dbg(common, ATH_DBG_CONFIG,
1882 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1883 queue, txq->axq_qnum, params->aifs, params->cw_min,
1884 params->cw_max, params->txop);
f078f209 1885
066dae93 1886 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1887 if (ret)
3800276a 1888 ath_err(common, "TXQ Update failed\n");
f078f209 1889
94db2936 1890 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
066dae93 1891 if (queue == WME_AC_BE && !ret)
94db2936
VN
1892 ath_beaconq_config(sc);
1893
141b38b6 1894 mutex_unlock(&sc->mutex);
96f372c9 1895 ath9k_ps_restore(sc);
141b38b6 1896
8feceb67
VT
1897 return ret;
1898}
f078f209 1899
8feceb67
VT
1900static int ath9k_set_key(struct ieee80211_hw *hw,
1901 enum set_key_cmd cmd,
dc822b5d
JB
1902 struct ieee80211_vif *vif,
1903 struct ieee80211_sta *sta,
8feceb67
VT
1904 struct ieee80211_key_conf *key)
1905{
9ac58615 1906 struct ath_softc *sc = hw->priv;
c46917bb 1907 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1908 int ret = 0;
f078f209 1909
3e6109c5 1910 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM
1911 return -ENOSPC;
1912
cfdc9a8b
JM
1913 if (vif->type == NL80211_IFTYPE_ADHOC &&
1914 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1915 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1916 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1917 /*
1918 * For now, disable hw crypto for the RSN IBSS group keys. This
1919 * could be optimized in the future to use a modified key cache
1920 * design to support per-STA RX GTK, but until that gets
1921 * implemented, use of software crypto for group addressed
1922 * frames is a acceptable to allow RSN IBSS to be used.
1923 */
1924 return -EOPNOTSUPP;
1925 }
1926
141b38b6 1927 mutex_lock(&sc->mutex);
3cbb5dd7 1928 ath9k_ps_wakeup(sc);
226afe68 1929 ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 1930
8feceb67
VT
1931 switch (cmd) {
1932 case SET_KEY:
93ae2dd2
FF
1933 if (sta)
1934 ath9k_del_ps_key(sc, vif, sta);
1935
040e539e 1936 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1937 if (ret >= 0) {
1938 key->hw_key_idx = ret;
8feceb67
VT
1939 /* push IV and Michael MIC generation to stack */
1940 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1941 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1942 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB
1943 if (sc->sc_ah->sw_mgmt_crypto &&
1944 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 1945 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1946 ret = 0;
8feceb67
VT
1947 }
1948 break;
1949 case DISABLE_KEY:
040e539e 1950 ath_key_delete(common, key);
8feceb67
VT
1951 break;
1952 default:
1953 ret = -EINVAL;
1954 }
f078f209 1955
3cbb5dd7 1956 ath9k_ps_restore(sc);
141b38b6
S
1957 mutex_unlock(&sc->mutex);
1958
8feceb67
VT
1959 return ret;
1960}
4f5ef75b
RM
1961static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1962{
1963 struct ath_softc *sc = data;
1964 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1965 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1966 struct ath_vif *avp = (void *)vif->drv_priv;
1967
2e5ef459
RM
1968 /*
1969 * Skip iteration if primary station vif's bss info
1970 * was not changed
1971 */
1972 if (sc->sc_flags & SC_OP_PRIM_STA_VIF)
1973 return;
1974
1975 if (bss_conf->assoc) {
1976 sc->sc_flags |= SC_OP_PRIM_STA_VIF;
1977 avp->primary_sta_vif = true;
4f5ef75b
RM
1978 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1979 common->curaid = bss_conf->aid;
1980 ath9k_hw_write_associd(sc->sc_ah);
2e5ef459 1981 ath_dbg(common, ATH_DBG_CONFIG,
99e4d43a
RM
1982 "Bss Info ASSOC %d, bssid: %pM\n",
1983 bss_conf->aid, common->curbssid);
2e5ef459
RM
1984 ath_beacon_config(sc, vif);
1985 /*
1986 * Request a re-configuration of Beacon related timers
1987 * on the receipt of the first Beacon frame (i.e.,
1988 * after time sync with the AP).
1989 */
1990 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1991 /* Reset rssi stats */
1992 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1993 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
99e4d43a 1994
05c0be2f
MSS
1995 if (!common->disable_ani) {
1996 sc->sc_flags |= SC_OP_ANI_RUN;
1997 ath_start_ani(common);
1998 }
1999
4f5ef75b
RM
2000 }
2001}
2002
2003static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif)
2004{
2005 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2006 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
2007 struct ath_vif *avp = (void *)vif->drv_priv;
2008
2e5ef459
RM
2009 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
2010 return;
2011
4f5ef75b
RM
2012 /* Reconfigure bss info */
2013 if (avp->primary_sta_vif && !bss_conf->assoc) {
99e4d43a
RM
2014 ath_dbg(common, ATH_DBG_CONFIG,
2015 "Bss Info DISASSOC %d, bssid %pM\n",
2016 common->curaid, common->curbssid);
2017 sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS);
4f5ef75b
RM
2018 avp->primary_sta_vif = false;
2019 memset(common->curbssid, 0, ETH_ALEN);
2020 common->curaid = 0;
2021 }
2022
2023 ieee80211_iterate_active_interfaces_atomic(
2024 sc->hw, ath9k_bss_iter, sc);
2025
2026 /*
2027 * None of station vifs are associated.
2028 * Clear bssid & aid
2029 */
2e5ef459 2030 if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) {
4f5ef75b 2031 ath9k_hw_write_associd(sc->sc_ah);
99e4d43a
RM
2032 /* Stop ANI */
2033 sc->sc_flags &= ~SC_OP_ANI_RUN;
2034 del_timer_sync(&common->ani.timer);
2035 }
4f5ef75b 2036}
f078f209 2037
8feceb67
VT
2038static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2039 struct ieee80211_vif *vif,
2040 struct ieee80211_bss_conf *bss_conf,
2041 u32 changed)
2042{
9ac58615 2043 struct ath_softc *sc = hw->priv;
2d0ddec5 2044 struct ath_hw *ah = sc->sc_ah;
1510718d 2045 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 2046 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 2047 int slottime;
c6089ccc 2048 int error;
f078f209 2049
96f372c9 2050 ath9k_ps_wakeup(sc);
141b38b6
S
2051 mutex_lock(&sc->mutex);
2052
c6089ccc 2053 if (changed & BSS_CHANGED_BSSID) {
4f5ef75b 2054 ath9k_config_bss(sc, vif);
2d0ddec5 2055
226afe68
JP
2056 ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
2057 common->curbssid, common->curaid);
c6089ccc 2058 }
2d0ddec5 2059
2e5ef459
RM
2060 if (changed & BSS_CHANGED_IBSS) {
2061 /* There can be only one vif available */
2062 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2063 common->curaid = bss_conf->aid;
2064 ath9k_hw_write_associd(sc->sc_ah);
2065
2066 if (bss_conf->ibss_joined) {
2067 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
05c0be2f
MSS
2068
2069 if (!common->disable_ani) {
2070 sc->sc_flags |= SC_OP_ANI_RUN;
2071 ath_start_ani(common);
2072 }
2073
2e5ef459
RM
2074 } else {
2075 sc->sc_flags &= ~SC_OP_ANI_RUN;
2076 del_timer_sync(&common->ani.timer);
2077 }
2078 }
2079
c6089ccc
S
2080 /* Enable transmission of beacons (AP, IBSS, MESH) */
2081 if ((changed & BSS_CHANGED_BEACON) ||
2082 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
014cf3bb 2083 ath9k_set_beaconing_status(sc, false);
9ac58615 2084 error = ath_beacon_alloc(sc, vif);
c6089ccc
S
2085 if (!error)
2086 ath_beacon_config(sc, vif);
014cf3bb 2087 ath9k_set_beaconing_status(sc, true);
0005baf4
FF
2088 }
2089
2090 if (changed & BSS_CHANGED_ERP_SLOT) {
2091 if (bss_conf->use_short_slot)
2092 slottime = 9;
2093 else
2094 slottime = 20;
2095 if (vif->type == NL80211_IFTYPE_AP) {
2096 /*
2097 * Defer update, so that connected stations can adjust
2098 * their settings at the same time.
2099 * See beacon.c for more details
2100 */
2101 sc->beacon.slottime = slottime;
2102 sc->beacon.updateslot = UPDATE;
2103 } else {
2104 ah->slottime = slottime;
2105 ath9k_hw_init_global_settings(ah);
2106 }
2d0ddec5
JB
2107 }
2108
c6089ccc 2109 /* Disable transmission of beacons */
014cf3bb
RM
2110 if ((changed & BSS_CHANGED_BEACON_ENABLED) &&
2111 !bss_conf->enable_beacon) {
2112 ath9k_set_beaconing_status(sc, false);
2113 avp->is_bslot_active = false;
2114 ath9k_set_beaconing_status(sc, true);
2115 }
2d0ddec5 2116
c6089ccc 2117 if (changed & BSS_CHANGED_BEACON_INT) {
c6089ccc
S
2118 /*
2119 * In case of AP mode, the HW TSF has to be reset
2120 * when the beacon interval changes.
2121 */
2122 if (vif->type == NL80211_IFTYPE_AP) {
2123 sc->sc_flags |= SC_OP_TSF_RESET;
014cf3bb 2124 ath9k_set_beaconing_status(sc, false);
9ac58615 2125 error = ath_beacon_alloc(sc, vif);
2d0ddec5
JB
2126 if (!error)
2127 ath_beacon_config(sc, vif);
014cf3bb 2128 ath9k_set_beaconing_status(sc, true);
99e4d43a 2129 } else
c6089ccc 2130 ath_beacon_config(sc, vif);
2d0ddec5
JB
2131 }
2132
8feceb67 2133 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
226afe68
JP
2134 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2135 bss_conf->use_short_preamble);
8feceb67
VT
2136 if (bss_conf->use_short_preamble)
2137 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2138 else
2139 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2140 }
f078f209 2141
8feceb67 2142 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
226afe68
JP
2143 ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2144 bss_conf->use_cts_prot);
8feceb67
VT
2145 if (bss_conf->use_cts_prot &&
2146 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2147 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2148 else
2149 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2150 }
f078f209 2151
141b38b6 2152 mutex_unlock(&sc->mutex);
96f372c9 2153 ath9k_ps_restore(sc);
8feceb67 2154}
f078f209 2155
8feceb67
VT
2156static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2157{
9ac58615 2158 struct ath_softc *sc = hw->priv;
8feceb67 2159 u64 tsf;
f078f209 2160
141b38b6 2161 mutex_lock(&sc->mutex);
9abbfb27 2162 ath9k_ps_wakeup(sc);
141b38b6 2163 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 2164 ath9k_ps_restore(sc);
141b38b6 2165 mutex_unlock(&sc->mutex);
f078f209 2166
8feceb67
VT
2167 return tsf;
2168}
f078f209 2169
3b5d665b
AF
2170static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2171{
9ac58615 2172 struct ath_softc *sc = hw->priv;
3b5d665b 2173
141b38b6 2174 mutex_lock(&sc->mutex);
9abbfb27 2175 ath9k_ps_wakeup(sc);
141b38b6 2176 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 2177 ath9k_ps_restore(sc);
141b38b6 2178 mutex_unlock(&sc->mutex);
3b5d665b
AF
2179}
2180
8feceb67
VT
2181static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2182{
9ac58615 2183 struct ath_softc *sc = hw->priv;
c83be688 2184
141b38b6 2185 mutex_lock(&sc->mutex);
21526d57
LR
2186
2187 ath9k_ps_wakeup(sc);
141b38b6 2188 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
2189 ath9k_ps_restore(sc);
2190
141b38b6 2191 mutex_unlock(&sc->mutex);
8feceb67 2192}
f078f209 2193
8feceb67 2194static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2195 struct ieee80211_vif *vif,
141b38b6
S
2196 enum ieee80211_ampdu_mlme_action action,
2197 struct ieee80211_sta *sta,
0b01f030 2198 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 2199{
9ac58615 2200 struct ath_softc *sc = hw->priv;
8feceb67 2201 int ret = 0;
f078f209 2202
85ad181e
JB
2203 local_bh_disable();
2204
8feceb67
VT
2205 switch (action) {
2206 case IEEE80211_AMPDU_RX_START:
dca3edb8
S
2207 if (!(sc->sc_flags & SC_OP_RXAGGR))
2208 ret = -ENOTSUPP;
8feceb67
VT
2209 break;
2210 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
2211 break;
2212 case IEEE80211_AMPDU_TX_START:
71a3bf3e
FF
2213 if (!(sc->sc_flags & SC_OP_TXAGGR))
2214 return -EOPNOTSUPP;
2215
8b685ba9 2216 ath9k_ps_wakeup(sc);
231c3a1f
FF
2217 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2218 if (!ret)
2219 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2220 ath9k_ps_restore(sc);
8feceb67
VT
2221 break;
2222 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 2223 ath9k_ps_wakeup(sc);
f83da965 2224 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 2225 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2226 ath9k_ps_restore(sc);
8feceb67 2227 break;
b1720231 2228 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 2229 ath9k_ps_wakeup(sc);
8469cdef 2230 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 2231 ath9k_ps_restore(sc);
8469cdef 2232 break;
8feceb67 2233 default:
3800276a 2234 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT
2235 }
2236
85ad181e
JB
2237 local_bh_enable();
2238
8feceb67 2239 return ret;
f078f209
LR
2240}
2241
62dad5b0
BP
2242static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2243 struct survey_info *survey)
2244{
9ac58615 2245 struct ath_softc *sc = hw->priv;
3430098a 2246 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 2247 struct ieee80211_supported_band *sband;
3430098a
FF
2248 struct ieee80211_channel *chan;
2249 unsigned long flags;
2250 int pos;
2251
2252 spin_lock_irqsave(&common->cc_lock, flags);
2253 if (idx == 0)
2254 ath_update_survey_stats(sc);
39162dbe
FF
2255
2256 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2257 if (sband && idx >= sband->n_channels) {
2258 idx -= sband->n_channels;
2259 sband = NULL;
2260 }
62dad5b0 2261
39162dbe
FF
2262 if (!sband)
2263 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 2264
3430098a
FF
2265 if (!sband || idx >= sband->n_channels) {
2266 spin_unlock_irqrestore(&common->cc_lock, flags);
2267 return -ENOENT;
4f1a5a4b 2268 }
62dad5b0 2269
3430098a
FF
2270 chan = &sband->channels[idx];
2271 pos = chan->hw_value;
2272 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2273 survey->channel = chan;
2274 spin_unlock_irqrestore(&common->cc_lock, flags);
2275
62dad5b0
BP
2276 return 0;
2277}
2278
e239d859
FF
2279static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2280{
9ac58615 2281 struct ath_softc *sc = hw->priv;
e239d859
FF
2282 struct ath_hw *ah = sc->sc_ah;
2283
2284 mutex_lock(&sc->mutex);
2285 ah->coverage_class = coverage_class;
2286 ath9k_hw_init_global_settings(ah);
2287 mutex_unlock(&sc->mutex);
2288}
2289
69081624
VT
2290static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
2291{
69081624 2292 struct ath_softc *sc = hw->priv;
99aa55b6
MSS
2293 struct ath_hw *ah = sc->sc_ah;
2294 struct ath_common *common = ath9k_hw_common(ah);
86271e46
FF
2295 int timeout = 200; /* ms */
2296 int i, j;
2f6fc351 2297 bool drain_txq;
69081624
VT
2298
2299 mutex_lock(&sc->mutex);
69081624
VT
2300 cancel_delayed_work_sync(&sc->tx_complete_work);
2301
99aa55b6
MSS
2302 if (sc->sc_flags & SC_OP_INVALID) {
2303 ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
2304 mutex_unlock(&sc->mutex);
2305 return;
2306 }
2307
86271e46
FF
2308 if (drop)
2309 timeout = 1;
69081624 2310
86271e46 2311 for (j = 0; j < timeout; j++) {
108697c4 2312 bool npend = false;
86271e46
FF
2313
2314 if (j)
2315 usleep_range(1000, 2000);
69081624 2316
86271e46
FF
2317 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2318 if (!ATH_TXQ_SETUP(sc, i))
2319 continue;
2320
108697c4
MSS
2321 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
2322
2323 if (npend)
2324 break;
69081624 2325 }
86271e46
FF
2326
2327 if (!npend)
2328 goto out;
69081624
VT
2329 }
2330
51513906 2331 ath9k_ps_wakeup(sc);
2f6fc351
RM
2332 spin_lock_bh(&sc->sc_pcu_lock);
2333 drain_txq = ath_drain_all_txq(sc, false);
2f6fc351 2334 if (!drain_txq)
69081624 2335 ath_reset(sc, false);
f6b4e4d4 2336 spin_unlock_bh(&sc->sc_pcu_lock);
51513906 2337 ath9k_ps_restore(sc);
d78f4b3e
SB
2338 ieee80211_wake_queues(hw);
2339
86271e46 2340out:
69081624
VT
2341 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2342 mutex_unlock(&sc->mutex);
2343}
2344
15b91e83
VN
2345static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2346{
2347 struct ath_softc *sc = hw->priv;
2348 int i;
2349
2350 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2351 if (!ATH_TXQ_SETUP(sc, i))
2352 continue;
2353
2354 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
2355 return true;
2356 }
2357 return false;
2358}
2359
5595f119 2360static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
ba4903f9
FF
2361{
2362 struct ath_softc *sc = hw->priv;
2363 struct ath_hw *ah = sc->sc_ah;
2364 struct ieee80211_vif *vif;
2365 struct ath_vif *avp;
2366 struct ath_buf *bf;
2367 struct ath_tx_status ts;
2368 int status;
2369
2370 vif = sc->beacon.bslot[0];
2371 if (!vif)
2372 return 0;
2373
2374 avp = (void *)vif->drv_priv;
2375 if (!avp->is_bslot_active)
2376 return 0;
2377
2378 if (!sc->beacon.tx_processed) {
2379 tasklet_disable(&sc->bcon_tasklet);
2380
2381 bf = avp->av_bcbuf;
2382 if (!bf || !bf->bf_mpdu)
2383 goto skip;
2384
2385 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2386 if (status == -EINPROGRESS)
2387 goto skip;
2388
2389 sc->beacon.tx_processed = true;
2390 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2391
2392skip:
2393 tasklet_enable(&sc->bcon_tasklet);
2394 }
2395
2396 return sc->beacon.tx_last;
2397}
2398
6baff7f9 2399struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2400 .tx = ath9k_tx,
2401 .start = ath9k_start,
2402 .stop = ath9k_stop,
2403 .add_interface = ath9k_add_interface,
6b3b991d 2404 .change_interface = ath9k_change_interface,
8feceb67
VT
2405 .remove_interface = ath9k_remove_interface,
2406 .config = ath9k_config,
8feceb67 2407 .configure_filter = ath9k_configure_filter,
4ca77860
JB
2408 .sta_add = ath9k_sta_add,
2409 .sta_remove = ath9k_sta_remove,
5519541d 2410 .sta_notify = ath9k_sta_notify,
8feceb67 2411 .conf_tx = ath9k_conf_tx,
8feceb67 2412 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2413 .set_key = ath9k_set_key,
8feceb67 2414 .get_tsf = ath9k_get_tsf,
3b5d665b 2415 .set_tsf = ath9k_set_tsf,
8feceb67 2416 .reset_tsf = ath9k_reset_tsf,
4233df6b 2417 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2418 .get_survey = ath9k_get_survey,
3b319aae 2419 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2420 .set_coverage_class = ath9k_set_coverage_class,
69081624 2421 .flush = ath9k_flush,
15b91e83 2422 .tx_frames_pending = ath9k_tx_frames_pending,
ba4903f9 2423 .tx_last_beacon = ath9k_tx_last_beacon,
8feceb67 2424};
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