Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
69081624 | 18 | #include <linux/delay.h> |
394cf0a1 | 19 | #include "ath9k.h" |
af03abec | 20 | #include "btcoex.h" |
f078f209 | 21 | |
6dcc3444 SM |
22 | static void ath9k_set_assoc_state(struct ath_softc *sc, |
23 | struct ieee80211_vif *vif); | |
24 | ||
313eb87f | 25 | u8 ath9k_parse_mpdudensity(u8 mpdudensity) |
ff37e337 S |
26 | { |
27 | /* | |
28 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
29 | * 0 for no restriction | |
30 | * 1 for 1/4 us | |
31 | * 2 for 1/2 us | |
32 | * 3 for 1 us | |
33 | * 4 for 2 us | |
34 | * 5 for 4 us | |
35 | * 6 for 8 us | |
36 | * 7 for 16 us | |
37 | */ | |
38 | switch (mpdudensity) { | |
39 | case 0: | |
40 | return 0; | |
41 | case 1: | |
42 | case 2: | |
43 | case 3: | |
44 | /* Our lower layer calculations limit our precision to | |
45 | 1 microsecond */ | |
46 | return 1; | |
47 | case 4: | |
48 | return 2; | |
49 | case 5: | |
50 | return 4; | |
51 | case 6: | |
52 | return 8; | |
53 | case 7: | |
54 | return 16; | |
55 | default: | |
56 | return 0; | |
57 | } | |
58 | } | |
59 | ||
69081624 VT |
60 | static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) |
61 | { | |
62 | bool pending = false; | |
63 | ||
64 | spin_lock_bh(&txq->axq_lock); | |
65 | ||
66 | if (txq->axq_depth || !list_empty(&txq->axq_acq)) | |
67 | pending = true; | |
69081624 VT |
68 | |
69 | spin_unlock_bh(&txq->axq_lock); | |
70 | return pending; | |
71 | } | |
72 | ||
6d79cb4c | 73 | static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
74 | { |
75 | unsigned long flags; | |
76 | bool ret; | |
77 | ||
9ecdef4b LR |
78 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
79 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
80 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
81 | |
82 | return ret; | |
83 | } | |
84 | ||
a91d75ae LR |
85 | void ath9k_ps_wakeup(struct ath_softc *sc) |
86 | { | |
898c914a | 87 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae | 88 | unsigned long flags; |
fbb078fc | 89 | enum ath9k_power_mode power_mode; |
a91d75ae LR |
90 | |
91 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
92 | if (++sc->ps_usecount != 1) | |
93 | goto unlock; | |
94 | ||
fbb078fc | 95 | power_mode = sc->sc_ah->power_mode; |
9ecdef4b | 96 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae | 97 | |
898c914a FF |
98 | /* |
99 | * While the hardware is asleep, the cycle counters contain no | |
100 | * useful data. Better clear them now so that they don't mess up | |
101 | * survey data results. | |
102 | */ | |
fbb078fc FF |
103 | if (power_mode != ATH9K_PM_AWAKE) { |
104 | spin_lock(&common->cc_lock); | |
105 | ath_hw_cycle_counters_update(common); | |
106 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
c9ae6ab4 | 107 | memset(&common->cc_ani, 0, sizeof(common->cc_ani)); |
fbb078fc FF |
108 | spin_unlock(&common->cc_lock); |
109 | } | |
898c914a | 110 | |
a91d75ae LR |
111 | unlock: |
112 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
113 | } | |
114 | ||
115 | void ath9k_ps_restore(struct ath_softc *sc) | |
116 | { | |
898c914a | 117 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
c6c539f0 | 118 | enum ath9k_power_mode mode; |
a91d75ae | 119 | unsigned long flags; |
ad128860 | 120 | bool reset; |
a91d75ae LR |
121 | |
122 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
123 | if (--sc->ps_usecount != 0) | |
124 | goto unlock; | |
125 | ||
ad128860 SM |
126 | if (sc->ps_idle) { |
127 | ath9k_hw_setrxabort(sc->sc_ah, 1); | |
128 | ath9k_hw_stopdmarecv(sc->sc_ah, &reset); | |
c6c539f0 | 129 | mode = ATH9K_PM_FULL_SLEEP; |
ad128860 SM |
130 | } else if (sc->ps_enabled && |
131 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
132 | PS_WAIT_FOR_CAB | | |
133 | PS_WAIT_FOR_PSPOLL_DATA | | |
424749c7 RM |
134 | PS_WAIT_FOR_TX_ACK | |
135 | PS_WAIT_FOR_ANI))) { | |
c6c539f0 | 136 | mode = ATH9K_PM_NETWORK_SLEEP; |
08d4df41 RM |
137 | if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) |
138 | ath9k_btcoex_stop_gen_timer(sc); | |
ad128860 | 139 | } else { |
c6c539f0 | 140 | goto unlock; |
ad128860 | 141 | } |
c6c539f0 FF |
142 | |
143 | spin_lock(&common->cc_lock); | |
144 | ath_hw_cycle_counters_update(common); | |
145 | spin_unlock(&common->cc_lock); | |
146 | ||
1a8f0d39 | 147 | ath9k_hw_setpower(sc->sc_ah, mode); |
a91d75ae LR |
148 | |
149 | unlock: | |
150 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
151 | } | |
152 | ||
9adcf440 | 153 | static void __ath_cancel_work(struct ath_softc *sc) |
ff37e337 | 154 | { |
5ee08656 FF |
155 | cancel_work_sync(&sc->paprd_work); |
156 | cancel_work_sync(&sc->hw_check_work); | |
157 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
181fb18d | 158 | cancel_delayed_work_sync(&sc->hw_pll_work); |
fad29cd2 | 159 | |
bf52592f | 160 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
fad29cd2 SM |
161 | if (ath9k_hw_mci_is_enabled(sc->sc_ah)) |
162 | cancel_work_sync(&sc->mci_work); | |
bf52592f | 163 | #endif |
9adcf440 | 164 | } |
5ee08656 | 165 | |
9adcf440 FF |
166 | static void ath_cancel_work(struct ath_softc *sc) |
167 | { | |
168 | __ath_cancel_work(sc); | |
169 | cancel_work_sync(&sc->hw_reset_work); | |
170 | } | |
3cbb5dd7 | 171 | |
af68abad SM |
172 | static void ath_restart_work(struct ath_softc *sc) |
173 | { | |
af68abad SM |
174 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
175 | ||
c12b6021 GJ |
176 | if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) || |
177 | AR_SREV_9550(sc->sc_ah)) | |
af68abad SM |
178 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, |
179 | msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); | |
180 | ||
181 | ath_start_rx_poll(sc, 3); | |
da0d45f7 | 182 | ath_start_ani(sc); |
af68abad SM |
183 | } |
184 | ||
9adcf440 FF |
185 | static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush) |
186 | { | |
187 | struct ath_hw *ah = sc->sc_ah; | |
ceea2a51 | 188 | bool ret = true; |
6a6733f2 | 189 | |
9adcf440 | 190 | ieee80211_stop_queues(sc->hw); |
5e848f78 | 191 | |
9adcf440 | 192 | sc->hw_busy_count = 0; |
da0d45f7 | 193 | ath_stop_ani(sc); |
01e18918 | 194 | del_timer_sync(&sc->rx_poll_timer); |
ff37e337 | 195 | |
9adcf440 FF |
196 | ath9k_debug_samp_bb_mac(sc); |
197 | ath9k_hw_disable_interrupts(ah); | |
8b3f4616 | 198 | |
9adcf440 FF |
199 | if (!ath_stoprecv(sc)) |
200 | ret = false; | |
c0d7c7af | 201 | |
ceea2a51 FF |
202 | if (!ath_drain_all_txq(sc, retry_tx)) |
203 | ret = false; | |
204 | ||
9adcf440 FF |
205 | if (!flush) { |
206 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
3483288c FF |
207 | ath_rx_tasklet(sc, 1, true); |
208 | ath_rx_tasklet(sc, 1, false); | |
9adcf440 FF |
209 | } else { |
210 | ath_flushrecv(sc); | |
211 | } | |
20bd2a09 | 212 | |
9adcf440 FF |
213 | return ret; |
214 | } | |
ff37e337 | 215 | |
9adcf440 FF |
216 | static bool ath_complete_reset(struct ath_softc *sc, bool start) |
217 | { | |
218 | struct ath_hw *ah = sc->sc_ah; | |
219 | struct ath_common *common = ath9k_hw_common(ah); | |
196fb860 | 220 | unsigned long flags; |
c0d7c7af | 221 | |
c0d7c7af | 222 | if (ath_startrecv(sc) != 0) { |
3800276a | 223 | ath_err(common, "Unable to restart recv logic\n"); |
9adcf440 | 224 | return false; |
c0d7c7af LR |
225 | } |
226 | ||
5048e8c3 RM |
227 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
228 | sc->config.txpowlimit, &sc->curtxpow); | |
b74713d0 SM |
229 | |
230 | clear_bit(SC_OP_HW_RESET, &sc->sc_flags); | |
72d874c6 | 231 | ath9k_hw_set_interrupts(ah); |
b037b693 | 232 | ath9k_hw_enable_interrupts(ah); |
3989279c | 233 | |
4cb54fa3 | 234 | if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) { |
196fb860 SM |
235 | if (!test_bit(SC_OP_BEACONS, &sc->sc_flags)) |
236 | goto work; | |
237 | ||
ef4ad633 | 238 | ath9k_set_beacon(sc); |
196fb860 SM |
239 | |
240 | if (ah->opmode == NL80211_IFTYPE_STATION && | |
241 | test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { | |
242 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
243 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
244 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
245 | } | |
246 | work: | |
af68abad | 247 | ath_restart_work(sc); |
5ee08656 FF |
248 | } |
249 | ||
8da07830 SM |
250 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3) |
251 | ath_ant_comb_update(sc); | |
43c35284 | 252 | |
9adcf440 FF |
253 | ieee80211_wake_queues(sc->hw); |
254 | ||
255 | return true; | |
256 | } | |
257 | ||
258 | static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan, | |
259 | bool retry_tx) | |
260 | { | |
261 | struct ath_hw *ah = sc->sc_ah; | |
262 | struct ath_common *common = ath9k_hw_common(ah); | |
263 | struct ath9k_hw_cal_data *caldata = NULL; | |
264 | bool fastcc = true; | |
265 | bool flush = false; | |
266 | int r; | |
267 | ||
268 | __ath_cancel_work(sc); | |
269 | ||
270 | spin_lock_bh(&sc->sc_pcu_lock); | |
92460412 | 271 | |
4cb54fa3 | 272 | if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) { |
9adcf440 FF |
273 | fastcc = false; |
274 | caldata = &sc->caldata; | |
275 | } | |
276 | ||
277 | if (!hchan) { | |
278 | fastcc = false; | |
279 | flush = true; | |
280 | hchan = ah->curchan; | |
281 | } | |
282 | ||
9adcf440 FF |
283 | if (!ath_prepare_reset(sc, retry_tx, flush)) |
284 | fastcc = false; | |
285 | ||
d2182b69 | 286 | ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", |
feced201 | 287 | hchan->channel, IS_CHAN_HT40(hchan), fastcc); |
9adcf440 FF |
288 | |
289 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); | |
290 | if (r) { | |
291 | ath_err(common, | |
292 | "Unable to reset channel, reset status %d\n", r); | |
293 | goto out; | |
294 | } | |
295 | ||
e82cb03f RM |
296 | if (ath9k_hw_mci_is_enabled(sc->sc_ah) && |
297 | (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) | |
298 | ath9k_mci_set_txpower(sc, true, false); | |
299 | ||
9adcf440 FF |
300 | if (!ath_complete_reset(sc, true)) |
301 | r = -EIO; | |
302 | ||
303 | out: | |
6a6733f2 | 304 | spin_unlock_bh(&sc->sc_pcu_lock); |
9adcf440 FF |
305 | return r; |
306 | } | |
307 | ||
308 | ||
309 | /* | |
310 | * Set/change channels. If the channel is really being changed, it's done | |
311 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
312 | * DMA, then restart stuff. | |
313 | */ | |
314 | static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, | |
315 | struct ath9k_channel *hchan) | |
316 | { | |
317 | int r; | |
318 | ||
781b14a3 | 319 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) |
9adcf440 FF |
320 | return -EIO; |
321 | ||
9adcf440 | 322 | r = ath_reset_internal(sc, hchan, false); |
6a6733f2 | 323 | |
3989279c | 324 | return r; |
ff37e337 S |
325 | } |
326 | ||
7e1e3864 BG |
327 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, |
328 | struct ieee80211_vif *vif) | |
ff37e337 S |
329 | { |
330 | struct ath_node *an; | |
313eb87f | 331 | u8 density; |
ff37e337 S |
332 | an = (struct ath_node *)sta->drv_priv; |
333 | ||
7f010c93 BG |
334 | #ifdef CONFIG_ATH9K_DEBUGFS |
335 | spin_lock(&sc->nodes_lock); | |
336 | list_add(&an->list, &sc->nodes); | |
337 | spin_unlock(&sc->nodes_lock); | |
156369fa | 338 | #endif |
7f010c93 | 339 | an->sta = sta; |
7e1e3864 | 340 | an->vif = vif; |
3d4e20f2 | 341 | |
a4d6367f | 342 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
ff37e337 | 343 | ath_tx_node_init(sc, an); |
9e98ac65 | 344 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc | 345 | sta->ht_cap.ampdu_factor); |
313eb87f SE |
346 | density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density); |
347 | an->mpdudensity = density; | |
87792efc | 348 | } |
ff37e337 S |
349 | } |
350 | ||
351 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
352 | { | |
353 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
354 | ||
7f010c93 BG |
355 | #ifdef CONFIG_ATH9K_DEBUGFS |
356 | spin_lock(&sc->nodes_lock); | |
357 | list_del(&an->list); | |
358 | spin_unlock(&sc->nodes_lock); | |
359 | an->sta = NULL; | |
360 | #endif | |
361 | ||
a4d6367f | 362 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
ff37e337 S |
363 | ath_tx_node_cleanup(sc, an); |
364 | } | |
365 | ||
55624204 | 366 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
367 | { |
368 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 369 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 370 | struct ath_common *common = ath9k_hw_common(ah); |
124b979b | 371 | enum ath_reset_type type; |
07c15a3f | 372 | unsigned long flags; |
17d7904d | 373 | u32 status = sc->intrstatus; |
b5c80475 | 374 | u32 rxmask; |
ff37e337 | 375 | |
e3927007 FF |
376 | ath9k_ps_wakeup(sc); |
377 | spin_lock(&sc->sc_pcu_lock); | |
378 | ||
a4d86d95 RM |
379 | if ((status & ATH9K_INT_FATAL) || |
380 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
030d6294 FF |
381 | |
382 | if (status & ATH9K_INT_FATAL) | |
383 | type = RESET_TYPE_FATAL_INT; | |
384 | else | |
385 | type = RESET_TYPE_BB_WATCHDOG; | |
386 | ||
124b979b | 387 | ath9k_queue_reset(sc, type); |
e3927007 | 388 | goto out; |
063d8be3 | 389 | } |
ff37e337 | 390 | |
07c15a3f | 391 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
4105f807 RM |
392 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
393 | /* | |
394 | * TSF sync does not look correct; remain awake to sync with | |
395 | * the next Beacon. | |
396 | */ | |
d2182b69 | 397 | ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); |
e8fe7336 | 398 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
4105f807 | 399 | } |
07c15a3f | 400 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
4105f807 | 401 | |
b5c80475 FF |
402 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
403 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
404 | ATH9K_INT_RXORN); | |
405 | else | |
406 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
407 | ||
408 | if (status & rxmask) { | |
b5c80475 FF |
409 | /* Check for high priority Rx first */ |
410 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
411 | (status & ATH9K_INT_RXHP)) | |
412 | ath_rx_tasklet(sc, 0, true); | |
413 | ||
414 | ath_rx_tasklet(sc, 0, false); | |
ff37e337 S |
415 | } |
416 | ||
e5003249 VT |
417 | if (status & ATH9K_INT_TX) { |
418 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
419 | ath_tx_edma_tasklet(sc); | |
420 | else | |
421 | ath_tx_tasklet(sc); | |
422 | } | |
063d8be3 | 423 | |
56ca0dba | 424 | ath9k_btcoex_handle_interrupt(sc, status); |
19686ddf | 425 | |
e3927007 | 426 | out: |
ff37e337 | 427 | /* re-enable hardware interrupt */ |
4df3071e | 428 | ath9k_hw_enable_interrupts(ah); |
6a6733f2 | 429 | |
52671e43 | 430 | spin_unlock(&sc->sc_pcu_lock); |
153e080d | 431 | ath9k_ps_restore(sc); |
ff37e337 S |
432 | } |
433 | ||
6baff7f9 | 434 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 435 | { |
063d8be3 S |
436 | #define SCHED_INTR ( \ |
437 | ATH9K_INT_FATAL | \ | |
a4d86d95 | 438 | ATH9K_INT_BB_WATCHDOG | \ |
063d8be3 S |
439 | ATH9K_INT_RXORN | \ |
440 | ATH9K_INT_RXEOL | \ | |
441 | ATH9K_INT_RX | \ | |
b5c80475 FF |
442 | ATH9K_INT_RXLP | \ |
443 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
444 | ATH9K_INT_TX | \ |
445 | ATH9K_INT_BMISS | \ | |
446 | ATH9K_INT_CST | \ | |
ebb8e1d7 | 447 | ATH9K_INT_TSFOOR | \ |
40dc5392 MSS |
448 | ATH9K_INT_GENTIMER | \ |
449 | ATH9K_INT_MCI) | |
063d8be3 | 450 | |
ff37e337 | 451 | struct ath_softc *sc = dev; |
cbe61d8a | 452 | struct ath_hw *ah = sc->sc_ah; |
b5bfc568 | 453 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
454 | enum ath9k_int status; |
455 | bool sched = false; | |
456 | ||
063d8be3 S |
457 | /* |
458 | * The hardware is not ready/present, don't | |
459 | * touch anything. Note this can happen early | |
460 | * on if the IRQ is shared. | |
461 | */ | |
781b14a3 | 462 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) |
063d8be3 | 463 | return IRQ_NONE; |
ff37e337 | 464 | |
063d8be3 S |
465 | /* shared irq, not for us */ |
466 | ||
153e080d | 467 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 468 | return IRQ_NONE; |
063d8be3 | 469 | |
f41a9b3b FF |
470 | if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) { |
471 | ath9k_hw_kill_interrupts(ah); | |
b74713d0 | 472 | return IRQ_HANDLED; |
f41a9b3b | 473 | } |
b74713d0 | 474 | |
063d8be3 S |
475 | /* |
476 | * Figure out the reason(s) for the interrupt. Note | |
477 | * that the hal returns a pseudo-ISR that may include | |
478 | * bits we haven't explicitly enabled so we mask the | |
479 | * value to insure we only process bits we requested. | |
480 | */ | |
481 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 482 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 483 | |
063d8be3 S |
484 | /* |
485 | * If there are no status bits set, then this interrupt was not | |
486 | * for me (should have been caught above). | |
487 | */ | |
153e080d | 488 | if (!status) |
063d8be3 | 489 | return IRQ_NONE; |
ff37e337 | 490 | |
063d8be3 S |
491 | /* Cache the status */ |
492 | sc->intrstatus = status; | |
493 | ||
494 | if (status & SCHED_INTR) | |
495 | sched = true; | |
496 | ||
b11e640a MSS |
497 | #ifdef CONFIG_PM_SLEEP |
498 | if (status & ATH9K_INT_BMISS) { | |
499 | if (atomic_read(&sc->wow_sleep_proc_intr) == 0) { | |
500 | ath_dbg(common, ANY, "during WoW we got a BMISS\n"); | |
501 | atomic_inc(&sc->wow_got_bmiss_intr); | |
502 | atomic_dec(&sc->wow_sleep_proc_intr); | |
503 | } | |
504 | ath_dbg(common, INTERRUPT, "beacon miss interrupt\n"); | |
505 | } | |
506 | #endif | |
507 | ||
063d8be3 S |
508 | /* |
509 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
510 | * chip immediately. | |
511 | */ | |
b5c80475 FF |
512 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
513 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
514 | goto chip_reset; |
515 | ||
08578b8f LR |
516 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
517 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
b5bfc568 FF |
518 | |
519 | spin_lock(&common->cc_lock); | |
520 | ath_hw_cycle_counters_update(common); | |
08578b8f | 521 | ar9003_hw_bb_watchdog_dbg_info(ah); |
b5bfc568 FF |
522 | spin_unlock(&common->cc_lock); |
523 | ||
08578b8f LR |
524 | goto chip_reset; |
525 | } | |
526 | ||
063d8be3 S |
527 | if (status & ATH9K_INT_SWBA) |
528 | tasklet_schedule(&sc->bcon_tasklet); | |
529 | ||
530 | if (status & ATH9K_INT_TXURN) | |
531 | ath9k_hw_updatetxtriglevel(ah, true); | |
532 | ||
0682c9b5 RM |
533 | if (status & ATH9K_INT_RXEOL) { |
534 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
72d874c6 | 535 | ath9k_hw_set_interrupts(ah); |
b5c80475 FF |
536 | } |
537 | ||
153e080d VT |
538 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
539 | if (status & ATH9K_INT_TIM_TIMER) { | |
ff9f0b63 LR |
540 | if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) |
541 | goto chip_reset; | |
063d8be3 S |
542 | /* Clear RxAbort bit so that we can |
543 | * receive frames */ | |
9ecdef4b | 544 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
07c15a3f | 545 | spin_lock(&sc->sc_pm_lock); |
153e080d | 546 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 547 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
07c15a3f | 548 | spin_unlock(&sc->sc_pm_lock); |
ff37e337 | 549 | } |
063d8be3 S |
550 | |
551 | chip_reset: | |
ff37e337 | 552 | |
817e11de S |
553 | ath_debug_stat_interrupt(sc, status); |
554 | ||
ff37e337 | 555 | if (sched) { |
4df3071e FF |
556 | /* turn off every interrupt */ |
557 | ath9k_hw_disable_interrupts(ah); | |
ff37e337 S |
558 | tasklet_schedule(&sc->intr_tq); |
559 | } | |
560 | ||
561 | return IRQ_HANDLED; | |
063d8be3 S |
562 | |
563 | #undef SCHED_INTR | |
ff37e337 S |
564 | } |
565 | ||
236de514 | 566 | static int ath_reset(struct ath_softc *sc, bool retry_tx) |
ff37e337 | 567 | { |
ae8d2858 | 568 | int r; |
ff37e337 | 569 | |
783cd01e | 570 | ath9k_ps_wakeup(sc); |
6a6733f2 | 571 | |
9adcf440 | 572 | r = ath_reset_internal(sc, NULL, retry_tx); |
ff37e337 S |
573 | |
574 | if (retry_tx) { | |
575 | int i; | |
576 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
577 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
578 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
579 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
580 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
581 | } |
582 | } | |
583 | } | |
584 | ||
783cd01e | 585 | ath9k_ps_restore(sc); |
2ab81d4a | 586 | |
ae8d2858 | 587 | return r; |
ff37e337 S |
588 | } |
589 | ||
124b979b RM |
590 | void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) |
591 | { | |
592 | #ifdef CONFIG_ATH9K_DEBUGFS | |
593 | RESET_STAT_INC(sc, type); | |
594 | #endif | |
595 | set_bit(SC_OP_HW_RESET, &sc->sc_flags); | |
596 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); | |
597 | } | |
598 | ||
236de514 FF |
599 | void ath_reset_work(struct work_struct *work) |
600 | { | |
601 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); | |
602 | ||
236de514 | 603 | ath_reset(sc, true); |
236de514 FF |
604 | } |
605 | ||
ff37e337 S |
606 | /**********************/ |
607 | /* mac80211 callbacks */ | |
608 | /**********************/ | |
609 | ||
8feceb67 | 610 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 611 | { |
9ac58615 | 612 | struct ath_softc *sc = hw->priv; |
af03abec | 613 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 614 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 615 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 616 | struct ath9k_channel *init_channel; |
82880a7c | 617 | int r; |
f078f209 | 618 | |
d2182b69 | 619 | ath_dbg(common, CONFIG, |
226afe68 JP |
620 | "Starting driver with initial channel: %d MHz\n", |
621 | curchan->center_freq); | |
f078f209 | 622 | |
f62d816f | 623 | ath9k_ps_wakeup(sc); |
141b38b6 S |
624 | mutex_lock(&sc->mutex); |
625 | ||
c344c9cb | 626 | init_channel = ath9k_cmn_get_curchannel(hw, ah); |
ff37e337 S |
627 | |
628 | /* Reset SERDES registers */ | |
84c87dc8 | 629 | ath9k_hw_configpcipowersave(ah, false); |
ff37e337 S |
630 | |
631 | /* | |
632 | * The basic interface to setting the hardware in a good | |
633 | * state is ``reset''. On return the hardware is known to | |
634 | * be powered up and with interrupts disabled. This must | |
635 | * be followed by initialization of the appropriate bits | |
636 | * and then setup of the interrupt mask. | |
637 | */ | |
4bdd1e97 | 638 | spin_lock_bh(&sc->sc_pcu_lock); |
c0c11741 FF |
639 | |
640 | atomic_set(&ah->intr_ref_cnt, -1); | |
641 | ||
20bd2a09 | 642 | r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); |
ae8d2858 | 643 | if (r) { |
3800276a JP |
644 | ath_err(common, |
645 | "Unable to reset hardware; reset status %d (freq %u MHz)\n", | |
646 | r, curchan->center_freq); | |
ceb26a60 | 647 | ah->reset_power_on = false; |
ff37e337 | 648 | } |
ff37e337 | 649 | |
ff37e337 | 650 | /* Setup our intr mask. */ |
b5c80475 FF |
651 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
652 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
653 | ATH9K_INT_GLOBAL; | |
654 | ||
655 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f LR |
656 | ah->imask |= ATH9K_INT_RXHP | |
657 | ATH9K_INT_RXLP | | |
658 | ATH9K_INT_BB_WATCHDOG; | |
b5c80475 FF |
659 | else |
660 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 661 | |
364734fa | 662 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 663 | |
af03abec | 664 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 665 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 666 | |
e270e776 | 667 | ath_mci_enable(sc); |
40dc5392 | 668 | |
781b14a3 | 669 | clear_bit(SC_OP_INVALID, &sc->sc_flags); |
5f841b41 | 670 | sc->sc_ah->is_monitoring = false; |
ff37e337 | 671 | |
ceb26a60 FF |
672 | if (!ath_complete_reset(sc, false)) |
673 | ah->reset_power_on = false; | |
ff37e337 | 674 | |
c0c11741 FF |
675 | if (ah->led_pin >= 0) { |
676 | ath9k_hw_cfg_output(ah, ah->led_pin, | |
677 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
678 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); | |
679 | } | |
680 | ||
681 | /* | |
682 | * Reset key cache to sane defaults (all entries cleared) instead of | |
683 | * semi-random values after suspend/resume. | |
684 | */ | |
685 | ath9k_cmn_init_crypto(sc->sc_ah); | |
686 | ||
9adcf440 | 687 | spin_unlock_bh(&sc->sc_pcu_lock); |
164ace38 | 688 | |
8060e169 VT |
689 | if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en) |
690 | common->bus_ops->extn_synch_en(common); | |
691 | ||
141b38b6 S |
692 | mutex_unlock(&sc->mutex); |
693 | ||
f62d816f FF |
694 | ath9k_ps_restore(sc); |
695 | ||
ceb26a60 | 696 | return 0; |
f078f209 LR |
697 | } |
698 | ||
36323f81 TH |
699 | static void ath9k_tx(struct ieee80211_hw *hw, |
700 | struct ieee80211_tx_control *control, | |
701 | struct sk_buff *skb) | |
f078f209 | 702 | { |
9ac58615 | 703 | struct ath_softc *sc = hw->priv; |
c46917bb | 704 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 705 | struct ath_tx_control txctl; |
1bc14880 | 706 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
07c15a3f | 707 | unsigned long flags; |
528f0c6b | 708 | |
96148326 | 709 | if (sc->ps_enabled) { |
dc8c4585 JM |
710 | /* |
711 | * mac80211 does not set PM field for normal data frames, so we | |
712 | * need to update that based on the current PS mode. | |
713 | */ | |
714 | if (ieee80211_is_data(hdr->frame_control) && | |
715 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
716 | !ieee80211_has_pm(hdr->frame_control)) { | |
d2182b69 | 717 | ath_dbg(common, PS, |
226afe68 | 718 | "Add PM=1 for a TX frame while in PS mode\n"); |
dc8c4585 JM |
719 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
720 | } | |
721 | } | |
722 | ||
ad128860 | 723 | if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { |
9a23f9ca JM |
724 | /* |
725 | * We are using PS-Poll and mac80211 can request TX while in | |
726 | * power save mode. Need to wake up hardware for the TX to be | |
727 | * completed and if needed, also for RX of buffered frames. | |
728 | */ | |
9a23f9ca | 729 | ath9k_ps_wakeup(sc); |
07c15a3f | 730 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
fdf76622 VT |
731 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
732 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 733 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
d2182b69 | 734 | ath_dbg(common, PS, |
226afe68 | 735 | "Sending PS-Poll to pick a buffered frame\n"); |
1b04b930 | 736 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 737 | } else { |
d2182b69 | 738 | ath_dbg(common, PS, "Wake up to complete TX\n"); |
1b04b930 | 739 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
740 | } |
741 | /* | |
742 | * The actual restore operation will happen only after | |
ad128860 | 743 | * the ps_flags bit is cleared. We are just dropping |
9a23f9ca JM |
744 | * the ps_usecount here. |
745 | */ | |
07c15a3f | 746 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
9a23f9ca JM |
747 | ath9k_ps_restore(sc); |
748 | } | |
749 | ||
ad128860 SM |
750 | /* |
751 | * Cannot tx while the hardware is in full sleep, it first needs a full | |
752 | * chip reset to recover from that | |
753 | */ | |
754 | if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { | |
755 | ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); | |
756 | goto exit; | |
757 | } | |
758 | ||
528f0c6b | 759 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
066dae93 | 760 | txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; |
36323f81 | 761 | txctl.sta = control->sta; |
528f0c6b | 762 | |
d2182b69 | 763 | ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 764 | |
c52f33d0 | 765 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
d2182b69 | 766 | ath_dbg(common, XMIT, "TX failed\n"); |
a5a0bca1 | 767 | TX_STAT_INC(txctl.txq->axq_qnum, txfailed); |
528f0c6b | 768 | goto exit; |
8feceb67 VT |
769 | } |
770 | ||
7bb45683 | 771 | return; |
528f0c6b | 772 | exit: |
249ee722 | 773 | ieee80211_free_txskb(hw, skb); |
f078f209 LR |
774 | } |
775 | ||
8feceb67 | 776 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 777 | { |
9ac58615 | 778 | struct ath_softc *sc = hw->priv; |
af03abec | 779 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 780 | struct ath_common *common = ath9k_hw_common(ah); |
c0c11741 | 781 | bool prev_idle; |
f078f209 | 782 | |
4c483817 S |
783 | mutex_lock(&sc->mutex); |
784 | ||
9adcf440 | 785 | ath_cancel_work(sc); |
01e18918 | 786 | del_timer_sync(&sc->rx_poll_timer); |
c94dbff7 | 787 | |
781b14a3 | 788 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { |
d2182b69 | 789 | ath_dbg(common, ANY, "Device not present\n"); |
4c483817 | 790 | mutex_unlock(&sc->mutex); |
9c84b797 S |
791 | return; |
792 | } | |
8feceb67 | 793 | |
3867cf6a S |
794 | /* Ensure HW is awake when we try to shut it down. */ |
795 | ath9k_ps_wakeup(sc); | |
796 | ||
6a6733f2 LR |
797 | spin_lock_bh(&sc->sc_pcu_lock); |
798 | ||
203043f5 SG |
799 | /* prevent tasklets to enable interrupts once we disable them */ |
800 | ah->imask &= ~ATH9K_INT_GLOBAL; | |
801 | ||
ff37e337 S |
802 | /* make sure h/w will not generate any interrupt |
803 | * before setting the invalid flag. */ | |
4df3071e | 804 | ath9k_hw_disable_interrupts(ah); |
ff37e337 | 805 | |
c0c11741 FF |
806 | spin_unlock_bh(&sc->sc_pcu_lock); |
807 | ||
808 | /* we can now sync irq and kill any running tasklets, since we already | |
809 | * disabled interrupts and not holding a spin lock */ | |
810 | synchronize_irq(sc->irq); | |
811 | tasklet_kill(&sc->intr_tq); | |
812 | tasklet_kill(&sc->bcon_tasklet); | |
813 | ||
814 | prev_idle = sc->ps_idle; | |
815 | sc->ps_idle = true; | |
816 | ||
817 | spin_lock_bh(&sc->sc_pcu_lock); | |
818 | ||
819 | if (ah->led_pin >= 0) { | |
820 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); | |
821 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
822 | } | |
823 | ||
824 | ath_prepare_reset(sc, false, true); | |
ff37e337 | 825 | |
0d95521e FF |
826 | if (sc->rx.frag) { |
827 | dev_kfree_skb_any(sc->rx.frag); | |
828 | sc->rx.frag = NULL; | |
829 | } | |
830 | ||
c0c11741 FF |
831 | if (!ah->curchan) |
832 | ah->curchan = ath9k_cmn_get_curchannel(hw, ah); | |
6a6733f2 | 833 | |
c0c11741 FF |
834 | ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
835 | ath9k_hw_phy_disable(ah); | |
6a6733f2 | 836 | |
c0c11741 | 837 | ath9k_hw_configpcipowersave(ah, true); |
203043f5 | 838 | |
c0c11741 | 839 | spin_unlock_bh(&sc->sc_pcu_lock); |
3867cf6a | 840 | |
c0c11741 | 841 | ath9k_ps_restore(sc); |
ff37e337 | 842 | |
781b14a3 | 843 | set_bit(SC_OP_INVALID, &sc->sc_flags); |
c0c11741 | 844 | sc->ps_idle = prev_idle; |
500c064d | 845 | |
141b38b6 S |
846 | mutex_unlock(&sc->mutex); |
847 | ||
d2182b69 | 848 | ath_dbg(common, CONFIG, "Driver halt\n"); |
f078f209 LR |
849 | } |
850 | ||
4801416c BG |
851 | bool ath9k_uses_beacons(int type) |
852 | { | |
853 | switch (type) { | |
854 | case NL80211_IFTYPE_AP: | |
855 | case NL80211_IFTYPE_ADHOC: | |
856 | case NL80211_IFTYPE_MESH_POINT: | |
857 | return true; | |
858 | default: | |
859 | return false; | |
860 | } | |
861 | } | |
862 | ||
4801416c BG |
863 | static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
864 | { | |
865 | struct ath9k_vif_iter_data *iter_data = data; | |
866 | int i; | |
867 | ||
868 | if (iter_data->hw_macaddr) | |
869 | for (i = 0; i < ETH_ALEN; i++) | |
870 | iter_data->mask[i] &= | |
871 | ~(iter_data->hw_macaddr[i] ^ mac[i]); | |
141b38b6 | 872 | |
1ed32e4f | 873 | switch (vif->type) { |
4801416c BG |
874 | case NL80211_IFTYPE_AP: |
875 | iter_data->naps++; | |
f078f209 | 876 | break; |
4801416c BG |
877 | case NL80211_IFTYPE_STATION: |
878 | iter_data->nstations++; | |
e51f3eff | 879 | break; |
05c914fe | 880 | case NL80211_IFTYPE_ADHOC: |
4801416c BG |
881 | iter_data->nadhocs++; |
882 | break; | |
9cb5412b | 883 | case NL80211_IFTYPE_MESH_POINT: |
4801416c BG |
884 | iter_data->nmeshes++; |
885 | break; | |
886 | case NL80211_IFTYPE_WDS: | |
887 | iter_data->nwds++; | |
f078f209 LR |
888 | break; |
889 | default: | |
4801416c | 890 | break; |
f078f209 | 891 | } |
4801416c | 892 | } |
f078f209 | 893 | |
6dcc3444 SM |
894 | static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
895 | { | |
896 | struct ath_softc *sc = data; | |
897 | struct ath_vif *avp = (void *)vif->drv_priv; | |
898 | ||
899 | if (vif->type != NL80211_IFTYPE_STATION) | |
900 | return; | |
901 | ||
902 | if (avp->primary_sta_vif) | |
903 | ath9k_set_assoc_state(sc, vif); | |
904 | } | |
905 | ||
4801416c BG |
906 | /* Called with sc->mutex held. */ |
907 | void ath9k_calculate_iter_data(struct ieee80211_hw *hw, | |
908 | struct ieee80211_vif *vif, | |
909 | struct ath9k_vif_iter_data *iter_data) | |
910 | { | |
9ac58615 | 911 | struct ath_softc *sc = hw->priv; |
4801416c BG |
912 | struct ath_hw *ah = sc->sc_ah; |
913 | struct ath_common *common = ath9k_hw_common(ah); | |
8feceb67 | 914 | |
4801416c BG |
915 | /* |
916 | * Use the hardware MAC address as reference, the hardware uses it | |
917 | * together with the BSSID mask when matching addresses. | |
918 | */ | |
919 | memset(iter_data, 0, sizeof(*iter_data)); | |
920 | iter_data->hw_macaddr = common->macaddr; | |
921 | memset(&iter_data->mask, 0xff, ETH_ALEN); | |
5640b08e | 922 | |
4801416c BG |
923 | if (vif) |
924 | ath9k_vif_iter(iter_data, vif->addr, vif); | |
925 | ||
926 | /* Get list of all active MAC addresses */ | |
4801416c BG |
927 | ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter, |
928 | iter_data); | |
4801416c | 929 | } |
8ca21f01 | 930 | |
4801416c BG |
931 | /* Called with sc->mutex held. */ |
932 | static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, | |
933 | struct ieee80211_vif *vif) | |
934 | { | |
9ac58615 | 935 | struct ath_softc *sc = hw->priv; |
4801416c BG |
936 | struct ath_hw *ah = sc->sc_ah; |
937 | struct ath_common *common = ath9k_hw_common(ah); | |
938 | struct ath9k_vif_iter_data iter_data; | |
6dcc3444 | 939 | enum nl80211_iftype old_opmode = ah->opmode; |
8ca21f01 | 940 | |
4801416c | 941 | ath9k_calculate_iter_data(hw, vif, &iter_data); |
2c3db3d5 | 942 | |
4801416c BG |
943 | memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); |
944 | ath_hw_setbssidmask(common); | |
945 | ||
4801416c | 946 | if (iter_data.naps > 0) { |
60ca9f87 | 947 | ath9k_hw_set_tsfadjust(ah, true); |
4801416c BG |
948 | ah->opmode = NL80211_IFTYPE_AP; |
949 | } else { | |
60ca9f87 | 950 | ath9k_hw_set_tsfadjust(ah, false); |
5640b08e | 951 | |
fd5999cf JC |
952 | if (iter_data.nmeshes) |
953 | ah->opmode = NL80211_IFTYPE_MESH_POINT; | |
954 | else if (iter_data.nwds) | |
4801416c BG |
955 | ah->opmode = NL80211_IFTYPE_AP; |
956 | else if (iter_data.nadhocs) | |
957 | ah->opmode = NL80211_IFTYPE_ADHOC; | |
958 | else | |
959 | ah->opmode = NL80211_IFTYPE_STATION; | |
960 | } | |
5640b08e | 961 | |
df35d29e SM |
962 | ath9k_hw_setopmode(ah); |
963 | ||
198823fd | 964 | if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) |
3069168c | 965 | ah->imask |= ATH9K_INT_TSFOOR; |
198823fd | 966 | else |
4801416c | 967 | ah->imask &= ~ATH9K_INT_TSFOOR; |
4af9cf4f | 968 | |
72d874c6 | 969 | ath9k_hw_set_interrupts(ah); |
6dcc3444 SM |
970 | |
971 | /* | |
972 | * If we are changing the opmode to STATION, | |
973 | * a beacon sync needs to be done. | |
974 | */ | |
975 | if (ah->opmode == NL80211_IFTYPE_STATION && | |
976 | old_opmode == NL80211_IFTYPE_AP && | |
977 | test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { | |
978 | ieee80211_iterate_active_interfaces_atomic(sc->hw, | |
979 | ath9k_sta_vif_iter, sc); | |
980 | } | |
4801416c | 981 | } |
6f255425 | 982 | |
4801416c BG |
983 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
984 | struct ieee80211_vif *vif) | |
6b3b991d | 985 | { |
9ac58615 | 986 | struct ath_softc *sc = hw->priv; |
4801416c BG |
987 | struct ath_hw *ah = sc->sc_ah; |
988 | struct ath_common *common = ath9k_hw_common(ah); | |
6b3b991d | 989 | |
4801416c | 990 | mutex_lock(&sc->mutex); |
6b3b991d | 991 | |
d2182b69 | 992 | ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); |
4801416c BG |
993 | sc->nvifs++; |
994 | ||
327967cb | 995 | ath9k_ps_wakeup(sc); |
130ef6e9 | 996 | ath9k_calculate_summary_state(hw, vif); |
327967cb MSS |
997 | ath9k_ps_restore(sc); |
998 | ||
130ef6e9 SM |
999 | if (ath9k_uses_beacons(vif->type)) |
1000 | ath9k_beacon_assign_slot(sc, vif); | |
1001 | ||
4801416c | 1002 | mutex_unlock(&sc->mutex); |
327967cb | 1003 | return 0; |
6b3b991d RM |
1004 | } |
1005 | ||
1006 | static int ath9k_change_interface(struct ieee80211_hw *hw, | |
1007 | struct ieee80211_vif *vif, | |
1008 | enum nl80211_iftype new_type, | |
1009 | bool p2p) | |
1010 | { | |
9ac58615 | 1011 | struct ath_softc *sc = hw->priv; |
6b3b991d RM |
1012 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1013 | ||
d2182b69 | 1014 | ath_dbg(common, CONFIG, "Change Interface\n"); |
6b3b991d | 1015 | mutex_lock(&sc->mutex); |
4801416c | 1016 | |
4801416c | 1017 | if (ath9k_uses_beacons(vif->type)) |
130ef6e9 | 1018 | ath9k_beacon_remove_slot(sc, vif); |
4801416c | 1019 | |
6b3b991d RM |
1020 | vif->type = new_type; |
1021 | vif->p2p = p2p; | |
1022 | ||
327967cb | 1023 | ath9k_ps_wakeup(sc); |
130ef6e9 | 1024 | ath9k_calculate_summary_state(hw, vif); |
327967cb MSS |
1025 | ath9k_ps_restore(sc); |
1026 | ||
130ef6e9 SM |
1027 | if (ath9k_uses_beacons(vif->type)) |
1028 | ath9k_beacon_assign_slot(sc, vif); | |
1029 | ||
6b3b991d | 1030 | mutex_unlock(&sc->mutex); |
327967cb | 1031 | return 0; |
6b3b991d RM |
1032 | } |
1033 | ||
8feceb67 | 1034 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1035 | struct ieee80211_vif *vif) |
f078f209 | 1036 | { |
9ac58615 | 1037 | struct ath_softc *sc = hw->priv; |
c46917bb | 1038 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
f078f209 | 1039 | |
d2182b69 | 1040 | ath_dbg(common, CONFIG, "Detach Interface\n"); |
f078f209 | 1041 | |
141b38b6 S |
1042 | mutex_lock(&sc->mutex); |
1043 | ||
4801416c | 1044 | sc->nvifs--; |
580f0b8a | 1045 | |
4801416c | 1046 | if (ath9k_uses_beacons(vif->type)) |
130ef6e9 | 1047 | ath9k_beacon_remove_slot(sc, vif); |
2c3db3d5 | 1048 | |
327967cb | 1049 | ath9k_ps_wakeup(sc); |
4801416c | 1050 | ath9k_calculate_summary_state(hw, NULL); |
327967cb | 1051 | ath9k_ps_restore(sc); |
141b38b6 S |
1052 | |
1053 | mutex_unlock(&sc->mutex); | |
f078f209 LR |
1054 | } |
1055 | ||
fbab7390 | 1056 | static void ath9k_enable_ps(struct ath_softc *sc) |
3f7c5c10 | 1057 | { |
3069168c | 1058 | struct ath_hw *ah = sc->sc_ah; |
ad128860 | 1059 | struct ath_common *common = ath9k_hw_common(ah); |
3069168c | 1060 | |
3f7c5c10 | 1061 | sc->ps_enabled = true; |
3069168c PR |
1062 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1063 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1064 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
72d874c6 | 1065 | ath9k_hw_set_interrupts(ah); |
3f7c5c10 | 1066 | } |
fdf76622 | 1067 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1068 | } |
ad128860 | 1069 | ath_dbg(common, PS, "PowerSave enabled\n"); |
3f7c5c10 SB |
1070 | } |
1071 | ||
845d708e SB |
1072 | static void ath9k_disable_ps(struct ath_softc *sc) |
1073 | { | |
1074 | struct ath_hw *ah = sc->sc_ah; | |
ad128860 | 1075 | struct ath_common *common = ath9k_hw_common(ah); |
845d708e SB |
1076 | |
1077 | sc->ps_enabled = false; | |
1078 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
1079 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | |
1080 | ath9k_hw_setrxabort(ah, 0); | |
1081 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | | |
1082 | PS_WAIT_FOR_CAB | | |
1083 | PS_WAIT_FOR_PSPOLL_DATA | | |
1084 | PS_WAIT_FOR_TX_ACK); | |
1085 | if (ah->imask & ATH9K_INT_TIM_TIMER) { | |
1086 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
72d874c6 | 1087 | ath9k_hw_set_interrupts(ah); |
845d708e SB |
1088 | } |
1089 | } | |
ad128860 | 1090 | ath_dbg(common, PS, "PowerSave disabled\n"); |
845d708e SB |
1091 | } |
1092 | ||
e8975581 | 1093 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1094 | { |
9ac58615 | 1095 | struct ath_softc *sc = hw->priv; |
3430098a FF |
1096 | struct ath_hw *ah = sc->sc_ah; |
1097 | struct ath_common *common = ath9k_hw_common(ah); | |
e8975581 | 1098 | struct ieee80211_conf *conf = &hw->conf; |
75600abf | 1099 | bool reset_channel = false; |
f078f209 | 1100 | |
c0c11741 | 1101 | ath9k_ps_wakeup(sc); |
aa33de09 | 1102 | mutex_lock(&sc->mutex); |
141b38b6 | 1103 | |
daa1b6ee | 1104 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
7545daf4 | 1105 | sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); |
b73f3e78 | 1106 | if (sc->ps_idle) { |
daa1b6ee | 1107 | ath_cancel_work(sc); |
b73f3e78 RM |
1108 | ath9k_stop_btcoex(sc); |
1109 | } else { | |
1110 | ath9k_start_btcoex(sc); | |
75600abf FF |
1111 | /* |
1112 | * The chip needs a reset to properly wake up from | |
1113 | * full sleep | |
1114 | */ | |
1115 | reset_channel = ah->chip_fullsleep; | |
b73f3e78 | 1116 | } |
daa1b6ee | 1117 | } |
64839170 | 1118 | |
e7824a50 LR |
1119 | /* |
1120 | * We just prepare to enable PS. We have to wait until our AP has | |
1121 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1122 | * those ACKs and end up retransmitting the same null data frames. | |
1123 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1124 | */ | |
3cbb5dd7 | 1125 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
8ab2cd09 LR |
1126 | unsigned long flags; |
1127 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
fbab7390 SB |
1128 | if (conf->flags & IEEE80211_CONF_PS) |
1129 | ath9k_enable_ps(sc); | |
845d708e SB |
1130 | else |
1131 | ath9k_disable_ps(sc); | |
8ab2cd09 | 1132 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
3cbb5dd7 VN |
1133 | } |
1134 | ||
199afd9d S |
1135 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1136 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
d2182b69 | 1137 | ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); |
5f841b41 RM |
1138 | sc->sc_ah->is_monitoring = true; |
1139 | } else { | |
d2182b69 | 1140 | ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); |
5f841b41 | 1141 | sc->sc_ah->is_monitoring = false; |
199afd9d S |
1142 | } |
1143 | } | |
1144 | ||
75600abf | 1145 | if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) { |
99405f93 | 1146 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 1147 | int pos = curchan->hw_value; |
3430098a FF |
1148 | int old_pos = -1; |
1149 | unsigned long flags; | |
1150 | ||
1151 | if (ah->curchan) | |
1152 | old_pos = ah->curchan - &ah->channels[0]; | |
ae5eb026 | 1153 | |
d2182b69 | 1154 | ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n", |
8c79a610 | 1155 | curchan->center_freq, conf->channel_type); |
f078f209 | 1156 | |
3430098a FF |
1157 | /* update survey stats for the old channel before switching */ |
1158 | spin_lock_irqsave(&common->cc_lock, flags); | |
1159 | ath_update_survey_stats(sc); | |
1160 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1161 | ||
e338a85e RM |
1162 | /* |
1163 | * Preserve the current channel values, before updating | |
1164 | * the same channel | |
1165 | */ | |
1a19f77f RM |
1166 | if (ah->curchan && (old_pos == pos)) |
1167 | ath9k_hw_getnf(ah, ah->curchan); | |
e338a85e RM |
1168 | |
1169 | ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos], | |
1170 | curchan, conf->channel_type); | |
1171 | ||
3430098a FF |
1172 | /* |
1173 | * If the operating channel changes, change the survey in-use flags | |
1174 | * along with it. | |
1175 | * Reset the survey data for the new channel, unless we're switching | |
1176 | * back to the operating channel from an off-channel operation. | |
1177 | */ | |
1178 | if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && | |
1179 | sc->cur_survey != &sc->survey[pos]) { | |
1180 | ||
1181 | if (sc->cur_survey) | |
1182 | sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; | |
1183 | ||
1184 | sc->cur_survey = &sc->survey[pos]; | |
1185 | ||
1186 | memset(sc->cur_survey, 0, sizeof(struct survey_info)); | |
1187 | sc->cur_survey->filled |= SURVEY_INFO_IN_USE; | |
1188 | } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { | |
1189 | memset(&sc->survey[pos], 0, sizeof(struct survey_info)); | |
1190 | } | |
1191 | ||
0e2dedf9 | 1192 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
3800276a | 1193 | ath_err(common, "Unable to set channel\n"); |
aa33de09 | 1194 | mutex_unlock(&sc->mutex); |
8389fb3f | 1195 | ath9k_ps_restore(sc); |
e11602b7 S |
1196 | return -EINVAL; |
1197 | } | |
3430098a FF |
1198 | |
1199 | /* | |
1200 | * The most recent snapshot of channel->noisefloor for the old | |
1201 | * channel is only available after the hardware reset. Copy it to | |
1202 | * the survey stats now. | |
1203 | */ | |
1204 | if (old_pos >= 0) | |
1205 | ath_update_survey_nf(sc, old_pos); | |
094d05dc | 1206 | } |
f078f209 | 1207 | |
c9f6a656 | 1208 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
d2182b69 | 1209 | ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level); |
17d7904d | 1210 | sc->config.txpowlimit = 2 * conf->power_level; |
5048e8c3 RM |
1211 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
1212 | sc->config.txpowlimit, &sc->curtxpow); | |
64839170 LR |
1213 | } |
1214 | ||
aa33de09 | 1215 | mutex_unlock(&sc->mutex); |
c0c11741 | 1216 | ath9k_ps_restore(sc); |
141b38b6 | 1217 | |
f078f209 LR |
1218 | return 0; |
1219 | } | |
1220 | ||
8feceb67 VT |
1221 | #define SUPPORTED_FILTERS \ |
1222 | (FIF_PROMISC_IN_BSS | \ | |
1223 | FIF_ALLMULTI | \ | |
1224 | FIF_CONTROL | \ | |
af6a3fc7 | 1225 | FIF_PSPOLL | \ |
8feceb67 VT |
1226 | FIF_OTHER_BSS | \ |
1227 | FIF_BCN_PRBRESP_PROMISC | \ | |
9c1d8e4a | 1228 | FIF_PROBE_REQ | \ |
8feceb67 | 1229 | FIF_FCSFAIL) |
c83be688 | 1230 | |
8feceb67 VT |
1231 | /* FIXME: sc->sc_full_reset ? */ |
1232 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1233 | unsigned int changed_flags, | |
1234 | unsigned int *total_flags, | |
3ac64bee | 1235 | u64 multicast) |
8feceb67 | 1236 | { |
9ac58615 | 1237 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1238 | u32 rfilt; |
f078f209 | 1239 | |
8feceb67 VT |
1240 | changed_flags &= SUPPORTED_FILTERS; |
1241 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1242 | |
b77f483f | 1243 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1244 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1245 | rfilt = ath_calcrxfilter(sc); |
1246 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1247 | ath9k_ps_restore(sc); |
f078f209 | 1248 | |
d2182b69 JP |
1249 | ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", |
1250 | rfilt); | |
8feceb67 | 1251 | } |
f078f209 | 1252 | |
4ca77860 JB |
1253 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1254 | struct ieee80211_vif *vif, | |
1255 | struct ieee80211_sta *sta) | |
8feceb67 | 1256 | { |
9ac58615 | 1257 | struct ath_softc *sc = hw->priv; |
93ae2dd2 FF |
1258 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1259 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1260 | struct ieee80211_key_conf ps_key = { }; | |
f078f209 | 1261 | |
7e1e3864 | 1262 | ath_node_attach(sc, sta, vif); |
f59a59fe FF |
1263 | |
1264 | if (vif->type != NL80211_IFTYPE_AP && | |
1265 | vif->type != NL80211_IFTYPE_AP_VLAN) | |
1266 | return 0; | |
1267 | ||
93ae2dd2 | 1268 | an->ps_key = ath_key_config(common, vif, sta, &ps_key); |
4ca77860 JB |
1269 | |
1270 | return 0; | |
1271 | } | |
1272 | ||
93ae2dd2 FF |
1273 | static void ath9k_del_ps_key(struct ath_softc *sc, |
1274 | struct ieee80211_vif *vif, | |
1275 | struct ieee80211_sta *sta) | |
1276 | { | |
1277 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1278 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1279 | struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; | |
1280 | ||
1281 | if (!an->ps_key) | |
1282 | return; | |
1283 | ||
1284 | ath_key_delete(common, &ps_key); | |
1285 | } | |
1286 | ||
4ca77860 JB |
1287 | static int ath9k_sta_remove(struct ieee80211_hw *hw, |
1288 | struct ieee80211_vif *vif, | |
1289 | struct ieee80211_sta *sta) | |
1290 | { | |
9ac58615 | 1291 | struct ath_softc *sc = hw->priv; |
4ca77860 | 1292 | |
93ae2dd2 | 1293 | ath9k_del_ps_key(sc, vif, sta); |
4ca77860 JB |
1294 | ath_node_detach(sc, sta); |
1295 | ||
1296 | return 0; | |
f078f209 LR |
1297 | } |
1298 | ||
5519541d FF |
1299 | static void ath9k_sta_notify(struct ieee80211_hw *hw, |
1300 | struct ieee80211_vif *vif, | |
1301 | enum sta_notify_cmd cmd, | |
1302 | struct ieee80211_sta *sta) | |
1303 | { | |
1304 | struct ath_softc *sc = hw->priv; | |
1305 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1306 | ||
3d4e20f2 | 1307 | if (!sta->ht_cap.ht_supported) |
b25bfda3 MSS |
1308 | return; |
1309 | ||
5519541d FF |
1310 | switch (cmd) { |
1311 | case STA_NOTIFY_SLEEP: | |
1312 | an->sleeping = true; | |
042ec453 | 1313 | ath_tx_aggr_sleep(sta, sc, an); |
5519541d FF |
1314 | break; |
1315 | case STA_NOTIFY_AWAKE: | |
1316 | an->sleeping = false; | |
1317 | ath_tx_aggr_wakeup(sc, an); | |
1318 | break; | |
1319 | } | |
1320 | } | |
1321 | ||
8a3a3c85 EP |
1322 | static int ath9k_conf_tx(struct ieee80211_hw *hw, |
1323 | struct ieee80211_vif *vif, u16 queue, | |
8feceb67 | 1324 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1325 | { |
9ac58615 | 1326 | struct ath_softc *sc = hw->priv; |
c46917bb | 1327 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
066dae93 | 1328 | struct ath_txq *txq; |
8feceb67 | 1329 | struct ath9k_tx_queue_info qi; |
066dae93 | 1330 | int ret = 0; |
f078f209 | 1331 | |
8feceb67 VT |
1332 | if (queue >= WME_NUM_AC) |
1333 | return 0; | |
f078f209 | 1334 | |
066dae93 FF |
1335 | txq = sc->tx.txq_map[queue]; |
1336 | ||
96f372c9 | 1337 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1338 | mutex_lock(&sc->mutex); |
1339 | ||
1ffb0610 S |
1340 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1341 | ||
8feceb67 VT |
1342 | qi.tqi_aifs = params->aifs; |
1343 | qi.tqi_cwmin = params->cw_min; | |
1344 | qi.tqi_cwmax = params->cw_max; | |
531bd079 | 1345 | qi.tqi_burstTime = params->txop * 32; |
f078f209 | 1346 | |
d2182b69 | 1347 | ath_dbg(common, CONFIG, |
226afe68 JP |
1348 | "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", |
1349 | queue, txq->axq_qnum, params->aifs, params->cw_min, | |
1350 | params->cw_max, params->txop); | |
f078f209 | 1351 | |
aa5955c3 | 1352 | ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); |
066dae93 | 1353 | ret = ath_txq_update(sc, txq->axq_qnum, &qi); |
8feceb67 | 1354 | if (ret) |
3800276a | 1355 | ath_err(common, "TXQ Update failed\n"); |
f078f209 | 1356 | |
141b38b6 | 1357 | mutex_unlock(&sc->mutex); |
96f372c9 | 1358 | ath9k_ps_restore(sc); |
141b38b6 | 1359 | |
8feceb67 VT |
1360 | return ret; |
1361 | } | |
f078f209 | 1362 | |
8feceb67 VT |
1363 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1364 | enum set_key_cmd cmd, | |
dc822b5d JB |
1365 | struct ieee80211_vif *vif, |
1366 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1367 | struct ieee80211_key_conf *key) |
1368 | { | |
9ac58615 | 1369 | struct ath_softc *sc = hw->priv; |
c46917bb | 1370 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1371 | int ret = 0; |
f078f209 | 1372 | |
3e6109c5 | 1373 | if (ath9k_modparam_nohwcrypt) |
b3bd89ce JM |
1374 | return -ENOSPC; |
1375 | ||
5bd5e9a6 CYY |
1376 | if ((vif->type == NL80211_IFTYPE_ADHOC || |
1377 | vif->type == NL80211_IFTYPE_MESH_POINT) && | |
cfdc9a8b JM |
1378 | (key->cipher == WLAN_CIPHER_SUITE_TKIP || |
1379 | key->cipher == WLAN_CIPHER_SUITE_CCMP) && | |
1380 | !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { | |
1381 | /* | |
1382 | * For now, disable hw crypto for the RSN IBSS group keys. This | |
1383 | * could be optimized in the future to use a modified key cache | |
1384 | * design to support per-STA RX GTK, but until that gets | |
1385 | * implemented, use of software crypto for group addressed | |
1386 | * frames is a acceptable to allow RSN IBSS to be used. | |
1387 | */ | |
1388 | return -EOPNOTSUPP; | |
1389 | } | |
1390 | ||
141b38b6 | 1391 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1392 | ath9k_ps_wakeup(sc); |
d2182b69 | 1393 | ath_dbg(common, CONFIG, "Set HW Key\n"); |
f078f209 | 1394 | |
8feceb67 VT |
1395 | switch (cmd) { |
1396 | case SET_KEY: | |
93ae2dd2 FF |
1397 | if (sta) |
1398 | ath9k_del_ps_key(sc, vif, sta); | |
1399 | ||
040e539e | 1400 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1401 | if (ret >= 0) { |
1402 | key->hw_key_idx = ret; | |
8feceb67 VT |
1403 | /* push IV and Michael MIC generation to stack */ |
1404 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
97359d12 | 1405 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) |
8feceb67 | 1406 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
97359d12 JB |
1407 | if (sc->sc_ah->sw_mgmt_crypto && |
1408 | key->cipher == WLAN_CIPHER_SUITE_CCMP) | |
e548c49e | 1409 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; |
6ace2891 | 1410 | ret = 0; |
8feceb67 VT |
1411 | } |
1412 | break; | |
1413 | case DISABLE_KEY: | |
040e539e | 1414 | ath_key_delete(common, key); |
8feceb67 VT |
1415 | break; |
1416 | default: | |
1417 | ret = -EINVAL; | |
1418 | } | |
f078f209 | 1419 | |
3cbb5dd7 | 1420 | ath9k_ps_restore(sc); |
141b38b6 S |
1421 | mutex_unlock(&sc->mutex); |
1422 | ||
8feceb67 VT |
1423 | return ret; |
1424 | } | |
6c43c090 SM |
1425 | |
1426 | static void ath9k_set_assoc_state(struct ath_softc *sc, | |
1427 | struct ieee80211_vif *vif) | |
4f5ef75b | 1428 | { |
4f5ef75b | 1429 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4f5ef75b | 1430 | struct ath_vif *avp = (void *)vif->drv_priv; |
6c43c090 | 1431 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; |
07c15a3f | 1432 | unsigned long flags; |
6c43c090 SM |
1433 | |
1434 | set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); | |
1435 | avp->primary_sta_vif = true; | |
1436 | ||
2e5ef459 | 1437 | /* |
6c43c090 SM |
1438 | * Set the AID, BSSID and do beacon-sync only when |
1439 | * the HW opmode is STATION. | |
1440 | * | |
1441 | * But the primary bit is set above in any case. | |
2e5ef459 | 1442 | */ |
6c43c090 | 1443 | if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) |
2e5ef459 RM |
1444 | return; |
1445 | ||
6c43c090 SM |
1446 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); |
1447 | common->curaid = bss_conf->aid; | |
1448 | ath9k_hw_write_associd(sc->sc_ah); | |
07c15a3f | 1449 | |
6c43c090 SM |
1450 | sc->last_rssi = ATH_RSSI_DUMMY_MARKER; |
1451 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; | |
99e4d43a | 1452 | |
6c43c090 SM |
1453 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
1454 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
1455 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
05c0be2f | 1456 | |
50072ebc RM |
1457 | if (ath9k_hw_mci_is_enabled(sc->sc_ah)) |
1458 | ath9k_mci_update_wlan_channels(sc, false); | |
1459 | ||
6c43c090 SM |
1460 | ath_dbg(common, CONFIG, |
1461 | "Primary Station interface: %pM, BSSID: %pM\n", | |
1462 | vif->addr, common->curbssid); | |
4f5ef75b RM |
1463 | } |
1464 | ||
6c43c090 | 1465 | static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
4f5ef75b | 1466 | { |
6c43c090 | 1467 | struct ath_softc *sc = data; |
4f5ef75b | 1468 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; |
4f5ef75b | 1469 | |
6c43c090 | 1470 | if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) |
2e5ef459 RM |
1471 | return; |
1472 | ||
6c43c090 SM |
1473 | if (bss_conf->assoc) |
1474 | ath9k_set_assoc_state(sc, vif); | |
4f5ef75b | 1475 | } |
f078f209 | 1476 | |
8feceb67 VT |
1477 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1478 | struct ieee80211_vif *vif, | |
1479 | struct ieee80211_bss_conf *bss_conf, | |
1480 | u32 changed) | |
1481 | { | |
da0d45f7 SM |
1482 | #define CHECK_ANI \ |
1483 | (BSS_CHANGED_ASSOC | \ | |
1484 | BSS_CHANGED_IBSS | \ | |
1485 | BSS_CHANGED_BEACON_ENABLED) | |
1486 | ||
9ac58615 | 1487 | struct ath_softc *sc = hw->priv; |
2d0ddec5 | 1488 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1489 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1490 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1491 | int slottime; |
f078f209 | 1492 | |
96f372c9 | 1493 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1494 | mutex_lock(&sc->mutex); |
1495 | ||
9f61903c | 1496 | if (changed & BSS_CHANGED_ASSOC) { |
6c43c090 SM |
1497 | ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", |
1498 | bss_conf->bssid, bss_conf->assoc); | |
1499 | ||
1500 | if (avp->primary_sta_vif && !bss_conf->assoc) { | |
1501 | clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags); | |
1502 | avp->primary_sta_vif = false; | |
1503 | ||
1504 | if (ah->opmode == NL80211_IFTYPE_STATION) | |
1505 | clear_bit(SC_OP_BEACONS, &sc->sc_flags); | |
1506 | } | |
1507 | ||
1508 | ieee80211_iterate_active_interfaces_atomic(sc->hw, | |
1509 | ath9k_bss_assoc_iter, sc); | |
2d0ddec5 | 1510 | |
6c43c090 SM |
1511 | if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) && |
1512 | ah->opmode == NL80211_IFTYPE_STATION) { | |
1513 | memset(common->curbssid, 0, ETH_ALEN); | |
1514 | common->curaid = 0; | |
1515 | ath9k_hw_write_associd(sc->sc_ah); | |
50072ebc RM |
1516 | if (ath9k_hw_mci_is_enabled(sc->sc_ah)) |
1517 | ath9k_mci_update_wlan_channels(sc, true); | |
6c43c090 | 1518 | } |
c6089ccc | 1519 | } |
2d0ddec5 | 1520 | |
2e5ef459 | 1521 | if (changed & BSS_CHANGED_IBSS) { |
2e5ef459 RM |
1522 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); |
1523 | common->curaid = bss_conf->aid; | |
1524 | ath9k_hw_write_associd(sc->sc_ah); | |
2e5ef459 RM |
1525 | } |
1526 | ||
ef4ad633 SM |
1527 | if ((changed & BSS_CHANGED_BEACON_ENABLED) || |
1528 | (changed & BSS_CHANGED_BEACON_INT)) { | |
2f8e82e8 SM |
1529 | if (ah->opmode == NL80211_IFTYPE_AP && |
1530 | bss_conf->enable_beacon) | |
1531 | ath9k_set_tsfadjust(sc, vif); | |
ef4ad633 SM |
1532 | if (ath9k_allow_beacon_config(sc, vif)) |
1533 | ath9k_beacon_config(sc, vif, changed); | |
0005baf4 FF |
1534 | } |
1535 | ||
1536 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
1537 | if (bss_conf->use_short_slot) | |
1538 | slottime = 9; | |
1539 | else | |
1540 | slottime = 20; | |
1541 | if (vif->type == NL80211_IFTYPE_AP) { | |
1542 | /* | |
1543 | * Defer update, so that connected stations can adjust | |
1544 | * their settings at the same time. | |
1545 | * See beacon.c for more details | |
1546 | */ | |
1547 | sc->beacon.slottime = slottime; | |
1548 | sc->beacon.updateslot = UPDATE; | |
1549 | } else { | |
1550 | ah->slottime = slottime; | |
1551 | ath9k_hw_init_global_settings(ah); | |
1552 | } | |
2d0ddec5 JB |
1553 | } |
1554 | ||
da0d45f7 SM |
1555 | if (changed & CHECK_ANI) |
1556 | ath_check_ani(sc); | |
1557 | ||
141b38b6 | 1558 | mutex_unlock(&sc->mutex); |
96f372c9 | 1559 | ath9k_ps_restore(sc); |
da0d45f7 SM |
1560 | |
1561 | #undef CHECK_ANI | |
8feceb67 | 1562 | } |
f078f209 | 1563 | |
37a41b4a | 1564 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 1565 | { |
9ac58615 | 1566 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1567 | u64 tsf; |
f078f209 | 1568 | |
141b38b6 | 1569 | mutex_lock(&sc->mutex); |
9abbfb27 | 1570 | ath9k_ps_wakeup(sc); |
141b38b6 | 1571 | tsf = ath9k_hw_gettsf64(sc->sc_ah); |
9abbfb27 | 1572 | ath9k_ps_restore(sc); |
141b38b6 | 1573 | mutex_unlock(&sc->mutex); |
f078f209 | 1574 | |
8feceb67 VT |
1575 | return tsf; |
1576 | } | |
f078f209 | 1577 | |
37a41b4a EP |
1578 | static void ath9k_set_tsf(struct ieee80211_hw *hw, |
1579 | struct ieee80211_vif *vif, | |
1580 | u64 tsf) | |
3b5d665b | 1581 | { |
9ac58615 | 1582 | struct ath_softc *sc = hw->priv; |
3b5d665b | 1583 | |
141b38b6 | 1584 | mutex_lock(&sc->mutex); |
9abbfb27 | 1585 | ath9k_ps_wakeup(sc); |
141b38b6 | 1586 | ath9k_hw_settsf64(sc->sc_ah, tsf); |
9abbfb27 | 1587 | ath9k_ps_restore(sc); |
141b38b6 | 1588 | mutex_unlock(&sc->mutex); |
3b5d665b AF |
1589 | } |
1590 | ||
37a41b4a | 1591 | static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 1592 | { |
9ac58615 | 1593 | struct ath_softc *sc = hw->priv; |
c83be688 | 1594 | |
141b38b6 | 1595 | mutex_lock(&sc->mutex); |
21526d57 LR |
1596 | |
1597 | ath9k_ps_wakeup(sc); | |
141b38b6 | 1598 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
1599 | ath9k_ps_restore(sc); |
1600 | ||
141b38b6 | 1601 | mutex_unlock(&sc->mutex); |
8feceb67 | 1602 | } |
f078f209 | 1603 | |
8feceb67 | 1604 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 1605 | struct ieee80211_vif *vif, |
141b38b6 S |
1606 | enum ieee80211_ampdu_mlme_action action, |
1607 | struct ieee80211_sta *sta, | |
0b01f030 | 1608 | u16 tid, u16 *ssn, u8 buf_size) |
8feceb67 | 1609 | { |
9ac58615 | 1610 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1611 | int ret = 0; |
f078f209 | 1612 | |
85ad181e JB |
1613 | local_bh_disable(); |
1614 | ||
8feceb67 VT |
1615 | switch (action) { |
1616 | case IEEE80211_AMPDU_RX_START: | |
8feceb67 VT |
1617 | break; |
1618 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
1619 | break; |
1620 | case IEEE80211_AMPDU_TX_START: | |
8b685ba9 | 1621 | ath9k_ps_wakeup(sc); |
231c3a1f FF |
1622 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
1623 | if (!ret) | |
1624 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
8b685ba9 | 1625 | ath9k_ps_restore(sc); |
8feceb67 VT |
1626 | break; |
1627 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 1628 | ath9k_ps_wakeup(sc); |
f83da965 | 1629 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 1630 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1631 | ath9k_ps_restore(sc); |
8feceb67 | 1632 | break; |
b1720231 | 1633 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 1634 | ath9k_ps_wakeup(sc); |
8469cdef | 1635 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 1636 | ath9k_ps_restore(sc); |
8469cdef | 1637 | break; |
8feceb67 | 1638 | default: |
3800276a | 1639 | ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); |
8feceb67 VT |
1640 | } |
1641 | ||
85ad181e JB |
1642 | local_bh_enable(); |
1643 | ||
8feceb67 | 1644 | return ret; |
f078f209 LR |
1645 | } |
1646 | ||
62dad5b0 BP |
1647 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
1648 | struct survey_info *survey) | |
1649 | { | |
9ac58615 | 1650 | struct ath_softc *sc = hw->priv; |
3430098a | 1651 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39162dbe | 1652 | struct ieee80211_supported_band *sband; |
3430098a FF |
1653 | struct ieee80211_channel *chan; |
1654 | unsigned long flags; | |
1655 | int pos; | |
1656 | ||
1657 | spin_lock_irqsave(&common->cc_lock, flags); | |
1658 | if (idx == 0) | |
1659 | ath_update_survey_stats(sc); | |
39162dbe FF |
1660 | |
1661 | sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; | |
1662 | if (sband && idx >= sband->n_channels) { | |
1663 | idx -= sband->n_channels; | |
1664 | sband = NULL; | |
1665 | } | |
62dad5b0 | 1666 | |
39162dbe FF |
1667 | if (!sband) |
1668 | sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; | |
62dad5b0 | 1669 | |
3430098a FF |
1670 | if (!sband || idx >= sband->n_channels) { |
1671 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1672 | return -ENOENT; | |
4f1a5a4b | 1673 | } |
62dad5b0 | 1674 | |
3430098a FF |
1675 | chan = &sband->channels[idx]; |
1676 | pos = chan->hw_value; | |
1677 | memcpy(survey, &sc->survey[pos], sizeof(*survey)); | |
1678 | survey->channel = chan; | |
1679 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1680 | ||
62dad5b0 BP |
1681 | return 0; |
1682 | } | |
1683 | ||
e239d859 FF |
1684 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
1685 | { | |
9ac58615 | 1686 | struct ath_softc *sc = hw->priv; |
e239d859 FF |
1687 | struct ath_hw *ah = sc->sc_ah; |
1688 | ||
1689 | mutex_lock(&sc->mutex); | |
1690 | ah->coverage_class = coverage_class; | |
8b2a3827 MSS |
1691 | |
1692 | ath9k_ps_wakeup(sc); | |
e239d859 | 1693 | ath9k_hw_init_global_settings(ah); |
8b2a3827 MSS |
1694 | ath9k_ps_restore(sc); |
1695 | ||
e239d859 FF |
1696 | mutex_unlock(&sc->mutex); |
1697 | } | |
1698 | ||
69081624 VT |
1699 | static void ath9k_flush(struct ieee80211_hw *hw, bool drop) |
1700 | { | |
69081624 | 1701 | struct ath_softc *sc = hw->priv; |
99aa55b6 MSS |
1702 | struct ath_hw *ah = sc->sc_ah; |
1703 | struct ath_common *common = ath9k_hw_common(ah); | |
86271e46 FF |
1704 | int timeout = 200; /* ms */ |
1705 | int i, j; | |
2f6fc351 | 1706 | bool drain_txq; |
69081624 VT |
1707 | |
1708 | mutex_lock(&sc->mutex); | |
69081624 VT |
1709 | cancel_delayed_work_sync(&sc->tx_complete_work); |
1710 | ||
6a6b3f3e | 1711 | if (ah->ah_flags & AH_UNPLUGGED) { |
d2182b69 | 1712 | ath_dbg(common, ANY, "Device has been unplugged!\n"); |
6a6b3f3e MSS |
1713 | mutex_unlock(&sc->mutex); |
1714 | return; | |
1715 | } | |
1716 | ||
781b14a3 | 1717 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { |
d2182b69 | 1718 | ath_dbg(common, ANY, "Device not present\n"); |
99aa55b6 MSS |
1719 | mutex_unlock(&sc->mutex); |
1720 | return; | |
1721 | } | |
1722 | ||
86271e46 | 1723 | for (j = 0; j < timeout; j++) { |
108697c4 | 1724 | bool npend = false; |
86271e46 FF |
1725 | |
1726 | if (j) | |
1727 | usleep_range(1000, 2000); | |
69081624 | 1728 | |
86271e46 FF |
1729 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
1730 | if (!ATH_TXQ_SETUP(sc, i)) | |
1731 | continue; | |
1732 | ||
108697c4 MSS |
1733 | npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); |
1734 | ||
1735 | if (npend) | |
1736 | break; | |
69081624 | 1737 | } |
86271e46 FF |
1738 | |
1739 | if (!npend) | |
9df0d6a2 | 1740 | break; |
69081624 VT |
1741 | } |
1742 | ||
9df0d6a2 FF |
1743 | if (drop) { |
1744 | ath9k_ps_wakeup(sc); | |
1745 | spin_lock_bh(&sc->sc_pcu_lock); | |
1746 | drain_txq = ath_drain_all_txq(sc, false); | |
1747 | spin_unlock_bh(&sc->sc_pcu_lock); | |
9adcf440 | 1748 | |
9df0d6a2 FF |
1749 | if (!drain_txq) |
1750 | ath_reset(sc, false); | |
9adcf440 | 1751 | |
9df0d6a2 FF |
1752 | ath9k_ps_restore(sc); |
1753 | ieee80211_wake_queues(hw); | |
1754 | } | |
d78f4b3e | 1755 | |
69081624 VT |
1756 | ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); |
1757 | mutex_unlock(&sc->mutex); | |
1758 | } | |
1759 | ||
15b91e83 VN |
1760 | static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) |
1761 | { | |
1762 | struct ath_softc *sc = hw->priv; | |
1763 | int i; | |
1764 | ||
1765 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1766 | if (!ATH_TXQ_SETUP(sc, i)) | |
1767 | continue; | |
1768 | ||
1769 | if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) | |
1770 | return true; | |
1771 | } | |
1772 | return false; | |
1773 | } | |
1774 | ||
5595f119 | 1775 | static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) |
ba4903f9 FF |
1776 | { |
1777 | struct ath_softc *sc = hw->priv; | |
1778 | struct ath_hw *ah = sc->sc_ah; | |
1779 | struct ieee80211_vif *vif; | |
1780 | struct ath_vif *avp; | |
1781 | struct ath_buf *bf; | |
1782 | struct ath_tx_status ts; | |
4286df60 | 1783 | bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); |
ba4903f9 FF |
1784 | int status; |
1785 | ||
1786 | vif = sc->beacon.bslot[0]; | |
1787 | if (!vif) | |
1788 | return 0; | |
1789 | ||
aa45fe96 | 1790 | if (!vif->bss_conf.enable_beacon) |
ba4903f9 FF |
1791 | return 0; |
1792 | ||
aa45fe96 SM |
1793 | avp = (void *)vif->drv_priv; |
1794 | ||
4286df60 | 1795 | if (!sc->beacon.tx_processed && !edma) { |
ba4903f9 FF |
1796 | tasklet_disable(&sc->bcon_tasklet); |
1797 | ||
1798 | bf = avp->av_bcbuf; | |
1799 | if (!bf || !bf->bf_mpdu) | |
1800 | goto skip; | |
1801 | ||
1802 | status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); | |
1803 | if (status == -EINPROGRESS) | |
1804 | goto skip; | |
1805 | ||
1806 | sc->beacon.tx_processed = true; | |
1807 | sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); | |
1808 | ||
1809 | skip: | |
1810 | tasklet_enable(&sc->bcon_tasklet); | |
1811 | } | |
1812 | ||
1813 | return sc->beacon.tx_last; | |
1814 | } | |
1815 | ||
52c94f41 MSS |
1816 | static int ath9k_get_stats(struct ieee80211_hw *hw, |
1817 | struct ieee80211_low_level_stats *stats) | |
1818 | { | |
1819 | struct ath_softc *sc = hw->priv; | |
1820 | struct ath_hw *ah = sc->sc_ah; | |
1821 | struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; | |
1822 | ||
1823 | stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; | |
1824 | stats->dot11RTSFailureCount = mib_stats->rts_bad; | |
1825 | stats->dot11FCSErrorCount = mib_stats->fcs_bad; | |
1826 | stats->dot11RTSSuccessCount = mib_stats->rts_good; | |
1827 | return 0; | |
1828 | } | |
1829 | ||
43c35284 FF |
1830 | static u32 fill_chainmask(u32 cap, u32 new) |
1831 | { | |
1832 | u32 filled = 0; | |
1833 | int i; | |
1834 | ||
1835 | for (i = 0; cap && new; i++, cap >>= 1) { | |
1836 | if (!(cap & BIT(0))) | |
1837 | continue; | |
1838 | ||
1839 | if (new & BIT(0)) | |
1840 | filled |= BIT(i); | |
1841 | ||
1842 | new >>= 1; | |
1843 | } | |
1844 | ||
1845 | return filled; | |
1846 | } | |
1847 | ||
5d9c7e3c FF |
1848 | static bool validate_antenna_mask(struct ath_hw *ah, u32 val) |
1849 | { | |
1850 | switch (val & 0x7) { | |
1851 | case 0x1: | |
1852 | case 0x3: | |
1853 | case 0x7: | |
1854 | return true; | |
1855 | case 0x2: | |
1856 | return (ah->caps.rx_chainmask == 1); | |
1857 | default: | |
1858 | return false; | |
1859 | } | |
1860 | } | |
1861 | ||
43c35284 FF |
1862 | static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) |
1863 | { | |
1864 | struct ath_softc *sc = hw->priv; | |
1865 | struct ath_hw *ah = sc->sc_ah; | |
1866 | ||
5d9c7e3c FF |
1867 | if (ah->caps.rx_chainmask != 1) |
1868 | rx_ant |= tx_ant; | |
1869 | ||
1870 | if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) | |
43c35284 FF |
1871 | return -EINVAL; |
1872 | ||
1873 | sc->ant_rx = rx_ant; | |
1874 | sc->ant_tx = tx_ant; | |
1875 | ||
1876 | if (ah->caps.rx_chainmask == 1) | |
1877 | return 0; | |
1878 | ||
1879 | /* AR9100 runs into calibration issues if not all rx chains are enabled */ | |
1880 | if (AR_SREV_9100(ah)) | |
1881 | ah->rxchainmask = 0x7; | |
1882 | else | |
1883 | ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); | |
1884 | ||
1885 | ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); | |
1886 | ath9k_reload_chainmask_settings(sc); | |
1887 | ||
1888 | return 0; | |
1889 | } | |
1890 | ||
1891 | static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) | |
1892 | { | |
1893 | struct ath_softc *sc = hw->priv; | |
1894 | ||
1895 | *tx_ant = sc->ant_tx; | |
1896 | *rx_ant = sc->ant_rx; | |
1897 | return 0; | |
1898 | } | |
1899 | ||
b90bd9d1 BG |
1900 | #ifdef CONFIG_ATH9K_DEBUGFS |
1901 | ||
1902 | /* Ethtool support for get-stats */ | |
1903 | ||
1904 | #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO" | |
1905 | static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = { | |
1906 | "tx_pkts_nic", | |
1907 | "tx_bytes_nic", | |
1908 | "rx_pkts_nic", | |
1909 | "rx_bytes_nic", | |
1910 | AMKSTR(d_tx_pkts), | |
1911 | AMKSTR(d_tx_bytes), | |
1912 | AMKSTR(d_tx_mpdus_queued), | |
1913 | AMKSTR(d_tx_mpdus_completed), | |
1914 | AMKSTR(d_tx_mpdu_xretries), | |
1915 | AMKSTR(d_tx_aggregates), | |
1916 | AMKSTR(d_tx_ampdus_queued_hw), | |
1917 | AMKSTR(d_tx_ampdus_queued_sw), | |
1918 | AMKSTR(d_tx_ampdus_completed), | |
1919 | AMKSTR(d_tx_ampdu_retries), | |
1920 | AMKSTR(d_tx_ampdu_xretries), | |
1921 | AMKSTR(d_tx_fifo_underrun), | |
1922 | AMKSTR(d_tx_op_exceeded), | |
1923 | AMKSTR(d_tx_timer_expiry), | |
1924 | AMKSTR(d_tx_desc_cfg_err), | |
1925 | AMKSTR(d_tx_data_underrun), | |
1926 | AMKSTR(d_tx_delim_underrun), | |
1927 | ||
1928 | "d_rx_decrypt_crc_err", | |
1929 | "d_rx_phy_err", | |
1930 | "d_rx_mic_err", | |
1931 | "d_rx_pre_delim_crc_err", | |
1932 | "d_rx_post_delim_crc_err", | |
1933 | "d_rx_decrypt_busy_err", | |
1934 | ||
1935 | "d_rx_phyerr_radar", | |
1936 | "d_rx_phyerr_ofdm_timing", | |
1937 | "d_rx_phyerr_cck_timing", | |
1938 | ||
1939 | }; | |
1940 | #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats) | |
1941 | ||
1942 | static void ath9k_get_et_strings(struct ieee80211_hw *hw, | |
1943 | struct ieee80211_vif *vif, | |
1944 | u32 sset, u8 *data) | |
1945 | { | |
1946 | if (sset == ETH_SS_STATS) | |
1947 | memcpy(data, *ath9k_gstrings_stats, | |
1948 | sizeof(ath9k_gstrings_stats)); | |
1949 | } | |
1950 | ||
1951 | static int ath9k_get_et_sset_count(struct ieee80211_hw *hw, | |
1952 | struct ieee80211_vif *vif, int sset) | |
1953 | { | |
1954 | if (sset == ETH_SS_STATS) | |
1955 | return ATH9K_SSTATS_LEN; | |
1956 | return 0; | |
1957 | } | |
1958 | ||
1959 | #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum) | |
1960 | #define AWDATA(elem) \ | |
1961 | do { \ | |
1962 | data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \ | |
1963 | data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \ | |
1964 | data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \ | |
1965 | data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \ | |
1966 | } while (0) | |
1967 | ||
1968 | #define AWDATA_RX(elem) \ | |
1969 | do { \ | |
1970 | data[i++] = sc->debug.stats.rxstats.elem; \ | |
1971 | } while (0) | |
1972 | ||
1973 | static void ath9k_get_et_stats(struct ieee80211_hw *hw, | |
1974 | struct ieee80211_vif *vif, | |
1975 | struct ethtool_stats *stats, u64 *data) | |
1976 | { | |
1977 | struct ath_softc *sc = hw->priv; | |
1978 | int i = 0; | |
1979 | ||
1980 | data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all + | |
1981 | sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all + | |
1982 | sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all + | |
1983 | sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all); | |
1984 | data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all + | |
1985 | sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all + | |
1986 | sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all + | |
1987 | sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all); | |
1988 | AWDATA_RX(rx_pkts_all); | |
1989 | AWDATA_RX(rx_bytes_all); | |
1990 | ||
1991 | AWDATA(tx_pkts_all); | |
1992 | AWDATA(tx_bytes_all); | |
1993 | AWDATA(queued); | |
1994 | AWDATA(completed); | |
1995 | AWDATA(xretries); | |
1996 | AWDATA(a_aggr); | |
1997 | AWDATA(a_queued_hw); | |
1998 | AWDATA(a_queued_sw); | |
1999 | AWDATA(a_completed); | |
2000 | AWDATA(a_retries); | |
2001 | AWDATA(a_xretries); | |
2002 | AWDATA(fifo_underrun); | |
2003 | AWDATA(xtxop); | |
2004 | AWDATA(timer_exp); | |
2005 | AWDATA(desc_cfg_err); | |
2006 | AWDATA(data_underrun); | |
2007 | AWDATA(delim_underrun); | |
2008 | ||
2009 | AWDATA_RX(decrypt_crc_err); | |
2010 | AWDATA_RX(phy_err); | |
2011 | AWDATA_RX(mic_err); | |
2012 | AWDATA_RX(pre_delim_crc_err); | |
2013 | AWDATA_RX(post_delim_crc_err); | |
2014 | AWDATA_RX(decrypt_busy_err); | |
2015 | ||
2016 | AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]); | |
2017 | AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]); | |
2018 | AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]); | |
2019 | ||
2020 | WARN_ON(i != ATH9K_SSTATS_LEN); | |
2021 | } | |
2022 | ||
2023 | /* End of ethtool get-stats functions */ | |
2024 | ||
2025 | #endif | |
2026 | ||
2027 | ||
b11e640a MSS |
2028 | #ifdef CONFIG_PM_SLEEP |
2029 | ||
2030 | static void ath9k_wow_map_triggers(struct ath_softc *sc, | |
2031 | struct cfg80211_wowlan *wowlan, | |
2032 | u32 *wow_triggers) | |
2033 | { | |
2034 | if (wowlan->disconnect) | |
2035 | *wow_triggers |= AH_WOW_LINK_CHANGE | | |
2036 | AH_WOW_BEACON_MISS; | |
2037 | if (wowlan->magic_pkt) | |
2038 | *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN; | |
2039 | ||
2040 | if (wowlan->n_patterns) | |
2041 | *wow_triggers |= AH_WOW_USER_PATTERN_EN; | |
2042 | ||
2043 | sc->wow_enabled = *wow_triggers; | |
2044 | ||
2045 | } | |
2046 | ||
2047 | static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc) | |
2048 | { | |
2049 | struct ath_hw *ah = sc->sc_ah; | |
2050 | struct ath_common *common = ath9k_hw_common(ah); | |
2051 | struct ath9k_hw_capabilities *pcaps = &ah->caps; | |
2052 | int pattern_count = 0; | |
2053 | int i, byte_cnt; | |
2054 | u8 dis_deauth_pattern[MAX_PATTERN_SIZE]; | |
2055 | u8 dis_deauth_mask[MAX_PATTERN_SIZE]; | |
2056 | ||
2057 | memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE); | |
2058 | memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE); | |
2059 | ||
2060 | /* | |
2061 | * Create Dissassociate / Deauthenticate packet filter | |
2062 | * | |
2063 | * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes | |
2064 | * +--------------+----------+---------+--------+--------+---- | |
2065 | * + Frame Control+ Duration + DA + SA + BSSID + | |
2066 | * +--------------+----------+---------+--------+--------+---- | |
2067 | * | |
2068 | * The above is the management frame format for disassociate/ | |
2069 | * deauthenticate pattern, from this we need to match the first byte | |
2070 | * of 'Frame Control' and DA, SA, and BSSID fields | |
2071 | * (skipping 2nd byte of FC and Duration feild. | |
2072 | * | |
2073 | * Disassociate pattern | |
2074 | * -------------------- | |
2075 | * Frame control = 00 00 1010 | |
2076 | * DA, SA, BSSID = x:x:x:x:x:x | |
2077 | * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x | |
2078 | * | x:x:x:x:x:x -- 22 bytes | |
2079 | * | |
2080 | * Deauthenticate pattern | |
2081 | * ---------------------- | |
2082 | * Frame control = 00 00 1100 | |
2083 | * DA, SA, BSSID = x:x:x:x:x:x | |
2084 | * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x | |
2085 | * | x:x:x:x:x:x -- 22 bytes | |
2086 | */ | |
2087 | ||
2088 | /* Create Disassociate Pattern first */ | |
2089 | ||
2090 | byte_cnt = 0; | |
2091 | ||
2092 | /* Fill out the mask with all FF's */ | |
2093 | ||
2094 | for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++) | |
2095 | dis_deauth_mask[i] = 0xff; | |
2096 | ||
2097 | /* copy the first byte of frame control field */ | |
2098 | dis_deauth_pattern[byte_cnt] = 0xa0; | |
2099 | byte_cnt++; | |
2100 | ||
2101 | /* skip 2nd byte of frame control and Duration field */ | |
2102 | byte_cnt += 3; | |
2103 | ||
2104 | /* | |
2105 | * need not match the destination mac address, it can be a broadcast | |
2106 | * mac address or an unicast to this station | |
2107 | */ | |
2108 | byte_cnt += 6; | |
2109 | ||
2110 | /* copy the source mac address */ | |
2111 | memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN); | |
2112 | ||
2113 | byte_cnt += 6; | |
2114 | ||
2115 | /* copy the bssid, its same as the source mac address */ | |
2116 | ||
2117 | memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN); | |
2118 | ||
2119 | /* Create Disassociate pattern mask */ | |
2120 | ||
2121 | if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) { | |
2122 | ||
2123 | if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) { | |
2124 | /* | |
2125 | * for AR9280, because of hardware limitation, the | |
2126 | * first 4 bytes have to be matched for all patterns. | |
2127 | * the mask for disassociation and de-auth pattern | |
2128 | * matching need to enable the first 4 bytes. | |
2129 | * also the duration field needs to be filled. | |
2130 | */ | |
2131 | dis_deauth_mask[0] = 0xf0; | |
2132 | ||
2133 | /* | |
2134 | * fill in duration field | |
2135 | FIXME: what is the exact value ? | |
2136 | */ | |
2137 | dis_deauth_pattern[2] = 0xff; | |
2138 | dis_deauth_pattern[3] = 0xff; | |
2139 | } else { | |
2140 | dis_deauth_mask[0] = 0xfe; | |
2141 | } | |
2142 | ||
2143 | dis_deauth_mask[1] = 0x03; | |
2144 | dis_deauth_mask[2] = 0xc0; | |
2145 | } else { | |
2146 | dis_deauth_mask[0] = 0xef; | |
2147 | dis_deauth_mask[1] = 0x3f; | |
2148 | dis_deauth_mask[2] = 0x00; | |
2149 | dis_deauth_mask[3] = 0xfc; | |
2150 | } | |
2151 | ||
2152 | ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n"); | |
2153 | ||
2154 | ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask, | |
2155 | pattern_count, byte_cnt); | |
2156 | ||
2157 | pattern_count++; | |
2158 | /* | |
2159 | * for de-authenticate pattern, only the first byte of the frame | |
2160 | * control field gets changed from 0xA0 to 0xC0 | |
2161 | */ | |
2162 | dis_deauth_pattern[0] = 0xC0; | |
2163 | ||
2164 | ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask, | |
2165 | pattern_count, byte_cnt); | |
2166 | ||
2167 | } | |
2168 | ||
2169 | static void ath9k_wow_add_pattern(struct ath_softc *sc, | |
2170 | struct cfg80211_wowlan *wowlan) | |
2171 | { | |
2172 | struct ath_hw *ah = sc->sc_ah; | |
2173 | struct ath9k_wow_pattern *wow_pattern = NULL; | |
2174 | struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns; | |
2175 | int mask_len; | |
2176 | s8 i = 0; | |
2177 | ||
2178 | if (!wowlan->n_patterns) | |
2179 | return; | |
2180 | ||
2181 | /* | |
2182 | * Add the new user configured patterns | |
2183 | */ | |
2184 | for (i = 0; i < wowlan->n_patterns; i++) { | |
2185 | ||
2186 | wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL); | |
2187 | ||
2188 | if (!wow_pattern) | |
2189 | return; | |
2190 | ||
2191 | /* | |
2192 | * TODO: convert the generic user space pattern to | |
2193 | * appropriate chip specific/802.11 pattern. | |
2194 | */ | |
2195 | ||
2196 | mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8); | |
2197 | memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE); | |
2198 | memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE); | |
2199 | memcpy(wow_pattern->pattern_bytes, patterns[i].pattern, | |
2200 | patterns[i].pattern_len); | |
2201 | memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len); | |
2202 | wow_pattern->pattern_len = patterns[i].pattern_len; | |
2203 | ||
2204 | /* | |
2205 | * just need to take care of deauth and disssoc pattern, | |
2206 | * make sure we don't overwrite them. | |
2207 | */ | |
2208 | ||
2209 | ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes, | |
2210 | wow_pattern->mask_bytes, | |
2211 | i + 2, | |
2212 | wow_pattern->pattern_len); | |
2213 | kfree(wow_pattern); | |
2214 | ||
2215 | } | |
2216 | ||
2217 | } | |
2218 | ||
2219 | static int ath9k_suspend(struct ieee80211_hw *hw, | |
2220 | struct cfg80211_wowlan *wowlan) | |
2221 | { | |
2222 | struct ath_softc *sc = hw->priv; | |
2223 | struct ath_hw *ah = sc->sc_ah; | |
2224 | struct ath_common *common = ath9k_hw_common(ah); | |
2225 | u32 wow_triggers_enabled = 0; | |
2226 | int ret = 0; | |
2227 | ||
2228 | mutex_lock(&sc->mutex); | |
2229 | ||
2230 | ath_cancel_work(sc); | |
5686cac5 | 2231 | ath_stop_ani(sc); |
b11e640a MSS |
2232 | del_timer_sync(&sc->rx_poll_timer); |
2233 | ||
2234 | if (test_bit(SC_OP_INVALID, &sc->sc_flags)) { | |
2235 | ath_dbg(common, ANY, "Device not present\n"); | |
2236 | ret = -EINVAL; | |
2237 | goto fail_wow; | |
2238 | } | |
2239 | ||
2240 | if (WARN_ON(!wowlan)) { | |
2241 | ath_dbg(common, WOW, "None of the WoW triggers enabled\n"); | |
2242 | ret = -EINVAL; | |
2243 | goto fail_wow; | |
2244 | } | |
2245 | ||
2246 | if (!device_can_wakeup(sc->dev)) { | |
2247 | ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n"); | |
2248 | ret = 1; | |
2249 | goto fail_wow; | |
2250 | } | |
2251 | ||
2252 | /* | |
2253 | * none of the sta vifs are associated | |
2254 | * and we are not currently handling multivif | |
2255 | * cases, for instance we have to seperately | |
2256 | * configure 'keep alive frame' for each | |
2257 | * STA. | |
2258 | */ | |
2259 | ||
2260 | if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) { | |
2261 | ath_dbg(common, WOW, "None of the STA vifs are associated\n"); | |
2262 | ret = 1; | |
2263 | goto fail_wow; | |
2264 | } | |
2265 | ||
2266 | if (sc->nvifs > 1) { | |
2267 | ath_dbg(common, WOW, "WoW for multivif is not yet supported\n"); | |
2268 | ret = 1; | |
2269 | goto fail_wow; | |
2270 | } | |
2271 | ||
2272 | ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled); | |
2273 | ||
2274 | ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n", | |
2275 | wow_triggers_enabled); | |
2276 | ||
2277 | ath9k_ps_wakeup(sc); | |
2278 | ||
2279 | ath9k_stop_btcoex(sc); | |
2280 | ||
2281 | /* | |
2282 | * Enable wake up on recieving disassoc/deauth | |
2283 | * frame by default. | |
2284 | */ | |
2285 | ath9k_wow_add_disassoc_deauth_pattern(sc); | |
2286 | ||
2287 | if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN) | |
2288 | ath9k_wow_add_pattern(sc, wowlan); | |
2289 | ||
2290 | spin_lock_bh(&sc->sc_pcu_lock); | |
2291 | /* | |
2292 | * To avoid false wake, we enable beacon miss interrupt only | |
2293 | * when we go to sleep. We save the current interrupt mask | |
2294 | * so we can restore it after the system wakes up | |
2295 | */ | |
2296 | sc->wow_intr_before_sleep = ah->imask; | |
2297 | ah->imask &= ~ATH9K_INT_GLOBAL; | |
2298 | ath9k_hw_disable_interrupts(ah); | |
2299 | ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL; | |
2300 | ath9k_hw_set_interrupts(ah); | |
2301 | ath9k_hw_enable_interrupts(ah); | |
2302 | ||
2303 | spin_unlock_bh(&sc->sc_pcu_lock); | |
2304 | ||
2305 | /* | |
2306 | * we can now sync irq and kill any running tasklets, since we already | |
2307 | * disabled interrupts and not holding a spin lock | |
2308 | */ | |
2309 | synchronize_irq(sc->irq); | |
2310 | tasklet_kill(&sc->intr_tq); | |
2311 | ||
2312 | ath9k_hw_wow_enable(ah, wow_triggers_enabled); | |
2313 | ||
2314 | ath9k_ps_restore(sc); | |
2315 | ath_dbg(common, ANY, "WoW enabled in ath9k\n"); | |
2316 | atomic_inc(&sc->wow_sleep_proc_intr); | |
2317 | ||
2318 | fail_wow: | |
2319 | mutex_unlock(&sc->mutex); | |
2320 | return ret; | |
2321 | } | |
2322 | ||
2323 | static int ath9k_resume(struct ieee80211_hw *hw) | |
2324 | { | |
2325 | struct ath_softc *sc = hw->priv; | |
2326 | struct ath_hw *ah = sc->sc_ah; | |
2327 | struct ath_common *common = ath9k_hw_common(ah); | |
2328 | u32 wow_status; | |
2329 | ||
2330 | mutex_lock(&sc->mutex); | |
2331 | ||
2332 | ath9k_ps_wakeup(sc); | |
2333 | ||
2334 | spin_lock_bh(&sc->sc_pcu_lock); | |
2335 | ||
2336 | ath9k_hw_disable_interrupts(ah); | |
2337 | ah->imask = sc->wow_intr_before_sleep; | |
2338 | ath9k_hw_set_interrupts(ah); | |
2339 | ath9k_hw_enable_interrupts(ah); | |
2340 | ||
2341 | spin_unlock_bh(&sc->sc_pcu_lock); | |
2342 | ||
2343 | wow_status = ath9k_hw_wow_wakeup(ah); | |
2344 | ||
2345 | if (atomic_read(&sc->wow_got_bmiss_intr) == 0) { | |
2346 | /* | |
2347 | * some devices may not pick beacon miss | |
2348 | * as the reason they woke up so we add | |
2349 | * that here for that shortcoming. | |
2350 | */ | |
2351 | wow_status |= AH_WOW_BEACON_MISS; | |
2352 | atomic_dec(&sc->wow_got_bmiss_intr); | |
2353 | ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n"); | |
2354 | } | |
2355 | ||
2356 | atomic_dec(&sc->wow_sleep_proc_intr); | |
2357 | ||
2358 | if (wow_status) { | |
2359 | ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n", | |
2360 | ath9k_hw_wow_event_to_string(wow_status), wow_status); | |
2361 | } | |
2362 | ||
2363 | ath_restart_work(sc); | |
2364 | ath9k_start_btcoex(sc); | |
2365 | ||
2366 | ath9k_ps_restore(sc); | |
2367 | mutex_unlock(&sc->mutex); | |
2368 | ||
2369 | return 0; | |
2370 | } | |
2371 | ||
2372 | static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled) | |
2373 | { | |
2374 | struct ath_softc *sc = hw->priv; | |
2375 | ||
2376 | mutex_lock(&sc->mutex); | |
2377 | device_init_wakeup(sc->dev, 1); | |
2378 | device_set_wakeup_enable(sc->dev, enabled); | |
2379 | mutex_unlock(&sc->mutex); | |
2380 | } | |
2381 | ||
2382 | #endif | |
2383 | ||
6baff7f9 | 2384 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2385 | .tx = ath9k_tx, |
2386 | .start = ath9k_start, | |
2387 | .stop = ath9k_stop, | |
2388 | .add_interface = ath9k_add_interface, | |
6b3b991d | 2389 | .change_interface = ath9k_change_interface, |
8feceb67 VT |
2390 | .remove_interface = ath9k_remove_interface, |
2391 | .config = ath9k_config, | |
8feceb67 | 2392 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2393 | .sta_add = ath9k_sta_add, |
2394 | .sta_remove = ath9k_sta_remove, | |
5519541d | 2395 | .sta_notify = ath9k_sta_notify, |
8feceb67 | 2396 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2397 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2398 | .set_key = ath9k_set_key, |
8feceb67 | 2399 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2400 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2401 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2402 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2403 | .get_survey = ath9k_get_survey, |
3b319aae | 2404 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2405 | .set_coverage_class = ath9k_set_coverage_class, |
69081624 | 2406 | .flush = ath9k_flush, |
15b91e83 | 2407 | .tx_frames_pending = ath9k_tx_frames_pending, |
52c94f41 MSS |
2408 | .tx_last_beacon = ath9k_tx_last_beacon, |
2409 | .get_stats = ath9k_get_stats, | |
43c35284 FF |
2410 | .set_antenna = ath9k_set_antenna, |
2411 | .get_antenna = ath9k_get_antenna, | |
b90bd9d1 | 2412 | |
b11e640a MSS |
2413 | #ifdef CONFIG_PM_SLEEP |
2414 | .suspend = ath9k_suspend, | |
2415 | .resume = ath9k_resume, | |
2416 | .set_wakeup = ath9k_set_wakeup, | |
2417 | #endif | |
2418 | ||
b90bd9d1 BG |
2419 | #ifdef CONFIG_ATH9K_DEBUGFS |
2420 | .get_et_sset_count = ath9k_get_et_sset_count, | |
2421 | .get_et_stats = ath9k_get_et_stats, | |
2422 | .get_et_strings = ath9k_get_et_strings, | |
2423 | #endif | |
8feceb67 | 2424 | }; |