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ath9k: re-order cancelling of work on mac80211 workqueue
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209 19
f078f209
LR		 20static char *dev_info = "ath9k";
21
22MODULE_AUTHOR("Atheros Communications");
23MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
24MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
25MODULE_LICENSE("Dual BSD/GPL");
26
b3bd89ce
JM		 27static int modparam_nohwcrypt;
28module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
29MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
30
5f8e077c
LR		 31/* We use the hw_value as an index into our private channel structure */
32
33#define CHAN2G(_freq, _idx) { \
34 .center_freq = (_freq), \
35 .hw_value = (_idx), \
eeddfd9d 36 .max_power = 20, \
5f8e077c
LR		 37}
38
39#define CHAN5G(_freq, _idx) { \
40 .band = IEEE80211_BAND_5GHZ, \
41 .center_freq = (_freq), \
42 .hw_value = (_idx), \
eeddfd9d 43 .max_power = 20, \
5f8e077c
LR		 44}
45
46/* Some 2 GHz radios are actually tunable on 2312-2732
47 * on 5 MHz steps, we support the channels which we know
48 * we have calibration data for all cards though to make
49 * this static */
50static struct ieee80211_channel ath9k_2ghz_chantable[] = {
51 CHAN2G(2412, 0), /* Channel 1 */
52 CHAN2G(2417, 1), /* Channel 2 */
53 CHAN2G(2422, 2), /* Channel 3 */
54 CHAN2G(2427, 3), /* Channel 4 */
55 CHAN2G(2432, 4), /* Channel 5 */
56 CHAN2G(2437, 5), /* Channel 6 */
57 CHAN2G(2442, 6), /* Channel 7 */
58 CHAN2G(2447, 7), /* Channel 8 */
59 CHAN2G(2452, 8), /* Channel 9 */
60 CHAN2G(2457, 9), /* Channel 10 */
61 CHAN2G(2462, 10), /* Channel 11 */
62 CHAN2G(2467, 11), /* Channel 12 */
63 CHAN2G(2472, 12), /* Channel 13 */
64 CHAN2G(2484, 13), /* Channel 14 */
65};
66
67/* Some 5 GHz radios are actually tunable on XXXX-YYYY
68 * on 5 MHz steps, we support the channels which we know
69 * we have calibration data for all cards though to make
70 * this static */
71static struct ieee80211_channel ath9k_5ghz_chantable[] = {
72 /* _We_ call this UNII 1 */
73 CHAN5G(5180, 14), /* Channel 36 */
74 CHAN5G(5200, 15), /* Channel 40 */
75 CHAN5G(5220, 16), /* Channel 44 */
76 CHAN5G(5240, 17), /* Channel 48 */
77 /* _We_ call this UNII 2 */
78 CHAN5G(5260, 18), /* Channel 52 */
79 CHAN5G(5280, 19), /* Channel 56 */
80 CHAN5G(5300, 20), /* Channel 60 */
81 CHAN5G(5320, 21), /* Channel 64 */
82 /* _We_ call this "Middle band" */
83 CHAN5G(5500, 22), /* Channel 100 */
84 CHAN5G(5520, 23), /* Channel 104 */
85 CHAN5G(5540, 24), /* Channel 108 */
86 CHAN5G(5560, 25), /* Channel 112 */
87 CHAN5G(5580, 26), /* Channel 116 */
88 CHAN5G(5600, 27), /* Channel 120 */
89 CHAN5G(5620, 28), /* Channel 124 */
90 CHAN5G(5640, 29), /* Channel 128 */
91 CHAN5G(5660, 30), /* Channel 132 */
92 CHAN5G(5680, 31), /* Channel 136 */
93 CHAN5G(5700, 32), /* Channel 140 */
94 /* _We_ call this UNII 3 */
95 CHAN5G(5745, 33), /* Channel 149 */
96 CHAN5G(5765, 34), /* Channel 153 */
97 CHAN5G(5785, 35), /* Channel 157 */
98 CHAN5G(5805, 36), /* Channel 161 */
99 CHAN5G(5825, 37), /* Channel 165 */
100};
101
ce111bad
LR		 102static void ath_cache_conf_rate(struct ath_softc *sc,
103 struct ieee80211_conf *conf)
ff37e337 104{
030bb495
LR		 105 switch (conf->channel->band) {
106 case IEEE80211_BAND_2GHZ:
107 if (conf_is_ht20(conf))
108 sc->cur_rate_table =
109 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
110 else if (conf_is_ht40_minus(conf))
111 sc->cur_rate_table =
112 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
113 else if (conf_is_ht40_plus(conf))
114 sc->cur_rate_table =
115 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 116 else
030bb495
LR		 117 sc->cur_rate_table =
118 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 119 break;
120 case IEEE80211_BAND_5GHZ:
121 if (conf_is_ht20(conf))
122 sc->cur_rate_table =
123 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
124 else if (conf_is_ht40_minus(conf))
125 sc->cur_rate_table =
126 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
127 else if (conf_is_ht40_plus(conf))
128 sc->cur_rate_table =
129 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
130 else
96742256
LR		 131 sc->cur_rate_table =
132 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 133 break;
134 default:
ce111bad 135 BUG_ON(1);
030bb495
LR		 136 break;
137 }
ff37e337
S		 138}
139
140static void ath_update_txpow(struct ath_softc *sc)
141{
cbe61d8a 142 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 143 u32 txpow;
144
17d7904d
S		 145 if (sc->curtxpow != sc->config.txpowlimit) {
146 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 147 /* read back in case value is clamped */
148 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 149 sc->curtxpow = txpow;
ff37e337
S		 150 }
151}
152
153static u8 parse_mpdudensity(u8 mpdudensity)
154{
155 /*
156 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
157 * 0 for no restriction
158 * 1 for 1/4 us
159 * 2 for 1/2 us
160 * 3 for 1 us
161 * 4 for 2 us
162 * 5 for 4 us
163 * 6 for 8 us
164 * 7 for 16 us
165 */
166 switch (mpdudensity) {
167 case 0:
168 return 0;
169 case 1:
170 case 2:
171 case 3:
172 /* Our lower layer calculations limit our precision to
173 1 microsecond */
174 return 1;
175 case 4:
176 return 2;
177 case 5:
178 return 4;
179 case 6:
180 return 8;
181 case 7:
182 return 16;
183 default:
184 return 0;
185 }
186}
187
188static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
189{
4f0fc7c3 190 const struct ath_rate_table *rate_table = NULL;
ff37e337
S		 191 struct ieee80211_supported_band *sband;
192 struct ieee80211_rate *rate;
193 int i, maxrates;
194
195 switch (band) {
196 case IEEE80211_BAND_2GHZ:
197 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
198 break;
199 case IEEE80211_BAND_5GHZ:
200 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
201 break;
202 default:
203 break;
204 }
205
206 if (rate_table == NULL)
207 return;
208
209 sband = &sc->sbands[band];
210 rate = sc->rates[band];
211
212 if (rate_table->rate_cnt > ATH_RATE_MAX)
213 maxrates = ATH_RATE_MAX;
214 else
215 maxrates = rate_table->rate_cnt;
216
217 for (i = 0; i < maxrates; i++) {
218 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
219 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 220 if (rate_table->info[i].short_preamble) {
221 rate[i].hw_value_short = rate_table->info[i].ratecode |
222 rate_table->info[i].short_preamble;
223 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
224 }
ff37e337 225 sband->n_bitrates++;
f46730d1 226
04bd4638
S		 227 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
228 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 229 }
230}
231
82880a7c
VT		 232static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
233 struct ieee80211_hw *hw)
234{
235 struct ieee80211_channel *curchan = hw->conf.channel;
236 struct ath9k_channel *channel;
237 u8 chan_idx;
238
239 chan_idx = curchan->hw_value;
240 channel = &sc->sc_ah->channels[chan_idx];
241 ath9k_update_ichannel(sc, hw, channel);
242 return channel;
243}
244
ff37e337
S		 245/*
246 * Set/change channels. If the channel is really being changed, it's done
247 * by reseting the chip. To accomplish this we must first cleanup any pending
248 * DMA, then restart stuff.
249*/
0e2dedf9
JM		 250int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
251 struct ath9k_channel *hchan)
ff37e337 252{
cbe61d8a 253 struct ath_hw *ah = sc->sc_ah;
ff37e337 254 bool fastcc = true, stopped;
ae8d2858
LR		 255 struct ieee80211_channel *channel = hw->conf.channel;
256 int r;
ff37e337
S		 257
258 if (sc->sc_flags & SC_OP_INVALID)
259 return -EIO;
260
3cbb5dd7
VN		 261 ath9k_ps_wakeup(sc);
262
c0d7c7af
LR		 263 /*
264 * This is only performed if the channel settings have
265 * actually changed.
266 *
267 * To switch channels clear any pending DMA operations;
268 * wait long enough for the RX fifo to drain, reset the
269 * hardware at the new frequency, and then re-enable
270 * the relevant bits of the h/w.
271 */
272 ath9k_hw_set_interrupts(ah, 0);
043a0405 273 ath_drain_all_txq(sc, false);
c0d7c7af 274 stopped = ath_stoprecv(sc);
ff37e337 275
c0d7c7af
LR		 276 /* XXX: do not flush receive queue here. We don't want
277 * to flush data frames already in queue because of
278 * changing channel. */
ff37e337 279
c0d7c7af
LR		 280 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
281 fastcc = false;
282
283 DPRINTF(sc, ATH_DBG_CONFIG,
284 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 285 sc->sc_ah->curchan->channel,
c0d7c7af 286 channel->center_freq, sc->tx_chan_width);
ff37e337 287
c0d7c7af
LR		 288 spin_lock_bh(&sc->sc_resetlock);
289
290 r = ath9k_hw_reset(ah, hchan, fastcc);
291 if (r) {
292 DPRINTF(sc, ATH_DBG_FATAL,
293 "Unable to reset channel (%u Mhz) "
6b45784f 294 "reset status %d\n",
c0d7c7af
LR		 295 channel->center_freq, r);
296 spin_unlock_bh(&sc->sc_resetlock);
3989279c 297 goto ps_restore;
ff37e337 298 }
c0d7c7af
LR		 299 spin_unlock_bh(&sc->sc_resetlock);
300
c0d7c7af
LR		 301 sc->sc_flags &= ~SC_OP_FULL_RESET;
302
303 if (ath_startrecv(sc) != 0) {
304 DPRINTF(sc, ATH_DBG_FATAL,
305 "Unable to restart recv logic\n");
3989279c
GJ		 306 r = -EIO;
307 goto ps_restore;
c0d7c7af
LR		 308 }
309
310 ath_cache_conf_rate(sc, &hw->conf);
311 ath_update_txpow(sc);
17d7904d 312 ath9k_hw_set_interrupts(ah, sc->imask);
3989279c
GJ		 313
314 ps_restore:
3cbb5dd7 315 ath9k_ps_restore(sc);
3989279c 316 return r;
ff37e337
S		 317}
318
319/*
320 * This routine performs the periodic noise floor calibration function
321 * that is used to adjust and optimize the chip performance. This
322 * takes environmental changes (location, temperature) into account.
323 * When the task is complete, it reschedules itself depending on the
324 * appropriate interval that was calculated.
325 */
326static void ath_ani_calibrate(unsigned long data)
327{
20977d3e
S		 328 struct ath_softc *sc = (struct ath_softc *)data;
329 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 330 bool longcal = false;
331 bool shortcal = false;
332 bool aniflag = false;
333 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 334 u32 cal_interval, short_cal_interval;
ff37e337 335
20977d3e
S		 336 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
337 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 338
339 /*
340 * don't calibrate when we're scanning.
341 * we are most likely not on our home channel.
342 */
e5f0921a 343 spin_lock(&sc->ani_lock);
0c98de65 344 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 345 goto set_timer;
ff37e337 346
1ffc1c61
JM		 347 /* Only calibrate if awake */
348 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
349 goto set_timer;
350
351 ath9k_ps_wakeup(sc);
352
ff37e337 353 /* Long calibration runs independently of short calibration. */
17d7904d 354 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 355 longcal = true;
04bd4638 356 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 357 sc->ani.longcal_timer = timestamp;
ff37e337
S		 358 }
359
17d7904d
S		 360 /* Short calibration applies only while caldone is false */
361 if (!sc->ani.caldone) {
20977d3e 362 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 363 shortcal = true;
04bd4638 364 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 365 sc->ani.shortcal_timer = timestamp;
366 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 367 }
368 } else {
17d7904d 369 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 370 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 371 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
372 if (sc->ani.caldone)
373 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 374 }
375 }
376
377 /* Verify whether we must check ANI */
20977d3e 378 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 379 aniflag = true;
17d7904d 380 sc->ani.checkani_timer = timestamp;
ff37e337
S		 381 }
382
383 /* Skip all processing if there's nothing to do. */
384 if (longcal || shortcal || aniflag) {
385 /* Call ANI routine if necessary */
386 if (aniflag)
20977d3e 387 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
ff37e337
S		 388
389 /* Perform calibration if necessary */
390 if (longcal || shortcal) {
379f0440
S		 391 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
392 sc->rx_chainmask, longcal);
393
394 if (longcal)
395 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
396 ah->curchan);
397
398 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
399 ah->curchan->channel, ah->curchan->channelFlags,
400 sc->ani.noise_floor);
ff37e337
S		 401 }
402 }
403
1ffc1c61
JM		 404 ath9k_ps_restore(sc);
405
20977d3e 406set_timer:
e5f0921a 407 spin_unlock(&sc->ani_lock);
ff37e337
S		 408 /*
409 * Set timer interval based on previous results.
410 * The interval must be the shortest necessary to satisfy ANI,
411 * short calibration and long calibration.
412 */
aac9207e 413 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 414 if (sc->sc_ah->config.enable_ani)
aac9207e 415 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 416 if (!sc->ani.caldone)
20977d3e 417 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 418
17d7904d 419 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 420}
421
415f738e
S		 422static void ath_start_ani(struct ath_softc *sc)
423{
424 unsigned long timestamp = jiffies_to_msecs(jiffies);
425
426 sc->ani.longcal_timer = timestamp;
427 sc->ani.shortcal_timer = timestamp;
428 sc->ani.checkani_timer = timestamp;
429
430 mod_timer(&sc->ani.timer,
431 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
432}
433
ff37e337
S		 434/*
435 * Update tx/rx chainmask. For legacy association,
436 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 437 * the chainmask configuration, for bt coexistence, use
438 * the chainmask configuration even in legacy mode.
ff37e337 439 */
0e2dedf9 440void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 441{
c97c92d9 442 if (is_ht ||
2660b81a
S		 443 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
444 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
445 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 446 } else {
17d7904d
S		 447 sc->tx_chainmask = 1;
448 sc->rx_chainmask = 1;
ff37e337
S		 449 }
450
04bd4638 451 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 452 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 453}
454
455static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
456{
457 struct ath_node *an;
458
459 an = (struct ath_node *)sta->drv_priv;
460
87792efc 461 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 462 ath_tx_node_init(sc, an);
9e98ac65 463 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S		 464 sta->ht_cap.ampdu_factor);
465 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
a59b5a5e 466 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
87792efc 467 }
ff37e337
S		 468}
469
470static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
471{
472 struct ath_node *an = (struct ath_node *)sta->drv_priv;
473
474 if (sc->sc_flags & SC_OP_TXAGGR)
475 ath_tx_node_cleanup(sc, an);
476}
477
478static void ath9k_tasklet(unsigned long data)
479{
480 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 481 u32 status = sc->intrstatus;
ff37e337 482
153e080d
VT		 483 ath9k_ps_wakeup(sc);
484
ff37e337 485 if (status & ATH9K_INT_FATAL) {
ff37e337 486 ath_reset(sc, false);
153e080d 487 ath9k_ps_restore(sc);
ff37e337 488 return;
063d8be3 489 }
ff37e337 490
063d8be3
S		 491 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
492 spin_lock_bh(&sc->rx.rxflushlock);
493 ath_rx_tasklet(sc, 0);
494 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 495 }
496
063d8be3
S		 497 if (status & ATH9K_INT_TX)
498 ath_tx_tasklet(sc);
499
96148326 500 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM		 501 /*
502 * TSF sync does not look correct; remain awake to sync with
503 * the next Beacon.
504 */
505 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
ccdfeab6 506 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
54ce846e
JM		 507 }
508
ff37e337 509 /* re-enable hardware interrupt */
17d7904d 510 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
153e080d 511 ath9k_ps_restore(sc);
ff37e337
S		 512}
513
6baff7f9 514irqreturn_t ath_isr(int irq, void *dev)
ff37e337 515{
063d8be3
S		 516#define SCHED_INTR ( \
517 ATH9K_INT_FATAL | \
518 ATH9K_INT_RXORN | \
519 ATH9K_INT_RXEOL | \
520 ATH9K_INT_RX | \
521 ATH9K_INT_TX | \
522 ATH9K_INT_BMISS | \
523 ATH9K_INT_CST | \
524 ATH9K_INT_TSFOOR)
525
ff37e337 526 struct ath_softc *sc = dev;
cbe61d8a 527 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 528 enum ath9k_int status;
529 bool sched = false;
530
063d8be3
S		 531 /*
532 * The hardware is not ready/present, don't
533 * touch anything. Note this can happen early
534 * on if the IRQ is shared.
535 */
536 if (sc->sc_flags & SC_OP_INVALID)
537 return IRQ_NONE;
ff37e337 538
063d8be3
S		 539
540 /* shared irq, not for us */
541
153e080d 542 if (!ath9k_hw_intrpend(ah))
063d8be3 543 return IRQ_NONE;
063d8be3
S		 544
545 /*
546 * Figure out the reason(s) for the interrupt. Note
547 * that the hal returns a pseudo-ISR that may include
548 * bits we haven't explicitly enabled so we mask the
549 * value to insure we only process bits we requested.
550 */
551 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
552 status &= sc->imask; /* discard unasked-for bits */
ff37e337 553
063d8be3
S		 554 /*
555 * If there are no status bits set, then this interrupt was not
556 * for me (should have been caught above).
557 */
153e080d 558 if (!status)
063d8be3 559 return IRQ_NONE;
ff37e337 560
063d8be3
S		 561 /* Cache the status */
562 sc->intrstatus = status;
563
564 if (status & SCHED_INTR)
565 sched = true;
566
567 /*
568 * If a FATAL or RXORN interrupt is received, we have to reset the
569 * chip immediately.
570 */
571 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
572 goto chip_reset;
573
574 if (status & ATH9K_INT_SWBA)
575 tasklet_schedule(&sc->bcon_tasklet);
576
577 if (status & ATH9K_INT_TXURN)
578 ath9k_hw_updatetxtriglevel(ah, true);
579
580 if (status & ATH9K_INT_MIB) {
ff37e337 581 /*
063d8be3
S		 582 * Disable interrupts until we service the MIB
583 * interrupt; otherwise it will continue to
584 * fire.
ff37e337 585 */
063d8be3
S		 586 ath9k_hw_set_interrupts(ah, 0);
587 /*
588 * Let the hal handle the event. We assume
589 * it will clear whatever condition caused
590 * the interrupt.
591 */
592 ath9k_hw_procmibevent(ah, &sc->nodestats);
593 ath9k_hw_set_interrupts(ah, sc->imask);
594 }
ff37e337 595
153e080d
VT		 596 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
597 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S		 598 /* Clear RxAbort bit so that we can
599 * receive frames */
600 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
153e080d 601 ath9k_hw_setrxabort(sc->sc_ah, 0);
063d8be3 602 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 603 }
063d8be3
S		 604
605chip_reset:
ff37e337 606
817e11de
S		 607 ath_debug_stat_interrupt(sc, status);
608
ff37e337
S		 609 if (sched) {
610 /* turn off every interrupt except SWBA */
17d7904d 611 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 612 tasklet_schedule(&sc->intr_tq);
613 }
614
615 return IRQ_HANDLED;
063d8be3
S		 616
617#undef SCHED_INTR
ff37e337
S		 618}
619
f078f209 620static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 621 struct ieee80211_channel *chan,
094d05dc 622 enum nl80211_channel_type channel_type)
f078f209
LR		 623{
624 u32 chanmode = 0;
f078f209
LR		 625
626 switch (chan->band) {
627 case IEEE80211_BAND_2GHZ:
094d05dc
S		 628 switch(channel_type) {
629 case NL80211_CHAN_NO_HT:
630 case NL80211_CHAN_HT20:
f078f209 631 chanmode = CHANNEL_G_HT20;
094d05dc
S		 632 break;
633 case NL80211_CHAN_HT40PLUS:
f078f209 634 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 635 break;
636 case NL80211_CHAN_HT40MINUS:
f078f209 637 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 638 break;
639 }
f078f209
LR		 640 break;
641 case IEEE80211_BAND_5GHZ:
094d05dc
S		 642 switch(channel_type) {
643 case NL80211_CHAN_NO_HT:
644 case NL80211_CHAN_HT20:
f078f209 645 chanmode = CHANNEL_A_HT20;
094d05dc
S		 646 break;
647 case NL80211_CHAN_HT40PLUS:
f078f209 648 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 649 break;
650 case NL80211_CHAN_HT40MINUS:
f078f209 651 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 652 break;
653 }
f078f209
LR		 654 break;
655 default:
656 break;
657 }
658
659 return chanmode;
660}
661
6ace2891 662static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 663 struct ath9k_keyval *hk, const u8 *addr,
664 bool authenticator)
f078f209 665{
6ace2891
JM		 666 const u8 *key_rxmic;
667 const u8 *key_txmic;
f078f209 668
6ace2891
JM		 669 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
670 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 671
672 if (addr == NULL) {
d216aaa6
JM		 673 /*
674 * Group key installation - only two key cache entries are used
675 * regardless of splitmic capability since group key is only
676 * used either for TX or RX.
677 */
3f53dd64
JM		 678 if (authenticator) {
679 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
680 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
681 } else {
682 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
683 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
684 }
d216aaa6 685 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 686 }
17d7904d 687 if (!sc->splitmic) {
d216aaa6 688 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 689 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
690 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 691 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 692 }
d216aaa6
JM		 693
694 /* Separate key cache entries for TX and RX */
695
696 /* TX key goes at first index, RX key at +32. */
f078f209 697 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 698 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
699 /* TX MIC entry failed. No need to proceed further */
d8baa939 700 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 701 "Setting TX MIC Key Failed\n");
f078f209
LR		 702 return 0;
703 }
704
705 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
706 /* XXX delete tx key on failure? */
d216aaa6 707 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 708}
709
710static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
711{
712 int i;
713
17d7904d
S		 714 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
715 if (test_bit(i, sc->keymap) ||
716 test_bit(i + 64, sc->keymap))
6ace2891 717 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 718 if (sc->splitmic &&
719 (test_bit(i + 32, sc->keymap) ||
720 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 721 continue; /* At least one part of TKIP key allocated */
722
723 /* Found a free slot for a TKIP key */
724 return i;
725 }
726 return -1;
727}
728
729static int ath_reserve_key_cache_slot(struct ath_softc *sc)
730{
731 int i;
732
733 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 734 if (sc->splitmic) {
735 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
736 if (!test_bit(i, sc->keymap) &&
737 (test_bit(i + 32, sc->keymap) ||
738 test_bit(i + 64, sc->keymap) ||
739 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 740 return i;
17d7904d
S		 741 if (!test_bit(i + 32, sc->keymap) &&
742 (test_bit(i, sc->keymap) ||
743 test_bit(i + 64, sc->keymap) ||
744 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 745 return i + 32;
17d7904d
S		 746 if (!test_bit(i + 64, sc->keymap) &&
747 (test_bit(i , sc->keymap) ||
748 test_bit(i + 32, sc->keymap) ||
749 test_bit(i + 64 + 32, sc->keymap)))
ea612132 750 return i + 64;
17d7904d
S		 751 if (!test_bit(i + 64 + 32, sc->keymap) &&
752 (test_bit(i, sc->keymap) ||
753 test_bit(i + 32, sc->keymap) ||
754 test_bit(i + 64, sc->keymap)))
ea612132 755 return i + 64 + 32;
6ace2891
JM		 756 }
757 } else {
17d7904d
S		 758 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
759 if (!test_bit(i, sc->keymap) &&
760 test_bit(i + 64, sc->keymap))
6ace2891 761 return i;
17d7904d
S		 762 if (test_bit(i, sc->keymap) &&
763 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 764 return i + 64;
765 }
766 }
767
768 /* No partially used TKIP slots, pick any available slot */
17d7904d 769 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 770 /* Do not allow slots that could be needed for TKIP group keys
771 * to be used. This limitation could be removed if we know that
772 * TKIP will not be used. */
773 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
774 continue;
17d7904d 775 if (sc->splitmic) {
be2864cf
JM		 776 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
777 continue;
778 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
779 continue;
780 }
781
17d7904d 782 if (!test_bit(i, sc->keymap))
6ace2891
JM		 783 return i; /* Found a free slot for a key */
784 }
785
786 /* No free slot found */
787 return -1;
f078f209
LR		 788}
789
790static int ath_key_config(struct ath_softc *sc,
3f53dd64 791 struct ieee80211_vif *vif,
dc822b5d 792 struct ieee80211_sta *sta,
f078f209
LR		 793 struct ieee80211_key_conf *key)
794{
f078f209
LR		 795 struct ath9k_keyval hk;
796 const u8 *mac = NULL;
797 int ret = 0;
6ace2891 798 int idx;
f078f209
LR		 799
800 memset(&hk, 0, sizeof(hk));
801
802 switch (key->alg) {
803 case ALG_WEP:
804 hk.kv_type = ATH9K_CIPHER_WEP;
805 break;
806 case ALG_TKIP:
807 hk.kv_type = ATH9K_CIPHER_TKIP;
808 break;
809 case ALG_CCMP:
810 hk.kv_type = ATH9K_CIPHER_AES_CCM;
811 break;
812 default:
ca470b29 813 return -EOPNOTSUPP;
f078f209
LR		 814 }
815
6ace2891 816 hk.kv_len = key->keylen;
f078f209
LR		 817 memcpy(hk.kv_val, key->key, key->keylen);
818
6ace2891
JM		 819 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
820 /* For now, use the default keys for broadcast keys. This may
821 * need to change with virtual interfaces. */
822 idx = key->keyidx;
823 } else if (key->keyidx) {
dc822b5d
JB		 824 if (WARN_ON(!sta))
825 return -EOPNOTSUPP;
826 mac = sta->addr;
827
6ace2891
JM		 828 if (vif->type != NL80211_IFTYPE_AP) {
829 /* Only keyidx 0 should be used with unicast key, but
830 * allow this for client mode for now. */
831 idx = key->keyidx;
832 } else
833 return -EIO;
f078f209 834 } else {
dc822b5d
JB		 835 if (WARN_ON(!sta))
836 return -EOPNOTSUPP;
837 mac = sta->addr;
838
6ace2891
JM		 839 if (key->alg == ALG_TKIP)
840 idx = ath_reserve_key_cache_slot_tkip(sc);
841 else
842 idx = ath_reserve_key_cache_slot(sc);
843 if (idx < 0)
ca470b29 844 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 845 }
846
847 if (key->alg == ALG_TKIP)
3f53dd64
JM		 848 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
849 vif->type == NL80211_IFTYPE_AP);
f078f209 850 else
d216aaa6 851 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 852
853 if (!ret)
854 return -EIO;
855
17d7904d 856 set_bit(idx, sc->keymap);
6ace2891 857 if (key->alg == ALG_TKIP) {
17d7904d
S		 858 set_bit(idx + 64, sc->keymap);
859 if (sc->splitmic) {
860 set_bit(idx + 32, sc->keymap);
861 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 862 }
863 }
864
865 return idx;
f078f209
LR		 866}
867
868static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
869{
6ace2891
JM		 870 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
871 if (key->hw_key_idx < IEEE80211_WEP_NKID)
872 return;
873
17d7904d 874 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 875 if (key->alg != ALG_TKIP)
876 return;
f078f209 877
17d7904d
S		 878 clear_bit(key->hw_key_idx + 64, sc->keymap);
879 if (sc->splitmic) {
880 clear_bit(key->hw_key_idx + 32, sc->keymap);
881 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 882 }
f078f209
LR		 883}
884
eb2599ca
S		 885static void setup_ht_cap(struct ath_softc *sc,
886 struct ieee80211_sta_ht_cap *ht_info)
f078f209 887{
140add21 888 u8 tx_streams, rx_streams;
f078f209 889
d9fe60de
JB		 890 ht_info->ht_supported = true;
891 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
892 IEEE80211_HT_CAP_SM_PS |
893 IEEE80211_HT_CAP_SGI_40 |
894 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 895
9e98ac65
S		 896 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
897 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
eb2599ca 898
d9fe60de
JB		 899 /* set up supported mcs set */
900 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
140add21
SB		 901 tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
902 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
903
904 if (tx_streams != rx_streams) {
905 DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
906 tx_streams, rx_streams);
907 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
908 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
909 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
910 }
eb2599ca 911
140add21
SB		 912 ht_info->mcs.rx_mask[0] = 0xff;
913 if (rx_streams >= 2)
eb2599ca 914 ht_info->mcs.rx_mask[1] = 0xff;
eb2599ca 915
140add21 916 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 917}
918
8feceb67 919static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 920 struct ieee80211_vif *vif,
8feceb67 921 struct ieee80211_bss_conf *bss_conf)
f078f209 922{
f078f209 923
8feceb67 924 if (bss_conf->assoc) {
094d05dc 925 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 926 bss_conf->aid, sc->curbssid);
f078f209 927
8feceb67 928 /* New association, store aid */
2664f201
SB		 929 sc->curaid = bss_conf->aid;
930 ath9k_hw_write_associd(sc);
931
932 /*
933 * Request a re-configuration of Beacon related timers
934 * on the receipt of the first Beacon frame (i.e.,
935 * after time sync with the AP).
936 */
937 sc->sc_flags |= SC_OP_BEACON_SYNC;
f078f209 938
8feceb67 939 /* Configure the beacon */
2c3db3d5 940 ath_beacon_config(sc, vif);
f078f209 941
8feceb67 942 /* Reset rssi stats */
17d7904d
S		 943 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
944 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
945 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
946 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 947
415f738e 948 ath_start_ani(sc);
8feceb67 949 } else {
1ffb0610 950 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
17d7904d 951 sc->curaid = 0;
f38faa31
SB		 952 /* Stop ANI */
953 del_timer_sync(&sc->ani.timer);
f078f209 954 }
8feceb67 955}
f078f209 956
8feceb67
VT		 957/********************************/
958/* LED functions */
959/********************************/
f078f209 960
f2bffa7e
VT		 961static void ath_led_blink_work(struct work_struct *work)
962{
963 struct ath_softc *sc = container_of(work, struct ath_softc,
964 ath_led_blink_work.work);
965
966 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
967 return;
85067c06
VT		 968
969 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
970 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
971 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
972 else
973 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
974 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e
VT		 975
976 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
977 (sc->sc_flags & SC_OP_LED_ON) ?
978 msecs_to_jiffies(sc->led_off_duration) :
979 msecs_to_jiffies(sc->led_on_duration));
980
85067c06
VT		 981 sc->led_on_duration = sc->led_on_cnt ?
982 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
983 ATH_LED_ON_DURATION_IDLE;
984 sc->led_off_duration = sc->led_off_cnt ?
985 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
986 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 987 sc->led_on_cnt = sc->led_off_cnt = 0;
988 if (sc->sc_flags & SC_OP_LED_ON)
989 sc->sc_flags &= ~SC_OP_LED_ON;
990 else
991 sc->sc_flags |= SC_OP_LED_ON;
992}
993
8feceb67
VT		 994static void ath_led_brightness(struct led_classdev *led_cdev,
995 enum led_brightness brightness)
996{
997 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
998 struct ath_softc *sc = led->sc;
f078f209 999
8feceb67
VT		 1000 switch (brightness) {
1001 case LED_OFF:
1002 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 1003 led->led_type == ATH_LED_RADIO) {
1004 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
1005 (led->led_type == ATH_LED_RADIO));
8feceb67 1006 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1007 if (led->led_type == ATH_LED_RADIO)
1008 sc->sc_flags &= ~SC_OP_LED_ON;
1009 } else {
1010 sc->led_off_cnt++;
1011 }
8feceb67
VT		 1012 break;
1013 case LED_FULL:
f2bffa7e 1014 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 1015 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1016 queue_delayed_work(sc->hw->workqueue,
1017 &sc->ath_led_blink_work, 0);
1018 } else if (led->led_type == ATH_LED_RADIO) {
1019 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
1020 sc->sc_flags |= SC_OP_LED_ON;
1021 } else {
1022 sc->led_on_cnt++;
1023 }
8feceb67
VT		 1024 break;
1025 default:
1026 break;
f078f209 1027 }
8feceb67 1028}
f078f209 1029
8feceb67
VT		 1030static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1031 char *trigger)
1032{
1033 int ret;
f078f209 1034
8feceb67
VT		 1035 led->sc = sc;
1036 led->led_cdev.name = led->name;
1037 led->led_cdev.default_trigger = trigger;
1038 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1039
8feceb67
VT		 1040 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1041 if (ret)
1042 DPRINTF(sc, ATH_DBG_FATAL,
1043 "Failed to register led:%s", led->name);
1044 else
1045 led->registered = 1;
1046 return ret;
1047}
f078f209 1048
8feceb67
VT		 1049static void ath_unregister_led(struct ath_led *led)
1050{
1051 if (led->registered) {
1052 led_classdev_unregister(&led->led_cdev);
1053 led->registered = 0;
f078f209 1054 }
f078f209
LR		 1055}
1056
8feceb67 1057static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1058{
f2bffa7e 1059 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67
VT		 1060 ath_unregister_led(&sc->assoc_led);
1061 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1062 ath_unregister_led(&sc->tx_led);
1063 ath_unregister_led(&sc->rx_led);
1064 ath_unregister_led(&sc->radio_led);
1065 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1066}
f078f209 1067
8feceb67
VT		 1068static void ath_init_leds(struct ath_softc *sc)
1069{
1070 char *trigger;
1071 int ret;
f078f209 1072
8feceb67
VT		 1073 /* Configure gpio 1 for output */
1074 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1075 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1076 /* LED off, active low */
1077 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1078
f2bffa7e
VT		 1079 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1080
8feceb67
VT		 1081 trigger = ieee80211_get_radio_led_name(sc->hw);
1082 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1083 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1084 ret = ath_register_led(sc, &sc->radio_led, trigger);
1085 sc->radio_led.led_type = ATH_LED_RADIO;
1086 if (ret)
1087 goto fail;
7dcfdcd9 1088
8feceb67
VT		 1089 trigger = ieee80211_get_assoc_led_name(sc->hw);
1090 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1091 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1092 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1093 sc->assoc_led.led_type = ATH_LED_ASSOC;
1094 if (ret)
1095 goto fail;
f078f209 1096
8feceb67
VT		 1097 trigger = ieee80211_get_tx_led_name(sc->hw);
1098 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1099 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1100 ret = ath_register_led(sc, &sc->tx_led, trigger);
1101 sc->tx_led.led_type = ATH_LED_TX;
1102 if (ret)
1103 goto fail;
f078f209 1104
8feceb67
VT		 1105 trigger = ieee80211_get_rx_led_name(sc->hw);
1106 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1107 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1108 ret = ath_register_led(sc, &sc->rx_led, trigger);
1109 sc->rx_led.led_type = ATH_LED_RX;
1110 if (ret)
1111 goto fail;
f078f209 1112
8feceb67
VT		 1113 return;
1114
1115fail:
1116 ath_deinit_leds(sc);
f078f209
LR		 1117}
1118
7ec3e514 1119void ath_radio_enable(struct ath_softc *sc)
500c064d 1120{
cbe61d8a 1121 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1122 struct ieee80211_channel *channel = sc->hw->conf.channel;
1123 int r;
500c064d 1124
3cbb5dd7 1125 ath9k_ps_wakeup(sc);
d2f5b3a6 1126 ath9k_hw_configpcipowersave(ah, 0);
ae8d2858 1127
159cd468
VT		 1128 if (!ah->curchan)
1129 ah->curchan = ath_get_curchannel(sc, sc->hw);
1130
d2f5b3a6 1131 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1132 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1133 if (r) {
500c064d 1134 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1135 "Unable to reset channel %u (%uMhz) ",
6b45784f 1136 "reset status %d\n",
ae8d2858 1137 channel->center_freq, r);
500c064d
VT		 1138 }
1139 spin_unlock_bh(&sc->sc_resetlock);
1140
1141 ath_update_txpow(sc);
1142 if (ath_startrecv(sc) != 0) {
1143 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1144 "Unable to restart recv logic\n");
500c064d
VT		 1145 return;
1146 }
1147
1148 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1149 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1150
1151 /* Re-Enable interrupts */
17d7904d 1152 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1153
1154 /* Enable LED */
1155 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1156 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1157 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1158
1159 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1160 ath9k_ps_restore(sc);
500c064d
VT		 1161}
1162
7ec3e514 1163void ath_radio_disable(struct ath_softc *sc)
500c064d 1164{
cbe61d8a 1165 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1166 struct ieee80211_channel *channel = sc->hw->conf.channel;
1167 int r;
500c064d 1168
3cbb5dd7 1169 ath9k_ps_wakeup(sc);
500c064d
VT		 1170 ieee80211_stop_queues(sc->hw);
1171
1172 /* Disable LED */
1173 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1174 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1175
1176 /* Disable interrupts */
1177 ath9k_hw_set_interrupts(ah, 0);
1178
043a0405 1179 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1180 ath_stoprecv(sc); /* turn off frame recv */
1181 ath_flushrecv(sc); /* flush recv queue */
1182
159cd468
VT		 1183 if (!ah->curchan)
1184 ah->curchan = ath_get_curchannel(sc, sc->hw);
1185
500c064d 1186 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1187 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1188 if (r) {
500c064d 1189 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1190 "Unable to reset channel %u (%uMhz) "
6b45784f 1191 "reset status %d\n",
ae8d2858 1192 channel->center_freq, r);
500c064d
VT		 1193 }
1194 spin_unlock_bh(&sc->sc_resetlock);
1195
1196 ath9k_hw_phy_disable(ah);
d2f5b3a6 1197 ath9k_hw_configpcipowersave(ah, 1);
3cbb5dd7 1198 ath9k_ps_restore(sc);
38ab422e 1199 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
500c064d
VT		 1200}
1201
5077fd35
GJ		 1202/*******************/
1203/* Rfkill */
1204/*******************/
1205
500c064d
VT		 1206static bool ath_is_rfkill_set(struct ath_softc *sc)
1207{
cbe61d8a 1208 struct ath_hw *ah = sc->sc_ah;
500c064d 1209
2660b81a
S		 1210 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1211 ah->rfkill_polarity;
500c064d
VT		 1212}
1213
3b319aae 1214static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
500c064d 1215{
3b319aae
JB		 1216 struct ath_wiphy *aphy = hw->priv;
1217 struct ath_softc *sc = aphy->sc;
19d337df 1218 bool blocked = !!ath_is_rfkill_set(sc);
500c064d 1219
3b319aae
JB		 1220 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1221
1222 if (blocked)
19d337df
JB		 1223 ath_radio_disable(sc);
1224 else
1225 ath_radio_enable(sc);
500c064d
VT		 1226}
1227
3b319aae 1228static void ath_start_rfkill_poll(struct ath_softc *sc)
500c064d 1229{
3b319aae 1230 struct ath_hw *ah = sc->sc_ah;
9c84b797 1231
3b319aae
JB		 1232 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1233 wiphy_rfkill_start_polling(sc->hw->wiphy);
9c84b797 1234}
500c064d 1235
6baff7f9 1236void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1237{
1238 ath_detach(sc);
1239 free_irq(sc->irq, sc);
1240 ath_bus_cleanup(sc);
c52f33d0 1241 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1242 ieee80211_free_hw(sc->hw);
1243}
1244
6baff7f9 1245void ath_detach(struct ath_softc *sc)
f078f209 1246{
8feceb67 1247 struct ieee80211_hw *hw = sc->hw;
9c84b797 1248 int i = 0;
f078f209 1249
3cbb5dd7
VN		 1250 ath9k_ps_wakeup(sc);
1251
04bd4638 1252 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1253
3fcdfb4b 1254 ath_deinit_leds(sc);
164ace38 1255 cancel_delayed_work_sync(&sc->tx_complete_work);
9851bad7
LR		 1256 cancel_delayed_work_sync(&sc->wiphy_work);
1257 cancel_work_sync(&sc->chan_work);
3fcdfb4b 1258
c52f33d0
JM		 1259 for (i = 0; i < sc->num_sec_wiphy; i++) {
1260 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1261 if (aphy == NULL)
1262 continue;
1263 sc->sec_wiphy[i] = NULL;
1264 ieee80211_unregister_hw(aphy->hw);
1265 ieee80211_free_hw(aphy->hw);
1266 }
3fcdfb4b 1267 ieee80211_unregister_hw(hw);
8feceb67
VT		 1268 ath_rx_cleanup(sc);
1269 ath_tx_cleanup(sc);
f078f209 1270
9c84b797
S		 1271 tasklet_kill(&sc->intr_tq);
1272 tasklet_kill(&sc->bcon_tasklet);
f078f209 1273
9c84b797
S		 1274 if (!(sc->sc_flags & SC_OP_INVALID))
1275 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1276
9c84b797
S		 1277 /* cleanup tx queues */
1278 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1279 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1280 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1281
1282 ath9k_hw_detach(sc->sc_ah);
826d2680 1283 ath9k_exit_debug(sc);
f078f209
LR		 1284}
1285
e3bb249b
BC		 1286static int ath9k_reg_notifier(struct wiphy *wiphy,
1287 struct regulatory_request *request)
1288{
1289 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1290 struct ath_wiphy *aphy = hw->priv;
1291 struct ath_softc *sc = aphy->sc;
1292 struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1293
1294 return ath_reg_notifier_apply(wiphy, request, reg);
1295}
1296
ff37e337
S		 1297static int ath_init(u16 devid, struct ath_softc *sc)
1298{
cbe61d8a 1299 struct ath_hw *ah = NULL;
ff37e337
S		 1300 int status;
1301 int error = 0, i;
1302 int csz = 0;
1303
1304 /* XXX: hardware will not be ready until ath_open() being called */
1305 sc->sc_flags |= SC_OP_INVALID;
88b126af 1306
826d2680
S		 1307 if (ath9k_init_debug(sc) < 0)
1308 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337 1309
c52f33d0 1310 spin_lock_init(&sc->wiphy_lock);
ff37e337 1311 spin_lock_init(&sc->sc_resetlock);
6158425b 1312 spin_lock_init(&sc->sc_serial_rw);
e5f0921a 1313 spin_lock_init(&sc->ani_lock);
04717ccd 1314 spin_lock_init(&sc->sc_pm_lock);
aa33de09 1315 mutex_init(&sc->mutex);
ff37e337 1316 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1317 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1318 (unsigned long)sc);
1319
1320 /*
1321 * Cache line size is used to size and align various
1322 * structures used to communicate with the hardware.
1323 */
88d15707 1324 ath_read_cachesize(sc, &csz);
ff37e337 1325 /* XXX assert csz is non-zero */
17d7904d 1326 sc->cachelsz = csz << 2; /* convert to bytes */
ff37e337 1327
cbe61d8a 1328 ah = ath9k_hw_attach(devid, sc, &status);
ff37e337
S		 1329 if (ah == NULL) {
1330 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1331 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1332 error = -ENXIO;
1333 goto bad;
1334 }
1335 sc->sc_ah = ah;
1336
1337 /* Get the hardware key cache size. */
2660b81a 1338 sc->keymax = ah->caps.keycache_size;
17d7904d 1339 if (sc->keymax > ATH_KEYMAX) {
d8baa939 1340 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 1341 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1342 ATH_KEYMAX, sc->keymax);
1343 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1344 }
1345
1346 /*
1347 * Reset the key cache since some parts do not
1348 * reset the contents on initial power up.
1349 */
17d7904d 1350 for (i = 0; i < sc->keymax; i++)
ff37e337 1351 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1352
85efc86e 1353 if (error)
ff37e337
S		 1354 goto bad;
1355
1356 /* default to MONITOR mode */
2660b81a 1357 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1358
ff37e337
S		 1359 /* Setup rate tables */
1360
1361 ath_rate_attach(sc);
1362 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1363 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1364
1365 /*
1366 * Allocate hardware transmit queues: one queue for
1367 * beacon frames and one data queue for each QoS
1368 * priority. Note that the hal handles reseting
1369 * these queues at the needed time.
1370 */
b77f483f
S		 1371 sc->beacon.beaconq = ath_beaconq_setup(ah);
1372 if (sc->beacon.beaconq == -1) {
ff37e337 1373 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1374 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1375 error = -EIO;
1376 goto bad2;
1377 }
b77f483f
S		 1378 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1379 if (sc->beacon.cabq == NULL) {
ff37e337 1380 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1381 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1382 error = -EIO;
1383 goto bad2;
1384 }
1385
17d7904d 1386 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1387 ath_cabq_update(sc);
1388
b77f483f
S		 1389 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1390 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1391
1392 /* Setup data queues */
1393 /* NB: ensure BK queue is the lowest priority h/w queue */
1394 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1395 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1396 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1397 error = -EIO;
1398 goto bad2;
1399 }
1400
1401 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1402 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1403 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1404 error = -EIO;
1405 goto bad2;
1406 }
1407 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1408 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1409 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1410 error = -EIO;
1411 goto bad2;
1412 }
1413 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1414 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1415 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1416 error = -EIO;
1417 goto bad2;
1418 }
1419
1420 /* Initializes the noise floor to a reasonable default value.
1421 * Later on this will be updated during ANI processing. */
1422
17d7904d
S		 1423 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1424 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1425
1426 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1427 ATH9K_CIPHER_TKIP, NULL)) {
1428 /*
1429 * Whether we should enable h/w TKIP MIC.
1430 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1431 * report WMM capable, so it's always safe to turn on
1432 * TKIP MIC in this case.
1433 */
1434 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1435 0, 1, NULL);
1436 }
1437
1438 /*
1439 * Check whether the separate key cache entries
1440 * are required to handle both tx+rx MIC keys.
1441 * With split mic keys the number of stations is limited
1442 * to 27 otherwise 59.
1443 */
1444 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1445 ATH9K_CIPHER_TKIP, NULL)
1446 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1447 ATH9K_CIPHER_MIC, NULL)
1448 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1449 0, NULL))
17d7904d 1450 sc->splitmic = 1;
ff37e337
S		 1451
1452 /* turn on mcast key search if possible */
1453 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1454 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1455 1, NULL);
1456
17d7904d 1457 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1458
1459 /* 11n Capabilities */
2660b81a 1460 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1461 sc->sc_flags |= SC_OP_TXAGGR;
1462 sc->sc_flags |= SC_OP_RXAGGR;
1463 }
1464
2660b81a
S		 1465 sc->tx_chainmask = ah->caps.tx_chainmask;
1466 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1467
1468 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1469 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1470
8ca21f01 1471 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1472 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1473
b77f483f 1474 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1475
1476 /* initialize beacon slots */
c52f33d0 1477 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1478 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1479 sc->beacon.bslot_aphy[i] = NULL;
1480 }
ff37e337 1481
ff37e337
S		 1482 /* setup channels and rates */
1483
5f8e077c 1484 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1485 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1486 sc->rates[IEEE80211_BAND_2GHZ];
1487 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1488 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1489 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1490
2660b81a 1491 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1492 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1493 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1494 sc->rates[IEEE80211_BAND_5GHZ];
1495 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1496 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1497 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1498 }
1499
2660b81a 1500 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
c97c92d9
VT		 1501 ath9k_hw_btcoex_enable(sc->sc_ah);
1502
ff37e337
S		 1503 return 0;
1504bad2:
1505 /* cleanup tx queues */
1506 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1507 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1508 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1509bad:
1510 if (ah)
1511 ath9k_hw_detach(ah);
40b130a9 1512 ath9k_exit_debug(sc);
ff37e337
S		 1513
1514 return error;
1515}
1516
c52f33d0 1517void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1518{
9c84b797
S		 1519 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1520 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1521 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1522 IEEE80211_HW_AMPDU_AGGREGATION |
1523 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1524 IEEE80211_HW_PS_NULLFUNC_STACK |
1525 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1526
b3bd89ce 1527 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1528 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1529
9c84b797
S		 1530 hw->wiphy->interface_modes =
1531 BIT(NL80211_IFTYPE_AP) |
1532 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1533 BIT(NL80211_IFTYPE_ADHOC) |
1534 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1535
8feceb67 1536 hw->queues = 4;
e63835b0 1537 hw->max_rates = 4;
171387ef 1538 hw->channel_change_time = 5000;
465ca84d 1539 hw->max_listen_interval = 10;
dd190183
LR		 1540 /* Hardware supports 10 but we use 4 */
1541 hw->max_rate_tries = 4;
528f0c6b 1542 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1543 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1544
8feceb67 1545 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1546
c52f33d0
JM		 1547 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1548 &sc->sbands[IEEE80211_BAND_2GHZ];
1549 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1550 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1551 &sc->sbands[IEEE80211_BAND_5GHZ];
1552}
1553
1554int ath_attach(u16 devid, struct ath_softc *sc)
1555{
1556 struct ieee80211_hw *hw = sc->hw;
c52f33d0 1557 int error = 0, i;
3a702e49 1558 struct ath_regulatory *reg;
c52f33d0
JM		 1559
1560 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1561
1562 error = ath_init(devid, sc);
1563 if (error != 0)
1564 return error;
1565
1566 /* get mac address from hardware and set in mac80211 */
1567
1568 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1569
1570 ath_set_hw_capab(sc, hw);
1571
c26c2e57
LR		 1572 error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1573 ath9k_reg_notifier);
1574 if (error)
1575 return error;
1576
1577 reg = &sc->sc_ah->regulatory;
1578
2660b81a 1579 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1580 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1581 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1582 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1583 }
1584
db93e7b5
SB		 1585 /* initialize tx/rx engine */
1586 error = ath_tx_init(sc, ATH_TXBUF);
1587 if (error != 0)
40b130a9 1588 goto error_attach;
8feceb67 1589
db93e7b5
SB		 1590 error = ath_rx_init(sc, ATH_RXBUF);
1591 if (error != 0)
40b130a9 1592 goto error_attach;
8feceb67 1593
0e2dedf9 1594 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1595 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1596 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1597
db93e7b5 1598 error = ieee80211_register_hw(hw);
8feceb67 1599
3a702e49 1600 if (!ath_is_world_regd(reg)) {
c02cf373 1601 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1602 if (error)
1603 goto error_attach;
1604 }
5f8e077c 1605
db93e7b5
SB		 1606 /* Initialize LED control */
1607 ath_init_leds(sc);
8feceb67 1608
3b319aae 1609 ath_start_rfkill_poll(sc);
5f8e077c 1610
8feceb67 1611 return 0;
40b130a9
VT		 1612
1613error_attach:
1614 /* cleanup tx queues */
1615 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1616 if (ATH_TXQ_SETUP(sc, i))
1617 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1618
1619 ath9k_hw_detach(sc->sc_ah);
1620 ath9k_exit_debug(sc);
1621
8feceb67 1622 return error;
f078f209
LR		 1623}
1624
ff37e337
S		 1625int ath_reset(struct ath_softc *sc, bool retry_tx)
1626{
cbe61d8a 1627 struct ath_hw *ah = sc->sc_ah;
030bb495 1628 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1629 int r;
ff37e337
S		 1630
1631 ath9k_hw_set_interrupts(ah, 0);
043a0405 1632 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1633 ath_stoprecv(sc);
1634 ath_flushrecv(sc);
1635
1636 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1637 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1638 if (r)
ff37e337 1639 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1640 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 1641 spin_unlock_bh(&sc->sc_resetlock);
1642
1643 if (ath_startrecv(sc) != 0)
04bd4638 1644 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1645
1646 /*
1647 * We may be doing a reset in response to a request
1648 * that changes the channel so update any state that
1649 * might change as a result.
1650 */
ce111bad 1651 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1652
1653 ath_update_txpow(sc);
1654
1655 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1656 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1657
17d7904d 1658 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1659
1660 if (retry_tx) {
1661 int i;
1662 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1663 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1664 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1665 ath_txq_schedule(sc, &sc->tx.txq[i]);
1666 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1667 }
1668 }
1669 }
1670
ae8d2858 1671 return r;
ff37e337
S		 1672}
1673
1674/*
1675 * This function will allocate both the DMA descriptor structure, and the
1676 * buffers it contains. These are used to contain the descriptors used
1677 * by the system.
1678*/
1679int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1680 struct list_head *head, const char *name,
1681 int nbuf, int ndesc)
1682{
1683#define DS2PHYS(_dd, _ds) \
1684 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1685#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1686#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1687
1688 struct ath_desc *ds;
1689 struct ath_buf *bf;
1690 int i, bsize, error;
1691
04bd4638
S		 1692 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1693 name, nbuf, ndesc);
ff37e337 1694
b03a9db9 1695 INIT_LIST_HEAD(head);
ff37e337
S		 1696 /* ath_desc must be a multiple of DWORDs */
1697 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1698 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1699 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1700 error = -ENOMEM;
1701 goto fail;
1702 }
1703
ff37e337
S		 1704 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1705
1706 /*
1707 * Need additional DMA memory because we can't use
1708 * descriptors that cross the 4K page boundary. Assume
1709 * one skipped descriptor per 4K page.
1710 */
2660b81a 1711 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1712 u32 ndesc_skipped =
1713 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1714 u32 dma_len;
1715
1716 while (ndesc_skipped) {
1717 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1718 dd->dd_desc_len += dma_len;
1719
1720 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1721 };
1722 }
1723
1724 /* allocate descriptors */
7da3c55c 1725 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 1726 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 1727 if (dd->dd_desc == NULL) {
1728 error = -ENOMEM;
1729 goto fail;
1730 }
1731 ds = dd->dd_desc;
04bd4638 1732 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
ae459af1 1733 name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1734 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1735
1736 /* allocate buffers */
1737 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 1738 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 1739 if (bf == NULL) {
1740 error = -ENOMEM;
1741 goto fail2;
1742 }
ff37e337
S		 1743 dd->dd_bufptr = bf;
1744
ff37e337
S		 1745 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1746 bf->bf_desc = ds;
1747 bf->bf_daddr = DS2PHYS(dd, ds);
1748
2660b81a 1749 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1750 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1751 /*
1752 * Skip descriptor addresses which can cause 4KB
1753 * boundary crossing (addr + length) with a 32 dword
1754 * descriptor fetch.
1755 */
1756 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1757 ASSERT((caddr_t) bf->bf_desc <
1758 ((caddr_t) dd->dd_desc +
1759 dd->dd_desc_len));
1760
1761 ds += ndesc;
1762 bf->bf_desc = ds;
1763 bf->bf_daddr = DS2PHYS(dd, ds);
1764 }
1765 }
1766 list_add_tail(&bf->list, head);
1767 }
1768 return 0;
1769fail2:
7da3c55c
GJ		 1770 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1771 dd->dd_desc_paddr);
ff37e337
S		 1772fail:
1773 memset(dd, 0, sizeof(*dd));
1774 return error;
1775#undef ATH_DESC_4KB_BOUND_CHECK
1776#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1777#undef DS2PHYS
1778}
1779
1780void ath_descdma_cleanup(struct ath_softc *sc,
1781 struct ath_descdma *dd,
1782 struct list_head *head)
1783{
7da3c55c
GJ		 1784 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1785 dd->dd_desc_paddr);
ff37e337
S		 1786
1787 INIT_LIST_HEAD(head);
1788 kfree(dd->dd_bufptr);
1789 memset(dd, 0, sizeof(*dd));
1790}
1791
1792int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1793{
1794 int qnum;
1795
1796 switch (queue) {
1797 case 0:
b77f483f 1798 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1799 break;
1800 case 1:
b77f483f 1801 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1802 break;
1803 case 2:
b77f483f 1804 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1805 break;
1806 case 3:
b77f483f 1807 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1808 break;
1809 default:
b77f483f 1810 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1811 break;
1812 }
1813
1814 return qnum;
1815}
1816
1817int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1818{
1819 int qnum;
1820
1821 switch (queue) {
1822 case ATH9K_WME_AC_VO:
1823 qnum = 0;
1824 break;
1825 case ATH9K_WME_AC_VI:
1826 qnum = 1;
1827 break;
1828 case ATH9K_WME_AC_BE:
1829 qnum = 2;
1830 break;
1831 case ATH9K_WME_AC_BK:
1832 qnum = 3;
1833 break;
1834 default:
1835 qnum = -1;
1836 break;
1837 }
1838
1839 return qnum;
1840}
1841
5f8e077c
LR		 1842/* XXX: Remove me once we don't depend on ath9k_channel for all
1843 * this redundant data */
0e2dedf9
JM		 1844void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1845 struct ath9k_channel *ichan)
5f8e077c 1846{
5f8e077c
LR		 1847 struct ieee80211_channel *chan = hw->conf.channel;
1848 struct ieee80211_conf *conf = &hw->conf;
1849
1850 ichan->channel = chan->center_freq;
1851 ichan->chan = chan;
1852
1853 if (chan->band == IEEE80211_BAND_2GHZ) {
1854 ichan->chanmode = CHANNEL_G;
1855 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1856 } else {
1857 ichan->chanmode = CHANNEL_A;
1858 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1859 }
1860
1861 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1862
1863 if (conf_is_ht(conf)) {
1864 if (conf_is_ht40(conf))
1865 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1866
1867 ichan->chanmode = ath_get_extchanmode(sc, chan,
1868 conf->channel_type);
1869 }
1870}
1871
ff37e337
S		 1872/**********************/
1873/* mac80211 callbacks */
1874/**********************/
1875
8feceb67 1876static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1877{
bce048d7
JM		 1878 struct ath_wiphy *aphy = hw->priv;
1879 struct ath_softc *sc = aphy->sc;
8feceb67 1880 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1881 struct ath9k_channel *init_channel;
82880a7c 1882 int r;
f078f209 1883
04bd4638
S		 1884 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1885 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1886
141b38b6
S		 1887 mutex_lock(&sc->mutex);
1888
9580a222
JM		 1889 if (ath9k_wiphy_started(sc)) {
1890 if (sc->chan_idx == curchan->hw_value) {
1891 /*
1892 * Already on the operational channel, the new wiphy
1893 * can be marked active.
1894 */
1895 aphy->state = ATH_WIPHY_ACTIVE;
1896 ieee80211_wake_queues(hw);
1897 } else {
1898 /*
1899 * Another wiphy is on another channel, start the new
1900 * wiphy in paused state.
1901 */
1902 aphy->state = ATH_WIPHY_PAUSED;
1903 ieee80211_stop_queues(hw);
1904 }
1905 mutex_unlock(&sc->mutex);
1906 return 0;
1907 }
1908 aphy->state = ATH_WIPHY_ACTIVE;
1909
8feceb67 1910 /* setup initial channel */
f078f209 1911
82880a7c 1912 sc->chan_idx = curchan->hw_value;
f078f209 1913
82880a7c 1914 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S		 1915
1916 /* Reset SERDES registers */
1917 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1918
1919 /*
1920 * The basic interface to setting the hardware in a good
1921 * state is ``reset''. On return the hardware is known to
1922 * be powered up and with interrupts disabled. This must
1923 * be followed by initialization of the appropriate bits
1924 * and then setup of the interrupt mask.
1925 */
1926 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1927 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1928 if (r) {
ff37e337 1929 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1930 "Unable to reset hardware; reset status %d "
ae8d2858
LR		 1931 "(freq %u MHz)\n", r,
1932 curchan->center_freq);
ff37e337 1933 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1934 goto mutex_unlock;
ff37e337
S		 1935 }
1936 spin_unlock_bh(&sc->sc_resetlock);
1937
1938 /*
1939 * This is needed only to setup initial state
1940 * but it's best done after a reset.
1941 */
1942 ath_update_txpow(sc);
8feceb67 1943
ff37e337
S		 1944 /*
1945 * Setup the hardware after reset:
1946 * The receive engine is set going.
1947 * Frame transmit is handled entirely
1948 * in the frame output path; there's nothing to do
1949 * here except setup the interrupt mask.
1950 */
1951 if (ath_startrecv(sc) != 0) {
1ffb0610 1952 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
141b38b6
S		 1953 r = -EIO;
1954 goto mutex_unlock;
f078f209 1955 }
8feceb67 1956
ff37e337 1957 /* Setup our intr mask. */
17d7904d 1958 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 1959 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1960 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1961
2660b81a 1962 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 1963 sc->imask |= ATH9K_INT_GTT;
ff37e337 1964
2660b81a 1965 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 1966 sc->imask |= ATH9K_INT_CST;
ff37e337 1967
ce111bad 1968 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1969
1970 sc->sc_flags &= ~SC_OP_INVALID;
1971
1972 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 1973 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1974 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337 1975
bce048d7 1976 ieee80211_wake_queues(hw);
ff37e337 1977
164ace38
SB		 1978 queue_delayed_work(sc->hw->workqueue, &sc->tx_complete_work, 0);
1979
141b38b6
S		 1980mutex_unlock:
1981 mutex_unlock(&sc->mutex);
1982
ae8d2858 1983 return r;
f078f209
LR		 1984}
1985
8feceb67
VT		 1986static int ath9k_tx(struct ieee80211_hw *hw,
1987 struct sk_buff *skb)
f078f209 1988{
528f0c6b 1989 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 1990 struct ath_wiphy *aphy = hw->priv;
1991 struct ath_softc *sc = aphy->sc;
528f0c6b 1992 struct ath_tx_control txctl;
8feceb67 1993 int hdrlen, padsize;
528f0c6b 1994
8089cc47 1995 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
ee166a0e
JM		 1996 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
1997 "%d\n", wiphy_name(hw->wiphy), aphy->state);
1998 goto exit;
1999 }
2000
96148326 2001 if (sc->ps_enabled) {
dc8c4585
JM		 2002 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2003 /*
2004 * mac80211 does not set PM field for normal data frames, so we
2005 * need to update that based on the current PS mode.
2006 */
2007 if (ieee80211_is_data(hdr->frame_control) &&
2008 !ieee80211_is_nullfunc(hdr->frame_control) &&
2009 !ieee80211_has_pm(hdr->frame_control)) {
2010 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2011 "while in PS mode\n");
2012 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2013 }
2014 }
2015
9a23f9ca
JM		 2016 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2017 /*
2018 * We are using PS-Poll and mac80211 can request TX while in
2019 * power save mode. Need to wake up hardware for the TX to be
2020 * completed and if needed, also for RX of buffered frames.
2021 */
2022 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2023 ath9k_ps_wakeup(sc);
2024 ath9k_hw_setrxabort(sc->sc_ah, 0);
2025 if (ieee80211_is_pspoll(hdr->frame_control)) {
2026 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2027 "buffered frame\n");
2028 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2029 } else {
2030 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2031 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2032 }
2033 /*
2034 * The actual restore operation will happen only after
2035 * the sc_flags bit is cleared. We are just dropping
2036 * the ps_usecount here.
2037 */
2038 ath9k_ps_restore(sc);
2039 }
2040
528f0c6b 2041 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2042
8feceb67
VT		 2043 /*
2044 * As a temporary workaround, assign seq# here; this will likely need
2045 * to be cleaned up to work better with Beacon transmission and virtual
2046 * BSSes.
2047 */
2048 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2049 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2050 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2051 sc->tx.seq_no += 0x10;
8feceb67 2052 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2053 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2054 }
f078f209 2055
8feceb67
VT		 2056 /* Add the padding after the header if this is not already done */
2057 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2058 if (hdrlen & 3) {
2059 padsize = hdrlen % 4;
2060 if (skb_headroom(skb) < padsize)
2061 return -1;
2062 skb_push(skb, padsize);
2063 memmove(skb->data, skb->data + padsize, hdrlen);
2064 }
2065
528f0c6b
S		 2066 /* Check if a tx queue is available */
2067
2068 txctl.txq = ath_test_get_txq(sc, skb);
2069 if (!txctl.txq)
2070 goto exit;
2071
04bd4638 2072 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2073
c52f33d0 2074 if (ath_tx_start(hw, skb, &txctl) != 0) {
04bd4638 2075 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2076 goto exit;
8feceb67
VT		 2077 }
2078
528f0c6b
S		 2079 return 0;
2080exit:
2081 dev_kfree_skb_any(skb);
8feceb67 2082 return 0;
f078f209
LR		 2083}
2084
8feceb67 2085static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2086{
bce048d7
JM		 2087 struct ath_wiphy *aphy = hw->priv;
2088 struct ath_softc *sc = aphy->sc;
f078f209 2089
9580a222
JM		 2090 aphy->state = ATH_WIPHY_INACTIVE;
2091
9c84b797 2092 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2093 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2094 return;
2095 }
8feceb67 2096
141b38b6 2097 mutex_lock(&sc->mutex);
ff37e337 2098
9580a222
JM		 2099 if (ath9k_wiphy_started(sc)) {
2100 mutex_unlock(&sc->mutex);
2101 return; /* another wiphy still in use */
2102 }
2103
ff37e337
S		 2104 /* make sure h/w will not generate any interrupt
2105 * before setting the invalid flag. */
2106 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2107
2108 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2109 ath_drain_all_txq(sc, false);
ff37e337
S		 2110 ath_stoprecv(sc);
2111 ath9k_hw_phy_disable(sc->sc_ah);
2112 } else
b77f483f 2113 sc->rx.rxlink = NULL;
ff37e337 2114
3b319aae 2115 wiphy_rfkill_stop_polling(sc->hw->wiphy);
19d337df 2116
ff37e337
S		 2117 /* disable HAL and put h/w to sleep */
2118 ath9k_hw_disable(sc->sc_ah);
2119 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2120
2121 sc->sc_flags |= SC_OP_INVALID;
500c064d 2122
141b38b6
S		 2123 mutex_unlock(&sc->mutex);
2124
04bd4638 2125 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2126}
2127
8feceb67
VT		 2128static int ath9k_add_interface(struct ieee80211_hw *hw,
2129 struct ieee80211_if_init_conf *conf)
f078f209 2130{
bce048d7
JM		 2131 struct ath_wiphy *aphy = hw->priv;
2132 struct ath_softc *sc = aphy->sc;
17d7904d 2133 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2134 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2135 int ret = 0;
8feceb67 2136
141b38b6
S		 2137 mutex_lock(&sc->mutex);
2138
8ca21f01
JM		 2139 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2140 sc->nvifs > 0) {
2141 ret = -ENOBUFS;
2142 goto out;
2143 }
2144
8feceb67 2145 switch (conf->type) {
05c914fe 2146 case NL80211_IFTYPE_STATION:
d97809db 2147 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2148 break;
05c914fe 2149 case NL80211_IFTYPE_ADHOC:
05c914fe 2150 case NL80211_IFTYPE_AP:
9cb5412b 2151 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2152 if (sc->nbcnvifs >= ATH_BCBUF) {
2153 ret = -ENOBUFS;
2154 goto out;
2155 }
9cb5412b 2156 ic_opmode = conf->type;
f078f209
LR		 2157 break;
2158 default:
2159 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2160 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2161 ret = -EOPNOTSUPP;
2162 goto out;
f078f209
LR		 2163 }
2164
17d7904d 2165 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2166
17d7904d 2167 /* Set the VIF opmode */
5640b08e
S		 2168 avp->av_opmode = ic_opmode;
2169 avp->av_bslot = -1;
2170
2c3db3d5 2171 sc->nvifs++;
8ca21f01
JM		 2172
2173 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2174 ath9k_set_bssid_mask(hw);
2175
2c3db3d5
JM		 2176 if (sc->nvifs > 1)
2177 goto out; /* skip global settings for secondary vif */
2178
b238e90e 2179 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2180 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2181 sc->sc_flags |= SC_OP_TSF_RESET;
2182 }
5640b08e 2183
5640b08e 2184 /* Set the device opmode */
2660b81a 2185 sc->sc_ah->opmode = ic_opmode;
5640b08e 2186
4e30ffa2
VN		 2187 /*
2188 * Enable MIB interrupts when there are hardware phy counters.
2189 * Note we only do this (at the moment) for station mode.
2190 */
4af9cf4f 2191 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2192 (conf->type == NL80211_IFTYPE_ADHOC) ||
2193 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
4af9cf4f
S		 2194 if (ath9k_hw_phycounters(sc->sc_ah))
2195 sc->imask |= ATH9K_INT_MIB;
2196 sc->imask |= ATH9K_INT_TSFOOR;
2197 }
2198
17d7904d 2199 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2200
f38faa31
SB		 2201 if (conf->type == NL80211_IFTYPE_AP ||
2202 conf->type == NL80211_IFTYPE_ADHOC ||
2203 conf->type == NL80211_IFTYPE_MONITOR)
415f738e 2204 ath_start_ani(sc);
6f255425 2205
2c3db3d5 2206out:
141b38b6 2207 mutex_unlock(&sc->mutex);
2c3db3d5 2208 return ret;
f078f209
LR		 2209}
2210
8feceb67
VT		 2211static void ath9k_remove_interface(struct ieee80211_hw *hw,
2212 struct ieee80211_if_init_conf *conf)
f078f209 2213{
bce048d7
JM		 2214 struct ath_wiphy *aphy = hw->priv;
2215 struct ath_softc *sc = aphy->sc;
17d7904d 2216 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2217 int i;
f078f209 2218
04bd4638 2219 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2220
141b38b6
S		 2221 mutex_lock(&sc->mutex);
2222
6f255425 2223 /* Stop ANI */
17d7904d 2224 del_timer_sync(&sc->ani.timer);
580f0b8a 2225
8feceb67 2226 /* Reclaim beacon resources */
9cb5412b
PE		 2227 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2228 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2229 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2230 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2231 ath_beacon_return(sc, avp);
580f0b8a 2232 }
f078f209 2233
8feceb67 2234 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2235
2c3db3d5
JM		 2236 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2237 if (sc->beacon.bslot[i] == conf->vif) {
2238 printk(KERN_DEBUG "%s: vif had allocated beacon "
2239 "slot\n", __func__);
2240 sc->beacon.bslot[i] = NULL;
c52f33d0 2241 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2242 }
2243 }
2244
17d7904d 2245 sc->nvifs--;
141b38b6
S		 2246
2247 mutex_unlock(&sc->mutex);
f078f209
LR		 2248}
2249
e8975581 2250static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2251{
bce048d7
JM		 2252 struct ath_wiphy *aphy = hw->priv;
2253 struct ath_softc *sc = aphy->sc;
e8975581 2254 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2255 struct ath_hw *ah = sc->sc_ah;
64839170 2256 bool all_wiphys_idle = false, disable_radio = false;
f078f209 2257
aa33de09 2258 mutex_lock(&sc->mutex);
141b38b6 2259
64839170
LR		 2260 /* Leave this as the first check */
2261 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2262
2263 spin_lock_bh(&sc->wiphy_lock);
2264 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2265 spin_unlock_bh(&sc->wiphy_lock);
2266
2267 if (conf->flags & IEEE80211_CONF_IDLE){
2268 if (all_wiphys_idle)
2269 disable_radio = true;
2270 }
2271 else if (all_wiphys_idle) {
2272 ath_radio_enable(sc);
2273 DPRINTF(sc, ATH_DBG_CONFIG,
2274 "not-idle: enabling radio\n");
2275 }
2276 }
2277
3cbb5dd7
VN		 2278 if (changed & IEEE80211_CONF_CHANGE_PS) {
2279 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2280 if (!(ah->caps.hw_caps &
2281 ATH9K_HW_CAP_AUTOSLEEP)) {
2282 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2283 sc->imask |= ATH9K_INT_TIM_TIMER;
2284 ath9k_hw_set_interrupts(sc->sc_ah,
2285 sc->imask);
2286 }
2287 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2288 }
96148326 2289 sc->ps_enabled = true;
3cbb5dd7 2290 } else {
96148326 2291 sc->ps_enabled = false;
3cbb5dd7 2292 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8782b41d
VN		 2293 if (!(ah->caps.hw_caps &
2294 ATH9K_HW_CAP_AUTOSLEEP)) {
2295 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca
JM		 2296 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2297 SC_OP_WAIT_FOR_CAB |
2298 SC_OP_WAIT_FOR_PSPOLL_DATA |
2299 SC_OP_WAIT_FOR_TX_ACK);
8782b41d
VN		 2300 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2301 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2302 ath9k_hw_set_interrupts(sc->sc_ah,
2303 sc->imask);
2304 }
3cbb5dd7
VN		 2305 }
2306 }
2307 }
2308
4797938c 2309 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2310 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2311 int pos = curchan->hw_value;
ae5eb026 2312
0e2dedf9
JM		 2313 aphy->chan_idx = pos;
2314 aphy->chan_is_ht = conf_is_ht(conf);
2315
8089cc47
JM		 2316 if (aphy->state == ATH_WIPHY_SCAN ||
2317 aphy->state == ATH_WIPHY_ACTIVE)
2318 ath9k_wiphy_pause_all_forced(sc, aphy);
2319 else {
2320 /*
2321 * Do not change operational channel based on a paused
2322 * wiphy changes.
2323 */
2324 goto skip_chan_change;
2325 }
0e2dedf9 2326
04bd4638
S		 2327 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2328 curchan->center_freq);
f078f209 2329
5f8e077c 2330 /* XXX: remove me eventualy */
0e2dedf9 2331 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2332
ecf70441 2333 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2334
0e2dedf9 2335 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2336 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2337 mutex_unlock(&sc->mutex);
e11602b7
S		 2338 return -EINVAL;
2339 }
094d05dc 2340 }
f078f209 2341
8089cc47 2342skip_chan_change:
5c020dc6 2343 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2344 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2345
64839170
LR		 2346 if (disable_radio) {
2347 DPRINTF(sc, ATH_DBG_CONFIG, "idle: disabling radio\n");
2348 ath_radio_disable(sc);
2349 }
2350
aa33de09 2351 mutex_unlock(&sc->mutex);
141b38b6 2352
f078f209
LR		 2353 return 0;
2354}
2355
8feceb67
VT		 2356#define SUPPORTED_FILTERS \
2357 (FIF_PROMISC_IN_BSS | \
2358 FIF_ALLMULTI | \
2359 FIF_CONTROL | \
2360 FIF_OTHER_BSS | \
2361 FIF_BCN_PRBRESP_PROMISC | \
2362 FIF_FCSFAIL)
c83be688 2363
8feceb67
VT		 2364/* FIXME: sc->sc_full_reset ? */
2365static void ath9k_configure_filter(struct ieee80211_hw *hw,
2366 unsigned int changed_flags,
2367 unsigned int *total_flags,
2368 int mc_count,
2369 struct dev_mc_list *mclist)
2370{
bce048d7
JM		 2371 struct ath_wiphy *aphy = hw->priv;
2372 struct ath_softc *sc = aphy->sc;
8feceb67 2373 u32 rfilt;
f078f209 2374
8feceb67
VT		 2375 changed_flags &= SUPPORTED_FILTERS;
2376 *total_flags &= SUPPORTED_FILTERS;
f078f209 2377
b77f483f 2378 sc->rx.rxfilter = *total_flags;
aa68aeaa 2379 ath9k_ps_wakeup(sc);
8feceb67
VT		 2380 rfilt = ath_calcrxfilter(sc);
2381 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 2382 ath9k_ps_restore(sc);
f078f209 2383
b77f483f 2384 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2385}
f078f209 2386
8feceb67
VT		 2387static void ath9k_sta_notify(struct ieee80211_hw *hw,
2388 struct ieee80211_vif *vif,
2389 enum sta_notify_cmd cmd,
17741cdc 2390 struct ieee80211_sta *sta)
8feceb67 2391{
bce048d7
JM		 2392 struct ath_wiphy *aphy = hw->priv;
2393 struct ath_softc *sc = aphy->sc;
f078f209 2394
8feceb67
VT		 2395 switch (cmd) {
2396 case STA_NOTIFY_ADD:
5640b08e 2397 ath_node_attach(sc, sta);
8feceb67
VT		 2398 break;
2399 case STA_NOTIFY_REMOVE:
b5aa9bf9 2400 ath_node_detach(sc, sta);
8feceb67
VT		 2401 break;
2402 default:
2403 break;
2404 }
f078f209
LR		 2405}
2406
141b38b6 2407static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2408 const struct ieee80211_tx_queue_params *params)
f078f209 2409{
bce048d7
JM		 2410 struct ath_wiphy *aphy = hw->priv;
2411 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2412 struct ath9k_tx_queue_info qi;
2413 int ret = 0, qnum;
f078f209 2414
8feceb67
VT		 2415 if (queue >= WME_NUM_AC)
2416 return 0;
f078f209 2417
141b38b6
S		 2418 mutex_lock(&sc->mutex);
2419
1ffb0610
S		 2420 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2421
8feceb67
VT		 2422 qi.tqi_aifs = params->aifs;
2423 qi.tqi_cwmin = params->cw_min;
2424 qi.tqi_cwmax = params->cw_max;
2425 qi.tqi_burstTime = params->txop;
2426 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2427
8feceb67 2428 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2429 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2430 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2431 queue, qnum, params->aifs, params->cw_min,
2432 params->cw_max, params->txop);
f078f209 2433
8feceb67
VT		 2434 ret = ath_txq_update(sc, qnum, &qi);
2435 if (ret)
04bd4638 2436 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2437
141b38b6
S		 2438 mutex_unlock(&sc->mutex);
2439
8feceb67
VT		 2440 return ret;
2441}
f078f209 2442
8feceb67
VT		 2443static int ath9k_set_key(struct ieee80211_hw *hw,
2444 enum set_key_cmd cmd,
dc822b5d
JB		 2445 struct ieee80211_vif *vif,
2446 struct ieee80211_sta *sta,
8feceb67
VT		 2447 struct ieee80211_key_conf *key)
2448{
bce048d7
JM		 2449 struct ath_wiphy *aphy = hw->priv;
2450 struct ath_softc *sc = aphy->sc;
8feceb67 2451 int ret = 0;
f078f209 2452
b3bd89ce
JM		 2453 if (modparam_nohwcrypt)
2454 return -ENOSPC;
2455
141b38b6 2456 mutex_lock(&sc->mutex);
3cbb5dd7 2457 ath9k_ps_wakeup(sc);
d8baa939 2458 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2459
8feceb67
VT		 2460 switch (cmd) {
2461 case SET_KEY:
3f53dd64 2462 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2463 if (ret >= 0) {
2464 key->hw_key_idx = ret;
8feceb67
VT		 2465 /* push IV and Michael MIC generation to stack */
2466 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2467 if (key->alg == ALG_TKIP)
2468 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2469 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2470 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2471 ret = 0;
8feceb67
VT		 2472 }
2473 break;
2474 case DISABLE_KEY:
2475 ath_key_delete(sc, key);
8feceb67
VT		 2476 break;
2477 default:
2478 ret = -EINVAL;
2479 }
f078f209 2480
3cbb5dd7 2481 ath9k_ps_restore(sc);
141b38b6
S		 2482 mutex_unlock(&sc->mutex);
2483
8feceb67
VT		 2484 return ret;
2485}
f078f209 2486
8feceb67
VT		 2487static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2488 struct ieee80211_vif *vif,
2489 struct ieee80211_bss_conf *bss_conf,
2490 u32 changed)
2491{
bce048d7
JM		 2492 struct ath_wiphy *aphy = hw->priv;
2493 struct ath_softc *sc = aphy->sc;
2d0ddec5
JB		 2494 struct ath_hw *ah = sc->sc_ah;
2495 struct ath_vif *avp = (void *)vif->drv_priv;
2496 u32 rfilt = 0;
2497 int error, i;
f078f209 2498
141b38b6
S		 2499 mutex_lock(&sc->mutex);
2500
2d0ddec5
JB		 2501 /*
2502 * TODO: Need to decide which hw opmode to use for
2503 * multi-interface cases
2504 * XXX: This belongs into add_interface!
2505 */
2506 if (vif->type == NL80211_IFTYPE_AP &&
2507 ah->opmode != NL80211_IFTYPE_AP) {
2508 ah->opmode = NL80211_IFTYPE_STATION;
2509 ath9k_hw_setopmode(ah);
2510 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2511 sc->curaid = 0;
2512 ath9k_hw_write_associd(sc);
2513 /* Request full reset to get hw opmode changed properly */
2514 sc->sc_flags |= SC_OP_FULL_RESET;
2515 }
2516
2517 if ((changed & BSS_CHANGED_BSSID) &&
2518 !is_zero_ether_addr(bss_conf->bssid)) {
2519 switch (vif->type) {
2520 case NL80211_IFTYPE_STATION:
2521 case NL80211_IFTYPE_ADHOC:
2522 case NL80211_IFTYPE_MESH_POINT:
2523 /* Set BSSID */
2524 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2525 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2526 sc->curaid = 0;
2527 ath9k_hw_write_associd(sc);
2528
2529 /* Set aggregation protection mode parameters */
2530 sc->config.ath_aggr_prot = 0;
2531
2532 DPRINTF(sc, ATH_DBG_CONFIG,
2533 "RX filter 0x%x bssid %pM aid 0x%x\n",
2534 rfilt, sc->curbssid, sc->curaid);
2535
2536 /* need to reconfigure the beacon */
2537 sc->sc_flags &= ~SC_OP_BEACONS ;
2538
2539 break;
2540 default:
2541 break;
2542 }
2543 }
2544
2545 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2546 (vif->type == NL80211_IFTYPE_AP) ||
2547 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2548 if ((changed & BSS_CHANGED_BEACON) ||
2549 (changed & BSS_CHANGED_BEACON_ENABLED &&
2550 bss_conf->enable_beacon)) {
2551 /*
2552 * Allocate and setup the beacon frame.
2553 *
2554 * Stop any previous beacon DMA. This may be
2555 * necessary, for example, when an ibss merge
2556 * causes reconfiguration; we may be called
2557 * with beacon transmission active.
2558 */
2559 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2560
2561 error = ath_beacon_alloc(aphy, vif);
2562 if (!error)
2563 ath_beacon_config(sc, vif);
2564 }
2565 }
2566
2567 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2568 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2569 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2570 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2571 ath9k_hw_keysetmac(sc->sc_ah,
2572 (u16)i,
2573 sc->curbssid);
2574 }
2575
2576 /* Only legacy IBSS for now */
2577 if (vif->type == NL80211_IFTYPE_ADHOC)
2578 ath_update_chainmask(sc, 0);
2579
8feceb67 2580 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2581 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2582 bss_conf->use_short_preamble);
2583 if (bss_conf->use_short_preamble)
2584 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2585 else
2586 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2587 }
f078f209 2588
8feceb67 2589 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2590 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2591 bss_conf->use_cts_prot);
2592 if (bss_conf->use_cts_prot &&
2593 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2594 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2595 else
2596 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2597 }
f078f209 2598
8feceb67 2599 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2600 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2601 bss_conf->assoc);
5640b08e 2602 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2603 }
141b38b6 2604
57c4d7b4
JB		 2605 /*
2606 * The HW TSF has to be reset when the beacon interval changes.
2607 * We set the flag here, and ath_beacon_config_ap() would take this
2608 * into account when it gets called through the subsequent
2609 * config_interface() call - with IFCC_BEACON in the changed field.
2610 */
2611
2612 if (changed & BSS_CHANGED_BEACON_INT) {
2613 sc->sc_flags |= SC_OP_TSF_RESET;
2614 sc->beacon_interval = bss_conf->beacon_int;
2615 }
2616
141b38b6 2617 mutex_unlock(&sc->mutex);
8feceb67 2618}
f078f209 2619
8feceb67
VT		 2620static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2621{
2622 u64 tsf;
bce048d7
JM		 2623 struct ath_wiphy *aphy = hw->priv;
2624 struct ath_softc *sc = aphy->sc;
f078f209 2625
141b38b6
S		 2626 mutex_lock(&sc->mutex);
2627 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2628 mutex_unlock(&sc->mutex);
f078f209 2629
8feceb67
VT		 2630 return tsf;
2631}
f078f209 2632
3b5d665b
AF		 2633static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2634{
bce048d7
JM		 2635 struct ath_wiphy *aphy = hw->priv;
2636 struct ath_softc *sc = aphy->sc;
3b5d665b 2637
141b38b6
S		 2638 mutex_lock(&sc->mutex);
2639 ath9k_hw_settsf64(sc->sc_ah, tsf);
2640 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2641}
2642
8feceb67
VT		 2643static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2644{
bce048d7
JM		 2645 struct ath_wiphy *aphy = hw->priv;
2646 struct ath_softc *sc = aphy->sc;
c83be688 2647
141b38b6
S		 2648 mutex_lock(&sc->mutex);
2649 ath9k_hw_reset_tsf(sc->sc_ah);
2650 mutex_unlock(&sc->mutex);
8feceb67 2651}
f078f209 2652
8feceb67 2653static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2654 enum ieee80211_ampdu_mlme_action action,
2655 struct ieee80211_sta *sta,
2656 u16 tid, u16 *ssn)
8feceb67 2657{
bce048d7
JM		 2658 struct ath_wiphy *aphy = hw->priv;
2659 struct ath_softc *sc = aphy->sc;
8feceb67 2660 int ret = 0;
f078f209 2661
8feceb67
VT		 2662 switch (action) {
2663 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2664 if (!(sc->sc_flags & SC_OP_RXAGGR))
2665 ret = -ENOTSUPP;
8feceb67
VT		 2666 break;
2667 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2668 break;
2669 case IEEE80211_AMPDU_TX_START:
f83da965
S		 2670 ath_tx_aggr_start(sc, sta, tid, ssn);
2671 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2672 break;
2673 case IEEE80211_AMPDU_TX_STOP:
f83da965 2674 ath_tx_aggr_stop(sc, sta, tid);
17741cdc 2675 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2676 break;
b1720231 2677 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 2678 ath_tx_aggr_resume(sc, sta, tid);
2679 break;
8feceb67 2680 default:
04bd4638 2681 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2682 }
2683
2684 return ret;
f078f209
LR		 2685}
2686
0c98de65
S		 2687static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2688{
bce048d7
JM		 2689 struct ath_wiphy *aphy = hw->priv;
2690 struct ath_softc *sc = aphy->sc;
0c98de65 2691
8089cc47
JM		 2692 if (ath9k_wiphy_scanning(sc)) {
2693 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2694 "same time\n");
2695 /*
2696 * Do not allow the concurrent scanning state for now. This
2697 * could be improved with scanning control moved into ath9k.
2698 */
2699 return;
2700 }
2701
2702 aphy->state = ATH_WIPHY_SCAN;
2703 ath9k_wiphy_pause_all_forced(sc, aphy);
2704
e5f0921a 2705 spin_lock_bh(&sc->ani_lock);
0c98de65 2706 sc->sc_flags |= SC_OP_SCANNING;
e5f0921a 2707 spin_unlock_bh(&sc->ani_lock);
0c98de65
S		 2708}
2709
2710static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2711{
bce048d7
JM		 2712 struct ath_wiphy *aphy = hw->priv;
2713 struct ath_softc *sc = aphy->sc;
0c98de65 2714
e5f0921a 2715 spin_lock_bh(&sc->ani_lock);
8089cc47 2716 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 2717 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 2718 sc->sc_flags |= SC_OP_FULL_RESET;
e5f0921a 2719 spin_unlock_bh(&sc->ani_lock);
0c98de65
S		 2720}
2721
6baff7f9 2722struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2723 .tx = ath9k_tx,
2724 .start = ath9k_start,
2725 .stop = ath9k_stop,
2726 .add_interface = ath9k_add_interface,
2727 .remove_interface = ath9k_remove_interface,
2728 .config = ath9k_config,
8feceb67 2729 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2730 .sta_notify = ath9k_sta_notify,
2731 .conf_tx = ath9k_conf_tx,
8feceb67 2732 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2733 .set_key = ath9k_set_key,
8feceb67 2734 .get_tsf = ath9k_get_tsf,
3b5d665b 2735 .set_tsf = ath9k_set_tsf,
8feceb67 2736 .reset_tsf = ath9k_reset_tsf,
4233df6b 2737 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 2738 .sw_scan_start = ath9k_sw_scan_start,
2739 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 2740 .rfkill_poll = ath9k_rfkill_poll_state,
8feceb67
VT		 2741};
2742
392dff83
BP		 2743static struct {
2744 u32 version;
2745 const char * name;
2746} ath_mac_bb_names[] = {
2747 { AR_SREV_VERSION_5416_PCI, "5416" },
2748 { AR_SREV_VERSION_5416_PCIE, "5418" },
2749 { AR_SREV_VERSION_9100, "9100" },
2750 { AR_SREV_VERSION_9160, "9160" },
2751 { AR_SREV_VERSION_9280, "9280" },
ac88b6ec
VN		 2752 { AR_SREV_VERSION_9285, "9285" },
2753 { AR_SREV_VERSION_9287, "9287" }
392dff83
BP		 2754};
2755
2756static struct {
2757 u16 version;
2758 const char * name;
2759} ath_rf_names[] = {
2760 { 0, "5133" },
2761 { AR_RAD5133_SREV_MAJOR, "5133" },
2762 { AR_RAD5122_SREV_MAJOR, "5122" },
2763 { AR_RAD2133_SREV_MAJOR, "2133" },
2764 { AR_RAD2122_SREV_MAJOR, "2122" }
2765};
2766
2767/*
2768 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2769 */
6baff7f9 2770const char *
392dff83
BP		 2771ath_mac_bb_name(u32 mac_bb_version)
2772{
2773 int i;
2774
2775 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2776 if (ath_mac_bb_names[i].version == mac_bb_version) {
2777 return ath_mac_bb_names[i].name;
2778 }
2779 }
2780
2781 return "????";
2782}
2783
2784/*
2785 * Return the RF name. "????" is returned if the RF is unknown.
2786 */
6baff7f9 2787const char *
392dff83
BP		 2788ath_rf_name(u16 rf_version)
2789{
2790 int i;
2791
2792 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2793 if (ath_rf_names[i].version == rf_version) {
2794 return ath_rf_names[i].name;
2795 }
2796 }
2797
2798 return "????";
2799}
2800
6baff7f9 2801static int __init ath9k_init(void)
f078f209 2802{
ca8a8560
VT		 2803 int error;
2804
ca8a8560
VT		 2805 /* Register rate control algorithm */
2806 error = ath_rate_control_register();
2807 if (error != 0) {
2808 printk(KERN_ERR
b51bb3cd
LR		 2809 "ath9k: Unable to register rate control "
2810 "algorithm: %d\n",
ca8a8560 2811 error);
6baff7f9 2812 goto err_out;
ca8a8560
VT		 2813 }
2814
19d8bc22
GJ		 2815 error = ath9k_debug_create_root();
2816 if (error) {
2817 printk(KERN_ERR
2818 "ath9k: Unable to create debugfs root: %d\n",
2819 error);
2820 goto err_rate_unregister;
2821 }
2822
6baff7f9
GJ		 2823 error = ath_pci_init();
2824 if (error < 0) {
f078f209 2825 printk(KERN_ERR
b51bb3cd 2826 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 2827 error = -ENODEV;
19d8bc22 2828 goto err_remove_root;
f078f209
LR		 2829 }
2830
09329d37
GJ		 2831 error = ath_ahb_init();
2832 if (error < 0) {
2833 error = -ENODEV;
2834 goto err_pci_exit;
2835 }
2836
f078f209 2837 return 0;
6baff7f9 2838
09329d37
GJ		 2839 err_pci_exit:
2840 ath_pci_exit();
2841
19d8bc22
GJ		 2842 err_remove_root:
2843 ath9k_debug_remove_root();
6baff7f9
GJ		 2844 err_rate_unregister:
2845 ath_rate_control_unregister();
2846 err_out:
2847 return error;
f078f209 2848}
6baff7f9 2849module_init(ath9k_init);
f078f209 2850
6baff7f9 2851static void __exit ath9k_exit(void)
f078f209 2852{
09329d37 2853 ath_ahb_exit();
6baff7f9 2854 ath_pci_exit();
19d8bc22 2855 ath9k_debug_remove_root();
ca8a8560 2856 ath_rate_control_unregister();
04bd4638 2857 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2858}
6baff7f9 2859module_exit(ath9k_exit);
Linux kernel - Deliverables
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