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ath9k: Use ath_chanctx_check_active properly
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
313eb87f 22u8 ath9k_parse_mpdudensity(u8 mpdudensity)
ff37e337
S		 23{
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55}
56
69081624
VT		 57static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
58{
59 bool pending = false;
60
61 spin_lock_bh(&txq->axq_lock);
62
0453531e 63 if (txq->axq_depth)
69081624 64 pending = true;
69081624 65
0453531e
FF		 66 if (txq->mac80211_qnum >= 0) {
67 struct list_head *list;
68
69 list = &sc->cur_chan->acq[txq->mac80211_qnum];
70 if (!list_empty(list))
71 pending = true;
72 }
69081624
VT		 73 spin_unlock_bh(&txq->axq_lock);
74 return pending;
75}
76
6d79cb4c 77static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR		 78{
79 unsigned long flags;
80 bool ret;
81
9ecdef4b
LR		 82 spin_lock_irqsave(&sc->sc_pm_lock, flags);
83 ret = ath9k_hw_setpower(sc->sc_ah, mode);
84 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR		 85
86 return ret;
87}
88
bf3dac5a
FF		 89void ath_ps_full_sleep(unsigned long data)
90{
91 struct ath_softc *sc = (struct ath_softc *) data;
92 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
93 bool reset;
94
95 spin_lock(&common->cc_lock);
96 ath_hw_cycle_counters_update(common);
97 spin_unlock(&common->cc_lock);
98
99 ath9k_hw_setrxabort(sc->sc_ah, 1);
100 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
101
102 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
103}
104
a91d75ae
LR		 105void ath9k_ps_wakeup(struct ath_softc *sc)
106{
898c914a 107 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 108 unsigned long flags;
fbb078fc 109 enum ath9k_power_mode power_mode;
a91d75ae
LR		 110
111 spin_lock_irqsave(&sc->sc_pm_lock, flags);
112 if (++sc->ps_usecount != 1)
113 goto unlock;
114
bf3dac5a 115 del_timer_sync(&sc->sleep_timer);
fbb078fc 116 power_mode = sc->sc_ah->power_mode;
9ecdef4b 117 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 118
898c914a
FF		 119 /*
120 * While the hardware is asleep, the cycle counters contain no
121 * useful data. Better clear them now so that they don't mess up
122 * survey data results.
123 */
fbb078fc
FF		 124 if (power_mode != ATH9K_PM_AWAKE) {
125 spin_lock(&common->cc_lock);
126 ath_hw_cycle_counters_update(common);
127 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
c9ae6ab4 128 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
fbb078fc
FF		 129 spin_unlock(&common->cc_lock);
130 }
898c914a 131
a91d75ae
LR		 132 unlock:
133 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
134}
135
136void ath9k_ps_restore(struct ath_softc *sc)
137{
898c914a 138 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
c6c539f0 139 enum ath9k_power_mode mode;
a91d75ae
LR		 140 unsigned long flags;
141
142 spin_lock_irqsave(&sc->sc_pm_lock, flags);
143 if (--sc->ps_usecount != 0)
144 goto unlock;
145
ad128860 146 if (sc->ps_idle) {
bf3dac5a
FF		 147 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
148 goto unlock;
149 }
150
151 if (sc->ps_enabled &&
ad128860
SM		 152 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
153 PS_WAIT_FOR_CAB |
154 PS_WAIT_FOR_PSPOLL_DATA |
424749c7
RM		 155 PS_WAIT_FOR_TX_ACK |
156 PS_WAIT_FOR_ANI))) {
c6c539f0 157 mode = ATH9K_PM_NETWORK_SLEEP;
08d4df41
RM		 158 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
159 ath9k_btcoex_stop_gen_timer(sc);
ad128860 160 } else {
c6c539f0 161 goto unlock;
ad128860 162 }
c6c539f0
FF		 163
164 spin_lock(&common->cc_lock);
165 ath_hw_cycle_counters_update(common);
166 spin_unlock(&common->cc_lock);
167
1a8f0d39 168 ath9k_hw_setpower(sc->sc_ah, mode);
a91d75ae
LR		 169
170 unlock:
171 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
172}
173
9adcf440 174static void __ath_cancel_work(struct ath_softc *sc)
ff37e337 175{
5ee08656 176 cancel_work_sync(&sc->paprd_work);
5ee08656 177 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 178 cancel_delayed_work_sync(&sc->hw_pll_work);
fad29cd2 179
bf52592f 180#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
fad29cd2
SM		 181 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
182 cancel_work_sync(&sc->mci_work);
bf52592f 183#endif
9adcf440 184}
5ee08656 185
e60001e7 186void ath_cancel_work(struct ath_softc *sc)
9adcf440
FF		 187{
188 __ath_cancel_work(sc);
189 cancel_work_sync(&sc->hw_reset_work);
190}
3cbb5dd7 191
e60001e7 192void ath_restart_work(struct ath_softc *sc)
af68abad 193{
af68abad
SM		 194 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
195
19c36160 196 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
af68abad
SM		 197 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
198 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
199
da0d45f7 200 ath_start_ani(sc);
af68abad
SM		 201}
202
9ebea382 203static bool ath_prepare_reset(struct ath_softc *sc)
9adcf440
FF		 204{
205 struct ath_hw *ah = sc->sc_ah;
ceea2a51 206 bool ret = true;
6a6733f2 207
9adcf440 208 ieee80211_stop_queues(sc->hw);
da0d45f7 209 ath_stop_ani(sc);
9adcf440 210 ath9k_hw_disable_interrupts(ah);
8b3f4616 211
1381559b 212 if (!ath_drain_all_txq(sc))
9adcf440 213 ret = false;
c0d7c7af 214
0a62acb1 215 if (!ath_stoprecv(sc))
ceea2a51
FF		 216 ret = false;
217
9adcf440
FF		 218 return ret;
219}
ff37e337 220
9adcf440
FF		 221static bool ath_complete_reset(struct ath_softc *sc, bool start)
222{
223 struct ath_hw *ah = sc->sc_ah;
224 struct ath_common *common = ath9k_hw_common(ah);
196fb860 225 unsigned long flags;
c0d7c7af 226
c0d7c7af 227 if (ath_startrecv(sc) != 0) {
3800276a 228 ath_err(common, "Unable to restart recv logic\n");
9adcf440 229 return false;
c0d7c7af
LR		 230 }
231
5048e8c3 232 ath9k_cmn_update_txpow(ah, sc->curtxpow,
bc7e1be7 233 sc->cur_chan->txpower, &sc->curtxpow);
b74713d0 234
eefa01dd 235 clear_bit(ATH_OP_HW_RESET, &common->op_flags);
9a9c4fbc 236 ath9k_calculate_summary_state(sc, sc->cur_chan);
3989279c 237
fbbcd146 238 if (!sc->cur_chan->offchannel && start) {
8d7e09dd
FF		 239 /* restore per chanctx TSF timer */
240 if (sc->cur_chan->tsf_val) {
241 u32 offset;
242
243 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
244 NULL);
245 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
246 }
247
248
eefa01dd 249 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
196fb860
SM		 250 goto work;
251
196fb860 252 if (ah->opmode == NL80211_IFTYPE_STATION &&
eefa01dd 253 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
196fb860
SM		 254 spin_lock_irqsave(&sc->sc_pm_lock, flags);
255 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
256 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
a6768280
SM		 257 } else {
258 ath9k_set_beacon(sc);
196fb860
SM		 259 }
260 work:
af68abad 261 ath_restart_work(sc);
0453531e 262 ath_txq_schedule_all(sc);
5ee08656
FF		 263 }
264
071aa9a8 265 sc->gtt_cnt = 0;
9a9c4fbc
RM		 266
267 ath9k_hw_set_interrupts(ah);
268 ath9k_hw_enable_interrupts(ah);
269
499afacc 270 if (!ath9k_is_chanctx_enabled())
3ad9c386 271 ieee80211_wake_queues(sc->hw);
0e08b5fb
SM		 272 else
273 ath9k_chanctx_wake_queues(sc);
9adcf440 274
d463af4a
FF		 275 ath9k_p2p_ps_timer(sc);
276
9adcf440
FF		 277 return true;
278}
279
fbbcd146 280int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
9adcf440
FF		 281{
282 struct ath_hw *ah = sc->sc_ah;
283 struct ath_common *common = ath9k_hw_common(ah);
284 struct ath9k_hw_cal_data *caldata = NULL;
285 bool fastcc = true;
9adcf440
FF		 286 int r;
287
288 __ath_cancel_work(sc);
289
4668cce5 290 tasklet_disable(&sc->intr_tq);
9adcf440 291 spin_lock_bh(&sc->sc_pcu_lock);
92460412 292
fbbcd146 293 if (!sc->cur_chan->offchannel) {
9adcf440 294 fastcc = false;
b01459e8 295 caldata = &sc->cur_chan->caldata;
9adcf440
FF		 296 }
297
298 if (!hchan) {
299 fastcc = false;
9adcf440
FF		 300 hchan = ah->curchan;
301 }
302
9ebea382 303 if (!ath_prepare_reset(sc))
9adcf440
FF		 304 fastcc = false;
305
d6067f0e
RM		 306 spin_lock_bh(&sc->chan_lock);
307 sc->cur_chandef = sc->cur_chan->chandef;
308 spin_unlock_bh(&sc->chan_lock);
bff11766 309
d2182b69 310 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
feced201 311 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
9adcf440
FF		 312
313 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
314 if (r) {
315 ath_err(common,
316 "Unable to reset channel, reset status %d\n", r);
f50b1cd3
RS		 317
318 ath9k_hw_enable_interrupts(ah);
319 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
320
9adcf440
FF		 321 goto out;
322 }
323
e82cb03f 324 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
fbbcd146 325 sc->cur_chan->offchannel)
e82cb03f
RM		 326 ath9k_mci_set_txpower(sc, true, false);
327
9adcf440
FF		 328 if (!ath_complete_reset(sc, true))
329 r = -EIO;
330
331out:
6a6733f2 332 spin_unlock_bh(&sc->sc_pcu_lock);
4668cce5
FF		 333 tasklet_enable(&sc->intr_tq);
334
9adcf440
FF		 335 return r;
336}
337
7e1e3864
BG		 338static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
339 struct ieee80211_vif *vif)
ff37e337
S		 340{
341 struct ath_node *an;
ff37e337
S		 342 an = (struct ath_node *)sta->drv_priv;
343
a145daf7 344 an->sc = sc;
7f010c93 345 an->sta = sta;
7e1e3864 346 an->vif = vif;
4bbf4414 347 memset(&an->key_idx, 0, sizeof(an->key_idx));
3d4e20f2 348
dd5ee59b 349 ath_tx_node_init(sc, an);
ff37e337
S		 350}
351
352static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
353{
354 struct ath_node *an = (struct ath_node *)sta->drv_priv;
dd5ee59b 355 ath_tx_node_cleanup(sc, an);
ff37e337
S		 356}
357
55624204 358void ath9k_tasklet(unsigned long data)
ff37e337
S		 359{
360 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 361 struct ath_hw *ah = sc->sc_ah;
c46917bb 362 struct ath_common *common = ath9k_hw_common(ah);
124b979b 363 enum ath_reset_type type;
07c15a3f 364 unsigned long flags;
17d7904d 365 u32 status = sc->intrstatus;
b5c80475 366 u32 rxmask;
ff37e337 367
e3927007
FF		 368 ath9k_ps_wakeup(sc);
369 spin_lock(&sc->sc_pcu_lock);
370
6549a860
SM		 371 if (status & ATH9K_INT_FATAL) {
372 type = RESET_TYPE_FATAL_INT;
124b979b 373 ath9k_queue_reset(sc, type);
c6cc47b1
SM		 374
375 /*
376 * Increment the ref. counter here so that
377 * interrupts are enabled in the reset routine.
378 */
379 atomic_inc(&ah->intr_ref_cnt);
affad456 380 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
e3927007 381 goto out;
063d8be3 382 }
ff37e337 383
6549a860
SM		 384 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
385 (status & ATH9K_INT_BB_WATCHDOG)) {
0c759977
SM		 386 spin_lock(&common->cc_lock);
387 ath_hw_cycle_counters_update(common);
388 ar9003_hw_bb_watchdog_dbg_info(ah);
389 spin_unlock(&common->cc_lock);
390
6549a860
SM		 391 if (ar9003_hw_bb_watchdog_check(ah)) {
392 type = RESET_TYPE_BB_WATCHDOG;
393 ath9k_queue_reset(sc, type);
394
395 /*
396 * Increment the ref. counter here so that
397 * interrupts are enabled in the reset routine.
398 */
399 atomic_inc(&ah->intr_ref_cnt);
affad456 400 ath_dbg(common, RESET,
6549a860
SM		 401 "BB_WATCHDOG: Skipping interrupts\n");
402 goto out;
403 }
404 }
405
071aa9a8
SM		 406 if (status & ATH9K_INT_GTT) {
407 sc->gtt_cnt++;
408
409 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
410 type = RESET_TYPE_TX_GTT;
411 ath9k_queue_reset(sc, type);
412 atomic_inc(&ah->intr_ref_cnt);
affad456 413 ath_dbg(common, RESET,
071aa9a8
SM		 414 "GTT: Skipping interrupts\n");
415 goto out;
416 }
417 }
418
07c15a3f 419 spin_lock_irqsave(&sc->sc_pm_lock, flags);
4105f807
RM		 420 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
421 /*
422 * TSF sync does not look correct; remain awake to sync with
423 * the next Beacon.
424 */
d2182b69 425 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
e8fe7336 426 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
4105f807 427 }
07c15a3f 428 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
4105f807 429
b5c80475
FF		 430 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
431 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
432 ATH9K_INT_RXORN);
433 else
434 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
435
436 if (status & rxmask) {
b5c80475
FF		 437 /* Check for high priority Rx first */
438 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
439 (status & ATH9K_INT_RXHP))
440 ath_rx_tasklet(sc, 0, true);
441
442 ath_rx_tasklet(sc, 0, false);
ff37e337
S		 443 }
444
e5003249 445 if (status & ATH9K_INT_TX) {
071aa9a8
SM		 446 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
447 /*
448 * For EDMA chips, TX completion is enabled for the
449 * beacon queue, so if a beacon has been transmitted
450 * successfully after a GTT interrupt, the GTT counter
451 * gets reset to zero here.
452 */
3b745c7b 453 sc->gtt_cnt = 0;
071aa9a8 454
e5003249 455 ath_tx_edma_tasklet(sc);
071aa9a8 456 } else {
e5003249 457 ath_tx_tasklet(sc);
071aa9a8 458 }
10e23181
FF		 459
460 wake_up(&sc->tx_wait);
e5003249 461 }
063d8be3 462
c67ce339
FF		 463 if (status & ATH9K_INT_GENTIMER)
464 ath_gen_timer_isr(sc->sc_ah);
465
56ca0dba 466 ath9k_btcoex_handle_interrupt(sc, status);
19686ddf 467
ff37e337 468 /* re-enable hardware interrupt */
4df3071e 469 ath9k_hw_enable_interrupts(ah);
c6cc47b1 470out:
52671e43 471 spin_unlock(&sc->sc_pcu_lock);
153e080d 472 ath9k_ps_restore(sc);
ff37e337
S		 473}
474
6baff7f9 475irqreturn_t ath_isr(int irq, void *dev)
ff37e337 476{
063d8be3
S		 477#define SCHED_INTR ( \
478 ATH9K_INT_FATAL | \
a4d86d95 479 ATH9K_INT_BB_WATCHDOG | \
063d8be3
S		 480 ATH9K_INT_RXORN | \
481 ATH9K_INT_RXEOL | \
482 ATH9K_INT_RX | \
b5c80475
FF		 483 ATH9K_INT_RXLP | \
484 ATH9K_INT_RXHP | \
063d8be3
S		 485 ATH9K_INT_TX | \
486 ATH9K_INT_BMISS | \
487 ATH9K_INT_CST | \
071aa9a8 488 ATH9K_INT_GTT | \
ebb8e1d7 489 ATH9K_INT_TSFOOR | \
40dc5392
MSS		 490 ATH9K_INT_GENTIMER | \
491 ATH9K_INT_MCI)
063d8be3 492
ff37e337 493 struct ath_softc *sc = dev;
cbe61d8a 494 struct ath_hw *ah = sc->sc_ah;
eefa01dd 495 struct ath_common *common = ath9k_hw_common(ah);
ff37e337 496 enum ath9k_int status;
78c8a950 497 u32 sync_cause = 0;
ff37e337
S		 498 bool sched = false;
499
063d8be3
S		 500 /*
501 * The hardware is not ready/present, don't
502 * touch anything. Note this can happen early
503 * on if the IRQ is shared.
504 */
eefa01dd 505 if (test_bit(ATH_OP_INVALID, &common->op_flags))
063d8be3 506 return IRQ_NONE;
ff37e337 507
063d8be3
S		 508 /* shared irq, not for us */
509
153e080d 510 if (!ath9k_hw_intrpend(ah))
063d8be3 511 return IRQ_NONE;
063d8be3 512
eefa01dd 513 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) {
f41a9b3b 514 ath9k_hw_kill_interrupts(ah);
b74713d0 515 return IRQ_HANDLED;
f41a9b3b 516 }
b74713d0 517
063d8be3
S		 518 /*
519 * Figure out the reason(s) for the interrupt. Note
520 * that the hal returns a pseudo-ISR that may include
521 * bits we haven't explicitly enabled so we mask the
522 * value to insure we only process bits we requested.
523 */
6a4d05dc
FF		 524 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
525 ath9k_debug_sync_cause(sc, sync_cause);
3069168c 526 status &= ah->imask; /* discard unasked-for bits */
ff37e337 527
063d8be3
S		 528 /*
529 * If there are no status bits set, then this interrupt was not
530 * for me (should have been caught above).
531 */
153e080d 532 if (!status)
063d8be3 533 return IRQ_NONE;
ff37e337 534
063d8be3
S		 535 /* Cache the status */
536 sc->intrstatus = status;
537
538 if (status & SCHED_INTR)
539 sched = true;
540
541 /*
542 * If a FATAL or RXORN interrupt is received, we have to reset the
543 * chip immediately.
544 */
b5c80475
FF		 545 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
546 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S		 547 goto chip_reset;
548
a6bb860b 549 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
0c759977 550 (status & ATH9K_INT_BB_WATCHDOG))
08578b8f 551 goto chip_reset;
e60001e7
SM		 552
553#ifdef CONFIG_ATH9K_WOW
ca90ef44
RM		 554 if (status & ATH9K_INT_BMISS) {
555 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
ca90ef44
RM		 556 atomic_inc(&sc->wow_got_bmiss_intr);
557 atomic_dec(&sc->wow_sleep_proc_intr);
558 }
559 }
560#endif
e60001e7 561
063d8be3
S		 562 if (status & ATH9K_INT_SWBA)
563 tasklet_schedule(&sc->bcon_tasklet);
564
565 if (status & ATH9K_INT_TXURN)
566 ath9k_hw_updatetxtriglevel(ah, true);
567
0682c9b5
RM		 568 if (status & ATH9K_INT_RXEOL) {
569 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
72d874c6 570 ath9k_hw_set_interrupts(ah);
b5c80475
FF		 571 }
572
153e080d
VT		 573 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
574 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR		 575 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
576 goto chip_reset;
063d8be3
S		 577 /* Clear RxAbort bit so that we can
578 * receive frames */
9ecdef4b 579 ath9k_setpower(sc, ATH9K_PM_AWAKE);
07c15a3f 580 spin_lock(&sc->sc_pm_lock);
153e080d 581 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 582 sc->ps_flags |= PS_WAIT_FOR_BEACON;
07c15a3f 583 spin_unlock(&sc->sc_pm_lock);
ff37e337 584 }
063d8be3
S		 585
586chip_reset:
ff37e337 587
817e11de
S		 588 ath_debug_stat_interrupt(sc, status);
589
ff37e337 590 if (sched) {
4df3071e
FF		 591 /* turn off every interrupt */
592 ath9k_hw_disable_interrupts(ah);
ff37e337
S		 593 tasklet_schedule(&sc->intr_tq);
594 }
595
596 return IRQ_HANDLED;
063d8be3
S		 597
598#undef SCHED_INTR
ff37e337
S		 599}
600
ef6b19e4 601int ath_reset(struct ath_softc *sc)
ff37e337 602{
ec30326e 603 int r;
ff37e337 604
783cd01e 605 ath9k_ps_wakeup(sc);
1381559b 606 r = ath_reset_internal(sc, NULL);
783cd01e 607 ath9k_ps_restore(sc);
2ab81d4a 608
ae8d2858 609 return r;
ff37e337
S		 610}
611
124b979b
RM		 612void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
613{
eefa01dd 614 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
124b979b
RM		 615#ifdef CONFIG_ATH9K_DEBUGFS
616 RESET_STAT_INC(sc, type);
617#endif
eefa01dd 618 set_bit(ATH_OP_HW_RESET, &common->op_flags);
124b979b
RM		 619 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
620}
621
236de514
FF		 622void ath_reset_work(struct work_struct *work)
623{
624 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
625
1381559b 626 ath_reset(sc);
236de514
FF		 627}
628
ff37e337
S		 629/**********************/
630/* mac80211 callbacks */
631/**********************/
632
8feceb67 633static int ath9k_start(struct ieee80211_hw *hw)
f078f209 634{
9ac58615 635 struct ath_softc *sc = hw->priv;
af03abec 636 struct ath_hw *ah = sc->sc_ah;
c46917bb 637 struct ath_common *common = ath9k_hw_common(ah);
39305635 638 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
fbbcd146 639 struct ath_chanctx *ctx = sc->cur_chan;
ff37e337 640 struct ath9k_channel *init_channel;
82880a7c 641 int r;
f078f209 642
d2182b69 643 ath_dbg(common, CONFIG,
226afe68
JP		 644 "Starting driver with initial channel: %d MHz\n",
645 curchan->center_freq);
f078f209 646
f62d816f 647 ath9k_ps_wakeup(sc);
141b38b6
S		 648 mutex_lock(&sc->mutex);
649
fbbcd146 650 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
bff11766 651 sc->cur_chandef = hw->conf.chandef;
ff37e337
S		 652
653 /* Reset SERDES registers */
84c87dc8 654 ath9k_hw_configpcipowersave(ah, false);
ff37e337
S		 655
656 /*
657 * The basic interface to setting the hardware in a good
658 * state is ``reset''. On return the hardware is known to
659 * be powered up and with interrupts disabled. This must
660 * be followed by initialization of the appropriate bits
661 * and then setup of the interrupt mask.
662 */
4bdd1e97 663 spin_lock_bh(&sc->sc_pcu_lock);
c0c11741
FF		 664
665 atomic_set(&ah->intr_ref_cnt, -1);
666
20bd2a09 667 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 668 if (r) {
3800276a
JP		 669 ath_err(common,
670 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
671 r, curchan->center_freq);
ceb26a60 672 ah->reset_power_on = false;
ff37e337 673 }
ff37e337 674
ff37e337 675 /* Setup our intr mask. */
b5c80475
FF		 676 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
677 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
678 ATH9K_INT_GLOBAL;
679
680 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f 681 ah->imask |= ATH9K_INT_RXHP |
a6bb860b 682 ATH9K_INT_RXLP;
b5c80475
FF		 683 else
684 ah->imask |= ATH9K_INT_RX;
ff37e337 685
a6bb860b
SM		 686 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
687 ah->imask |= ATH9K_INT_BB_WATCHDOG;
688
071aa9a8
SM		 689 /*
690 * Enable GTT interrupts only for AR9003/AR9004 chips
691 * for now.
692 */
693 if (AR_SREV_9300_20_OR_LATER(ah))
694 ah->imask |= ATH9K_INT_GTT;
ff37e337 695
af03abec 696 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 697 ah->imask |= ATH9K_INT_CST;
ff37e337 698
e270e776 699 ath_mci_enable(sc);
40dc5392 700
eefa01dd 701 clear_bit(ATH_OP_INVALID, &common->op_flags);
5f841b41 702 sc->sc_ah->is_monitoring = false;
ff37e337 703
ceb26a60
FF		 704 if (!ath_complete_reset(sc, false))
705 ah->reset_power_on = false;
ff37e337 706
c0c11741
FF		 707 if (ah->led_pin >= 0) {
708 ath9k_hw_cfg_output(ah, ah->led_pin,
709 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
710 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
711 }
712
713 /*
714 * Reset key cache to sane defaults (all entries cleared) instead of
715 * semi-random values after suspend/resume.
716 */
717 ath9k_cmn_init_crypto(sc->sc_ah);
718
a35051ce
FF		 719 ath9k_hw_reset_tsf(ah);
720
9adcf440 721 spin_unlock_bh(&sc->sc_pcu_lock);
164ace38 722
141b38b6
S		 723 mutex_unlock(&sc->mutex);
724
f62d816f
FF		 725 ath9k_ps_restore(sc);
726
ceb26a60 727 return 0;
f078f209
LR		 728}
729
36323f81
TH		 730static void ath9k_tx(struct ieee80211_hw *hw,
731 struct ieee80211_tx_control *control,
732 struct sk_buff *skb)
f078f209 733{
9ac58615 734 struct ath_softc *sc = hw->priv;
c46917bb 735 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 736 struct ath_tx_control txctl;
1bc14880 737 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
07c15a3f 738 unsigned long flags;
528f0c6b 739
96148326 740 if (sc->ps_enabled) {
dc8c4585
JM		 741 /*
742 * mac80211 does not set PM field for normal data frames, so we
743 * need to update that based on the current PS mode.
744 */
745 if (ieee80211_is_data(hdr->frame_control) &&
746 !ieee80211_is_nullfunc(hdr->frame_control) &&
747 !ieee80211_has_pm(hdr->frame_control)) {
d2182b69 748 ath_dbg(common, PS,
226afe68 749 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM		 750 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
751 }
752 }
753
ad128860 754 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
9a23f9ca
JM		 755 /*
756 * We are using PS-Poll and mac80211 can request TX while in
757 * power save mode. Need to wake up hardware for the TX to be
758 * completed and if needed, also for RX of buffered frames.
759 */
9a23f9ca 760 ath9k_ps_wakeup(sc);
07c15a3f 761 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fdf76622
VT		 762 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
763 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 764 if (ieee80211_is_pspoll(hdr->frame_control)) {
d2182b69 765 ath_dbg(common, PS,
226afe68 766 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 767 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 768 } else {
d2182b69 769 ath_dbg(common, PS, "Wake up to complete TX\n");
1b04b930 770 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM		 771 }
772 /*
773 * The actual restore operation will happen only after
ad128860 774 * the ps_flags bit is cleared. We are just dropping
9a23f9ca
JM		 775 * the ps_usecount here.
776 */
07c15a3f 777 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
9a23f9ca
JM		 778 ath9k_ps_restore(sc);
779 }
780
ad128860
SM		 781 /*
782 * Cannot tx while the hardware is in full sleep, it first needs a full
783 * chip reset to recover from that
784 */
785 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
786 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
787 goto exit;
788 }
789
528f0c6b 790 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 791 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
36323f81 792 txctl.sta = control->sta;
528f0c6b 793
d2182b69 794 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 795
c52f33d0 796 if (ath_tx_start(hw, skb, &txctl) != 0) {
d2182b69 797 ath_dbg(common, XMIT, "TX failed\n");
a5a0bca1 798 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
528f0c6b 799 goto exit;
8feceb67
VT		 800 }
801
7bb45683 802 return;
528f0c6b 803exit:
249ee722 804 ieee80211_free_txskb(hw, skb);
f078f209
LR		 805}
806
8feceb67 807static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 808{
9ac58615 809 struct ath_softc *sc = hw->priv;
af03abec 810 struct ath_hw *ah = sc->sc_ah;
c46917bb 811 struct ath_common *common = ath9k_hw_common(ah);
c0c11741 812 bool prev_idle;
f078f209 813
ea22df29
SM		 814 ath9k_deinit_channel_context(sc);
815
4c483817
S		 816 mutex_lock(&sc->mutex);
817
9adcf440 818 ath_cancel_work(sc);
c94dbff7 819
eefa01dd 820 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
d2182b69 821 ath_dbg(common, ANY, "Device not present\n");
4c483817 822 mutex_unlock(&sc->mutex);
9c84b797
S		 823 return;
824 }
8feceb67 825
3867cf6a
S		 826 /* Ensure HW is awake when we try to shut it down. */
827 ath9k_ps_wakeup(sc);
828
6a6733f2
LR		 829 spin_lock_bh(&sc->sc_pcu_lock);
830
203043f5
SG		 831 /* prevent tasklets to enable interrupts once we disable them */
832 ah->imask &= ~ATH9K_INT_GLOBAL;
833
ff37e337
S		 834 /* make sure h/w will not generate any interrupt
835 * before setting the invalid flag. */
4df3071e 836 ath9k_hw_disable_interrupts(ah);
ff37e337 837
c0c11741
FF		 838 spin_unlock_bh(&sc->sc_pcu_lock);
839
840 /* we can now sync irq and kill any running tasklets, since we already
841 * disabled interrupts and not holding a spin lock */
842 synchronize_irq(sc->irq);
843 tasklet_kill(&sc->intr_tq);
844 tasklet_kill(&sc->bcon_tasklet);
845
846 prev_idle = sc->ps_idle;
847 sc->ps_idle = true;
848
849 spin_lock_bh(&sc->sc_pcu_lock);
850
851 if (ah->led_pin >= 0) {
852 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
853 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
854 }
855
9ebea382 856 ath_prepare_reset(sc);
ff37e337 857
0d95521e
FF		 858 if (sc->rx.frag) {
859 dev_kfree_skb_any(sc->rx.frag);
860 sc->rx.frag = NULL;
861 }
862
c0c11741 863 if (!ah->curchan)
fbbcd146
FF		 864 ah->curchan = ath9k_cmn_get_channel(hw, ah,
865 &sc->cur_chan->chandef);
6a6733f2 866
c0c11741
FF		 867 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
868 ath9k_hw_phy_disable(ah);
6a6733f2 869
c0c11741 870 ath9k_hw_configpcipowersave(ah, true);
203043f5 871
c0c11741 872 spin_unlock_bh(&sc->sc_pcu_lock);
3867cf6a 873
c0c11741 874 ath9k_ps_restore(sc);
ff37e337 875
eefa01dd 876 set_bit(ATH_OP_INVALID, &common->op_flags);
c0c11741 877 sc->ps_idle = prev_idle;
500c064d 878
141b38b6
S		 879 mutex_unlock(&sc->mutex);
880
d2182b69 881 ath_dbg(common, CONFIG, "Driver halt\n");
f078f209
LR		 882}
883
c648ecb0 884static bool ath9k_uses_beacons(int type)
4801416c
BG		 885{
886 switch (type) {
887 case NL80211_IFTYPE_AP:
888 case NL80211_IFTYPE_ADHOC:
889 case NL80211_IFTYPE_MESH_POINT:
890 return true;
891 default:
892 return false;
893 }
894}
895
4801416c
BG		 896static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
897{
898 struct ath9k_vif_iter_data *iter_data = data;
899 int i;
900
ab11bb28 901 if (iter_data->has_hw_macaddr) {
4801416c
BG		 902 for (i = 0; i < ETH_ALEN; i++)
903 iter_data->mask[i] &=
904 ~(iter_data->hw_macaddr[i] ^ mac[i]);
ab11bb28
FF		 905 } else {
906 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
907 iter_data->has_hw_macaddr = true;
908 }
141b38b6 909
9a9c4fbc
RM		 910 if (!vif->bss_conf.use_short_slot)
911 iter_data->slottime = ATH9K_SLOT_TIME_20;
912
1ed32e4f 913 switch (vif->type) {
4801416c
BG		 914 case NL80211_IFTYPE_AP:
915 iter_data->naps++;
9a9c4fbc
RM		 916 if (vif->bss_conf.enable_beacon)
917 iter_data->beacons = true;
f078f209 918 break;
4801416c
BG		 919 case NL80211_IFTYPE_STATION:
920 iter_data->nstations++;
9a9c4fbc
RM		 921 if (vif->bss_conf.assoc && !iter_data->primary_sta)
922 iter_data->primary_sta = vif;
e51f3eff 923 break;
05c914fe 924 case NL80211_IFTYPE_ADHOC:
4801416c 925 iter_data->nadhocs++;
9a9c4fbc
RM		 926 if (vif->bss_conf.enable_beacon)
927 iter_data->beacons = true;
4801416c 928 break;
9cb5412b 929 case NL80211_IFTYPE_MESH_POINT:
4801416c 930 iter_data->nmeshes++;
9a9c4fbc
RM		 931 if (vif->bss_conf.enable_beacon)
932 iter_data->beacons = true;
4801416c
BG		 933 break;
934 case NL80211_IFTYPE_WDS:
935 iter_data->nwds++;
f078f209
LR		 936 break;
937 default:
4801416c 938 break;
f078f209 939 }
4801416c 940}
f078f209 941
4801416c 942/* Called with sc->mutex held. */
9a9c4fbc
RM		 943void ath9k_calculate_iter_data(struct ath_softc *sc,
944 struct ath_chanctx *ctx,
4801416c
BG		 945 struct ath9k_vif_iter_data *iter_data)
946{
9a9c4fbc 947 struct ath_vif *avp;
8feceb67 948
4801416c 949 /*
657eb17d
MV		 950 * Pick the MAC address of the first interface as the new hardware
951 * MAC address. The hardware will use it together with the BSSID mask
952 * when matching addresses.
4801416c
BG		 953 */
954 memset(iter_data, 0, sizeof(*iter_data));
4801416c 955 memset(&iter_data->mask, 0xff, ETH_ALEN);
9a9c4fbc
RM		 956 iter_data->slottime = ATH9K_SLOT_TIME_9;
957
958 list_for_each_entry(avp, &ctx->vifs, list)
959 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
960
961 if (ctx == &sc->offchannel.chan) {
962 struct ieee80211_vif *vif;
963
964 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
965 vif = sc->offchannel.scan_vif;
966 else
967 vif = sc->offchannel.roc_vif;
968
969 if (vif)
970 ath9k_vif_iter(iter_data, vif->addr, vif);
971 iter_data->beacons = false;
972 }
973}
974
975static void ath9k_set_assoc_state(struct ath_softc *sc,
976 struct ieee80211_vif *vif, bool changed)
977{
978 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
979 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
980 unsigned long flags;
981
982 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
983 /* Set the AID, BSSID and do beacon-sync only when
984 * the HW opmode is STATION.
985 *
986 * But the primary bit is set above in any case.
987 */
988 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
989 return;
990
991 ether_addr_copy(common->curbssid, bss_conf->bssid);
992 common->curaid = bss_conf->aid;
993 ath9k_hw_write_associd(sc->sc_ah);
994
995 if (changed) {
996 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
997 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
5640b08e 998
9a9c4fbc
RM		 999 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1000 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1001 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1002 }
4801416c 1003
9a9c4fbc
RM		 1004 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1005 ath9k_mci_update_wlan_channels(sc, false);
ab11bb28 1006
9a9c4fbc
RM		 1007 ath_dbg(common, CONFIG,
1008 "Primary Station interface: %pM, BSSID: %pM\n",
1009 vif->addr, common->curbssid);
4801416c 1010}
8ca21f01 1011
4801416c 1012/* Called with sc->mutex held. */
9a9c4fbc
RM		 1013void ath9k_calculate_summary_state(struct ath_softc *sc,
1014 struct ath_chanctx *ctx)
4801416c 1015{
4801416c
BG		 1016 struct ath_hw *ah = sc->sc_ah;
1017 struct ath_common *common = ath9k_hw_common(ah);
1018 struct ath9k_vif_iter_data iter_data;
8ca21f01 1019
9a9c4fbc
RM		 1020 ath_chanctx_check_active(sc, ctx);
1021
1022 if (ctx != sc->cur_chan)
1023 return;
1024
1025 ath9k_ps_wakeup(sc);
1026 ath9k_calculate_iter_data(sc, ctx, &iter_data);
1027
1028 if (iter_data.has_hw_macaddr)
1029 ether_addr_copy(common->macaddr, iter_data.hw_macaddr);
2c3db3d5 1030
4801416c
BG		 1031 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1032 ath_hw_setbssidmask(common);
1033
4801416c 1034 if (iter_data.naps > 0) {
60ca9f87 1035 ath9k_hw_set_tsfadjust(ah, true);
4801416c
BG		 1036 ah->opmode = NL80211_IFTYPE_AP;
1037 } else {
60ca9f87 1038 ath9k_hw_set_tsfadjust(ah, false);
5640b08e 1039
fd5999cf
JC		 1040 if (iter_data.nmeshes)
1041 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1042 else if (iter_data.nwds)
4801416c
BG		 1043 ah->opmode = NL80211_IFTYPE_AP;
1044 else if (iter_data.nadhocs)
1045 ah->opmode = NL80211_IFTYPE_ADHOC;
1046 else
1047 ah->opmode = NL80211_IFTYPE_STATION;
1048 }
5640b08e 1049
df35d29e
SM		 1050 ath9k_hw_setopmode(ah);
1051
748299f2 1052 ctx->switch_after_beacon = false;
198823fd 1053 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
3069168c 1054 ah->imask |= ATH9K_INT_TSFOOR;
748299f2 1055 else {
4801416c 1056 ah->imask &= ~ATH9K_INT_TSFOOR;
748299f2
FF		 1057 if (iter_data.naps == 1 && iter_data.beacons)
1058 ctx->switch_after_beacon = true;
1059 }
4af9cf4f 1060
9a9c4fbc
RM		 1061 ah->imask &= ~ATH9K_INT_SWBA;
1062 if (ah->opmode == NL80211_IFTYPE_STATION) {
1063 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1064
1065 iter_data.beacons = true;
1066 if (iter_data.primary_sta) {
1067 ath9k_set_assoc_state(sc, iter_data.primary_sta,
1068 changed);
1069 if (!ctx->primary_sta ||
1070 !ctx->primary_sta->bss_conf.assoc)
1071 ctx->primary_sta = iter_data.primary_sta;
1072 } else {
1073 ctx->primary_sta = NULL;
1074 memset(common->curbssid, 0, ETH_ALEN);
1075 common->curaid = 0;
1076 ath9k_hw_write_associd(sc->sc_ah);
1077 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1078 ath9k_mci_update_wlan_channels(sc, true);
1079 }
1080 } else if (iter_data.beacons) {
1081 ah->imask |= ATH9K_INT_SWBA;
1082 }
72d874c6 1083 ath9k_hw_set_interrupts(ah);
6dcc3444 1084
9a9c4fbc
RM		 1085 if (iter_data.beacons)
1086 set_bit(ATH_OP_BEACONS, &common->op_flags);
1087 else
1088 clear_bit(ATH_OP_BEACONS, &common->op_flags);
1089
1090 if (ah->slottime != iter_data.slottime) {
1091 ah->slottime = iter_data.slottime;
1092 ath9k_hw_init_global_settings(ah);
6dcc3444 1093 }
9a9c4fbc
RM		 1094
1095 if (iter_data.primary_sta)
1096 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1097 else
1098 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1099
1100 ctx->primary_sta = iter_data.primary_sta;
1101
1102 ath9k_ps_restore(sc);
4801416c 1103}
6f255425 1104
4801416c
BG		 1105static int ath9k_add_interface(struct ieee80211_hw *hw,
1106 struct ieee80211_vif *vif)
6b3b991d 1107{
9ac58615 1108 struct ath_softc *sc = hw->priv;
4801416c
BG		 1109 struct ath_hw *ah = sc->sc_ah;
1110 struct ath_common *common = ath9k_hw_common(ah);
f89d1bc4
FF		 1111 struct ath_vif *avp = (void *)vif->drv_priv;
1112 struct ath_node *an = &avp->mcast_node;
3ad9c386 1113 int i;
6b3b991d 1114
4801416c 1115 mutex_lock(&sc->mutex);
6b3b991d 1116
89f927af
LR		 1117 if (config_enabled(CONFIG_ATH9K_TX99)) {
1118 if (sc->nvifs >= 1) {
1119 mutex_unlock(&sc->mutex);
1120 return -EOPNOTSUPP;
1121 }
1122 sc->tx99_vif = vif;
1123 }
1124
d2182b69 1125 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
4801416c
BG		 1126 sc->nvifs++;
1127
130ef6e9
SM		 1128 if (ath9k_uses_beacons(vif->type))
1129 ath9k_beacon_assign_slot(sc, vif);
1130
d463af4a 1131 avp->vif = vif;
499afacc 1132 if (!ath9k_is_chanctx_enabled()) {
39305635 1133 avp->chanctx = sc->cur_chan;
9a9c4fbc
RM		 1134 list_add_tail(&avp->list, &avp->chanctx->vifs);
1135 }
3ad9c386
RM		 1136 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1137 vif->hw_queue[i] = i;
1138 if (vif->type == NL80211_IFTYPE_AP)
1139 vif->cab_queue = hw->queues - 2;
1140 else
1141 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
0453531e 1142
f89d1bc4
FF		 1143 an->sc = sc;
1144 an->sta = NULL;
1145 an->vif = vif;
1146 an->no_ps_filter = true;
1147 ath_tx_node_init(sc, an);
1148
4801416c 1149 mutex_unlock(&sc->mutex);
327967cb 1150 return 0;
6b3b991d
RM		 1151}
1152
1153static int ath9k_change_interface(struct ieee80211_hw *hw,
1154 struct ieee80211_vif *vif,
1155 enum nl80211_iftype new_type,
1156 bool p2p)
1157{
9ac58615 1158 struct ath_softc *sc = hw->priv;
6b3b991d 1159 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
c083ce99 1160 struct ath_vif *avp = (void *)vif->drv_priv;
3ad9c386 1161 int i;
6b3b991d 1162
6b3b991d 1163 mutex_lock(&sc->mutex);
4801416c 1164
89f927af
LR		 1165 if (config_enabled(CONFIG_ATH9K_TX99)) {
1166 mutex_unlock(&sc->mutex);
1167 return -EOPNOTSUPP;
1168 }
1169
1170 ath_dbg(common, CONFIG, "Change Interface\n");
1171
4801416c 1172 if (ath9k_uses_beacons(vif->type))
130ef6e9 1173 ath9k_beacon_remove_slot(sc, vif);
4801416c 1174
6b3b991d
RM		 1175 vif->type = new_type;
1176 vif->p2p = p2p;
1177
130ef6e9
SM		 1178 if (ath9k_uses_beacons(vif->type))
1179 ath9k_beacon_assign_slot(sc, vif);
9a9c4fbc 1180
3ad9c386
RM		 1181 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1182 vif->hw_queue[i] = i;
1183
1184 if (vif->type == NL80211_IFTYPE_AP)
1185 vif->cab_queue = hw->queues - 2;
1186 else
1187 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1188
9a9c4fbc 1189 ath9k_calculate_summary_state(sc, avp->chanctx);
130ef6e9 1190
6b3b991d 1191 mutex_unlock(&sc->mutex);
327967cb 1192 return 0;
6b3b991d
RM		 1193}
1194
8feceb67 1195static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1196 struct ieee80211_vif *vif)
f078f209 1197{
9ac58615 1198 struct ath_softc *sc = hw->priv;
c46917bb 1199 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f89d1bc4 1200 struct ath_vif *avp = (void *)vif->drv_priv;
f078f209 1201
d2182b69 1202 ath_dbg(common, CONFIG, "Detach Interface\n");
f078f209 1203
141b38b6
S		 1204 mutex_lock(&sc->mutex);
1205
c7dd40c9 1206 ath9k_p2p_remove_vif(sc, vif);
d463af4a 1207
4801416c 1208 sc->nvifs--;
89f927af 1209 sc->tx99_vif = NULL;
499afacc 1210 if (!ath9k_is_chanctx_enabled())
9a9c4fbc 1211 list_del(&avp->list);
580f0b8a 1212
4801416c 1213 if (ath9k_uses_beacons(vif->type))
130ef6e9 1214 ath9k_beacon_remove_slot(sc, vif);
2c3db3d5 1215
f89d1bc4
FF		 1216 ath_tx_node_cleanup(sc, &avp->mcast_node);
1217
141b38b6 1218 mutex_unlock(&sc->mutex);
f078f209
LR		 1219}
1220
fbab7390 1221static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1222{
3069168c 1223 struct ath_hw *ah = sc->sc_ah;
ad128860 1224 struct ath_common *common = ath9k_hw_common(ah);
3069168c 1225
89f927af
LR		 1226 if (config_enabled(CONFIG_ATH9K_TX99))
1227 return;
1228
3f7c5c10 1229 sc->ps_enabled = true;
3069168c
PR		 1230 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1231 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1232 ah->imask |= ATH9K_INT_TIM_TIMER;
72d874c6 1233 ath9k_hw_set_interrupts(ah);
3f7c5c10 1234 }
fdf76622 1235 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1236 }
ad128860 1237 ath_dbg(common, PS, "PowerSave enabled\n");
3f7c5c10
SB		 1238}
1239
845d708e
SB		 1240static void ath9k_disable_ps(struct ath_softc *sc)
1241{
1242 struct ath_hw *ah = sc->sc_ah;
ad128860 1243 struct ath_common *common = ath9k_hw_common(ah);
845d708e 1244
89f927af
LR		 1245 if (config_enabled(CONFIG_ATH9K_TX99))
1246 return;
1247
845d708e
SB		 1248 sc->ps_enabled = false;
1249 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1250 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1251 ath9k_hw_setrxabort(ah, 0);
1252 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1253 PS_WAIT_FOR_CAB |
1254 PS_WAIT_FOR_PSPOLL_DATA |
1255 PS_WAIT_FOR_TX_ACK);
1256 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1257 ah->imask &= ~ATH9K_INT_TIM_TIMER;
72d874c6 1258 ath9k_hw_set_interrupts(ah);
845d708e
SB		 1259 }
1260 }
ad128860 1261 ath_dbg(common, PS, "PowerSave disabled\n");
845d708e
SB		 1262}
1263
e93d083f
SW		 1264void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw)
1265{
1266 struct ath_softc *sc = hw->priv;
1267 struct ath_hw *ah = sc->sc_ah;
1268 struct ath_common *common = ath9k_hw_common(ah);
1269 u32 rxfilter;
1270
89f927af
LR		 1271 if (config_enabled(CONFIG_ATH9K_TX99))
1272 return;
1273
e93d083f
SW		 1274 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
1275 ath_err(common, "spectrum analyzer not implemented on this hardware\n");
1276 return;
1277 }
1278
1279 ath9k_ps_wakeup(sc);
1280 rxfilter = ath9k_hw_getrxfilter(ah);
1281 ath9k_hw_setrxfilter(ah, rxfilter |
1282 ATH9K_RX_FILTER_PHYRADAR |
1283 ATH9K_RX_FILTER_PHYERR);
1284
1285 /* TODO: usually this should not be neccesary, but for some reason
1286 * (or in some mode?) the trigger must be called after the
1287 * configuration, otherwise the register will have its values reset
1288 * (on my ar9220 to value 0x01002310)
1289 */
1290 ath9k_spectral_scan_config(hw, sc->spectral_mode);
1291 ath9k_hw_ops(ah)->spectral_scan_trigger(ah);
1292 ath9k_ps_restore(sc);
1293}
1294
1295int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
1296 enum spectral_mode spectral_mode)
1297{
1298 struct ath_softc *sc = hw->priv;
1299 struct ath_hw *ah = sc->sc_ah;
1300 struct ath_common *common = ath9k_hw_common(ah);
e93d083f
SW		 1301
1302 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
1303 ath_err(common, "spectrum analyzer not implemented on this hardware\n");
1304 return -1;
1305 }
1306
e93d083f
SW		 1307 switch (spectral_mode) {
1308 case SPECTRAL_DISABLED:
04ccd4a1 1309 sc->spec_config.enabled = 0;
e93d083f
SW		 1310 break;
1311 case SPECTRAL_BACKGROUND:
1312 /* send endless samples.
1313 * TODO: is this really useful for "background"?
1314 */
04ccd4a1
SW		 1315 sc->spec_config.endless = 1;
1316 sc->spec_config.enabled = 1;
e93d083f
SW		 1317 break;
1318 case SPECTRAL_CHANSCAN:
e93d083f 1319 case SPECTRAL_MANUAL:
04ccd4a1
SW		 1320 sc->spec_config.endless = 0;
1321 sc->spec_config.enabled = 1;
e93d083f
SW		 1322 break;
1323 default:
1324 return -1;
1325 }
1326
1327 ath9k_ps_wakeup(sc);
04ccd4a1 1328 ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config);
e93d083f
SW		 1329 ath9k_ps_restore(sc);
1330
1331 sc->spectral_mode = spectral_mode;
1332
1333 return 0;
1334}
1335
e8975581 1336static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1337{
9ac58615 1338 struct ath_softc *sc = hw->priv;
3430098a
FF		 1339 struct ath_hw *ah = sc->sc_ah;
1340 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1341 struct ieee80211_conf *conf = &hw->conf;
fbbcd146 1342 struct ath_chanctx *ctx = sc->cur_chan;
f078f209 1343
c0c11741 1344 ath9k_ps_wakeup(sc);
aa33de09 1345 mutex_lock(&sc->mutex);
141b38b6 1346
daa1b6ee 1347 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4 1348 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
b73f3e78 1349 if (sc->ps_idle) {
daa1b6ee 1350 ath_cancel_work(sc);
b73f3e78
RM		 1351 ath9k_stop_btcoex(sc);
1352 } else {
1353 ath9k_start_btcoex(sc);
75600abf
FF		 1354 /*
1355 * The chip needs a reset to properly wake up from
1356 * full sleep
1357 */
39305635 1358 ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
b73f3e78 1359 }
daa1b6ee 1360 }
64839170 1361
e7824a50
LR		 1362 /*
1363 * We just prepare to enable PS. We have to wait until our AP has
1364 * ACK'd our null data frame to disable RX otherwise we'll ignore
1365 * those ACKs and end up retransmitting the same null data frames.
1366 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1367 */
3cbb5dd7 1368 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR		 1369 unsigned long flags;
1370 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB		 1371 if (conf->flags & IEEE80211_CONF_PS)
1372 ath9k_enable_ps(sc);
845d708e
SB		 1373 else
1374 ath9k_disable_ps(sc);
8ab2cd09 1375 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN		 1376 }
1377
199afd9d
S		 1378 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1379 if (conf->flags & IEEE80211_CONF_MONITOR) {
d2182b69 1380 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
5f841b41
RM		 1381 sc->sc_ah->is_monitoring = true;
1382 } else {
d2182b69 1383 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
5f841b41 1384 sc->sc_ah->is_monitoring = false;
199afd9d
S		 1385 }
1386 }
1387
499afacc 1388 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
fbbcd146 1389 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
bff11766 1390 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
094d05dc 1391 }
f078f209 1392
c9f6a656 1393 if (changed & IEEE80211_CONF_CHANGE_POWER) {
d2182b69 1394 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
bc7e1be7 1395 sc->cur_chan->txpower = 2 * conf->power_level;
5048e8c3 1396 ath9k_cmn_update_txpow(ah, sc->curtxpow,
bc7e1be7 1397 sc->cur_chan->txpower, &sc->curtxpow);
64839170
LR		 1398 }
1399
aa33de09 1400 mutex_unlock(&sc->mutex);
c0c11741 1401 ath9k_ps_restore(sc);
141b38b6 1402
f078f209
LR		 1403 return 0;
1404}
1405
8feceb67
VT		 1406#define SUPPORTED_FILTERS \
1407 (FIF_PROMISC_IN_BSS | \
1408 FIF_ALLMULTI | \
1409 FIF_CONTROL | \
af6a3fc7 1410 FIF_PSPOLL | \
8feceb67
VT		 1411 FIF_OTHER_BSS | \
1412 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1413 FIF_PROBE_REQ | \
8feceb67 1414 FIF_FCSFAIL)
c83be688 1415
8feceb67
VT		 1416/* FIXME: sc->sc_full_reset ? */
1417static void ath9k_configure_filter(struct ieee80211_hw *hw,
1418 unsigned int changed_flags,
1419 unsigned int *total_flags,
3ac64bee 1420 u64 multicast)
8feceb67 1421{
9ac58615 1422 struct ath_softc *sc = hw->priv;
8feceb67 1423 u32 rfilt;
f078f209 1424
8feceb67
VT		 1425 changed_flags &= SUPPORTED_FILTERS;
1426 *total_flags &= SUPPORTED_FILTERS;
f078f209 1427
b77f483f 1428 sc->rx.rxfilter = *total_flags;
aa68aeaa 1429 ath9k_ps_wakeup(sc);
8feceb67
VT		 1430 rfilt = ath_calcrxfilter(sc);
1431 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1432 ath9k_ps_restore(sc);
f078f209 1433
d2182b69
JP		 1434 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1435 rfilt);
8feceb67 1436}
f078f209 1437
4ca77860
JB		 1438static int ath9k_sta_add(struct ieee80211_hw *hw,
1439 struct ieee80211_vif *vif,
1440 struct ieee80211_sta *sta)
8feceb67 1441{
9ac58615 1442 struct ath_softc *sc = hw->priv;
93ae2dd2
FF		 1443 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1444 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1445 struct ieee80211_key_conf ps_key = { };
4ef69d03 1446 int key;
f078f209 1447
7e1e3864 1448 ath_node_attach(sc, sta, vif);
f59a59fe
FF		 1449
1450 if (vif->type != NL80211_IFTYPE_AP &&
1451 vif->type != NL80211_IFTYPE_AP_VLAN)
1452 return 0;
1453
4ef69d03 1454 key = ath_key_config(common, vif, sta, &ps_key);
4bbf4414 1455 if (key > 0) {
4ef69d03 1456 an->ps_key = key;
4bbf4414
RM		 1457 an->key_idx[0] = key;
1458 }
4ca77860
JB		 1459
1460 return 0;
1461}
1462
93ae2dd2
FF		 1463static void ath9k_del_ps_key(struct ath_softc *sc,
1464 struct ieee80211_vif *vif,
1465 struct ieee80211_sta *sta)
1466{
1467 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1468 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1469 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1470
1471 if (!an->ps_key)
1472 return;
1473
1474 ath_key_delete(common, &ps_key);
4ef69d03 1475 an->ps_key = 0;
4bbf4414 1476 an->key_idx[0] = 0;
93ae2dd2
FF		 1477}
1478
4ca77860
JB		 1479static int ath9k_sta_remove(struct ieee80211_hw *hw,
1480 struct ieee80211_vif *vif,
1481 struct ieee80211_sta *sta)
1482{
9ac58615 1483 struct ath_softc *sc = hw->priv;
4ca77860 1484
93ae2dd2 1485 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB		 1486 ath_node_detach(sc, sta);
1487
1488 return 0;
f078f209
LR		 1489}
1490
4bbf4414
RM		 1491static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1492 struct ath_node *an,
1493 bool set)
1494{
1495 int i;
1496
1497 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1498 if (!an->key_idx[i])
1499 continue;
1500 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1501 }
1502}
1503
5519541d
FF		 1504static void ath9k_sta_notify(struct ieee80211_hw *hw,
1505 struct ieee80211_vif *vif,
1506 enum sta_notify_cmd cmd,
1507 struct ieee80211_sta *sta)
1508{
1509 struct ath_softc *sc = hw->priv;
1510 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1511
1512 switch (cmd) {
1513 case STA_NOTIFY_SLEEP:
1514 an->sleeping = true;
042ec453 1515 ath_tx_aggr_sleep(sta, sc, an);
4bbf4414 1516 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
5519541d
FF		 1517 break;
1518 case STA_NOTIFY_AWAKE:
4bbf4414 1519 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
5519541d
FF		 1520 an->sleeping = false;
1521 ath_tx_aggr_wakeup(sc, an);
1522 break;
1523 }
1524}
1525
8a3a3c85
EP		 1526static int ath9k_conf_tx(struct ieee80211_hw *hw,
1527 struct ieee80211_vif *vif, u16 queue,
8feceb67 1528 const struct ieee80211_tx_queue_params *params)
f078f209 1529{
9ac58615 1530 struct ath_softc *sc = hw->priv;
c46917bb 1531 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1532 struct ath_txq *txq;
8feceb67 1533 struct ath9k_tx_queue_info qi;
066dae93 1534 int ret = 0;
f078f209 1535
bea843c7 1536 if (queue >= IEEE80211_NUM_ACS)
8feceb67 1537 return 0;
f078f209 1538
066dae93
FF		 1539 txq = sc->tx.txq_map[queue];
1540
96f372c9 1541 ath9k_ps_wakeup(sc);
141b38b6
S		 1542 mutex_lock(&sc->mutex);
1543
1ffb0610
S		 1544 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1545
8feceb67
VT		 1546 qi.tqi_aifs = params->aifs;
1547 qi.tqi_cwmin = params->cw_min;
1548 qi.tqi_cwmax = params->cw_max;
531bd079 1549 qi.tqi_burstTime = params->txop * 32;
f078f209 1550
d2182b69 1551 ath_dbg(common, CONFIG,
226afe68
JP		 1552 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1553 queue, txq->axq_qnum, params->aifs, params->cw_min,
1554 params->cw_max, params->txop);
f078f209 1555
aa5955c3 1556 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
066dae93 1557 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1558 if (ret)
3800276a 1559 ath_err(common, "TXQ Update failed\n");
f078f209 1560
141b38b6 1561 mutex_unlock(&sc->mutex);
96f372c9 1562 ath9k_ps_restore(sc);
141b38b6 1563
8feceb67
VT		 1564 return ret;
1565}
f078f209 1566
8feceb67
VT		 1567static int ath9k_set_key(struct ieee80211_hw *hw,
1568 enum set_key_cmd cmd,
dc822b5d
JB		 1569 struct ieee80211_vif *vif,
1570 struct ieee80211_sta *sta,
8feceb67
VT		 1571 struct ieee80211_key_conf *key)
1572{
9ac58615 1573 struct ath_softc *sc = hw->priv;
c46917bb 1574 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
4bbf4414
RM		 1575 struct ath_node *an = NULL;
1576 int ret = 0, i;
f078f209 1577
3e6109c5 1578 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM		 1579 return -ENOSPC;
1580
5bd5e9a6
CYY		 1581 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1582 vif->type == NL80211_IFTYPE_MESH_POINT) &&
cfdc9a8b
JM		 1583 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1584 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1585 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1586 /*
1587 * For now, disable hw crypto for the RSN IBSS group keys. This
1588 * could be optimized in the future to use a modified key cache
1589 * design to support per-STA RX GTK, but until that gets
1590 * implemented, use of software crypto for group addressed
1591 * frames is a acceptable to allow RSN IBSS to be used.
1592 */
1593 return -EOPNOTSUPP;
1594 }
1595
141b38b6 1596 mutex_lock(&sc->mutex);
3cbb5dd7 1597 ath9k_ps_wakeup(sc);
4bbf4414
RM		 1598 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1599 if (sta)
1600 an = (struct ath_node *)sta->drv_priv;
f078f209 1601
8feceb67
VT		 1602 switch (cmd) {
1603 case SET_KEY:
93ae2dd2
FF		 1604 if (sta)
1605 ath9k_del_ps_key(sc, vif, sta);
1606
4bbf4414 1607 key->hw_key_idx = 0;
040e539e 1608 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM		 1609 if (ret >= 0) {
1610 key->hw_key_idx = ret;
8feceb67
VT		 1611 /* push IV and Michael MIC generation to stack */
1612 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1613 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1614 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB		 1615 if (sc->sc_ah->sw_mgmt_crypto &&
1616 key->cipher == WLAN_CIPHER_SUITE_CCMP)
e548c49e 1617 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
6ace2891 1618 ret = 0;
8feceb67 1619 }
4bbf4414
RM		 1620 if (an && key->hw_key_idx) {
1621 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1622 if (an->key_idx[i])
1623 continue;
1624 an->key_idx[i] = key->hw_key_idx;
1625 break;
1626 }
1627 WARN_ON(i == ARRAY_SIZE(an->key_idx));
1628 }
8feceb67
VT		 1629 break;
1630 case DISABLE_KEY:
040e539e 1631 ath_key_delete(common, key);
4bbf4414
RM		 1632 if (an) {
1633 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1634 if (an->key_idx[i] != key->hw_key_idx)
1635 continue;
1636 an->key_idx[i] = 0;
1637 break;
1638 }
1639 }
1640 key->hw_key_idx = 0;
8feceb67
VT		 1641 break;
1642 default:
1643 ret = -EINVAL;
1644 }
f078f209 1645
3cbb5dd7 1646 ath9k_ps_restore(sc);
141b38b6
S		 1647 mutex_unlock(&sc->mutex);
1648
8feceb67
VT		 1649 return ret;
1650}
6c43c090 1651
8feceb67
VT		 1652static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1653 struct ieee80211_vif *vif,
1654 struct ieee80211_bss_conf *bss_conf,
1655 u32 changed)
1656{
da0d45f7
SM		 1657#define CHECK_ANI \
1658 (BSS_CHANGED_ASSOC | \
1659 BSS_CHANGED_IBSS | \
1660 BSS_CHANGED_BEACON_ENABLED)
1661
9ac58615 1662 struct ath_softc *sc = hw->priv;
2d0ddec5 1663 struct ath_hw *ah = sc->sc_ah;
1510718d 1664 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1665 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 1666 int slottime;
f078f209 1667
96f372c9 1668 ath9k_ps_wakeup(sc);
141b38b6
S		 1669 mutex_lock(&sc->mutex);
1670
9f61903c 1671 if (changed & BSS_CHANGED_ASSOC) {
6c43c090
SM		 1672 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1673 bss_conf->bssid, bss_conf->assoc);
1674
9a9c4fbc 1675 ath9k_calculate_summary_state(sc, avp->chanctx);
27babf9f
SM		 1676
1677 if (ath9k_is_chanctx_enabled()) {
1678 if (bss_conf->assoc)
1679 ath_chanctx_event(sc, vif,
1680 ATH_CHANCTX_EVENT_ASSOC);
1681 }
c6089ccc 1682 }
2d0ddec5 1683
2e5ef459 1684 if (changed & BSS_CHANGED_IBSS) {
2e5ef459
RM		 1685 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1686 common->curaid = bss_conf->aid;
1687 ath9k_hw_write_associd(sc->sc_ah);
2e5ef459
RM		 1688 }
1689
ef4ad633 1690 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
9198cf4a
RM		 1691 (changed & BSS_CHANGED_BEACON_INT) ||
1692 (changed & BSS_CHANGED_BEACON_INFO)) {
9a9c4fbc
RM		 1693 if (changed & BSS_CHANGED_BEACON_ENABLED)
1694 ath9k_calculate_summary_state(sc, avp->chanctx);
c32e4e51 1695 ath9k_beacon_config(sc, vif, changed);
9a9c4fbc 1696 }
0005baf4 1697
9a9c4fbc
RM		 1698 if ((avp->chanctx == sc->cur_chan) &&
1699 (changed & BSS_CHANGED_ERP_SLOT)) {
0005baf4
FF		 1700 if (bss_conf->use_short_slot)
1701 slottime = 9;
1702 else
1703 slottime = 20;
1704 if (vif->type == NL80211_IFTYPE_AP) {
1705 /*
1706 * Defer update, so that connected stations can adjust
1707 * their settings at the same time.
1708 * See beacon.c for more details
1709 */
1710 sc->beacon.slottime = slottime;
1711 sc->beacon.updateslot = UPDATE;
1712 } else {
1713 ah->slottime = slottime;
1714 ath9k_hw_init_global_settings(ah);
1715 }
2d0ddec5
JB		 1716 }
1717
c7dd40c9
SM		 1718 if (changed & BSS_CHANGED_P2P_PS)
1719 ath9k_p2p_bss_info_changed(sc, vif);
d463af4a 1720
da0d45f7
SM		 1721 if (changed & CHECK_ANI)
1722 ath_check_ani(sc);
1723
141b38b6 1724 mutex_unlock(&sc->mutex);
96f372c9 1725 ath9k_ps_restore(sc);
da0d45f7
SM		 1726
1727#undef CHECK_ANI
8feceb67 1728}
f078f209 1729
37a41b4a 1730static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1731{
9ac58615 1732 struct ath_softc *sc = hw->priv;
8feceb67 1733 u64 tsf;
f078f209 1734
141b38b6 1735 mutex_lock(&sc->mutex);
9abbfb27 1736 ath9k_ps_wakeup(sc);
141b38b6 1737 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 1738 ath9k_ps_restore(sc);
141b38b6 1739 mutex_unlock(&sc->mutex);
f078f209 1740
8feceb67
VT		 1741 return tsf;
1742}
f078f209 1743
37a41b4a
EP		 1744static void ath9k_set_tsf(struct ieee80211_hw *hw,
1745 struct ieee80211_vif *vif,
1746 u64 tsf)
3b5d665b 1747{
9ac58615 1748 struct ath_softc *sc = hw->priv;
3b5d665b 1749
141b38b6 1750 mutex_lock(&sc->mutex);
9abbfb27 1751 ath9k_ps_wakeup(sc);
141b38b6 1752 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 1753 ath9k_ps_restore(sc);
141b38b6 1754 mutex_unlock(&sc->mutex);
3b5d665b
AF		 1755}
1756
37a41b4a 1757static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1758{
9ac58615 1759 struct ath_softc *sc = hw->priv;
c83be688 1760
141b38b6 1761 mutex_lock(&sc->mutex);
21526d57
LR		 1762
1763 ath9k_ps_wakeup(sc);
141b38b6 1764 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR		 1765 ath9k_ps_restore(sc);
1766
141b38b6 1767 mutex_unlock(&sc->mutex);
8feceb67 1768}
f078f209 1769
8feceb67 1770static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 1771 struct ieee80211_vif *vif,
141b38b6
S		 1772 enum ieee80211_ampdu_mlme_action action,
1773 struct ieee80211_sta *sta,
0b01f030 1774 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 1775{
9ac58615 1776 struct ath_softc *sc = hw->priv;
16e23428 1777 bool flush = false;
8feceb67 1778 int ret = 0;
f078f209 1779
7ca7c776 1780 mutex_lock(&sc->mutex);
85ad181e 1781
8feceb67
VT		 1782 switch (action) {
1783 case IEEE80211_AMPDU_RX_START:
8feceb67
VT		 1784 break;
1785 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 1786 break;
1787 case IEEE80211_AMPDU_TX_START:
8b685ba9 1788 ath9k_ps_wakeup(sc);
231c3a1f
FF		 1789 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1790 if (!ret)
1791 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1792 ath9k_ps_restore(sc);
8feceb67 1793 break;
18b559d5
JB		 1794 case IEEE80211_AMPDU_TX_STOP_FLUSH:
1795 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
16e23428
FF		 1796 flush = true;
1797 case IEEE80211_AMPDU_TX_STOP_CONT:
8b685ba9 1798 ath9k_ps_wakeup(sc);
f83da965 1799 ath_tx_aggr_stop(sc, sta, tid);
08c96abd 1800 if (!flush)
16e23428 1801 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1802 ath9k_ps_restore(sc);
8feceb67 1803 break;
b1720231 1804 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 1805 ath9k_ps_wakeup(sc);
8469cdef 1806 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 1807 ath9k_ps_restore(sc);
8469cdef 1808 break;
8feceb67 1809 default:
3800276a 1810 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT		 1811 }
1812
7ca7c776 1813 mutex_unlock(&sc->mutex);
85ad181e 1814
8feceb67 1815 return ret;
f078f209
LR		 1816}
1817
62dad5b0
BP		 1818static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1819 struct survey_info *survey)
1820{
9ac58615 1821 struct ath_softc *sc = hw->priv;
3430098a 1822 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 1823 struct ieee80211_supported_band *sband;
3430098a 1824 struct ieee80211_channel *chan;
3430098a
FF		 1825 int pos;
1826
89f927af
LR		 1827 if (config_enabled(CONFIG_ATH9K_TX99))
1828 return -EOPNOTSUPP;
1829
b7cc9b97 1830 spin_lock_bh(&common->cc_lock);
3430098a
FF		 1831 if (idx == 0)
1832 ath_update_survey_stats(sc);
39162dbe
FF		 1833
1834 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1835 if (sband && idx >= sband->n_channels) {
1836 idx -= sband->n_channels;
1837 sband = NULL;
1838 }
62dad5b0 1839
39162dbe
FF		 1840 if (!sband)
1841 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 1842
3430098a 1843 if (!sband || idx >= sband->n_channels) {
b7cc9b97 1844 spin_unlock_bh(&common->cc_lock);
3430098a 1845 return -ENOENT;
4f1a5a4b 1846 }
62dad5b0 1847
3430098a
FF		 1848 chan = &sband->channels[idx];
1849 pos = chan->hw_value;
1850 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1851 survey->channel = chan;
b7cc9b97 1852 spin_unlock_bh(&common->cc_lock);
3430098a 1853
62dad5b0
BP		 1854 return 0;
1855}
1856
e239d859
FF		 1857static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
1858{
9ac58615 1859 struct ath_softc *sc = hw->priv;
e239d859
FF		 1860 struct ath_hw *ah = sc->sc_ah;
1861
89f927af
LR		 1862 if (config_enabled(CONFIG_ATH9K_TX99))
1863 return;
1864
e239d859
FF		 1865 mutex_lock(&sc->mutex);
1866 ah->coverage_class = coverage_class;
8b2a3827
MSS		 1867
1868 ath9k_ps_wakeup(sc);
e239d859 1869 ath9k_hw_init_global_settings(ah);
8b2a3827
MSS		 1870 ath9k_ps_restore(sc);
1871
e239d859
FF		 1872 mutex_unlock(&sc->mutex);
1873}
1874
10e23181
FF		 1875static bool ath9k_has_tx_pending(struct ath_softc *sc)
1876{
f7838073 1877 int i, npend = 0;
10e23181
FF		 1878
1879 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1880 if (!ATH_TXQ_SETUP(sc, i))
1881 continue;
1882
1883 if (!sc->tx.txq[i].axq_depth)
1884 continue;
1885
1886 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1887 if (npend)
1888 break;
1889 }
1890
1891 return !!npend;
1892}
1893
77be2c54
EG		 1894static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1895 u32 queues, bool drop)
bff11766
FF		 1896{
1897 struct ath_softc *sc = hw->priv;
1898
1899 mutex_lock(&sc->mutex);
1900 __ath9k_flush(hw, queues, drop);
1901 mutex_unlock(&sc->mutex);
1902}
1903
1904void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
69081624 1905{
69081624 1906 struct ath_softc *sc = hw->priv;
99aa55b6
MSS		 1907 struct ath_hw *ah = sc->sc_ah;
1908 struct ath_common *common = ath9k_hw_common(ah);
10e23181 1909 int timeout = HZ / 5; /* 200 ms */
2f6fc351 1910 bool drain_txq;
3ad9c386 1911 int i;
69081624 1912
69081624
VT		 1913 cancel_delayed_work_sync(&sc->tx_complete_work);
1914
6a6b3f3e 1915 if (ah->ah_flags & AH_UNPLUGGED) {
d2182b69 1916 ath_dbg(common, ANY, "Device has been unplugged!\n");
6a6b3f3e
MSS		 1917 return;
1918 }
1919
eefa01dd 1920 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
d2182b69 1921 ath_dbg(common, ANY, "Device not present\n");
99aa55b6
MSS		 1922 return;
1923 }
1924
10e23181
FF		 1925 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc),
1926 timeout) > 0)
1927 drop = false;
69081624 1928
9df0d6a2
FF		 1929 if (drop) {
1930 ath9k_ps_wakeup(sc);
1931 spin_lock_bh(&sc->sc_pcu_lock);
1381559b 1932 drain_txq = ath_drain_all_txq(sc);
9df0d6a2 1933 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440 1934
9df0d6a2 1935 if (!drain_txq)
1381559b 1936 ath_reset(sc);
9adcf440 1937
9df0d6a2 1938 ath9k_ps_restore(sc);
3ad9c386
RM		 1939 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
1940 ieee80211_wake_queue(sc->hw,
1941 sc->cur_chan->hw_queue_base + i);
1942 }
9df0d6a2 1943 }
d78f4b3e 1944
69081624 1945 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
69081624
VT		 1946}
1947
15b91e83
VN		 1948static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
1949{
1950 struct ath_softc *sc = hw->priv;
1951 int i;
1952
1953 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1954 if (!ATH_TXQ_SETUP(sc, i))
1955 continue;
1956
1957 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
1958 return true;
1959 }
1960 return false;
1961}
1962
5595f119 1963static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
ba4903f9
FF		 1964{
1965 struct ath_softc *sc = hw->priv;
1966 struct ath_hw *ah = sc->sc_ah;
1967 struct ieee80211_vif *vif;
1968 struct ath_vif *avp;
1969 struct ath_buf *bf;
1970 struct ath_tx_status ts;
4286df60 1971 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
ba4903f9
FF		 1972 int status;
1973
1974 vif = sc->beacon.bslot[0];
1975 if (!vif)
1976 return 0;
1977
aa45fe96 1978 if (!vif->bss_conf.enable_beacon)
ba4903f9
FF		 1979 return 0;
1980
aa45fe96
SM		 1981 avp = (void *)vif->drv_priv;
1982
4286df60 1983 if (!sc->beacon.tx_processed && !edma) {
ba4903f9
FF		 1984 tasklet_disable(&sc->bcon_tasklet);
1985
1986 bf = avp->av_bcbuf;
1987 if (!bf || !bf->bf_mpdu)
1988 goto skip;
1989
1990 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
1991 if (status == -EINPROGRESS)
1992 goto skip;
1993
1994 sc->beacon.tx_processed = true;
1995 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
1996
1997skip:
1998 tasklet_enable(&sc->bcon_tasklet);
1999 }
2000
2001 return sc->beacon.tx_last;
2002}
2003
52c94f41
MSS		 2004static int ath9k_get_stats(struct ieee80211_hw *hw,
2005 struct ieee80211_low_level_stats *stats)
2006{
2007 struct ath_softc *sc = hw->priv;
2008 struct ath_hw *ah = sc->sc_ah;
2009 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2010
2011 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2012 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2013 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2014 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2015 return 0;
2016}
2017
43c35284
FF		 2018static u32 fill_chainmask(u32 cap, u32 new)
2019{
2020 u32 filled = 0;
2021 int i;
2022
2023 for (i = 0; cap && new; i++, cap >>= 1) {
2024 if (!(cap & BIT(0)))
2025 continue;
2026
2027 if (new & BIT(0))
2028 filled |= BIT(i);
2029
2030 new >>= 1;
2031 }
2032
2033 return filled;
2034}
2035
5d9c7e3c
FF		 2036static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2037{
fea92cbf
FF		 2038 if (AR_SREV_9300_20_OR_LATER(ah))
2039 return true;
2040
5d9c7e3c
FF		 2041 switch (val & 0x7) {
2042 case 0x1:
2043 case 0x3:
2044 case 0x7:
2045 return true;
2046 case 0x2:
2047 return (ah->caps.rx_chainmask == 1);
2048 default:
2049 return false;
2050 }
2051}
2052
43c35284
FF		 2053static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2054{
2055 struct ath_softc *sc = hw->priv;
2056 struct ath_hw *ah = sc->sc_ah;
2057
5d9c7e3c
FF		 2058 if (ah->caps.rx_chainmask != 1)
2059 rx_ant |= tx_ant;
2060
2061 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
43c35284
FF		 2062 return -EINVAL;
2063
2064 sc->ant_rx = rx_ant;
2065 sc->ant_tx = tx_ant;
2066
2067 if (ah->caps.rx_chainmask == 1)
2068 return 0;
2069
2070 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2071 if (AR_SREV_9100(ah))
2072 ah->rxchainmask = 0x7;
2073 else
2074 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2075
2076 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
b57ba3b2 2077 ath9k_cmn_reload_chainmask(ah);
43c35284
FF		 2078
2079 return 0;
2080}
2081
2082static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2083{
2084 struct ath_softc *sc = hw->priv;
2085
2086 *tx_ant = sc->ant_tx;
2087 *rx_ant = sc->ant_rx;
2088 return 0;
2089}
2090
e93d083f
SW		 2091static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2092{
2093 struct ath_softc *sc = hw->priv;
eefa01dd
OR		 2094 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2095 set_bit(ATH_OP_SCANNING, &common->op_flags);
e93d083f
SW		 2096}
2097
2098static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2099{
2100 struct ath_softc *sc = hw->priv;
eefa01dd
OR		 2101 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2102 clear_bit(ATH_OP_SCANNING, &common->op_flags);
e93d083f 2103}
b11e640a 2104
499afacc
SM		 2105#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2106
78b21949 2107static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
855df36d 2108 struct ieee80211_scan_request *hw_req)
78b21949 2109{
855df36d 2110 struct cfg80211_scan_request *req = &hw_req->req;
78b21949
FF		 2111 struct ath_softc *sc = hw->priv;
2112 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2113 int ret = 0;
2114
2115 mutex_lock(&sc->mutex);
2116
2117 if (WARN_ON(sc->offchannel.scan_req)) {
2118 ret = -EBUSY;
2119 goto out;
2120 }
2121
2122 ath9k_ps_wakeup(sc);
2123 set_bit(ATH_OP_SCANNING, &common->op_flags);
2124 sc->offchannel.scan_vif = vif;
2125 sc->offchannel.scan_req = req;
2126 sc->offchannel.scan_idx = 0;
78b21949 2127
bc81d43a
SM		 2128 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2129 vif->addr);
2130
2131 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2132 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
405393cf 2133 ath_offchannel_next(sc);
bc81d43a 2134 }
78b21949
FF		 2135
2136out:
2137 mutex_unlock(&sc->mutex);
2138
2139 return ret;
2140}
2141
2142static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2143 struct ieee80211_vif *vif)
2144{
2145 struct ath_softc *sc = hw->priv;
bc81d43a
SM		 2146 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2147
2148 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
78b21949
FF		 2149
2150 mutex_lock(&sc->mutex);
2151 del_timer_sync(&sc->offchannel.timer);
2152 ath_scan_complete(sc, true);
2153 mutex_unlock(&sc->mutex);
2154}
2155
405393cf
FF		 2156static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2157 struct ieee80211_vif *vif,
2158 struct ieee80211_channel *chan, int duration,
2159 enum ieee80211_roc_type type)
2160{
2161 struct ath_softc *sc = hw->priv;
bc81d43a 2162 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
405393cf
FF		 2163 int ret = 0;
2164
2165 mutex_lock(&sc->mutex);
2166
2167 if (WARN_ON(sc->offchannel.roc_vif)) {
2168 ret = -EBUSY;
2169 goto out;
2170 }
2171
2172 ath9k_ps_wakeup(sc);
2173 sc->offchannel.roc_vif = vif;
2174 sc->offchannel.roc_chan = chan;
2175 sc->offchannel.roc_duration = duration;
2176
bc81d43a
SM		 2177 ath_dbg(common, CHAN_CTX,
2178 "RoC request on vif: %pM, type: %d duration: %d\n",
2179 vif->addr, type, duration);
2180
2181 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2182 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
405393cf 2183 ath_offchannel_next(sc);
bc81d43a 2184 }
405393cf
FF		 2185
2186out:
2187 mutex_unlock(&sc->mutex);
2188
2189 return ret;
2190}
2191
2192static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw)
2193{
2194 struct ath_softc *sc = hw->priv;
bc81d43a 2195 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
405393cf
FF		 2196
2197 mutex_lock(&sc->mutex);
2198
bc81d43a 2199 ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
405393cf
FF		 2200 del_timer_sync(&sc->offchannel.timer);
2201
2202 if (sc->offchannel.roc_vif) {
2203 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2204 ath_roc_complete(sc, true);
2205 }
2206
2207 mutex_unlock(&sc->mutex);
2208
2209 return 0;
2210}
2211
39305635
FF		 2212static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2213 struct ieee80211_chanctx_conf *conf)
2214{
2215 struct ath_softc *sc = hw->priv;
bc81d43a 2216 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635 2217 struct ath_chanctx *ctx, **ptr;
3ad9c386 2218 int pos;
39305635
FF		 2219
2220 mutex_lock(&sc->mutex);
c4dc0d04
RM		 2221
2222 ath_for_each_chanctx(sc, ctx) {
2223 if (ctx->assigned)
2224 continue;
2225
2226 ptr = (void *) conf->drv_priv;
2227 *ptr = ctx;
2228 ctx->assigned = true;
3ad9c386
RM		 2229 pos = ctx - &sc->chanctx[0];
2230 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
bc81d43a
SM		 2231
2232 ath_dbg(common, CHAN_CTX,
2233 "Add channel context: %d MHz\n",
2234 conf->def.chan->center_freq);
2235
c4dc0d04 2236 ath_chanctx_set_channel(sc, ctx, &conf->def);
39305635 2237 mutex_unlock(&sc->mutex);
c4dc0d04 2238 return 0;
39305635 2239 }
bc81d43a 2240
39305635 2241 mutex_unlock(&sc->mutex);
c4dc0d04 2242 return -ENOSPC;
39305635
FF		 2243}
2244
2245
2246static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2247 struct ieee80211_chanctx_conf *conf)
2248{
2249 struct ath_softc *sc = hw->priv;
bc81d43a 2250 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635
FF		 2251 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2252
2253 mutex_lock(&sc->mutex);
bc81d43a
SM		 2254
2255 ath_dbg(common, CHAN_CTX,
2256 "Remove channel context: %d MHz\n",
2257 conf->def.chan->center_freq);
2258
39305635 2259 ctx->assigned = false;
3ad9c386 2260 ctx->hw_queue_base = -1;
73fa2f26 2261 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
bc81d43a 2262
39305635
FF		 2263 mutex_unlock(&sc->mutex);
2264}
2265
2266static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2267 struct ieee80211_chanctx_conf *conf,
2268 u32 changed)
2269{
2270 struct ath_softc *sc = hw->priv;
bc81d43a 2271 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635
FF		 2272 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2273
2274 mutex_lock(&sc->mutex);
bc81d43a
SM		 2275 ath_dbg(common, CHAN_CTX,
2276 "Change channel context: %d MHz\n",
2277 conf->def.chan->center_freq);
39305635
FF		 2278 ath_chanctx_set_channel(sc, ctx, &conf->def);
2279 mutex_unlock(&sc->mutex);
2280}
2281
2282static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2283 struct ieee80211_vif *vif,
2284 struct ieee80211_chanctx_conf *conf)
2285{
2286 struct ath_softc *sc = hw->priv;
bc81d43a 2287 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635
FF		 2288 struct ath_vif *avp = (void *)vif->drv_priv;
2289 struct ath_chanctx *ctx = ath_chanctx_get(conf);
3ad9c386 2290 int i;
39305635
FF		 2291
2292 mutex_lock(&sc->mutex);
bc81d43a
SM		 2293
2294 ath_dbg(common, CHAN_CTX,
2295 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2296 vif->addr, vif->type, vif->p2p,
2297 conf->def.chan->center_freq);
2298
39305635
FF		 2299 avp->chanctx = ctx;
2300 list_add_tail(&avp->list, &ctx->vifs);
9a9c4fbc 2301 ath9k_calculate_summary_state(sc, ctx);
3ad9c386
RM		 2302 for (i = 0; i < IEEE80211_NUM_ACS; i++)
2303 vif->hw_queue[i] = ctx->hw_queue_base + i;
bc81d43a 2304
39305635
FF		 2305 mutex_unlock(&sc->mutex);
2306
2307 return 0;
2308}
2309
2310static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2311 struct ieee80211_vif *vif,
2312 struct ieee80211_chanctx_conf *conf)
2313{
2314 struct ath_softc *sc = hw->priv;
bc81d43a 2315 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635
FF		 2316 struct ath_vif *avp = (void *)vif->drv_priv;
2317 struct ath_chanctx *ctx = ath_chanctx_get(conf);
3ad9c386 2318 int ac;
39305635
FF		 2319
2320 mutex_lock(&sc->mutex);
bc81d43a
SM		 2321
2322 ath_dbg(common, CHAN_CTX,
2323 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2324 vif->addr, vif->type, vif->p2p,
2325 conf->def.chan->center_freq);
2326
39305635
FF		 2327 avp->chanctx = NULL;
2328 list_del(&avp->list);
9a9c4fbc 2329 ath9k_calculate_summary_state(sc, ctx);
3ad9c386
RM		 2330 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2331 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
bc81d43a 2332
39305635
FF		 2333 mutex_unlock(&sc->mutex);
2334}
2335
e20a854e
SM		 2336static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2337 struct ieee80211_vif *vif)
2338{
2339 struct ath_softc *sc = hw->priv;
2340 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2341 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
2342 bool changed = false;
2343
2344 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2345 return;
2346
2347 if (!avp->chanctx)
2348 return;
2349
2350 mutex_lock(&sc->mutex);
2351
2352 spin_lock_bh(&sc->chan_lock);
2353 if (sc->next_chan || (sc->cur_chan != avp->chanctx)) {
2354 sc->next_chan = avp->chanctx;
2355 changed = true;
2356 }
2357 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2358 spin_unlock_bh(&sc->chan_lock);
2359
2360 if (changed)
2361 ath_chanctx_set_next(sc, true);
2362
2363 mutex_unlock(&sc->mutex);
2364}
2365
78b21949
FF		 2366void ath9k_fill_chanctx_ops(void)
2367{
499afacc 2368 if (!ath9k_is_chanctx_enabled())
78b21949
FF		 2369 return;
2370
bc81d43a
SM		 2371 ath9k_ops.hw_scan = ath9k_hw_scan;
2372 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
2373 ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
405393cf 2374 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
bc81d43a
SM		 2375 ath9k_ops.add_chanctx = ath9k_add_chanctx;
2376 ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
2377 ath9k_ops.change_chanctx = ath9k_change_chanctx;
2378 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
2379 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
e20a854e 2380 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
78b21949
FF		 2381}
2382
499afacc
SM		 2383#endif
2384
6baff7f9 2385struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2386 .tx = ath9k_tx,
2387 .start = ath9k_start,
2388 .stop = ath9k_stop,
2389 .add_interface = ath9k_add_interface,
6b3b991d 2390 .change_interface = ath9k_change_interface,
8feceb67
VT		 2391 .remove_interface = ath9k_remove_interface,
2392 .config = ath9k_config,
8feceb67 2393 .configure_filter = ath9k_configure_filter,
4ca77860
JB		 2394 .sta_add = ath9k_sta_add,
2395 .sta_remove = ath9k_sta_remove,
5519541d 2396 .sta_notify = ath9k_sta_notify,
8feceb67 2397 .conf_tx = ath9k_conf_tx,
8feceb67 2398 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2399 .set_key = ath9k_set_key,
8feceb67 2400 .get_tsf = ath9k_get_tsf,
3b5d665b 2401 .set_tsf = ath9k_set_tsf,
8feceb67 2402 .reset_tsf = ath9k_reset_tsf,
4233df6b 2403 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2404 .get_survey = ath9k_get_survey,
3b319aae 2405 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2406 .set_coverage_class = ath9k_set_coverage_class,
69081624 2407 .flush = ath9k_flush,
15b91e83 2408 .tx_frames_pending = ath9k_tx_frames_pending,
52c94f41 2409 .tx_last_beacon = ath9k_tx_last_beacon,
86a22acf 2410 .release_buffered_frames = ath9k_release_buffered_frames,
52c94f41 2411 .get_stats = ath9k_get_stats,
43c35284
FF		 2412 .set_antenna = ath9k_set_antenna,
2413 .get_antenna = ath9k_get_antenna,
b90bd9d1 2414
e60001e7 2415#ifdef CONFIG_ATH9K_WOW
b11e640a
MSS		 2416 .suspend = ath9k_suspend,
2417 .resume = ath9k_resume,
2418 .set_wakeup = ath9k_set_wakeup,
2419#endif
2420
b90bd9d1
BG		 2421#ifdef CONFIG_ATH9K_DEBUGFS
2422 .get_et_sset_count = ath9k_get_et_sset_count,
a145daf7
SM		 2423 .get_et_stats = ath9k_get_et_stats,
2424 .get_et_strings = ath9k_get_et_strings,
2425#endif
2426
1cdbaf0d 2427#if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
a145daf7 2428 .sta_add_debugfs = ath9k_sta_add_debugfs,
b90bd9d1 2429#endif
e93d083f
SW		 2430 .sw_scan_start = ath9k_sw_scan_start,
2431 .sw_scan_complete = ath9k_sw_scan_complete,
8feceb67 2432};
Linux kernel - Deliverables
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