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ath9k: Fix bug in determining calibration support
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209
LR		 19
20#define ATH_PCI_VERSION "0.1"
21
f078f209
LR		 22static char *dev_info = "ath9k";
23
24MODULE_AUTHOR("Atheros Communications");
25MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27MODULE_LICENSE("Dual BSD/GPL");
28
b3bd89ce
JM		 29static int modparam_nohwcrypt;
30module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
5f8e077c
LR		 33/* We use the hw_value as an index into our private channel structure */
34
35#define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
38 .max_power = 30, \
39}
40
41#define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
45 .max_power = 30, \
46}
47
48/* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67};
68
69/* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102};
103
ce111bad
LR		 104static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
ff37e337 106{
030bb495
LR		 107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 118 else
030bb495
LR		 119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
96742256
LR		 133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 135 break;
136 default:
ce111bad 137 BUG_ON(1);
030bb495
LR		 138 break;
139 }
ff37e337
S		 140}
141
142static void ath_update_txpow(struct ath_softc *sc)
143{
cbe61d8a 144 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 145 u32 txpow;
146
17d7904d
S		 147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 151 sc->curtxpow = txpow;
ff37e337
S		 152 }
153}
154
155static u8 parse_mpdudensity(u8 mpdudensity)
156{
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188}
189
190static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191{
192 struct ath_rate_table *rate_table = NULL;
193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
ff37e337 227 sband->n_bitrates++;
f46730d1 228
04bd4638
S		 229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 231 }
232}
233
ff37e337
S		 234/*
235 * Set/change channels. If the channel is really being changed, it's done
236 * by reseting the chip. To accomplish this we must first cleanup any pending
237 * DMA, then restart stuff.
238*/
0e2dedf9
JM		 239int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
240 struct ath9k_channel *hchan)
ff37e337 241{
cbe61d8a 242 struct ath_hw *ah = sc->sc_ah;
ff37e337 243 bool fastcc = true, stopped;
ae8d2858
LR		 244 struct ieee80211_channel *channel = hw->conf.channel;
245 int r;
ff37e337
S		 246
247 if (sc->sc_flags & SC_OP_INVALID)
248 return -EIO;
249
3cbb5dd7
VN		 250 ath9k_ps_wakeup(sc);
251
c0d7c7af
LR		 252 /*
253 * This is only performed if the channel settings have
254 * actually changed.
255 *
256 * To switch channels clear any pending DMA operations;
257 * wait long enough for the RX fifo to drain, reset the
258 * hardware at the new frequency, and then re-enable
259 * the relevant bits of the h/w.
260 */
261 ath9k_hw_set_interrupts(ah, 0);
043a0405 262 ath_drain_all_txq(sc, false);
c0d7c7af 263 stopped = ath_stoprecv(sc);
ff37e337 264
c0d7c7af
LR		 265 /* XXX: do not flush receive queue here. We don't want
266 * to flush data frames already in queue because of
267 * changing channel. */
ff37e337 268
c0d7c7af
LR		 269 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
270 fastcc = false;
271
272 DPRINTF(sc, ATH_DBG_CONFIG,
273 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 274 sc->sc_ah->curchan->channel,
c0d7c7af 275 channel->center_freq, sc->tx_chan_width);
ff37e337 276
c0d7c7af
LR		 277 spin_lock_bh(&sc->sc_resetlock);
278
279 r = ath9k_hw_reset(ah, hchan, fastcc);
280 if (r) {
281 DPRINTF(sc, ATH_DBG_FATAL,
282 "Unable to reset channel (%u Mhz) "
283 "reset status %u\n",
284 channel->center_freq, r);
285 spin_unlock_bh(&sc->sc_resetlock);
286 return r;
ff37e337 287 }
c0d7c7af
LR		 288 spin_unlock_bh(&sc->sc_resetlock);
289
c0d7c7af
LR		 290 sc->sc_flags &= ~SC_OP_FULL_RESET;
291
292 if (ath_startrecv(sc) != 0) {
293 DPRINTF(sc, ATH_DBG_FATAL,
294 "Unable to restart recv logic\n");
295 return -EIO;
296 }
297
298 ath_cache_conf_rate(sc, &hw->conf);
299 ath_update_txpow(sc);
17d7904d 300 ath9k_hw_set_interrupts(ah, sc->imask);
3cbb5dd7 301 ath9k_ps_restore(sc);
ff37e337
S		 302 return 0;
303}
304
305/*
306 * This routine performs the periodic noise floor calibration function
307 * that is used to adjust and optimize the chip performance. This
308 * takes environmental changes (location, temperature) into account.
309 * When the task is complete, it reschedules itself depending on the
310 * appropriate interval that was calculated.
311 */
312static void ath_ani_calibrate(unsigned long data)
313{
20977d3e
S		 314 struct ath_softc *sc = (struct ath_softc *)data;
315 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 316 bool longcal = false;
317 bool shortcal = false;
318 bool aniflag = false;
319 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 320 u32 cal_interval, short_cal_interval;
ff37e337 321
20977d3e
S		 322 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
323 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 324
325 /*
326 * don't calibrate when we're scanning.
327 * we are most likely not on our home channel.
328 */
0c98de65 329 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 330 goto set_timer;
ff37e337
S		 331
332 /* Long calibration runs independently of short calibration. */
17d7904d 333 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 334 longcal = true;
04bd4638 335 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 336 sc->ani.longcal_timer = timestamp;
ff37e337
S		 337 }
338
17d7904d
S		 339 /* Short calibration applies only while caldone is false */
340 if (!sc->ani.caldone) {
20977d3e 341 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 342 shortcal = true;
04bd4638 343 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 344 sc->ani.shortcal_timer = timestamp;
345 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 346 }
347 } else {
17d7904d 348 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 349 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 350 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
351 if (sc->ani.caldone)
352 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 353 }
354 }
355
356 /* Verify whether we must check ANI */
20977d3e 357 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 358 aniflag = true;
17d7904d 359 sc->ani.checkani_timer = timestamp;
ff37e337
S		 360 }
361
362 /* Skip all processing if there's nothing to do. */
363 if (longcal || shortcal || aniflag) {
364 /* Call ANI routine if necessary */
365 if (aniflag)
20977d3e 366 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
ff37e337
S		 367
368 /* Perform calibration if necessary */
369 if (longcal || shortcal) {
370 bool iscaldone = false;
371
2660b81a 372 if (ath9k_hw_calibrate(ah, ah->curchan,
17d7904d 373 sc->rx_chainmask, longcal,
ff37e337
S		 374 &iscaldone)) {
375 if (longcal)
17d7904d 376 sc->ani.noise_floor =
ff37e337 377 ath9k_hw_getchan_noise(ah,
2660b81a 378 ah->curchan);
ff37e337
S		 379
380 DPRINTF(sc, ATH_DBG_ANI,
04bd4638 381 "calibrate chan %u/%x nf: %d\n",
2660b81a
S		 382 ah->curchan->channel,
383 ah->curchan->channelFlags,
17d7904d 384 sc->ani.noise_floor);
ff37e337
S		 385 } else {
386 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 387 "calibrate chan %u/%x failed\n",
2660b81a
S		 388 ah->curchan->channel,
389 ah->curchan->channelFlags);
ff37e337 390 }
17d7904d 391 sc->ani.caldone = iscaldone;
ff37e337
S		 392 }
393 }
394
20977d3e 395set_timer:
ff37e337
S		 396 /*
397 * Set timer interval based on previous results.
398 * The interval must be the shortest necessary to satisfy ANI,
399 * short calibration and long calibration.
400 */
aac9207e 401 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 402 if (sc->sc_ah->config.enable_ani)
aac9207e 403 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 404 if (!sc->ani.caldone)
20977d3e 405 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 406
17d7904d 407 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 408}
409
410/*
411 * Update tx/rx chainmask. For legacy association,
412 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 413 * the chainmask configuration, for bt coexistence, use
414 * the chainmask configuration even in legacy mode.
ff37e337 415 */
0e2dedf9 416void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 417{
c97c92d9 418 if (is_ht ||
2660b81a
S		 419 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
420 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
421 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 422 } else {
17d7904d
S		 423 sc->tx_chainmask = 1;
424 sc->rx_chainmask = 1;
ff37e337
S		 425 }
426
04bd4638 427 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 428 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 429}
430
431static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
432{
433 struct ath_node *an;
434
435 an = (struct ath_node *)sta->drv_priv;
436
87792efc 437 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 438 ath_tx_node_init(sc, an);
87792efc
S		 439 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
440 sta->ht_cap.ampdu_factor);
441 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
442 }
ff37e337
S		 443}
444
445static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
446{
447 struct ath_node *an = (struct ath_node *)sta->drv_priv;
448
449 if (sc->sc_flags & SC_OP_TXAGGR)
450 ath_tx_node_cleanup(sc, an);
451}
452
453static void ath9k_tasklet(unsigned long data)
454{
455 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 456 u32 status = sc->intrstatus;
ff37e337
S		 457
458 if (status & ATH9K_INT_FATAL) {
ff37e337
S		 459 ath_reset(sc, false);
460 return;
063d8be3 461 }
ff37e337 462
063d8be3
S		 463 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
464 spin_lock_bh(&sc->rx.rxflushlock);
465 ath_rx_tasklet(sc, 0);
466 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 467 }
468
063d8be3
S		 469 if (status & ATH9K_INT_TX)
470 ath_tx_tasklet(sc);
471
ff37e337 472 /* re-enable hardware interrupt */
17d7904d 473 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337
S		 474}
475
6baff7f9 476irqreturn_t ath_isr(int irq, void *dev)
ff37e337 477{
063d8be3
S		 478#define SCHED_INTR ( \
479 ATH9K_INT_FATAL | \
480 ATH9K_INT_RXORN | \
481 ATH9K_INT_RXEOL | \
482 ATH9K_INT_RX | \
483 ATH9K_INT_TX | \
484 ATH9K_INT_BMISS | \
485 ATH9K_INT_CST | \
486 ATH9K_INT_TSFOOR)
487
ff37e337 488 struct ath_softc *sc = dev;
cbe61d8a 489 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 490 enum ath9k_int status;
491 bool sched = false;
492
063d8be3
S		 493 /*
494 * The hardware is not ready/present, don't
495 * touch anything. Note this can happen early
496 * on if the IRQ is shared.
497 */
498 if (sc->sc_flags & SC_OP_INVALID)
499 return IRQ_NONE;
ff37e337 500
063d8be3
S		 501 ath9k_ps_wakeup(sc);
502
503 /* shared irq, not for us */
504
505 if (!ath9k_hw_intrpend(ah)) {
506 ath9k_ps_restore(sc);
507 return IRQ_NONE;
508 }
509
510 /*
511 * Figure out the reason(s) for the interrupt. Note
512 * that the hal returns a pseudo-ISR that may include
513 * bits we haven't explicitly enabled so we mask the
514 * value to insure we only process bits we requested.
515 */
516 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
517 status &= sc->imask; /* discard unasked-for bits */
ff37e337 518
063d8be3
S		 519 /*
520 * If there are no status bits set, then this interrupt was not
521 * for me (should have been caught above).
522 */
523 if (!status) {
524 ath9k_ps_restore(sc);
525 return IRQ_NONE;
526 }
ff37e337 527
063d8be3
S		 528 /* Cache the status */
529 sc->intrstatus = status;
530
531 if (status & SCHED_INTR)
532 sched = true;
533
534 /*
535 * If a FATAL or RXORN interrupt is received, we have to reset the
536 * chip immediately.
537 */
538 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
539 goto chip_reset;
540
541 if (status & ATH9K_INT_SWBA)
542 tasklet_schedule(&sc->bcon_tasklet);
543
544 if (status & ATH9K_INT_TXURN)
545 ath9k_hw_updatetxtriglevel(ah, true);
546
547 if (status & ATH9K_INT_MIB) {
ff37e337 548 /*
063d8be3
S		 549 * Disable interrupts until we service the MIB
550 * interrupt; otherwise it will continue to
551 * fire.
ff37e337 552 */
063d8be3
S		 553 ath9k_hw_set_interrupts(ah, 0);
554 /*
555 * Let the hal handle the event. We assume
556 * it will clear whatever condition caused
557 * the interrupt.
558 */
559 ath9k_hw_procmibevent(ah, &sc->nodestats);
560 ath9k_hw_set_interrupts(ah, sc->imask);
561 }
ff37e337 562
063d8be3
S		 563 if (status & ATH9K_INT_TIM_TIMER) {
564 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
565 /* Clear RxAbort bit so that we can
566 * receive frames */
567 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
568 ath9k_hw_setrxabort(ah, 0);
ff37e337 569 sched = true;
063d8be3 570 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 571 }
063d8be3
S		 572 }
573
574chip_reset:
ff37e337 575
063d8be3 576 ath9k_ps_restore(sc);
817e11de
S		 577 ath_debug_stat_interrupt(sc, status);
578
ff37e337
S		 579 if (sched) {
580 /* turn off every interrupt except SWBA */
17d7904d 581 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 582 tasklet_schedule(&sc->intr_tq);
583 }
584
585 return IRQ_HANDLED;
063d8be3
S		 586
587#undef SCHED_INTR
ff37e337
S		 588}
589
f078f209 590static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 591 struct ieee80211_channel *chan,
094d05dc 592 enum nl80211_channel_type channel_type)
f078f209
LR		 593{
594 u32 chanmode = 0;
f078f209
LR		 595
596 switch (chan->band) {
597 case IEEE80211_BAND_2GHZ:
094d05dc
S		 598 switch(channel_type) {
599 case NL80211_CHAN_NO_HT:
600 case NL80211_CHAN_HT20:
f078f209 601 chanmode = CHANNEL_G_HT20;
094d05dc
S		 602 break;
603 case NL80211_CHAN_HT40PLUS:
f078f209 604 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 605 break;
606 case NL80211_CHAN_HT40MINUS:
f078f209 607 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 608 break;
609 }
f078f209
LR		 610 break;
611 case IEEE80211_BAND_5GHZ:
094d05dc
S		 612 switch(channel_type) {
613 case NL80211_CHAN_NO_HT:
614 case NL80211_CHAN_HT20:
f078f209 615 chanmode = CHANNEL_A_HT20;
094d05dc
S		 616 break;
617 case NL80211_CHAN_HT40PLUS:
f078f209 618 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 619 break;
620 case NL80211_CHAN_HT40MINUS:
f078f209 621 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 622 break;
623 }
f078f209
LR		 624 break;
625 default:
626 break;
627 }
628
629 return chanmode;
630}
631
6ace2891 632static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 633 struct ath9k_keyval *hk, const u8 *addr,
634 bool authenticator)
f078f209 635{
6ace2891
JM		 636 const u8 *key_rxmic;
637 const u8 *key_txmic;
f078f209 638
6ace2891
JM		 639 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
640 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 641
642 if (addr == NULL) {
d216aaa6
JM		 643 /*
644 * Group key installation - only two key cache entries are used
645 * regardless of splitmic capability since group key is only
646 * used either for TX or RX.
647 */
3f53dd64
JM		 648 if (authenticator) {
649 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
650 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
651 } else {
652 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
653 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
654 }
d216aaa6 655 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 656 }
17d7904d 657 if (!sc->splitmic) {
d216aaa6 658 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 659 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
660 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 661 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 662 }
d216aaa6
JM		 663
664 /* Separate key cache entries for TX and RX */
665
666 /* TX key goes at first index, RX key at +32. */
f078f209 667 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 668 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
669 /* TX MIC entry failed. No need to proceed further */
d8baa939 670 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 671 "Setting TX MIC Key Failed\n");
f078f209
LR		 672 return 0;
673 }
674
675 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
676 /* XXX delete tx key on failure? */
d216aaa6 677 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 678}
679
680static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
681{
682 int i;
683
17d7904d
S		 684 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
685 if (test_bit(i, sc->keymap) ||
686 test_bit(i + 64, sc->keymap))
6ace2891 687 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 688 if (sc->splitmic &&
689 (test_bit(i + 32, sc->keymap) ||
690 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 691 continue; /* At least one part of TKIP key allocated */
692
693 /* Found a free slot for a TKIP key */
694 return i;
695 }
696 return -1;
697}
698
699static int ath_reserve_key_cache_slot(struct ath_softc *sc)
700{
701 int i;
702
703 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 704 if (sc->splitmic) {
705 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
706 if (!test_bit(i, sc->keymap) &&
707 (test_bit(i + 32, sc->keymap) ||
708 test_bit(i + 64, sc->keymap) ||
709 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 710 return i;
17d7904d
S		 711 if (!test_bit(i + 32, sc->keymap) &&
712 (test_bit(i, sc->keymap) ||
713 test_bit(i + 64, sc->keymap) ||
714 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 715 return i + 32;
17d7904d
S		 716 if (!test_bit(i + 64, sc->keymap) &&
717 (test_bit(i , sc->keymap) ||
718 test_bit(i + 32, sc->keymap) ||
719 test_bit(i + 64 + 32, sc->keymap)))
ea612132 720 return i + 64;
17d7904d
S		 721 if (!test_bit(i + 64 + 32, sc->keymap) &&
722 (test_bit(i, sc->keymap) ||
723 test_bit(i + 32, sc->keymap) ||
724 test_bit(i + 64, sc->keymap)))
ea612132 725 return i + 64 + 32;
6ace2891
JM		 726 }
727 } else {
17d7904d
S		 728 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
729 if (!test_bit(i, sc->keymap) &&
730 test_bit(i + 64, sc->keymap))
6ace2891 731 return i;
17d7904d
S		 732 if (test_bit(i, sc->keymap) &&
733 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 734 return i + 64;
735 }
736 }
737
738 /* No partially used TKIP slots, pick any available slot */
17d7904d 739 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 740 /* Do not allow slots that could be needed for TKIP group keys
741 * to be used. This limitation could be removed if we know that
742 * TKIP will not be used. */
743 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
744 continue;
17d7904d 745 if (sc->splitmic) {
be2864cf
JM		 746 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
747 continue;
748 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
749 continue;
750 }
751
17d7904d 752 if (!test_bit(i, sc->keymap))
6ace2891
JM		 753 return i; /* Found a free slot for a key */
754 }
755
756 /* No free slot found */
757 return -1;
f078f209
LR		 758}
759
760static int ath_key_config(struct ath_softc *sc,
3f53dd64 761 struct ieee80211_vif *vif,
dc822b5d 762 struct ieee80211_sta *sta,
f078f209
LR		 763 struct ieee80211_key_conf *key)
764{
f078f209
LR		 765 struct ath9k_keyval hk;
766 const u8 *mac = NULL;
767 int ret = 0;
6ace2891 768 int idx;
f078f209
LR		 769
770 memset(&hk, 0, sizeof(hk));
771
772 switch (key->alg) {
773 case ALG_WEP:
774 hk.kv_type = ATH9K_CIPHER_WEP;
775 break;
776 case ALG_TKIP:
777 hk.kv_type = ATH9K_CIPHER_TKIP;
778 break;
779 case ALG_CCMP:
780 hk.kv_type = ATH9K_CIPHER_AES_CCM;
781 break;
782 default:
ca470b29 783 return -EOPNOTSUPP;
f078f209
LR		 784 }
785
6ace2891 786 hk.kv_len = key->keylen;
f078f209
LR		 787 memcpy(hk.kv_val, key->key, key->keylen);
788
6ace2891
JM		 789 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
790 /* For now, use the default keys for broadcast keys. This may
791 * need to change with virtual interfaces. */
792 idx = key->keyidx;
793 } else if (key->keyidx) {
dc822b5d
JB		 794 if (WARN_ON(!sta))
795 return -EOPNOTSUPP;
796 mac = sta->addr;
797
6ace2891
JM		 798 if (vif->type != NL80211_IFTYPE_AP) {
799 /* Only keyidx 0 should be used with unicast key, but
800 * allow this for client mode for now. */
801 idx = key->keyidx;
802 } else
803 return -EIO;
f078f209 804 } else {
dc822b5d
JB		 805 if (WARN_ON(!sta))
806 return -EOPNOTSUPP;
807 mac = sta->addr;
808
6ace2891
JM		 809 if (key->alg == ALG_TKIP)
810 idx = ath_reserve_key_cache_slot_tkip(sc);
811 else
812 idx = ath_reserve_key_cache_slot(sc);
813 if (idx < 0)
ca470b29 814 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 815 }
816
817 if (key->alg == ALG_TKIP)
3f53dd64
JM		 818 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
819 vif->type == NL80211_IFTYPE_AP);
f078f209 820 else
d216aaa6 821 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 822
823 if (!ret)
824 return -EIO;
825
17d7904d 826 set_bit(idx, sc->keymap);
6ace2891 827 if (key->alg == ALG_TKIP) {
17d7904d
S		 828 set_bit(idx + 64, sc->keymap);
829 if (sc->splitmic) {
830 set_bit(idx + 32, sc->keymap);
831 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 832 }
833 }
834
835 return idx;
f078f209
LR		 836}
837
838static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
839{
6ace2891
JM		 840 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
841 if (key->hw_key_idx < IEEE80211_WEP_NKID)
842 return;
843
17d7904d 844 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 845 if (key->alg != ALG_TKIP)
846 return;
f078f209 847
17d7904d
S		 848 clear_bit(key->hw_key_idx + 64, sc->keymap);
849 if (sc->splitmic) {
850 clear_bit(key->hw_key_idx + 32, sc->keymap);
851 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 852 }
f078f209
LR		 853}
854
eb2599ca
S		 855static void setup_ht_cap(struct ath_softc *sc,
856 struct ieee80211_sta_ht_cap *ht_info)
f078f209 857{
60653678
S		 858#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
859#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 860
d9fe60de
JB		 861 ht_info->ht_supported = true;
862 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
863 IEEE80211_HT_CAP_SM_PS |
864 IEEE80211_HT_CAP_SGI_40 |
865 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 866
60653678
S		 867 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
868 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
eb2599ca 869
d9fe60de
JB		 870 /* set up supported mcs set */
871 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
eb2599ca 872
17d7904d 873 switch(sc->rx_chainmask) {
eb2599ca
S		 874 case 1:
875 ht_info->mcs.rx_mask[0] = 0xff;
876 break;
3c457265 877 case 3:
eb2599ca
S		 878 case 5:
879 case 7:
880 default:
881 ht_info->mcs.rx_mask[0] = 0xff;
882 ht_info->mcs.rx_mask[1] = 0xff;
883 break;
884 }
885
d9fe60de 886 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 887}
888
8feceb67 889static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 890 struct ieee80211_vif *vif,
8feceb67 891 struct ieee80211_bss_conf *bss_conf)
f078f209 892{
17d7904d 893 struct ath_vif *avp = (void *)vif->drv_priv;
f078f209 894
8feceb67 895 if (bss_conf->assoc) {
094d05dc 896 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 897 bss_conf->aid, sc->curbssid);
f078f209 898
8feceb67 899 /* New association, store aid */
d97809db 900 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
17d7904d 901 sc->curaid = bss_conf->aid;
ba52da58 902 ath9k_hw_write_associd(sc);
8feceb67 903 }
f078f209 904
8feceb67 905 /* Configure the beacon */
2c3db3d5 906 ath_beacon_config(sc, vif);
f078f209 907
8feceb67 908 /* Reset rssi stats */
17d7904d
S		 909 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
910 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
911 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
912 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 913
6f255425 914 /* Start ANI */
17d7904d 915 mod_timer(&sc->ani.timer,
20977d3e 916 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
8feceb67 917 } else {
1ffb0610 918 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
17d7904d 919 sc->curaid = 0;
f078f209 920 }
8feceb67 921}
f078f209 922
8feceb67
VT		 923/********************************/
924/* LED functions */
925/********************************/
f078f209 926
f2bffa7e
VT		 927static void ath_led_blink_work(struct work_struct *work)
928{
929 struct ath_softc *sc = container_of(work, struct ath_softc,
930 ath_led_blink_work.work);
931
932 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
933 return;
85067c06
VT		 934
935 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
936 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
937 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
938 else
939 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
940 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e
VT		 941
942 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
943 (sc->sc_flags & SC_OP_LED_ON) ?
944 msecs_to_jiffies(sc->led_off_duration) :
945 msecs_to_jiffies(sc->led_on_duration));
946
85067c06
VT		 947 sc->led_on_duration = sc->led_on_cnt ?
948 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
949 ATH_LED_ON_DURATION_IDLE;
950 sc->led_off_duration = sc->led_off_cnt ?
951 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
952 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 953 sc->led_on_cnt = sc->led_off_cnt = 0;
954 if (sc->sc_flags & SC_OP_LED_ON)
955 sc->sc_flags &= ~SC_OP_LED_ON;
956 else
957 sc->sc_flags |= SC_OP_LED_ON;
958}
959
8feceb67
VT		 960static void ath_led_brightness(struct led_classdev *led_cdev,
961 enum led_brightness brightness)
962{
963 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
964 struct ath_softc *sc = led->sc;
f078f209 965
8feceb67
VT		 966 switch (brightness) {
967 case LED_OFF:
968 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 969 led->led_type == ATH_LED_RADIO) {
970 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
971 (led->led_type == ATH_LED_RADIO));
8feceb67 972 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 973 if (led->led_type == ATH_LED_RADIO)
974 sc->sc_flags &= ~SC_OP_LED_ON;
975 } else {
976 sc->led_off_cnt++;
977 }
8feceb67
VT		 978 break;
979 case LED_FULL:
f2bffa7e 980 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 981 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 982 queue_delayed_work(sc->hw->workqueue,
983 &sc->ath_led_blink_work, 0);
984 } else if (led->led_type == ATH_LED_RADIO) {
985 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
986 sc->sc_flags |= SC_OP_LED_ON;
987 } else {
988 sc->led_on_cnt++;
989 }
8feceb67
VT		 990 break;
991 default:
992 break;
f078f209 993 }
8feceb67 994}
f078f209 995
8feceb67
VT		 996static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
997 char *trigger)
998{
999 int ret;
f078f209 1000
8feceb67
VT		 1001 led->sc = sc;
1002 led->led_cdev.name = led->name;
1003 led->led_cdev.default_trigger = trigger;
1004 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1005
8feceb67
VT		 1006 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1007 if (ret)
1008 DPRINTF(sc, ATH_DBG_FATAL,
1009 "Failed to register led:%s", led->name);
1010 else
1011 led->registered = 1;
1012 return ret;
1013}
f078f209 1014
8feceb67
VT		 1015static void ath_unregister_led(struct ath_led *led)
1016{
1017 if (led->registered) {
1018 led_classdev_unregister(&led->led_cdev);
1019 led->registered = 0;
f078f209 1020 }
f078f209
LR		 1021}
1022
8feceb67 1023static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1024{
f2bffa7e 1025 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67
VT		 1026 ath_unregister_led(&sc->assoc_led);
1027 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1028 ath_unregister_led(&sc->tx_led);
1029 ath_unregister_led(&sc->rx_led);
1030 ath_unregister_led(&sc->radio_led);
1031 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1032}
f078f209 1033
8feceb67
VT		 1034static void ath_init_leds(struct ath_softc *sc)
1035{
1036 char *trigger;
1037 int ret;
f078f209 1038
8feceb67
VT		 1039 /* Configure gpio 1 for output */
1040 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1041 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1042 /* LED off, active low */
1043 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1044
f2bffa7e
VT		 1045 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1046
8feceb67
VT		 1047 trigger = ieee80211_get_radio_led_name(sc->hw);
1048 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1049 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1050 ret = ath_register_led(sc, &sc->radio_led, trigger);
1051 sc->radio_led.led_type = ATH_LED_RADIO;
1052 if (ret)
1053 goto fail;
7dcfdcd9 1054
8feceb67
VT		 1055 trigger = ieee80211_get_assoc_led_name(sc->hw);
1056 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1057 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1058 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1059 sc->assoc_led.led_type = ATH_LED_ASSOC;
1060 if (ret)
1061 goto fail;
f078f209 1062
8feceb67
VT		 1063 trigger = ieee80211_get_tx_led_name(sc->hw);
1064 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1065 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1066 ret = ath_register_led(sc, &sc->tx_led, trigger);
1067 sc->tx_led.led_type = ATH_LED_TX;
1068 if (ret)
1069 goto fail;
f078f209 1070
8feceb67
VT		 1071 trigger = ieee80211_get_rx_led_name(sc->hw);
1072 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1073 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1074 ret = ath_register_led(sc, &sc->rx_led, trigger);
1075 sc->rx_led.led_type = ATH_LED_RX;
1076 if (ret)
1077 goto fail;
f078f209 1078
8feceb67
VT		 1079 return;
1080
1081fail:
1082 ath_deinit_leds(sc);
f078f209
LR		 1083}
1084
7ec3e514 1085void ath_radio_enable(struct ath_softc *sc)
500c064d 1086{
cbe61d8a 1087 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1088 struct ieee80211_channel *channel = sc->hw->conf.channel;
1089 int r;
500c064d 1090
3cbb5dd7 1091 ath9k_ps_wakeup(sc);
d2f5b3a6 1092 ath9k_hw_configpcipowersave(ah, 0);
ae8d2858 1093
d2f5b3a6 1094 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1095 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1096 if (r) {
500c064d 1097 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1098 "Unable to reset channel %u (%uMhz) ",
1099 "reset status %u\n",
1100 channel->center_freq, r);
500c064d
VT		 1101 }
1102 spin_unlock_bh(&sc->sc_resetlock);
1103
1104 ath_update_txpow(sc);
1105 if (ath_startrecv(sc) != 0) {
1106 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1107 "Unable to restart recv logic\n");
500c064d
VT		 1108 return;
1109 }
1110
1111 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1112 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1113
1114 /* Re-Enable interrupts */
17d7904d 1115 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1116
1117 /* Enable LED */
1118 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1119 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1120 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1121
1122 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1123 ath9k_ps_restore(sc);
500c064d
VT		 1124}
1125
7ec3e514 1126void ath_radio_disable(struct ath_softc *sc)
500c064d 1127{
cbe61d8a 1128 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1129 struct ieee80211_channel *channel = sc->hw->conf.channel;
1130 int r;
500c064d 1131
3cbb5dd7 1132 ath9k_ps_wakeup(sc);
500c064d
VT		 1133 ieee80211_stop_queues(sc->hw);
1134
1135 /* Disable LED */
1136 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1137 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1138
1139 /* Disable interrupts */
1140 ath9k_hw_set_interrupts(ah, 0);
1141
043a0405 1142 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1143 ath_stoprecv(sc); /* turn off frame recv */
1144 ath_flushrecv(sc); /* flush recv queue */
1145
1146 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1147 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1148 if (r) {
500c064d 1149 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1150 "Unable to reset channel %u (%uMhz) "
ae8d2858
LR		 1151 "reset status %u\n",
1152 channel->center_freq, r);
500c064d
VT		 1153 }
1154 spin_unlock_bh(&sc->sc_resetlock);
1155
1156 ath9k_hw_phy_disable(ah);
d2f5b3a6 1157 ath9k_hw_configpcipowersave(ah, 1);
500c064d 1158 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3cbb5dd7 1159 ath9k_ps_restore(sc);
500c064d
VT		 1160}
1161
5077fd35
GJ		 1162#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1163
1164/*******************/
1165/* Rfkill */
1166/*******************/
1167
500c064d
VT		 1168static bool ath_is_rfkill_set(struct ath_softc *sc)
1169{
cbe61d8a 1170 struct ath_hw *ah = sc->sc_ah;
500c064d 1171
2660b81a
S		 1172 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1173 ah->rfkill_polarity;
500c064d
VT		 1174}
1175
1176/* h/w rfkill poll function */
1177static void ath_rfkill_poll(struct work_struct *work)
1178{
1179 struct ath_softc *sc = container_of(work, struct ath_softc,
1180 rf_kill.rfkill_poll.work);
1181 bool radio_on;
1182
1183 if (sc->sc_flags & SC_OP_INVALID)
1184 return;
1185
1186 radio_on = !ath_is_rfkill_set(sc);
1187
1188 /*
1189 * enable/disable radio only when there is a
1190 * state change in RF switch
1191 */
1192 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1193 enum rfkill_state state;
1194
1195 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1196 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1197 : RFKILL_STATE_HARD_BLOCKED;
1198 } else if (radio_on) {
1199 ath_radio_enable(sc);
1200 state = RFKILL_STATE_UNBLOCKED;
1201 } else {
1202 ath_radio_disable(sc);
1203 state = RFKILL_STATE_HARD_BLOCKED;
1204 }
1205
1206 if (state == RFKILL_STATE_HARD_BLOCKED)
1207 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1208 else
1209 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1210
1211 rfkill_force_state(sc->rf_kill.rfkill, state);
1212 }
1213
1214 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1215 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1216}
1217
1218/* s/w rfkill handler */
1219static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1220{
1221 struct ath_softc *sc = data;
1222
1223 switch (state) {
1224 case RFKILL_STATE_SOFT_BLOCKED:
1225 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1226 SC_OP_RFKILL_SW_BLOCKED)))
1227 ath_radio_disable(sc);
1228 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1229 return 0;
1230 case RFKILL_STATE_UNBLOCKED:
1231 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1232 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1233 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1234 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1235 "radio as it is disabled by h/w\n");
500c064d
VT		 1236 return -EPERM;
1237 }
1238 ath_radio_enable(sc);
1239 }
1240 return 0;
1241 default:
1242 return -EINVAL;
1243 }
1244}
1245
1246/* Init s/w rfkill */
1247static int ath_init_sw_rfkill(struct ath_softc *sc)
1248{
1249 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1250 RFKILL_TYPE_WLAN);
1251 if (!sc->rf_kill.rfkill) {
1252 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1253 return -ENOMEM;
1254 }
1255
1256 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
0818cb8a 1257 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
500c064d
VT		 1258 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1259 sc->rf_kill.rfkill->data = sc;
1260 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1261 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
500c064d
VT		 1262
1263 return 0;
1264}
1265
1266/* Deinitialize rfkill */
1267static void ath_deinit_rfkill(struct ath_softc *sc)
1268{
2660b81a 1269 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1270 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1271
1272 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1273 rfkill_unregister(sc->rf_kill.rfkill);
1274 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1275 sc->rf_kill.rfkill = NULL;
1276 }
1277}
9c84b797
S		 1278
1279static int ath_start_rfkill_poll(struct ath_softc *sc)
1280{
2660b81a 1281 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
9c84b797
S		 1282 queue_delayed_work(sc->hw->workqueue,
1283 &sc->rf_kill.rfkill_poll, 0);
1284
1285 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1286 if (rfkill_register(sc->rf_kill.rfkill)) {
1287 DPRINTF(sc, ATH_DBG_FATAL,
1288 "Unable to register rfkill\n");
1289 rfkill_free(sc->rf_kill.rfkill);
1290
1291 /* Deinitialize the device */
39c3c2f2 1292 ath_cleanup(sc);
9c84b797
S		 1293 return -EIO;
1294 } else {
1295 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1296 }
1297 }
1298
1299 return 0;
1300}
500c064d
VT		 1301#endif /* CONFIG_RFKILL */
1302
6baff7f9 1303void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1304{
1305 ath_detach(sc);
1306 free_irq(sc->irq, sc);
1307 ath_bus_cleanup(sc);
c52f33d0 1308 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1309 ieee80211_free_hw(sc->hw);
1310}
1311
6baff7f9 1312void ath_detach(struct ath_softc *sc)
f078f209 1313{
8feceb67 1314 struct ieee80211_hw *hw = sc->hw;
9c84b797 1315 int i = 0;
f078f209 1316
3cbb5dd7
VN		 1317 ath9k_ps_wakeup(sc);
1318
04bd4638 1319 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1320
e97275cb 1321#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1322 ath_deinit_rfkill(sc);
1323#endif
3fcdfb4b 1324 ath_deinit_leds(sc);
0e2dedf9 1325 cancel_work_sync(&sc->chan_work);
f98c3bd2 1326 cancel_delayed_work_sync(&sc->wiphy_work);
3fcdfb4b 1327
c52f33d0
JM		 1328 for (i = 0; i < sc->num_sec_wiphy; i++) {
1329 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1330 if (aphy == NULL)
1331 continue;
1332 sc->sec_wiphy[i] = NULL;
1333 ieee80211_unregister_hw(aphy->hw);
1334 ieee80211_free_hw(aphy->hw);
1335 }
3fcdfb4b 1336 ieee80211_unregister_hw(hw);
8feceb67
VT		 1337 ath_rx_cleanup(sc);
1338 ath_tx_cleanup(sc);
f078f209 1339
9c84b797
S		 1340 tasklet_kill(&sc->intr_tq);
1341 tasklet_kill(&sc->bcon_tasklet);
f078f209 1342
9c84b797
S		 1343 if (!(sc->sc_flags & SC_OP_INVALID))
1344 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1345
9c84b797
S		 1346 /* cleanup tx queues */
1347 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1348 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1349 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1350
1351 ath9k_hw_detach(sc->sc_ah);
826d2680 1352 ath9k_exit_debug(sc);
3cbb5dd7 1353 ath9k_ps_restore(sc);
f078f209
LR		 1354}
1355
e3bb249b
BC		 1356static int ath9k_reg_notifier(struct wiphy *wiphy,
1357 struct regulatory_request *request)
1358{
1359 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1360 struct ath_wiphy *aphy = hw->priv;
1361 struct ath_softc *sc = aphy->sc;
1362 struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1363
1364 return ath_reg_notifier_apply(wiphy, request, reg);
1365}
1366
ff37e337
S		 1367static int ath_init(u16 devid, struct ath_softc *sc)
1368{
cbe61d8a 1369 struct ath_hw *ah = NULL;
ff37e337
S		 1370 int status;
1371 int error = 0, i;
1372 int csz = 0;
1373
1374 /* XXX: hardware will not be ready until ath_open() being called */
1375 sc->sc_flags |= SC_OP_INVALID;
88b126af 1376
826d2680
S		 1377 if (ath9k_init_debug(sc) < 0)
1378 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337 1379
c52f33d0 1380 spin_lock_init(&sc->wiphy_lock);
ff37e337 1381 spin_lock_init(&sc->sc_resetlock);
6158425b 1382 spin_lock_init(&sc->sc_serial_rw);
aa33de09 1383 mutex_init(&sc->mutex);
ff37e337 1384 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1385 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1386 (unsigned long)sc);
1387
1388 /*
1389 * Cache line size is used to size and align various
1390 * structures used to communicate with the hardware.
1391 */
88d15707 1392 ath_read_cachesize(sc, &csz);
ff37e337 1393 /* XXX assert csz is non-zero */
17d7904d 1394 sc->cachelsz = csz << 2; /* convert to bytes */
ff37e337 1395
cbe61d8a 1396 ah = ath9k_hw_attach(devid, sc, &status);
ff37e337
S		 1397 if (ah == NULL) {
1398 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1399 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1400 error = -ENXIO;
1401 goto bad;
1402 }
1403 sc->sc_ah = ah;
1404
1405 /* Get the hardware key cache size. */
2660b81a 1406 sc->keymax = ah->caps.keycache_size;
17d7904d 1407 if (sc->keymax > ATH_KEYMAX) {
d8baa939 1408 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 1409 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1410 ATH_KEYMAX, sc->keymax);
1411 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1412 }
1413
1414 /*
1415 * Reset the key cache since some parts do not
1416 * reset the contents on initial power up.
1417 */
17d7904d 1418 for (i = 0; i < sc->keymax; i++)
ff37e337 1419 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1420
e3bb249b
BC		 1421 if (ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1422 ath9k_reg_notifier))
ff37e337
S		 1423 goto bad;
1424
1425 /* default to MONITOR mode */
2660b81a 1426 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1427
ff37e337
S		 1428 /* Setup rate tables */
1429
1430 ath_rate_attach(sc);
1431 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1432 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1433
1434 /*
1435 * Allocate hardware transmit queues: one queue for
1436 * beacon frames and one data queue for each QoS
1437 * priority. Note that the hal handles reseting
1438 * these queues at the needed time.
1439 */
b77f483f
S		 1440 sc->beacon.beaconq = ath_beaconq_setup(ah);
1441 if (sc->beacon.beaconq == -1) {
ff37e337 1442 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1443 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1444 error = -EIO;
1445 goto bad2;
1446 }
b77f483f
S		 1447 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1448 if (sc->beacon.cabq == NULL) {
ff37e337 1449 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1450 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1451 error = -EIO;
1452 goto bad2;
1453 }
1454
17d7904d 1455 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1456 ath_cabq_update(sc);
1457
b77f483f
S		 1458 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1459 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1460
1461 /* Setup data queues */
1462 /* NB: ensure BK queue is the lowest priority h/w queue */
1463 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1464 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1465 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1466 error = -EIO;
1467 goto bad2;
1468 }
1469
1470 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1471 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1472 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1473 error = -EIO;
1474 goto bad2;
1475 }
1476 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1477 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1478 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1479 error = -EIO;
1480 goto bad2;
1481 }
1482 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1483 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1484 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1485 error = -EIO;
1486 goto bad2;
1487 }
1488
1489 /* Initializes the noise floor to a reasonable default value.
1490 * Later on this will be updated during ANI processing. */
1491
17d7904d
S		 1492 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1493 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1494
1495 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1496 ATH9K_CIPHER_TKIP, NULL)) {
1497 /*
1498 * Whether we should enable h/w TKIP MIC.
1499 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1500 * report WMM capable, so it's always safe to turn on
1501 * TKIP MIC in this case.
1502 */
1503 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1504 0, 1, NULL);
1505 }
1506
1507 /*
1508 * Check whether the separate key cache entries
1509 * are required to handle both tx+rx MIC keys.
1510 * With split mic keys the number of stations is limited
1511 * to 27 otherwise 59.
1512 */
1513 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1514 ATH9K_CIPHER_TKIP, NULL)
1515 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1516 ATH9K_CIPHER_MIC, NULL)
1517 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1518 0, NULL))
17d7904d 1519 sc->splitmic = 1;
ff37e337
S		 1520
1521 /* turn on mcast key search if possible */
1522 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1523 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1524 1, NULL);
1525
17d7904d 1526 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1527
1528 /* 11n Capabilities */
2660b81a 1529 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1530 sc->sc_flags |= SC_OP_TXAGGR;
1531 sc->sc_flags |= SC_OP_RXAGGR;
1532 }
1533
2660b81a
S		 1534 sc->tx_chainmask = ah->caps.tx_chainmask;
1535 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1536
1537 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1538 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1539
8ca21f01 1540 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1541 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1542
b77f483f 1543 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1544
1545 /* initialize beacon slots */
c52f33d0 1546 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1547 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1548 sc->beacon.bslot_aphy[i] = NULL;
1549 }
ff37e337 1550
ff37e337
S		 1551 /* setup channels and rates */
1552
5f8e077c 1553 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1554 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1555 sc->rates[IEEE80211_BAND_2GHZ];
1556 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1557 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1558 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1559
2660b81a 1560 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1561 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1562 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1563 sc->rates[IEEE80211_BAND_5GHZ];
1564 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1565 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1566 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1567 }
1568
2660b81a 1569 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
c97c92d9
VT		 1570 ath9k_hw_btcoex_enable(sc->sc_ah);
1571
ff37e337
S		 1572 return 0;
1573bad2:
1574 /* cleanup tx queues */
1575 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1576 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1577 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1578bad:
1579 if (ah)
1580 ath9k_hw_detach(ah);
40b130a9 1581 ath9k_exit_debug(sc);
ff37e337
S		 1582
1583 return error;
1584}
1585
c52f33d0 1586void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1587{
9c84b797
S		 1588 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1589 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1590 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1591 IEEE80211_HW_AMPDU_AGGREGATION |
1592 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1593 IEEE80211_HW_PS_NULLFUNC_STACK |
1594 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1595
b3bd89ce 1596 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1597 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1598
9c84b797
S		 1599 hw->wiphy->interface_modes =
1600 BIT(NL80211_IFTYPE_AP) |
1601 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1602 BIT(NL80211_IFTYPE_ADHOC) |
1603 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1604
8feceb67 1605 hw->queues = 4;
e63835b0 1606 hw->max_rates = 4;
171387ef 1607 hw->channel_change_time = 5000;
465ca84d 1608 hw->max_listen_interval = 10;
e63835b0 1609 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1610 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1611 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1612
8feceb67 1613 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1614
c52f33d0
JM		 1615 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1616 &sc->sbands[IEEE80211_BAND_2GHZ];
1617 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1618 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1619 &sc->sbands[IEEE80211_BAND_5GHZ];
1620}
1621
1622int ath_attach(u16 devid, struct ath_softc *sc)
1623{
1624 struct ieee80211_hw *hw = sc->hw;
c52f33d0 1625 int error = 0, i;
3a702e49 1626 struct ath_regulatory *reg;
c52f33d0
JM		 1627
1628 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1629
1630 error = ath_init(devid, sc);
1631 if (error != 0)
1632 return error;
1633
c02cf373
BC		 1634 reg = &sc->sc_ah->regulatory;
1635
c52f33d0
JM		 1636 /* get mac address from hardware and set in mac80211 */
1637
1638 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1639
1640 ath_set_hw_capab(sc, hw);
1641
2660b81a 1642 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1643 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1644 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1645 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1646 }
1647
db93e7b5
SB		 1648 /* initialize tx/rx engine */
1649 error = ath_tx_init(sc, ATH_TXBUF);
1650 if (error != 0)
40b130a9 1651 goto error_attach;
8feceb67 1652
db93e7b5
SB		 1653 error = ath_rx_init(sc, ATH_RXBUF);
1654 if (error != 0)
40b130a9 1655 goto error_attach;
8feceb67 1656
e97275cb 1657#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d 1658 /* Initialze h/w Rfkill */
2660b81a 1659 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1660 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1661
1662 /* Initialize s/w rfkill */
40b130a9
VT		 1663 error = ath_init_sw_rfkill(sc);
1664 if (error)
1665 goto error_attach;
500c064d
VT		 1666#endif
1667
0e2dedf9 1668 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1669 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1670 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1671
db93e7b5 1672 error = ieee80211_register_hw(hw);
8feceb67 1673
3a702e49 1674 if (!ath_is_world_regd(reg)) {
c02cf373 1675 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1676 if (error)
1677 goto error_attach;
1678 }
5f8e077c 1679
db93e7b5
SB		 1680 /* Initialize LED control */
1681 ath_init_leds(sc);
8feceb67 1682
5f8e077c 1683
8feceb67 1684 return 0;
40b130a9
VT		 1685
1686error_attach:
1687 /* cleanup tx queues */
1688 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1689 if (ATH_TXQ_SETUP(sc, i))
1690 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1691
1692 ath9k_hw_detach(sc->sc_ah);
1693 ath9k_exit_debug(sc);
1694
8feceb67 1695 return error;
f078f209
LR		 1696}
1697
ff37e337
S		 1698int ath_reset(struct ath_softc *sc, bool retry_tx)
1699{
cbe61d8a 1700 struct ath_hw *ah = sc->sc_ah;
030bb495 1701 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1702 int r;
ff37e337
S		 1703
1704 ath9k_hw_set_interrupts(ah, 0);
043a0405 1705 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1706 ath_stoprecv(sc);
1707 ath_flushrecv(sc);
1708
1709 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1710 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1711 if (r)
ff37e337 1712 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1713 "Unable to reset hardware; reset status %u\n", r);
ff37e337
S		 1714 spin_unlock_bh(&sc->sc_resetlock);
1715
1716 if (ath_startrecv(sc) != 0)
04bd4638 1717 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1718
1719 /*
1720 * We may be doing a reset in response to a request
1721 * that changes the channel so update any state that
1722 * might change as a result.
1723 */
ce111bad 1724 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1725
1726 ath_update_txpow(sc);
1727
1728 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1729 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1730
17d7904d 1731 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1732
1733 if (retry_tx) {
1734 int i;
1735 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1736 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1737 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1738 ath_txq_schedule(sc, &sc->tx.txq[i]);
1739 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1740 }
1741 }
1742 }
1743
ae8d2858 1744 return r;
ff37e337
S		 1745}
1746
1747/*
1748 * This function will allocate both the DMA descriptor structure, and the
1749 * buffers it contains. These are used to contain the descriptors used
1750 * by the system.
1751*/
1752int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1753 struct list_head *head, const char *name,
1754 int nbuf, int ndesc)
1755{
1756#define DS2PHYS(_dd, _ds) \
1757 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1758#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1759#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1760
1761 struct ath_desc *ds;
1762 struct ath_buf *bf;
1763 int i, bsize, error;
1764
04bd4638
S		 1765 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1766 name, nbuf, ndesc);
ff37e337 1767
b03a9db9 1768 INIT_LIST_HEAD(head);
ff37e337
S		 1769 /* ath_desc must be a multiple of DWORDs */
1770 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1771 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1772 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1773 error = -ENOMEM;
1774 goto fail;
1775 }
1776
ff37e337
S		 1777 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1778
1779 /*
1780 * Need additional DMA memory because we can't use
1781 * descriptors that cross the 4K page boundary. Assume
1782 * one skipped descriptor per 4K page.
1783 */
2660b81a 1784 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1785 u32 ndesc_skipped =
1786 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1787 u32 dma_len;
1788
1789 while (ndesc_skipped) {
1790 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1791 dd->dd_desc_len += dma_len;
1792
1793 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1794 };
1795 }
1796
1797 /* allocate descriptors */
7da3c55c 1798 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 1799 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 1800 if (dd->dd_desc == NULL) {
1801 error = -ENOMEM;
1802 goto fail;
1803 }
1804 ds = dd->dd_desc;
04bd4638 1805 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
ae459af1 1806 name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1807 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1808
1809 /* allocate buffers */
1810 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 1811 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 1812 if (bf == NULL) {
1813 error = -ENOMEM;
1814 goto fail2;
1815 }
ff37e337
S		 1816 dd->dd_bufptr = bf;
1817
ff37e337
S		 1818 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1819 bf->bf_desc = ds;
1820 bf->bf_daddr = DS2PHYS(dd, ds);
1821
2660b81a 1822 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1823 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1824 /*
1825 * Skip descriptor addresses which can cause 4KB
1826 * boundary crossing (addr + length) with a 32 dword
1827 * descriptor fetch.
1828 */
1829 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1830 ASSERT((caddr_t) bf->bf_desc <
1831 ((caddr_t) dd->dd_desc +
1832 dd->dd_desc_len));
1833
1834 ds += ndesc;
1835 bf->bf_desc = ds;
1836 bf->bf_daddr = DS2PHYS(dd, ds);
1837 }
1838 }
1839 list_add_tail(&bf->list, head);
1840 }
1841 return 0;
1842fail2:
7da3c55c
GJ		 1843 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1844 dd->dd_desc_paddr);
ff37e337
S		 1845fail:
1846 memset(dd, 0, sizeof(*dd));
1847 return error;
1848#undef ATH_DESC_4KB_BOUND_CHECK
1849#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1850#undef DS2PHYS
1851}
1852
1853void ath_descdma_cleanup(struct ath_softc *sc,
1854 struct ath_descdma *dd,
1855 struct list_head *head)
1856{
7da3c55c
GJ		 1857 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1858 dd->dd_desc_paddr);
ff37e337
S		 1859
1860 INIT_LIST_HEAD(head);
1861 kfree(dd->dd_bufptr);
1862 memset(dd, 0, sizeof(*dd));
1863}
1864
1865int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1866{
1867 int qnum;
1868
1869 switch (queue) {
1870 case 0:
b77f483f 1871 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1872 break;
1873 case 1:
b77f483f 1874 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1875 break;
1876 case 2:
b77f483f 1877 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1878 break;
1879 case 3:
b77f483f 1880 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1881 break;
1882 default:
b77f483f 1883 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1884 break;
1885 }
1886
1887 return qnum;
1888}
1889
1890int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1891{
1892 int qnum;
1893
1894 switch (queue) {
1895 case ATH9K_WME_AC_VO:
1896 qnum = 0;
1897 break;
1898 case ATH9K_WME_AC_VI:
1899 qnum = 1;
1900 break;
1901 case ATH9K_WME_AC_BE:
1902 qnum = 2;
1903 break;
1904 case ATH9K_WME_AC_BK:
1905 qnum = 3;
1906 break;
1907 default:
1908 qnum = -1;
1909 break;
1910 }
1911
1912 return qnum;
1913}
1914
5f8e077c
LR		 1915/* XXX: Remove me once we don't depend on ath9k_channel for all
1916 * this redundant data */
0e2dedf9
JM		 1917void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1918 struct ath9k_channel *ichan)
5f8e077c 1919{
5f8e077c
LR		 1920 struct ieee80211_channel *chan = hw->conf.channel;
1921 struct ieee80211_conf *conf = &hw->conf;
1922
1923 ichan->channel = chan->center_freq;
1924 ichan->chan = chan;
1925
1926 if (chan->band == IEEE80211_BAND_2GHZ) {
1927 ichan->chanmode = CHANNEL_G;
1928 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1929 } else {
1930 ichan->chanmode = CHANNEL_A;
1931 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1932 }
1933
1934 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1935
1936 if (conf_is_ht(conf)) {
1937 if (conf_is_ht40(conf))
1938 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1939
1940 ichan->chanmode = ath_get_extchanmode(sc, chan,
1941 conf->channel_type);
1942 }
1943}
1944
ff37e337
S		 1945/**********************/
1946/* mac80211 callbacks */
1947/**********************/
1948
8feceb67 1949static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1950{
bce048d7
JM		 1951 struct ath_wiphy *aphy = hw->priv;
1952 struct ath_softc *sc = aphy->sc;
8feceb67 1953 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1954 struct ath9k_channel *init_channel;
ae8d2858 1955 int r, pos;
f078f209 1956
04bd4638
S		 1957 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1958 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1959
141b38b6
S		 1960 mutex_lock(&sc->mutex);
1961
9580a222
JM		 1962 if (ath9k_wiphy_started(sc)) {
1963 if (sc->chan_idx == curchan->hw_value) {
1964 /*
1965 * Already on the operational channel, the new wiphy
1966 * can be marked active.
1967 */
1968 aphy->state = ATH_WIPHY_ACTIVE;
1969 ieee80211_wake_queues(hw);
1970 } else {
1971 /*
1972 * Another wiphy is on another channel, start the new
1973 * wiphy in paused state.
1974 */
1975 aphy->state = ATH_WIPHY_PAUSED;
1976 ieee80211_stop_queues(hw);
1977 }
1978 mutex_unlock(&sc->mutex);
1979 return 0;
1980 }
1981 aphy->state = ATH_WIPHY_ACTIVE;
1982
8feceb67 1983 /* setup initial channel */
f078f209 1984
5f8e077c 1985 pos = curchan->hw_value;
f078f209 1986
0e2dedf9 1987 sc->chan_idx = pos;
2660b81a 1988 init_channel = &sc->sc_ah->channels[pos];
0e2dedf9 1989 ath9k_update_ichannel(sc, hw, init_channel);
ff37e337
S		 1990
1991 /* Reset SERDES registers */
1992 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1993
1994 /*
1995 * The basic interface to setting the hardware in a good
1996 * state is ``reset''. On return the hardware is known to
1997 * be powered up and with interrupts disabled. This must
1998 * be followed by initialization of the appropriate bits
1999 * and then setup of the interrupt mask.
2000 */
2001 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 2002 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
2003 if (r) {
ff37e337 2004 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 2005 "Unable to reset hardware; reset status %u "
2006 "(freq %u MHz)\n", r,
2007 curchan->center_freq);
ff37e337 2008 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 2009 goto mutex_unlock;
ff37e337
S		 2010 }
2011 spin_unlock_bh(&sc->sc_resetlock);
2012
2013 /*
2014 * This is needed only to setup initial state
2015 * but it's best done after a reset.
2016 */
2017 ath_update_txpow(sc);
8feceb67 2018
ff37e337
S		 2019 /*
2020 * Setup the hardware after reset:
2021 * The receive engine is set going.
2022 * Frame transmit is handled entirely
2023 * in the frame output path; there's nothing to do
2024 * here except setup the interrupt mask.
2025 */
2026 if (ath_startrecv(sc) != 0) {
1ffb0610 2027 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
141b38b6
S		 2028 r = -EIO;
2029 goto mutex_unlock;
f078f209 2030 }
8feceb67 2031
ff37e337 2032 /* Setup our intr mask. */
17d7904d 2033 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 2034 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2035 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2036
2660b81a 2037 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2038 sc->imask |= ATH9K_INT_GTT;
ff37e337 2039
2660b81a 2040 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2041 sc->imask |= ATH9K_INT_CST;
ff37e337 2042
ce111bad 2043 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2044
2045 sc->sc_flags &= ~SC_OP_INVALID;
2046
2047 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 2048 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2049 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337 2050
bce048d7 2051 ieee80211_wake_queues(hw);
ff37e337 2052
e97275cb 2053#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 2054 r = ath_start_rfkill_poll(sc);
500c064d 2055#endif
141b38b6
S		 2056
2057mutex_unlock:
2058 mutex_unlock(&sc->mutex);
2059
ae8d2858 2060 return r;
f078f209
LR		 2061}
2062
8feceb67
VT		 2063static int ath9k_tx(struct ieee80211_hw *hw,
2064 struct sk_buff *skb)
f078f209 2065{
528f0c6b 2066 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 2067 struct ath_wiphy *aphy = hw->priv;
2068 struct ath_softc *sc = aphy->sc;
528f0c6b 2069 struct ath_tx_control txctl;
8feceb67 2070 int hdrlen, padsize;
528f0c6b 2071
8089cc47 2072 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
ee166a0e
JM		 2073 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2074 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2075 goto exit;
2076 }
2077
528f0c6b 2078 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2079
8feceb67
VT		 2080 /*
2081 * As a temporary workaround, assign seq# here; this will likely need
2082 * to be cleaned up to work better with Beacon transmission and virtual
2083 * BSSes.
2084 */
2085 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2086 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2087 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2088 sc->tx.seq_no += 0x10;
8feceb67 2089 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2090 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2091 }
f078f209 2092
8feceb67
VT		 2093 /* Add the padding after the header if this is not already done */
2094 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2095 if (hdrlen & 3) {
2096 padsize = hdrlen % 4;
2097 if (skb_headroom(skb) < padsize)
2098 return -1;
2099 skb_push(skb, padsize);
2100 memmove(skb->data, skb->data + padsize, hdrlen);
2101 }
2102
528f0c6b
S		 2103 /* Check if a tx queue is available */
2104
2105 txctl.txq = ath_test_get_txq(sc, skb);
2106 if (!txctl.txq)
2107 goto exit;
2108
04bd4638 2109 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2110
c52f33d0 2111 if (ath_tx_start(hw, skb, &txctl) != 0) {
04bd4638 2112 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2113 goto exit;
8feceb67
VT		 2114 }
2115
528f0c6b
S		 2116 return 0;
2117exit:
2118 dev_kfree_skb_any(skb);
8feceb67 2119 return 0;
f078f209
LR		 2120}
2121
8feceb67 2122static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2123{
bce048d7
JM		 2124 struct ath_wiphy *aphy = hw->priv;
2125 struct ath_softc *sc = aphy->sc;
f078f209 2126
9580a222
JM		 2127 aphy->state = ATH_WIPHY_INACTIVE;
2128
9c84b797 2129 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2130 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2131 return;
2132 }
8feceb67 2133
141b38b6 2134 mutex_lock(&sc->mutex);
ff37e337 2135
bce048d7 2136 ieee80211_stop_queues(hw);
ff37e337 2137
9580a222
JM		 2138 if (ath9k_wiphy_started(sc)) {
2139 mutex_unlock(&sc->mutex);
2140 return; /* another wiphy still in use */
2141 }
2142
ff37e337
S		 2143 /* make sure h/w will not generate any interrupt
2144 * before setting the invalid flag. */
2145 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2146
2147 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2148 ath_drain_all_txq(sc, false);
ff37e337
S		 2149 ath_stoprecv(sc);
2150 ath9k_hw_phy_disable(sc->sc_ah);
2151 } else
b77f483f 2152 sc->rx.rxlink = NULL;
ff37e337
S		 2153
2154#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a 2155 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
ff37e337
S		 2156 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2157#endif
2158 /* disable HAL and put h/w to sleep */
2159 ath9k_hw_disable(sc->sc_ah);
2160 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2161
2162 sc->sc_flags |= SC_OP_INVALID;
500c064d 2163
141b38b6
S		 2164 mutex_unlock(&sc->mutex);
2165
04bd4638 2166 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2167}
2168
8feceb67
VT		 2169static int ath9k_add_interface(struct ieee80211_hw *hw,
2170 struct ieee80211_if_init_conf *conf)
f078f209 2171{
bce048d7
JM		 2172 struct ath_wiphy *aphy = hw->priv;
2173 struct ath_softc *sc = aphy->sc;
17d7904d 2174 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2175 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2176 int ret = 0;
8feceb67 2177
141b38b6
S		 2178 mutex_lock(&sc->mutex);
2179
8ca21f01
JM		 2180 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2181 sc->nvifs > 0) {
2182 ret = -ENOBUFS;
2183 goto out;
2184 }
2185
8feceb67 2186 switch (conf->type) {
05c914fe 2187 case NL80211_IFTYPE_STATION:
d97809db 2188 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2189 break;
05c914fe 2190 case NL80211_IFTYPE_ADHOC:
05c914fe 2191 case NL80211_IFTYPE_AP:
9cb5412b 2192 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2193 if (sc->nbcnvifs >= ATH_BCBUF) {
2194 ret = -ENOBUFS;
2195 goto out;
2196 }
9cb5412b 2197 ic_opmode = conf->type;
f078f209
LR		 2198 break;
2199 default:
2200 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2201 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2202 ret = -EOPNOTSUPP;
2203 goto out;
f078f209
LR		 2204 }
2205
17d7904d 2206 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2207
17d7904d 2208 /* Set the VIF opmode */
5640b08e
S		 2209 avp->av_opmode = ic_opmode;
2210 avp->av_bslot = -1;
2211
2c3db3d5 2212 sc->nvifs++;
8ca21f01
JM		 2213
2214 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2215 ath9k_set_bssid_mask(hw);
2216
2c3db3d5
JM		 2217 if (sc->nvifs > 1)
2218 goto out; /* skip global settings for secondary vif */
2219
b238e90e 2220 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2221 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2222 sc->sc_flags |= SC_OP_TSF_RESET;
2223 }
5640b08e 2224
5640b08e 2225 /* Set the device opmode */
2660b81a 2226 sc->sc_ah->opmode = ic_opmode;
5640b08e 2227
4e30ffa2
VN		 2228 /*
2229 * Enable MIB interrupts when there are hardware phy counters.
2230 * Note we only do this (at the moment) for station mode.
2231 */
4af9cf4f 2232 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2233 (conf->type == NL80211_IFTYPE_ADHOC) ||
2234 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
4af9cf4f
S		 2235 if (ath9k_hw_phycounters(sc->sc_ah))
2236 sc->imask |= ATH9K_INT_MIB;
2237 sc->imask |= ATH9K_INT_TSFOOR;
2238 }
2239
17d7904d 2240 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2241
6f255425
LR		 2242 if (conf->type == NL80211_IFTYPE_AP) {
2243 /* TODO: is this a suitable place to start ANI for AP mode? */
2244 /* Start ANI */
17d7904d 2245 mod_timer(&sc->ani.timer,
6f255425
LR		 2246 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2247 }
2248
2c3db3d5 2249out:
141b38b6 2250 mutex_unlock(&sc->mutex);
2c3db3d5 2251 return ret;
f078f209
LR		 2252}
2253
8feceb67
VT		 2254static void ath9k_remove_interface(struct ieee80211_hw *hw,
2255 struct ieee80211_if_init_conf *conf)
f078f209 2256{
bce048d7
JM		 2257 struct ath_wiphy *aphy = hw->priv;
2258 struct ath_softc *sc = aphy->sc;
17d7904d 2259 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2260 int i;
f078f209 2261
04bd4638 2262 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2263
141b38b6
S		 2264 mutex_lock(&sc->mutex);
2265
6f255425 2266 /* Stop ANI */
17d7904d 2267 del_timer_sync(&sc->ani.timer);
580f0b8a 2268
8feceb67 2269 /* Reclaim beacon resources */
9cb5412b
PE		 2270 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2271 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2272 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2273 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2274 ath_beacon_return(sc, avp);
580f0b8a 2275 }
f078f209 2276
8feceb67 2277 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2278
2c3db3d5
JM		 2279 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2280 if (sc->beacon.bslot[i] == conf->vif) {
2281 printk(KERN_DEBUG "%s: vif had allocated beacon "
2282 "slot\n", __func__);
2283 sc->beacon.bslot[i] = NULL;
c52f33d0 2284 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2285 }
2286 }
2287
17d7904d 2288 sc->nvifs--;
141b38b6
S		 2289
2290 mutex_unlock(&sc->mutex);
f078f209
LR		 2291}
2292
e8975581 2293static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2294{
bce048d7
JM		 2295 struct ath_wiphy *aphy = hw->priv;
2296 struct ath_softc *sc = aphy->sc;
e8975581 2297 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2298 struct ath_hw *ah = sc->sc_ah;
f078f209 2299
aa33de09 2300 mutex_lock(&sc->mutex);
141b38b6 2301
3cbb5dd7
VN		 2302 if (changed & IEEE80211_CONF_CHANGE_PS) {
2303 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2304 if (!(ah->caps.hw_caps &
2305 ATH9K_HW_CAP_AUTOSLEEP)) {
2306 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2307 sc->imask |= ATH9K_INT_TIM_TIMER;
2308 ath9k_hw_set_interrupts(sc->sc_ah,
2309 sc->imask);
2310 }
2311 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2312 }
3cbb5dd7
VN		 2313 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2314 } else {
2315 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8782b41d
VN		 2316 if (!(ah->caps.hw_caps &
2317 ATH9K_HW_CAP_AUTOSLEEP)) {
2318 ath9k_hw_setrxabort(sc->sc_ah, 0);
2319 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2320 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2321 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2322 ath9k_hw_set_interrupts(sc->sc_ah,
2323 sc->imask);
2324 }
3cbb5dd7
VN		 2325 }
2326 }
2327 }
2328
4797938c 2329 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2330 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2331 int pos = curchan->hw_value;
ae5eb026 2332
0e2dedf9
JM		 2333 aphy->chan_idx = pos;
2334 aphy->chan_is_ht = conf_is_ht(conf);
2335
8089cc47
JM		 2336 if (aphy->state == ATH_WIPHY_SCAN ||
2337 aphy->state == ATH_WIPHY_ACTIVE)
2338 ath9k_wiphy_pause_all_forced(sc, aphy);
2339 else {
2340 /*
2341 * Do not change operational channel based on a paused
2342 * wiphy changes.
2343 */
2344 goto skip_chan_change;
2345 }
0e2dedf9 2346
04bd4638
S		 2347 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2348 curchan->center_freq);
f078f209 2349
5f8e077c 2350 /* XXX: remove me eventualy */
0e2dedf9 2351 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2352
ecf70441 2353 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2354
0e2dedf9 2355 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2356 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2357 mutex_unlock(&sc->mutex);
e11602b7
S		 2358 return -EINVAL;
2359 }
094d05dc 2360 }
f078f209 2361
8089cc47 2362skip_chan_change:
5c020dc6 2363 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2364 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2365
b238e90e
S		 2366 /*
2367 * The HW TSF has to be reset when the beacon interval changes.
2368 * We set the flag here, and ath_beacon_config_ap() would take this
2369 * into account when it gets called through the subsequent
2370 * config_interface() call - with IFCC_BEACON in the changed field.
2371 */
2372
2373 if (changed & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
2374 sc->sc_flags |= SC_OP_TSF_RESET;
2375
aa33de09 2376 mutex_unlock(&sc->mutex);
141b38b6 2377
f078f209
LR		 2378 return 0;
2379}
2380
8feceb67
VT		 2381static int ath9k_config_interface(struct ieee80211_hw *hw,
2382 struct ieee80211_vif *vif,
2383 struct ieee80211_if_conf *conf)
c83be688 2384{
bce048d7
JM		 2385 struct ath_wiphy *aphy = hw->priv;
2386 struct ath_softc *sc = aphy->sc;
cbe61d8a 2387 struct ath_hw *ah = sc->sc_ah;
17d7904d 2388 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67
VT		 2389 u32 rfilt = 0;
2390 int error, i;
c83be688 2391
2554935b
S		 2392 mutex_lock(&sc->mutex);
2393
8feceb67
VT		 2394 /* TODO: Need to decide which hw opmode to use for multi-interface
2395 * cases */
05c914fe 2396 if (vif->type == NL80211_IFTYPE_AP &&
2660b81a
S		 2397 ah->opmode != NL80211_IFTYPE_AP) {
2398 ah->opmode = NL80211_IFTYPE_STATION;
8feceb67 2399 ath9k_hw_setopmode(ah);
ba52da58
S		 2400 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2401 sc->curaid = 0;
2402 ath9k_hw_write_associd(sc);
8feceb67
VT		 2403 /* Request full reset to get hw opmode changed properly */
2404 sc->sc_flags |= SC_OP_FULL_RESET;
2405 }
c83be688 2406
8feceb67
VT		 2407 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2408 !is_zero_ether_addr(conf->bssid)) {
2409 switch (vif->type) {
05c914fe
JB		 2410 case NL80211_IFTYPE_STATION:
2411 case NL80211_IFTYPE_ADHOC:
9cb5412b 2412 case NL80211_IFTYPE_MESH_POINT:
8feceb67 2413 /* Set BSSID */
17d7904d 2414 memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
f0ed85c6 2415 memcpy(avp->bssid, conf->bssid, ETH_ALEN);
17d7904d 2416 sc->curaid = 0;
ba52da58 2417 ath9k_hw_write_associd(sc);
c83be688 2418
8feceb67 2419 /* Set aggregation protection mode parameters */
17d7904d 2420 sc->config.ath_aggr_prot = 0;
c83be688 2421
8feceb67 2422 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2423 "RX filter 0x%x bssid %pM aid 0x%x\n",
17d7904d 2424 rfilt, sc->curbssid, sc->curaid);
c83be688 2425
8feceb67
VT		 2426 /* need to reconfigure the beacon */
2427 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 2428
8feceb67
VT		 2429 break;
2430 default:
2431 break;
2432 }
2433 }
c83be688 2434
1f7d6cbf 2435 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
9cb5412b
PE		 2436 (vif->type == NL80211_IFTYPE_AP) ||
2437 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
1f7d6cbf
S		 2438 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2439 (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2440 conf->enable_beacon)) {
2441 /*
2442 * Allocate and setup the beacon frame.
2443 *
2444 * Stop any previous beacon DMA. This may be
2445 * necessary, for example, when an ibss merge
2446 * causes reconfiguration; we may be called
2447 * with beacon transmission active.
2448 */
2449 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
c83be688 2450
c52f33d0 2451 error = ath_beacon_alloc(aphy, vif);
2554935b
S		 2452 if (error != 0) {
2453 mutex_unlock(&sc->mutex);
1f7d6cbf 2454 return error;
2554935b 2455 }
c83be688 2456
2c3db3d5 2457 ath_beacon_config(sc, vif);
1f7d6cbf 2458 }
8feceb67 2459 }
c83be688 2460
8feceb67 2461 /* Check for WLAN_CAPABILITY_PRIVACY ? */
d97809db 2462 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT		 2463 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2464 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2465 ath9k_hw_keysetmac(sc->sc_ah,
2466 (u16)i,
17d7904d 2467 sc->curbssid);
8feceb67 2468 }
c83be688 2469
8feceb67 2470 /* Only legacy IBSS for now */
05c914fe 2471 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 2472 ath_update_chainmask(sc, 0);
f078f209 2473
2554935b
S		 2474 mutex_unlock(&sc->mutex);
2475
8feceb67
VT		 2476 return 0;
2477}
f078f209 2478
8feceb67
VT		 2479#define SUPPORTED_FILTERS \
2480 (FIF_PROMISC_IN_BSS | \
2481 FIF_ALLMULTI | \
2482 FIF_CONTROL | \
2483 FIF_OTHER_BSS | \
2484 FIF_BCN_PRBRESP_PROMISC | \
2485 FIF_FCSFAIL)
c83be688 2486
8feceb67
VT		 2487/* FIXME: sc->sc_full_reset ? */
2488static void ath9k_configure_filter(struct ieee80211_hw *hw,
2489 unsigned int changed_flags,
2490 unsigned int *total_flags,
2491 int mc_count,
2492 struct dev_mc_list *mclist)
2493{
bce048d7
JM		 2494 struct ath_wiphy *aphy = hw->priv;
2495 struct ath_softc *sc = aphy->sc;
8feceb67 2496 u32 rfilt;
f078f209 2497
8feceb67
VT		 2498 changed_flags &= SUPPORTED_FILTERS;
2499 *total_flags &= SUPPORTED_FILTERS;
f078f209 2500
b77f483f 2501 sc->rx.rxfilter = *total_flags;
8feceb67
VT		 2502 rfilt = ath_calcrxfilter(sc);
2503 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2504
b77f483f 2505 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2506}
f078f209 2507
8feceb67
VT		 2508static void ath9k_sta_notify(struct ieee80211_hw *hw,
2509 struct ieee80211_vif *vif,
2510 enum sta_notify_cmd cmd,
17741cdc 2511 struct ieee80211_sta *sta)
8feceb67 2512{
bce048d7
JM		 2513 struct ath_wiphy *aphy = hw->priv;
2514 struct ath_softc *sc = aphy->sc;
f078f209 2515
8feceb67
VT		 2516 switch (cmd) {
2517 case STA_NOTIFY_ADD:
5640b08e 2518 ath_node_attach(sc, sta);
8feceb67
VT		 2519 break;
2520 case STA_NOTIFY_REMOVE:
b5aa9bf9 2521 ath_node_detach(sc, sta);
8feceb67
VT		 2522 break;
2523 default:
2524 break;
2525 }
f078f209
LR		 2526}
2527
141b38b6 2528static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2529 const struct ieee80211_tx_queue_params *params)
f078f209 2530{
bce048d7
JM		 2531 struct ath_wiphy *aphy = hw->priv;
2532 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2533 struct ath9k_tx_queue_info qi;
2534 int ret = 0, qnum;
f078f209 2535
8feceb67
VT		 2536 if (queue >= WME_NUM_AC)
2537 return 0;
f078f209 2538
141b38b6
S		 2539 mutex_lock(&sc->mutex);
2540
1ffb0610
S		 2541 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2542
8feceb67
VT		 2543 qi.tqi_aifs = params->aifs;
2544 qi.tqi_cwmin = params->cw_min;
2545 qi.tqi_cwmax = params->cw_max;
2546 qi.tqi_burstTime = params->txop;
2547 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2548
8feceb67 2549 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2550 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2551 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2552 queue, qnum, params->aifs, params->cw_min,
2553 params->cw_max, params->txop);
f078f209 2554
8feceb67
VT		 2555 ret = ath_txq_update(sc, qnum, &qi);
2556 if (ret)
04bd4638 2557 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2558
141b38b6
S		 2559 mutex_unlock(&sc->mutex);
2560
8feceb67
VT		 2561 return ret;
2562}
f078f209 2563
8feceb67
VT		 2564static int ath9k_set_key(struct ieee80211_hw *hw,
2565 enum set_key_cmd cmd,
dc822b5d
JB		 2566 struct ieee80211_vif *vif,
2567 struct ieee80211_sta *sta,
8feceb67
VT		 2568 struct ieee80211_key_conf *key)
2569{
bce048d7
JM		 2570 struct ath_wiphy *aphy = hw->priv;
2571 struct ath_softc *sc = aphy->sc;
8feceb67 2572 int ret = 0;
f078f209 2573
b3bd89ce
JM		 2574 if (modparam_nohwcrypt)
2575 return -ENOSPC;
2576
141b38b6 2577 mutex_lock(&sc->mutex);
3cbb5dd7 2578 ath9k_ps_wakeup(sc);
d8baa939 2579 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2580
8feceb67
VT		 2581 switch (cmd) {
2582 case SET_KEY:
3f53dd64 2583 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2584 if (ret >= 0) {
2585 key->hw_key_idx = ret;
8feceb67
VT		 2586 /* push IV and Michael MIC generation to stack */
2587 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2588 if (key->alg == ALG_TKIP)
2589 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2590 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2591 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2592 ret = 0;
8feceb67
VT		 2593 }
2594 break;
2595 case DISABLE_KEY:
2596 ath_key_delete(sc, key);
8feceb67
VT		 2597 break;
2598 default:
2599 ret = -EINVAL;
2600 }
f078f209 2601
3cbb5dd7 2602 ath9k_ps_restore(sc);
141b38b6
S		 2603 mutex_unlock(&sc->mutex);
2604
8feceb67
VT		 2605 return ret;
2606}
f078f209 2607
8feceb67
VT		 2608static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2609 struct ieee80211_vif *vif,
2610 struct ieee80211_bss_conf *bss_conf,
2611 u32 changed)
2612{
bce048d7
JM		 2613 struct ath_wiphy *aphy = hw->priv;
2614 struct ath_softc *sc = aphy->sc;
f078f209 2615
141b38b6
S		 2616 mutex_lock(&sc->mutex);
2617
8feceb67 2618 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2619 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2620 bss_conf->use_short_preamble);
2621 if (bss_conf->use_short_preamble)
2622 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2623 else
2624 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2625 }
f078f209 2626
8feceb67 2627 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2628 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2629 bss_conf->use_cts_prot);
2630 if (bss_conf->use_cts_prot &&
2631 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2632 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2633 else
2634 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2635 }
f078f209 2636
8feceb67 2637 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2638 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2639 bss_conf->assoc);
5640b08e 2640 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2641 }
141b38b6
S		 2642
2643 mutex_unlock(&sc->mutex);
8feceb67 2644}
f078f209 2645
8feceb67
VT		 2646static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2647{
2648 u64 tsf;
bce048d7
JM		 2649 struct ath_wiphy *aphy = hw->priv;
2650 struct ath_softc *sc = aphy->sc;
f078f209 2651
141b38b6
S		 2652 mutex_lock(&sc->mutex);
2653 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2654 mutex_unlock(&sc->mutex);
f078f209 2655
8feceb67
VT		 2656 return tsf;
2657}
f078f209 2658
3b5d665b
AF		 2659static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2660{
bce048d7
JM		 2661 struct ath_wiphy *aphy = hw->priv;
2662 struct ath_softc *sc = aphy->sc;
3b5d665b 2663
141b38b6
S		 2664 mutex_lock(&sc->mutex);
2665 ath9k_hw_settsf64(sc->sc_ah, tsf);
2666 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2667}
2668
8feceb67
VT		 2669static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2670{
bce048d7
JM		 2671 struct ath_wiphy *aphy = hw->priv;
2672 struct ath_softc *sc = aphy->sc;
c83be688 2673
141b38b6
S		 2674 mutex_lock(&sc->mutex);
2675 ath9k_hw_reset_tsf(sc->sc_ah);
2676 mutex_unlock(&sc->mutex);
8feceb67 2677}
f078f209 2678
8feceb67 2679static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2680 enum ieee80211_ampdu_mlme_action action,
2681 struct ieee80211_sta *sta,
2682 u16 tid, u16 *ssn)
8feceb67 2683{
bce048d7
JM		 2684 struct ath_wiphy *aphy = hw->priv;
2685 struct ath_softc *sc = aphy->sc;
8feceb67 2686 int ret = 0;
f078f209 2687
8feceb67
VT		 2688 switch (action) {
2689 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2690 if (!(sc->sc_flags & SC_OP_RXAGGR))
2691 ret = -ENOTSUPP;
8feceb67
VT		 2692 break;
2693 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2694 break;
2695 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2696 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2697 if (ret < 0)
2698 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2699 "Unable to start TX aggregation\n");
8feceb67 2700 else
17741cdc 2701 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2702 break;
2703 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2704 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2705 if (ret < 0)
2706 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2707 "Unable to stop TX aggregation\n");
f078f209 2708
17741cdc 2709 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2710 break;
b1720231 2711 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 2712 ath_tx_aggr_resume(sc, sta, tid);
2713 break;
8feceb67 2714 default:
04bd4638 2715 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2716 }
2717
2718 return ret;
f078f209
LR		 2719}
2720
0c98de65
S		 2721static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2722{
bce048d7
JM		 2723 struct ath_wiphy *aphy = hw->priv;
2724 struct ath_softc *sc = aphy->sc;
0c98de65 2725
8089cc47
JM		 2726 if (ath9k_wiphy_scanning(sc)) {
2727 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2728 "same time\n");
2729 /*
2730 * Do not allow the concurrent scanning state for now. This
2731 * could be improved with scanning control moved into ath9k.
2732 */
2733 return;
2734 }
2735
2736 aphy->state = ATH_WIPHY_SCAN;
2737 ath9k_wiphy_pause_all_forced(sc, aphy);
2738
0c98de65
S		 2739 mutex_lock(&sc->mutex);
2740 sc->sc_flags |= SC_OP_SCANNING;
2741 mutex_unlock(&sc->mutex);
2742}
2743
2744static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2745{
bce048d7
JM		 2746 struct ath_wiphy *aphy = hw->priv;
2747 struct ath_softc *sc = aphy->sc;
0c98de65
S		 2748
2749 mutex_lock(&sc->mutex);
8089cc47 2750 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 2751 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 2752 sc->sc_flags |= SC_OP_FULL_RESET;
0c98de65
S		 2753 mutex_unlock(&sc->mutex);
2754}
2755
6baff7f9 2756struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2757 .tx = ath9k_tx,
2758 .start = ath9k_start,
2759 .stop = ath9k_stop,
2760 .add_interface = ath9k_add_interface,
2761 .remove_interface = ath9k_remove_interface,
2762 .config = ath9k_config,
2763 .config_interface = ath9k_config_interface,
2764 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2765 .sta_notify = ath9k_sta_notify,
2766 .conf_tx = ath9k_conf_tx,
8feceb67 2767 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2768 .set_key = ath9k_set_key,
8feceb67 2769 .get_tsf = ath9k_get_tsf,
3b5d665b 2770 .set_tsf = ath9k_set_tsf,
8feceb67 2771 .reset_tsf = ath9k_reset_tsf,
4233df6b 2772 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 2773 .sw_scan_start = ath9k_sw_scan_start,
2774 .sw_scan_complete = ath9k_sw_scan_complete,
8feceb67
VT		 2775};
2776
392dff83
BP		 2777static struct {
2778 u32 version;
2779 const char * name;
2780} ath_mac_bb_names[] = {
2781 { AR_SREV_VERSION_5416_PCI, "5416" },
2782 { AR_SREV_VERSION_5416_PCIE, "5418" },
2783 { AR_SREV_VERSION_9100, "9100" },
2784 { AR_SREV_VERSION_9160, "9160" },
2785 { AR_SREV_VERSION_9280, "9280" },
2786 { AR_SREV_VERSION_9285, "9285" }
2787};
2788
2789static struct {
2790 u16 version;
2791 const char * name;
2792} ath_rf_names[] = {
2793 { 0, "5133" },
2794 { AR_RAD5133_SREV_MAJOR, "5133" },
2795 { AR_RAD5122_SREV_MAJOR, "5122" },
2796 { AR_RAD2133_SREV_MAJOR, "2133" },
2797 { AR_RAD2122_SREV_MAJOR, "2122" }
2798};
2799
2800/*
2801 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2802 */
6baff7f9 2803const char *
392dff83
BP		 2804ath_mac_bb_name(u32 mac_bb_version)
2805{
2806 int i;
2807
2808 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2809 if (ath_mac_bb_names[i].version == mac_bb_version) {
2810 return ath_mac_bb_names[i].name;
2811 }
2812 }
2813
2814 return "????";
2815}
2816
2817/*
2818 * Return the RF name. "????" is returned if the RF is unknown.
2819 */
6baff7f9 2820const char *
392dff83
BP		 2821ath_rf_name(u16 rf_version)
2822{
2823 int i;
2824
2825 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2826 if (ath_rf_names[i].version == rf_version) {
2827 return ath_rf_names[i].name;
2828 }
2829 }
2830
2831 return "????";
2832}
2833
6baff7f9 2834static int __init ath9k_init(void)
f078f209 2835{
ca8a8560
VT		 2836 int error;
2837
ca8a8560
VT		 2838 /* Register rate control algorithm */
2839 error = ath_rate_control_register();
2840 if (error != 0) {
2841 printk(KERN_ERR
b51bb3cd
LR		 2842 "ath9k: Unable to register rate control "
2843 "algorithm: %d\n",
ca8a8560 2844 error);
6baff7f9 2845 goto err_out;
ca8a8560
VT		 2846 }
2847
19d8bc22
GJ		 2848 error = ath9k_debug_create_root();
2849 if (error) {
2850 printk(KERN_ERR
2851 "ath9k: Unable to create debugfs root: %d\n",
2852 error);
2853 goto err_rate_unregister;
2854 }
2855
6baff7f9
GJ		 2856 error = ath_pci_init();
2857 if (error < 0) {
f078f209 2858 printk(KERN_ERR
b51bb3cd 2859 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 2860 error = -ENODEV;
19d8bc22 2861 goto err_remove_root;
f078f209
LR		 2862 }
2863
09329d37
GJ		 2864 error = ath_ahb_init();
2865 if (error < 0) {
2866 error = -ENODEV;
2867 goto err_pci_exit;
2868 }
2869
f078f209 2870 return 0;
6baff7f9 2871
09329d37
GJ		 2872 err_pci_exit:
2873 ath_pci_exit();
2874
19d8bc22
GJ		 2875 err_remove_root:
2876 ath9k_debug_remove_root();
6baff7f9
GJ		 2877 err_rate_unregister:
2878 ath_rate_control_unregister();
2879 err_out:
2880 return error;
f078f209 2881}
6baff7f9 2882module_init(ath9k_init);
f078f209 2883
6baff7f9 2884static void __exit ath9k_exit(void)
f078f209 2885{
09329d37 2886 ath_ahb_exit();
6baff7f9 2887 ath_pci_exit();
19d8bc22 2888 ath9k_debug_remove_root();
ca8a8560 2889 ath_rate_control_unregister();
04bd4638 2890 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2891}
6baff7f9 2892module_exit(ath9k_exit);
Linux kernel - Deliverables
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