Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
69081624 | 18 | #include <linux/delay.h> |
394cf0a1 | 19 | #include "ath9k.h" |
af03abec | 20 | #include "btcoex.h" |
f078f209 | 21 | |
ff37e337 S |
22 | static u8 parse_mpdudensity(u8 mpdudensity) |
23 | { | |
24 | /* | |
25 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
26 | * 0 for no restriction | |
27 | * 1 for 1/4 us | |
28 | * 2 for 1/2 us | |
29 | * 3 for 1 us | |
30 | * 4 for 2 us | |
31 | * 5 for 4 us | |
32 | * 6 for 8 us | |
33 | * 7 for 16 us | |
34 | */ | |
35 | switch (mpdudensity) { | |
36 | case 0: | |
37 | return 0; | |
38 | case 1: | |
39 | case 2: | |
40 | case 3: | |
41 | /* Our lower layer calculations limit our precision to | |
42 | 1 microsecond */ | |
43 | return 1; | |
44 | case 4: | |
45 | return 2; | |
46 | case 5: | |
47 | return 4; | |
48 | case 6: | |
49 | return 8; | |
50 | case 7: | |
51 | return 16; | |
52 | default: | |
53 | return 0; | |
54 | } | |
55 | } | |
56 | ||
69081624 VT |
57 | static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq) |
58 | { | |
59 | bool pending = false; | |
60 | ||
61 | spin_lock_bh(&txq->axq_lock); | |
62 | ||
63 | if (txq->axq_depth || !list_empty(&txq->axq_acq)) | |
64 | pending = true; | |
69081624 VT |
65 | |
66 | spin_unlock_bh(&txq->axq_lock); | |
67 | return pending; | |
68 | } | |
69 | ||
6d79cb4c | 70 | static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
71 | { |
72 | unsigned long flags; | |
73 | bool ret; | |
74 | ||
9ecdef4b LR |
75 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
76 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
77 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
78 | |
79 | return ret; | |
80 | } | |
81 | ||
a91d75ae LR |
82 | void ath9k_ps_wakeup(struct ath_softc *sc) |
83 | { | |
898c914a | 84 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae | 85 | unsigned long flags; |
fbb078fc | 86 | enum ath9k_power_mode power_mode; |
a91d75ae LR |
87 | |
88 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
89 | if (++sc->ps_usecount != 1) | |
90 | goto unlock; | |
91 | ||
fbb078fc | 92 | power_mode = sc->sc_ah->power_mode; |
9ecdef4b | 93 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae | 94 | |
898c914a FF |
95 | /* |
96 | * While the hardware is asleep, the cycle counters contain no | |
97 | * useful data. Better clear them now so that they don't mess up | |
98 | * survey data results. | |
99 | */ | |
fbb078fc FF |
100 | if (power_mode != ATH9K_PM_AWAKE) { |
101 | spin_lock(&common->cc_lock); | |
102 | ath_hw_cycle_counters_update(common); | |
103 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
104 | spin_unlock(&common->cc_lock); | |
105 | } | |
898c914a | 106 | |
a91d75ae LR |
107 | unlock: |
108 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
109 | } | |
110 | ||
111 | void ath9k_ps_restore(struct ath_softc *sc) | |
112 | { | |
898c914a | 113 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
c6c539f0 | 114 | enum ath9k_power_mode mode; |
a91d75ae LR |
115 | unsigned long flags; |
116 | ||
117 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
118 | if (--sc->ps_usecount != 0) | |
119 | goto unlock; | |
120 | ||
c8e8868e | 121 | if (sc->ps_idle && (sc->ps_flags & PS_WAIT_FOR_TX_ACK)) |
c6c539f0 | 122 | mode = ATH9K_PM_FULL_SLEEP; |
1dbfd9d4 VN |
123 | else if (sc->ps_enabled && |
124 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
1b04b930 S |
125 | PS_WAIT_FOR_CAB | |
126 | PS_WAIT_FOR_PSPOLL_DATA | | |
127 | PS_WAIT_FOR_TX_ACK))) | |
c6c539f0 FF |
128 | mode = ATH9K_PM_NETWORK_SLEEP; |
129 | else | |
130 | goto unlock; | |
131 | ||
132 | spin_lock(&common->cc_lock); | |
133 | ath_hw_cycle_counters_update(common); | |
134 | spin_unlock(&common->cc_lock); | |
135 | ||
1a8f0d39 | 136 | ath9k_hw_setpower(sc->sc_ah, mode); |
a91d75ae LR |
137 | |
138 | unlock: | |
139 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
140 | } | |
141 | ||
05c0be2f | 142 | void ath_start_ani(struct ath_common *common) |
5ee08656 FF |
143 | { |
144 | struct ath_hw *ah = common->ah; | |
145 | unsigned long timestamp = jiffies_to_msecs(jiffies); | |
146 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
147 | ||
148 | if (!(sc->sc_flags & SC_OP_ANI_RUN)) | |
149 | return; | |
150 | ||
151 | if (sc->sc_flags & SC_OP_OFFCHANNEL) | |
152 | return; | |
153 | ||
154 | common->ani.longcal_timer = timestamp; | |
155 | common->ani.shortcal_timer = timestamp; | |
156 | common->ani.checkani_timer = timestamp; | |
157 | ||
158 | mod_timer(&common->ani.timer, | |
159 | jiffies + | |
160 | msecs_to_jiffies((u32)ah->config.ani_poll_interval)); | |
161 | } | |
162 | ||
3430098a FF |
163 | static void ath_update_survey_nf(struct ath_softc *sc, int channel) |
164 | { | |
165 | struct ath_hw *ah = sc->sc_ah; | |
166 | struct ath9k_channel *chan = &ah->channels[channel]; | |
167 | struct survey_info *survey = &sc->survey[channel]; | |
168 | ||
169 | if (chan->noisefloor) { | |
170 | survey->filled |= SURVEY_INFO_NOISE_DBM; | |
f749b946 | 171 | survey->noise = ath9k_hw_getchan_noise(ah, chan); |
3430098a FF |
172 | } |
173 | } | |
174 | ||
cb8d61de FF |
175 | /* |
176 | * Updates the survey statistics and returns the busy time since last | |
177 | * update in %, if the measurement duration was long enough for the | |
178 | * result to be useful, -1 otherwise. | |
179 | */ | |
180 | static int ath_update_survey_stats(struct ath_softc *sc) | |
3430098a FF |
181 | { |
182 | struct ath_hw *ah = sc->sc_ah; | |
183 | struct ath_common *common = ath9k_hw_common(ah); | |
184 | int pos = ah->curchan - &ah->channels[0]; | |
185 | struct survey_info *survey = &sc->survey[pos]; | |
186 | struct ath_cycle_counters *cc = &common->cc_survey; | |
187 | unsigned int div = common->clockrate * 1000; | |
cb8d61de | 188 | int ret = 0; |
3430098a | 189 | |
0845735e | 190 | if (!ah->curchan) |
cb8d61de | 191 | return -1; |
0845735e | 192 | |
898c914a FF |
193 | if (ah->power_mode == ATH9K_PM_AWAKE) |
194 | ath_hw_cycle_counters_update(common); | |
3430098a FF |
195 | |
196 | if (cc->cycles > 0) { | |
197 | survey->filled |= SURVEY_INFO_CHANNEL_TIME | | |
198 | SURVEY_INFO_CHANNEL_TIME_BUSY | | |
199 | SURVEY_INFO_CHANNEL_TIME_RX | | |
200 | SURVEY_INFO_CHANNEL_TIME_TX; | |
201 | survey->channel_time += cc->cycles / div; | |
202 | survey->channel_time_busy += cc->rx_busy / div; | |
203 | survey->channel_time_rx += cc->rx_frame / div; | |
204 | survey->channel_time_tx += cc->tx_frame / div; | |
205 | } | |
cb8d61de FF |
206 | |
207 | if (cc->cycles < div) | |
208 | return -1; | |
209 | ||
210 | if (cc->cycles > 0) | |
211 | ret = cc->rx_busy * 100 / cc->cycles; | |
212 | ||
3430098a FF |
213 | memset(cc, 0, sizeof(*cc)); |
214 | ||
215 | ath_update_survey_nf(sc, pos); | |
cb8d61de FF |
216 | |
217 | return ret; | |
3430098a FF |
218 | } |
219 | ||
9adcf440 | 220 | static void __ath_cancel_work(struct ath_softc *sc) |
ff37e337 | 221 | { |
5ee08656 FF |
222 | cancel_work_sync(&sc->paprd_work); |
223 | cancel_work_sync(&sc->hw_check_work); | |
224 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
181fb18d | 225 | cancel_delayed_work_sync(&sc->hw_pll_work); |
9adcf440 | 226 | } |
5ee08656 | 227 | |
9adcf440 FF |
228 | static void ath_cancel_work(struct ath_softc *sc) |
229 | { | |
230 | __ath_cancel_work(sc); | |
231 | cancel_work_sync(&sc->hw_reset_work); | |
232 | } | |
3cbb5dd7 | 233 | |
9adcf440 FF |
234 | static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush) |
235 | { | |
236 | struct ath_hw *ah = sc->sc_ah; | |
237 | struct ath_common *common = ath9k_hw_common(ah); | |
238 | bool ret; | |
6a6733f2 | 239 | |
9adcf440 | 240 | ieee80211_stop_queues(sc->hw); |
5e848f78 | 241 | |
9adcf440 FF |
242 | sc->hw_busy_count = 0; |
243 | del_timer_sync(&common->ani.timer); | |
ff37e337 | 244 | |
9adcf440 FF |
245 | ath9k_debug_samp_bb_mac(sc); |
246 | ath9k_hw_disable_interrupts(ah); | |
8b3f4616 | 247 | |
9adcf440 | 248 | ret = ath_drain_all_txq(sc, retry_tx); |
ff37e337 | 249 | |
9adcf440 FF |
250 | if (!ath_stoprecv(sc)) |
251 | ret = false; | |
c0d7c7af | 252 | |
9adcf440 FF |
253 | if (!flush) { |
254 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
3483288c FF |
255 | ath_rx_tasklet(sc, 1, true); |
256 | ath_rx_tasklet(sc, 1, false); | |
9adcf440 FF |
257 | } else { |
258 | ath_flushrecv(sc); | |
259 | } | |
20bd2a09 | 260 | |
9adcf440 FF |
261 | return ret; |
262 | } | |
ff37e337 | 263 | |
9adcf440 FF |
264 | static bool ath_complete_reset(struct ath_softc *sc, bool start) |
265 | { | |
266 | struct ath_hw *ah = sc->sc_ah; | |
267 | struct ath_common *common = ath9k_hw_common(ah); | |
c0d7c7af | 268 | |
c0d7c7af | 269 | if (ath_startrecv(sc) != 0) { |
3800276a | 270 | ath_err(common, "Unable to restart recv logic\n"); |
9adcf440 | 271 | return false; |
c0d7c7af LR |
272 | } |
273 | ||
5048e8c3 RM |
274 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
275 | sc->config.txpowlimit, &sc->curtxpow); | |
72d874c6 | 276 | ath9k_hw_set_interrupts(ah); |
b037b693 | 277 | ath9k_hw_enable_interrupts(ah); |
3989279c | 278 | |
9adcf440 | 279 | if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)) && start) { |
1186488b | 280 | if (sc->sc_flags & SC_OP_BEACONS) |
99e4d43a | 281 | ath_set_beacon(sc); |
9adcf440 | 282 | |
5ee08656 | 283 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
181fb18d | 284 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2); |
05c0be2f MSS |
285 | if (!common->disable_ani) |
286 | ath_start_ani(common); | |
5ee08656 FF |
287 | } |
288 | ||
43c35284 FF |
289 | if (ath9k_hw_ops(ah)->antdiv_comb_conf_get && sc->ant_rx != 3) { |
290 | struct ath_hw_antcomb_conf div_ant_conf; | |
291 | u8 lna_conf; | |
292 | ||
293 | ath9k_hw_antdiv_comb_conf_get(ah, &div_ant_conf); | |
294 | ||
295 | if (sc->ant_rx == 1) | |
296 | lna_conf = ATH_ANT_DIV_COMB_LNA1; | |
297 | else | |
298 | lna_conf = ATH_ANT_DIV_COMB_LNA2; | |
299 | div_ant_conf.main_lna_conf = lna_conf; | |
300 | div_ant_conf.alt_lna_conf = lna_conf; | |
301 | ||
302 | ath9k_hw_antdiv_comb_conf_set(ah, &div_ant_conf); | |
303 | } | |
304 | ||
9adcf440 FF |
305 | ieee80211_wake_queues(sc->hw); |
306 | ||
307 | return true; | |
308 | } | |
309 | ||
310 | static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan, | |
311 | bool retry_tx) | |
312 | { | |
313 | struct ath_hw *ah = sc->sc_ah; | |
314 | struct ath_common *common = ath9k_hw_common(ah); | |
315 | struct ath9k_hw_cal_data *caldata = NULL; | |
316 | bool fastcc = true; | |
317 | bool flush = false; | |
318 | int r; | |
319 | ||
320 | __ath_cancel_work(sc); | |
321 | ||
322 | spin_lock_bh(&sc->sc_pcu_lock); | |
92460412 | 323 | |
9adcf440 FF |
324 | if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) { |
325 | fastcc = false; | |
326 | caldata = &sc->caldata; | |
327 | } | |
328 | ||
329 | if (!hchan) { | |
330 | fastcc = false; | |
331 | flush = true; | |
332 | hchan = ah->curchan; | |
333 | } | |
334 | ||
c8e8868e FF |
335 | if (fastcc && (ah->chip_fullsleep || |
336 | !ath9k_hw_check_alive(ah))) | |
9adcf440 FF |
337 | fastcc = false; |
338 | ||
339 | if (!ath_prepare_reset(sc, retry_tx, flush)) | |
340 | fastcc = false; | |
341 | ||
342 | ath_dbg(common, ATH_DBG_CONFIG, | |
343 | "Reset to %u MHz, HT40: %d fastcc: %d\n", | |
344 | hchan->channel, !!(hchan->channelFlags & (CHANNEL_HT40MINUS | | |
345 | CHANNEL_HT40PLUS)), | |
346 | fastcc); | |
347 | ||
348 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); | |
349 | if (r) { | |
350 | ath_err(common, | |
351 | "Unable to reset channel, reset status %d\n", r); | |
352 | goto out; | |
353 | } | |
354 | ||
355 | if (!ath_complete_reset(sc, true)) | |
356 | r = -EIO; | |
357 | ||
358 | out: | |
6a6733f2 | 359 | spin_unlock_bh(&sc->sc_pcu_lock); |
9adcf440 FF |
360 | return r; |
361 | } | |
362 | ||
363 | ||
364 | /* | |
365 | * Set/change channels. If the channel is really being changed, it's done | |
366 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
367 | * DMA, then restart stuff. | |
368 | */ | |
369 | static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, | |
370 | struct ath9k_channel *hchan) | |
371 | { | |
372 | int r; | |
373 | ||
374 | if (sc->sc_flags & SC_OP_INVALID) | |
375 | return -EIO; | |
376 | ||
377 | ath9k_ps_wakeup(sc); | |
378 | ||
379 | r = ath_reset_internal(sc, hchan, false); | |
6a6733f2 | 380 | |
3cbb5dd7 | 381 | ath9k_ps_restore(sc); |
9adcf440 | 382 | |
3989279c | 383 | return r; |
ff37e337 S |
384 | } |
385 | ||
9f42c2b6 FF |
386 | static void ath_paprd_activate(struct ath_softc *sc) |
387 | { | |
388 | struct ath_hw *ah = sc->sc_ah; | |
20bd2a09 | 389 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9f42c2b6 FF |
390 | int chain; |
391 | ||
20bd2a09 | 392 | if (!caldata || !caldata->paprd_done) |
9f42c2b6 FF |
393 | return; |
394 | ||
395 | ath9k_ps_wakeup(sc); | |
ddfef792 | 396 | ar9003_paprd_enable(ah, false); |
9f42c2b6 | 397 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
82b2d334 | 398 | if (!(ah->txchainmask & BIT(chain))) |
9f42c2b6 FF |
399 | continue; |
400 | ||
20bd2a09 | 401 | ar9003_paprd_populate_single_table(ah, caldata, chain); |
9f42c2b6 FF |
402 | } |
403 | ||
404 | ar9003_paprd_enable(ah, true); | |
405 | ath9k_ps_restore(sc); | |
406 | } | |
407 | ||
7607cbe2 FF |
408 | static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain) |
409 | { | |
410 | struct ieee80211_hw *hw = sc->hw; | |
411 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
47960077 MSS |
412 | struct ath_hw *ah = sc->sc_ah; |
413 | struct ath_common *common = ath9k_hw_common(ah); | |
7607cbe2 FF |
414 | struct ath_tx_control txctl; |
415 | int time_left; | |
416 | ||
417 | memset(&txctl, 0, sizeof(txctl)); | |
418 | txctl.txq = sc->tx.txq_map[WME_AC_BE]; | |
419 | ||
420 | memset(tx_info, 0, sizeof(*tx_info)); | |
421 | tx_info->band = hw->conf.channel->band; | |
422 | tx_info->flags |= IEEE80211_TX_CTL_NO_ACK; | |
423 | tx_info->control.rates[0].idx = 0; | |
424 | tx_info->control.rates[0].count = 1; | |
425 | tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS; | |
426 | tx_info->control.rates[1].idx = -1; | |
427 | ||
428 | init_completion(&sc->paprd_complete); | |
7607cbe2 | 429 | txctl.paprd = BIT(chain); |
47960077 MSS |
430 | |
431 | if (ath_tx_start(hw, skb, &txctl) != 0) { | |
d4bb17c4 | 432 | ath_dbg(common, ATH_DBG_CALIBRATE, "PAPRD TX failed\n"); |
47960077 | 433 | dev_kfree_skb_any(skb); |
7607cbe2 | 434 | return false; |
47960077 | 435 | } |
7607cbe2 FF |
436 | |
437 | time_left = wait_for_completion_timeout(&sc->paprd_complete, | |
438 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); | |
7607cbe2 FF |
439 | |
440 | if (!time_left) | |
d4bb17c4 | 441 | ath_dbg(common, ATH_DBG_CALIBRATE, |
7607cbe2 FF |
442 | "Timeout waiting for paprd training on TX chain %d\n", |
443 | chain); | |
444 | ||
445 | return !!time_left; | |
446 | } | |
447 | ||
9f42c2b6 FF |
448 | void ath_paprd_calibrate(struct work_struct *work) |
449 | { | |
450 | struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work); | |
451 | struct ieee80211_hw *hw = sc->hw; | |
452 | struct ath_hw *ah = sc->sc_ah; | |
453 | struct ieee80211_hdr *hdr; | |
454 | struct sk_buff *skb = NULL; | |
20bd2a09 | 455 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9094537c | 456 | struct ath_common *common = ath9k_hw_common(ah); |
066dae93 | 457 | int ftype; |
9f42c2b6 FF |
458 | int chain_ok = 0; |
459 | int chain; | |
460 | int len = 1800; | |
9f42c2b6 | 461 | |
20bd2a09 FF |
462 | if (!caldata) |
463 | return; | |
464 | ||
b942471b MSS |
465 | ath9k_ps_wakeup(sc); |
466 | ||
1bf38661 | 467 | if (ar9003_paprd_init_table(ah) < 0) |
b942471b | 468 | goto fail_paprd; |
1bf38661 | 469 | |
9f42c2b6 FF |
470 | skb = alloc_skb(len, GFP_KERNEL); |
471 | if (!skb) | |
b942471b | 472 | goto fail_paprd; |
9f42c2b6 | 473 | |
9f42c2b6 FF |
474 | skb_put(skb, len); |
475 | memset(skb->data, 0, len); | |
476 | hdr = (struct ieee80211_hdr *)skb->data; | |
477 | ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC; | |
478 | hdr->frame_control = cpu_to_le16(ftype); | |
a3d3da14 | 479 | hdr->duration_id = cpu_to_le16(10); |
9f42c2b6 FF |
480 | memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN); |
481 | memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN); | |
482 | memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); | |
483 | ||
9f42c2b6 | 484 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
82b2d334 | 485 | if (!(ah->txchainmask & BIT(chain))) |
9f42c2b6 FF |
486 | continue; |
487 | ||
488 | chain_ok = 0; | |
9f42c2b6 | 489 | |
7607cbe2 FF |
490 | ath_dbg(common, ATH_DBG_CALIBRATE, |
491 | "Sending PAPRD frame for thermal measurement " | |
492 | "on chain %d\n", chain); | |
493 | if (!ath_paprd_send_frame(sc, skb, chain)) | |
494 | goto fail_paprd; | |
9f42c2b6 | 495 | |
9f42c2b6 | 496 | ar9003_paprd_setup_gain_table(ah, chain); |
9f42c2b6 | 497 | |
7607cbe2 FF |
498 | ath_dbg(common, ATH_DBG_CALIBRATE, |
499 | "Sending PAPRD training frame on chain %d\n", chain); | |
500 | if (!ath_paprd_send_frame(sc, skb, chain)) | |
ca369eb4 | 501 | goto fail_paprd; |
9f42c2b6 | 502 | |
d4bb17c4 MSS |
503 | if (!ar9003_paprd_is_done(ah)) { |
504 | ath_dbg(common, ATH_DBG_CALIBRATE, | |
505 | "PAPRD not yet done on chain %d\n", chain); | |
9f42c2b6 | 506 | break; |
d4bb17c4 | 507 | } |
9f42c2b6 | 508 | |
d4bb17c4 MSS |
509 | if (ar9003_paprd_create_curve(ah, caldata, chain)) { |
510 | ath_dbg(common, ATH_DBG_CALIBRATE, | |
511 | "PAPRD create curve failed on chain %d\n", | |
512 | chain); | |
9f42c2b6 | 513 | break; |
d4bb17c4 | 514 | } |
9f42c2b6 FF |
515 | |
516 | chain_ok = 1; | |
517 | } | |
518 | kfree_skb(skb); | |
519 | ||
520 | if (chain_ok) { | |
20bd2a09 | 521 | caldata->paprd_done = true; |
9f42c2b6 FF |
522 | ath_paprd_activate(sc); |
523 | } | |
524 | ||
ca369eb4 | 525 | fail_paprd: |
9f42c2b6 FF |
526 | ath9k_ps_restore(sc); |
527 | } | |
528 | ||
ff37e337 S |
529 | /* |
530 | * This routine performs the periodic noise floor calibration function | |
531 | * that is used to adjust and optimize the chip performance. This | |
532 | * takes environmental changes (location, temperature) into account. | |
533 | * When the task is complete, it reschedules itself depending on the | |
534 | * appropriate interval that was calculated. | |
535 | */ | |
55624204 | 536 | void ath_ani_calibrate(unsigned long data) |
ff37e337 | 537 | { |
20977d3e S |
538 | struct ath_softc *sc = (struct ath_softc *)data; |
539 | struct ath_hw *ah = sc->sc_ah; | |
c46917bb | 540 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
541 | bool longcal = false; |
542 | bool shortcal = false; | |
543 | bool aniflag = false; | |
544 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
6044474e | 545 | u32 cal_interval, short_cal_interval, long_cal_interval; |
b5bfc568 | 546 | unsigned long flags; |
6044474e FF |
547 | |
548 | if (ah->caldata && ah->caldata->nfcal_interference) | |
549 | long_cal_interval = ATH_LONG_CALINTERVAL_INT; | |
550 | else | |
551 | long_cal_interval = ATH_LONG_CALINTERVAL; | |
ff37e337 | 552 | |
20977d3e S |
553 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
554 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 | 555 | |
1ffc1c61 JM |
556 | /* Only calibrate if awake */ |
557 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
558 | goto set_timer; | |
559 | ||
560 | ath9k_ps_wakeup(sc); | |
561 | ||
ff37e337 | 562 | /* Long calibration runs independently of short calibration. */ |
6044474e | 563 | if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) { |
ff37e337 | 564 | longcal = true; |
226afe68 | 565 | ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
3d536acf | 566 | common->ani.longcal_timer = timestamp; |
ff37e337 S |
567 | } |
568 | ||
17d7904d | 569 | /* Short calibration applies only while caldone is false */ |
3d536acf LR |
570 | if (!common->ani.caldone) { |
571 | if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { | |
ff37e337 | 572 | shortcal = true; |
226afe68 JP |
573 | ath_dbg(common, ATH_DBG_ANI, |
574 | "shortcal @%lu\n", jiffies); | |
3d536acf LR |
575 | common->ani.shortcal_timer = timestamp; |
576 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
577 | } |
578 | } else { | |
3d536acf | 579 | if ((timestamp - common->ani.resetcal_timer) >= |
ff37e337 | 580 | ATH_RESTART_CALINTERVAL) { |
3d536acf LR |
581 | common->ani.caldone = ath9k_hw_reset_calvalid(ah); |
582 | if (common->ani.caldone) | |
583 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
584 | } |
585 | } | |
586 | ||
587 | /* Verify whether we must check ANI */ | |
e36b27af LR |
588 | if ((timestamp - common->ani.checkani_timer) >= |
589 | ah->config.ani_poll_interval) { | |
ff37e337 | 590 | aniflag = true; |
3d536acf | 591 | common->ani.checkani_timer = timestamp; |
ff37e337 S |
592 | } |
593 | ||
e62ddec9 MSS |
594 | /* Call ANI routine if necessary */ |
595 | if (aniflag) { | |
596 | spin_lock_irqsave(&common->cc_lock, flags); | |
597 | ath9k_hw_ani_monitor(ah, ah->curchan); | |
598 | ath_update_survey_stats(sc); | |
599 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
600 | } | |
ff37e337 | 601 | |
e62ddec9 MSS |
602 | /* Perform calibration if necessary */ |
603 | if (longcal || shortcal) { | |
604 | common->ani.caldone = | |
605 | ath9k_hw_calibrate(ah, ah->curchan, | |
82b2d334 | 606 | ah->rxchainmask, longcal); |
ff37e337 S |
607 | } |
608 | ||
1ffc1c61 JM |
609 | ath9k_ps_restore(sc); |
610 | ||
20977d3e | 611 | set_timer: |
ff37e337 S |
612 | /* |
613 | * Set timer interval based on previous results. | |
614 | * The interval must be the shortest necessary to satisfy ANI, | |
615 | * short calibration and long calibration. | |
616 | */ | |
cf3af748 | 617 | ath9k_debug_samp_bb_mac(sc); |
aac9207e | 618 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 619 | if (sc->sc_ah->config.enable_ani) |
e36b27af LR |
620 | cal_interval = min(cal_interval, |
621 | (u32)ah->config.ani_poll_interval); | |
3d536acf | 622 | if (!common->ani.caldone) |
20977d3e | 623 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 624 | |
3d536acf | 625 | mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
20bd2a09 FF |
626 | if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) { |
627 | if (!ah->caldata->paprd_done) | |
9f42c2b6 | 628 | ieee80211_queue_work(sc->hw, &sc->paprd_work); |
45ef6a0b | 629 | else if (!ah->paprd_table_write_done) |
9f42c2b6 FF |
630 | ath_paprd_activate(sc); |
631 | } | |
ff37e337 S |
632 | } |
633 | ||
7e1e3864 BG |
634 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, |
635 | struct ieee80211_vif *vif) | |
ff37e337 S |
636 | { |
637 | struct ath_node *an; | |
ff37e337 S |
638 | an = (struct ath_node *)sta->drv_priv; |
639 | ||
7f010c93 BG |
640 | #ifdef CONFIG_ATH9K_DEBUGFS |
641 | spin_lock(&sc->nodes_lock); | |
642 | list_add(&an->list, &sc->nodes); | |
643 | spin_unlock(&sc->nodes_lock); | |
644 | an->sta = sta; | |
7e1e3864 | 645 | an->vif = vif; |
7f010c93 | 646 | #endif |
87792efc | 647 | if (sc->sc_flags & SC_OP_TXAGGR) { |
ff37e337 | 648 | ath_tx_node_init(sc, an); |
9e98ac65 | 649 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc S |
650 | sta->ht_cap.ampdu_factor); |
651 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
652 | } | |
ff37e337 S |
653 | } |
654 | ||
655 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
656 | { | |
657 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
658 | ||
7f010c93 BG |
659 | #ifdef CONFIG_ATH9K_DEBUGFS |
660 | spin_lock(&sc->nodes_lock); | |
661 | list_del(&an->list); | |
662 | spin_unlock(&sc->nodes_lock); | |
663 | an->sta = NULL; | |
664 | #endif | |
665 | ||
ff37e337 S |
666 | if (sc->sc_flags & SC_OP_TXAGGR) |
667 | ath_tx_node_cleanup(sc, an); | |
668 | } | |
669 | ||
9eab61c2 | 670 | |
55624204 | 671 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
672 | { |
673 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 674 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 675 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 676 | |
17d7904d | 677 | u32 status = sc->intrstatus; |
b5c80475 | 678 | u32 rxmask; |
ff37e337 | 679 | |
e3927007 FF |
680 | ath9k_ps_wakeup(sc); |
681 | spin_lock(&sc->sc_pcu_lock); | |
682 | ||
a4d86d95 RM |
683 | if ((status & ATH9K_INT_FATAL) || |
684 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
030d6294 FF |
685 | #ifdef CONFIG_ATH9K_DEBUGFS |
686 | enum ath_reset_type type; | |
687 | ||
688 | if (status & ATH9K_INT_FATAL) | |
689 | type = RESET_TYPE_FATAL_INT; | |
690 | else | |
691 | type = RESET_TYPE_BB_WATCHDOG; | |
692 | ||
693 | RESET_STAT_INC(sc, type); | |
694 | #endif | |
236de514 | 695 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
e3927007 | 696 | goto out; |
063d8be3 | 697 | } |
ff37e337 | 698 | |
8b3f4616 FF |
699 | /* |
700 | * Only run the baseband hang check if beacons stop working in AP or | |
701 | * IBSS mode, because it has a high false positive rate. For station | |
702 | * mode it should not be necessary, since the upper layers will detect | |
703 | * this through a beacon miss automatically and the following channel | |
704 | * change will trigger a hardware reset anyway | |
705 | */ | |
706 | if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 && | |
707 | !ath9k_hw_check_alive(ah)) | |
347809fc FF |
708 | ieee80211_queue_work(sc->hw, &sc->hw_check_work); |
709 | ||
4105f807 RM |
710 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
711 | /* | |
712 | * TSF sync does not look correct; remain awake to sync with | |
713 | * the next Beacon. | |
714 | */ | |
715 | ath_dbg(common, ATH_DBG_PS, | |
716 | "TSFOOR - Sync with next Beacon\n"); | |
e8fe7336 | 717 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
4105f807 RM |
718 | } |
719 | ||
b5c80475 FF |
720 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
721 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
722 | ATH9K_INT_RXORN); | |
723 | else | |
724 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
725 | ||
726 | if (status & rxmask) { | |
b5c80475 FF |
727 | /* Check for high priority Rx first */ |
728 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
729 | (status & ATH9K_INT_RXHP)) | |
730 | ath_rx_tasklet(sc, 0, true); | |
731 | ||
732 | ath_rx_tasklet(sc, 0, false); | |
ff37e337 S |
733 | } |
734 | ||
e5003249 VT |
735 | if (status & ATH9K_INT_TX) { |
736 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
737 | ath_tx_edma_tasklet(sc); | |
738 | else | |
739 | ath_tx_tasklet(sc); | |
740 | } | |
063d8be3 | 741 | |
766ec4a9 | 742 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
ebb8e1d7 VT |
743 | if (status & ATH9K_INT_GENTIMER) |
744 | ath_gen_timer_isr(sc->sc_ah); | |
745 | ||
19686ddf MSS |
746 | if (status & ATH9K_INT_MCI) |
747 | ath_mci_intr(sc); | |
748 | ||
e3927007 | 749 | out: |
ff37e337 | 750 | /* re-enable hardware interrupt */ |
4df3071e | 751 | ath9k_hw_enable_interrupts(ah); |
6a6733f2 | 752 | |
52671e43 | 753 | spin_unlock(&sc->sc_pcu_lock); |
153e080d | 754 | ath9k_ps_restore(sc); |
ff37e337 S |
755 | } |
756 | ||
6baff7f9 | 757 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 758 | { |
063d8be3 S |
759 | #define SCHED_INTR ( \ |
760 | ATH9K_INT_FATAL | \ | |
a4d86d95 | 761 | ATH9K_INT_BB_WATCHDOG | \ |
063d8be3 S |
762 | ATH9K_INT_RXORN | \ |
763 | ATH9K_INT_RXEOL | \ | |
764 | ATH9K_INT_RX | \ | |
b5c80475 FF |
765 | ATH9K_INT_RXLP | \ |
766 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
767 | ATH9K_INT_TX | \ |
768 | ATH9K_INT_BMISS | \ | |
769 | ATH9K_INT_CST | \ | |
ebb8e1d7 | 770 | ATH9K_INT_TSFOOR | \ |
40dc5392 MSS |
771 | ATH9K_INT_GENTIMER | \ |
772 | ATH9K_INT_MCI) | |
063d8be3 | 773 | |
ff37e337 | 774 | struct ath_softc *sc = dev; |
cbe61d8a | 775 | struct ath_hw *ah = sc->sc_ah; |
b5bfc568 | 776 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
777 | enum ath9k_int status; |
778 | bool sched = false; | |
779 | ||
063d8be3 S |
780 | /* |
781 | * The hardware is not ready/present, don't | |
782 | * touch anything. Note this can happen early | |
783 | * on if the IRQ is shared. | |
784 | */ | |
785 | if (sc->sc_flags & SC_OP_INVALID) | |
786 | return IRQ_NONE; | |
ff37e337 | 787 | |
063d8be3 S |
788 | |
789 | /* shared irq, not for us */ | |
790 | ||
153e080d | 791 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 792 | return IRQ_NONE; |
063d8be3 S |
793 | |
794 | /* | |
795 | * Figure out the reason(s) for the interrupt. Note | |
796 | * that the hal returns a pseudo-ISR that may include | |
797 | * bits we haven't explicitly enabled so we mask the | |
798 | * value to insure we only process bits we requested. | |
799 | */ | |
800 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 801 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 802 | |
063d8be3 S |
803 | /* |
804 | * If there are no status bits set, then this interrupt was not | |
805 | * for me (should have been caught above). | |
806 | */ | |
153e080d | 807 | if (!status) |
063d8be3 | 808 | return IRQ_NONE; |
ff37e337 | 809 | |
063d8be3 S |
810 | /* Cache the status */ |
811 | sc->intrstatus = status; | |
812 | ||
813 | if (status & SCHED_INTR) | |
814 | sched = true; | |
815 | ||
816 | /* | |
817 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
818 | * chip immediately. | |
819 | */ | |
b5c80475 FF |
820 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
821 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
822 | goto chip_reset; |
823 | ||
08578b8f LR |
824 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
825 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
b5bfc568 FF |
826 | |
827 | spin_lock(&common->cc_lock); | |
828 | ath_hw_cycle_counters_update(common); | |
08578b8f | 829 | ar9003_hw_bb_watchdog_dbg_info(ah); |
b5bfc568 FF |
830 | spin_unlock(&common->cc_lock); |
831 | ||
08578b8f LR |
832 | goto chip_reset; |
833 | } | |
834 | ||
063d8be3 S |
835 | if (status & ATH9K_INT_SWBA) |
836 | tasklet_schedule(&sc->bcon_tasklet); | |
837 | ||
838 | if (status & ATH9K_INT_TXURN) | |
839 | ath9k_hw_updatetxtriglevel(ah, true); | |
840 | ||
0682c9b5 RM |
841 | if (status & ATH9K_INT_RXEOL) { |
842 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
72d874c6 | 843 | ath9k_hw_set_interrupts(ah); |
b5c80475 FF |
844 | } |
845 | ||
063d8be3 | 846 | if (status & ATH9K_INT_MIB) { |
ff37e337 | 847 | /* |
063d8be3 S |
848 | * Disable interrupts until we service the MIB |
849 | * interrupt; otherwise it will continue to | |
850 | * fire. | |
ff37e337 | 851 | */ |
4df3071e | 852 | ath9k_hw_disable_interrupts(ah); |
063d8be3 S |
853 | /* |
854 | * Let the hal handle the event. We assume | |
855 | * it will clear whatever condition caused | |
856 | * the interrupt. | |
857 | */ | |
88eac2da | 858 | spin_lock(&common->cc_lock); |
bfc472bb | 859 | ath9k_hw_proc_mib_event(ah); |
88eac2da | 860 | spin_unlock(&common->cc_lock); |
4df3071e | 861 | ath9k_hw_enable_interrupts(ah); |
063d8be3 | 862 | } |
ff37e337 | 863 | |
153e080d VT |
864 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
865 | if (status & ATH9K_INT_TIM_TIMER) { | |
ff9f0b63 LR |
866 | if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) |
867 | goto chip_reset; | |
063d8be3 S |
868 | /* Clear RxAbort bit so that we can |
869 | * receive frames */ | |
9ecdef4b | 870 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
153e080d | 871 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 872 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
ff37e337 | 873 | } |
063d8be3 S |
874 | |
875 | chip_reset: | |
ff37e337 | 876 | |
817e11de S |
877 | ath_debug_stat_interrupt(sc, status); |
878 | ||
ff37e337 | 879 | if (sched) { |
4df3071e FF |
880 | /* turn off every interrupt */ |
881 | ath9k_hw_disable_interrupts(ah); | |
ff37e337 S |
882 | tasklet_schedule(&sc->intr_tq); |
883 | } | |
884 | ||
885 | return IRQ_HANDLED; | |
063d8be3 S |
886 | |
887 | #undef SCHED_INTR | |
ff37e337 S |
888 | } |
889 | ||
236de514 | 890 | static int ath_reset(struct ath_softc *sc, bool retry_tx) |
ff37e337 | 891 | { |
ae8d2858 | 892 | int r; |
ff37e337 | 893 | |
783cd01e | 894 | ath9k_ps_wakeup(sc); |
6a6733f2 | 895 | |
9adcf440 | 896 | r = ath_reset_internal(sc, NULL, retry_tx); |
ff37e337 S |
897 | |
898 | if (retry_tx) { | |
899 | int i; | |
900 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
901 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
902 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
903 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
904 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
905 | } |
906 | } | |
907 | } | |
908 | ||
783cd01e | 909 | ath9k_ps_restore(sc); |
2ab81d4a | 910 | |
ae8d2858 | 911 | return r; |
ff37e337 S |
912 | } |
913 | ||
236de514 FF |
914 | void ath_reset_work(struct work_struct *work) |
915 | { | |
916 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); | |
917 | ||
236de514 | 918 | ath_reset(sc, true); |
236de514 FF |
919 | } |
920 | ||
e8cfe9f8 FF |
921 | void ath_hw_check(struct work_struct *work) |
922 | { | |
923 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work); | |
924 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
925 | unsigned long flags; | |
926 | int busy; | |
927 | ||
928 | ath9k_ps_wakeup(sc); | |
929 | if (ath9k_hw_check_alive(sc->sc_ah)) | |
930 | goto out; | |
931 | ||
932 | spin_lock_irqsave(&common->cc_lock, flags); | |
933 | busy = ath_update_survey_stats(sc); | |
934 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
935 | ||
936 | ath_dbg(common, ATH_DBG_RESET, "Possible baseband hang, " | |
937 | "busy=%d (try %d)\n", busy, sc->hw_busy_count + 1); | |
938 | if (busy >= 99) { | |
030d6294 FF |
939 | if (++sc->hw_busy_count >= 3) { |
940 | RESET_STAT_INC(sc, RESET_TYPE_BB_HANG); | |
9adcf440 | 941 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
030d6294 | 942 | } |
e8cfe9f8 FF |
943 | |
944 | } else if (busy >= 0) | |
945 | sc->hw_busy_count = 0; | |
946 | ||
947 | out: | |
948 | ath9k_ps_restore(sc); | |
949 | } | |
950 | ||
951 | static void ath_hw_pll_rx_hang_check(struct ath_softc *sc, u32 pll_sqsum) | |
952 | { | |
953 | static int count; | |
954 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
955 | ||
956 | if (pll_sqsum >= 0x40000) { | |
957 | count++; | |
958 | if (count == 3) { | |
959 | /* Rx is hung for more than 500ms. Reset it */ | |
960 | ath_dbg(common, ATH_DBG_RESET, | |
961 | "Possible RX hang, resetting"); | |
030d6294 | 962 | RESET_STAT_INC(sc, RESET_TYPE_PLL_HANG); |
9adcf440 | 963 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
e8cfe9f8 FF |
964 | count = 0; |
965 | } | |
966 | } else | |
967 | count = 0; | |
968 | } | |
969 | ||
970 | void ath_hw_pll_work(struct work_struct *work) | |
971 | { | |
972 | struct ath_softc *sc = container_of(work, struct ath_softc, | |
973 | hw_pll_work.work); | |
974 | u32 pll_sqsum; | |
975 | ||
976 | if (AR_SREV_9485(sc->sc_ah)) { | |
977 | ||
978 | ath9k_ps_wakeup(sc); | |
979 | pll_sqsum = ar9003_get_pll_sqsum_dvc(sc->sc_ah); | |
980 | ath9k_ps_restore(sc); | |
981 | ||
982 | ath_hw_pll_rx_hang_check(sc, pll_sqsum); | |
983 | ||
984 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/5); | |
985 | } | |
986 | } | |
987 | ||
ff37e337 S |
988 | /**********************/ |
989 | /* mac80211 callbacks */ | |
990 | /**********************/ | |
991 | ||
8feceb67 | 992 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 993 | { |
9ac58615 | 994 | struct ath_softc *sc = hw->priv; |
af03abec | 995 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 996 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 997 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 998 | struct ath9k_channel *init_channel; |
82880a7c | 999 | int r; |
f078f209 | 1000 | |
226afe68 JP |
1001 | ath_dbg(common, ATH_DBG_CONFIG, |
1002 | "Starting driver with initial channel: %d MHz\n", | |
1003 | curchan->center_freq); | |
f078f209 | 1004 | |
f62d816f FF |
1005 | ath9k_ps_wakeup(sc); |
1006 | ||
141b38b6 S |
1007 | mutex_lock(&sc->mutex); |
1008 | ||
8feceb67 | 1009 | /* setup initial channel */ |
82880a7c | 1010 | sc->chan_idx = curchan->hw_value; |
f078f209 | 1011 | |
c344c9cb | 1012 | init_channel = ath9k_cmn_get_curchannel(hw, ah); |
ff37e337 S |
1013 | |
1014 | /* Reset SERDES registers */ | |
84c87dc8 | 1015 | ath9k_hw_configpcipowersave(ah, false); |
ff37e337 S |
1016 | |
1017 | /* | |
1018 | * The basic interface to setting the hardware in a good | |
1019 | * state is ``reset''. On return the hardware is known to | |
1020 | * be powered up and with interrupts disabled. This must | |
1021 | * be followed by initialization of the appropriate bits | |
1022 | * and then setup of the interrupt mask. | |
1023 | */ | |
4bdd1e97 | 1024 | spin_lock_bh(&sc->sc_pcu_lock); |
c0c11741 FF |
1025 | |
1026 | atomic_set(&ah->intr_ref_cnt, -1); | |
1027 | ||
20bd2a09 | 1028 | r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); |
ae8d2858 | 1029 | if (r) { |
3800276a JP |
1030 | ath_err(common, |
1031 | "Unable to reset hardware; reset status %d (freq %u MHz)\n", | |
1032 | r, curchan->center_freq); | |
4bdd1e97 | 1033 | spin_unlock_bh(&sc->sc_pcu_lock); |
141b38b6 | 1034 | goto mutex_unlock; |
ff37e337 | 1035 | } |
ff37e337 | 1036 | |
ff37e337 | 1037 | /* Setup our intr mask. */ |
b5c80475 FF |
1038 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
1039 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
1040 | ATH9K_INT_GLOBAL; | |
1041 | ||
1042 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f LR |
1043 | ah->imask |= ATH9K_INT_RXHP | |
1044 | ATH9K_INT_RXLP | | |
1045 | ATH9K_INT_BB_WATCHDOG; | |
b5c80475 FF |
1046 | else |
1047 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 1048 | |
364734fa | 1049 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 1050 | |
af03abec | 1051 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 1052 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 1053 | |
40dc5392 MSS |
1054 | if (ah->caps.hw_caps & ATH9K_HW_CAP_MCI) |
1055 | ah->imask |= ATH9K_INT_MCI; | |
1056 | ||
ff37e337 | 1057 | sc->sc_flags &= ~SC_OP_INVALID; |
5f841b41 | 1058 | sc->sc_ah->is_monitoring = false; |
ff37e337 S |
1059 | |
1060 | /* Disable BMISS interrupt when we're not associated */ | |
3069168c | 1061 | ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
ff37e337 | 1062 | |
9adcf440 FF |
1063 | if (!ath_complete_reset(sc, false)) { |
1064 | r = -EIO; | |
1065 | spin_unlock_bh(&sc->sc_pcu_lock); | |
1066 | goto mutex_unlock; | |
1067 | } | |
ff37e337 | 1068 | |
c0c11741 FF |
1069 | if (ah->led_pin >= 0) { |
1070 | ath9k_hw_cfg_output(ah, ah->led_pin, | |
1071 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
1072 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); | |
1073 | } | |
1074 | ||
1075 | /* | |
1076 | * Reset key cache to sane defaults (all entries cleared) instead of | |
1077 | * semi-random values after suspend/resume. | |
1078 | */ | |
1079 | ath9k_cmn_init_crypto(sc->sc_ah); | |
1080 | ||
9adcf440 | 1081 | spin_unlock_bh(&sc->sc_pcu_lock); |
164ace38 | 1082 | |
766ec4a9 LR |
1083 | if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && |
1084 | !ah->btcoex_hw.enabled) { | |
7dc181c2 RM |
1085 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_MCI)) |
1086 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, | |
1087 | AR_STOMP_LOW_WLAN_WGHT); | |
af03abec | 1088 | ath9k_hw_btcoex_enable(ah); |
f985ad12 | 1089 | |
766ec4a9 | 1090 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1091 | ath9k_btcoex_timer_resume(sc); |
1773912b VT |
1092 | } |
1093 | ||
8060e169 VT |
1094 | if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en) |
1095 | common->bus_ops->extn_synch_en(common); | |
1096 | ||
141b38b6 S |
1097 | mutex_unlock: |
1098 | mutex_unlock(&sc->mutex); | |
1099 | ||
f62d816f FF |
1100 | ath9k_ps_restore(sc); |
1101 | ||
ae8d2858 | 1102 | return r; |
f078f209 LR |
1103 | } |
1104 | ||
7bb45683 | 1105 | static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) |
f078f209 | 1106 | { |
9ac58615 | 1107 | struct ath_softc *sc = hw->priv; |
c46917bb | 1108 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1109 | struct ath_tx_control txctl; |
1bc14880 | 1110 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
528f0c6b | 1111 | |
96148326 | 1112 | if (sc->ps_enabled) { |
dc8c4585 JM |
1113 | /* |
1114 | * mac80211 does not set PM field for normal data frames, so we | |
1115 | * need to update that based on the current PS mode. | |
1116 | */ | |
1117 | if (ieee80211_is_data(hdr->frame_control) && | |
1118 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
1119 | !ieee80211_has_pm(hdr->frame_control)) { | |
226afe68 JP |
1120 | ath_dbg(common, ATH_DBG_PS, |
1121 | "Add PM=1 for a TX frame while in PS mode\n"); | |
dc8c4585 JM |
1122 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
1123 | } | |
1124 | } | |
1125 | ||
c8e8868e FF |
1126 | /* |
1127 | * Cannot tx while the hardware is in full sleep, it first needs a full | |
1128 | * chip reset to recover from that | |
1129 | */ | |
1130 | if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) | |
1131 | goto exit; | |
1132 | ||
9a23f9ca JM |
1133 | if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { |
1134 | /* | |
1135 | * We are using PS-Poll and mac80211 can request TX while in | |
1136 | * power save mode. Need to wake up hardware for the TX to be | |
1137 | * completed and if needed, also for RX of buffered frames. | |
1138 | */ | |
9a23f9ca | 1139 | ath9k_ps_wakeup(sc); |
fdf76622 VT |
1140 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
1141 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 1142 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
226afe68 JP |
1143 | ath_dbg(common, ATH_DBG_PS, |
1144 | "Sending PS-Poll to pick a buffered frame\n"); | |
1b04b930 | 1145 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 1146 | } else { |
226afe68 JP |
1147 | ath_dbg(common, ATH_DBG_PS, |
1148 | "Wake up to complete TX\n"); | |
1b04b930 | 1149 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
1150 | } |
1151 | /* | |
1152 | * The actual restore operation will happen only after | |
1153 | * the sc_flags bit is cleared. We are just dropping | |
1154 | * the ps_usecount here. | |
1155 | */ | |
1156 | ath9k_ps_restore(sc); | |
1157 | } | |
1158 | ||
528f0c6b | 1159 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
066dae93 | 1160 | txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; |
528f0c6b | 1161 | |
226afe68 | 1162 | ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 1163 | |
c52f33d0 | 1164 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
226afe68 | 1165 | ath_dbg(common, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 1166 | goto exit; |
8feceb67 VT |
1167 | } |
1168 | ||
7bb45683 | 1169 | return; |
528f0c6b S |
1170 | exit: |
1171 | dev_kfree_skb_any(skb); | |
f078f209 LR |
1172 | } |
1173 | ||
8feceb67 | 1174 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 1175 | { |
9ac58615 | 1176 | struct ath_softc *sc = hw->priv; |
af03abec | 1177 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1178 | struct ath_common *common = ath9k_hw_common(ah); |
c0c11741 | 1179 | bool prev_idle; |
f078f209 | 1180 | |
4c483817 S |
1181 | mutex_lock(&sc->mutex); |
1182 | ||
9adcf440 | 1183 | ath_cancel_work(sc); |
c94dbff7 | 1184 | |
9c84b797 | 1185 | if (sc->sc_flags & SC_OP_INVALID) { |
226afe68 | 1186 | ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); |
4c483817 | 1187 | mutex_unlock(&sc->mutex); |
9c84b797 S |
1188 | return; |
1189 | } | |
8feceb67 | 1190 | |
3867cf6a S |
1191 | /* Ensure HW is awake when we try to shut it down. */ |
1192 | ath9k_ps_wakeup(sc); | |
1193 | ||
766ec4a9 | 1194 | if (ah->btcoex_hw.enabled) { |
af03abec | 1195 | ath9k_hw_btcoex_disable(ah); |
766ec4a9 | 1196 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1197 | ath9k_btcoex_timer_pause(sc); |
7dc181c2 | 1198 | ath_mci_flush_profile(&sc->btcoex.mci); |
1773912b VT |
1199 | } |
1200 | ||
6a6733f2 LR |
1201 | spin_lock_bh(&sc->sc_pcu_lock); |
1202 | ||
203043f5 SG |
1203 | /* prevent tasklets to enable interrupts once we disable them */ |
1204 | ah->imask &= ~ATH9K_INT_GLOBAL; | |
1205 | ||
ff37e337 S |
1206 | /* make sure h/w will not generate any interrupt |
1207 | * before setting the invalid flag. */ | |
4df3071e | 1208 | ath9k_hw_disable_interrupts(ah); |
ff37e337 | 1209 | |
c0c11741 FF |
1210 | spin_unlock_bh(&sc->sc_pcu_lock); |
1211 | ||
1212 | /* we can now sync irq and kill any running tasklets, since we already | |
1213 | * disabled interrupts and not holding a spin lock */ | |
1214 | synchronize_irq(sc->irq); | |
1215 | tasklet_kill(&sc->intr_tq); | |
1216 | tasklet_kill(&sc->bcon_tasklet); | |
1217 | ||
1218 | prev_idle = sc->ps_idle; | |
1219 | sc->ps_idle = true; | |
1220 | ||
1221 | spin_lock_bh(&sc->sc_pcu_lock); | |
1222 | ||
1223 | if (ah->led_pin >= 0) { | |
1224 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); | |
1225 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
1226 | } | |
1227 | ||
1228 | ath_prepare_reset(sc, false, true); | |
ff37e337 | 1229 | |
0d95521e FF |
1230 | if (sc->rx.frag) { |
1231 | dev_kfree_skb_any(sc->rx.frag); | |
1232 | sc->rx.frag = NULL; | |
1233 | } | |
1234 | ||
c0c11741 FF |
1235 | if (!ah->curchan) |
1236 | ah->curchan = ath9k_cmn_get_curchannel(hw, ah); | |
6a6733f2 | 1237 | |
c0c11741 FF |
1238 | ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
1239 | ath9k_hw_phy_disable(ah); | |
6a6733f2 | 1240 | |
c0c11741 | 1241 | ath9k_hw_configpcipowersave(ah, true); |
203043f5 | 1242 | |
c0c11741 | 1243 | spin_unlock_bh(&sc->sc_pcu_lock); |
3867cf6a | 1244 | |
c0c11741 | 1245 | ath9k_ps_restore(sc); |
ff37e337 S |
1246 | |
1247 | sc->sc_flags |= SC_OP_INVALID; | |
c0c11741 | 1248 | sc->ps_idle = prev_idle; |
500c064d | 1249 | |
141b38b6 S |
1250 | mutex_unlock(&sc->mutex); |
1251 | ||
226afe68 | 1252 | ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
1253 | } |
1254 | ||
4801416c BG |
1255 | bool ath9k_uses_beacons(int type) |
1256 | { | |
1257 | switch (type) { | |
1258 | case NL80211_IFTYPE_AP: | |
1259 | case NL80211_IFTYPE_ADHOC: | |
1260 | case NL80211_IFTYPE_MESH_POINT: | |
1261 | return true; | |
1262 | default: | |
1263 | return false; | |
1264 | } | |
1265 | } | |
1266 | ||
1267 | static void ath9k_reclaim_beacon(struct ath_softc *sc, | |
1268 | struct ieee80211_vif *vif) | |
f078f209 | 1269 | { |
1ed32e4f | 1270 | struct ath_vif *avp = (void *)vif->drv_priv; |
8feceb67 | 1271 | |
014cf3bb | 1272 | ath9k_set_beaconing_status(sc, false); |
4801416c | 1273 | ath_beacon_return(sc, avp); |
014cf3bb | 1274 | ath9k_set_beaconing_status(sc, true); |
4801416c | 1275 | sc->sc_flags &= ~SC_OP_BEACONS; |
4801416c BG |
1276 | } |
1277 | ||
1278 | static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) | |
1279 | { | |
1280 | struct ath9k_vif_iter_data *iter_data = data; | |
1281 | int i; | |
1282 | ||
1283 | if (iter_data->hw_macaddr) | |
1284 | for (i = 0; i < ETH_ALEN; i++) | |
1285 | iter_data->mask[i] &= | |
1286 | ~(iter_data->hw_macaddr[i] ^ mac[i]); | |
141b38b6 | 1287 | |
1ed32e4f | 1288 | switch (vif->type) { |
4801416c BG |
1289 | case NL80211_IFTYPE_AP: |
1290 | iter_data->naps++; | |
f078f209 | 1291 | break; |
4801416c BG |
1292 | case NL80211_IFTYPE_STATION: |
1293 | iter_data->nstations++; | |
e51f3eff | 1294 | break; |
05c914fe | 1295 | case NL80211_IFTYPE_ADHOC: |
4801416c BG |
1296 | iter_data->nadhocs++; |
1297 | break; | |
9cb5412b | 1298 | case NL80211_IFTYPE_MESH_POINT: |
4801416c BG |
1299 | iter_data->nmeshes++; |
1300 | break; | |
1301 | case NL80211_IFTYPE_WDS: | |
1302 | iter_data->nwds++; | |
f078f209 LR |
1303 | break; |
1304 | default: | |
4801416c BG |
1305 | iter_data->nothers++; |
1306 | break; | |
f078f209 | 1307 | } |
4801416c | 1308 | } |
f078f209 | 1309 | |
4801416c BG |
1310 | /* Called with sc->mutex held. */ |
1311 | void ath9k_calculate_iter_data(struct ieee80211_hw *hw, | |
1312 | struct ieee80211_vif *vif, | |
1313 | struct ath9k_vif_iter_data *iter_data) | |
1314 | { | |
9ac58615 | 1315 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1316 | struct ath_hw *ah = sc->sc_ah; |
1317 | struct ath_common *common = ath9k_hw_common(ah); | |
8feceb67 | 1318 | |
4801416c BG |
1319 | /* |
1320 | * Use the hardware MAC address as reference, the hardware uses it | |
1321 | * together with the BSSID mask when matching addresses. | |
1322 | */ | |
1323 | memset(iter_data, 0, sizeof(*iter_data)); | |
1324 | iter_data->hw_macaddr = common->macaddr; | |
1325 | memset(&iter_data->mask, 0xff, ETH_ALEN); | |
5640b08e | 1326 | |
4801416c BG |
1327 | if (vif) |
1328 | ath9k_vif_iter(iter_data, vif->addr, vif); | |
1329 | ||
1330 | /* Get list of all active MAC addresses */ | |
4801416c BG |
1331 | ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter, |
1332 | iter_data); | |
4801416c | 1333 | } |
8ca21f01 | 1334 | |
4801416c BG |
1335 | /* Called with sc->mutex held. */ |
1336 | static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, | |
1337 | struct ieee80211_vif *vif) | |
1338 | { | |
9ac58615 | 1339 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1340 | struct ath_hw *ah = sc->sc_ah; |
1341 | struct ath_common *common = ath9k_hw_common(ah); | |
1342 | struct ath9k_vif_iter_data iter_data; | |
8ca21f01 | 1343 | |
4801416c | 1344 | ath9k_calculate_iter_data(hw, vif, &iter_data); |
2c3db3d5 | 1345 | |
4801416c BG |
1346 | /* Set BSSID mask. */ |
1347 | memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); | |
1348 | ath_hw_setbssidmask(common); | |
1349 | ||
1350 | /* Set op-mode & TSF */ | |
1351 | if (iter_data.naps > 0) { | |
3069168c | 1352 | ath9k_hw_set_tsfadjust(ah, 1); |
b238e90e | 1353 | sc->sc_flags |= SC_OP_TSF_RESET; |
4801416c BG |
1354 | ah->opmode = NL80211_IFTYPE_AP; |
1355 | } else { | |
1356 | ath9k_hw_set_tsfadjust(ah, 0); | |
1357 | sc->sc_flags &= ~SC_OP_TSF_RESET; | |
5640b08e | 1358 | |
fd5999cf JC |
1359 | if (iter_data.nmeshes) |
1360 | ah->opmode = NL80211_IFTYPE_MESH_POINT; | |
1361 | else if (iter_data.nwds) | |
4801416c BG |
1362 | ah->opmode = NL80211_IFTYPE_AP; |
1363 | else if (iter_data.nadhocs) | |
1364 | ah->opmode = NL80211_IFTYPE_ADHOC; | |
1365 | else | |
1366 | ah->opmode = NL80211_IFTYPE_STATION; | |
1367 | } | |
5640b08e | 1368 | |
4e30ffa2 VN |
1369 | /* |
1370 | * Enable MIB interrupts when there are hardware phy counters. | |
4e30ffa2 | 1371 | */ |
4801416c | 1372 | if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) { |
3448f912 LR |
1373 | if (ah->config.enable_ani) |
1374 | ah->imask |= ATH9K_INT_MIB; | |
3069168c | 1375 | ah->imask |= ATH9K_INT_TSFOOR; |
4801416c BG |
1376 | } else { |
1377 | ah->imask &= ~ATH9K_INT_MIB; | |
1378 | ah->imask &= ~ATH9K_INT_TSFOOR; | |
4af9cf4f S |
1379 | } |
1380 | ||
72d874c6 | 1381 | ath9k_hw_set_interrupts(ah); |
4e30ffa2 | 1382 | |
4801416c | 1383 | /* Set up ANI */ |
2e5ef459 | 1384 | if (iter_data.naps > 0) { |
729da390 | 1385 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; |
05c0be2f MSS |
1386 | |
1387 | if (!common->disable_ani) { | |
1388 | sc->sc_flags |= SC_OP_ANI_RUN; | |
1389 | ath_start_ani(common); | |
1390 | } | |
1391 | ||
f60c49b6 RM |
1392 | } else { |
1393 | sc->sc_flags &= ~SC_OP_ANI_RUN; | |
1394 | del_timer_sync(&common->ani.timer); | |
6c3118e2 | 1395 | } |
4801416c | 1396 | } |
6f255425 | 1397 | |
4801416c BG |
1398 | /* Called with sc->mutex held, vif counts set up properly. */ |
1399 | static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw, | |
1400 | struct ieee80211_vif *vif) | |
1401 | { | |
9ac58615 | 1402 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1403 | |
1404 | ath9k_calculate_summary_state(hw, vif); | |
1405 | ||
1406 | if (ath9k_uses_beacons(vif->type)) { | |
1407 | int error; | |
4801416c BG |
1408 | /* This may fail because upper levels do not have beacons |
1409 | * properly configured yet. That's OK, we assume it | |
1410 | * will be properly configured and then we will be notified | |
1411 | * in the info_changed method and set up beacons properly | |
1412 | * there. | |
1413 | */ | |
014cf3bb | 1414 | ath9k_set_beaconing_status(sc, false); |
9ac58615 | 1415 | error = ath_beacon_alloc(sc, vif); |
391bd1c4 | 1416 | if (!error) |
4801416c | 1417 | ath_beacon_config(sc, vif); |
014cf3bb | 1418 | ath9k_set_beaconing_status(sc, true); |
4801416c | 1419 | } |
f078f209 LR |
1420 | } |
1421 | ||
4801416c BG |
1422 | |
1423 | static int ath9k_add_interface(struct ieee80211_hw *hw, | |
1424 | struct ieee80211_vif *vif) | |
6b3b991d | 1425 | { |
9ac58615 | 1426 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1427 | struct ath_hw *ah = sc->sc_ah; |
1428 | struct ath_common *common = ath9k_hw_common(ah); | |
4801416c | 1429 | int ret = 0; |
6b3b991d | 1430 | |
96f372c9 | 1431 | ath9k_ps_wakeup(sc); |
4801416c | 1432 | mutex_lock(&sc->mutex); |
6b3b991d | 1433 | |
4801416c BG |
1434 | switch (vif->type) { |
1435 | case NL80211_IFTYPE_STATION: | |
1436 | case NL80211_IFTYPE_WDS: | |
1437 | case NL80211_IFTYPE_ADHOC: | |
1438 | case NL80211_IFTYPE_AP: | |
1439 | case NL80211_IFTYPE_MESH_POINT: | |
1440 | break; | |
1441 | default: | |
1442 | ath_err(common, "Interface type %d not yet supported\n", | |
1443 | vif->type); | |
1444 | ret = -EOPNOTSUPP; | |
1445 | goto out; | |
1446 | } | |
6b3b991d | 1447 | |
4801416c BG |
1448 | if (ath9k_uses_beacons(vif->type)) { |
1449 | if (sc->nbcnvifs >= ATH_BCBUF) { | |
1450 | ath_err(common, "Not enough beacon buffers when adding" | |
1451 | " new interface of type: %i\n", | |
1452 | vif->type); | |
1453 | ret = -ENOBUFS; | |
1454 | goto out; | |
1455 | } | |
1456 | } | |
1457 | ||
59575d1c RM |
1458 | if ((ah->opmode == NL80211_IFTYPE_ADHOC) || |
1459 | ((vif->type == NL80211_IFTYPE_ADHOC) && | |
1460 | sc->nvifs > 0)) { | |
4801416c BG |
1461 | ath_err(common, "Cannot create ADHOC interface when other" |
1462 | " interfaces already exist.\n"); | |
1463 | ret = -EINVAL; | |
1464 | goto out; | |
6b3b991d | 1465 | } |
4801416c BG |
1466 | |
1467 | ath_dbg(common, ATH_DBG_CONFIG, | |
1468 | "Attach a VIF of type: %d\n", vif->type); | |
1469 | ||
4801416c BG |
1470 | sc->nvifs++; |
1471 | ||
1472 | ath9k_do_vif_add_setup(hw, vif); | |
1473 | out: | |
1474 | mutex_unlock(&sc->mutex); | |
96f372c9 | 1475 | ath9k_ps_restore(sc); |
4801416c | 1476 | return ret; |
6b3b991d RM |
1477 | } |
1478 | ||
1479 | static int ath9k_change_interface(struct ieee80211_hw *hw, | |
1480 | struct ieee80211_vif *vif, | |
1481 | enum nl80211_iftype new_type, | |
1482 | bool p2p) | |
1483 | { | |
9ac58615 | 1484 | struct ath_softc *sc = hw->priv; |
6b3b991d | 1485 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
6dab55bf | 1486 | int ret = 0; |
6b3b991d RM |
1487 | |
1488 | ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n"); | |
1489 | mutex_lock(&sc->mutex); | |
96f372c9 | 1490 | ath9k_ps_wakeup(sc); |
6b3b991d | 1491 | |
4801416c BG |
1492 | /* See if new interface type is valid. */ |
1493 | if ((new_type == NL80211_IFTYPE_ADHOC) && | |
1494 | (sc->nvifs > 1)) { | |
1495 | ath_err(common, "When using ADHOC, it must be the only" | |
1496 | " interface.\n"); | |
1497 | ret = -EINVAL; | |
1498 | goto out; | |
1499 | } | |
1500 | ||
1501 | if (ath9k_uses_beacons(new_type) && | |
1502 | !ath9k_uses_beacons(vif->type)) { | |
6b3b991d RM |
1503 | if (sc->nbcnvifs >= ATH_BCBUF) { |
1504 | ath_err(common, "No beacon slot available\n"); | |
6dab55bf DC |
1505 | ret = -ENOBUFS; |
1506 | goto out; | |
6b3b991d | 1507 | } |
6b3b991d | 1508 | } |
4801416c BG |
1509 | |
1510 | /* Clean up old vif stuff */ | |
1511 | if (ath9k_uses_beacons(vif->type)) | |
1512 | ath9k_reclaim_beacon(sc, vif); | |
1513 | ||
1514 | /* Add new settings */ | |
6b3b991d RM |
1515 | vif->type = new_type; |
1516 | vif->p2p = p2p; | |
1517 | ||
4801416c | 1518 | ath9k_do_vif_add_setup(hw, vif); |
6dab55bf | 1519 | out: |
96f372c9 | 1520 | ath9k_ps_restore(sc); |
6b3b991d | 1521 | mutex_unlock(&sc->mutex); |
6dab55bf | 1522 | return ret; |
6b3b991d RM |
1523 | } |
1524 | ||
8feceb67 | 1525 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1526 | struct ieee80211_vif *vif) |
f078f209 | 1527 | { |
9ac58615 | 1528 | struct ath_softc *sc = hw->priv; |
c46917bb | 1529 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
f078f209 | 1530 | |
226afe68 | 1531 | ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 1532 | |
96f372c9 | 1533 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1534 | mutex_lock(&sc->mutex); |
1535 | ||
4801416c | 1536 | sc->nvifs--; |
580f0b8a | 1537 | |
8feceb67 | 1538 | /* Reclaim beacon resources */ |
4801416c | 1539 | if (ath9k_uses_beacons(vif->type)) |
6b3b991d | 1540 | ath9k_reclaim_beacon(sc, vif); |
2c3db3d5 | 1541 | |
4801416c | 1542 | ath9k_calculate_summary_state(hw, NULL); |
141b38b6 S |
1543 | |
1544 | mutex_unlock(&sc->mutex); | |
96f372c9 | 1545 | ath9k_ps_restore(sc); |
f078f209 LR |
1546 | } |
1547 | ||
fbab7390 | 1548 | static void ath9k_enable_ps(struct ath_softc *sc) |
3f7c5c10 | 1549 | { |
3069168c PR |
1550 | struct ath_hw *ah = sc->sc_ah; |
1551 | ||
3f7c5c10 | 1552 | sc->ps_enabled = true; |
3069168c PR |
1553 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1554 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1555 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
72d874c6 | 1556 | ath9k_hw_set_interrupts(ah); |
3f7c5c10 | 1557 | } |
fdf76622 | 1558 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1559 | } |
3f7c5c10 SB |
1560 | } |
1561 | ||
845d708e SB |
1562 | static void ath9k_disable_ps(struct ath_softc *sc) |
1563 | { | |
1564 | struct ath_hw *ah = sc->sc_ah; | |
1565 | ||
1566 | sc->ps_enabled = false; | |
1567 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
1568 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | |
1569 | ath9k_hw_setrxabort(ah, 0); | |
1570 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | | |
1571 | PS_WAIT_FOR_CAB | | |
1572 | PS_WAIT_FOR_PSPOLL_DATA | | |
1573 | PS_WAIT_FOR_TX_ACK); | |
1574 | if (ah->imask & ATH9K_INT_TIM_TIMER) { | |
1575 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
72d874c6 | 1576 | ath9k_hw_set_interrupts(ah); |
845d708e SB |
1577 | } |
1578 | } | |
1579 | ||
1580 | } | |
1581 | ||
e8975581 | 1582 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1583 | { |
9ac58615 | 1584 | struct ath_softc *sc = hw->priv; |
3430098a FF |
1585 | struct ath_hw *ah = sc->sc_ah; |
1586 | struct ath_common *common = ath9k_hw_common(ah); | |
e8975581 | 1587 | struct ieee80211_conf *conf = &hw->conf; |
f078f209 | 1588 | |
c0c11741 | 1589 | ath9k_ps_wakeup(sc); |
aa33de09 | 1590 | mutex_lock(&sc->mutex); |
141b38b6 | 1591 | |
194b7c13 LR |
1592 | /* |
1593 | * Leave this as the first check because we need to turn on the | |
1594 | * radio if it was disabled before prior to processing the rest | |
1595 | * of the changes. Likewise we must only disable the radio towards | |
1596 | * the end. | |
1597 | */ | |
daa1b6ee | 1598 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
7545daf4 | 1599 | sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); |
daa1b6ee FF |
1600 | if (sc->ps_idle) |
1601 | ath_cancel_work(sc); | |
1602 | } | |
64839170 | 1603 | |
e7824a50 LR |
1604 | /* |
1605 | * We just prepare to enable PS. We have to wait until our AP has | |
1606 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1607 | * those ACKs and end up retransmitting the same null data frames. | |
1608 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1609 | */ | |
3cbb5dd7 | 1610 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
8ab2cd09 LR |
1611 | unsigned long flags; |
1612 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
fbab7390 SB |
1613 | if (conf->flags & IEEE80211_CONF_PS) |
1614 | ath9k_enable_ps(sc); | |
845d708e SB |
1615 | else |
1616 | ath9k_disable_ps(sc); | |
8ab2cd09 | 1617 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
3cbb5dd7 VN |
1618 | } |
1619 | ||
199afd9d S |
1620 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1621 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
226afe68 JP |
1622 | ath_dbg(common, ATH_DBG_CONFIG, |
1623 | "Monitor mode is enabled\n"); | |
5f841b41 RM |
1624 | sc->sc_ah->is_monitoring = true; |
1625 | } else { | |
226afe68 JP |
1626 | ath_dbg(common, ATH_DBG_CONFIG, |
1627 | "Monitor mode is disabled\n"); | |
5f841b41 | 1628 | sc->sc_ah->is_monitoring = false; |
199afd9d S |
1629 | } |
1630 | } | |
1631 | ||
4797938c | 1632 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
99405f93 | 1633 | struct ieee80211_channel *curchan = hw->conf.channel; |
e338a85e | 1634 | struct ath9k_channel old_chan; |
5f8e077c | 1635 | int pos = curchan->hw_value; |
3430098a FF |
1636 | int old_pos = -1; |
1637 | unsigned long flags; | |
1638 | ||
1639 | if (ah->curchan) | |
1640 | old_pos = ah->curchan - &ah->channels[0]; | |
ae5eb026 | 1641 | |
5ee08656 FF |
1642 | if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) |
1643 | sc->sc_flags |= SC_OP_OFFCHANNEL; | |
1644 | else | |
1645 | sc->sc_flags &= ~SC_OP_OFFCHANNEL; | |
0e2dedf9 | 1646 | |
8c79a610 BG |
1647 | ath_dbg(common, ATH_DBG_CONFIG, |
1648 | "Set channel: %d MHz type: %d\n", | |
1649 | curchan->center_freq, conf->channel_type); | |
f078f209 | 1650 | |
3430098a FF |
1651 | /* update survey stats for the old channel before switching */ |
1652 | spin_lock_irqsave(&common->cc_lock, flags); | |
1653 | ath_update_survey_stats(sc); | |
1654 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1655 | ||
e338a85e RM |
1656 | /* |
1657 | * Preserve the current channel values, before updating | |
1658 | * the same channel | |
1659 | */ | |
1660 | if (old_pos == pos) { | |
1661 | memcpy(&old_chan, &sc->sc_ah->channels[pos], | |
1662 | sizeof(struct ath9k_channel)); | |
1663 | ah->curchan = &old_chan; | |
1664 | } | |
1665 | ||
1666 | ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos], | |
1667 | curchan, conf->channel_type); | |
1668 | ||
3430098a FF |
1669 | /* |
1670 | * If the operating channel changes, change the survey in-use flags | |
1671 | * along with it. | |
1672 | * Reset the survey data for the new channel, unless we're switching | |
1673 | * back to the operating channel from an off-channel operation. | |
1674 | */ | |
1675 | if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && | |
1676 | sc->cur_survey != &sc->survey[pos]) { | |
1677 | ||
1678 | if (sc->cur_survey) | |
1679 | sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; | |
1680 | ||
1681 | sc->cur_survey = &sc->survey[pos]; | |
1682 | ||
1683 | memset(sc->cur_survey, 0, sizeof(struct survey_info)); | |
1684 | sc->cur_survey->filled |= SURVEY_INFO_IN_USE; | |
1685 | } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { | |
1686 | memset(&sc->survey[pos], 0, sizeof(struct survey_info)); | |
1687 | } | |
1688 | ||
0e2dedf9 | 1689 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
3800276a | 1690 | ath_err(common, "Unable to set channel\n"); |
aa33de09 | 1691 | mutex_unlock(&sc->mutex); |
e11602b7 S |
1692 | return -EINVAL; |
1693 | } | |
3430098a FF |
1694 | |
1695 | /* | |
1696 | * The most recent snapshot of channel->noisefloor for the old | |
1697 | * channel is only available after the hardware reset. Copy it to | |
1698 | * the survey stats now. | |
1699 | */ | |
1700 | if (old_pos >= 0) | |
1701 | ath_update_survey_nf(sc, old_pos); | |
094d05dc | 1702 | } |
f078f209 | 1703 | |
c9f6a656 | 1704 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
603b3eef BG |
1705 | ath_dbg(common, ATH_DBG_CONFIG, |
1706 | "Set power: %d\n", conf->power_level); | |
17d7904d | 1707 | sc->config.txpowlimit = 2 * conf->power_level; |
5048e8c3 RM |
1708 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
1709 | sc->config.txpowlimit, &sc->curtxpow); | |
64839170 LR |
1710 | } |
1711 | ||
aa33de09 | 1712 | mutex_unlock(&sc->mutex); |
c0c11741 | 1713 | ath9k_ps_restore(sc); |
141b38b6 | 1714 | |
f078f209 LR |
1715 | return 0; |
1716 | } | |
1717 | ||
8feceb67 VT |
1718 | #define SUPPORTED_FILTERS \ |
1719 | (FIF_PROMISC_IN_BSS | \ | |
1720 | FIF_ALLMULTI | \ | |
1721 | FIF_CONTROL | \ | |
af6a3fc7 | 1722 | FIF_PSPOLL | \ |
8feceb67 VT |
1723 | FIF_OTHER_BSS | \ |
1724 | FIF_BCN_PRBRESP_PROMISC | \ | |
9c1d8e4a | 1725 | FIF_PROBE_REQ | \ |
8feceb67 | 1726 | FIF_FCSFAIL) |
c83be688 | 1727 | |
8feceb67 VT |
1728 | /* FIXME: sc->sc_full_reset ? */ |
1729 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1730 | unsigned int changed_flags, | |
1731 | unsigned int *total_flags, | |
3ac64bee | 1732 | u64 multicast) |
8feceb67 | 1733 | { |
9ac58615 | 1734 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1735 | u32 rfilt; |
f078f209 | 1736 | |
8feceb67 VT |
1737 | changed_flags &= SUPPORTED_FILTERS; |
1738 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1739 | |
b77f483f | 1740 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1741 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1742 | rfilt = ath_calcrxfilter(sc); |
1743 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1744 | ath9k_ps_restore(sc); |
f078f209 | 1745 | |
226afe68 JP |
1746 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, |
1747 | "Set HW RX filter: 0x%x\n", rfilt); | |
8feceb67 | 1748 | } |
f078f209 | 1749 | |
4ca77860 JB |
1750 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1751 | struct ieee80211_vif *vif, | |
1752 | struct ieee80211_sta *sta) | |
8feceb67 | 1753 | { |
9ac58615 | 1754 | struct ath_softc *sc = hw->priv; |
93ae2dd2 FF |
1755 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1756 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1757 | struct ieee80211_key_conf ps_key = { }; | |
f078f209 | 1758 | |
7e1e3864 | 1759 | ath_node_attach(sc, sta, vif); |
f59a59fe FF |
1760 | |
1761 | if (vif->type != NL80211_IFTYPE_AP && | |
1762 | vif->type != NL80211_IFTYPE_AP_VLAN) | |
1763 | return 0; | |
1764 | ||
93ae2dd2 | 1765 | an->ps_key = ath_key_config(common, vif, sta, &ps_key); |
4ca77860 JB |
1766 | |
1767 | return 0; | |
1768 | } | |
1769 | ||
93ae2dd2 FF |
1770 | static void ath9k_del_ps_key(struct ath_softc *sc, |
1771 | struct ieee80211_vif *vif, | |
1772 | struct ieee80211_sta *sta) | |
1773 | { | |
1774 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1775 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1776 | struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; | |
1777 | ||
1778 | if (!an->ps_key) | |
1779 | return; | |
1780 | ||
1781 | ath_key_delete(common, &ps_key); | |
1782 | } | |
1783 | ||
4ca77860 JB |
1784 | static int ath9k_sta_remove(struct ieee80211_hw *hw, |
1785 | struct ieee80211_vif *vif, | |
1786 | struct ieee80211_sta *sta) | |
1787 | { | |
9ac58615 | 1788 | struct ath_softc *sc = hw->priv; |
4ca77860 | 1789 | |
93ae2dd2 | 1790 | ath9k_del_ps_key(sc, vif, sta); |
4ca77860 JB |
1791 | ath_node_detach(sc, sta); |
1792 | ||
1793 | return 0; | |
f078f209 LR |
1794 | } |
1795 | ||
5519541d FF |
1796 | static void ath9k_sta_notify(struct ieee80211_hw *hw, |
1797 | struct ieee80211_vif *vif, | |
1798 | enum sta_notify_cmd cmd, | |
1799 | struct ieee80211_sta *sta) | |
1800 | { | |
1801 | struct ath_softc *sc = hw->priv; | |
1802 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1803 | ||
1804 | switch (cmd) { | |
1805 | case STA_NOTIFY_SLEEP: | |
1806 | an->sleeping = true; | |
042ec453 | 1807 | ath_tx_aggr_sleep(sta, sc, an); |
5519541d FF |
1808 | break; |
1809 | case STA_NOTIFY_AWAKE: | |
1810 | an->sleeping = false; | |
1811 | ath_tx_aggr_wakeup(sc, an); | |
1812 | break; | |
1813 | } | |
1814 | } | |
1815 | ||
8a3a3c85 EP |
1816 | static int ath9k_conf_tx(struct ieee80211_hw *hw, |
1817 | struct ieee80211_vif *vif, u16 queue, | |
8feceb67 | 1818 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1819 | { |
9ac58615 | 1820 | struct ath_softc *sc = hw->priv; |
c46917bb | 1821 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
066dae93 | 1822 | struct ath_txq *txq; |
8feceb67 | 1823 | struct ath9k_tx_queue_info qi; |
066dae93 | 1824 | int ret = 0; |
f078f209 | 1825 | |
8feceb67 VT |
1826 | if (queue >= WME_NUM_AC) |
1827 | return 0; | |
f078f209 | 1828 | |
066dae93 FF |
1829 | txq = sc->tx.txq_map[queue]; |
1830 | ||
96f372c9 | 1831 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1832 | mutex_lock(&sc->mutex); |
1833 | ||
1ffb0610 S |
1834 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1835 | ||
8feceb67 VT |
1836 | qi.tqi_aifs = params->aifs; |
1837 | qi.tqi_cwmin = params->cw_min; | |
1838 | qi.tqi_cwmax = params->cw_max; | |
1839 | qi.tqi_burstTime = params->txop; | |
f078f209 | 1840 | |
226afe68 JP |
1841 | ath_dbg(common, ATH_DBG_CONFIG, |
1842 | "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | |
1843 | queue, txq->axq_qnum, params->aifs, params->cw_min, | |
1844 | params->cw_max, params->txop); | |
f078f209 | 1845 | |
066dae93 | 1846 | ret = ath_txq_update(sc, txq->axq_qnum, &qi); |
8feceb67 | 1847 | if (ret) |
3800276a | 1848 | ath_err(common, "TXQ Update failed\n"); |
f078f209 | 1849 | |
94db2936 | 1850 | if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) |
066dae93 | 1851 | if (queue == WME_AC_BE && !ret) |
94db2936 VN |
1852 | ath_beaconq_config(sc); |
1853 | ||
141b38b6 | 1854 | mutex_unlock(&sc->mutex); |
96f372c9 | 1855 | ath9k_ps_restore(sc); |
141b38b6 | 1856 | |
8feceb67 VT |
1857 | return ret; |
1858 | } | |
f078f209 | 1859 | |
8feceb67 VT |
1860 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1861 | enum set_key_cmd cmd, | |
dc822b5d JB |
1862 | struct ieee80211_vif *vif, |
1863 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1864 | struct ieee80211_key_conf *key) |
1865 | { | |
9ac58615 | 1866 | struct ath_softc *sc = hw->priv; |
c46917bb | 1867 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1868 | int ret = 0; |
f078f209 | 1869 | |
3e6109c5 | 1870 | if (ath9k_modparam_nohwcrypt) |
b3bd89ce JM |
1871 | return -ENOSPC; |
1872 | ||
cfdc9a8b JM |
1873 | if (vif->type == NL80211_IFTYPE_ADHOC && |
1874 | (key->cipher == WLAN_CIPHER_SUITE_TKIP || | |
1875 | key->cipher == WLAN_CIPHER_SUITE_CCMP) && | |
1876 | !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { | |
1877 | /* | |
1878 | * For now, disable hw crypto for the RSN IBSS group keys. This | |
1879 | * could be optimized in the future to use a modified key cache | |
1880 | * design to support per-STA RX GTK, but until that gets | |
1881 | * implemented, use of software crypto for group addressed | |
1882 | * frames is a acceptable to allow RSN IBSS to be used. | |
1883 | */ | |
1884 | return -EOPNOTSUPP; | |
1885 | } | |
1886 | ||
141b38b6 | 1887 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1888 | ath9k_ps_wakeup(sc); |
226afe68 | 1889 | ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n"); |
f078f209 | 1890 | |
8feceb67 VT |
1891 | switch (cmd) { |
1892 | case SET_KEY: | |
93ae2dd2 FF |
1893 | if (sta) |
1894 | ath9k_del_ps_key(sc, vif, sta); | |
1895 | ||
040e539e | 1896 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1897 | if (ret >= 0) { |
1898 | key->hw_key_idx = ret; | |
8feceb67 VT |
1899 | /* push IV and Michael MIC generation to stack */ |
1900 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
97359d12 | 1901 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) |
8feceb67 | 1902 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
97359d12 JB |
1903 | if (sc->sc_ah->sw_mgmt_crypto && |
1904 | key->cipher == WLAN_CIPHER_SUITE_CCMP) | |
0ced0e17 | 1905 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; |
6ace2891 | 1906 | ret = 0; |
8feceb67 VT |
1907 | } |
1908 | break; | |
1909 | case DISABLE_KEY: | |
040e539e | 1910 | ath_key_delete(common, key); |
8feceb67 VT |
1911 | break; |
1912 | default: | |
1913 | ret = -EINVAL; | |
1914 | } | |
f078f209 | 1915 | |
3cbb5dd7 | 1916 | ath9k_ps_restore(sc); |
141b38b6 S |
1917 | mutex_unlock(&sc->mutex); |
1918 | ||
8feceb67 VT |
1919 | return ret; |
1920 | } | |
4f5ef75b RM |
1921 | static void ath9k_bss_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
1922 | { | |
1923 | struct ath_softc *sc = data; | |
1924 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1925 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; | |
1926 | struct ath_vif *avp = (void *)vif->drv_priv; | |
1927 | ||
2e5ef459 RM |
1928 | /* |
1929 | * Skip iteration if primary station vif's bss info | |
1930 | * was not changed | |
1931 | */ | |
1932 | if (sc->sc_flags & SC_OP_PRIM_STA_VIF) | |
1933 | return; | |
1934 | ||
1935 | if (bss_conf->assoc) { | |
1936 | sc->sc_flags |= SC_OP_PRIM_STA_VIF; | |
1937 | avp->primary_sta_vif = true; | |
4f5ef75b RM |
1938 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); |
1939 | common->curaid = bss_conf->aid; | |
1940 | ath9k_hw_write_associd(sc->sc_ah); | |
2e5ef459 | 1941 | ath_dbg(common, ATH_DBG_CONFIG, |
99e4d43a RM |
1942 | "Bss Info ASSOC %d, bssid: %pM\n", |
1943 | bss_conf->aid, common->curbssid); | |
2e5ef459 RM |
1944 | ath_beacon_config(sc, vif); |
1945 | /* | |
1946 | * Request a re-configuration of Beacon related timers | |
1947 | * on the receipt of the first Beacon frame (i.e., | |
1948 | * after time sync with the AP). | |
1949 | */ | |
1950 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
1951 | /* Reset rssi stats */ | |
1952 | sc->last_rssi = ATH_RSSI_DUMMY_MARKER; | |
1953 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; | |
99e4d43a | 1954 | |
05c0be2f MSS |
1955 | if (!common->disable_ani) { |
1956 | sc->sc_flags |= SC_OP_ANI_RUN; | |
1957 | ath_start_ani(common); | |
1958 | } | |
1959 | ||
4f5ef75b RM |
1960 | } |
1961 | } | |
1962 | ||
1963 | static void ath9k_config_bss(struct ath_softc *sc, struct ieee80211_vif *vif) | |
1964 | { | |
1965 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1966 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; | |
1967 | struct ath_vif *avp = (void *)vif->drv_priv; | |
1968 | ||
2e5ef459 RM |
1969 | if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) |
1970 | return; | |
1971 | ||
4f5ef75b RM |
1972 | /* Reconfigure bss info */ |
1973 | if (avp->primary_sta_vif && !bss_conf->assoc) { | |
99e4d43a RM |
1974 | ath_dbg(common, ATH_DBG_CONFIG, |
1975 | "Bss Info DISASSOC %d, bssid %pM\n", | |
1976 | common->curaid, common->curbssid); | |
1977 | sc->sc_flags &= ~(SC_OP_PRIM_STA_VIF | SC_OP_BEACONS); | |
4f5ef75b RM |
1978 | avp->primary_sta_vif = false; |
1979 | memset(common->curbssid, 0, ETH_ALEN); | |
1980 | common->curaid = 0; | |
1981 | } | |
1982 | ||
1983 | ieee80211_iterate_active_interfaces_atomic( | |
1984 | sc->hw, ath9k_bss_iter, sc); | |
1985 | ||
1986 | /* | |
1987 | * None of station vifs are associated. | |
1988 | * Clear bssid & aid | |
1989 | */ | |
2e5ef459 | 1990 | if (!(sc->sc_flags & SC_OP_PRIM_STA_VIF)) { |
4f5ef75b | 1991 | ath9k_hw_write_associd(sc->sc_ah); |
99e4d43a RM |
1992 | /* Stop ANI */ |
1993 | sc->sc_flags &= ~SC_OP_ANI_RUN; | |
1994 | del_timer_sync(&common->ani.timer); | |
d2c71c20 | 1995 | memset(&sc->caldata, 0, sizeof(sc->caldata)); |
99e4d43a | 1996 | } |
4f5ef75b | 1997 | } |
f078f209 | 1998 | |
8feceb67 VT |
1999 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
2000 | struct ieee80211_vif *vif, | |
2001 | struct ieee80211_bss_conf *bss_conf, | |
2002 | u32 changed) | |
2003 | { | |
9ac58615 | 2004 | struct ath_softc *sc = hw->priv; |
2d0ddec5 | 2005 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 2006 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 2007 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 2008 | int slottime; |
c6089ccc | 2009 | int error; |
f078f209 | 2010 | |
96f372c9 | 2011 | ath9k_ps_wakeup(sc); |
141b38b6 S |
2012 | mutex_lock(&sc->mutex); |
2013 | ||
c6089ccc | 2014 | if (changed & BSS_CHANGED_BSSID) { |
4f5ef75b | 2015 | ath9k_config_bss(sc, vif); |
2d0ddec5 | 2016 | |
226afe68 JP |
2017 | ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n", |
2018 | common->curbssid, common->curaid); | |
c6089ccc | 2019 | } |
2d0ddec5 | 2020 | |
2e5ef459 RM |
2021 | if (changed & BSS_CHANGED_IBSS) { |
2022 | /* There can be only one vif available */ | |
2023 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | |
2024 | common->curaid = bss_conf->aid; | |
2025 | ath9k_hw_write_associd(sc->sc_ah); | |
2026 | ||
2027 | if (bss_conf->ibss_joined) { | |
2028 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; | |
05c0be2f MSS |
2029 | |
2030 | if (!common->disable_ani) { | |
2031 | sc->sc_flags |= SC_OP_ANI_RUN; | |
2032 | ath_start_ani(common); | |
2033 | } | |
2034 | ||
2e5ef459 RM |
2035 | } else { |
2036 | sc->sc_flags &= ~SC_OP_ANI_RUN; | |
2037 | del_timer_sync(&common->ani.timer); | |
2038 | } | |
2039 | } | |
2040 | ||
c6089ccc S |
2041 | /* Enable transmission of beacons (AP, IBSS, MESH) */ |
2042 | if ((changed & BSS_CHANGED_BEACON) || | |
2043 | ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { | |
014cf3bb | 2044 | ath9k_set_beaconing_status(sc, false); |
9ac58615 | 2045 | error = ath_beacon_alloc(sc, vif); |
c6089ccc S |
2046 | if (!error) |
2047 | ath_beacon_config(sc, vif); | |
014cf3bb | 2048 | ath9k_set_beaconing_status(sc, true); |
0005baf4 FF |
2049 | } |
2050 | ||
2051 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
2052 | if (bss_conf->use_short_slot) | |
2053 | slottime = 9; | |
2054 | else | |
2055 | slottime = 20; | |
2056 | if (vif->type == NL80211_IFTYPE_AP) { | |
2057 | /* | |
2058 | * Defer update, so that connected stations can adjust | |
2059 | * their settings at the same time. | |
2060 | * See beacon.c for more details | |
2061 | */ | |
2062 | sc->beacon.slottime = slottime; | |
2063 | sc->beacon.updateslot = UPDATE; | |
2064 | } else { | |
2065 | ah->slottime = slottime; | |
2066 | ath9k_hw_init_global_settings(ah); | |
2067 | } | |
2d0ddec5 JB |
2068 | } |
2069 | ||
c6089ccc | 2070 | /* Disable transmission of beacons */ |
014cf3bb RM |
2071 | if ((changed & BSS_CHANGED_BEACON_ENABLED) && |
2072 | !bss_conf->enable_beacon) { | |
2073 | ath9k_set_beaconing_status(sc, false); | |
2074 | avp->is_bslot_active = false; | |
2075 | ath9k_set_beaconing_status(sc, true); | |
2076 | } | |
2d0ddec5 | 2077 | |
c6089ccc | 2078 | if (changed & BSS_CHANGED_BEACON_INT) { |
c6089ccc S |
2079 | /* |
2080 | * In case of AP mode, the HW TSF has to be reset | |
2081 | * when the beacon interval changes. | |
2082 | */ | |
2083 | if (vif->type == NL80211_IFTYPE_AP) { | |
2084 | sc->sc_flags |= SC_OP_TSF_RESET; | |
014cf3bb | 2085 | ath9k_set_beaconing_status(sc, false); |
9ac58615 | 2086 | error = ath_beacon_alloc(sc, vif); |
2d0ddec5 JB |
2087 | if (!error) |
2088 | ath_beacon_config(sc, vif); | |
014cf3bb | 2089 | ath9k_set_beaconing_status(sc, true); |
99e4d43a | 2090 | } else |
c6089ccc | 2091 | ath_beacon_config(sc, vif); |
2d0ddec5 JB |
2092 | } |
2093 | ||
8feceb67 | 2094 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
226afe68 JP |
2095 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
2096 | bss_conf->use_short_preamble); | |
8feceb67 VT |
2097 | if (bss_conf->use_short_preamble) |
2098 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
2099 | else | |
2100 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
2101 | } | |
f078f209 | 2102 | |
8feceb67 | 2103 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
226afe68 JP |
2104 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
2105 | bss_conf->use_cts_prot); | |
8feceb67 VT |
2106 | if (bss_conf->use_cts_prot && |
2107 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
2108 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
2109 | else | |
2110 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
2111 | } | |
f078f209 | 2112 | |
141b38b6 | 2113 | mutex_unlock(&sc->mutex); |
96f372c9 | 2114 | ath9k_ps_restore(sc); |
8feceb67 | 2115 | } |
f078f209 | 2116 | |
37a41b4a | 2117 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 2118 | { |
9ac58615 | 2119 | struct ath_softc *sc = hw->priv; |
8feceb67 | 2120 | u64 tsf; |
f078f209 | 2121 | |
141b38b6 | 2122 | mutex_lock(&sc->mutex); |
9abbfb27 | 2123 | ath9k_ps_wakeup(sc); |
141b38b6 | 2124 | tsf = ath9k_hw_gettsf64(sc->sc_ah); |
9abbfb27 | 2125 | ath9k_ps_restore(sc); |
141b38b6 | 2126 | mutex_unlock(&sc->mutex); |
f078f209 | 2127 | |
8feceb67 VT |
2128 | return tsf; |
2129 | } | |
f078f209 | 2130 | |
37a41b4a EP |
2131 | static void ath9k_set_tsf(struct ieee80211_hw *hw, |
2132 | struct ieee80211_vif *vif, | |
2133 | u64 tsf) | |
3b5d665b | 2134 | { |
9ac58615 | 2135 | struct ath_softc *sc = hw->priv; |
3b5d665b | 2136 | |
141b38b6 | 2137 | mutex_lock(&sc->mutex); |
9abbfb27 | 2138 | ath9k_ps_wakeup(sc); |
141b38b6 | 2139 | ath9k_hw_settsf64(sc->sc_ah, tsf); |
9abbfb27 | 2140 | ath9k_ps_restore(sc); |
141b38b6 | 2141 | mutex_unlock(&sc->mutex); |
3b5d665b AF |
2142 | } |
2143 | ||
37a41b4a | 2144 | static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 2145 | { |
9ac58615 | 2146 | struct ath_softc *sc = hw->priv; |
c83be688 | 2147 | |
141b38b6 | 2148 | mutex_lock(&sc->mutex); |
21526d57 LR |
2149 | |
2150 | ath9k_ps_wakeup(sc); | |
141b38b6 | 2151 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
2152 | ath9k_ps_restore(sc); |
2153 | ||
141b38b6 | 2154 | mutex_unlock(&sc->mutex); |
8feceb67 | 2155 | } |
f078f209 | 2156 | |
8feceb67 | 2157 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 2158 | struct ieee80211_vif *vif, |
141b38b6 S |
2159 | enum ieee80211_ampdu_mlme_action action, |
2160 | struct ieee80211_sta *sta, | |
0b01f030 | 2161 | u16 tid, u16 *ssn, u8 buf_size) |
8feceb67 | 2162 | { |
9ac58615 | 2163 | struct ath_softc *sc = hw->priv; |
8feceb67 | 2164 | int ret = 0; |
f078f209 | 2165 | |
85ad181e JB |
2166 | local_bh_disable(); |
2167 | ||
8feceb67 VT |
2168 | switch (action) { |
2169 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
2170 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
2171 | ret = -ENOTSUPP; | |
8feceb67 VT |
2172 | break; |
2173 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
2174 | break; |
2175 | case IEEE80211_AMPDU_TX_START: | |
71a3bf3e FF |
2176 | if (!(sc->sc_flags & SC_OP_TXAGGR)) |
2177 | return -EOPNOTSUPP; | |
2178 | ||
8b685ba9 | 2179 | ath9k_ps_wakeup(sc); |
231c3a1f FF |
2180 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
2181 | if (!ret) | |
2182 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
8b685ba9 | 2183 | ath9k_ps_restore(sc); |
8feceb67 VT |
2184 | break; |
2185 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 2186 | ath9k_ps_wakeup(sc); |
f83da965 | 2187 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 2188 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 2189 | ath9k_ps_restore(sc); |
8feceb67 | 2190 | break; |
b1720231 | 2191 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 2192 | ath9k_ps_wakeup(sc); |
8469cdef | 2193 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 2194 | ath9k_ps_restore(sc); |
8469cdef | 2195 | break; |
8feceb67 | 2196 | default: |
3800276a | 2197 | ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); |
8feceb67 VT |
2198 | } |
2199 | ||
85ad181e JB |
2200 | local_bh_enable(); |
2201 | ||
8feceb67 | 2202 | return ret; |
f078f209 LR |
2203 | } |
2204 | ||
62dad5b0 BP |
2205 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
2206 | struct survey_info *survey) | |
2207 | { | |
9ac58615 | 2208 | struct ath_softc *sc = hw->priv; |
3430098a | 2209 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39162dbe | 2210 | struct ieee80211_supported_band *sband; |
3430098a FF |
2211 | struct ieee80211_channel *chan; |
2212 | unsigned long flags; | |
2213 | int pos; | |
2214 | ||
2215 | spin_lock_irqsave(&common->cc_lock, flags); | |
2216 | if (idx == 0) | |
2217 | ath_update_survey_stats(sc); | |
39162dbe FF |
2218 | |
2219 | sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; | |
2220 | if (sband && idx >= sband->n_channels) { | |
2221 | idx -= sband->n_channels; | |
2222 | sband = NULL; | |
2223 | } | |
62dad5b0 | 2224 | |
39162dbe FF |
2225 | if (!sband) |
2226 | sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; | |
62dad5b0 | 2227 | |
3430098a FF |
2228 | if (!sband || idx >= sband->n_channels) { |
2229 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
2230 | return -ENOENT; | |
4f1a5a4b | 2231 | } |
62dad5b0 | 2232 | |
3430098a FF |
2233 | chan = &sband->channels[idx]; |
2234 | pos = chan->hw_value; | |
2235 | memcpy(survey, &sc->survey[pos], sizeof(*survey)); | |
2236 | survey->channel = chan; | |
2237 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
2238 | ||
62dad5b0 BP |
2239 | return 0; |
2240 | } | |
2241 | ||
e239d859 FF |
2242 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
2243 | { | |
9ac58615 | 2244 | struct ath_softc *sc = hw->priv; |
e239d859 FF |
2245 | struct ath_hw *ah = sc->sc_ah; |
2246 | ||
2247 | mutex_lock(&sc->mutex); | |
2248 | ah->coverage_class = coverage_class; | |
8b2a3827 MSS |
2249 | |
2250 | ath9k_ps_wakeup(sc); | |
e239d859 | 2251 | ath9k_hw_init_global_settings(ah); |
8b2a3827 MSS |
2252 | ath9k_ps_restore(sc); |
2253 | ||
e239d859 FF |
2254 | mutex_unlock(&sc->mutex); |
2255 | } | |
2256 | ||
69081624 VT |
2257 | static void ath9k_flush(struct ieee80211_hw *hw, bool drop) |
2258 | { | |
69081624 | 2259 | struct ath_softc *sc = hw->priv; |
99aa55b6 MSS |
2260 | struct ath_hw *ah = sc->sc_ah; |
2261 | struct ath_common *common = ath9k_hw_common(ah); | |
86271e46 FF |
2262 | int timeout = 200; /* ms */ |
2263 | int i, j; | |
2f6fc351 | 2264 | bool drain_txq; |
69081624 VT |
2265 | |
2266 | mutex_lock(&sc->mutex); | |
69081624 VT |
2267 | cancel_delayed_work_sync(&sc->tx_complete_work); |
2268 | ||
6a6b3f3e MSS |
2269 | if (ah->ah_flags & AH_UNPLUGGED) { |
2270 | ath_dbg(common, ATH_DBG_ANY, "Device has been unplugged!\n"); | |
2271 | mutex_unlock(&sc->mutex); | |
2272 | return; | |
2273 | } | |
2274 | ||
99aa55b6 MSS |
2275 | if (sc->sc_flags & SC_OP_INVALID) { |
2276 | ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); | |
2277 | mutex_unlock(&sc->mutex); | |
2278 | return; | |
2279 | } | |
2280 | ||
86271e46 | 2281 | for (j = 0; j < timeout; j++) { |
108697c4 | 2282 | bool npend = false; |
86271e46 FF |
2283 | |
2284 | if (j) | |
2285 | usleep_range(1000, 2000); | |
69081624 | 2286 | |
86271e46 FF |
2287 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2288 | if (!ATH_TXQ_SETUP(sc, i)) | |
2289 | continue; | |
2290 | ||
108697c4 MSS |
2291 | npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]); |
2292 | ||
2293 | if (npend) | |
2294 | break; | |
69081624 | 2295 | } |
86271e46 FF |
2296 | |
2297 | if (!npend) | |
9df0d6a2 | 2298 | break; |
69081624 VT |
2299 | } |
2300 | ||
9df0d6a2 FF |
2301 | if (drop) { |
2302 | ath9k_ps_wakeup(sc); | |
2303 | spin_lock_bh(&sc->sc_pcu_lock); | |
2304 | drain_txq = ath_drain_all_txq(sc, false); | |
2305 | spin_unlock_bh(&sc->sc_pcu_lock); | |
9adcf440 | 2306 | |
9df0d6a2 FF |
2307 | if (!drain_txq) |
2308 | ath_reset(sc, false); | |
9adcf440 | 2309 | |
9df0d6a2 FF |
2310 | ath9k_ps_restore(sc); |
2311 | ieee80211_wake_queues(hw); | |
2312 | } | |
d78f4b3e | 2313 | |
69081624 VT |
2314 | ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); |
2315 | mutex_unlock(&sc->mutex); | |
2316 | } | |
2317 | ||
15b91e83 VN |
2318 | static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) |
2319 | { | |
2320 | struct ath_softc *sc = hw->priv; | |
2321 | int i; | |
2322 | ||
2323 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
2324 | if (!ATH_TXQ_SETUP(sc, i)) | |
2325 | continue; | |
2326 | ||
2327 | if (ath9k_has_pending_frames(sc, &sc->tx.txq[i])) | |
2328 | return true; | |
2329 | } | |
2330 | return false; | |
2331 | } | |
2332 | ||
5595f119 | 2333 | static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) |
ba4903f9 FF |
2334 | { |
2335 | struct ath_softc *sc = hw->priv; | |
2336 | struct ath_hw *ah = sc->sc_ah; | |
2337 | struct ieee80211_vif *vif; | |
2338 | struct ath_vif *avp; | |
2339 | struct ath_buf *bf; | |
2340 | struct ath_tx_status ts; | |
2341 | int status; | |
2342 | ||
2343 | vif = sc->beacon.bslot[0]; | |
2344 | if (!vif) | |
2345 | return 0; | |
2346 | ||
2347 | avp = (void *)vif->drv_priv; | |
2348 | if (!avp->is_bslot_active) | |
2349 | return 0; | |
2350 | ||
2351 | if (!sc->beacon.tx_processed) { | |
2352 | tasklet_disable(&sc->bcon_tasklet); | |
2353 | ||
2354 | bf = avp->av_bcbuf; | |
2355 | if (!bf || !bf->bf_mpdu) | |
2356 | goto skip; | |
2357 | ||
2358 | status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); | |
2359 | if (status == -EINPROGRESS) | |
2360 | goto skip; | |
2361 | ||
2362 | sc->beacon.tx_processed = true; | |
2363 | sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); | |
2364 | ||
2365 | skip: | |
2366 | tasklet_enable(&sc->bcon_tasklet); | |
2367 | } | |
2368 | ||
2369 | return sc->beacon.tx_last; | |
2370 | } | |
2371 | ||
52c94f41 MSS |
2372 | static int ath9k_get_stats(struct ieee80211_hw *hw, |
2373 | struct ieee80211_low_level_stats *stats) | |
2374 | { | |
2375 | struct ath_softc *sc = hw->priv; | |
2376 | struct ath_hw *ah = sc->sc_ah; | |
2377 | struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; | |
2378 | ||
2379 | stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; | |
2380 | stats->dot11RTSFailureCount = mib_stats->rts_bad; | |
2381 | stats->dot11FCSErrorCount = mib_stats->fcs_bad; | |
2382 | stats->dot11RTSSuccessCount = mib_stats->rts_good; | |
2383 | return 0; | |
2384 | } | |
2385 | ||
43c35284 FF |
2386 | static u32 fill_chainmask(u32 cap, u32 new) |
2387 | { | |
2388 | u32 filled = 0; | |
2389 | int i; | |
2390 | ||
2391 | for (i = 0; cap && new; i++, cap >>= 1) { | |
2392 | if (!(cap & BIT(0))) | |
2393 | continue; | |
2394 | ||
2395 | if (new & BIT(0)) | |
2396 | filled |= BIT(i); | |
2397 | ||
2398 | new >>= 1; | |
2399 | } | |
2400 | ||
2401 | return filled; | |
2402 | } | |
2403 | ||
2404 | static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) | |
2405 | { | |
2406 | struct ath_softc *sc = hw->priv; | |
2407 | struct ath_hw *ah = sc->sc_ah; | |
2408 | ||
2409 | if (!rx_ant || !tx_ant) | |
2410 | return -EINVAL; | |
2411 | ||
2412 | sc->ant_rx = rx_ant; | |
2413 | sc->ant_tx = tx_ant; | |
2414 | ||
2415 | if (ah->caps.rx_chainmask == 1) | |
2416 | return 0; | |
2417 | ||
2418 | /* AR9100 runs into calibration issues if not all rx chains are enabled */ | |
2419 | if (AR_SREV_9100(ah)) | |
2420 | ah->rxchainmask = 0x7; | |
2421 | else | |
2422 | ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); | |
2423 | ||
2424 | ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); | |
2425 | ath9k_reload_chainmask_settings(sc); | |
2426 | ||
2427 | return 0; | |
2428 | } | |
2429 | ||
2430 | static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) | |
2431 | { | |
2432 | struct ath_softc *sc = hw->priv; | |
2433 | ||
2434 | *tx_ant = sc->ant_tx; | |
2435 | *rx_ant = sc->ant_rx; | |
2436 | return 0; | |
2437 | } | |
2438 | ||
6baff7f9 | 2439 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2440 | .tx = ath9k_tx, |
2441 | .start = ath9k_start, | |
2442 | .stop = ath9k_stop, | |
2443 | .add_interface = ath9k_add_interface, | |
6b3b991d | 2444 | .change_interface = ath9k_change_interface, |
8feceb67 VT |
2445 | .remove_interface = ath9k_remove_interface, |
2446 | .config = ath9k_config, | |
8feceb67 | 2447 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2448 | .sta_add = ath9k_sta_add, |
2449 | .sta_remove = ath9k_sta_remove, | |
5519541d | 2450 | .sta_notify = ath9k_sta_notify, |
8feceb67 | 2451 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2452 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2453 | .set_key = ath9k_set_key, |
8feceb67 | 2454 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2455 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2456 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2457 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2458 | .get_survey = ath9k_get_survey, |
3b319aae | 2459 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2460 | .set_coverage_class = ath9k_set_coverage_class, |
69081624 | 2461 | .flush = ath9k_flush, |
15b91e83 | 2462 | .tx_frames_pending = ath9k_tx_frames_pending, |
52c94f41 MSS |
2463 | .tx_last_beacon = ath9k_tx_last_beacon, |
2464 | .get_stats = ath9k_get_stats, | |
43c35284 FF |
2465 | .set_antenna = ath9k_set_antenna, |
2466 | .get_antenna = ath9k_get_antenna, | |
8feceb67 | 2467 | }; |