Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
394cf0a1 | 18 | #include "ath9k.h" |
af03abec | 19 | #include "btcoex.h" |
f078f209 | 20 | |
ff37e337 S |
21 | static u8 parse_mpdudensity(u8 mpdudensity) |
22 | { | |
23 | /* | |
24 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
25 | * 0 for no restriction | |
26 | * 1 for 1/4 us | |
27 | * 2 for 1/2 us | |
28 | * 3 for 1 us | |
29 | * 4 for 2 us | |
30 | * 5 for 4 us | |
31 | * 6 for 8 us | |
32 | * 7 for 16 us | |
33 | */ | |
34 | switch (mpdudensity) { | |
35 | case 0: | |
36 | return 0; | |
37 | case 1: | |
38 | case 2: | |
39 | case 3: | |
40 | /* Our lower layer calculations limit our precision to | |
41 | 1 microsecond */ | |
42 | return 1; | |
43 | case 4: | |
44 | return 2; | |
45 | case 5: | |
46 | return 4; | |
47 | case 6: | |
48 | return 8; | |
49 | case 7: | |
50 | return 16; | |
51 | default: | |
52 | return 0; | |
53 | } | |
54 | } | |
55 | ||
55624204 | 56 | bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
57 | { |
58 | unsigned long flags; | |
59 | bool ret; | |
60 | ||
9ecdef4b LR |
61 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
62 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
63 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
64 | |
65 | return ret; | |
66 | } | |
67 | ||
a91d75ae LR |
68 | void ath9k_ps_wakeup(struct ath_softc *sc) |
69 | { | |
898c914a | 70 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae | 71 | unsigned long flags; |
fbb078fc | 72 | enum ath9k_power_mode power_mode; |
a91d75ae LR |
73 | |
74 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
75 | if (++sc->ps_usecount != 1) | |
76 | goto unlock; | |
77 | ||
fbb078fc | 78 | power_mode = sc->sc_ah->power_mode; |
9ecdef4b | 79 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae | 80 | |
898c914a FF |
81 | /* |
82 | * While the hardware is asleep, the cycle counters contain no | |
83 | * useful data. Better clear them now so that they don't mess up | |
84 | * survey data results. | |
85 | */ | |
fbb078fc FF |
86 | if (power_mode != ATH9K_PM_AWAKE) { |
87 | spin_lock(&common->cc_lock); | |
88 | ath_hw_cycle_counters_update(common); | |
89 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
90 | spin_unlock(&common->cc_lock); | |
91 | } | |
898c914a | 92 | |
a91d75ae LR |
93 | unlock: |
94 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
95 | } | |
96 | ||
97 | void ath9k_ps_restore(struct ath_softc *sc) | |
98 | { | |
898c914a | 99 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae LR |
100 | unsigned long flags; |
101 | ||
102 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
103 | if (--sc->ps_usecount != 0) | |
104 | goto unlock; | |
105 | ||
898c914a FF |
106 | spin_lock(&common->cc_lock); |
107 | ath_hw_cycle_counters_update(common); | |
108 | spin_unlock(&common->cc_lock); | |
109 | ||
1dbfd9d4 VN |
110 | if (sc->ps_idle) |
111 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); | |
112 | else if (sc->ps_enabled && | |
113 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
1b04b930 S |
114 | PS_WAIT_FOR_CAB | |
115 | PS_WAIT_FOR_PSPOLL_DATA | | |
116 | PS_WAIT_FOR_TX_ACK))) | |
9ecdef4b | 117 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); |
a91d75ae LR |
118 | |
119 | unlock: | |
120 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
121 | } | |
122 | ||
5ee08656 FF |
123 | static void ath_start_ani(struct ath_common *common) |
124 | { | |
125 | struct ath_hw *ah = common->ah; | |
126 | unsigned long timestamp = jiffies_to_msecs(jiffies); | |
127 | struct ath_softc *sc = (struct ath_softc *) common->priv; | |
128 | ||
129 | if (!(sc->sc_flags & SC_OP_ANI_RUN)) | |
130 | return; | |
131 | ||
132 | if (sc->sc_flags & SC_OP_OFFCHANNEL) | |
133 | return; | |
134 | ||
135 | common->ani.longcal_timer = timestamp; | |
136 | common->ani.shortcal_timer = timestamp; | |
137 | common->ani.checkani_timer = timestamp; | |
138 | ||
139 | mod_timer(&common->ani.timer, | |
140 | jiffies + | |
141 | msecs_to_jiffies((u32)ah->config.ani_poll_interval)); | |
142 | } | |
143 | ||
3430098a FF |
144 | static void ath_update_survey_nf(struct ath_softc *sc, int channel) |
145 | { | |
146 | struct ath_hw *ah = sc->sc_ah; | |
147 | struct ath9k_channel *chan = &ah->channels[channel]; | |
148 | struct survey_info *survey = &sc->survey[channel]; | |
149 | ||
150 | if (chan->noisefloor) { | |
151 | survey->filled |= SURVEY_INFO_NOISE_DBM; | |
152 | survey->noise = chan->noisefloor; | |
153 | } | |
154 | } | |
155 | ||
156 | static void ath_update_survey_stats(struct ath_softc *sc) | |
157 | { | |
158 | struct ath_hw *ah = sc->sc_ah; | |
159 | struct ath_common *common = ath9k_hw_common(ah); | |
160 | int pos = ah->curchan - &ah->channels[0]; | |
161 | struct survey_info *survey = &sc->survey[pos]; | |
162 | struct ath_cycle_counters *cc = &common->cc_survey; | |
163 | unsigned int div = common->clockrate * 1000; | |
164 | ||
0845735e FF |
165 | if (!ah->curchan) |
166 | return; | |
167 | ||
898c914a FF |
168 | if (ah->power_mode == ATH9K_PM_AWAKE) |
169 | ath_hw_cycle_counters_update(common); | |
3430098a FF |
170 | |
171 | if (cc->cycles > 0) { | |
172 | survey->filled |= SURVEY_INFO_CHANNEL_TIME | | |
173 | SURVEY_INFO_CHANNEL_TIME_BUSY | | |
174 | SURVEY_INFO_CHANNEL_TIME_RX | | |
175 | SURVEY_INFO_CHANNEL_TIME_TX; | |
176 | survey->channel_time += cc->cycles / div; | |
177 | survey->channel_time_busy += cc->rx_busy / div; | |
178 | survey->channel_time_rx += cc->rx_frame / div; | |
179 | survey->channel_time_tx += cc->tx_frame / div; | |
180 | } | |
181 | memset(cc, 0, sizeof(*cc)); | |
182 | ||
183 | ath_update_survey_nf(sc, pos); | |
184 | } | |
185 | ||
ff37e337 S |
186 | /* |
187 | * Set/change channels. If the channel is really being changed, it's done | |
188 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
189 | * DMA, then restart stuff. | |
190 | */ | |
0e2dedf9 JM |
191 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, |
192 | struct ath9k_channel *hchan) | |
ff37e337 | 193 | { |
cbe61d8a | 194 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 195 | struct ath_common *common = ath9k_hw_common(ah); |
25c56eec | 196 | struct ieee80211_conf *conf = &common->hw->conf; |
ff37e337 | 197 | bool fastcc = true, stopped; |
ae8d2858 | 198 | struct ieee80211_channel *channel = hw->conf.channel; |
20bd2a09 | 199 | struct ath9k_hw_cal_data *caldata = NULL; |
ae8d2858 | 200 | int r; |
ff37e337 S |
201 | |
202 | if (sc->sc_flags & SC_OP_INVALID) | |
203 | return -EIO; | |
204 | ||
5ee08656 FF |
205 | del_timer_sync(&common->ani.timer); |
206 | cancel_work_sync(&sc->paprd_work); | |
207 | cancel_work_sync(&sc->hw_check_work); | |
208 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
181fb18d | 209 | cancel_delayed_work_sync(&sc->hw_pll_work); |
5ee08656 | 210 | |
3cbb5dd7 VN |
211 | ath9k_ps_wakeup(sc); |
212 | ||
6a6733f2 LR |
213 | spin_lock_bh(&sc->sc_pcu_lock); |
214 | ||
c0d7c7af LR |
215 | /* |
216 | * This is only performed if the channel settings have | |
217 | * actually changed. | |
218 | * | |
219 | * To switch channels clear any pending DMA operations; | |
220 | * wait long enough for the RX fifo to drain, reset the | |
221 | * hardware at the new frequency, and then re-enable | |
222 | * the relevant bits of the h/w. | |
223 | */ | |
4df3071e | 224 | ath9k_hw_disable_interrupts(ah); |
080e1a25 | 225 | stopped = ath_drain_all_txq(sc, false); |
5e848f78 | 226 | |
080e1a25 FF |
227 | if (!ath_stoprecv(sc)) |
228 | stopped = false; | |
ff37e337 | 229 | |
8b3f4616 FF |
230 | if (!ath9k_hw_check_alive(ah)) |
231 | stopped = false; | |
232 | ||
c0d7c7af LR |
233 | /* XXX: do not flush receive queue here. We don't want |
234 | * to flush data frames already in queue because of | |
235 | * changing channel. */ | |
ff37e337 | 236 | |
5ee08656 | 237 | if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL)) |
c0d7c7af LR |
238 | fastcc = false; |
239 | ||
20bd2a09 | 240 | if (!(sc->sc_flags & SC_OP_OFFCHANNEL)) |
9ac58615 | 241 | caldata = &sc->caldata; |
20bd2a09 | 242 | |
226afe68 JP |
243 | ath_dbg(common, ATH_DBG_CONFIG, |
244 | "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n", | |
245 | sc->sc_ah->curchan->channel, | |
246 | channel->center_freq, conf_is_ht40(conf), | |
247 | fastcc); | |
ff37e337 | 248 | |
20bd2a09 | 249 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); |
c0d7c7af | 250 | if (r) { |
3800276a JP |
251 | ath_err(common, |
252 | "Unable to reset channel (%u MHz), reset status %d\n", | |
253 | channel->center_freq, r); | |
3989279c | 254 | goto ps_restore; |
ff37e337 | 255 | } |
c0d7c7af | 256 | |
c0d7c7af | 257 | if (ath_startrecv(sc) != 0) { |
3800276a | 258 | ath_err(common, "Unable to restart recv logic\n"); |
3989279c GJ |
259 | r = -EIO; |
260 | goto ps_restore; | |
c0d7c7af LR |
261 | } |
262 | ||
5048e8c3 RM |
263 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
264 | sc->config.txpowlimit, &sc->curtxpow); | |
3069168c | 265 | ath9k_hw_set_interrupts(ah, ah->imask); |
3989279c | 266 | |
48a6a468 | 267 | if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) { |
1186488b RM |
268 | if (sc->sc_flags & SC_OP_BEACONS) |
269 | ath_beacon_config(sc, NULL); | |
5ee08656 | 270 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
181fb18d | 271 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, HZ/2); |
48a6a468 | 272 | ath_start_ani(common); |
5ee08656 FF |
273 | } |
274 | ||
3989279c | 275 | ps_restore: |
92460412 FF |
276 | ieee80211_wake_queues(hw); |
277 | ||
6a6733f2 LR |
278 | spin_unlock_bh(&sc->sc_pcu_lock); |
279 | ||
3cbb5dd7 | 280 | ath9k_ps_restore(sc); |
3989279c | 281 | return r; |
ff37e337 S |
282 | } |
283 | ||
9f42c2b6 FF |
284 | static void ath_paprd_activate(struct ath_softc *sc) |
285 | { | |
286 | struct ath_hw *ah = sc->sc_ah; | |
20bd2a09 | 287 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9094537c | 288 | struct ath_common *common = ath9k_hw_common(ah); |
9f42c2b6 FF |
289 | int chain; |
290 | ||
20bd2a09 | 291 | if (!caldata || !caldata->paprd_done) |
9f42c2b6 FF |
292 | return; |
293 | ||
294 | ath9k_ps_wakeup(sc); | |
ddfef792 | 295 | ar9003_paprd_enable(ah, false); |
9f42c2b6 | 296 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
9094537c | 297 | if (!(common->tx_chainmask & BIT(chain))) |
9f42c2b6 FF |
298 | continue; |
299 | ||
20bd2a09 | 300 | ar9003_paprd_populate_single_table(ah, caldata, chain); |
9f42c2b6 FF |
301 | } |
302 | ||
303 | ar9003_paprd_enable(ah, true); | |
304 | ath9k_ps_restore(sc); | |
305 | } | |
306 | ||
7607cbe2 FF |
307 | static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain) |
308 | { | |
309 | struct ieee80211_hw *hw = sc->hw; | |
310 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
47960077 MSS |
311 | struct ath_hw *ah = sc->sc_ah; |
312 | struct ath_common *common = ath9k_hw_common(ah); | |
7607cbe2 FF |
313 | struct ath_tx_control txctl; |
314 | int time_left; | |
315 | ||
316 | memset(&txctl, 0, sizeof(txctl)); | |
317 | txctl.txq = sc->tx.txq_map[WME_AC_BE]; | |
318 | ||
319 | memset(tx_info, 0, sizeof(*tx_info)); | |
320 | tx_info->band = hw->conf.channel->band; | |
321 | tx_info->flags |= IEEE80211_TX_CTL_NO_ACK; | |
322 | tx_info->control.rates[0].idx = 0; | |
323 | tx_info->control.rates[0].count = 1; | |
324 | tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS; | |
325 | tx_info->control.rates[1].idx = -1; | |
326 | ||
327 | init_completion(&sc->paprd_complete); | |
328 | sc->paprd_pending = true; | |
329 | txctl.paprd = BIT(chain); | |
47960077 MSS |
330 | |
331 | if (ath_tx_start(hw, skb, &txctl) != 0) { | |
332 | ath_dbg(common, ATH_DBG_XMIT, "PAPRD TX failed\n"); | |
333 | dev_kfree_skb_any(skb); | |
7607cbe2 | 334 | return false; |
47960077 | 335 | } |
7607cbe2 FF |
336 | |
337 | time_left = wait_for_completion_timeout(&sc->paprd_complete, | |
338 | msecs_to_jiffies(ATH_PAPRD_TIMEOUT)); | |
339 | sc->paprd_pending = false; | |
340 | ||
341 | if (!time_left) | |
342 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE, | |
343 | "Timeout waiting for paprd training on TX chain %d\n", | |
344 | chain); | |
345 | ||
346 | return !!time_left; | |
347 | } | |
348 | ||
9f42c2b6 FF |
349 | void ath_paprd_calibrate(struct work_struct *work) |
350 | { | |
351 | struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work); | |
352 | struct ieee80211_hw *hw = sc->hw; | |
353 | struct ath_hw *ah = sc->sc_ah; | |
354 | struct ieee80211_hdr *hdr; | |
355 | struct sk_buff *skb = NULL; | |
20bd2a09 | 356 | struct ath9k_hw_cal_data *caldata = ah->caldata; |
9094537c | 357 | struct ath_common *common = ath9k_hw_common(ah); |
066dae93 | 358 | int ftype; |
9f42c2b6 FF |
359 | int chain_ok = 0; |
360 | int chain; | |
361 | int len = 1800; | |
9f42c2b6 | 362 | |
20bd2a09 FF |
363 | if (!caldata) |
364 | return; | |
365 | ||
1bf38661 FF |
366 | if (ar9003_paprd_init_table(ah) < 0) |
367 | return; | |
368 | ||
9f42c2b6 FF |
369 | skb = alloc_skb(len, GFP_KERNEL); |
370 | if (!skb) | |
371 | return; | |
372 | ||
9f42c2b6 FF |
373 | skb_put(skb, len); |
374 | memset(skb->data, 0, len); | |
375 | hdr = (struct ieee80211_hdr *)skb->data; | |
376 | ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC; | |
377 | hdr->frame_control = cpu_to_le16(ftype); | |
a3d3da14 | 378 | hdr->duration_id = cpu_to_le16(10); |
9f42c2b6 FF |
379 | memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN); |
380 | memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN); | |
381 | memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); | |
382 | ||
47399f1a | 383 | ath9k_ps_wakeup(sc); |
9f42c2b6 | 384 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { |
9094537c | 385 | if (!(common->tx_chainmask & BIT(chain))) |
9f42c2b6 FF |
386 | continue; |
387 | ||
388 | chain_ok = 0; | |
9f42c2b6 | 389 | |
7607cbe2 FF |
390 | ath_dbg(common, ATH_DBG_CALIBRATE, |
391 | "Sending PAPRD frame for thermal measurement " | |
392 | "on chain %d\n", chain); | |
393 | if (!ath_paprd_send_frame(sc, skb, chain)) | |
394 | goto fail_paprd; | |
9f42c2b6 | 395 | |
9f42c2b6 | 396 | ar9003_paprd_setup_gain_table(ah, chain); |
9f42c2b6 | 397 | |
7607cbe2 FF |
398 | ath_dbg(common, ATH_DBG_CALIBRATE, |
399 | "Sending PAPRD training frame on chain %d\n", chain); | |
400 | if (!ath_paprd_send_frame(sc, skb, chain)) | |
ca369eb4 | 401 | goto fail_paprd; |
9f42c2b6 FF |
402 | |
403 | if (!ar9003_paprd_is_done(ah)) | |
404 | break; | |
405 | ||
20bd2a09 | 406 | if (ar9003_paprd_create_curve(ah, caldata, chain) != 0) |
9f42c2b6 FF |
407 | break; |
408 | ||
409 | chain_ok = 1; | |
410 | } | |
411 | kfree_skb(skb); | |
412 | ||
413 | if (chain_ok) { | |
20bd2a09 | 414 | caldata->paprd_done = true; |
9f42c2b6 FF |
415 | ath_paprd_activate(sc); |
416 | } | |
417 | ||
ca369eb4 | 418 | fail_paprd: |
9f42c2b6 FF |
419 | ath9k_ps_restore(sc); |
420 | } | |
421 | ||
ff37e337 S |
422 | /* |
423 | * This routine performs the periodic noise floor calibration function | |
424 | * that is used to adjust and optimize the chip performance. This | |
425 | * takes environmental changes (location, temperature) into account. | |
426 | * When the task is complete, it reschedules itself depending on the | |
427 | * appropriate interval that was calculated. | |
428 | */ | |
55624204 | 429 | void ath_ani_calibrate(unsigned long data) |
ff37e337 | 430 | { |
20977d3e S |
431 | struct ath_softc *sc = (struct ath_softc *)data; |
432 | struct ath_hw *ah = sc->sc_ah; | |
c46917bb | 433 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
434 | bool longcal = false; |
435 | bool shortcal = false; | |
436 | bool aniflag = false; | |
437 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
6044474e | 438 | u32 cal_interval, short_cal_interval, long_cal_interval; |
b5bfc568 | 439 | unsigned long flags; |
6044474e FF |
440 | |
441 | if (ah->caldata && ah->caldata->nfcal_interference) | |
442 | long_cal_interval = ATH_LONG_CALINTERVAL_INT; | |
443 | else | |
444 | long_cal_interval = ATH_LONG_CALINTERVAL; | |
ff37e337 | 445 | |
20977d3e S |
446 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
447 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 | 448 | |
1ffc1c61 JM |
449 | /* Only calibrate if awake */ |
450 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
451 | goto set_timer; | |
452 | ||
453 | ath9k_ps_wakeup(sc); | |
454 | ||
ff37e337 | 455 | /* Long calibration runs independently of short calibration. */ |
6044474e | 456 | if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) { |
ff37e337 | 457 | longcal = true; |
226afe68 | 458 | ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
3d536acf | 459 | common->ani.longcal_timer = timestamp; |
ff37e337 S |
460 | } |
461 | ||
17d7904d | 462 | /* Short calibration applies only while caldone is false */ |
3d536acf LR |
463 | if (!common->ani.caldone) { |
464 | if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { | |
ff37e337 | 465 | shortcal = true; |
226afe68 JP |
466 | ath_dbg(common, ATH_DBG_ANI, |
467 | "shortcal @%lu\n", jiffies); | |
3d536acf LR |
468 | common->ani.shortcal_timer = timestamp; |
469 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
470 | } |
471 | } else { | |
3d536acf | 472 | if ((timestamp - common->ani.resetcal_timer) >= |
ff37e337 | 473 | ATH_RESTART_CALINTERVAL) { |
3d536acf LR |
474 | common->ani.caldone = ath9k_hw_reset_calvalid(ah); |
475 | if (common->ani.caldone) | |
476 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
477 | } |
478 | } | |
479 | ||
480 | /* Verify whether we must check ANI */ | |
e36b27af LR |
481 | if ((timestamp - common->ani.checkani_timer) >= |
482 | ah->config.ani_poll_interval) { | |
ff37e337 | 483 | aniflag = true; |
3d536acf | 484 | common->ani.checkani_timer = timestamp; |
ff37e337 S |
485 | } |
486 | ||
487 | /* Skip all processing if there's nothing to do. */ | |
488 | if (longcal || shortcal || aniflag) { | |
489 | /* Call ANI routine if necessary */ | |
b5bfc568 FF |
490 | if (aniflag) { |
491 | spin_lock_irqsave(&common->cc_lock, flags); | |
22e66a4c | 492 | ath9k_hw_ani_monitor(ah, ah->curchan); |
3430098a | 493 | ath_update_survey_stats(sc); |
b5bfc568 FF |
494 | spin_unlock_irqrestore(&common->cc_lock, flags); |
495 | } | |
ff37e337 S |
496 | |
497 | /* Perform calibration if necessary */ | |
498 | if (longcal || shortcal) { | |
3d536acf | 499 | common->ani.caldone = |
43c27613 LR |
500 | ath9k_hw_calibrate(ah, |
501 | ah->curchan, | |
502 | common->rx_chainmask, | |
503 | longcal); | |
ff37e337 S |
504 | } |
505 | } | |
506 | ||
1ffc1c61 JM |
507 | ath9k_ps_restore(sc); |
508 | ||
20977d3e | 509 | set_timer: |
ff37e337 S |
510 | /* |
511 | * Set timer interval based on previous results. | |
512 | * The interval must be the shortest necessary to satisfy ANI, | |
513 | * short calibration and long calibration. | |
514 | */ | |
aac9207e | 515 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 516 | if (sc->sc_ah->config.enable_ani) |
e36b27af LR |
517 | cal_interval = min(cal_interval, |
518 | (u32)ah->config.ani_poll_interval); | |
3d536acf | 519 | if (!common->ani.caldone) |
20977d3e | 520 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 521 | |
3d536acf | 522 | mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
20bd2a09 FF |
523 | if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) { |
524 | if (!ah->caldata->paprd_done) | |
9f42c2b6 | 525 | ieee80211_queue_work(sc->hw, &sc->paprd_work); |
45ef6a0b | 526 | else if (!ah->paprd_table_write_done) |
9f42c2b6 FF |
527 | ath_paprd_activate(sc); |
528 | } | |
ff37e337 S |
529 | } |
530 | ||
ff37e337 S |
531 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) |
532 | { | |
533 | struct ath_node *an; | |
ea066d5a | 534 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
535 | an = (struct ath_node *)sta->drv_priv; |
536 | ||
7f010c93 BG |
537 | #ifdef CONFIG_ATH9K_DEBUGFS |
538 | spin_lock(&sc->nodes_lock); | |
539 | list_add(&an->list, &sc->nodes); | |
540 | spin_unlock(&sc->nodes_lock); | |
541 | an->sta = sta; | |
542 | #endif | |
ea066d5a MSS |
543 | if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM) |
544 | sc->sc_flags |= SC_OP_ENABLE_APM; | |
545 | ||
87792efc | 546 | if (sc->sc_flags & SC_OP_TXAGGR) { |
ff37e337 | 547 | ath_tx_node_init(sc, an); |
9e98ac65 | 548 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc S |
549 | sta->ht_cap.ampdu_factor); |
550 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
551 | } | |
ff37e337 S |
552 | } |
553 | ||
554 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
555 | { | |
556 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
557 | ||
7f010c93 BG |
558 | #ifdef CONFIG_ATH9K_DEBUGFS |
559 | spin_lock(&sc->nodes_lock); | |
560 | list_del(&an->list); | |
561 | spin_unlock(&sc->nodes_lock); | |
562 | an->sta = NULL; | |
563 | #endif | |
564 | ||
ff37e337 S |
565 | if (sc->sc_flags & SC_OP_TXAGGR) |
566 | ath_tx_node_cleanup(sc, an); | |
567 | } | |
568 | ||
347809fc FF |
569 | void ath_hw_check(struct work_struct *work) |
570 | { | |
571 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work); | |
572 | int i; | |
573 | ||
574 | ath9k_ps_wakeup(sc); | |
575 | ||
576 | for (i = 0; i < 3; i++) { | |
577 | if (ath9k_hw_check_alive(sc->sc_ah)) | |
578 | goto out; | |
579 | ||
580 | msleep(1); | |
581 | } | |
fac6b6a0 | 582 | ath_reset(sc, true); |
347809fc FF |
583 | |
584 | out: | |
585 | ath9k_ps_restore(sc); | |
586 | } | |
587 | ||
55624204 | 588 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
589 | { |
590 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 591 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 592 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 593 | |
17d7904d | 594 | u32 status = sc->intrstatus; |
b5c80475 | 595 | u32 rxmask; |
ff37e337 | 596 | |
347809fc | 597 | if (status & ATH9K_INT_FATAL) { |
fac6b6a0 | 598 | ath_reset(sc, true); |
ff37e337 | 599 | return; |
063d8be3 | 600 | } |
ff37e337 | 601 | |
783cd01e | 602 | ath9k_ps_wakeup(sc); |
52671e43 | 603 | spin_lock(&sc->sc_pcu_lock); |
6a6733f2 | 604 | |
8b3f4616 FF |
605 | /* |
606 | * Only run the baseband hang check if beacons stop working in AP or | |
607 | * IBSS mode, because it has a high false positive rate. For station | |
608 | * mode it should not be necessary, since the upper layers will detect | |
609 | * this through a beacon miss automatically and the following channel | |
610 | * change will trigger a hardware reset anyway | |
611 | */ | |
612 | if (ath9k_hw_numtxpending(ah, sc->beacon.beaconq) != 0 && | |
613 | !ath9k_hw_check_alive(ah)) | |
347809fc FF |
614 | ieee80211_queue_work(sc->hw, &sc->hw_check_work); |
615 | ||
b5c80475 FF |
616 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
617 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
618 | ATH9K_INT_RXORN); | |
619 | else | |
620 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
621 | ||
622 | if (status & rxmask) { | |
b5c80475 FF |
623 | /* Check for high priority Rx first */ |
624 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
625 | (status & ATH9K_INT_RXHP)) | |
626 | ath_rx_tasklet(sc, 0, true); | |
627 | ||
628 | ath_rx_tasklet(sc, 0, false); | |
ff37e337 S |
629 | } |
630 | ||
e5003249 VT |
631 | if (status & ATH9K_INT_TX) { |
632 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
633 | ath_tx_edma_tasklet(sc); | |
634 | else | |
635 | ath_tx_tasklet(sc); | |
636 | } | |
063d8be3 | 637 | |
96148326 | 638 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
54ce846e JM |
639 | /* |
640 | * TSF sync does not look correct; remain awake to sync with | |
641 | * the next Beacon. | |
642 | */ | |
226afe68 JP |
643 | ath_dbg(common, ATH_DBG_PS, |
644 | "TSFOOR - Sync with next Beacon\n"); | |
1b04b930 | 645 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
54ce846e JM |
646 | } |
647 | ||
766ec4a9 | 648 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
ebb8e1d7 VT |
649 | if (status & ATH9K_INT_GENTIMER) |
650 | ath_gen_timer_isr(sc->sc_ah); | |
651 | ||
ff37e337 | 652 | /* re-enable hardware interrupt */ |
4df3071e | 653 | ath9k_hw_enable_interrupts(ah); |
6a6733f2 | 654 | |
52671e43 | 655 | spin_unlock(&sc->sc_pcu_lock); |
153e080d | 656 | ath9k_ps_restore(sc); |
ff37e337 S |
657 | } |
658 | ||
6baff7f9 | 659 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 660 | { |
063d8be3 S |
661 | #define SCHED_INTR ( \ |
662 | ATH9K_INT_FATAL | \ | |
663 | ATH9K_INT_RXORN | \ | |
664 | ATH9K_INT_RXEOL | \ | |
665 | ATH9K_INT_RX | \ | |
b5c80475 FF |
666 | ATH9K_INT_RXLP | \ |
667 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
668 | ATH9K_INT_TX | \ |
669 | ATH9K_INT_BMISS | \ | |
670 | ATH9K_INT_CST | \ | |
ebb8e1d7 VT |
671 | ATH9K_INT_TSFOOR | \ |
672 | ATH9K_INT_GENTIMER) | |
063d8be3 | 673 | |
ff37e337 | 674 | struct ath_softc *sc = dev; |
cbe61d8a | 675 | struct ath_hw *ah = sc->sc_ah; |
b5bfc568 | 676 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
677 | enum ath9k_int status; |
678 | bool sched = false; | |
679 | ||
063d8be3 S |
680 | /* |
681 | * The hardware is not ready/present, don't | |
682 | * touch anything. Note this can happen early | |
683 | * on if the IRQ is shared. | |
684 | */ | |
685 | if (sc->sc_flags & SC_OP_INVALID) | |
686 | return IRQ_NONE; | |
ff37e337 | 687 | |
063d8be3 S |
688 | |
689 | /* shared irq, not for us */ | |
690 | ||
153e080d | 691 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 692 | return IRQ_NONE; |
063d8be3 S |
693 | |
694 | /* | |
695 | * Figure out the reason(s) for the interrupt. Note | |
696 | * that the hal returns a pseudo-ISR that may include | |
697 | * bits we haven't explicitly enabled so we mask the | |
698 | * value to insure we only process bits we requested. | |
699 | */ | |
700 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 701 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 702 | |
063d8be3 S |
703 | /* |
704 | * If there are no status bits set, then this interrupt was not | |
705 | * for me (should have been caught above). | |
706 | */ | |
153e080d | 707 | if (!status) |
063d8be3 | 708 | return IRQ_NONE; |
ff37e337 | 709 | |
063d8be3 S |
710 | /* Cache the status */ |
711 | sc->intrstatus = status; | |
712 | ||
713 | if (status & SCHED_INTR) | |
714 | sched = true; | |
715 | ||
716 | /* | |
717 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
718 | * chip immediately. | |
719 | */ | |
b5c80475 FF |
720 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
721 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
722 | goto chip_reset; |
723 | ||
08578b8f LR |
724 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
725 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
b5bfc568 FF |
726 | |
727 | spin_lock(&common->cc_lock); | |
728 | ath_hw_cycle_counters_update(common); | |
08578b8f | 729 | ar9003_hw_bb_watchdog_dbg_info(ah); |
b5bfc568 FF |
730 | spin_unlock(&common->cc_lock); |
731 | ||
08578b8f LR |
732 | goto chip_reset; |
733 | } | |
734 | ||
063d8be3 S |
735 | if (status & ATH9K_INT_SWBA) |
736 | tasklet_schedule(&sc->bcon_tasklet); | |
737 | ||
738 | if (status & ATH9K_INT_TXURN) | |
739 | ath9k_hw_updatetxtriglevel(ah, true); | |
740 | ||
b5c80475 FF |
741 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
742 | if (status & ATH9K_INT_RXEOL) { | |
743 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
744 | ath9k_hw_set_interrupts(ah, ah->imask); | |
745 | } | |
746 | } | |
747 | ||
063d8be3 | 748 | if (status & ATH9K_INT_MIB) { |
ff37e337 | 749 | /* |
063d8be3 S |
750 | * Disable interrupts until we service the MIB |
751 | * interrupt; otherwise it will continue to | |
752 | * fire. | |
ff37e337 | 753 | */ |
4df3071e | 754 | ath9k_hw_disable_interrupts(ah); |
063d8be3 S |
755 | /* |
756 | * Let the hal handle the event. We assume | |
757 | * it will clear whatever condition caused | |
758 | * the interrupt. | |
759 | */ | |
88eac2da | 760 | spin_lock(&common->cc_lock); |
bfc472bb | 761 | ath9k_hw_proc_mib_event(ah); |
88eac2da | 762 | spin_unlock(&common->cc_lock); |
4df3071e | 763 | ath9k_hw_enable_interrupts(ah); |
063d8be3 | 764 | } |
ff37e337 | 765 | |
153e080d VT |
766 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
767 | if (status & ATH9K_INT_TIM_TIMER) { | |
ff9f0b63 LR |
768 | if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) |
769 | goto chip_reset; | |
063d8be3 S |
770 | /* Clear RxAbort bit so that we can |
771 | * receive frames */ | |
9ecdef4b | 772 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
153e080d | 773 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 774 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
ff37e337 | 775 | } |
063d8be3 S |
776 | |
777 | chip_reset: | |
ff37e337 | 778 | |
817e11de S |
779 | ath_debug_stat_interrupt(sc, status); |
780 | ||
ff37e337 | 781 | if (sched) { |
4df3071e FF |
782 | /* turn off every interrupt */ |
783 | ath9k_hw_disable_interrupts(ah); | |
ff37e337 S |
784 | tasklet_schedule(&sc->intr_tq); |
785 | } | |
786 | ||
787 | return IRQ_HANDLED; | |
063d8be3 S |
788 | |
789 | #undef SCHED_INTR | |
ff37e337 S |
790 | } |
791 | ||
8feceb67 | 792 | static void ath9k_bss_assoc_info(struct ath_softc *sc, |
9fa23e17 | 793 | struct ieee80211_hw *hw, |
5640b08e | 794 | struct ieee80211_vif *vif, |
8feceb67 | 795 | struct ieee80211_bss_conf *bss_conf) |
f078f209 | 796 | { |
f2b2143e | 797 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 798 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 799 | |
8feceb67 | 800 | if (bss_conf->assoc) { |
226afe68 JP |
801 | ath_dbg(common, ATH_DBG_CONFIG, |
802 | "Bss Info ASSOC %d, bssid: %pM\n", | |
803 | bss_conf->aid, common->curbssid); | |
f078f209 | 804 | |
8feceb67 | 805 | /* New association, store aid */ |
1510718d | 806 | common->curaid = bss_conf->aid; |
f2b2143e | 807 | ath9k_hw_write_associd(ah); |
2664f201 SB |
808 | |
809 | /* | |
810 | * Request a re-configuration of Beacon related timers | |
811 | * on the receipt of the first Beacon frame (i.e., | |
812 | * after time sync with the AP). | |
813 | */ | |
1b04b930 | 814 | sc->ps_flags |= PS_BEACON_SYNC; |
f078f209 | 815 | |
8feceb67 | 816 | /* Configure the beacon */ |
2c3db3d5 | 817 | ath_beacon_config(sc, vif); |
f078f209 | 818 | |
8feceb67 | 819 | /* Reset rssi stats */ |
9ac58615 | 820 | sc->last_rssi = ATH_RSSI_DUMMY_MARKER; |
22e66a4c | 821 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; |
f078f209 | 822 | |
6c3118e2 | 823 | sc->sc_flags |= SC_OP_ANI_RUN; |
3d536acf | 824 | ath_start_ani(common); |
8feceb67 | 825 | } else { |
226afe68 | 826 | ath_dbg(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); |
1510718d | 827 | common->curaid = 0; |
f38faa31 | 828 | /* Stop ANI */ |
6c3118e2 | 829 | sc->sc_flags &= ~SC_OP_ANI_RUN; |
3d536acf | 830 | del_timer_sync(&common->ani.timer); |
f078f209 | 831 | } |
8feceb67 | 832 | } |
f078f209 | 833 | |
68a89116 | 834 | void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 835 | { |
cbe61d8a | 836 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 837 | struct ath_common *common = ath9k_hw_common(ah); |
68a89116 | 838 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 839 | int r; |
500c064d | 840 | |
3cbb5dd7 | 841 | ath9k_ps_wakeup(sc); |
6a6733f2 LR |
842 | spin_lock_bh(&sc->sc_pcu_lock); |
843 | ||
93b1b37f | 844 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ae8d2858 | 845 | |
159cd468 | 846 | if (!ah->curchan) |
c344c9cb | 847 | ah->curchan = ath9k_cmn_get_curchannel(sc->hw, ah); |
159cd468 | 848 | |
20bd2a09 | 849 | r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ae8d2858 | 850 | if (r) { |
3800276a JP |
851 | ath_err(common, |
852 | "Unable to reset channel (%u MHz), reset status %d\n", | |
853 | channel->center_freq, r); | |
500c064d | 854 | } |
500c064d | 855 | |
5048e8c3 RM |
856 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
857 | sc->config.txpowlimit, &sc->curtxpow); | |
500c064d | 858 | if (ath_startrecv(sc) != 0) { |
3800276a | 859 | ath_err(common, "Unable to restart recv logic\n"); |
c2731b81 | 860 | goto out; |
500c064d | 861 | } |
500c064d | 862 | if (sc->sc_flags & SC_OP_BEACONS) |
2c3db3d5 | 863 | ath_beacon_config(sc, NULL); /* restart beacons */ |
500c064d VT |
864 | |
865 | /* Re-Enable interrupts */ | |
3069168c | 866 | ath9k_hw_set_interrupts(ah, ah->imask); |
500c064d VT |
867 | |
868 | /* Enable LED */ | |
08fc5c1b | 869 | ath9k_hw_cfg_output(ah, ah->led_pin, |
500c064d | 870 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
08fc5c1b | 871 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); |
500c064d | 872 | |
68a89116 | 873 | ieee80211_wake_queues(hw); |
c2731b81 | 874 | out: |
6a6733f2 LR |
875 | spin_unlock_bh(&sc->sc_pcu_lock); |
876 | ||
3cbb5dd7 | 877 | ath9k_ps_restore(sc); |
500c064d VT |
878 | } |
879 | ||
68a89116 | 880 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 881 | { |
cbe61d8a | 882 | struct ath_hw *ah = sc->sc_ah; |
68a89116 | 883 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 884 | int r; |
500c064d | 885 | |
3cbb5dd7 | 886 | ath9k_ps_wakeup(sc); |
6a6733f2 LR |
887 | spin_lock_bh(&sc->sc_pcu_lock); |
888 | ||
68a89116 | 889 | ieee80211_stop_queues(hw); |
500c064d | 890 | |
982723df VN |
891 | /* |
892 | * Keep the LED on when the radio is disabled | |
893 | * during idle unassociated state. | |
894 | */ | |
895 | if (!sc->ps_idle) { | |
896 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); | |
897 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
898 | } | |
500c064d VT |
899 | |
900 | /* Disable interrupts */ | |
4df3071e | 901 | ath9k_hw_disable_interrupts(ah); |
500c064d | 902 | |
043a0405 | 903 | ath_drain_all_txq(sc, false); /* clear pending tx frames */ |
5e848f78 | 904 | |
500c064d VT |
905 | ath_stoprecv(sc); /* turn off frame recv */ |
906 | ath_flushrecv(sc); /* flush recv queue */ | |
907 | ||
159cd468 | 908 | if (!ah->curchan) |
c344c9cb | 909 | ah->curchan = ath9k_cmn_get_curchannel(hw, ah); |
159cd468 | 910 | |
20bd2a09 | 911 | r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ae8d2858 | 912 | if (r) { |
3800276a JP |
913 | ath_err(ath9k_hw_common(sc->sc_ah), |
914 | "Unable to reset channel (%u MHz), reset status %d\n", | |
915 | channel->center_freq, r); | |
500c064d | 916 | } |
500c064d VT |
917 | |
918 | ath9k_hw_phy_disable(ah); | |
5e848f78 | 919 | |
93b1b37f | 920 | ath9k_hw_configpcipowersave(ah, 1, 1); |
6a6733f2 LR |
921 | |
922 | spin_unlock_bh(&sc->sc_pcu_lock); | |
3cbb5dd7 | 923 | ath9k_ps_restore(sc); |
500c064d VT |
924 | } |
925 | ||
ff37e337 S |
926 | int ath_reset(struct ath_softc *sc, bool retry_tx) |
927 | { | |
cbe61d8a | 928 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 929 | struct ath_common *common = ath9k_hw_common(ah); |
030bb495 | 930 | struct ieee80211_hw *hw = sc->hw; |
ae8d2858 | 931 | int r; |
ff37e337 | 932 | |
2ab81d4a S |
933 | /* Stop ANI */ |
934 | del_timer_sync(&common->ani.timer); | |
935 | ||
783cd01e | 936 | ath9k_ps_wakeup(sc); |
6a6733f2 LR |
937 | spin_lock_bh(&sc->sc_pcu_lock); |
938 | ||
cc9c378a S |
939 | ieee80211_stop_queues(hw); |
940 | ||
4df3071e | 941 | ath9k_hw_disable_interrupts(ah); |
043a0405 | 942 | ath_drain_all_txq(sc, retry_tx); |
5e848f78 | 943 | |
ff37e337 S |
944 | ath_stoprecv(sc); |
945 | ath_flushrecv(sc); | |
946 | ||
20bd2a09 | 947 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false); |
ae8d2858 | 948 | if (r) |
3800276a JP |
949 | ath_err(common, |
950 | "Unable to reset hardware; reset status %d\n", r); | |
ff37e337 S |
951 | |
952 | if (ath_startrecv(sc) != 0) | |
3800276a | 953 | ath_err(common, "Unable to start recv logic\n"); |
ff37e337 S |
954 | |
955 | /* | |
956 | * We may be doing a reset in response to a request | |
957 | * that changes the channel so update any state that | |
958 | * might change as a result. | |
959 | */ | |
5048e8c3 RM |
960 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
961 | sc->config.txpowlimit, &sc->curtxpow); | |
ff37e337 | 962 | |
52b8ac92 | 963 | if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL))) |
2c3db3d5 | 964 | ath_beacon_config(sc, NULL); /* restart beacons */ |
ff37e337 | 965 | |
3069168c | 966 | ath9k_hw_set_interrupts(ah, ah->imask); |
ff37e337 S |
967 | |
968 | if (retry_tx) { | |
969 | int i; | |
970 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
971 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
972 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
973 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
974 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
975 | } |
976 | } | |
977 | } | |
978 | ||
cc9c378a | 979 | ieee80211_wake_queues(hw); |
6a6733f2 | 980 | spin_unlock_bh(&sc->sc_pcu_lock); |
cc9c378a | 981 | |
2ab81d4a S |
982 | /* Start ANI */ |
983 | ath_start_ani(common); | |
783cd01e | 984 | ath9k_ps_restore(sc); |
2ab81d4a | 985 | |
ae8d2858 | 986 | return r; |
ff37e337 S |
987 | } |
988 | ||
ff37e337 S |
989 | /**********************/ |
990 | /* mac80211 callbacks */ | |
991 | /**********************/ | |
992 | ||
8feceb67 | 993 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 994 | { |
9ac58615 | 995 | struct ath_softc *sc = hw->priv; |
af03abec | 996 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 997 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 998 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 999 | struct ath9k_channel *init_channel; |
82880a7c | 1000 | int r; |
f078f209 | 1001 | |
226afe68 JP |
1002 | ath_dbg(common, ATH_DBG_CONFIG, |
1003 | "Starting driver with initial channel: %d MHz\n", | |
1004 | curchan->center_freq); | |
f078f209 | 1005 | |
141b38b6 S |
1006 | mutex_lock(&sc->mutex); |
1007 | ||
8feceb67 | 1008 | /* setup initial channel */ |
82880a7c | 1009 | sc->chan_idx = curchan->hw_value; |
f078f209 | 1010 | |
c344c9cb | 1011 | init_channel = ath9k_cmn_get_curchannel(hw, ah); |
ff37e337 S |
1012 | |
1013 | /* Reset SERDES registers */ | |
af03abec | 1014 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ff37e337 S |
1015 | |
1016 | /* | |
1017 | * The basic interface to setting the hardware in a good | |
1018 | * state is ``reset''. On return the hardware is known to | |
1019 | * be powered up and with interrupts disabled. This must | |
1020 | * be followed by initialization of the appropriate bits | |
1021 | * and then setup of the interrupt mask. | |
1022 | */ | |
4bdd1e97 | 1023 | spin_lock_bh(&sc->sc_pcu_lock); |
20bd2a09 | 1024 | r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); |
ae8d2858 | 1025 | if (r) { |
3800276a JP |
1026 | ath_err(common, |
1027 | "Unable to reset hardware; reset status %d (freq %u MHz)\n", | |
1028 | r, curchan->center_freq); | |
4bdd1e97 | 1029 | spin_unlock_bh(&sc->sc_pcu_lock); |
141b38b6 | 1030 | goto mutex_unlock; |
ff37e337 | 1031 | } |
ff37e337 S |
1032 | |
1033 | /* | |
1034 | * This is needed only to setup initial state | |
1035 | * but it's best done after a reset. | |
1036 | */ | |
5048e8c3 RM |
1037 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
1038 | sc->config.txpowlimit, &sc->curtxpow); | |
8feceb67 | 1039 | |
ff37e337 S |
1040 | /* |
1041 | * Setup the hardware after reset: | |
1042 | * The receive engine is set going. | |
1043 | * Frame transmit is handled entirely | |
1044 | * in the frame output path; there's nothing to do | |
1045 | * here except setup the interrupt mask. | |
1046 | */ | |
1047 | if (ath_startrecv(sc) != 0) { | |
3800276a | 1048 | ath_err(common, "Unable to start recv logic\n"); |
141b38b6 | 1049 | r = -EIO; |
4bdd1e97 | 1050 | spin_unlock_bh(&sc->sc_pcu_lock); |
141b38b6 | 1051 | goto mutex_unlock; |
f078f209 | 1052 | } |
4bdd1e97 | 1053 | spin_unlock_bh(&sc->sc_pcu_lock); |
8feceb67 | 1054 | |
ff37e337 | 1055 | /* Setup our intr mask. */ |
b5c80475 FF |
1056 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
1057 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
1058 | ATH9K_INT_GLOBAL; | |
1059 | ||
1060 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f LR |
1061 | ah->imask |= ATH9K_INT_RXHP | |
1062 | ATH9K_INT_RXLP | | |
1063 | ATH9K_INT_BB_WATCHDOG; | |
b5c80475 FF |
1064 | else |
1065 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 1066 | |
364734fa | 1067 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 1068 | |
af03abec | 1069 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 1070 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 1071 | |
ff37e337 | 1072 | sc->sc_flags &= ~SC_OP_INVALID; |
5f841b41 | 1073 | sc->sc_ah->is_monitoring = false; |
ff37e337 S |
1074 | |
1075 | /* Disable BMISS interrupt when we're not associated */ | |
3069168c PR |
1076 | ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
1077 | ath9k_hw_set_interrupts(ah, ah->imask); | |
ff37e337 | 1078 | |
bce048d7 | 1079 | ieee80211_wake_queues(hw); |
ff37e337 | 1080 | |
42935eca | 1081 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
164ace38 | 1082 | |
766ec4a9 LR |
1083 | if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && |
1084 | !ah->btcoex_hw.enabled) { | |
5e197292 LR |
1085 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, |
1086 | AR_STOMP_LOW_WLAN_WGHT); | |
af03abec | 1087 | ath9k_hw_btcoex_enable(ah); |
f985ad12 | 1088 | |
5bb12791 LR |
1089 | if (common->bus_ops->bt_coex_prep) |
1090 | common->bus_ops->bt_coex_prep(common); | |
766ec4a9 | 1091 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1092 | ath9k_btcoex_timer_resume(sc); |
1773912b VT |
1093 | } |
1094 | ||
2b7e6bce MSS |
1095 | /* User has the option to provide pm-qos value as a module |
1096 | * parameter rather than using the default value of | |
1097 | * 'ATH9K_PM_QOS_DEFAULT_VALUE'. | |
1098 | */ | |
4dc3530d | 1099 | pm_qos_update_request(&sc->pm_qos_req, ath9k_pm_qos_value); |
10598c12 | 1100 | |
8060e169 VT |
1101 | if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en) |
1102 | common->bus_ops->extn_synch_en(common); | |
1103 | ||
141b38b6 S |
1104 | mutex_unlock: |
1105 | mutex_unlock(&sc->mutex); | |
1106 | ||
ae8d2858 | 1107 | return r; |
f078f209 LR |
1108 | } |
1109 | ||
8feceb67 VT |
1110 | static int ath9k_tx(struct ieee80211_hw *hw, |
1111 | struct sk_buff *skb) | |
f078f209 | 1112 | { |
9ac58615 | 1113 | struct ath_softc *sc = hw->priv; |
c46917bb | 1114 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1115 | struct ath_tx_control txctl; |
1bc14880 | 1116 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
528f0c6b | 1117 | |
96148326 | 1118 | if (sc->ps_enabled) { |
dc8c4585 JM |
1119 | /* |
1120 | * mac80211 does not set PM field for normal data frames, so we | |
1121 | * need to update that based on the current PS mode. | |
1122 | */ | |
1123 | if (ieee80211_is_data(hdr->frame_control) && | |
1124 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
1125 | !ieee80211_has_pm(hdr->frame_control)) { | |
226afe68 JP |
1126 | ath_dbg(common, ATH_DBG_PS, |
1127 | "Add PM=1 for a TX frame while in PS mode\n"); | |
dc8c4585 JM |
1128 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
1129 | } | |
1130 | } | |
1131 | ||
9a23f9ca JM |
1132 | if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { |
1133 | /* | |
1134 | * We are using PS-Poll and mac80211 can request TX while in | |
1135 | * power save mode. Need to wake up hardware for the TX to be | |
1136 | * completed and if needed, also for RX of buffered frames. | |
1137 | */ | |
9a23f9ca | 1138 | ath9k_ps_wakeup(sc); |
fdf76622 VT |
1139 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
1140 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 1141 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
226afe68 JP |
1142 | ath_dbg(common, ATH_DBG_PS, |
1143 | "Sending PS-Poll to pick a buffered frame\n"); | |
1b04b930 | 1144 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 1145 | } else { |
226afe68 JP |
1146 | ath_dbg(common, ATH_DBG_PS, |
1147 | "Wake up to complete TX\n"); | |
1b04b930 | 1148 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
1149 | } |
1150 | /* | |
1151 | * The actual restore operation will happen only after | |
1152 | * the sc_flags bit is cleared. We are just dropping | |
1153 | * the ps_usecount here. | |
1154 | */ | |
1155 | ath9k_ps_restore(sc); | |
1156 | } | |
1157 | ||
528f0c6b | 1158 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
066dae93 | 1159 | txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; |
528f0c6b | 1160 | |
226afe68 | 1161 | ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 1162 | |
c52f33d0 | 1163 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
226afe68 | 1164 | ath_dbg(common, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 1165 | goto exit; |
8feceb67 VT |
1166 | } |
1167 | ||
528f0c6b S |
1168 | return 0; |
1169 | exit: | |
1170 | dev_kfree_skb_any(skb); | |
8feceb67 | 1171 | return 0; |
f078f209 LR |
1172 | } |
1173 | ||
8feceb67 | 1174 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 1175 | { |
9ac58615 | 1176 | struct ath_softc *sc = hw->priv; |
af03abec | 1177 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1178 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 1179 | |
4c483817 S |
1180 | mutex_lock(&sc->mutex); |
1181 | ||
9a75c2ff VN |
1182 | if (led_blink) |
1183 | cancel_delayed_work_sync(&sc->ath_led_blink_work); | |
1184 | ||
c94dbff7 | 1185 | cancel_delayed_work_sync(&sc->tx_complete_work); |
181fb18d | 1186 | cancel_delayed_work_sync(&sc->hw_pll_work); |
9f42c2b6 | 1187 | cancel_work_sync(&sc->paprd_work); |
347809fc | 1188 | cancel_work_sync(&sc->hw_check_work); |
c94dbff7 | 1189 | |
9c84b797 | 1190 | if (sc->sc_flags & SC_OP_INVALID) { |
226afe68 | 1191 | ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); |
4c483817 | 1192 | mutex_unlock(&sc->mutex); |
9c84b797 S |
1193 | return; |
1194 | } | |
8feceb67 | 1195 | |
3867cf6a S |
1196 | /* Ensure HW is awake when we try to shut it down. */ |
1197 | ath9k_ps_wakeup(sc); | |
1198 | ||
766ec4a9 | 1199 | if (ah->btcoex_hw.enabled) { |
af03abec | 1200 | ath9k_hw_btcoex_disable(ah); |
766ec4a9 | 1201 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1202 | ath9k_btcoex_timer_pause(sc); |
1773912b VT |
1203 | } |
1204 | ||
6a6733f2 LR |
1205 | spin_lock_bh(&sc->sc_pcu_lock); |
1206 | ||
203043f5 SG |
1207 | /* prevent tasklets to enable interrupts once we disable them */ |
1208 | ah->imask &= ~ATH9K_INT_GLOBAL; | |
1209 | ||
ff37e337 S |
1210 | /* make sure h/w will not generate any interrupt |
1211 | * before setting the invalid flag. */ | |
4df3071e | 1212 | ath9k_hw_disable_interrupts(ah); |
ff37e337 S |
1213 | |
1214 | if (!(sc->sc_flags & SC_OP_INVALID)) { | |
043a0405 | 1215 | ath_drain_all_txq(sc, false); |
ff37e337 | 1216 | ath_stoprecv(sc); |
af03abec | 1217 | ath9k_hw_phy_disable(ah); |
6a6733f2 | 1218 | } else |
b77f483f | 1219 | sc->rx.rxlink = NULL; |
ff37e337 | 1220 | |
0d95521e FF |
1221 | if (sc->rx.frag) { |
1222 | dev_kfree_skb_any(sc->rx.frag); | |
1223 | sc->rx.frag = NULL; | |
1224 | } | |
1225 | ||
ff37e337 | 1226 | /* disable HAL and put h/w to sleep */ |
af03abec LR |
1227 | ath9k_hw_disable(ah); |
1228 | ath9k_hw_configpcipowersave(ah, 1, 1); | |
6a6733f2 LR |
1229 | |
1230 | spin_unlock_bh(&sc->sc_pcu_lock); | |
1231 | ||
203043f5 SG |
1232 | /* we can now sync irq and kill any running tasklets, since we already |
1233 | * disabled interrupts and not holding a spin lock */ | |
1234 | synchronize_irq(sc->irq); | |
1235 | tasklet_kill(&sc->intr_tq); | |
1236 | tasklet_kill(&sc->bcon_tasklet); | |
1237 | ||
3867cf6a S |
1238 | ath9k_ps_restore(sc); |
1239 | ||
a08e7ade LR |
1240 | sc->ps_idle = true; |
1241 | ath_radio_disable(sc, hw); | |
ff37e337 S |
1242 | |
1243 | sc->sc_flags |= SC_OP_INVALID; | |
500c064d | 1244 | |
98c316e3 | 1245 | pm_qos_update_request(&sc->pm_qos_req, PM_QOS_DEFAULT_VALUE); |
10598c12 | 1246 | |
141b38b6 S |
1247 | mutex_unlock(&sc->mutex); |
1248 | ||
226afe68 | 1249 | ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
1250 | } |
1251 | ||
4801416c BG |
1252 | bool ath9k_uses_beacons(int type) |
1253 | { | |
1254 | switch (type) { | |
1255 | case NL80211_IFTYPE_AP: | |
1256 | case NL80211_IFTYPE_ADHOC: | |
1257 | case NL80211_IFTYPE_MESH_POINT: | |
1258 | return true; | |
1259 | default: | |
1260 | return false; | |
1261 | } | |
1262 | } | |
1263 | ||
1264 | static void ath9k_reclaim_beacon(struct ath_softc *sc, | |
1265 | struct ieee80211_vif *vif) | |
f078f209 | 1266 | { |
1ed32e4f | 1267 | struct ath_vif *avp = (void *)vif->drv_priv; |
8feceb67 | 1268 | |
4801416c BG |
1269 | /* Disable SWBA interrupt */ |
1270 | sc->sc_ah->imask &= ~ATH9K_INT_SWBA; | |
1271 | ath9k_ps_wakeup(sc); | |
1272 | ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask); | |
1273 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1274 | tasklet_kill(&sc->bcon_tasklet); | |
1275 | ath9k_ps_restore(sc); | |
1276 | ||
1277 | ath_beacon_return(sc, avp); | |
1278 | sc->sc_flags &= ~SC_OP_BEACONS; | |
1279 | ||
1280 | if (sc->nbcnvifs > 0) { | |
1281 | /* Re-enable beaconing */ | |
1282 | sc->sc_ah->imask |= ATH9K_INT_SWBA; | |
1283 | ath9k_ps_wakeup(sc); | |
1284 | ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask); | |
1285 | ath9k_ps_restore(sc); | |
1286 | } | |
1287 | } | |
1288 | ||
1289 | static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) | |
1290 | { | |
1291 | struct ath9k_vif_iter_data *iter_data = data; | |
1292 | int i; | |
1293 | ||
1294 | if (iter_data->hw_macaddr) | |
1295 | for (i = 0; i < ETH_ALEN; i++) | |
1296 | iter_data->mask[i] &= | |
1297 | ~(iter_data->hw_macaddr[i] ^ mac[i]); | |
141b38b6 | 1298 | |
1ed32e4f | 1299 | switch (vif->type) { |
4801416c BG |
1300 | case NL80211_IFTYPE_AP: |
1301 | iter_data->naps++; | |
f078f209 | 1302 | break; |
4801416c BG |
1303 | case NL80211_IFTYPE_STATION: |
1304 | iter_data->nstations++; | |
e51f3eff | 1305 | break; |
05c914fe | 1306 | case NL80211_IFTYPE_ADHOC: |
4801416c BG |
1307 | iter_data->nadhocs++; |
1308 | break; | |
9cb5412b | 1309 | case NL80211_IFTYPE_MESH_POINT: |
4801416c BG |
1310 | iter_data->nmeshes++; |
1311 | break; | |
1312 | case NL80211_IFTYPE_WDS: | |
1313 | iter_data->nwds++; | |
f078f209 LR |
1314 | break; |
1315 | default: | |
4801416c BG |
1316 | iter_data->nothers++; |
1317 | break; | |
f078f209 | 1318 | } |
4801416c | 1319 | } |
f078f209 | 1320 | |
4801416c BG |
1321 | /* Called with sc->mutex held. */ |
1322 | void ath9k_calculate_iter_data(struct ieee80211_hw *hw, | |
1323 | struct ieee80211_vif *vif, | |
1324 | struct ath9k_vif_iter_data *iter_data) | |
1325 | { | |
9ac58615 | 1326 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1327 | struct ath_hw *ah = sc->sc_ah; |
1328 | struct ath_common *common = ath9k_hw_common(ah); | |
8feceb67 | 1329 | |
4801416c BG |
1330 | /* |
1331 | * Use the hardware MAC address as reference, the hardware uses it | |
1332 | * together with the BSSID mask when matching addresses. | |
1333 | */ | |
1334 | memset(iter_data, 0, sizeof(*iter_data)); | |
1335 | iter_data->hw_macaddr = common->macaddr; | |
1336 | memset(&iter_data->mask, 0xff, ETH_ALEN); | |
5640b08e | 1337 | |
4801416c BG |
1338 | if (vif) |
1339 | ath9k_vif_iter(iter_data, vif->addr, vif); | |
1340 | ||
1341 | /* Get list of all active MAC addresses */ | |
4801416c BG |
1342 | ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter, |
1343 | iter_data); | |
4801416c | 1344 | } |
8ca21f01 | 1345 | |
4801416c BG |
1346 | /* Called with sc->mutex held. */ |
1347 | static void ath9k_calculate_summary_state(struct ieee80211_hw *hw, | |
1348 | struct ieee80211_vif *vif) | |
1349 | { | |
9ac58615 | 1350 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1351 | struct ath_hw *ah = sc->sc_ah; |
1352 | struct ath_common *common = ath9k_hw_common(ah); | |
1353 | struct ath9k_vif_iter_data iter_data; | |
8ca21f01 | 1354 | |
4801416c | 1355 | ath9k_calculate_iter_data(hw, vif, &iter_data); |
2c3db3d5 | 1356 | |
4c89fe95 | 1357 | ath9k_ps_wakeup(sc); |
4801416c BG |
1358 | /* Set BSSID mask. */ |
1359 | memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); | |
1360 | ath_hw_setbssidmask(common); | |
1361 | ||
1362 | /* Set op-mode & TSF */ | |
1363 | if (iter_data.naps > 0) { | |
3069168c | 1364 | ath9k_hw_set_tsfadjust(ah, 1); |
b238e90e | 1365 | sc->sc_flags |= SC_OP_TSF_RESET; |
4801416c BG |
1366 | ah->opmode = NL80211_IFTYPE_AP; |
1367 | } else { | |
1368 | ath9k_hw_set_tsfadjust(ah, 0); | |
1369 | sc->sc_flags &= ~SC_OP_TSF_RESET; | |
5640b08e | 1370 | |
4801416c BG |
1371 | if (iter_data.nwds + iter_data.nmeshes) |
1372 | ah->opmode = NL80211_IFTYPE_AP; | |
1373 | else if (iter_data.nadhocs) | |
1374 | ah->opmode = NL80211_IFTYPE_ADHOC; | |
1375 | else | |
1376 | ah->opmode = NL80211_IFTYPE_STATION; | |
1377 | } | |
5640b08e | 1378 | |
4e30ffa2 VN |
1379 | /* |
1380 | * Enable MIB interrupts when there are hardware phy counters. | |
4e30ffa2 | 1381 | */ |
4801416c | 1382 | if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) { |
3448f912 LR |
1383 | if (ah->config.enable_ani) |
1384 | ah->imask |= ATH9K_INT_MIB; | |
3069168c | 1385 | ah->imask |= ATH9K_INT_TSFOOR; |
4801416c BG |
1386 | } else { |
1387 | ah->imask &= ~ATH9K_INT_MIB; | |
1388 | ah->imask &= ~ATH9K_INT_TSFOOR; | |
4af9cf4f S |
1389 | } |
1390 | ||
3069168c | 1391 | ath9k_hw_set_interrupts(ah, ah->imask); |
4c89fe95 | 1392 | ath9k_ps_restore(sc); |
4e30ffa2 | 1393 | |
4801416c BG |
1394 | /* Set up ANI */ |
1395 | if ((iter_data.naps + iter_data.nadhocs) > 0) { | |
6c3118e2 | 1396 | sc->sc_flags |= SC_OP_ANI_RUN; |
3d536acf | 1397 | ath_start_ani(common); |
4801416c BG |
1398 | } else { |
1399 | sc->sc_flags &= ~SC_OP_ANI_RUN; | |
1400 | del_timer_sync(&common->ani.timer); | |
6c3118e2 | 1401 | } |
4801416c | 1402 | } |
6f255425 | 1403 | |
4801416c BG |
1404 | /* Called with sc->mutex held, vif counts set up properly. */ |
1405 | static void ath9k_do_vif_add_setup(struct ieee80211_hw *hw, | |
1406 | struct ieee80211_vif *vif) | |
1407 | { | |
9ac58615 | 1408 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1409 | |
1410 | ath9k_calculate_summary_state(hw, vif); | |
1411 | ||
1412 | if (ath9k_uses_beacons(vif->type)) { | |
1413 | int error; | |
1414 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1415 | /* This may fail because upper levels do not have beacons | |
1416 | * properly configured yet. That's OK, we assume it | |
1417 | * will be properly configured and then we will be notified | |
1418 | * in the info_changed method and set up beacons properly | |
1419 | * there. | |
1420 | */ | |
9ac58615 | 1421 | error = ath_beacon_alloc(sc, vif); |
391bd1c4 | 1422 | if (!error) |
4801416c BG |
1423 | ath_beacon_config(sc, vif); |
1424 | } | |
f078f209 LR |
1425 | } |
1426 | ||
4801416c BG |
1427 | |
1428 | static int ath9k_add_interface(struct ieee80211_hw *hw, | |
1429 | struct ieee80211_vif *vif) | |
6b3b991d | 1430 | { |
9ac58615 | 1431 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1432 | struct ath_hw *ah = sc->sc_ah; |
1433 | struct ath_common *common = ath9k_hw_common(ah); | |
6b3b991d | 1434 | struct ath_vif *avp = (void *)vif->drv_priv; |
4801416c | 1435 | int ret = 0; |
6b3b991d | 1436 | |
4801416c | 1437 | mutex_lock(&sc->mutex); |
6b3b991d | 1438 | |
4801416c BG |
1439 | switch (vif->type) { |
1440 | case NL80211_IFTYPE_STATION: | |
1441 | case NL80211_IFTYPE_WDS: | |
1442 | case NL80211_IFTYPE_ADHOC: | |
1443 | case NL80211_IFTYPE_AP: | |
1444 | case NL80211_IFTYPE_MESH_POINT: | |
1445 | break; | |
1446 | default: | |
1447 | ath_err(common, "Interface type %d not yet supported\n", | |
1448 | vif->type); | |
1449 | ret = -EOPNOTSUPP; | |
1450 | goto out; | |
1451 | } | |
6b3b991d | 1452 | |
4801416c BG |
1453 | if (ath9k_uses_beacons(vif->type)) { |
1454 | if (sc->nbcnvifs >= ATH_BCBUF) { | |
1455 | ath_err(common, "Not enough beacon buffers when adding" | |
1456 | " new interface of type: %i\n", | |
1457 | vif->type); | |
1458 | ret = -ENOBUFS; | |
1459 | goto out; | |
1460 | } | |
1461 | } | |
1462 | ||
1463 | if ((vif->type == NL80211_IFTYPE_ADHOC) && | |
1464 | sc->nvifs > 0) { | |
1465 | ath_err(common, "Cannot create ADHOC interface when other" | |
1466 | " interfaces already exist.\n"); | |
1467 | ret = -EINVAL; | |
1468 | goto out; | |
6b3b991d | 1469 | } |
4801416c BG |
1470 | |
1471 | ath_dbg(common, ATH_DBG_CONFIG, | |
1472 | "Attach a VIF of type: %d\n", vif->type); | |
1473 | ||
1474 | /* Set the VIF opmode */ | |
1475 | avp->av_opmode = vif->type; | |
1476 | avp->av_bslot = -1; | |
1477 | ||
1478 | sc->nvifs++; | |
1479 | ||
1480 | ath9k_do_vif_add_setup(hw, vif); | |
1481 | out: | |
1482 | mutex_unlock(&sc->mutex); | |
1483 | return ret; | |
6b3b991d RM |
1484 | } |
1485 | ||
1486 | static int ath9k_change_interface(struct ieee80211_hw *hw, | |
1487 | struct ieee80211_vif *vif, | |
1488 | enum nl80211_iftype new_type, | |
1489 | bool p2p) | |
1490 | { | |
9ac58615 | 1491 | struct ath_softc *sc = hw->priv; |
6b3b991d | 1492 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
6dab55bf | 1493 | int ret = 0; |
6b3b991d RM |
1494 | |
1495 | ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n"); | |
1496 | mutex_lock(&sc->mutex); | |
1497 | ||
4801416c BG |
1498 | /* See if new interface type is valid. */ |
1499 | if ((new_type == NL80211_IFTYPE_ADHOC) && | |
1500 | (sc->nvifs > 1)) { | |
1501 | ath_err(common, "When using ADHOC, it must be the only" | |
1502 | " interface.\n"); | |
1503 | ret = -EINVAL; | |
1504 | goto out; | |
1505 | } | |
1506 | ||
1507 | if (ath9k_uses_beacons(new_type) && | |
1508 | !ath9k_uses_beacons(vif->type)) { | |
6b3b991d RM |
1509 | if (sc->nbcnvifs >= ATH_BCBUF) { |
1510 | ath_err(common, "No beacon slot available\n"); | |
6dab55bf DC |
1511 | ret = -ENOBUFS; |
1512 | goto out; | |
6b3b991d | 1513 | } |
6b3b991d | 1514 | } |
4801416c BG |
1515 | |
1516 | /* Clean up old vif stuff */ | |
1517 | if (ath9k_uses_beacons(vif->type)) | |
1518 | ath9k_reclaim_beacon(sc, vif); | |
1519 | ||
1520 | /* Add new settings */ | |
6b3b991d RM |
1521 | vif->type = new_type; |
1522 | vif->p2p = p2p; | |
1523 | ||
4801416c | 1524 | ath9k_do_vif_add_setup(hw, vif); |
6dab55bf | 1525 | out: |
6b3b991d | 1526 | mutex_unlock(&sc->mutex); |
6dab55bf | 1527 | return ret; |
6b3b991d RM |
1528 | } |
1529 | ||
8feceb67 | 1530 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1531 | struct ieee80211_vif *vif) |
f078f209 | 1532 | { |
9ac58615 | 1533 | struct ath_softc *sc = hw->priv; |
c46917bb | 1534 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
f078f209 | 1535 | |
226afe68 | 1536 | ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 1537 | |
141b38b6 S |
1538 | mutex_lock(&sc->mutex); |
1539 | ||
4801416c | 1540 | sc->nvifs--; |
580f0b8a | 1541 | |
8feceb67 | 1542 | /* Reclaim beacon resources */ |
4801416c | 1543 | if (ath9k_uses_beacons(vif->type)) |
6b3b991d | 1544 | ath9k_reclaim_beacon(sc, vif); |
2c3db3d5 | 1545 | |
4801416c | 1546 | ath9k_calculate_summary_state(hw, NULL); |
141b38b6 S |
1547 | |
1548 | mutex_unlock(&sc->mutex); | |
f078f209 LR |
1549 | } |
1550 | ||
fbab7390 | 1551 | static void ath9k_enable_ps(struct ath_softc *sc) |
3f7c5c10 | 1552 | { |
3069168c PR |
1553 | struct ath_hw *ah = sc->sc_ah; |
1554 | ||
3f7c5c10 | 1555 | sc->ps_enabled = true; |
3069168c PR |
1556 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1557 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1558 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
1559 | ath9k_hw_set_interrupts(ah, ah->imask); | |
3f7c5c10 | 1560 | } |
fdf76622 | 1561 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1562 | } |
3f7c5c10 SB |
1563 | } |
1564 | ||
845d708e SB |
1565 | static void ath9k_disable_ps(struct ath_softc *sc) |
1566 | { | |
1567 | struct ath_hw *ah = sc->sc_ah; | |
1568 | ||
1569 | sc->ps_enabled = false; | |
1570 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
1571 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | |
1572 | ath9k_hw_setrxabort(ah, 0); | |
1573 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | | |
1574 | PS_WAIT_FOR_CAB | | |
1575 | PS_WAIT_FOR_PSPOLL_DATA | | |
1576 | PS_WAIT_FOR_TX_ACK); | |
1577 | if (ah->imask & ATH9K_INT_TIM_TIMER) { | |
1578 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
1579 | ath9k_hw_set_interrupts(ah, ah->imask); | |
1580 | } | |
1581 | } | |
1582 | ||
1583 | } | |
1584 | ||
e8975581 | 1585 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1586 | { |
9ac58615 | 1587 | struct ath_softc *sc = hw->priv; |
3430098a FF |
1588 | struct ath_hw *ah = sc->sc_ah; |
1589 | struct ath_common *common = ath9k_hw_common(ah); | |
e8975581 | 1590 | struct ieee80211_conf *conf = &hw->conf; |
7545daf4 | 1591 | bool disable_radio = false; |
f078f209 | 1592 | |
aa33de09 | 1593 | mutex_lock(&sc->mutex); |
141b38b6 | 1594 | |
194b7c13 LR |
1595 | /* |
1596 | * Leave this as the first check because we need to turn on the | |
1597 | * radio if it was disabled before prior to processing the rest | |
1598 | * of the changes. Likewise we must only disable the radio towards | |
1599 | * the end. | |
1600 | */ | |
64839170 | 1601 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
7545daf4 FF |
1602 | sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); |
1603 | if (!sc->ps_idle) { | |
68a89116 | 1604 | ath_radio_enable(sc, hw); |
226afe68 JP |
1605 | ath_dbg(common, ATH_DBG_CONFIG, |
1606 | "not-idle: enabling radio\n"); | |
7545daf4 FF |
1607 | } else { |
1608 | disable_radio = true; | |
64839170 LR |
1609 | } |
1610 | } | |
1611 | ||
e7824a50 LR |
1612 | /* |
1613 | * We just prepare to enable PS. We have to wait until our AP has | |
1614 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1615 | * those ACKs and end up retransmitting the same null data frames. | |
1616 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1617 | */ | |
3cbb5dd7 | 1618 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
8ab2cd09 LR |
1619 | unsigned long flags; |
1620 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
fbab7390 SB |
1621 | if (conf->flags & IEEE80211_CONF_PS) |
1622 | ath9k_enable_ps(sc); | |
845d708e SB |
1623 | else |
1624 | ath9k_disable_ps(sc); | |
8ab2cd09 | 1625 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
3cbb5dd7 VN |
1626 | } |
1627 | ||
199afd9d S |
1628 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1629 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
226afe68 JP |
1630 | ath_dbg(common, ATH_DBG_CONFIG, |
1631 | "Monitor mode is enabled\n"); | |
5f841b41 RM |
1632 | sc->sc_ah->is_monitoring = true; |
1633 | } else { | |
226afe68 JP |
1634 | ath_dbg(common, ATH_DBG_CONFIG, |
1635 | "Monitor mode is disabled\n"); | |
5f841b41 | 1636 | sc->sc_ah->is_monitoring = false; |
199afd9d S |
1637 | } |
1638 | } | |
1639 | ||
4797938c | 1640 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
99405f93 | 1641 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 1642 | int pos = curchan->hw_value; |
3430098a FF |
1643 | int old_pos = -1; |
1644 | unsigned long flags; | |
1645 | ||
1646 | if (ah->curchan) | |
1647 | old_pos = ah->curchan - &ah->channels[0]; | |
ae5eb026 | 1648 | |
5ee08656 FF |
1649 | if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) |
1650 | sc->sc_flags |= SC_OP_OFFCHANNEL; | |
1651 | else | |
1652 | sc->sc_flags &= ~SC_OP_OFFCHANNEL; | |
0e2dedf9 | 1653 | |
226afe68 JP |
1654 | ath_dbg(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", |
1655 | curchan->center_freq); | |
f078f209 | 1656 | |
de87f736 RM |
1657 | ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos], |
1658 | curchan, conf->channel_type); | |
e11602b7 | 1659 | |
3430098a FF |
1660 | /* update survey stats for the old channel before switching */ |
1661 | spin_lock_irqsave(&common->cc_lock, flags); | |
1662 | ath_update_survey_stats(sc); | |
1663 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
1664 | ||
1665 | /* | |
1666 | * If the operating channel changes, change the survey in-use flags | |
1667 | * along with it. | |
1668 | * Reset the survey data for the new channel, unless we're switching | |
1669 | * back to the operating channel from an off-channel operation. | |
1670 | */ | |
1671 | if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && | |
1672 | sc->cur_survey != &sc->survey[pos]) { | |
1673 | ||
1674 | if (sc->cur_survey) | |
1675 | sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; | |
1676 | ||
1677 | sc->cur_survey = &sc->survey[pos]; | |
1678 | ||
1679 | memset(sc->cur_survey, 0, sizeof(struct survey_info)); | |
1680 | sc->cur_survey->filled |= SURVEY_INFO_IN_USE; | |
1681 | } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) { | |
1682 | memset(&sc->survey[pos], 0, sizeof(struct survey_info)); | |
1683 | } | |
1684 | ||
0e2dedf9 | 1685 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
3800276a | 1686 | ath_err(common, "Unable to set channel\n"); |
aa33de09 | 1687 | mutex_unlock(&sc->mutex); |
e11602b7 S |
1688 | return -EINVAL; |
1689 | } | |
3430098a FF |
1690 | |
1691 | /* | |
1692 | * The most recent snapshot of channel->noisefloor for the old | |
1693 | * channel is only available after the hardware reset. Copy it to | |
1694 | * the survey stats now. | |
1695 | */ | |
1696 | if (old_pos >= 0) | |
1697 | ath_update_survey_nf(sc, old_pos); | |
094d05dc | 1698 | } |
f078f209 | 1699 | |
c9f6a656 | 1700 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
17d7904d | 1701 | sc->config.txpowlimit = 2 * conf->power_level; |
783cd01e | 1702 | ath9k_ps_wakeup(sc); |
5048e8c3 RM |
1703 | ath9k_cmn_update_txpow(ah, sc->curtxpow, |
1704 | sc->config.txpowlimit, &sc->curtxpow); | |
783cd01e | 1705 | ath9k_ps_restore(sc); |
c9f6a656 | 1706 | } |
f078f209 | 1707 | |
64839170 | 1708 | if (disable_radio) { |
226afe68 | 1709 | ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); |
68a89116 | 1710 | ath_radio_disable(sc, hw); |
64839170 LR |
1711 | } |
1712 | ||
aa33de09 | 1713 | mutex_unlock(&sc->mutex); |
141b38b6 | 1714 | |
f078f209 LR |
1715 | return 0; |
1716 | } | |
1717 | ||
8feceb67 VT |
1718 | #define SUPPORTED_FILTERS \ |
1719 | (FIF_PROMISC_IN_BSS | \ | |
1720 | FIF_ALLMULTI | \ | |
1721 | FIF_CONTROL | \ | |
af6a3fc7 | 1722 | FIF_PSPOLL | \ |
8feceb67 VT |
1723 | FIF_OTHER_BSS | \ |
1724 | FIF_BCN_PRBRESP_PROMISC | \ | |
9c1d8e4a | 1725 | FIF_PROBE_REQ | \ |
8feceb67 | 1726 | FIF_FCSFAIL) |
c83be688 | 1727 | |
8feceb67 VT |
1728 | /* FIXME: sc->sc_full_reset ? */ |
1729 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1730 | unsigned int changed_flags, | |
1731 | unsigned int *total_flags, | |
3ac64bee | 1732 | u64 multicast) |
8feceb67 | 1733 | { |
9ac58615 | 1734 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1735 | u32 rfilt; |
f078f209 | 1736 | |
8feceb67 VT |
1737 | changed_flags &= SUPPORTED_FILTERS; |
1738 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1739 | |
b77f483f | 1740 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1741 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1742 | rfilt = ath_calcrxfilter(sc); |
1743 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1744 | ath9k_ps_restore(sc); |
f078f209 | 1745 | |
226afe68 JP |
1746 | ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, |
1747 | "Set HW RX filter: 0x%x\n", rfilt); | |
8feceb67 | 1748 | } |
f078f209 | 1749 | |
4ca77860 JB |
1750 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1751 | struct ieee80211_vif *vif, | |
1752 | struct ieee80211_sta *sta) | |
8feceb67 | 1753 | { |
9ac58615 | 1754 | struct ath_softc *sc = hw->priv; |
f078f209 | 1755 | |
4ca77860 JB |
1756 | ath_node_attach(sc, sta); |
1757 | ||
1758 | return 0; | |
1759 | } | |
1760 | ||
1761 | static int ath9k_sta_remove(struct ieee80211_hw *hw, | |
1762 | struct ieee80211_vif *vif, | |
1763 | struct ieee80211_sta *sta) | |
1764 | { | |
9ac58615 | 1765 | struct ath_softc *sc = hw->priv; |
4ca77860 JB |
1766 | |
1767 | ath_node_detach(sc, sta); | |
1768 | ||
1769 | return 0; | |
f078f209 LR |
1770 | } |
1771 | ||
141b38b6 | 1772 | static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
8feceb67 | 1773 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1774 | { |
9ac58615 | 1775 | struct ath_softc *sc = hw->priv; |
c46917bb | 1776 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
066dae93 | 1777 | struct ath_txq *txq; |
8feceb67 | 1778 | struct ath9k_tx_queue_info qi; |
066dae93 | 1779 | int ret = 0; |
f078f209 | 1780 | |
8feceb67 VT |
1781 | if (queue >= WME_NUM_AC) |
1782 | return 0; | |
f078f209 | 1783 | |
066dae93 FF |
1784 | txq = sc->tx.txq_map[queue]; |
1785 | ||
141b38b6 S |
1786 | mutex_lock(&sc->mutex); |
1787 | ||
1ffb0610 S |
1788 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1789 | ||
8feceb67 VT |
1790 | qi.tqi_aifs = params->aifs; |
1791 | qi.tqi_cwmin = params->cw_min; | |
1792 | qi.tqi_cwmax = params->cw_max; | |
1793 | qi.tqi_burstTime = params->txop; | |
f078f209 | 1794 | |
226afe68 JP |
1795 | ath_dbg(common, ATH_DBG_CONFIG, |
1796 | "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | |
1797 | queue, txq->axq_qnum, params->aifs, params->cw_min, | |
1798 | params->cw_max, params->txop); | |
f078f209 | 1799 | |
066dae93 | 1800 | ret = ath_txq_update(sc, txq->axq_qnum, &qi); |
8feceb67 | 1801 | if (ret) |
3800276a | 1802 | ath_err(common, "TXQ Update failed\n"); |
f078f209 | 1803 | |
94db2936 | 1804 | if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) |
066dae93 | 1805 | if (queue == WME_AC_BE && !ret) |
94db2936 VN |
1806 | ath_beaconq_config(sc); |
1807 | ||
141b38b6 S |
1808 | mutex_unlock(&sc->mutex); |
1809 | ||
8feceb67 VT |
1810 | return ret; |
1811 | } | |
f078f209 | 1812 | |
8feceb67 VT |
1813 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1814 | enum set_key_cmd cmd, | |
dc822b5d JB |
1815 | struct ieee80211_vif *vif, |
1816 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1817 | struct ieee80211_key_conf *key) |
1818 | { | |
9ac58615 | 1819 | struct ath_softc *sc = hw->priv; |
c46917bb | 1820 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1821 | int ret = 0; |
f078f209 | 1822 | |
3e6109c5 | 1823 | if (ath9k_modparam_nohwcrypt) |
b3bd89ce JM |
1824 | return -ENOSPC; |
1825 | ||
141b38b6 | 1826 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1827 | ath9k_ps_wakeup(sc); |
226afe68 | 1828 | ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n"); |
f078f209 | 1829 | |
8feceb67 VT |
1830 | switch (cmd) { |
1831 | case SET_KEY: | |
040e539e | 1832 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1833 | if (ret >= 0) { |
1834 | key->hw_key_idx = ret; | |
8feceb67 VT |
1835 | /* push IV and Michael MIC generation to stack */ |
1836 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
97359d12 | 1837 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) |
8feceb67 | 1838 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
97359d12 JB |
1839 | if (sc->sc_ah->sw_mgmt_crypto && |
1840 | key->cipher == WLAN_CIPHER_SUITE_CCMP) | |
0ced0e17 | 1841 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; |
6ace2891 | 1842 | ret = 0; |
8feceb67 VT |
1843 | } |
1844 | break; | |
1845 | case DISABLE_KEY: | |
040e539e | 1846 | ath_key_delete(common, key); |
8feceb67 VT |
1847 | break; |
1848 | default: | |
1849 | ret = -EINVAL; | |
1850 | } | |
f078f209 | 1851 | |
3cbb5dd7 | 1852 | ath9k_ps_restore(sc); |
141b38b6 S |
1853 | mutex_unlock(&sc->mutex); |
1854 | ||
8feceb67 VT |
1855 | return ret; |
1856 | } | |
f078f209 | 1857 | |
8feceb67 VT |
1858 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1859 | struct ieee80211_vif *vif, | |
1860 | struct ieee80211_bss_conf *bss_conf, | |
1861 | u32 changed) | |
1862 | { | |
9ac58615 | 1863 | struct ath_softc *sc = hw->priv; |
2d0ddec5 | 1864 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1865 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1866 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1867 | int slottime; |
c6089ccc | 1868 | int error; |
f078f209 | 1869 | |
141b38b6 S |
1870 | mutex_lock(&sc->mutex); |
1871 | ||
c6089ccc S |
1872 | if (changed & BSS_CHANGED_BSSID) { |
1873 | /* Set BSSID */ | |
1874 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | |
1875 | memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); | |
1510718d | 1876 | common->curaid = 0; |
f2b2143e | 1877 | ath9k_hw_write_associd(ah); |
2d0ddec5 | 1878 | |
c6089ccc S |
1879 | /* Set aggregation protection mode parameters */ |
1880 | sc->config.ath_aggr_prot = 0; | |
2d0ddec5 | 1881 | |
226afe68 JP |
1882 | ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n", |
1883 | common->curbssid, common->curaid); | |
2d0ddec5 | 1884 | |
c6089ccc S |
1885 | /* need to reconfigure the beacon */ |
1886 | sc->sc_flags &= ~SC_OP_BEACONS ; | |
1887 | } | |
2d0ddec5 | 1888 | |
c6089ccc S |
1889 | /* Enable transmission of beacons (AP, IBSS, MESH) */ |
1890 | if ((changed & BSS_CHANGED_BEACON) || | |
1891 | ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { | |
1892 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
9ac58615 | 1893 | error = ath_beacon_alloc(sc, vif); |
c6089ccc S |
1894 | if (!error) |
1895 | ath_beacon_config(sc, vif); | |
0005baf4 FF |
1896 | } |
1897 | ||
1898 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
1899 | if (bss_conf->use_short_slot) | |
1900 | slottime = 9; | |
1901 | else | |
1902 | slottime = 20; | |
1903 | if (vif->type == NL80211_IFTYPE_AP) { | |
1904 | /* | |
1905 | * Defer update, so that connected stations can adjust | |
1906 | * their settings at the same time. | |
1907 | * See beacon.c for more details | |
1908 | */ | |
1909 | sc->beacon.slottime = slottime; | |
1910 | sc->beacon.updateslot = UPDATE; | |
1911 | } else { | |
1912 | ah->slottime = slottime; | |
1913 | ath9k_hw_init_global_settings(ah); | |
1914 | } | |
2d0ddec5 JB |
1915 | } |
1916 | ||
c6089ccc S |
1917 | /* Disable transmission of beacons */ |
1918 | if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon) | |
1919 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 | 1920 | |
c6089ccc S |
1921 | if (changed & BSS_CHANGED_BEACON_INT) { |
1922 | sc->beacon_interval = bss_conf->beacon_int; | |
1923 | /* | |
1924 | * In case of AP mode, the HW TSF has to be reset | |
1925 | * when the beacon interval changes. | |
1926 | */ | |
1927 | if (vif->type == NL80211_IFTYPE_AP) { | |
1928 | sc->sc_flags |= SC_OP_TSF_RESET; | |
1929 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
9ac58615 | 1930 | error = ath_beacon_alloc(sc, vif); |
2d0ddec5 JB |
1931 | if (!error) |
1932 | ath_beacon_config(sc, vif); | |
c6089ccc S |
1933 | } else { |
1934 | ath_beacon_config(sc, vif); | |
2d0ddec5 JB |
1935 | } |
1936 | } | |
1937 | ||
8feceb67 | 1938 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
226afe68 JP |
1939 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
1940 | bss_conf->use_short_preamble); | |
8feceb67 VT |
1941 | if (bss_conf->use_short_preamble) |
1942 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
1943 | else | |
1944 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
1945 | } | |
f078f209 | 1946 | |
8feceb67 | 1947 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
226afe68 JP |
1948 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
1949 | bss_conf->use_cts_prot); | |
8feceb67 VT |
1950 | if (bss_conf->use_cts_prot && |
1951 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
1952 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
1953 | else | |
1954 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
1955 | } | |
f078f209 | 1956 | |
8feceb67 | 1957 | if (changed & BSS_CHANGED_ASSOC) { |
226afe68 | 1958 | ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", |
8feceb67 | 1959 | bss_conf->assoc); |
9fa23e17 | 1960 | ath9k_bss_assoc_info(sc, hw, vif, bss_conf); |
8feceb67 | 1961 | } |
141b38b6 S |
1962 | |
1963 | mutex_unlock(&sc->mutex); | |
8feceb67 | 1964 | } |
f078f209 | 1965 | |
8feceb67 VT |
1966 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) |
1967 | { | |
9ac58615 | 1968 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1969 | u64 tsf; |
f078f209 | 1970 | |
141b38b6 | 1971 | mutex_lock(&sc->mutex); |
9abbfb27 | 1972 | ath9k_ps_wakeup(sc); |
141b38b6 | 1973 | tsf = ath9k_hw_gettsf64(sc->sc_ah); |
9abbfb27 | 1974 | ath9k_ps_restore(sc); |
141b38b6 | 1975 | mutex_unlock(&sc->mutex); |
f078f209 | 1976 | |
8feceb67 VT |
1977 | return tsf; |
1978 | } | |
f078f209 | 1979 | |
3b5d665b AF |
1980 | static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) |
1981 | { | |
9ac58615 | 1982 | struct ath_softc *sc = hw->priv; |
3b5d665b | 1983 | |
141b38b6 | 1984 | mutex_lock(&sc->mutex); |
9abbfb27 | 1985 | ath9k_ps_wakeup(sc); |
141b38b6 | 1986 | ath9k_hw_settsf64(sc->sc_ah, tsf); |
9abbfb27 | 1987 | ath9k_ps_restore(sc); |
141b38b6 | 1988 | mutex_unlock(&sc->mutex); |
3b5d665b AF |
1989 | } |
1990 | ||
8feceb67 VT |
1991 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) |
1992 | { | |
9ac58615 | 1993 | struct ath_softc *sc = hw->priv; |
c83be688 | 1994 | |
141b38b6 | 1995 | mutex_lock(&sc->mutex); |
21526d57 LR |
1996 | |
1997 | ath9k_ps_wakeup(sc); | |
141b38b6 | 1998 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
1999 | ath9k_ps_restore(sc); |
2000 | ||
141b38b6 | 2001 | mutex_unlock(&sc->mutex); |
8feceb67 | 2002 | } |
f078f209 | 2003 | |
8feceb67 | 2004 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 2005 | struct ieee80211_vif *vif, |
141b38b6 S |
2006 | enum ieee80211_ampdu_mlme_action action, |
2007 | struct ieee80211_sta *sta, | |
0b01f030 | 2008 | u16 tid, u16 *ssn, u8 buf_size) |
8feceb67 | 2009 | { |
9ac58615 | 2010 | struct ath_softc *sc = hw->priv; |
8feceb67 | 2011 | int ret = 0; |
f078f209 | 2012 | |
85ad181e JB |
2013 | local_bh_disable(); |
2014 | ||
8feceb67 VT |
2015 | switch (action) { |
2016 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
2017 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
2018 | ret = -ENOTSUPP; | |
8feceb67 VT |
2019 | break; |
2020 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
2021 | break; |
2022 | case IEEE80211_AMPDU_TX_START: | |
71a3bf3e FF |
2023 | if (!(sc->sc_flags & SC_OP_TXAGGR)) |
2024 | return -EOPNOTSUPP; | |
2025 | ||
8b685ba9 | 2026 | ath9k_ps_wakeup(sc); |
231c3a1f FF |
2027 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
2028 | if (!ret) | |
2029 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
8b685ba9 | 2030 | ath9k_ps_restore(sc); |
8feceb67 VT |
2031 | break; |
2032 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 2033 | ath9k_ps_wakeup(sc); |
f83da965 | 2034 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 2035 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 2036 | ath9k_ps_restore(sc); |
8feceb67 | 2037 | break; |
b1720231 | 2038 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 2039 | ath9k_ps_wakeup(sc); |
8469cdef | 2040 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 2041 | ath9k_ps_restore(sc); |
8469cdef | 2042 | break; |
8feceb67 | 2043 | default: |
3800276a | 2044 | ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); |
8feceb67 VT |
2045 | } |
2046 | ||
85ad181e JB |
2047 | local_bh_enable(); |
2048 | ||
8feceb67 | 2049 | return ret; |
f078f209 LR |
2050 | } |
2051 | ||
62dad5b0 BP |
2052 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
2053 | struct survey_info *survey) | |
2054 | { | |
9ac58615 | 2055 | struct ath_softc *sc = hw->priv; |
3430098a | 2056 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39162dbe | 2057 | struct ieee80211_supported_band *sband; |
3430098a FF |
2058 | struct ieee80211_channel *chan; |
2059 | unsigned long flags; | |
2060 | int pos; | |
2061 | ||
2062 | spin_lock_irqsave(&common->cc_lock, flags); | |
2063 | if (idx == 0) | |
2064 | ath_update_survey_stats(sc); | |
39162dbe FF |
2065 | |
2066 | sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ]; | |
2067 | if (sband && idx >= sband->n_channels) { | |
2068 | idx -= sband->n_channels; | |
2069 | sband = NULL; | |
2070 | } | |
62dad5b0 | 2071 | |
39162dbe FF |
2072 | if (!sband) |
2073 | sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ]; | |
62dad5b0 | 2074 | |
3430098a FF |
2075 | if (!sband || idx >= sband->n_channels) { |
2076 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
2077 | return -ENOENT; | |
4f1a5a4b | 2078 | } |
62dad5b0 | 2079 | |
3430098a FF |
2080 | chan = &sband->channels[idx]; |
2081 | pos = chan->hw_value; | |
2082 | memcpy(survey, &sc->survey[pos], sizeof(*survey)); | |
2083 | survey->channel = chan; | |
2084 | spin_unlock_irqrestore(&common->cc_lock, flags); | |
2085 | ||
62dad5b0 BP |
2086 | return 0; |
2087 | } | |
2088 | ||
e239d859 FF |
2089 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
2090 | { | |
9ac58615 | 2091 | struct ath_softc *sc = hw->priv; |
e239d859 FF |
2092 | struct ath_hw *ah = sc->sc_ah; |
2093 | ||
2094 | mutex_lock(&sc->mutex); | |
2095 | ah->coverage_class = coverage_class; | |
2096 | ath9k_hw_init_global_settings(ah); | |
2097 | mutex_unlock(&sc->mutex); | |
2098 | } | |
2099 | ||
6baff7f9 | 2100 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2101 | .tx = ath9k_tx, |
2102 | .start = ath9k_start, | |
2103 | .stop = ath9k_stop, | |
2104 | .add_interface = ath9k_add_interface, | |
6b3b991d | 2105 | .change_interface = ath9k_change_interface, |
8feceb67 VT |
2106 | .remove_interface = ath9k_remove_interface, |
2107 | .config = ath9k_config, | |
8feceb67 | 2108 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2109 | .sta_add = ath9k_sta_add, |
2110 | .sta_remove = ath9k_sta_remove, | |
8feceb67 | 2111 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2112 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2113 | .set_key = ath9k_set_key, |
8feceb67 | 2114 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2115 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2116 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2117 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2118 | .get_survey = ath9k_get_survey, |
3b319aae | 2119 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2120 | .set_coverage_class = ath9k_set_coverage_class, |
8feceb67 | 2121 | }; |