Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
5b68138e | 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
69081624 | 18 | #include <linux/delay.h> |
394cf0a1 | 19 | #include "ath9k.h" |
af03abec | 20 | #include "btcoex.h" |
f078f209 | 21 | |
313eb87f | 22 | u8 ath9k_parse_mpdudensity(u8 mpdudensity) |
ff37e337 S |
23 | { |
24 | /* | |
25 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
26 | * 0 for no restriction | |
27 | * 1 for 1/4 us | |
28 | * 2 for 1/2 us | |
29 | * 3 for 1 us | |
30 | * 4 for 2 us | |
31 | * 5 for 4 us | |
32 | * 6 for 8 us | |
33 | * 7 for 16 us | |
34 | */ | |
35 | switch (mpdudensity) { | |
36 | case 0: | |
37 | return 0; | |
38 | case 1: | |
39 | case 2: | |
40 | case 3: | |
41 | /* Our lower layer calculations limit our precision to | |
42 | 1 microsecond */ | |
43 | return 1; | |
44 | case 4: | |
45 | return 2; | |
46 | case 5: | |
47 | return 4; | |
48 | case 6: | |
49 | return 8; | |
50 | case 7: | |
51 | return 16; | |
52 | default: | |
53 | return 0; | |
54 | } | |
55 | } | |
56 | ||
e2d389b5 SM |
57 | static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq, |
58 | bool sw_pending) | |
69081624 VT |
59 | { |
60 | bool pending = false; | |
61 | ||
62 | spin_lock_bh(&txq->axq_lock); | |
63 | ||
b7367285 | 64 | if (txq->axq_depth) { |
69081624 | 65 | pending = true; |
b7367285 SM |
66 | goto out; |
67 | } | |
69081624 | 68 | |
e2d389b5 SM |
69 | if (!sw_pending) |
70 | goto out; | |
71 | ||
0453531e FF |
72 | if (txq->mac80211_qnum >= 0) { |
73 | struct list_head *list; | |
74 | ||
75 | list = &sc->cur_chan->acq[txq->mac80211_qnum]; | |
76 | if (!list_empty(list)) | |
77 | pending = true; | |
78 | } | |
b7367285 | 79 | out: |
69081624 VT |
80 | spin_unlock_bh(&txq->axq_lock); |
81 | return pending; | |
82 | } | |
83 | ||
6d79cb4c | 84 | static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
85 | { |
86 | unsigned long flags; | |
87 | bool ret; | |
88 | ||
9ecdef4b LR |
89 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
90 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
91 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
92 | |
93 | return ret; | |
94 | } | |
95 | ||
bf3dac5a FF |
96 | void ath_ps_full_sleep(unsigned long data) |
97 | { | |
98 | struct ath_softc *sc = (struct ath_softc *) data; | |
99 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
100 | bool reset; | |
101 | ||
102 | spin_lock(&common->cc_lock); | |
103 | ath_hw_cycle_counters_update(common); | |
104 | spin_unlock(&common->cc_lock); | |
105 | ||
106 | ath9k_hw_setrxabort(sc->sc_ah, 1); | |
107 | ath9k_hw_stopdmarecv(sc->sc_ah, &reset); | |
108 | ||
109 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); | |
110 | } | |
111 | ||
a91d75ae LR |
112 | void ath9k_ps_wakeup(struct ath_softc *sc) |
113 | { | |
898c914a | 114 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
a91d75ae | 115 | unsigned long flags; |
fbb078fc | 116 | enum ath9k_power_mode power_mode; |
a91d75ae LR |
117 | |
118 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
119 | if (++sc->ps_usecount != 1) | |
120 | goto unlock; | |
121 | ||
bf3dac5a | 122 | del_timer_sync(&sc->sleep_timer); |
fbb078fc | 123 | power_mode = sc->sc_ah->power_mode; |
9ecdef4b | 124 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae | 125 | |
898c914a FF |
126 | /* |
127 | * While the hardware is asleep, the cycle counters contain no | |
128 | * useful data. Better clear them now so that they don't mess up | |
129 | * survey data results. | |
130 | */ | |
fbb078fc FF |
131 | if (power_mode != ATH9K_PM_AWAKE) { |
132 | spin_lock(&common->cc_lock); | |
133 | ath_hw_cycle_counters_update(common); | |
134 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
c9ae6ab4 | 135 | memset(&common->cc_ani, 0, sizeof(common->cc_ani)); |
fbb078fc FF |
136 | spin_unlock(&common->cc_lock); |
137 | } | |
898c914a | 138 | |
a91d75ae LR |
139 | unlock: |
140 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
141 | } | |
142 | ||
143 | void ath9k_ps_restore(struct ath_softc *sc) | |
144 | { | |
898c914a | 145 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
c6c539f0 | 146 | enum ath9k_power_mode mode; |
a91d75ae LR |
147 | unsigned long flags; |
148 | ||
149 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
150 | if (--sc->ps_usecount != 0) | |
151 | goto unlock; | |
152 | ||
ad128860 | 153 | if (sc->ps_idle) { |
bf3dac5a FF |
154 | mod_timer(&sc->sleep_timer, jiffies + HZ / 10); |
155 | goto unlock; | |
156 | } | |
157 | ||
158 | if (sc->ps_enabled && | |
ad128860 SM |
159 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | |
160 | PS_WAIT_FOR_CAB | | |
161 | PS_WAIT_FOR_PSPOLL_DATA | | |
424749c7 RM |
162 | PS_WAIT_FOR_TX_ACK | |
163 | PS_WAIT_FOR_ANI))) { | |
c6c539f0 | 164 | mode = ATH9K_PM_NETWORK_SLEEP; |
08d4df41 RM |
165 | if (ath9k_hw_btcoex_is_enabled(sc->sc_ah)) |
166 | ath9k_btcoex_stop_gen_timer(sc); | |
ad128860 | 167 | } else { |
c6c539f0 | 168 | goto unlock; |
ad128860 | 169 | } |
c6c539f0 FF |
170 | |
171 | spin_lock(&common->cc_lock); | |
172 | ath_hw_cycle_counters_update(common); | |
173 | spin_unlock(&common->cc_lock); | |
174 | ||
1a8f0d39 | 175 | ath9k_hw_setpower(sc->sc_ah, mode); |
a91d75ae LR |
176 | |
177 | unlock: | |
178 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
179 | } | |
180 | ||
9adcf440 | 181 | static void __ath_cancel_work(struct ath_softc *sc) |
ff37e337 | 182 | { |
5ee08656 | 183 | cancel_work_sync(&sc->paprd_work); |
5ee08656 | 184 | cancel_delayed_work_sync(&sc->tx_complete_work); |
181fb18d | 185 | cancel_delayed_work_sync(&sc->hw_pll_work); |
fad29cd2 | 186 | |
bf52592f | 187 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
fad29cd2 SM |
188 | if (ath9k_hw_mci_is_enabled(sc->sc_ah)) |
189 | cancel_work_sync(&sc->mci_work); | |
bf52592f | 190 | #endif |
9adcf440 | 191 | } |
5ee08656 | 192 | |
e60001e7 | 193 | void ath_cancel_work(struct ath_softc *sc) |
9adcf440 FF |
194 | { |
195 | __ath_cancel_work(sc); | |
196 | cancel_work_sync(&sc->hw_reset_work); | |
197 | } | |
3cbb5dd7 | 198 | |
e60001e7 | 199 | void ath_restart_work(struct ath_softc *sc) |
af68abad | 200 | { |
af68abad SM |
201 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
202 | ||
19c36160 | 203 | if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah)) |
af68abad SM |
204 | ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, |
205 | msecs_to_jiffies(ATH_PLL_WORK_INTERVAL)); | |
206 | ||
da0d45f7 | 207 | ath_start_ani(sc); |
af68abad SM |
208 | } |
209 | ||
9ebea382 | 210 | static bool ath_prepare_reset(struct ath_softc *sc) |
9adcf440 FF |
211 | { |
212 | struct ath_hw *ah = sc->sc_ah; | |
ceea2a51 | 213 | bool ret = true; |
6a6733f2 | 214 | |
9adcf440 | 215 | ieee80211_stop_queues(sc->hw); |
da0d45f7 | 216 | ath_stop_ani(sc); |
9adcf440 | 217 | ath9k_hw_disable_interrupts(ah); |
8b3f4616 | 218 | |
300f77c0 FF |
219 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
220 | ret &= ath_stoprecv(sc); | |
221 | ret &= ath_drain_all_txq(sc); | |
222 | } else { | |
223 | ret &= ath_drain_all_txq(sc); | |
224 | ret &= ath_stoprecv(sc); | |
225 | } | |
ceea2a51 | 226 | |
9adcf440 FF |
227 | return ret; |
228 | } | |
ff37e337 | 229 | |
9adcf440 FF |
230 | static bool ath_complete_reset(struct ath_softc *sc, bool start) |
231 | { | |
232 | struct ath_hw *ah = sc->sc_ah; | |
233 | struct ath_common *common = ath9k_hw_common(ah); | |
196fb860 | 234 | unsigned long flags; |
c0d7c7af | 235 | |
9019f646 | 236 | ath9k_calculate_summary_state(sc, sc->cur_chan); |
19ec477f | 237 | ath_startrecv(sc); |
d385c5c2 FF |
238 | ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower, |
239 | sc->cur_chan->txpower, | |
240 | &sc->cur_chan->cur_txpower); | |
eefa01dd | 241 | clear_bit(ATH_OP_HW_RESET, &common->op_flags); |
3989279c | 242 | |
fbbcd146 | 243 | if (!sc->cur_chan->offchannel && start) { |
8d7e09dd FF |
244 | /* restore per chanctx TSF timer */ |
245 | if (sc->cur_chan->tsf_val) { | |
246 | u32 offset; | |
247 | ||
248 | offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, | |
249 | NULL); | |
250 | ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset); | |
251 | } | |
252 | ||
253 | ||
eefa01dd | 254 | if (!test_bit(ATH_OP_BEACONS, &common->op_flags)) |
196fb860 SM |
255 | goto work; |
256 | ||
196fb860 | 257 | if (ah->opmode == NL80211_IFTYPE_STATION && |
eefa01dd | 258 | test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) { |
196fb860 SM |
259 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
260 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
261 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
a6768280 SM |
262 | } else { |
263 | ath9k_set_beacon(sc); | |
196fb860 SM |
264 | } |
265 | work: | |
af68abad | 266 | ath_restart_work(sc); |
0453531e | 267 | ath_txq_schedule_all(sc); |
5ee08656 FF |
268 | } |
269 | ||
071aa9a8 | 270 | sc->gtt_cnt = 0; |
9a9c4fbc RM |
271 | |
272 | ath9k_hw_set_interrupts(ah); | |
273 | ath9k_hw_enable_interrupts(ah); | |
5ba8d9d2 | 274 | ieee80211_wake_queues(sc->hw); |
d463af4a FF |
275 | ath9k_p2p_ps_timer(sc); |
276 | ||
9adcf440 FF |
277 | return true; |
278 | } | |
279 | ||
5555c955 | 280 | static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan) |
9adcf440 FF |
281 | { |
282 | struct ath_hw *ah = sc->sc_ah; | |
283 | struct ath_common *common = ath9k_hw_common(ah); | |
284 | struct ath9k_hw_cal_data *caldata = NULL; | |
285 | bool fastcc = true; | |
9adcf440 FF |
286 | int r; |
287 | ||
288 | __ath_cancel_work(sc); | |
289 | ||
e3f31175 | 290 | disable_irq(sc->irq); |
4668cce5 | 291 | tasklet_disable(&sc->intr_tq); |
eaf04a69 | 292 | tasklet_disable(&sc->bcon_tasklet); |
9adcf440 | 293 | spin_lock_bh(&sc->sc_pcu_lock); |
92460412 | 294 | |
fbbcd146 | 295 | if (!sc->cur_chan->offchannel) { |
9adcf440 | 296 | fastcc = false; |
b01459e8 | 297 | caldata = &sc->cur_chan->caldata; |
9adcf440 FF |
298 | } |
299 | ||
300 | if (!hchan) { | |
301 | fastcc = false; | |
9adcf440 FF |
302 | hchan = ah->curchan; |
303 | } | |
304 | ||
9ebea382 | 305 | if (!ath_prepare_reset(sc)) |
9adcf440 FF |
306 | fastcc = false; |
307 | ||
9ea3598b SM |
308 | if (ath9k_is_chanctx_enabled()) |
309 | fastcc = false; | |
310 | ||
d6067f0e RM |
311 | spin_lock_bh(&sc->chan_lock); |
312 | sc->cur_chandef = sc->cur_chan->chandef; | |
313 | spin_unlock_bh(&sc->chan_lock); | |
bff11766 | 314 | |
d2182b69 | 315 | ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n", |
feced201 | 316 | hchan->channel, IS_CHAN_HT40(hchan), fastcc); |
9adcf440 FF |
317 | |
318 | r = ath9k_hw_reset(ah, hchan, caldata, fastcc); | |
319 | if (r) { | |
320 | ath_err(common, | |
321 | "Unable to reset channel, reset status %d\n", r); | |
f50b1cd3 RS |
322 | |
323 | ath9k_hw_enable_interrupts(ah); | |
324 | ath9k_queue_reset(sc, RESET_TYPE_BB_HANG); | |
325 | ||
9adcf440 FF |
326 | goto out; |
327 | } | |
328 | ||
e82cb03f | 329 | if (ath9k_hw_mci_is_enabled(sc->sc_ah) && |
fbbcd146 | 330 | sc->cur_chan->offchannel) |
e82cb03f RM |
331 | ath9k_mci_set_txpower(sc, true, false); |
332 | ||
9adcf440 FF |
333 | if (!ath_complete_reset(sc, true)) |
334 | r = -EIO; | |
335 | ||
336 | out: | |
e3f31175 | 337 | enable_irq(sc->irq); |
6a6733f2 | 338 | spin_unlock_bh(&sc->sc_pcu_lock); |
eaf04a69 | 339 | tasklet_enable(&sc->bcon_tasklet); |
4668cce5 FF |
340 | tasklet_enable(&sc->intr_tq); |
341 | ||
9adcf440 FF |
342 | return r; |
343 | } | |
344 | ||
7e1e3864 BG |
345 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, |
346 | struct ieee80211_vif *vif) | |
ff37e337 S |
347 | { |
348 | struct ath_node *an; | |
ff37e337 S |
349 | an = (struct ath_node *)sta->drv_priv; |
350 | ||
a145daf7 | 351 | an->sc = sc; |
7f010c93 | 352 | an->sta = sta; |
7e1e3864 | 353 | an->vif = vif; |
4bbf4414 | 354 | memset(&an->key_idx, 0, sizeof(an->key_idx)); |
3d4e20f2 | 355 | |
dd5ee59b | 356 | ath_tx_node_init(sc, an); |
44b47a7d LB |
357 | |
358 | ath_dynack_node_init(sc->sc_ah, an); | |
ff37e337 S |
359 | } |
360 | ||
361 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
362 | { | |
363 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
dd5ee59b | 364 | ath_tx_node_cleanup(sc, an); |
44b47a7d LB |
365 | |
366 | ath_dynack_node_deinit(sc->sc_ah, an); | |
ff37e337 S |
367 | } |
368 | ||
55624204 | 369 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
370 | { |
371 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 372 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 373 | struct ath_common *common = ath9k_hw_common(ah); |
124b979b | 374 | enum ath_reset_type type; |
07c15a3f | 375 | unsigned long flags; |
17d7904d | 376 | u32 status = sc->intrstatus; |
b5c80475 | 377 | u32 rxmask; |
ff37e337 | 378 | |
e3927007 FF |
379 | ath9k_ps_wakeup(sc); |
380 | spin_lock(&sc->sc_pcu_lock); | |
381 | ||
6549a860 SM |
382 | if (status & ATH9K_INT_FATAL) { |
383 | type = RESET_TYPE_FATAL_INT; | |
124b979b | 384 | ath9k_queue_reset(sc, type); |
c6cc47b1 SM |
385 | |
386 | /* | |
387 | * Increment the ref. counter here so that | |
388 | * interrupts are enabled in the reset routine. | |
389 | */ | |
390 | atomic_inc(&ah->intr_ref_cnt); | |
affad456 | 391 | ath_dbg(common, RESET, "FATAL: Skipping interrupts\n"); |
e3927007 | 392 | goto out; |
063d8be3 | 393 | } |
ff37e337 | 394 | |
6549a860 SM |
395 | if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && |
396 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
0c759977 SM |
397 | spin_lock(&common->cc_lock); |
398 | ath_hw_cycle_counters_update(common); | |
399 | ar9003_hw_bb_watchdog_dbg_info(ah); | |
400 | spin_unlock(&common->cc_lock); | |
401 | ||
6549a860 SM |
402 | if (ar9003_hw_bb_watchdog_check(ah)) { |
403 | type = RESET_TYPE_BB_WATCHDOG; | |
404 | ath9k_queue_reset(sc, type); | |
405 | ||
406 | /* | |
407 | * Increment the ref. counter here so that | |
408 | * interrupts are enabled in the reset routine. | |
409 | */ | |
410 | atomic_inc(&ah->intr_ref_cnt); | |
affad456 | 411 | ath_dbg(common, RESET, |
6549a860 SM |
412 | "BB_WATCHDOG: Skipping interrupts\n"); |
413 | goto out; | |
414 | } | |
415 | } | |
416 | ||
071aa9a8 SM |
417 | if (status & ATH9K_INT_GTT) { |
418 | sc->gtt_cnt++; | |
419 | ||
420 | if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) { | |
421 | type = RESET_TYPE_TX_GTT; | |
422 | ath9k_queue_reset(sc, type); | |
423 | atomic_inc(&ah->intr_ref_cnt); | |
affad456 | 424 | ath_dbg(common, RESET, |
071aa9a8 SM |
425 | "GTT: Skipping interrupts\n"); |
426 | goto out; | |
427 | } | |
428 | } | |
429 | ||
07c15a3f | 430 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
4105f807 RM |
431 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
432 | /* | |
433 | * TSF sync does not look correct; remain awake to sync with | |
434 | * the next Beacon. | |
435 | */ | |
d2182b69 | 436 | ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n"); |
e8fe7336 | 437 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
4105f807 | 438 | } |
07c15a3f | 439 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
4105f807 | 440 | |
b5c80475 FF |
441 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
442 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
443 | ATH9K_INT_RXORN); | |
444 | else | |
445 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
446 | ||
447 | if (status & rxmask) { | |
b5c80475 FF |
448 | /* Check for high priority Rx first */ |
449 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
450 | (status & ATH9K_INT_RXHP)) | |
451 | ath_rx_tasklet(sc, 0, true); | |
452 | ||
453 | ath_rx_tasklet(sc, 0, false); | |
ff37e337 S |
454 | } |
455 | ||
e5003249 | 456 | if (status & ATH9K_INT_TX) { |
071aa9a8 SM |
457 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
458 | /* | |
459 | * For EDMA chips, TX completion is enabled for the | |
460 | * beacon queue, so if a beacon has been transmitted | |
461 | * successfully after a GTT interrupt, the GTT counter | |
462 | * gets reset to zero here. | |
463 | */ | |
3b745c7b | 464 | sc->gtt_cnt = 0; |
071aa9a8 | 465 | |
e5003249 | 466 | ath_tx_edma_tasklet(sc); |
071aa9a8 | 467 | } else { |
e5003249 | 468 | ath_tx_tasklet(sc); |
071aa9a8 | 469 | } |
10e23181 FF |
470 | |
471 | wake_up(&sc->tx_wait); | |
e5003249 | 472 | } |
063d8be3 | 473 | |
c67ce339 FF |
474 | if (status & ATH9K_INT_GENTIMER) |
475 | ath_gen_timer_isr(sc->sc_ah); | |
476 | ||
56ca0dba | 477 | ath9k_btcoex_handle_interrupt(sc, status); |
19686ddf | 478 | |
ff37e337 | 479 | /* re-enable hardware interrupt */ |
4df3071e | 480 | ath9k_hw_enable_interrupts(ah); |
c6cc47b1 | 481 | out: |
52671e43 | 482 | spin_unlock(&sc->sc_pcu_lock); |
153e080d | 483 | ath9k_ps_restore(sc); |
ff37e337 S |
484 | } |
485 | ||
6baff7f9 | 486 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 487 | { |
063d8be3 S |
488 | #define SCHED_INTR ( \ |
489 | ATH9K_INT_FATAL | \ | |
a4d86d95 | 490 | ATH9K_INT_BB_WATCHDOG | \ |
063d8be3 S |
491 | ATH9K_INT_RXORN | \ |
492 | ATH9K_INT_RXEOL | \ | |
493 | ATH9K_INT_RX | \ | |
b5c80475 FF |
494 | ATH9K_INT_RXLP | \ |
495 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
496 | ATH9K_INT_TX | \ |
497 | ATH9K_INT_BMISS | \ | |
498 | ATH9K_INT_CST | \ | |
071aa9a8 | 499 | ATH9K_INT_GTT | \ |
ebb8e1d7 | 500 | ATH9K_INT_TSFOOR | \ |
40dc5392 MSS |
501 | ATH9K_INT_GENTIMER | \ |
502 | ATH9K_INT_MCI) | |
063d8be3 | 503 | |
ff37e337 | 504 | struct ath_softc *sc = dev; |
cbe61d8a | 505 | struct ath_hw *ah = sc->sc_ah; |
eefa01dd | 506 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 | 507 | enum ath9k_int status; |
78c8a950 | 508 | u32 sync_cause = 0; |
ff37e337 S |
509 | bool sched = false; |
510 | ||
063d8be3 S |
511 | /* |
512 | * The hardware is not ready/present, don't | |
513 | * touch anything. Note this can happen early | |
514 | * on if the IRQ is shared. | |
515 | */ | |
2ba7d144 | 516 | if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags)) |
063d8be3 | 517 | return IRQ_NONE; |
ff37e337 | 518 | |
872b5d81 | 519 | /* shared irq, not for us */ |
153e080d | 520 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 521 | return IRQ_NONE; |
063d8be3 S |
522 | |
523 | /* | |
524 | * Figure out the reason(s) for the interrupt. Note | |
525 | * that the hal returns a pseudo-ISR that may include | |
526 | * bits we haven't explicitly enabled so we mask the | |
527 | * value to insure we only process bits we requested. | |
528 | */ | |
6a4d05dc FF |
529 | ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */ |
530 | ath9k_debug_sync_cause(sc, sync_cause); | |
3069168c | 531 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 532 | |
e3f31175 | 533 | if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) |
872b5d81 FF |
534 | return IRQ_HANDLED; |
535 | ||
063d8be3 S |
536 | /* |
537 | * If there are no status bits set, then this interrupt was not | |
538 | * for me (should have been caught above). | |
539 | */ | |
153e080d | 540 | if (!status) |
063d8be3 | 541 | return IRQ_NONE; |
ff37e337 | 542 | |
063d8be3 S |
543 | /* Cache the status */ |
544 | sc->intrstatus = status; | |
545 | ||
546 | if (status & SCHED_INTR) | |
547 | sched = true; | |
548 | ||
549 | /* | |
3b580144 FF |
550 | * If a FATAL interrupt is received, we have to reset the chip |
551 | * immediately. | |
063d8be3 | 552 | */ |
3b580144 | 553 | if (status & ATH9K_INT_FATAL) |
063d8be3 S |
554 | goto chip_reset; |
555 | ||
a6bb860b | 556 | if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) && |
0c759977 | 557 | (status & ATH9K_INT_BB_WATCHDOG)) |
08578b8f | 558 | goto chip_reset; |
e60001e7 | 559 | |
063d8be3 S |
560 | if (status & ATH9K_INT_SWBA) |
561 | tasklet_schedule(&sc->bcon_tasklet); | |
562 | ||
563 | if (status & ATH9K_INT_TXURN) | |
564 | ath9k_hw_updatetxtriglevel(ah, true); | |
565 | ||
0682c9b5 RM |
566 | if (status & ATH9K_INT_RXEOL) { |
567 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
72d874c6 | 568 | ath9k_hw_set_interrupts(ah); |
b5c80475 FF |
569 | } |
570 | ||
153e080d VT |
571 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
572 | if (status & ATH9K_INT_TIM_TIMER) { | |
ff9f0b63 LR |
573 | if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle)) |
574 | goto chip_reset; | |
063d8be3 S |
575 | /* Clear RxAbort bit so that we can |
576 | * receive frames */ | |
9ecdef4b | 577 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
07c15a3f | 578 | spin_lock(&sc->sc_pm_lock); |
153e080d | 579 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 580 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
07c15a3f | 581 | spin_unlock(&sc->sc_pm_lock); |
ff37e337 | 582 | } |
063d8be3 S |
583 | |
584 | chip_reset: | |
ff37e337 | 585 | |
817e11de S |
586 | ath_debug_stat_interrupt(sc, status); |
587 | ||
ff37e337 | 588 | if (sched) { |
4df3071e FF |
589 | /* turn off every interrupt */ |
590 | ath9k_hw_disable_interrupts(ah); | |
ff37e337 S |
591 | tasklet_schedule(&sc->intr_tq); |
592 | } | |
593 | ||
594 | return IRQ_HANDLED; | |
063d8be3 S |
595 | |
596 | #undef SCHED_INTR | |
ff37e337 S |
597 | } |
598 | ||
ae2ff239 SM |
599 | /* |
600 | * This function is called when a HW reset cannot be deferred | |
601 | * and has to be immediate. | |
602 | */ | |
5555c955 | 603 | int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan) |
ff37e337 | 604 | { |
ae2ff239 | 605 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
ec30326e | 606 | int r; |
ff37e337 | 607 | |
872b5d81 | 608 | ath9k_hw_kill_interrupts(sc->sc_ah); |
ae2ff239 SM |
609 | set_bit(ATH_OP_HW_RESET, &common->op_flags); |
610 | ||
783cd01e | 611 | ath9k_ps_wakeup(sc); |
5555c955 | 612 | r = ath_reset_internal(sc, hchan); |
783cd01e | 613 | ath9k_ps_restore(sc); |
2ab81d4a | 614 | |
ae8d2858 | 615 | return r; |
ff37e337 S |
616 | } |
617 | ||
ae2ff239 SM |
618 | /* |
619 | * When a HW reset can be deferred, it is added to the | |
620 | * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before | |
621 | * queueing. | |
622 | */ | |
124b979b RM |
623 | void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type) |
624 | { | |
eefa01dd | 625 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
124b979b RM |
626 | #ifdef CONFIG_ATH9K_DEBUGFS |
627 | RESET_STAT_INC(sc, type); | |
628 | #endif | |
872b5d81 | 629 | ath9k_hw_kill_interrupts(sc->sc_ah); |
eefa01dd | 630 | set_bit(ATH_OP_HW_RESET, &common->op_flags); |
124b979b RM |
631 | ieee80211_queue_work(sc->hw, &sc->hw_reset_work); |
632 | } | |
633 | ||
236de514 FF |
634 | void ath_reset_work(struct work_struct *work) |
635 | { | |
636 | struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work); | |
637 | ||
5555c955 SM |
638 | ath9k_ps_wakeup(sc); |
639 | ath_reset_internal(sc, NULL); | |
640 | ath9k_ps_restore(sc); | |
236de514 FF |
641 | } |
642 | ||
ff37e337 S |
643 | /**********************/ |
644 | /* mac80211 callbacks */ | |
645 | /**********************/ | |
646 | ||
8feceb67 | 647 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 648 | { |
9ac58615 | 649 | struct ath_softc *sc = hw->priv; |
af03abec | 650 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 651 | struct ath_common *common = ath9k_hw_common(ah); |
39305635 | 652 | struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan; |
fbbcd146 | 653 | struct ath_chanctx *ctx = sc->cur_chan; |
ff37e337 | 654 | struct ath9k_channel *init_channel; |
82880a7c | 655 | int r; |
f078f209 | 656 | |
d2182b69 | 657 | ath_dbg(common, CONFIG, |
226afe68 JP |
658 | "Starting driver with initial channel: %d MHz\n", |
659 | curchan->center_freq); | |
f078f209 | 660 | |
f62d816f | 661 | ath9k_ps_wakeup(sc); |
141b38b6 S |
662 | mutex_lock(&sc->mutex); |
663 | ||
fbbcd146 | 664 | init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef); |
bff11766 | 665 | sc->cur_chandef = hw->conf.chandef; |
ff37e337 S |
666 | |
667 | /* Reset SERDES registers */ | |
84c87dc8 | 668 | ath9k_hw_configpcipowersave(ah, false); |
ff37e337 S |
669 | |
670 | /* | |
671 | * The basic interface to setting the hardware in a good | |
672 | * state is ``reset''. On return the hardware is known to | |
673 | * be powered up and with interrupts disabled. This must | |
674 | * be followed by initialization of the appropriate bits | |
675 | * and then setup of the interrupt mask. | |
676 | */ | |
4bdd1e97 | 677 | spin_lock_bh(&sc->sc_pcu_lock); |
c0c11741 FF |
678 | |
679 | atomic_set(&ah->intr_ref_cnt, -1); | |
680 | ||
20bd2a09 | 681 | r = ath9k_hw_reset(ah, init_channel, ah->caldata, false); |
ae8d2858 | 682 | if (r) { |
3800276a JP |
683 | ath_err(common, |
684 | "Unable to reset hardware; reset status %d (freq %u MHz)\n", | |
685 | r, curchan->center_freq); | |
ceb26a60 | 686 | ah->reset_power_on = false; |
ff37e337 | 687 | } |
ff37e337 | 688 | |
ff37e337 | 689 | /* Setup our intr mask. */ |
b5c80475 FF |
690 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
691 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
692 | ATH9K_INT_GLOBAL; | |
693 | ||
694 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f | 695 | ah->imask |= ATH9K_INT_RXHP | |
a6bb860b | 696 | ATH9K_INT_RXLP; |
b5c80475 FF |
697 | else |
698 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 699 | |
a6bb860b SM |
700 | if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) |
701 | ah->imask |= ATH9K_INT_BB_WATCHDOG; | |
702 | ||
071aa9a8 SM |
703 | /* |
704 | * Enable GTT interrupts only for AR9003/AR9004 chips | |
705 | * for now. | |
706 | */ | |
707 | if (AR_SREV_9300_20_OR_LATER(ah)) | |
708 | ah->imask |= ATH9K_INT_GTT; | |
ff37e337 | 709 | |
af03abec | 710 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 711 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 712 | |
e270e776 | 713 | ath_mci_enable(sc); |
40dc5392 | 714 | |
eefa01dd | 715 | clear_bit(ATH_OP_INVALID, &common->op_flags); |
5f841b41 | 716 | sc->sc_ah->is_monitoring = false; |
ff37e337 | 717 | |
ceb26a60 FF |
718 | if (!ath_complete_reset(sc, false)) |
719 | ah->reset_power_on = false; | |
ff37e337 | 720 | |
79d4db12 | 721 | if (ah->led_pin >= 0) |
aeeb2065 SM |
722 | ath9k_hw_set_gpio(ah, ah->led_pin, |
723 | (ah->config.led_active_high) ? 1 : 0); | |
c0c11741 FF |
724 | |
725 | /* | |
726 | * Reset key cache to sane defaults (all entries cleared) instead of | |
727 | * semi-random values after suspend/resume. | |
728 | */ | |
729 | ath9k_cmn_init_crypto(sc->sc_ah); | |
730 | ||
a35051ce FF |
731 | ath9k_hw_reset_tsf(ah); |
732 | ||
9adcf440 | 733 | spin_unlock_bh(&sc->sc_pcu_lock); |
164ace38 | 734 | |
141b38b6 S |
735 | mutex_unlock(&sc->mutex); |
736 | ||
f62d816f FF |
737 | ath9k_ps_restore(sc); |
738 | ||
ed14dc0a MP |
739 | ath9k_rng_start(sc); |
740 | ||
ceb26a60 | 741 | return 0; |
f078f209 LR |
742 | } |
743 | ||
36323f81 TH |
744 | static void ath9k_tx(struct ieee80211_hw *hw, |
745 | struct ieee80211_tx_control *control, | |
746 | struct sk_buff *skb) | |
f078f209 | 747 | { |
9ac58615 | 748 | struct ath_softc *sc = hw->priv; |
c46917bb | 749 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 750 | struct ath_tx_control txctl; |
1bc14880 | 751 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
07c15a3f | 752 | unsigned long flags; |
528f0c6b | 753 | |
96148326 | 754 | if (sc->ps_enabled) { |
dc8c4585 JM |
755 | /* |
756 | * mac80211 does not set PM field for normal data frames, so we | |
757 | * need to update that based on the current PS mode. | |
758 | */ | |
759 | if (ieee80211_is_data(hdr->frame_control) && | |
760 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
761 | !ieee80211_has_pm(hdr->frame_control)) { | |
d2182b69 | 762 | ath_dbg(common, PS, |
226afe68 | 763 | "Add PM=1 for a TX frame while in PS mode\n"); |
dc8c4585 JM |
764 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
765 | } | |
766 | } | |
767 | ||
ad128860 | 768 | if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) { |
9a23f9ca JM |
769 | /* |
770 | * We are using PS-Poll and mac80211 can request TX while in | |
771 | * power save mode. Need to wake up hardware for the TX to be | |
772 | * completed and if needed, also for RX of buffered frames. | |
773 | */ | |
9a23f9ca | 774 | ath9k_ps_wakeup(sc); |
07c15a3f | 775 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
fdf76622 VT |
776 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
777 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 778 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
d2182b69 | 779 | ath_dbg(common, PS, |
226afe68 | 780 | "Sending PS-Poll to pick a buffered frame\n"); |
1b04b930 | 781 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 782 | } else { |
d2182b69 | 783 | ath_dbg(common, PS, "Wake up to complete TX\n"); |
1b04b930 | 784 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
785 | } |
786 | /* | |
787 | * The actual restore operation will happen only after | |
ad128860 | 788 | * the ps_flags bit is cleared. We are just dropping |
9a23f9ca JM |
789 | * the ps_usecount here. |
790 | */ | |
07c15a3f | 791 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
9a23f9ca JM |
792 | ath9k_ps_restore(sc); |
793 | } | |
794 | ||
ad128860 SM |
795 | /* |
796 | * Cannot tx while the hardware is in full sleep, it first needs a full | |
797 | * chip reset to recover from that | |
798 | */ | |
799 | if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) { | |
800 | ath_err(common, "TX while HW is in FULL_SLEEP mode\n"); | |
801 | goto exit; | |
802 | } | |
803 | ||
528f0c6b | 804 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
066dae93 | 805 | txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)]; |
36323f81 | 806 | txctl.sta = control->sta; |
528f0c6b | 807 | |
d2182b69 | 808 | ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 809 | |
c52f33d0 | 810 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
d2182b69 | 811 | ath_dbg(common, XMIT, "TX failed\n"); |
a5a0bca1 | 812 | TX_STAT_INC(txctl.txq->axq_qnum, txfailed); |
528f0c6b | 813 | goto exit; |
8feceb67 VT |
814 | } |
815 | ||
7bb45683 | 816 | return; |
528f0c6b | 817 | exit: |
249ee722 | 818 | ieee80211_free_txskb(hw, skb); |
f078f209 LR |
819 | } |
820 | ||
8feceb67 | 821 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 822 | { |
9ac58615 | 823 | struct ath_softc *sc = hw->priv; |
af03abec | 824 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 825 | struct ath_common *common = ath9k_hw_common(ah); |
c0c11741 | 826 | bool prev_idle; |
f078f209 | 827 | |
ea22df29 SM |
828 | ath9k_deinit_channel_context(sc); |
829 | ||
ed14dc0a MP |
830 | ath9k_rng_stop(sc); |
831 | ||
4c483817 S |
832 | mutex_lock(&sc->mutex); |
833 | ||
9adcf440 | 834 | ath_cancel_work(sc); |
c94dbff7 | 835 | |
eefa01dd | 836 | if (test_bit(ATH_OP_INVALID, &common->op_flags)) { |
d2182b69 | 837 | ath_dbg(common, ANY, "Device not present\n"); |
4c483817 | 838 | mutex_unlock(&sc->mutex); |
9c84b797 S |
839 | return; |
840 | } | |
8feceb67 | 841 | |
3867cf6a S |
842 | /* Ensure HW is awake when we try to shut it down. */ |
843 | ath9k_ps_wakeup(sc); | |
844 | ||
6a6733f2 LR |
845 | spin_lock_bh(&sc->sc_pcu_lock); |
846 | ||
203043f5 SG |
847 | /* prevent tasklets to enable interrupts once we disable them */ |
848 | ah->imask &= ~ATH9K_INT_GLOBAL; | |
849 | ||
ff37e337 S |
850 | /* make sure h/w will not generate any interrupt |
851 | * before setting the invalid flag. */ | |
4df3071e | 852 | ath9k_hw_disable_interrupts(ah); |
ff37e337 | 853 | |
c0c11741 FF |
854 | spin_unlock_bh(&sc->sc_pcu_lock); |
855 | ||
856 | /* we can now sync irq and kill any running tasklets, since we already | |
857 | * disabled interrupts and not holding a spin lock */ | |
858 | synchronize_irq(sc->irq); | |
859 | tasklet_kill(&sc->intr_tq); | |
860 | tasklet_kill(&sc->bcon_tasklet); | |
861 | ||
862 | prev_idle = sc->ps_idle; | |
863 | sc->ps_idle = true; | |
864 | ||
865 | spin_lock_bh(&sc->sc_pcu_lock); | |
866 | ||
79d4db12 | 867 | if (ah->led_pin >= 0) |
aeeb2065 SM |
868 | ath9k_hw_set_gpio(ah, ah->led_pin, |
869 | (ah->config.led_active_high) ? 0 : 1); | |
c0c11741 | 870 | |
9ebea382 | 871 | ath_prepare_reset(sc); |
ff37e337 | 872 | |
0d95521e FF |
873 | if (sc->rx.frag) { |
874 | dev_kfree_skb_any(sc->rx.frag); | |
875 | sc->rx.frag = NULL; | |
876 | } | |
877 | ||
c0c11741 | 878 | if (!ah->curchan) |
fbbcd146 FF |
879 | ah->curchan = ath9k_cmn_get_channel(hw, ah, |
880 | &sc->cur_chan->chandef); | |
6a6733f2 | 881 | |
c0c11741 | 882 | ath9k_hw_reset(ah, ah->curchan, ah->caldata, false); |
ef739ab6 FF |
883 | |
884 | set_bit(ATH_OP_INVALID, &common->op_flags); | |
885 | ||
c0c11741 | 886 | ath9k_hw_phy_disable(ah); |
6a6733f2 | 887 | |
c0c11741 | 888 | ath9k_hw_configpcipowersave(ah, true); |
203043f5 | 889 | |
c0c11741 | 890 | spin_unlock_bh(&sc->sc_pcu_lock); |
3867cf6a | 891 | |
c0c11741 | 892 | ath9k_ps_restore(sc); |
ff37e337 | 893 | |
c0c11741 | 894 | sc->ps_idle = prev_idle; |
500c064d | 895 | |
141b38b6 S |
896 | mutex_unlock(&sc->mutex); |
897 | ||
d2182b69 | 898 | ath_dbg(common, CONFIG, "Driver halt\n"); |
f078f209 LR |
899 | } |
900 | ||
c648ecb0 | 901 | static bool ath9k_uses_beacons(int type) |
4801416c BG |
902 | { |
903 | switch (type) { | |
904 | case NL80211_IFTYPE_AP: | |
905 | case NL80211_IFTYPE_ADHOC: | |
906 | case NL80211_IFTYPE_MESH_POINT: | |
907 | return true; | |
908 | default: | |
909 | return false; | |
910 | } | |
911 | } | |
912 | ||
4b93fd29 SM |
913 | static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data, |
914 | u8 *mac, struct ieee80211_vif *vif) | |
4801416c | 915 | { |
cb35582a | 916 | struct ath_vif *avp = (struct ath_vif *)vif->drv_priv; |
4801416c BG |
917 | int i; |
918 | ||
ab11bb28 | 919 | if (iter_data->has_hw_macaddr) { |
4801416c BG |
920 | for (i = 0; i < ETH_ALEN; i++) |
921 | iter_data->mask[i] &= | |
922 | ~(iter_data->hw_macaddr[i] ^ mac[i]); | |
ab11bb28 FF |
923 | } else { |
924 | memcpy(iter_data->hw_macaddr, mac, ETH_ALEN); | |
925 | iter_data->has_hw_macaddr = true; | |
926 | } | |
141b38b6 | 927 | |
9a9c4fbc RM |
928 | if (!vif->bss_conf.use_short_slot) |
929 | iter_data->slottime = ATH9K_SLOT_TIME_20; | |
930 | ||
1ed32e4f | 931 | switch (vif->type) { |
4801416c BG |
932 | case NL80211_IFTYPE_AP: |
933 | iter_data->naps++; | |
f078f209 | 934 | break; |
4801416c BG |
935 | case NL80211_IFTYPE_STATION: |
936 | iter_data->nstations++; | |
cb35582a | 937 | if (avp->assoc && !iter_data->primary_sta) |
9a9c4fbc | 938 | iter_data->primary_sta = vif; |
e51f3eff | 939 | break; |
862a336c JK |
940 | case NL80211_IFTYPE_OCB: |
941 | iter_data->nocbs++; | |
942 | break; | |
05c914fe | 943 | case NL80211_IFTYPE_ADHOC: |
4801416c | 944 | iter_data->nadhocs++; |
9a9c4fbc RM |
945 | if (vif->bss_conf.enable_beacon) |
946 | iter_data->beacons = true; | |
4801416c | 947 | break; |
9cb5412b | 948 | case NL80211_IFTYPE_MESH_POINT: |
4801416c | 949 | iter_data->nmeshes++; |
9a9c4fbc RM |
950 | if (vif->bss_conf.enable_beacon) |
951 | iter_data->beacons = true; | |
4801416c BG |
952 | break; |
953 | case NL80211_IFTYPE_WDS: | |
954 | iter_data->nwds++; | |
f078f209 LR |
955 | break; |
956 | default: | |
4801416c | 957 | break; |
f078f209 | 958 | } |
4801416c | 959 | } |
f078f209 | 960 | |
2ce73c02 SM |
961 | static void ath9k_update_bssid_mask(struct ath_softc *sc, |
962 | struct ath_chanctx *ctx, | |
963 | struct ath9k_vif_iter_data *iter_data) | |
964 | { | |
965 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
966 | struct ath_vif *avp; | |
967 | int i; | |
968 | ||
969 | if (!ath9k_is_chanctx_enabled()) | |
970 | return; | |
971 | ||
972 | list_for_each_entry(avp, &ctx->vifs, list) { | |
973 | if (ctx->nvifs_assigned != 1) | |
974 | continue; | |
975 | ||
b9a9693f | 976 | if (!iter_data->has_hw_macaddr) |
2ce73c02 SM |
977 | continue; |
978 | ||
979 | ether_addr_copy(common->curbssid, avp->bssid); | |
980 | ||
981 | /* perm_addr will be used as the p2p device address. */ | |
982 | for (i = 0; i < ETH_ALEN; i++) | |
983 | iter_data->mask[i] &= | |
984 | ~(iter_data->hw_macaddr[i] ^ | |
985 | sc->hw->wiphy->perm_addr[i]); | |
986 | } | |
987 | } | |
988 | ||
4801416c | 989 | /* Called with sc->mutex held. */ |
9a9c4fbc RM |
990 | void ath9k_calculate_iter_data(struct ath_softc *sc, |
991 | struct ath_chanctx *ctx, | |
4801416c BG |
992 | struct ath9k_vif_iter_data *iter_data) |
993 | { | |
9a9c4fbc | 994 | struct ath_vif *avp; |
8feceb67 | 995 | |
4801416c | 996 | /* |
daad1660 BG |
997 | * The hardware will use primary station addr together with the |
998 | * BSSID mask when matching addresses. | |
4801416c BG |
999 | */ |
1000 | memset(iter_data, 0, sizeof(*iter_data)); | |
93803b33 | 1001 | eth_broadcast_addr(iter_data->mask); |
9a9c4fbc RM |
1002 | iter_data->slottime = ATH9K_SLOT_TIME_9; |
1003 | ||
1004 | list_for_each_entry(avp, &ctx->vifs, list) | |
1005 | ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif); | |
2ce73c02 SM |
1006 | |
1007 | ath9k_update_bssid_mask(sc, ctx, iter_data); | |
9a9c4fbc RM |
1008 | } |
1009 | ||
1010 | static void ath9k_set_assoc_state(struct ath_softc *sc, | |
1011 | struct ieee80211_vif *vif, bool changed) | |
1012 | { | |
1013 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
cb35582a | 1014 | struct ath_vif *avp = (struct ath_vif *)vif->drv_priv; |
9a9c4fbc RM |
1015 | unsigned long flags; |
1016 | ||
1017 | set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); | |
9a9c4fbc | 1018 | |
cb35582a SM |
1019 | ether_addr_copy(common->curbssid, avp->bssid); |
1020 | common->curaid = avp->aid; | |
9a9c4fbc RM |
1021 | ath9k_hw_write_associd(sc->sc_ah); |
1022 | ||
1023 | if (changed) { | |
1024 | common->last_rssi = ATH_RSSI_DUMMY_MARKER; | |
1025 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; | |
5640b08e | 1026 | |
9a9c4fbc RM |
1027 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
1028 | sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON; | |
1029 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
1030 | } | |
4801416c | 1031 | |
9a9c4fbc RM |
1032 | if (ath9k_hw_mci_is_enabled(sc->sc_ah)) |
1033 | ath9k_mci_update_wlan_channels(sc, false); | |
ab11bb28 | 1034 | |
9a9c4fbc RM |
1035 | ath_dbg(common, CONFIG, |
1036 | "Primary Station interface: %pM, BSSID: %pM\n", | |
1037 | vif->addr, common->curbssid); | |
4801416c | 1038 | } |
8ca21f01 | 1039 | |
4ee26de1 SM |
1040 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
1041 | static void ath9k_set_offchannel_state(struct ath_softc *sc) | |
1042 | { | |
1043 | struct ath_hw *ah = sc->sc_ah; | |
1044 | struct ath_common *common = ath9k_hw_common(ah); | |
1045 | struct ieee80211_vif *vif = NULL; | |
1046 | ||
1047 | ath9k_ps_wakeup(sc); | |
1048 | ||
1049 | if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START) | |
1050 | vif = sc->offchannel.scan_vif; | |
1051 | else | |
1052 | vif = sc->offchannel.roc_vif; | |
1053 | ||
1054 | if (WARN_ON(!vif)) | |
1055 | goto exit; | |
1056 | ||
1057 | eth_zero_addr(common->curbssid); | |
1058 | eth_broadcast_addr(common->bssidmask); | |
62ae1aef | 1059 | memcpy(common->macaddr, vif->addr, ETH_ALEN); |
4ee26de1 SM |
1060 | common->curaid = 0; |
1061 | ah->opmode = vif->type; | |
1062 | ah->imask &= ~ATH9K_INT_SWBA; | |
1063 | ah->imask &= ~ATH9K_INT_TSFOOR; | |
1064 | ah->slottime = ATH9K_SLOT_TIME_9; | |
1065 | ||
1066 | ath_hw_setbssidmask(common); | |
1067 | ath9k_hw_setopmode(ah); | |
1068 | ath9k_hw_write_associd(sc->sc_ah); | |
1069 | ath9k_hw_set_interrupts(ah); | |
1070 | ath9k_hw_init_global_settings(ah); | |
1071 | ||
1072 | exit: | |
1073 | ath9k_ps_restore(sc); | |
1074 | } | |
1075 | #endif | |
1076 | ||
4801416c | 1077 | /* Called with sc->mutex held. */ |
9a9c4fbc RM |
1078 | void ath9k_calculate_summary_state(struct ath_softc *sc, |
1079 | struct ath_chanctx *ctx) | |
4801416c | 1080 | { |
4801416c BG |
1081 | struct ath_hw *ah = sc->sc_ah; |
1082 | struct ath_common *common = ath9k_hw_common(ah); | |
1083 | struct ath9k_vif_iter_data iter_data; | |
9bf30ff9 | 1084 | struct ath_beacon_config *cur_conf; |
8ca21f01 | 1085 | |
9a9c4fbc RM |
1086 | ath_chanctx_check_active(sc, ctx); |
1087 | ||
1088 | if (ctx != sc->cur_chan) | |
1089 | return; | |
1090 | ||
4ee26de1 SM |
1091 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
1092 | if (ctx == &sc->offchannel.chan) | |
1093 | return ath9k_set_offchannel_state(sc); | |
1094 | #endif | |
1095 | ||
9a9c4fbc RM |
1096 | ath9k_ps_wakeup(sc); |
1097 | ath9k_calculate_iter_data(sc, ctx, &iter_data); | |
1098 | ||
1099 | if (iter_data.has_hw_macaddr) | |
62ae1aef | 1100 | memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN); |
2c3db3d5 | 1101 | |
4801416c BG |
1102 | memcpy(common->bssidmask, iter_data.mask, ETH_ALEN); |
1103 | ath_hw_setbssidmask(common); | |
1104 | ||
4801416c | 1105 | if (iter_data.naps > 0) { |
9bf30ff9 | 1106 | cur_conf = &ctx->beacon; |
60ca9f87 | 1107 | ath9k_hw_set_tsfadjust(ah, true); |
4801416c | 1108 | ah->opmode = NL80211_IFTYPE_AP; |
9bf30ff9 SM |
1109 | if (cur_conf->enable_beacon) |
1110 | iter_data.beacons = true; | |
4801416c | 1111 | } else { |
60ca9f87 | 1112 | ath9k_hw_set_tsfadjust(ah, false); |
5640b08e | 1113 | |
fd5999cf JC |
1114 | if (iter_data.nmeshes) |
1115 | ah->opmode = NL80211_IFTYPE_MESH_POINT; | |
862a336c JK |
1116 | else if (iter_data.nocbs) |
1117 | ah->opmode = NL80211_IFTYPE_OCB; | |
fd5999cf | 1118 | else if (iter_data.nwds) |
4801416c BG |
1119 | ah->opmode = NL80211_IFTYPE_AP; |
1120 | else if (iter_data.nadhocs) | |
1121 | ah->opmode = NL80211_IFTYPE_ADHOC; | |
1122 | else | |
1123 | ah->opmode = NL80211_IFTYPE_STATION; | |
1124 | } | |
5640b08e | 1125 | |
df35d29e SM |
1126 | ath9k_hw_setopmode(ah); |
1127 | ||
748299f2 | 1128 | ctx->switch_after_beacon = false; |
198823fd | 1129 | if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0) |
3069168c | 1130 | ah->imask |= ATH9K_INT_TSFOOR; |
748299f2 | 1131 | else { |
4801416c | 1132 | ah->imask &= ~ATH9K_INT_TSFOOR; |
748299f2 FF |
1133 | if (iter_data.naps == 1 && iter_data.beacons) |
1134 | ctx->switch_after_beacon = true; | |
1135 | } | |
4af9cf4f | 1136 | |
9a9c4fbc RM |
1137 | ah->imask &= ~ATH9K_INT_SWBA; |
1138 | if (ah->opmode == NL80211_IFTYPE_STATION) { | |
1139 | bool changed = (iter_data.primary_sta != ctx->primary_sta); | |
1140 | ||
9a9c4fbc | 1141 | if (iter_data.primary_sta) { |
602607b6 | 1142 | iter_data.beacons = true; |
9a9c4fbc RM |
1143 | ath9k_set_assoc_state(sc, iter_data.primary_sta, |
1144 | changed); | |
1030f9fe | 1145 | ctx->primary_sta = iter_data.primary_sta; |
9a9c4fbc RM |
1146 | } else { |
1147 | ctx->primary_sta = NULL; | |
93803b33 | 1148 | eth_zero_addr(common->curbssid); |
9a9c4fbc RM |
1149 | common->curaid = 0; |
1150 | ath9k_hw_write_associd(sc->sc_ah); | |
1151 | if (ath9k_hw_mci_is_enabled(sc->sc_ah)) | |
1152 | ath9k_mci_update_wlan_channels(sc, true); | |
1153 | } | |
1154 | } else if (iter_data.beacons) { | |
1155 | ah->imask |= ATH9K_INT_SWBA; | |
1156 | } | |
72d874c6 | 1157 | ath9k_hw_set_interrupts(ah); |
6dcc3444 | 1158 | |
9a9c4fbc RM |
1159 | if (iter_data.beacons) |
1160 | set_bit(ATH_OP_BEACONS, &common->op_flags); | |
1161 | else | |
1162 | clear_bit(ATH_OP_BEACONS, &common->op_flags); | |
1163 | ||
1164 | if (ah->slottime != iter_data.slottime) { | |
1165 | ah->slottime = iter_data.slottime; | |
1166 | ath9k_hw_init_global_settings(ah); | |
6dcc3444 | 1167 | } |
9a9c4fbc RM |
1168 | |
1169 | if (iter_data.primary_sta) | |
1170 | set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); | |
1171 | else | |
1172 | clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags); | |
1173 | ||
2ce73c02 SM |
1174 | ath_dbg(common, CONFIG, |
1175 | "macaddr: %pM, bssid: %pM, bssidmask: %pM\n", | |
1176 | common->macaddr, common->curbssid, common->bssidmask); | |
1177 | ||
9a9c4fbc | 1178 | ath9k_ps_restore(sc); |
4801416c | 1179 | } |
6f255425 | 1180 | |
283dd119 LB |
1181 | static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
1182 | { | |
1183 | int *power = (int *)data; | |
1184 | ||
1185 | if (*power < vif->bss_conf.txpower) | |
1186 | *power = vif->bss_conf.txpower; | |
1187 | } | |
1188 | ||
1189 | /* Called with sc->mutex held. */ | |
1190 | void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif) | |
1191 | { | |
1192 | int power; | |
1193 | struct ath_hw *ah = sc->sc_ah; | |
1194 | struct ath_regulatory *reg = ath9k_hw_regulatory(ah); | |
1195 | ||
1196 | ath9k_ps_wakeup(sc); | |
1197 | if (ah->tpc_enabled) { | |
1198 | power = (vif) ? vif->bss_conf.txpower : -1; | |
1199 | ieee80211_iterate_active_interfaces_atomic( | |
1200 | sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL, | |
1201 | ath9k_tpc_vif_iter, &power); | |
1202 | if (power == -1) | |
1203 | power = sc->hw->conf.power_level; | |
1204 | } else { | |
1205 | power = sc->hw->conf.power_level; | |
1206 | } | |
1207 | sc->cur_chan->txpower = 2 * power; | |
1208 | ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false); | |
1209 | sc->cur_chan->cur_txpower = reg->max_power_level; | |
1210 | ath9k_ps_restore(sc); | |
1211 | } | |
1212 | ||
a4027644 SM |
1213 | static void ath9k_assign_hw_queues(struct ieee80211_hw *hw, |
1214 | struct ieee80211_vif *vif) | |
1215 | { | |
1216 | int i; | |
1217 | ||
868caae3 SM |
1218 | if (!ath9k_is_chanctx_enabled()) |
1219 | return; | |
1220 | ||
a4027644 SM |
1221 | for (i = 0; i < IEEE80211_NUM_ACS; i++) |
1222 | vif->hw_queue[i] = i; | |
1223 | ||
4b870c26 CYY |
1224 | if (vif->type == NL80211_IFTYPE_AP || |
1225 | vif->type == NL80211_IFTYPE_MESH_POINT) | |
a4027644 SM |
1226 | vif->cab_queue = hw->queues - 2; |
1227 | else | |
1228 | vif->cab_queue = IEEE80211_INVAL_HW_QUEUE; | |
1229 | } | |
1230 | ||
4801416c BG |
1231 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
1232 | struct ieee80211_vif *vif) | |
6b3b991d | 1233 | { |
9ac58615 | 1234 | struct ath_softc *sc = hw->priv; |
4801416c BG |
1235 | struct ath_hw *ah = sc->sc_ah; |
1236 | struct ath_common *common = ath9k_hw_common(ah); | |
f89d1bc4 FF |
1237 | struct ath_vif *avp = (void *)vif->drv_priv; |
1238 | struct ath_node *an = &avp->mcast_node; | |
6b3b991d | 1239 | |
4801416c | 1240 | mutex_lock(&sc->mutex); |
6b3b991d | 1241 | |
89f927af | 1242 | if (config_enabled(CONFIG_ATH9K_TX99)) { |
ca529c93 | 1243 | if (sc->cur_chan->nvifs >= 1) { |
89f927af LR |
1244 | mutex_unlock(&sc->mutex); |
1245 | return -EOPNOTSUPP; | |
1246 | } | |
1247 | sc->tx99_vif = vif; | |
1248 | } | |
1249 | ||
d2182b69 | 1250 | ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type); |
ca529c93 | 1251 | sc->cur_chan->nvifs++; |
4801416c | 1252 | |
b9a9693f KV |
1253 | if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled()) |
1254 | vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE; | |
1255 | ||
130ef6e9 SM |
1256 | if (ath9k_uses_beacons(vif->type)) |
1257 | ath9k_beacon_assign_slot(sc, vif); | |
1258 | ||
d463af4a | 1259 | avp->vif = vif; |
499afacc | 1260 | if (!ath9k_is_chanctx_enabled()) { |
39305635 | 1261 | avp->chanctx = sc->cur_chan; |
9a9c4fbc RM |
1262 | list_add_tail(&avp->list, &avp->chanctx->vifs); |
1263 | } | |
a4027644 | 1264 | |
daad1660 BG |
1265 | ath9k_calculate_summary_state(sc, avp->chanctx); |
1266 | ||
a4027644 | 1267 | ath9k_assign_hw_queues(hw, vif); |
0453531e | 1268 | |
283dd119 LB |
1269 | ath9k_set_txpower(sc, vif); |
1270 | ||
f89d1bc4 FF |
1271 | an->sc = sc; |
1272 | an->sta = NULL; | |
1273 | an->vif = vif; | |
1274 | an->no_ps_filter = true; | |
1275 | ath_tx_node_init(sc, an); | |
1276 | ||
4801416c | 1277 | mutex_unlock(&sc->mutex); |
327967cb | 1278 | return 0; |
6b3b991d RM |
1279 | } |
1280 | ||
1281 | static int ath9k_change_interface(struct ieee80211_hw *hw, | |
1282 | struct ieee80211_vif *vif, | |
1283 | enum nl80211_iftype new_type, | |
1284 | bool p2p) | |
1285 | { | |
9ac58615 | 1286 | struct ath_softc *sc = hw->priv; |
6b3b991d | 1287 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
c083ce99 | 1288 | struct ath_vif *avp = (void *)vif->drv_priv; |
6b3b991d | 1289 | |
6b3b991d | 1290 | mutex_lock(&sc->mutex); |
4801416c | 1291 | |
89f927af LR |
1292 | if (config_enabled(CONFIG_ATH9K_TX99)) { |
1293 | mutex_unlock(&sc->mutex); | |
1294 | return -EOPNOTSUPP; | |
1295 | } | |
1296 | ||
1297 | ath_dbg(common, CONFIG, "Change Interface\n"); | |
1298 | ||
4801416c | 1299 | if (ath9k_uses_beacons(vif->type)) |
130ef6e9 | 1300 | ath9k_beacon_remove_slot(sc, vif); |
4801416c | 1301 | |
6b3b991d RM |
1302 | vif->type = new_type; |
1303 | vif->p2p = p2p; | |
1304 | ||
130ef6e9 SM |
1305 | if (ath9k_uses_beacons(vif->type)) |
1306 | ath9k_beacon_assign_slot(sc, vif); | |
9a9c4fbc | 1307 | |
a4027644 | 1308 | ath9k_assign_hw_queues(hw, vif); |
9a9c4fbc | 1309 | ath9k_calculate_summary_state(sc, avp->chanctx); |
130ef6e9 | 1310 | |
283dd119 LB |
1311 | ath9k_set_txpower(sc, vif); |
1312 | ||
6b3b991d | 1313 | mutex_unlock(&sc->mutex); |
327967cb | 1314 | return 0; |
6b3b991d RM |
1315 | } |
1316 | ||
8feceb67 | 1317 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1318 | struct ieee80211_vif *vif) |
f078f209 | 1319 | { |
9ac58615 | 1320 | struct ath_softc *sc = hw->priv; |
c46917bb | 1321 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
f89d1bc4 | 1322 | struct ath_vif *avp = (void *)vif->drv_priv; |
f078f209 | 1323 | |
d2182b69 | 1324 | ath_dbg(common, CONFIG, "Detach Interface\n"); |
f078f209 | 1325 | |
141b38b6 S |
1326 | mutex_lock(&sc->mutex); |
1327 | ||
c7dd40c9 | 1328 | ath9k_p2p_remove_vif(sc, vif); |
d463af4a | 1329 | |
ca529c93 | 1330 | sc->cur_chan->nvifs--; |
89f927af | 1331 | sc->tx99_vif = NULL; |
499afacc | 1332 | if (!ath9k_is_chanctx_enabled()) |
9a9c4fbc | 1333 | list_del(&avp->list); |
580f0b8a | 1334 | |
4801416c | 1335 | if (ath9k_uses_beacons(vif->type)) |
130ef6e9 | 1336 | ath9k_beacon_remove_slot(sc, vif); |
2c3db3d5 | 1337 | |
f89d1bc4 FF |
1338 | ath_tx_node_cleanup(sc, &avp->mcast_node); |
1339 | ||
daad1660 BG |
1340 | ath9k_calculate_summary_state(sc, avp->chanctx); |
1341 | ||
283dd119 LB |
1342 | ath9k_set_txpower(sc, NULL); |
1343 | ||
141b38b6 | 1344 | mutex_unlock(&sc->mutex); |
f078f209 LR |
1345 | } |
1346 | ||
fbab7390 | 1347 | static void ath9k_enable_ps(struct ath_softc *sc) |
3f7c5c10 | 1348 | { |
3069168c | 1349 | struct ath_hw *ah = sc->sc_ah; |
ad128860 | 1350 | struct ath_common *common = ath9k_hw_common(ah); |
3069168c | 1351 | |
89f927af LR |
1352 | if (config_enabled(CONFIG_ATH9K_TX99)) |
1353 | return; | |
1354 | ||
3f7c5c10 | 1355 | sc->ps_enabled = true; |
3069168c PR |
1356 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1357 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1358 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
72d874c6 | 1359 | ath9k_hw_set_interrupts(ah); |
3f7c5c10 | 1360 | } |
fdf76622 | 1361 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1362 | } |
ad128860 | 1363 | ath_dbg(common, PS, "PowerSave enabled\n"); |
3f7c5c10 SB |
1364 | } |
1365 | ||
845d708e SB |
1366 | static void ath9k_disable_ps(struct ath_softc *sc) |
1367 | { | |
1368 | struct ath_hw *ah = sc->sc_ah; | |
ad128860 | 1369 | struct ath_common *common = ath9k_hw_common(ah); |
845d708e | 1370 | |
89f927af LR |
1371 | if (config_enabled(CONFIG_ATH9K_TX99)) |
1372 | return; | |
1373 | ||
845d708e SB |
1374 | sc->ps_enabled = false; |
1375 | ath9k_hw_setpower(ah, ATH9K_PM_AWAKE); | |
1376 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { | |
1377 | ath9k_hw_setrxabort(ah, 0); | |
1378 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | | |
1379 | PS_WAIT_FOR_CAB | | |
1380 | PS_WAIT_FOR_PSPOLL_DATA | | |
1381 | PS_WAIT_FOR_TX_ACK); | |
1382 | if (ah->imask & ATH9K_INT_TIM_TIMER) { | |
1383 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
72d874c6 | 1384 | ath9k_hw_set_interrupts(ah); |
845d708e SB |
1385 | } |
1386 | } | |
ad128860 | 1387 | ath_dbg(common, PS, "PowerSave disabled\n"); |
845d708e SB |
1388 | } |
1389 | ||
e8975581 | 1390 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1391 | { |
9ac58615 | 1392 | struct ath_softc *sc = hw->priv; |
3430098a FF |
1393 | struct ath_hw *ah = sc->sc_ah; |
1394 | struct ath_common *common = ath9k_hw_common(ah); | |
e8975581 | 1395 | struct ieee80211_conf *conf = &hw->conf; |
fbbcd146 | 1396 | struct ath_chanctx *ctx = sc->cur_chan; |
f078f209 | 1397 | |
c0c11741 | 1398 | ath9k_ps_wakeup(sc); |
aa33de09 | 1399 | mutex_lock(&sc->mutex); |
141b38b6 | 1400 | |
daa1b6ee | 1401 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
7545daf4 | 1402 | sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE); |
b73f3e78 | 1403 | if (sc->ps_idle) { |
daa1b6ee | 1404 | ath_cancel_work(sc); |
b73f3e78 RM |
1405 | ath9k_stop_btcoex(sc); |
1406 | } else { | |
1407 | ath9k_start_btcoex(sc); | |
75600abf FF |
1408 | /* |
1409 | * The chip needs a reset to properly wake up from | |
1410 | * full sleep | |
1411 | */ | |
39305635 | 1412 | ath_chanctx_set_channel(sc, ctx, &ctx->chandef); |
b73f3e78 | 1413 | } |
daa1b6ee | 1414 | } |
64839170 | 1415 | |
e7824a50 LR |
1416 | /* |
1417 | * We just prepare to enable PS. We have to wait until our AP has | |
1418 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1419 | * those ACKs and end up retransmitting the same null data frames. | |
1420 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1421 | */ | |
3cbb5dd7 | 1422 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
8ab2cd09 LR |
1423 | unsigned long flags; |
1424 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
fbab7390 SB |
1425 | if (conf->flags & IEEE80211_CONF_PS) |
1426 | ath9k_enable_ps(sc); | |
845d708e SB |
1427 | else |
1428 | ath9k_disable_ps(sc); | |
8ab2cd09 | 1429 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
3cbb5dd7 VN |
1430 | } |
1431 | ||
199afd9d S |
1432 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1433 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
d2182b69 | 1434 | ath_dbg(common, CONFIG, "Monitor mode is enabled\n"); |
5f841b41 RM |
1435 | sc->sc_ah->is_monitoring = true; |
1436 | } else { | |
d2182b69 | 1437 | ath_dbg(common, CONFIG, "Monitor mode is disabled\n"); |
5f841b41 | 1438 | sc->sc_ah->is_monitoring = false; |
199afd9d S |
1439 | } |
1440 | } | |
1441 | ||
499afacc | 1442 | if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) { |
fbbcd146 | 1443 | ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL); |
bff11766 | 1444 | ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef); |
094d05dc | 1445 | } |
f078f209 | 1446 | |
aa33de09 | 1447 | mutex_unlock(&sc->mutex); |
c0c11741 | 1448 | ath9k_ps_restore(sc); |
141b38b6 | 1449 | |
f078f209 LR |
1450 | return 0; |
1451 | } | |
1452 | ||
8feceb67 | 1453 | #define SUPPORTED_FILTERS \ |
df140465 | 1454 | (FIF_ALLMULTI | \ |
8feceb67 | 1455 | FIF_CONTROL | \ |
af6a3fc7 | 1456 | FIF_PSPOLL | \ |
8feceb67 VT |
1457 | FIF_OTHER_BSS | \ |
1458 | FIF_BCN_PRBRESP_PROMISC | \ | |
9c1d8e4a | 1459 | FIF_PROBE_REQ | \ |
8feceb67 | 1460 | FIF_FCSFAIL) |
c83be688 | 1461 | |
8feceb67 VT |
1462 | /* FIXME: sc->sc_full_reset ? */ |
1463 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1464 | unsigned int changed_flags, | |
1465 | unsigned int *total_flags, | |
3ac64bee | 1466 | u64 multicast) |
8feceb67 | 1467 | { |
9ac58615 | 1468 | struct ath_softc *sc = hw->priv; |
f3771c08 | 1469 | struct ath_chanctx *ctx; |
8feceb67 | 1470 | u32 rfilt; |
f078f209 | 1471 | |
8feceb67 VT |
1472 | changed_flags &= SUPPORTED_FILTERS; |
1473 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1474 | |
fce34430 | 1475 | spin_lock_bh(&sc->chan_lock); |
f3771c08 JD |
1476 | ath_for_each_chanctx(sc, ctx) |
1477 | ctx->rxfilter = *total_flags; | |
1738203e JD |
1478 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
1479 | sc->offchannel.chan.rxfilter = *total_flags; | |
1480 | #endif | |
fce34430 SM |
1481 | spin_unlock_bh(&sc->chan_lock); |
1482 | ||
aa68aeaa | 1483 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1484 | rfilt = ath_calcrxfilter(sc); |
1485 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1486 | ath9k_ps_restore(sc); |
f078f209 | 1487 | |
d2182b69 JP |
1488 | ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n", |
1489 | rfilt); | |
8feceb67 | 1490 | } |
f078f209 | 1491 | |
4ca77860 JB |
1492 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1493 | struct ieee80211_vif *vif, | |
1494 | struct ieee80211_sta *sta) | |
8feceb67 | 1495 | { |
9ac58615 | 1496 | struct ath_softc *sc = hw->priv; |
93ae2dd2 FF |
1497 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1498 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1499 | struct ieee80211_key_conf ps_key = { }; | |
4ef69d03 | 1500 | int key; |
f078f209 | 1501 | |
7e1e3864 | 1502 | ath_node_attach(sc, sta, vif); |
f59a59fe FF |
1503 | |
1504 | if (vif->type != NL80211_IFTYPE_AP && | |
1505 | vif->type != NL80211_IFTYPE_AP_VLAN) | |
1506 | return 0; | |
1507 | ||
4ef69d03 | 1508 | key = ath_key_config(common, vif, sta, &ps_key); |
4bbf4414 | 1509 | if (key > 0) { |
4ef69d03 | 1510 | an->ps_key = key; |
4bbf4414 RM |
1511 | an->key_idx[0] = key; |
1512 | } | |
4ca77860 JB |
1513 | |
1514 | return 0; | |
1515 | } | |
1516 | ||
93ae2dd2 FF |
1517 | static void ath9k_del_ps_key(struct ath_softc *sc, |
1518 | struct ieee80211_vif *vif, | |
1519 | struct ieee80211_sta *sta) | |
1520 | { | |
1521 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1522 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1523 | struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key }; | |
1524 | ||
1525 | if (!an->ps_key) | |
1526 | return; | |
1527 | ||
1528 | ath_key_delete(common, &ps_key); | |
4ef69d03 | 1529 | an->ps_key = 0; |
4bbf4414 | 1530 | an->key_idx[0] = 0; |
93ae2dd2 FF |
1531 | } |
1532 | ||
4ca77860 JB |
1533 | static int ath9k_sta_remove(struct ieee80211_hw *hw, |
1534 | struct ieee80211_vif *vif, | |
1535 | struct ieee80211_sta *sta) | |
1536 | { | |
9ac58615 | 1537 | struct ath_softc *sc = hw->priv; |
4ca77860 | 1538 | |
93ae2dd2 | 1539 | ath9k_del_ps_key(sc, vif, sta); |
4ca77860 JB |
1540 | ath_node_detach(sc, sta); |
1541 | ||
1542 | return 0; | |
f078f209 LR |
1543 | } |
1544 | ||
df3c6eb3 SM |
1545 | static int ath9k_sta_state(struct ieee80211_hw *hw, |
1546 | struct ieee80211_vif *vif, | |
1547 | struct ieee80211_sta *sta, | |
1548 | enum ieee80211_sta_state old_state, | |
1549 | enum ieee80211_sta_state new_state) | |
1550 | { | |
1551 | struct ath_softc *sc = hw->priv; | |
1552 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
1553 | int ret = 0; | |
1554 | ||
1555 | if (old_state == IEEE80211_STA_AUTH && | |
1556 | new_state == IEEE80211_STA_ASSOC) { | |
1557 | ret = ath9k_sta_add(hw, vif, sta); | |
1558 | ath_dbg(common, CONFIG, | |
1559 | "Add station: %pM\n", sta->addr); | |
1560 | } else if (old_state == IEEE80211_STA_ASSOC && | |
1561 | new_state == IEEE80211_STA_AUTH) { | |
1562 | ret = ath9k_sta_remove(hw, vif, sta); | |
1563 | ath_dbg(common, CONFIG, | |
1564 | "Remove station: %pM\n", sta->addr); | |
1565 | } | |
1566 | ||
b8f9279b | 1567 | if (ath9k_is_chanctx_enabled()) { |
91e6ceb3 SM |
1568 | if (vif->type == NL80211_IFTYPE_STATION) { |
1569 | if (old_state == IEEE80211_STA_ASSOC && | |
1570 | new_state == IEEE80211_STA_AUTHORIZED) | |
1571 | ath_chanctx_event(sc, vif, | |
1572 | ATH_CHANCTX_EVENT_AUTHORIZED); | |
1573 | } | |
b8f9279b SM |
1574 | } |
1575 | ||
df3c6eb3 SM |
1576 | return ret; |
1577 | } | |
1578 | ||
4bbf4414 RM |
1579 | static void ath9k_sta_set_tx_filter(struct ath_hw *ah, |
1580 | struct ath_node *an, | |
1581 | bool set) | |
1582 | { | |
1583 | int i; | |
1584 | ||
1585 | for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { | |
1586 | if (!an->key_idx[i]) | |
1587 | continue; | |
1588 | ath9k_hw_set_tx_filter(ah, an->key_idx[i], set); | |
1589 | } | |
1590 | } | |
1591 | ||
5519541d FF |
1592 | static void ath9k_sta_notify(struct ieee80211_hw *hw, |
1593 | struct ieee80211_vif *vif, | |
1594 | enum sta_notify_cmd cmd, | |
1595 | struct ieee80211_sta *sta) | |
1596 | { | |
1597 | struct ath_softc *sc = hw->priv; | |
1598 | struct ath_node *an = (struct ath_node *) sta->drv_priv; | |
1599 | ||
1600 | switch (cmd) { | |
1601 | case STA_NOTIFY_SLEEP: | |
1602 | an->sleeping = true; | |
042ec453 | 1603 | ath_tx_aggr_sleep(sta, sc, an); |
4bbf4414 | 1604 | ath9k_sta_set_tx_filter(sc->sc_ah, an, true); |
5519541d FF |
1605 | break; |
1606 | case STA_NOTIFY_AWAKE: | |
4bbf4414 | 1607 | ath9k_sta_set_tx_filter(sc->sc_ah, an, false); |
5519541d FF |
1608 | an->sleeping = false; |
1609 | ath_tx_aggr_wakeup(sc, an); | |
1610 | break; | |
1611 | } | |
1612 | } | |
1613 | ||
8a3a3c85 EP |
1614 | static int ath9k_conf_tx(struct ieee80211_hw *hw, |
1615 | struct ieee80211_vif *vif, u16 queue, | |
8feceb67 | 1616 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1617 | { |
9ac58615 | 1618 | struct ath_softc *sc = hw->priv; |
c46917bb | 1619 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
066dae93 | 1620 | struct ath_txq *txq; |
8feceb67 | 1621 | struct ath9k_tx_queue_info qi; |
066dae93 | 1622 | int ret = 0; |
f078f209 | 1623 | |
bea843c7 | 1624 | if (queue >= IEEE80211_NUM_ACS) |
8feceb67 | 1625 | return 0; |
f078f209 | 1626 | |
066dae93 FF |
1627 | txq = sc->tx.txq_map[queue]; |
1628 | ||
96f372c9 | 1629 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1630 | mutex_lock(&sc->mutex); |
1631 | ||
1ffb0610 S |
1632 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1633 | ||
8feceb67 VT |
1634 | qi.tqi_aifs = params->aifs; |
1635 | qi.tqi_cwmin = params->cw_min; | |
1636 | qi.tqi_cwmax = params->cw_max; | |
531bd079 | 1637 | qi.tqi_burstTime = params->txop * 32; |
f078f209 | 1638 | |
d2182b69 | 1639 | ath_dbg(common, CONFIG, |
226afe68 JP |
1640 | "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", |
1641 | queue, txq->axq_qnum, params->aifs, params->cw_min, | |
1642 | params->cw_max, params->txop); | |
f078f209 | 1643 | |
aa5955c3 | 1644 | ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime); |
066dae93 | 1645 | ret = ath_txq_update(sc, txq->axq_qnum, &qi); |
8feceb67 | 1646 | if (ret) |
3800276a | 1647 | ath_err(common, "TXQ Update failed\n"); |
f078f209 | 1648 | |
141b38b6 | 1649 | mutex_unlock(&sc->mutex); |
96f372c9 | 1650 | ath9k_ps_restore(sc); |
141b38b6 | 1651 | |
8feceb67 VT |
1652 | return ret; |
1653 | } | |
f078f209 | 1654 | |
8feceb67 VT |
1655 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1656 | enum set_key_cmd cmd, | |
dc822b5d JB |
1657 | struct ieee80211_vif *vif, |
1658 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1659 | struct ieee80211_key_conf *key) |
1660 | { | |
9ac58615 | 1661 | struct ath_softc *sc = hw->priv; |
c46917bb | 1662 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4bbf4414 RM |
1663 | struct ath_node *an = NULL; |
1664 | int ret = 0, i; | |
f078f209 | 1665 | |
3e6109c5 | 1666 | if (ath9k_modparam_nohwcrypt) |
b3bd89ce JM |
1667 | return -ENOSPC; |
1668 | ||
5bd5e9a6 CYY |
1669 | if ((vif->type == NL80211_IFTYPE_ADHOC || |
1670 | vif->type == NL80211_IFTYPE_MESH_POINT) && | |
cfdc9a8b JM |
1671 | (key->cipher == WLAN_CIPHER_SUITE_TKIP || |
1672 | key->cipher == WLAN_CIPHER_SUITE_CCMP) && | |
1673 | !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { | |
1674 | /* | |
1675 | * For now, disable hw crypto for the RSN IBSS group keys. This | |
1676 | * could be optimized in the future to use a modified key cache | |
1677 | * design to support per-STA RX GTK, but until that gets | |
1678 | * implemented, use of software crypto for group addressed | |
1679 | * frames is a acceptable to allow RSN IBSS to be used. | |
1680 | */ | |
1681 | return -EOPNOTSUPP; | |
1682 | } | |
1683 | ||
141b38b6 | 1684 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1685 | ath9k_ps_wakeup(sc); |
4bbf4414 RM |
1686 | ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd); |
1687 | if (sta) | |
1688 | an = (struct ath_node *)sta->drv_priv; | |
f078f209 | 1689 | |
8feceb67 VT |
1690 | switch (cmd) { |
1691 | case SET_KEY: | |
93ae2dd2 FF |
1692 | if (sta) |
1693 | ath9k_del_ps_key(sc, vif, sta); | |
1694 | ||
4bbf4414 | 1695 | key->hw_key_idx = 0; |
040e539e | 1696 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1697 | if (ret >= 0) { |
1698 | key->hw_key_idx = ret; | |
8feceb67 VT |
1699 | /* push IV and Michael MIC generation to stack */ |
1700 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
97359d12 | 1701 | if (key->cipher == WLAN_CIPHER_SUITE_TKIP) |
8feceb67 | 1702 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
e6510b11 | 1703 | if (sc->sc_ah->sw_mgmt_crypto_tx && |
97359d12 | 1704 | key->cipher == WLAN_CIPHER_SUITE_CCMP) |
e548c49e | 1705 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; |
6ace2891 | 1706 | ret = 0; |
8feceb67 | 1707 | } |
4bbf4414 RM |
1708 | if (an && key->hw_key_idx) { |
1709 | for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { | |
1710 | if (an->key_idx[i]) | |
1711 | continue; | |
1712 | an->key_idx[i] = key->hw_key_idx; | |
1713 | break; | |
1714 | } | |
1715 | WARN_ON(i == ARRAY_SIZE(an->key_idx)); | |
1716 | } | |
8feceb67 VT |
1717 | break; |
1718 | case DISABLE_KEY: | |
040e539e | 1719 | ath_key_delete(common, key); |
4bbf4414 RM |
1720 | if (an) { |
1721 | for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) { | |
1722 | if (an->key_idx[i] != key->hw_key_idx) | |
1723 | continue; | |
1724 | an->key_idx[i] = 0; | |
1725 | break; | |
1726 | } | |
1727 | } | |
1728 | key->hw_key_idx = 0; | |
8feceb67 VT |
1729 | break; |
1730 | default: | |
1731 | ret = -EINVAL; | |
1732 | } | |
f078f209 | 1733 | |
3cbb5dd7 | 1734 | ath9k_ps_restore(sc); |
141b38b6 S |
1735 | mutex_unlock(&sc->mutex); |
1736 | ||
8feceb67 VT |
1737 | return ret; |
1738 | } | |
6c43c090 | 1739 | |
8feceb67 VT |
1740 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1741 | struct ieee80211_vif *vif, | |
1742 | struct ieee80211_bss_conf *bss_conf, | |
1743 | u32 changed) | |
1744 | { | |
da0d45f7 SM |
1745 | #define CHECK_ANI \ |
1746 | (BSS_CHANGED_ASSOC | \ | |
1747 | BSS_CHANGED_IBSS | \ | |
1748 | BSS_CHANGED_BEACON_ENABLED) | |
1749 | ||
9ac58615 | 1750 | struct ath_softc *sc = hw->priv; |
2d0ddec5 | 1751 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1752 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1753 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1754 | int slottime; |
f078f209 | 1755 | |
96f372c9 | 1756 | ath9k_ps_wakeup(sc); |
141b38b6 S |
1757 | mutex_lock(&sc->mutex); |
1758 | ||
9f61903c | 1759 | if (changed & BSS_CHANGED_ASSOC) { |
6c43c090 SM |
1760 | ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n", |
1761 | bss_conf->bssid, bss_conf->assoc); | |
1762 | ||
62ae1aef | 1763 | memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); |
cb35582a SM |
1764 | avp->aid = bss_conf->aid; |
1765 | avp->assoc = bss_conf->assoc; | |
1766 | ||
9a9c4fbc | 1767 | ath9k_calculate_summary_state(sc, avp->chanctx); |
c6089ccc | 1768 | } |
2d0ddec5 | 1769 | |
862a336c JK |
1770 | if ((changed & BSS_CHANGED_IBSS) || |
1771 | (changed & BSS_CHANGED_OCB)) { | |
2e5ef459 RM |
1772 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); |
1773 | common->curaid = bss_conf->aid; | |
1774 | ath9k_hw_write_associd(sc->sc_ah); | |
2e5ef459 RM |
1775 | } |
1776 | ||
ef4ad633 | 1777 | if ((changed & BSS_CHANGED_BEACON_ENABLED) || |
9198cf4a RM |
1778 | (changed & BSS_CHANGED_BEACON_INT) || |
1779 | (changed & BSS_CHANGED_BEACON_INFO)) { | |
9bf30ff9 | 1780 | ath9k_beacon_config(sc, vif, changed); |
9a9c4fbc RM |
1781 | if (changed & BSS_CHANGED_BEACON_ENABLED) |
1782 | ath9k_calculate_summary_state(sc, avp->chanctx); | |
9a9c4fbc | 1783 | } |
0005baf4 | 1784 | |
9a9c4fbc RM |
1785 | if ((avp->chanctx == sc->cur_chan) && |
1786 | (changed & BSS_CHANGED_ERP_SLOT)) { | |
0005baf4 FF |
1787 | if (bss_conf->use_short_slot) |
1788 | slottime = 9; | |
1789 | else | |
1790 | slottime = 20; | |
1791 | if (vif->type == NL80211_IFTYPE_AP) { | |
1792 | /* | |
1793 | * Defer update, so that connected stations can adjust | |
1794 | * their settings at the same time. | |
1795 | * See beacon.c for more details | |
1796 | */ | |
1797 | sc->beacon.slottime = slottime; | |
1798 | sc->beacon.updateslot = UPDATE; | |
1799 | } else { | |
1800 | ah->slottime = slottime; | |
1801 | ath9k_hw_init_global_settings(ah); | |
1802 | } | |
2d0ddec5 JB |
1803 | } |
1804 | ||
c7dd40c9 SM |
1805 | if (changed & BSS_CHANGED_P2P_PS) |
1806 | ath9k_p2p_bss_info_changed(sc, vif); | |
d463af4a | 1807 | |
da0d45f7 SM |
1808 | if (changed & CHECK_ANI) |
1809 | ath_check_ani(sc); | |
1810 | ||
283dd119 LB |
1811 | if (changed & BSS_CHANGED_TXPOWER) { |
1812 | ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n", | |
1813 | vif->addr, bss_conf->txpower, bss_conf->txpower_type); | |
1814 | ath9k_set_txpower(sc, vif); | |
1815 | } | |
1816 | ||
141b38b6 | 1817 | mutex_unlock(&sc->mutex); |
96f372c9 | 1818 | ath9k_ps_restore(sc); |
da0d45f7 SM |
1819 | |
1820 | #undef CHECK_ANI | |
8feceb67 | 1821 | } |
f078f209 | 1822 | |
37a41b4a | 1823 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 1824 | { |
9ac58615 | 1825 | struct ath_softc *sc = hw->priv; |
8feceb67 | 1826 | u64 tsf; |
f078f209 | 1827 | |
141b38b6 | 1828 | mutex_lock(&sc->mutex); |
9abbfb27 | 1829 | ath9k_ps_wakeup(sc); |
141b38b6 | 1830 | tsf = ath9k_hw_gettsf64(sc->sc_ah); |
9abbfb27 | 1831 | ath9k_ps_restore(sc); |
141b38b6 | 1832 | mutex_unlock(&sc->mutex); |
f078f209 | 1833 | |
8feceb67 VT |
1834 | return tsf; |
1835 | } | |
f078f209 | 1836 | |
37a41b4a EP |
1837 | static void ath9k_set_tsf(struct ieee80211_hw *hw, |
1838 | struct ieee80211_vif *vif, | |
1839 | u64 tsf) | |
3b5d665b | 1840 | { |
9ac58615 | 1841 | struct ath_softc *sc = hw->priv; |
3b5d665b | 1842 | |
141b38b6 | 1843 | mutex_lock(&sc->mutex); |
9abbfb27 | 1844 | ath9k_ps_wakeup(sc); |
141b38b6 | 1845 | ath9k_hw_settsf64(sc->sc_ah, tsf); |
9abbfb27 | 1846 | ath9k_ps_restore(sc); |
141b38b6 | 1847 | mutex_unlock(&sc->mutex); |
3b5d665b AF |
1848 | } |
1849 | ||
37a41b4a | 1850 | static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
8feceb67 | 1851 | { |
9ac58615 | 1852 | struct ath_softc *sc = hw->priv; |
c83be688 | 1853 | |
141b38b6 | 1854 | mutex_lock(&sc->mutex); |
21526d57 LR |
1855 | |
1856 | ath9k_ps_wakeup(sc); | |
141b38b6 | 1857 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
1858 | ath9k_ps_restore(sc); |
1859 | ||
141b38b6 | 1860 | mutex_unlock(&sc->mutex); |
8feceb67 | 1861 | } |
f078f209 | 1862 | |
8feceb67 | 1863 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 1864 | struct ieee80211_vif *vif, |
50ea05ef | 1865 | struct ieee80211_ampdu_params *params) |
8feceb67 | 1866 | { |
9ac58615 | 1867 | struct ath_softc *sc = hw->priv; |
1e929d3e | 1868 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
16e23428 | 1869 | bool flush = false; |
8feceb67 | 1870 | int ret = 0; |
50ea05ef SS |
1871 | struct ieee80211_sta *sta = params->sta; |
1872 | enum ieee80211_ampdu_mlme_action action = params->action; | |
1873 | u16 tid = params->tid; | |
1874 | u16 *ssn = ¶ms->ssn; | |
f078f209 | 1875 | |
7ca7c776 | 1876 | mutex_lock(&sc->mutex); |
85ad181e | 1877 | |
8feceb67 VT |
1878 | switch (action) { |
1879 | case IEEE80211_AMPDU_RX_START: | |
8feceb67 VT |
1880 | break; |
1881 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
1882 | break; |
1883 | case IEEE80211_AMPDU_TX_START: | |
1e929d3e SM |
1884 | if (ath9k_is_chanctx_enabled()) { |
1885 | if (test_bit(ATH_OP_SCANNING, &common->op_flags)) { | |
1886 | ret = -EBUSY; | |
1887 | break; | |
1888 | } | |
1889 | } | |
8b685ba9 | 1890 | ath9k_ps_wakeup(sc); |
231c3a1f FF |
1891 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
1892 | if (!ret) | |
1893 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
8b685ba9 | 1894 | ath9k_ps_restore(sc); |
8feceb67 | 1895 | break; |
18b559d5 JB |
1896 | case IEEE80211_AMPDU_TX_STOP_FLUSH: |
1897 | case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: | |
16e23428 FF |
1898 | flush = true; |
1899 | case IEEE80211_AMPDU_TX_STOP_CONT: | |
8b685ba9 | 1900 | ath9k_ps_wakeup(sc); |
f83da965 | 1901 | ath_tx_aggr_stop(sc, sta, tid); |
08c96abd | 1902 | if (!flush) |
16e23428 | 1903 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1904 | ath9k_ps_restore(sc); |
8feceb67 | 1905 | break; |
b1720231 | 1906 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 1907 | ath9k_ps_wakeup(sc); |
8469cdef | 1908 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 1909 | ath9k_ps_restore(sc); |
8469cdef | 1910 | break; |
8feceb67 | 1911 | default: |
3800276a | 1912 | ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n"); |
8feceb67 VT |
1913 | } |
1914 | ||
7ca7c776 | 1915 | mutex_unlock(&sc->mutex); |
85ad181e | 1916 | |
8feceb67 | 1917 | return ret; |
f078f209 LR |
1918 | } |
1919 | ||
62dad5b0 BP |
1920 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
1921 | struct survey_info *survey) | |
1922 | { | |
9ac58615 | 1923 | struct ath_softc *sc = hw->priv; |
3430098a | 1924 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39162dbe | 1925 | struct ieee80211_supported_band *sband; |
3430098a | 1926 | struct ieee80211_channel *chan; |
3430098a FF |
1927 | int pos; |
1928 | ||
89f927af LR |
1929 | if (config_enabled(CONFIG_ATH9K_TX99)) |
1930 | return -EOPNOTSUPP; | |
1931 | ||
b7cc9b97 | 1932 | spin_lock_bh(&common->cc_lock); |
3430098a FF |
1933 | if (idx == 0) |
1934 | ath_update_survey_stats(sc); | |
39162dbe | 1935 | |
57fbcce3 | 1936 | sband = hw->wiphy->bands[NL80211_BAND_2GHZ]; |
39162dbe FF |
1937 | if (sband && idx >= sband->n_channels) { |
1938 | idx -= sband->n_channels; | |
1939 | sband = NULL; | |
1940 | } | |
62dad5b0 | 1941 | |
39162dbe | 1942 | if (!sband) |
57fbcce3 | 1943 | sband = hw->wiphy->bands[NL80211_BAND_5GHZ]; |
62dad5b0 | 1944 | |
3430098a | 1945 | if (!sband || idx >= sband->n_channels) { |
b7cc9b97 | 1946 | spin_unlock_bh(&common->cc_lock); |
3430098a | 1947 | return -ENOENT; |
4f1a5a4b | 1948 | } |
62dad5b0 | 1949 | |
3430098a FF |
1950 | chan = &sband->channels[idx]; |
1951 | pos = chan->hw_value; | |
1952 | memcpy(survey, &sc->survey[pos], sizeof(*survey)); | |
1953 | survey->channel = chan; | |
b7cc9b97 | 1954 | spin_unlock_bh(&common->cc_lock); |
3430098a | 1955 | |
62dad5b0 BP |
1956 | return 0; |
1957 | } | |
1958 | ||
24a1936b LB |
1959 | static void ath9k_enable_dynack(struct ath_softc *sc) |
1960 | { | |
1961 | #ifdef CONFIG_ATH9K_DYNACK | |
1962 | u32 rfilt; | |
1963 | struct ath_hw *ah = sc->sc_ah; | |
1964 | ||
1965 | ath_dynack_reset(ah); | |
1966 | ||
1967 | ah->dynack.enabled = true; | |
1968 | rfilt = ath_calcrxfilter(sc); | |
1969 | ath9k_hw_setrxfilter(ah, rfilt); | |
1970 | #endif | |
1971 | } | |
1972 | ||
a4bcaf55 LB |
1973 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, |
1974 | s16 coverage_class) | |
e239d859 | 1975 | { |
9ac58615 | 1976 | struct ath_softc *sc = hw->priv; |
e239d859 FF |
1977 | struct ath_hw *ah = sc->sc_ah; |
1978 | ||
89f927af LR |
1979 | if (config_enabled(CONFIG_ATH9K_TX99)) |
1980 | return; | |
1981 | ||
e239d859 | 1982 | mutex_lock(&sc->mutex); |
8b2a3827 | 1983 | |
24a1936b LB |
1984 | if (coverage_class >= 0) { |
1985 | ah->coverage_class = coverage_class; | |
1986 | if (ah->dynack.enabled) { | |
1987 | u32 rfilt; | |
1988 | ||
1989 | ah->dynack.enabled = false; | |
1990 | rfilt = ath_calcrxfilter(sc); | |
1991 | ath9k_hw_setrxfilter(ah, rfilt); | |
1992 | } | |
1993 | ath9k_ps_wakeup(sc); | |
1994 | ath9k_hw_init_global_settings(ah); | |
1995 | ath9k_ps_restore(sc); | |
1996 | } else if (!ah->dynack.enabled) { | |
1997 | ath9k_enable_dynack(sc); | |
1998 | } | |
8b2a3827 | 1999 | |
e239d859 FF |
2000 | mutex_unlock(&sc->mutex); |
2001 | } | |
2002 | ||
e2d389b5 SM |
2003 | static bool ath9k_has_tx_pending(struct ath_softc *sc, |
2004 | bool sw_pending) | |
10e23181 | 2005 | { |
f7838073 | 2006 | int i, npend = 0; |
10e23181 FF |
2007 | |
2008 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
2009 | if (!ATH_TXQ_SETUP(sc, i)) | |
2010 | continue; | |
2011 | ||
e2d389b5 SM |
2012 | npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i], |
2013 | sw_pending); | |
10e23181 FF |
2014 | if (npend) |
2015 | break; | |
2016 | } | |
2017 | ||
2018 | return !!npend; | |
2019 | } | |
2020 | ||
77be2c54 EG |
2021 | static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
2022 | u32 queues, bool drop) | |
bff11766 FF |
2023 | { |
2024 | struct ath_softc *sc = hw->priv; | |
25f3bc7d SM |
2025 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
2026 | ||
2027 | if (ath9k_is_chanctx_enabled()) { | |
2028 | if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags)) | |
2029 | goto flush; | |
bff11766 | 2030 | |
25f3bc7d SM |
2031 | /* |
2032 | * If MCC is active, extend the flush timeout | |
2033 | * and wait for the HW/SW queues to become | |
2034 | * empty. This needs to be done outside the | |
2035 | * sc->mutex lock to allow the channel scheduler | |
2036 | * to switch channel contexts. | |
2037 | * | |
2038 | * The vif queues have been stopped in mac80211, | |
2039 | * so there won't be any incoming frames. | |
2040 | */ | |
2041 | __ath9k_flush(hw, queues, drop, true, true); | |
2042 | return; | |
2043 | } | |
2044 | flush: | |
bff11766 | 2045 | mutex_lock(&sc->mutex); |
25f3bc7d | 2046 | __ath9k_flush(hw, queues, drop, true, false); |
bff11766 FF |
2047 | mutex_unlock(&sc->mutex); |
2048 | } | |
2049 | ||
e2d389b5 | 2050 | void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop, |
25f3bc7d | 2051 | bool sw_pending, bool timeout_override) |
69081624 | 2052 | { |
69081624 | 2053 | struct ath_softc *sc = hw->priv; |
99aa55b6 MSS |
2054 | struct ath_hw *ah = sc->sc_ah; |
2055 | struct ath_common *common = ath9k_hw_common(ah); | |
2fae0d9f | 2056 | int timeout; |
2f6fc351 | 2057 | bool drain_txq; |
69081624 | 2058 | |
69081624 VT |
2059 | cancel_delayed_work_sync(&sc->tx_complete_work); |
2060 | ||
6a6b3f3e | 2061 | if (ah->ah_flags & AH_UNPLUGGED) { |
d2182b69 | 2062 | ath_dbg(common, ANY, "Device has been unplugged!\n"); |
6a6b3f3e MSS |
2063 | return; |
2064 | } | |
2065 | ||
eefa01dd | 2066 | if (test_bit(ATH_OP_INVALID, &common->op_flags)) { |
d2182b69 | 2067 | ath_dbg(common, ANY, "Device not present\n"); |
99aa55b6 MSS |
2068 | return; |
2069 | } | |
2070 | ||
2fae0d9f | 2071 | spin_lock_bh(&sc->chan_lock); |
25f3bc7d SM |
2072 | if (timeout_override) |
2073 | timeout = HZ / 5; | |
2074 | else | |
2075 | timeout = sc->cur_chan->flush_timeout; | |
2fae0d9f SM |
2076 | spin_unlock_bh(&sc->chan_lock); |
2077 | ||
2078 | ath_dbg(common, CHAN_CTX, | |
2079 | "Flush timeout: %d\n", jiffies_to_msecs(timeout)); | |
2080 | ||
e2d389b5 | 2081 | if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending), |
10e23181 FF |
2082 | timeout) > 0) |
2083 | drop = false; | |
69081624 | 2084 | |
9df0d6a2 FF |
2085 | if (drop) { |
2086 | ath9k_ps_wakeup(sc); | |
2087 | spin_lock_bh(&sc->sc_pcu_lock); | |
1381559b | 2088 | drain_txq = ath_drain_all_txq(sc); |
9df0d6a2 | 2089 | spin_unlock_bh(&sc->sc_pcu_lock); |
9adcf440 | 2090 | |
9df0d6a2 | 2091 | if (!drain_txq) |
5555c955 | 2092 | ath_reset(sc, NULL); |
9adcf440 | 2093 | |
9df0d6a2 | 2094 | ath9k_ps_restore(sc); |
9df0d6a2 | 2095 | } |
d78f4b3e | 2096 | |
69081624 | 2097 | ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0); |
69081624 VT |
2098 | } |
2099 | ||
15b91e83 VN |
2100 | static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) |
2101 | { | |
2102 | struct ath_softc *sc = hw->priv; | |
15b91e83 | 2103 | |
e2d389b5 | 2104 | return ath9k_has_tx_pending(sc, true); |
15b91e83 VN |
2105 | } |
2106 | ||
5595f119 | 2107 | static int ath9k_tx_last_beacon(struct ieee80211_hw *hw) |
ba4903f9 FF |
2108 | { |
2109 | struct ath_softc *sc = hw->priv; | |
2110 | struct ath_hw *ah = sc->sc_ah; | |
2111 | struct ieee80211_vif *vif; | |
2112 | struct ath_vif *avp; | |
2113 | struct ath_buf *bf; | |
2114 | struct ath_tx_status ts; | |
4286df60 | 2115 | bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); |
ba4903f9 FF |
2116 | int status; |
2117 | ||
2118 | vif = sc->beacon.bslot[0]; | |
2119 | if (!vif) | |
2120 | return 0; | |
2121 | ||
aa45fe96 | 2122 | if (!vif->bss_conf.enable_beacon) |
ba4903f9 FF |
2123 | return 0; |
2124 | ||
aa45fe96 SM |
2125 | avp = (void *)vif->drv_priv; |
2126 | ||
4286df60 | 2127 | if (!sc->beacon.tx_processed && !edma) { |
ba4903f9 FF |
2128 | tasklet_disable(&sc->bcon_tasklet); |
2129 | ||
2130 | bf = avp->av_bcbuf; | |
2131 | if (!bf || !bf->bf_mpdu) | |
2132 | goto skip; | |
2133 | ||
2134 | status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts); | |
2135 | if (status == -EINPROGRESS) | |
2136 | goto skip; | |
2137 | ||
2138 | sc->beacon.tx_processed = true; | |
2139 | sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK); | |
2140 | ||
2141 | skip: | |
2142 | tasklet_enable(&sc->bcon_tasklet); | |
2143 | } | |
2144 | ||
2145 | return sc->beacon.tx_last; | |
2146 | } | |
2147 | ||
52c94f41 MSS |
2148 | static int ath9k_get_stats(struct ieee80211_hw *hw, |
2149 | struct ieee80211_low_level_stats *stats) | |
2150 | { | |
2151 | struct ath_softc *sc = hw->priv; | |
2152 | struct ath_hw *ah = sc->sc_ah; | |
2153 | struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats; | |
2154 | ||
2155 | stats->dot11ACKFailureCount = mib_stats->ackrcv_bad; | |
2156 | stats->dot11RTSFailureCount = mib_stats->rts_bad; | |
2157 | stats->dot11FCSErrorCount = mib_stats->fcs_bad; | |
2158 | stats->dot11RTSSuccessCount = mib_stats->rts_good; | |
2159 | return 0; | |
2160 | } | |
2161 | ||
43c35284 FF |
2162 | static u32 fill_chainmask(u32 cap, u32 new) |
2163 | { | |
2164 | u32 filled = 0; | |
2165 | int i; | |
2166 | ||
2167 | for (i = 0; cap && new; i++, cap >>= 1) { | |
2168 | if (!(cap & BIT(0))) | |
2169 | continue; | |
2170 | ||
2171 | if (new & BIT(0)) | |
2172 | filled |= BIT(i); | |
2173 | ||
2174 | new >>= 1; | |
2175 | } | |
2176 | ||
2177 | return filled; | |
2178 | } | |
2179 | ||
5d9c7e3c FF |
2180 | static bool validate_antenna_mask(struct ath_hw *ah, u32 val) |
2181 | { | |
fea92cbf FF |
2182 | if (AR_SREV_9300_20_OR_LATER(ah)) |
2183 | return true; | |
2184 | ||
5d9c7e3c FF |
2185 | switch (val & 0x7) { |
2186 | case 0x1: | |
2187 | case 0x3: | |
2188 | case 0x7: | |
2189 | return true; | |
2190 | case 0x2: | |
2191 | return (ah->caps.rx_chainmask == 1); | |
2192 | default: | |
2193 | return false; | |
2194 | } | |
2195 | } | |
2196 | ||
43c35284 FF |
2197 | static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) |
2198 | { | |
2199 | struct ath_softc *sc = hw->priv; | |
2200 | struct ath_hw *ah = sc->sc_ah; | |
2201 | ||
5d9c7e3c FF |
2202 | if (ah->caps.rx_chainmask != 1) |
2203 | rx_ant |= tx_ant; | |
2204 | ||
2205 | if (!validate_antenna_mask(ah, rx_ant) || !tx_ant) | |
43c35284 FF |
2206 | return -EINVAL; |
2207 | ||
2208 | sc->ant_rx = rx_ant; | |
2209 | sc->ant_tx = tx_ant; | |
2210 | ||
2211 | if (ah->caps.rx_chainmask == 1) | |
2212 | return 0; | |
2213 | ||
2214 | /* AR9100 runs into calibration issues if not all rx chains are enabled */ | |
2215 | if (AR_SREV_9100(ah)) | |
2216 | ah->rxchainmask = 0x7; | |
2217 | else | |
2218 | ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant); | |
2219 | ||
2220 | ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant); | |
b57ba3b2 | 2221 | ath9k_cmn_reload_chainmask(ah); |
43c35284 FF |
2222 | |
2223 | return 0; | |
2224 | } | |
2225 | ||
2226 | static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) | |
2227 | { | |
2228 | struct ath_softc *sc = hw->priv; | |
2229 | ||
2230 | *tx_ant = sc->ant_tx; | |
2231 | *rx_ant = sc->ant_rx; | |
2232 | return 0; | |
2233 | } | |
2234 | ||
a344d677 JB |
2235 | static void ath9k_sw_scan_start(struct ieee80211_hw *hw, |
2236 | struct ieee80211_vif *vif, | |
2237 | const u8 *mac_addr) | |
e93d083f SW |
2238 | { |
2239 | struct ath_softc *sc = hw->priv; | |
eefa01dd OR |
2240 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
2241 | set_bit(ATH_OP_SCANNING, &common->op_flags); | |
e93d083f SW |
2242 | } |
2243 | ||
a344d677 JB |
2244 | static void ath9k_sw_scan_complete(struct ieee80211_hw *hw, |
2245 | struct ieee80211_vif *vif) | |
e93d083f SW |
2246 | { |
2247 | struct ath_softc *sc = hw->priv; | |
eefa01dd OR |
2248 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
2249 | clear_bit(ATH_OP_SCANNING, &common->op_flags); | |
e93d083f | 2250 | } |
b11e640a | 2251 | |
499afacc SM |
2252 | #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT |
2253 | ||
6185672a SM |
2254 | static void ath9k_cancel_pending_offchannel(struct ath_softc *sc) |
2255 | { | |
2256 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
2257 | ||
2258 | if (sc->offchannel.roc_vif) { | |
2259 | ath_dbg(common, CHAN_CTX, | |
2260 | "%s: Aborting RoC\n", __func__); | |
2261 | ||
2262 | del_timer_sync(&sc->offchannel.timer); | |
2263 | if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START) | |
d83520b7 | 2264 | ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT); |
6185672a SM |
2265 | } |
2266 | ||
2267 | if (test_bit(ATH_OP_SCANNING, &common->op_flags)) { | |
2268 | ath_dbg(common, CHAN_CTX, | |
2269 | "%s: Aborting HW scan\n", __func__); | |
2270 | ||
2271 | del_timer_sync(&sc->offchannel.timer); | |
2272 | ath_scan_complete(sc, true); | |
2273 | } | |
2274 | } | |
2275 | ||
78b21949 | 2276 | static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
855df36d | 2277 | struct ieee80211_scan_request *hw_req) |
78b21949 | 2278 | { |
855df36d | 2279 | struct cfg80211_scan_request *req = &hw_req->req; |
78b21949 FF |
2280 | struct ath_softc *sc = hw->priv; |
2281 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
2282 | int ret = 0; | |
2283 | ||
2284 | mutex_lock(&sc->mutex); | |
2285 | ||
2286 | if (WARN_ON(sc->offchannel.scan_req)) { | |
2287 | ret = -EBUSY; | |
2288 | goto out; | |
2289 | } | |
2290 | ||
2291 | ath9k_ps_wakeup(sc); | |
2292 | set_bit(ATH_OP_SCANNING, &common->op_flags); | |
2293 | sc->offchannel.scan_vif = vif; | |
2294 | sc->offchannel.scan_req = req; | |
2295 | sc->offchannel.scan_idx = 0; | |
78b21949 | 2296 | |
bc81d43a SM |
2297 | ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n", |
2298 | vif->addr); | |
2299 | ||
2300 | if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) { | |
2301 | ath_dbg(common, CHAN_CTX, "Starting HW scan\n"); | |
405393cf | 2302 | ath_offchannel_next(sc); |
bc81d43a | 2303 | } |
78b21949 FF |
2304 | |
2305 | out: | |
2306 | mutex_unlock(&sc->mutex); | |
2307 | ||
2308 | return ret; | |
2309 | } | |
2310 | ||
2311 | static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw, | |
2312 | struct ieee80211_vif *vif) | |
2313 | { | |
2314 | struct ath_softc *sc = hw->priv; | |
bc81d43a SM |
2315 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
2316 | ||
2317 | ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr); | |
78b21949 FF |
2318 | |
2319 | mutex_lock(&sc->mutex); | |
2320 | del_timer_sync(&sc->offchannel.timer); | |
2321 | ath_scan_complete(sc, true); | |
2322 | mutex_unlock(&sc->mutex); | |
2323 | } | |
2324 | ||
405393cf FF |
2325 | static int ath9k_remain_on_channel(struct ieee80211_hw *hw, |
2326 | struct ieee80211_vif *vif, | |
2327 | struct ieee80211_channel *chan, int duration, | |
2328 | enum ieee80211_roc_type type) | |
2329 | { | |
2330 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2331 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
405393cf FF |
2332 | int ret = 0; |
2333 | ||
2334 | mutex_lock(&sc->mutex); | |
2335 | ||
2336 | if (WARN_ON(sc->offchannel.roc_vif)) { | |
2337 | ret = -EBUSY; | |
2338 | goto out; | |
2339 | } | |
2340 | ||
2341 | ath9k_ps_wakeup(sc); | |
2342 | sc->offchannel.roc_vif = vif; | |
2343 | sc->offchannel.roc_chan = chan; | |
2344 | sc->offchannel.roc_duration = duration; | |
2345 | ||
bc81d43a SM |
2346 | ath_dbg(common, CHAN_CTX, |
2347 | "RoC request on vif: %pM, type: %d duration: %d\n", | |
2348 | vif->addr, type, duration); | |
2349 | ||
2350 | if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) { | |
2351 | ath_dbg(common, CHAN_CTX, "Starting RoC period\n"); | |
405393cf | 2352 | ath_offchannel_next(sc); |
bc81d43a | 2353 | } |
405393cf FF |
2354 | |
2355 | out: | |
2356 | mutex_unlock(&sc->mutex); | |
2357 | ||
2358 | return ret; | |
2359 | } | |
2360 | ||
2361 | static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw) | |
2362 | { | |
2363 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2364 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
405393cf FF |
2365 | |
2366 | mutex_lock(&sc->mutex); | |
2367 | ||
bc81d43a | 2368 | ath_dbg(common, CHAN_CTX, "Cancel RoC\n"); |
405393cf FF |
2369 | del_timer_sync(&sc->offchannel.timer); |
2370 | ||
2371 | if (sc->offchannel.roc_vif) { | |
2372 | if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START) | |
d83520b7 | 2373 | ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL); |
405393cf FF |
2374 | } |
2375 | ||
2376 | mutex_unlock(&sc->mutex); | |
2377 | ||
2378 | return 0; | |
2379 | } | |
2380 | ||
39305635 FF |
2381 | static int ath9k_add_chanctx(struct ieee80211_hw *hw, |
2382 | struct ieee80211_chanctx_conf *conf) | |
2383 | { | |
2384 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2385 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39305635 | 2386 | struct ath_chanctx *ctx, **ptr; |
3ad9c386 | 2387 | int pos; |
39305635 FF |
2388 | |
2389 | mutex_lock(&sc->mutex); | |
c4dc0d04 RM |
2390 | |
2391 | ath_for_each_chanctx(sc, ctx) { | |
2392 | if (ctx->assigned) | |
2393 | continue; | |
2394 | ||
2395 | ptr = (void *) conf->drv_priv; | |
2396 | *ptr = ctx; | |
2397 | ctx->assigned = true; | |
3ad9c386 RM |
2398 | pos = ctx - &sc->chanctx[0]; |
2399 | ctx->hw_queue_base = pos * IEEE80211_NUM_ACS; | |
bc81d43a SM |
2400 | |
2401 | ath_dbg(common, CHAN_CTX, | |
2402 | "Add channel context: %d MHz\n", | |
2403 | conf->def.chan->center_freq); | |
2404 | ||
c4dc0d04 | 2405 | ath_chanctx_set_channel(sc, ctx, &conf->def); |
4c7e9aee | 2406 | |
39305635 | 2407 | mutex_unlock(&sc->mutex); |
c4dc0d04 | 2408 | return 0; |
39305635 | 2409 | } |
bc81d43a | 2410 | |
39305635 | 2411 | mutex_unlock(&sc->mutex); |
c4dc0d04 | 2412 | return -ENOSPC; |
39305635 FF |
2413 | } |
2414 | ||
2415 | ||
2416 | static void ath9k_remove_chanctx(struct ieee80211_hw *hw, | |
2417 | struct ieee80211_chanctx_conf *conf) | |
2418 | { | |
2419 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2420 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39305635 FF |
2421 | struct ath_chanctx *ctx = ath_chanctx_get(conf); |
2422 | ||
2423 | mutex_lock(&sc->mutex); | |
bc81d43a SM |
2424 | |
2425 | ath_dbg(common, CHAN_CTX, | |
2426 | "Remove channel context: %d MHz\n", | |
2427 | conf->def.chan->center_freq); | |
2428 | ||
39305635 | 2429 | ctx->assigned = false; |
b18111d9 | 2430 | ctx->hw_queue_base = 0; |
73fa2f26 | 2431 | ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN); |
bc81d43a | 2432 | |
39305635 FF |
2433 | mutex_unlock(&sc->mutex); |
2434 | } | |
2435 | ||
2436 | static void ath9k_change_chanctx(struct ieee80211_hw *hw, | |
2437 | struct ieee80211_chanctx_conf *conf, | |
2438 | u32 changed) | |
2439 | { | |
2440 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2441 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39305635 FF |
2442 | struct ath_chanctx *ctx = ath_chanctx_get(conf); |
2443 | ||
2444 | mutex_lock(&sc->mutex); | |
bc81d43a SM |
2445 | ath_dbg(common, CHAN_CTX, |
2446 | "Change channel context: %d MHz\n", | |
2447 | conf->def.chan->center_freq); | |
39305635 FF |
2448 | ath_chanctx_set_channel(sc, ctx, &conf->def); |
2449 | mutex_unlock(&sc->mutex); | |
2450 | } | |
2451 | ||
2452 | static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw, | |
2453 | struct ieee80211_vif *vif, | |
2454 | struct ieee80211_chanctx_conf *conf) | |
2455 | { | |
2456 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2457 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39305635 FF |
2458 | struct ath_vif *avp = (void *)vif->drv_priv; |
2459 | struct ath_chanctx *ctx = ath_chanctx_get(conf); | |
3ad9c386 | 2460 | int i; |
39305635 | 2461 | |
6185672a SM |
2462 | ath9k_cancel_pending_offchannel(sc); |
2463 | ||
39305635 | 2464 | mutex_lock(&sc->mutex); |
bc81d43a SM |
2465 | |
2466 | ath_dbg(common, CHAN_CTX, | |
2467 | "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n", | |
2468 | vif->addr, vif->type, vif->p2p, | |
2469 | conf->def.chan->center_freq); | |
2470 | ||
39305635 | 2471 | avp->chanctx = ctx; |
2ce73c02 | 2472 | ctx->nvifs_assigned++; |
39305635 | 2473 | list_add_tail(&avp->list, &ctx->vifs); |
9a9c4fbc | 2474 | ath9k_calculate_summary_state(sc, ctx); |
3ad9c386 RM |
2475 | for (i = 0; i < IEEE80211_NUM_ACS; i++) |
2476 | vif->hw_queue[i] = ctx->hw_queue_base + i; | |
bc81d43a | 2477 | |
39305635 FF |
2478 | mutex_unlock(&sc->mutex); |
2479 | ||
2480 | return 0; | |
2481 | } | |
2482 | ||
2483 | static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw, | |
2484 | struct ieee80211_vif *vif, | |
2485 | struct ieee80211_chanctx_conf *conf) | |
2486 | { | |
2487 | struct ath_softc *sc = hw->priv; | |
bc81d43a | 2488 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
39305635 FF |
2489 | struct ath_vif *avp = (void *)vif->drv_priv; |
2490 | struct ath_chanctx *ctx = ath_chanctx_get(conf); | |
3ad9c386 | 2491 | int ac; |
39305635 | 2492 | |
6185672a SM |
2493 | ath9k_cancel_pending_offchannel(sc); |
2494 | ||
39305635 | 2495 | mutex_lock(&sc->mutex); |
bc81d43a SM |
2496 | |
2497 | ath_dbg(common, CHAN_CTX, | |
2498 | "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n", | |
2499 | vif->addr, vif->type, vif->p2p, | |
2500 | conf->def.chan->center_freq); | |
2501 | ||
39305635 | 2502 | avp->chanctx = NULL; |
2ce73c02 | 2503 | ctx->nvifs_assigned--; |
39305635 | 2504 | list_del(&avp->list); |
9a9c4fbc | 2505 | ath9k_calculate_summary_state(sc, ctx); |
3ad9c386 RM |
2506 | for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) |
2507 | vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE; | |
bc81d43a | 2508 | |
39305635 FF |
2509 | mutex_unlock(&sc->mutex); |
2510 | } | |
2511 | ||
e20a854e SM |
2512 | static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw, |
2513 | struct ieee80211_vif *vif) | |
2514 | { | |
2515 | struct ath_softc *sc = hw->priv; | |
2516 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
2517 | struct ath_vif *avp = (struct ath_vif *) vif->drv_priv; | |
c6500ea2 SM |
2518 | struct ath_beacon_config *cur_conf; |
2519 | struct ath_chanctx *go_ctx; | |
2520 | unsigned long timeout; | |
e20a854e | 2521 | bool changed = false; |
c6500ea2 | 2522 | u32 beacon_int; |
e20a854e SM |
2523 | |
2524 | if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags)) | |
2525 | return; | |
2526 | ||
2527 | if (!avp->chanctx) | |
2528 | return; | |
2529 | ||
2530 | mutex_lock(&sc->mutex); | |
2531 | ||
2532 | spin_lock_bh(&sc->chan_lock); | |
c6500ea2 | 2533 | if (sc->next_chan || (sc->cur_chan != avp->chanctx)) |
e20a854e | 2534 | changed = true; |
c6500ea2 SM |
2535 | spin_unlock_bh(&sc->chan_lock); |
2536 | ||
2537 | if (!changed) | |
2538 | goto out; | |
2539 | ||
6185672a | 2540 | ath9k_cancel_pending_offchannel(sc); |
23aab0c2 | 2541 | |
c6500ea2 SM |
2542 | go_ctx = ath_is_go_chanctx_present(sc); |
2543 | ||
2544 | if (go_ctx) { | |
2545 | /* | |
2546 | * Wait till the GO interface gets a chance | |
2547 | * to send out an NoA. | |
2548 | */ | |
2549 | spin_lock_bh(&sc->chan_lock); | |
2550 | sc->sched.mgd_prepare_tx = true; | |
2551 | cur_conf = &go_ctx->beacon; | |
2552 | beacon_int = TU_TO_USEC(cur_conf->beacon_interval); | |
2553 | spin_unlock_bh(&sc->chan_lock); | |
2554 | ||
6185672a | 2555 | timeout = usecs_to_jiffies(beacon_int * 2); |
c6500ea2 SM |
2556 | init_completion(&sc->go_beacon); |
2557 | ||
6185672a | 2558 | mutex_unlock(&sc->mutex); |
2c3634a8 | 2559 | |
c6500ea2 | 2560 | if (wait_for_completion_timeout(&sc->go_beacon, |
2c3634a8 | 2561 | timeout) == 0) { |
c6500ea2 SM |
2562 | ath_dbg(common, CHAN_CTX, |
2563 | "Failed to send new NoA\n"); | |
2c3634a8 SM |
2564 | |
2565 | spin_lock_bh(&sc->chan_lock); | |
2566 | sc->sched.mgd_prepare_tx = false; | |
2567 | spin_unlock_bh(&sc->chan_lock); | |
2568 | } | |
2569 | ||
6185672a | 2570 | mutex_lock(&sc->mutex); |
e20a854e | 2571 | } |
c6500ea2 | 2572 | |
878066e7 | 2573 | ath_dbg(common, CHAN_CTX, |
c6500ea2 SM |
2574 | "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n", |
2575 | __func__, vif->addr); | |
2576 | ||
2577 | spin_lock_bh(&sc->chan_lock); | |
2578 | sc->next_chan = avp->chanctx; | |
e20a854e SM |
2579 | sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE; |
2580 | spin_unlock_bh(&sc->chan_lock); | |
2581 | ||
c6500ea2 SM |
2582 | ath_chanctx_set_next(sc, true); |
2583 | out: | |
e20a854e SM |
2584 | mutex_unlock(&sc->mutex); |
2585 | } | |
2586 | ||
78b21949 FF |
2587 | void ath9k_fill_chanctx_ops(void) |
2588 | { | |
499afacc | 2589 | if (!ath9k_is_chanctx_enabled()) |
78b21949 FF |
2590 | return; |
2591 | ||
bc81d43a SM |
2592 | ath9k_ops.hw_scan = ath9k_hw_scan; |
2593 | ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan; | |
2594 | ath9k_ops.remain_on_channel = ath9k_remain_on_channel; | |
405393cf | 2595 | ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel; |
bc81d43a SM |
2596 | ath9k_ops.add_chanctx = ath9k_add_chanctx; |
2597 | ath9k_ops.remove_chanctx = ath9k_remove_chanctx; | |
2598 | ath9k_ops.change_chanctx = ath9k_change_chanctx; | |
2599 | ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx; | |
2600 | ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx; | |
e20a854e | 2601 | ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx; |
78b21949 FF |
2602 | } |
2603 | ||
499afacc SM |
2604 | #endif |
2605 | ||
d385c5c2 FF |
2606 | static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
2607 | int *dbm) | |
2608 | { | |
2609 | struct ath_softc *sc = hw->priv; | |
2610 | struct ath_vif *avp = (void *)vif->drv_priv; | |
2611 | ||
2612 | mutex_lock(&sc->mutex); | |
2613 | if (avp->chanctx) | |
2614 | *dbm = avp->chanctx->cur_txpower; | |
2615 | else | |
2616 | *dbm = sc->cur_chan->cur_txpower; | |
2617 | mutex_unlock(&sc->mutex); | |
2618 | ||
2619 | *dbm /= 2; | |
2620 | ||
2621 | return 0; | |
2622 | } | |
2623 | ||
6baff7f9 | 2624 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2625 | .tx = ath9k_tx, |
2626 | .start = ath9k_start, | |
2627 | .stop = ath9k_stop, | |
2628 | .add_interface = ath9k_add_interface, | |
6b3b991d | 2629 | .change_interface = ath9k_change_interface, |
8feceb67 VT |
2630 | .remove_interface = ath9k_remove_interface, |
2631 | .config = ath9k_config, | |
8feceb67 | 2632 | .configure_filter = ath9k_configure_filter, |
df3c6eb3 | 2633 | .sta_state = ath9k_sta_state, |
5519541d | 2634 | .sta_notify = ath9k_sta_notify, |
8feceb67 | 2635 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2636 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2637 | .set_key = ath9k_set_key, |
8feceb67 | 2638 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2639 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2640 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2641 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2642 | .get_survey = ath9k_get_survey, |
3b319aae | 2643 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2644 | .set_coverage_class = ath9k_set_coverage_class, |
69081624 | 2645 | .flush = ath9k_flush, |
15b91e83 | 2646 | .tx_frames_pending = ath9k_tx_frames_pending, |
52c94f41 | 2647 | .tx_last_beacon = ath9k_tx_last_beacon, |
86a22acf | 2648 | .release_buffered_frames = ath9k_release_buffered_frames, |
52c94f41 | 2649 | .get_stats = ath9k_get_stats, |
43c35284 FF |
2650 | .set_antenna = ath9k_set_antenna, |
2651 | .get_antenna = ath9k_get_antenna, | |
b90bd9d1 | 2652 | |
e60001e7 | 2653 | #ifdef CONFIG_ATH9K_WOW |
b11e640a MSS |
2654 | .suspend = ath9k_suspend, |
2655 | .resume = ath9k_resume, | |
2656 | .set_wakeup = ath9k_set_wakeup, | |
2657 | #endif | |
2658 | ||
b90bd9d1 BG |
2659 | #ifdef CONFIG_ATH9K_DEBUGFS |
2660 | .get_et_sset_count = ath9k_get_et_sset_count, | |
a145daf7 SM |
2661 | .get_et_stats = ath9k_get_et_stats, |
2662 | .get_et_strings = ath9k_get_et_strings, | |
2663 | #endif | |
2664 | ||
1cdbaf0d | 2665 | #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS) |
a145daf7 | 2666 | .sta_add_debugfs = ath9k_sta_add_debugfs, |
b90bd9d1 | 2667 | #endif |
e93d083f SW |
2668 | .sw_scan_start = ath9k_sw_scan_start, |
2669 | .sw_scan_complete = ath9k_sw_scan_complete, | |
d385c5c2 | 2670 | .get_txpower = ath9k_get_txpower, |
8feceb67 | 2671 | }; |