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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth...
[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
6dcc3444
SM		 22static void ath9k_set_assoc_state(struct ath_softc *sc,
23 struct ieee80211_vif *vif);
24
313eb87f 25u8 ath9k_parse_mpdudensity(u8 mpdudensity)
ff37e337
S		 26{
27 /*
28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
29 * 0 for no restriction
30 * 1 for 1/4 us
31 * 2 for 1/2 us
32 * 3 for 1 us
33 * 4 for 2 us
34 * 5 for 4 us
35 * 6 for 8 us
36 * 7 for 16 us
37 */
38 switch (mpdudensity) {
39 case 0:
40 return 0;
41 case 1:
42 case 2:
43 case 3:
44 /* Our lower layer calculations limit our precision to
45 1 microsecond */
46 return 1;
47 case 4:
48 return 2;
49 case 5:
50 return 4;
51 case 6:
52 return 8;
53 case 7:
54 return 16;
55 default:
56 return 0;
57 }
58}
59
69081624
VT		 60static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
61{
62 bool pending = false;
63
64 spin_lock_bh(&txq->axq_lock);
65
66 if (txq->axq_depth || !list_empty(&txq->axq_acq))
67 pending = true;
69081624
VT		 68
69 spin_unlock_bh(&txq->axq_lock);
70 return pending;
71}
72
6d79cb4c 73static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR		 74{
75 unsigned long flags;
76 bool ret;
77
9ecdef4b
LR		 78 spin_lock_irqsave(&sc->sc_pm_lock, flags);
79 ret = ath9k_hw_setpower(sc->sc_ah, mode);
80 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR		 81
82 return ret;
83}
84
a91d75ae
LR		 85void ath9k_ps_wakeup(struct ath_softc *sc)
86{
898c914a 87 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 88 unsigned long flags;
fbb078fc 89 enum ath9k_power_mode power_mode;
a91d75ae
LR		 90
91 spin_lock_irqsave(&sc->sc_pm_lock, flags);
92 if (++sc->ps_usecount != 1)
93 goto unlock;
94
fbb078fc 95 power_mode = sc->sc_ah->power_mode;
9ecdef4b 96 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 97
898c914a
FF		 98 /*
99 * While the hardware is asleep, the cycle counters contain no
100 * useful data. Better clear them now so that they don't mess up
101 * survey data results.
102 */
fbb078fc
FF		 103 if (power_mode != ATH9K_PM_AWAKE) {
104 spin_lock(&common->cc_lock);
105 ath_hw_cycle_counters_update(common);
106 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
c9ae6ab4 107 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
fbb078fc
FF		 108 spin_unlock(&common->cc_lock);
109 }
898c914a 110
a91d75ae
LR		 111 unlock:
112 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
113}
114
115void ath9k_ps_restore(struct ath_softc *sc)
116{
898c914a 117 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
c6c539f0 118 enum ath9k_power_mode mode;
a91d75ae 119 unsigned long flags;
ad128860 120 bool reset;
a91d75ae
LR		 121
122 spin_lock_irqsave(&sc->sc_pm_lock, flags);
123 if (--sc->ps_usecount != 0)
124 goto unlock;
125
ad128860
SM		 126 if (sc->ps_idle) {
127 ath9k_hw_setrxabort(sc->sc_ah, 1);
128 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
c6c539f0 129 mode = ATH9K_PM_FULL_SLEEP;
ad128860
SM		 130 } else if (sc->ps_enabled &&
131 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
132 PS_WAIT_FOR_CAB |
133 PS_WAIT_FOR_PSPOLL_DATA |
134 PS_WAIT_FOR_TX_ACK))) {
c6c539f0 135 mode = ATH9K_PM_NETWORK_SLEEP;
08d4df41
RM		 136 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
137 ath9k_btcoex_stop_gen_timer(sc);
ad128860 138 } else {
c6c539f0 139 goto unlock;
ad128860 140 }
c6c539f0
FF		 141
142 spin_lock(&common->cc_lock);
143 ath_hw_cycle_counters_update(common);
144 spin_unlock(&common->cc_lock);
145
1a8f0d39 146 ath9k_hw_setpower(sc->sc_ah, mode);
a91d75ae
LR		 147
148 unlock:
149 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
150}
151
9adcf440 152static void __ath_cancel_work(struct ath_softc *sc)
ff37e337 153{
5ee08656
FF		 154 cancel_work_sync(&sc->paprd_work);
155 cancel_work_sync(&sc->hw_check_work);
156 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 157 cancel_delayed_work_sync(&sc->hw_pll_work);
fad29cd2 158
bf52592f 159#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
fad29cd2
SM		 160 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
161 cancel_work_sync(&sc->mci_work);
bf52592f 162#endif
9adcf440 163}
5ee08656 164
9adcf440
FF		 165static void ath_cancel_work(struct ath_softc *sc)
166{
167 __ath_cancel_work(sc);
168 cancel_work_sync(&sc->hw_reset_work);
169}
3cbb5dd7 170
af68abad
SM		 171static void ath_restart_work(struct ath_softc *sc)
172{
af68abad
SM		 173 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
174
c12b6021
GJ		 175 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
176 AR_SREV_9550(sc->sc_ah))
af68abad
SM		 177 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
178 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
179
180 ath_start_rx_poll(sc, 3);
da0d45f7 181 ath_start_ani(sc);
af68abad
SM		 182}
183
9adcf440
FF		 184static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
185{
186 struct ath_hw *ah = sc->sc_ah;
ceea2a51 187 bool ret = true;
6a6733f2 188
9adcf440 189 ieee80211_stop_queues(sc->hw);
5e848f78 190
9adcf440 191 sc->hw_busy_count = 0;
da0d45f7 192 ath_stop_ani(sc);
01e18918 193 del_timer_sync(&sc->rx_poll_timer);
ff37e337 194
9adcf440
FF		 195 ath9k_debug_samp_bb_mac(sc);
196 ath9k_hw_disable_interrupts(ah);
8b3f4616 197
9adcf440
FF		 198 if (!ath_stoprecv(sc))
199 ret = false;
c0d7c7af 200
ceea2a51
FF		 201 if (!ath_drain_all_txq(sc, retry_tx))
202 ret = false;
203
9adcf440
FF		 204 if (!flush) {
205 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
3483288c
FF		 206 ath_rx_tasklet(sc, 1, true);
207 ath_rx_tasklet(sc, 1, false);
9adcf440
FF		 208 } else {
209 ath_flushrecv(sc);
210 }
20bd2a09 211
9adcf440
FF		 212 return ret;
213}
ff37e337 214
9adcf440
FF		 215static bool ath_complete_reset(struct ath_softc *sc, bool start)
216{
217 struct ath_hw *ah = sc->sc_ah;
218 struct ath_common *common = ath9k_hw_common(ah);
196fb860 219 unsigned long flags;
c0d7c7af 220
c0d7c7af 221 if (ath_startrecv(sc) != 0) {
3800276a 222 ath_err(common, "Unable to restart recv logic\n");
9adcf440 223 return false;
c0d7c7af
LR		 224 }
225
5048e8c3
RM		 226 ath9k_cmn_update_txpow(ah, sc->curtxpow,
227 sc->config.txpowlimit, &sc->curtxpow);
b74713d0
SM		 228
229 clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
72d874c6 230 ath9k_hw_set_interrupts(ah);
b037b693 231 ath9k_hw_enable_interrupts(ah);
3989279c 232
4cb54fa3 233 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
196fb860
SM		 234 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
235 goto work;
236
ef4ad633 237 ath9k_set_beacon(sc);
196fb860
SM		 238
239 if (ah->opmode == NL80211_IFTYPE_STATION &&
240 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
241 spin_lock_irqsave(&sc->sc_pm_lock, flags);
242 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
243 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
244 }
245 work:
af68abad 246 ath_restart_work(sc);
5ee08656
FF		 247 }
248
8da07830
SM		 249 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
250 ath_ant_comb_update(sc);
43c35284 251
9adcf440
FF		 252 ieee80211_wake_queues(sc->hw);
253
254 return true;
255}
256
257static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
258 bool retry_tx)
259{
260 struct ath_hw *ah = sc->sc_ah;
261 struct ath_common *common = ath9k_hw_common(ah);
262 struct ath9k_hw_cal_data *caldata = NULL;
263 bool fastcc = true;
264 bool flush = false;
265 int r;
266
267 __ath_cancel_work(sc);
268
269 spin_lock_bh(&sc->sc_pcu_lock);
92460412 270
4cb54fa3 271 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
9adcf440
FF		 272 fastcc = false;
273 caldata = &sc->caldata;
274 }
275
276 if (!hchan) {
277 fastcc = false;
278 flush = true;
279 hchan = ah->curchan;
280 }
281
9adcf440
FF		 282 if (!ath_prepare_reset(sc, retry_tx, flush))
283 fastcc = false;
284
d2182b69 285 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
feced201 286 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
9adcf440
FF		 287
288 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
289 if (r) {
290 ath_err(common,
291 "Unable to reset channel, reset status %d\n", r);
292 goto out;
293 }
294
295 if (!ath_complete_reset(sc, true))
296 r = -EIO;
297
298out:
6a6733f2 299 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440
FF		 300 return r;
301}
302
303
304/*
305 * Set/change channels. If the channel is really being changed, it's done
306 * by reseting the chip. To accomplish this we must first cleanup any pending
307 * DMA, then restart stuff.
308*/
309static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
310 struct ath9k_channel *hchan)
311{
312 int r;
313
781b14a3 314 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
9adcf440
FF		 315 return -EIO;
316
9adcf440 317 r = ath_reset_internal(sc, hchan, false);
6a6733f2 318
3989279c 319 return r;
ff37e337
S		 320}
321
7e1e3864
BG		 322static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
323 struct ieee80211_vif *vif)
ff37e337
S		 324{
325 struct ath_node *an;
313eb87f 326 u8 density;
ff37e337
S		 327 an = (struct ath_node *)sta->drv_priv;
328
7f010c93
BG		 329#ifdef CONFIG_ATH9K_DEBUGFS
330 spin_lock(&sc->nodes_lock);
331 list_add(&an->list, &sc->nodes);
332 spin_unlock(&sc->nodes_lock);
156369fa 333#endif
7f010c93 334 an->sta = sta;
7e1e3864 335 an->vif = vif;
3d4e20f2 336
a4d6367f 337 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337 338 ath_tx_node_init(sc, an);
9e98ac65 339 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc 340 sta->ht_cap.ampdu_factor);
313eb87f
SE		 341 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
342 an->mpdudensity = density;
87792efc 343 }
ff37e337
S		 344}
345
346static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
347{
348 struct ath_node *an = (struct ath_node *)sta->drv_priv;
349
7f010c93
BG		 350#ifdef CONFIG_ATH9K_DEBUGFS
351 spin_lock(&sc->nodes_lock);
352 list_del(&an->list);
353 spin_unlock(&sc->nodes_lock);
354 an->sta = NULL;
355#endif
356
a4d6367f 357 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
ff37e337
S		 358 ath_tx_node_cleanup(sc, an);
359}
360
55624204 361void ath9k_tasklet(unsigned long data)
ff37e337
S		 362{
363 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 364 struct ath_hw *ah = sc->sc_ah;
c46917bb 365 struct ath_common *common = ath9k_hw_common(ah);
124b979b 366 enum ath_reset_type type;
07c15a3f 367 unsigned long flags;
17d7904d 368 u32 status = sc->intrstatus;
b5c80475 369 u32 rxmask;
ff37e337 370
e3927007
FF		 371 ath9k_ps_wakeup(sc);
372 spin_lock(&sc->sc_pcu_lock);
373
a4d86d95
RM		 374 if ((status & ATH9K_INT_FATAL) ||
375 (status & ATH9K_INT_BB_WATCHDOG)) {
030d6294
FF		 376
377 if (status & ATH9K_INT_FATAL)
378 type = RESET_TYPE_FATAL_INT;
379 else
380 type = RESET_TYPE_BB_WATCHDOG;
381
124b979b 382 ath9k_queue_reset(sc, type);
e3927007 383 goto out;
063d8be3 384 }
ff37e337 385
07c15a3f 386 spin_lock_irqsave(&sc->sc_pm_lock, flags);
4105f807
RM		 387 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
388 /*
389 * TSF sync does not look correct; remain awake to sync with
390 * the next Beacon.
391 */
d2182b69 392 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
e8fe7336 393 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
4105f807 394 }
07c15a3f 395 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
4105f807 396
b5c80475
FF		 397 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
398 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
399 ATH9K_INT_RXORN);
400 else
401 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
402
403 if (status & rxmask) {
b5c80475
FF		 404 /* Check for high priority Rx first */
405 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
406 (status & ATH9K_INT_RXHP))
407 ath_rx_tasklet(sc, 0, true);
408
409 ath_rx_tasklet(sc, 0, false);
ff37e337
S		 410 }
411
e5003249
VT		 412 if (status & ATH9K_INT_TX) {
413 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
414 ath_tx_edma_tasklet(sc);
415 else
416 ath_tx_tasklet(sc);
417 }
063d8be3 418
56ca0dba 419 ath9k_btcoex_handle_interrupt(sc, status);
19686ddf 420
e3927007 421out:
ff37e337 422 /* re-enable hardware interrupt */
4df3071e 423 ath9k_hw_enable_interrupts(ah);
6a6733f2 424
52671e43 425 spin_unlock(&sc->sc_pcu_lock);
153e080d 426 ath9k_ps_restore(sc);
ff37e337
S		 427}
428
6baff7f9 429irqreturn_t ath_isr(int irq, void *dev)
ff37e337 430{
063d8be3
S		 431#define SCHED_INTR ( \
432 ATH9K_INT_FATAL | \
a4d86d95 433 ATH9K_INT_BB_WATCHDOG | \
063d8be3
S		 434 ATH9K_INT_RXORN | \
435 ATH9K_INT_RXEOL | \
436 ATH9K_INT_RX | \
b5c80475
FF		 437 ATH9K_INT_RXLP | \
438 ATH9K_INT_RXHP | \
063d8be3
S		 439 ATH9K_INT_TX | \
440 ATH9K_INT_BMISS | \
441 ATH9K_INT_CST | \
ebb8e1d7 442 ATH9K_INT_TSFOOR | \
40dc5392
MSS		 443 ATH9K_INT_GENTIMER | \
444 ATH9K_INT_MCI)
063d8be3 445
ff37e337 446 struct ath_softc *sc = dev;
cbe61d8a 447 struct ath_hw *ah = sc->sc_ah;
b5bfc568 448 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S		 449 enum ath9k_int status;
450 bool sched = false;
451
063d8be3
S		 452 /*
453 * The hardware is not ready/present, don't
454 * touch anything. Note this can happen early
455 * on if the IRQ is shared.
456 */
781b14a3 457 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
063d8be3 458 return IRQ_NONE;
ff37e337 459
063d8be3
S		 460 /* shared irq, not for us */
461
153e080d 462 if (!ath9k_hw_intrpend(ah))
063d8be3 463 return IRQ_NONE;
063d8be3 464
b74713d0
SM		 465 if(test_bit(SC_OP_HW_RESET, &sc->sc_flags))
466 return IRQ_HANDLED;
467
063d8be3
S		 468 /*
469 * Figure out the reason(s) for the interrupt. Note
470 * that the hal returns a pseudo-ISR that may include
471 * bits we haven't explicitly enabled so we mask the
472 * value to insure we only process bits we requested.
473 */
474 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 475 status &= ah->imask; /* discard unasked-for bits */
ff37e337 476
063d8be3
S		 477 /*
478 * If there are no status bits set, then this interrupt was not
479 * for me (should have been caught above).
480 */
153e080d 481 if (!status)
063d8be3 482 return IRQ_NONE;
ff37e337 483
063d8be3
S		 484 /* Cache the status */
485 sc->intrstatus = status;
486
487 if (status & SCHED_INTR)
488 sched = true;
489
b11e640a
MSS		 490#ifdef CONFIG_PM_SLEEP
491 if (status & ATH9K_INT_BMISS) {
492 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
493 ath_dbg(common, ANY, "during WoW we got a BMISS\n");
494 atomic_inc(&sc->wow_got_bmiss_intr);
495 atomic_dec(&sc->wow_sleep_proc_intr);
496 }
497 ath_dbg(common, INTERRUPT, "beacon miss interrupt\n");
498 }
499#endif
500
063d8be3
S		 501 /*
502 * If a FATAL or RXORN interrupt is received, we have to reset the
503 * chip immediately.
504 */
b5c80475
FF		 505 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
506 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S		 507 goto chip_reset;
508
08578b8f
LR		 509 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
510 (status & ATH9K_INT_BB_WATCHDOG)) {
b5bfc568
FF		 511
512 spin_lock(&common->cc_lock);
513 ath_hw_cycle_counters_update(common);
08578b8f 514 ar9003_hw_bb_watchdog_dbg_info(ah);
b5bfc568
FF		 515 spin_unlock(&common->cc_lock);
516
08578b8f
LR		 517 goto chip_reset;
518 }
519
063d8be3
S		 520 if (status & ATH9K_INT_SWBA)
521 tasklet_schedule(&sc->bcon_tasklet);
522
523 if (status & ATH9K_INT_TXURN)
524 ath9k_hw_updatetxtriglevel(ah, true);
525
0682c9b5
RM		 526 if (status & ATH9K_INT_RXEOL) {
527 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
72d874c6 528 ath9k_hw_set_interrupts(ah);
b5c80475
FF		 529 }
530
153e080d
VT		 531 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
532 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR		 533 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
534 goto chip_reset;
063d8be3
S		 535 /* Clear RxAbort bit so that we can
536 * receive frames */
9ecdef4b 537 ath9k_setpower(sc, ATH9K_PM_AWAKE);
07c15a3f 538 spin_lock(&sc->sc_pm_lock);
153e080d 539 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 540 sc->ps_flags |= PS_WAIT_FOR_BEACON;
07c15a3f 541 spin_unlock(&sc->sc_pm_lock);
ff37e337 542 }
063d8be3
S		 543
544chip_reset:
ff37e337 545
817e11de
S		 546 ath_debug_stat_interrupt(sc, status);
547
ff37e337 548 if (sched) {
4df3071e
FF		 549 /* turn off every interrupt */
550 ath9k_hw_disable_interrupts(ah);
ff37e337
S		 551 tasklet_schedule(&sc->intr_tq);
552 }
553
554 return IRQ_HANDLED;
063d8be3
S		 555
556#undef SCHED_INTR
ff37e337
S		 557}
558
236de514 559static int ath_reset(struct ath_softc *sc, bool retry_tx)
ff37e337 560{
ae8d2858 561 int r;
ff37e337 562
783cd01e 563 ath9k_ps_wakeup(sc);
6a6733f2 564
9adcf440 565 r = ath_reset_internal(sc, NULL, retry_tx);
ff37e337
S		 566
567 if (retry_tx) {
568 int i;
569 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
570 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 571 spin_lock_bh(&sc->tx.txq[i].axq_lock);
572 ath_txq_schedule(sc, &sc->tx.txq[i]);
573 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 574 }
575 }
576 }
577
783cd01e 578 ath9k_ps_restore(sc);
2ab81d4a 579
ae8d2858 580 return r;
ff37e337
S		 581}
582
124b979b
RM		 583void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
584{
585#ifdef CONFIG_ATH9K_DEBUGFS
586 RESET_STAT_INC(sc, type);
587#endif
588 set_bit(SC_OP_HW_RESET, &sc->sc_flags);
589 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
590}
591
236de514
FF		 592void ath_reset_work(struct work_struct *work)
593{
594 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
595
236de514 596 ath_reset(sc, true);
236de514
FF		 597}
598
ff37e337
S		 599/**********************/
600/* mac80211 callbacks */
601/**********************/
602
8feceb67 603static int ath9k_start(struct ieee80211_hw *hw)
f078f209 604{
9ac58615 605 struct ath_softc *sc = hw->priv;
af03abec 606 struct ath_hw *ah = sc->sc_ah;
c46917bb 607 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 608 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 609 struct ath9k_channel *init_channel;
82880a7c 610 int r;
f078f209 611
d2182b69 612 ath_dbg(common, CONFIG,
226afe68
JP		 613 "Starting driver with initial channel: %d MHz\n",
614 curchan->center_freq);
f078f209 615
f62d816f 616 ath9k_ps_wakeup(sc);
141b38b6
S		 617 mutex_lock(&sc->mutex);
618
c344c9cb 619 init_channel = ath9k_cmn_get_curchannel(hw, ah);
ff37e337
S		 620
621 /* Reset SERDES registers */
84c87dc8 622 ath9k_hw_configpcipowersave(ah, false);
ff37e337
S		 623
624 /*
625 * The basic interface to setting the hardware in a good
626 * state is ``reset''. On return the hardware is known to
627 * be powered up and with interrupts disabled. This must
628 * be followed by initialization of the appropriate bits
629 * and then setup of the interrupt mask.
630 */
4bdd1e97 631 spin_lock_bh(&sc->sc_pcu_lock);
c0c11741
FF		 632
633 atomic_set(&ah->intr_ref_cnt, -1);
634
20bd2a09 635 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 636 if (r) {
3800276a
JP		 637 ath_err(common,
638 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
639 r, curchan->center_freq);
4bdd1e97 640 spin_unlock_bh(&sc->sc_pcu_lock);
141b38b6 641 goto mutex_unlock;
ff37e337 642 }
ff37e337 643
ff37e337 644 /* Setup our intr mask. */
b5c80475
FF		 645 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
646 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
647 ATH9K_INT_GLOBAL;
648
649 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR		 650 ah->imask |= ATH9K_INT_RXHP |
651 ATH9K_INT_RXLP |
652 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF		 653 else
654 ah->imask |= ATH9K_INT_RX;
ff37e337 655
364734fa 656 ah->imask |= ATH9K_INT_GTT;
ff37e337 657
af03abec 658 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 659 ah->imask |= ATH9K_INT_CST;
ff37e337 660
e270e776 661 ath_mci_enable(sc);
40dc5392 662
781b14a3 663 clear_bit(SC_OP_INVALID, &sc->sc_flags);
5f841b41 664 sc->sc_ah->is_monitoring = false;
ff37e337 665
9adcf440
FF		 666 if (!ath_complete_reset(sc, false)) {
667 r = -EIO;
668 spin_unlock_bh(&sc->sc_pcu_lock);
669 goto mutex_unlock;
670 }
ff37e337 671
c0c11741
FF		 672 if (ah->led_pin >= 0) {
673 ath9k_hw_cfg_output(ah, ah->led_pin,
674 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
675 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
676 }
677
678 /*
679 * Reset key cache to sane defaults (all entries cleared) instead of
680 * semi-random values after suspend/resume.
681 */
682 ath9k_cmn_init_crypto(sc->sc_ah);
683
9adcf440 684 spin_unlock_bh(&sc->sc_pcu_lock);
164ace38 685
8060e169
VT		 686 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
687 common->bus_ops->extn_synch_en(common);
688
141b38b6
S		 689mutex_unlock:
690 mutex_unlock(&sc->mutex);
691
f62d816f
FF		 692 ath9k_ps_restore(sc);
693
ae8d2858 694 return r;
f078f209
LR		 695}
696
7bb45683 697static void ath9k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
f078f209 698{
9ac58615 699 struct ath_softc *sc = hw->priv;
c46917bb 700 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 701 struct ath_tx_control txctl;
1bc14880 702 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
07c15a3f 703 unsigned long flags;
528f0c6b 704
96148326 705 if (sc->ps_enabled) {
dc8c4585
JM		 706 /*
707 * mac80211 does not set PM field for normal data frames, so we
708 * need to update that based on the current PS mode.
709 */
710 if (ieee80211_is_data(hdr->frame_control) &&
711 !ieee80211_is_nullfunc(hdr->frame_control) &&
712 !ieee80211_has_pm(hdr->frame_control)) {
d2182b69 713 ath_dbg(common, PS,
226afe68 714 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM		 715 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
716 }
717 }
718
ad128860 719 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
9a23f9ca
JM		 720 /*
721 * We are using PS-Poll and mac80211 can request TX while in
722 * power save mode. Need to wake up hardware for the TX to be
723 * completed and if needed, also for RX of buffered frames.
724 */
9a23f9ca 725 ath9k_ps_wakeup(sc);
07c15a3f 726 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fdf76622
VT		 727 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
728 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 729 if (ieee80211_is_pspoll(hdr->frame_control)) {
d2182b69 730 ath_dbg(common, PS,
226afe68 731 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 732 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 733 } else {
d2182b69 734 ath_dbg(common, PS, "Wake up to complete TX\n");
1b04b930 735 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM		 736 }
737 /*
738 * The actual restore operation will happen only after
ad128860 739 * the ps_flags bit is cleared. We are just dropping
9a23f9ca
JM		 740 * the ps_usecount here.
741 */
07c15a3f 742 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
9a23f9ca
JM		 743 ath9k_ps_restore(sc);
744 }
745
ad128860
SM		 746 /*
747 * Cannot tx while the hardware is in full sleep, it first needs a full
748 * chip reset to recover from that
749 */
750 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
751 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
752 goto exit;
753 }
754
528f0c6b 755 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 756 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
528f0c6b 757
d2182b69 758 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 759
c52f33d0 760 if (ath_tx_start(hw, skb, &txctl) != 0) {
d2182b69 761 ath_dbg(common, XMIT, "TX failed\n");
a5a0bca1 762 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
528f0c6b 763 goto exit;
8feceb67
VT		 764 }
765
7bb45683 766 return;
528f0c6b
S		 767exit:
768 dev_kfree_skb_any(skb);
f078f209
LR		 769}
770
8feceb67 771static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 772{
9ac58615 773 struct ath_softc *sc = hw->priv;
af03abec 774 struct ath_hw *ah = sc->sc_ah;
c46917bb 775 struct ath_common *common = ath9k_hw_common(ah);
c0c11741 776 bool prev_idle;
f078f209 777
4c483817
S		 778 mutex_lock(&sc->mutex);
779
9adcf440 780 ath_cancel_work(sc);
01e18918 781 del_timer_sync(&sc->rx_poll_timer);
c94dbff7 782
781b14a3 783 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
d2182b69 784 ath_dbg(common, ANY, "Device not present\n");
4c483817 785 mutex_unlock(&sc->mutex);
9c84b797
S		 786 return;
787 }
8feceb67 788
3867cf6a
S		 789 /* Ensure HW is awake when we try to shut it down. */
790 ath9k_ps_wakeup(sc);
791
6a6733f2
LR		 792 spin_lock_bh(&sc->sc_pcu_lock);
793
203043f5
SG		 794 /* prevent tasklets to enable interrupts once we disable them */
795 ah->imask &= ~ATH9K_INT_GLOBAL;
796
ff37e337
S		 797 /* make sure h/w will not generate any interrupt
798 * before setting the invalid flag. */
4df3071e 799 ath9k_hw_disable_interrupts(ah);
ff37e337 800
c0c11741
FF		 801 spin_unlock_bh(&sc->sc_pcu_lock);
802
803 /* we can now sync irq and kill any running tasklets, since we already
804 * disabled interrupts and not holding a spin lock */
805 synchronize_irq(sc->irq);
806 tasklet_kill(&sc->intr_tq);
807 tasklet_kill(&sc->bcon_tasklet);
808
809 prev_idle = sc->ps_idle;
810 sc->ps_idle = true;
811
812 spin_lock_bh(&sc->sc_pcu_lock);
813
814 if (ah->led_pin >= 0) {
815 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
816 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
817 }
818
819 ath_prepare_reset(sc, false, true);
ff37e337 820
0d95521e
FF		 821 if (sc->rx.frag) {
822 dev_kfree_skb_any(sc->rx.frag);
823 sc->rx.frag = NULL;
824 }
825
c0c11741
FF		 826 if (!ah->curchan)
827 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
6a6733f2 828
c0c11741
FF		 829 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
830 ath9k_hw_phy_disable(ah);
6a6733f2 831
c0c11741 832 ath9k_hw_configpcipowersave(ah, true);
203043f5 833
c0c11741 834 spin_unlock_bh(&sc->sc_pcu_lock);
3867cf6a 835
c0c11741 836 ath9k_ps_restore(sc);
ff37e337 837
781b14a3 838 set_bit(SC_OP_INVALID, &sc->sc_flags);
c0c11741 839 sc->ps_idle = prev_idle;
500c064d 840
141b38b6
S		 841 mutex_unlock(&sc->mutex);
842
d2182b69 843 ath_dbg(common, CONFIG, "Driver halt\n");
f078f209
LR		 844}
845
4801416c
BG		 846bool ath9k_uses_beacons(int type)
847{
848 switch (type) {
849 case NL80211_IFTYPE_AP:
850 case NL80211_IFTYPE_ADHOC:
851 case NL80211_IFTYPE_MESH_POINT:
852 return true;
853 default:
854 return false;
855 }
856}
857
4801416c
BG		 858static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
859{
860 struct ath9k_vif_iter_data *iter_data = data;
861 int i;
862
863 if (iter_data->hw_macaddr)
864 for (i = 0; i < ETH_ALEN; i++)
865 iter_data->mask[i] &=
866 ~(iter_data->hw_macaddr[i] ^ mac[i]);
141b38b6 867
1ed32e4f 868 switch (vif->type) {
4801416c
BG		 869 case NL80211_IFTYPE_AP:
870 iter_data->naps++;
f078f209 871 break;
4801416c
BG		 872 case NL80211_IFTYPE_STATION:
873 iter_data->nstations++;
e51f3eff 874 break;
05c914fe 875 case NL80211_IFTYPE_ADHOC:
4801416c
BG		 876 iter_data->nadhocs++;
877 break;
9cb5412b 878 case NL80211_IFTYPE_MESH_POINT:
4801416c
BG		 879 iter_data->nmeshes++;
880 break;
881 case NL80211_IFTYPE_WDS:
882 iter_data->nwds++;
f078f209
LR		 883 break;
884 default:
4801416c 885 break;
f078f209 886 }
4801416c 887}
f078f209 888
6dcc3444
SM		 889static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
890{
891 struct ath_softc *sc = data;
892 struct ath_vif *avp = (void *)vif->drv_priv;
893
894 if (vif->type != NL80211_IFTYPE_STATION)
895 return;
896
897 if (avp->primary_sta_vif)
898 ath9k_set_assoc_state(sc, vif);
899}
900
4801416c
BG		 901/* Called with sc->mutex held. */
902void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
903 struct ieee80211_vif *vif,
904 struct ath9k_vif_iter_data *iter_data)
905{
9ac58615 906 struct ath_softc *sc = hw->priv;
4801416c
BG		 907 struct ath_hw *ah = sc->sc_ah;
908 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 909
4801416c
BG		 910 /*
911 * Use the hardware MAC address as reference, the hardware uses it
912 * together with the BSSID mask when matching addresses.
913 */
914 memset(iter_data, 0, sizeof(*iter_data));
915 iter_data->hw_macaddr = common->macaddr;
916 memset(&iter_data->mask, 0xff, ETH_ALEN);
5640b08e 917
4801416c
BG		 918 if (vif)
919 ath9k_vif_iter(iter_data, vif->addr, vif);
920
921 /* Get list of all active MAC addresses */
4801416c
BG		 922 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
923 iter_data);
4801416c 924}
8ca21f01 925
4801416c
BG		 926/* Called with sc->mutex held. */
927static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
928 struct ieee80211_vif *vif)
929{
9ac58615 930 struct ath_softc *sc = hw->priv;
4801416c
BG		 931 struct ath_hw *ah = sc->sc_ah;
932 struct ath_common *common = ath9k_hw_common(ah);
933 struct ath9k_vif_iter_data iter_data;
6dcc3444 934 enum nl80211_iftype old_opmode = ah->opmode;
8ca21f01 935
4801416c 936 ath9k_calculate_iter_data(hw, vif, &iter_data);
2c3db3d5 937
4801416c
BG		 938 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
939 ath_hw_setbssidmask(common);
940
4801416c 941 if (iter_data.naps > 0) {
60ca9f87 942 ath9k_hw_set_tsfadjust(ah, true);
4801416c
BG		 943 ah->opmode = NL80211_IFTYPE_AP;
944 } else {
60ca9f87 945 ath9k_hw_set_tsfadjust(ah, false);
5640b08e 946
fd5999cf
JC		 947 if (iter_data.nmeshes)
948 ah->opmode = NL80211_IFTYPE_MESH_POINT;
949 else if (iter_data.nwds)
4801416c
BG		 950 ah->opmode = NL80211_IFTYPE_AP;
951 else if (iter_data.nadhocs)
952 ah->opmode = NL80211_IFTYPE_ADHOC;
953 else
954 ah->opmode = NL80211_IFTYPE_STATION;
955 }
5640b08e 956
df35d29e
SM		 957 ath9k_hw_setopmode(ah);
958
198823fd 959 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
3069168c 960 ah->imask |= ATH9K_INT_TSFOOR;
198823fd 961 else
4801416c 962 ah->imask &= ~ATH9K_INT_TSFOOR;
4af9cf4f 963
72d874c6 964 ath9k_hw_set_interrupts(ah);
6dcc3444
SM		 965
966 /*
967 * If we are changing the opmode to STATION,
968 * a beacon sync needs to be done.
969 */
970 if (ah->opmode == NL80211_IFTYPE_STATION &&
971 old_opmode == NL80211_IFTYPE_AP &&
972 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
973 ieee80211_iterate_active_interfaces_atomic(sc->hw,
974 ath9k_sta_vif_iter, sc);
975 }
4801416c 976}
6f255425 977
4801416c
BG		 978static int ath9k_add_interface(struct ieee80211_hw *hw,
979 struct ieee80211_vif *vif)
6b3b991d 980{
9ac58615 981 struct ath_softc *sc = hw->priv;
4801416c
BG		 982 struct ath_hw *ah = sc->sc_ah;
983 struct ath_common *common = ath9k_hw_common(ah);
4801416c 984 int ret = 0;
6b3b991d 985
96f372c9 986 ath9k_ps_wakeup(sc);
4801416c 987 mutex_lock(&sc->mutex);
6b3b991d 988
4801416c
BG		 989 switch (vif->type) {
990 case NL80211_IFTYPE_STATION:
991 case NL80211_IFTYPE_WDS:
992 case NL80211_IFTYPE_ADHOC:
993 case NL80211_IFTYPE_AP:
994 case NL80211_IFTYPE_MESH_POINT:
995 break;
996 default:
997 ath_err(common, "Interface type %d not yet supported\n",
998 vif->type);
999 ret = -EOPNOTSUPP;
1000 goto out;
1001 }
6b3b991d 1002
4801416c
BG		 1003 if (ath9k_uses_beacons(vif->type)) {
1004 if (sc->nbcnvifs >= ATH_BCBUF) {
1005 ath_err(common, "Not enough beacon buffers when adding"
1006 " new interface of type: %i\n",
1007 vif->type);
1008 ret = -ENOBUFS;
1009 goto out;
1010 }
1011 }
1012
d2182b69 1013 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
4801416c 1014
4801416c
BG		 1015 sc->nvifs++;
1016
130ef6e9
SM		 1017 ath9k_calculate_summary_state(hw, vif);
1018 if (ath9k_uses_beacons(vif->type))
1019 ath9k_beacon_assign_slot(sc, vif);
1020
4801416c
BG		 1021out:
1022 mutex_unlock(&sc->mutex);
96f372c9 1023 ath9k_ps_restore(sc);
4801416c 1024 return ret;
6b3b991d
RM		 1025}
1026
1027static int ath9k_change_interface(struct ieee80211_hw *hw,
1028 struct ieee80211_vif *vif,
1029 enum nl80211_iftype new_type,
1030 bool p2p)
1031{
9ac58615 1032 struct ath_softc *sc = hw->priv;
6b3b991d 1033 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
6dab55bf 1034 int ret = 0;
6b3b991d 1035
d2182b69 1036 ath_dbg(common, CONFIG, "Change Interface\n");
130ef6e9 1037
6b3b991d 1038 mutex_lock(&sc->mutex);
96f372c9 1039 ath9k_ps_wakeup(sc);
6b3b991d 1040
4801416c
BG		 1041 if (ath9k_uses_beacons(new_type) &&
1042 !ath9k_uses_beacons(vif->type)) {
6b3b991d
RM		 1043 if (sc->nbcnvifs >= ATH_BCBUF) {
1044 ath_err(common, "No beacon slot available\n");
6dab55bf
DC		 1045 ret = -ENOBUFS;
1046 goto out;
6b3b991d 1047 }
6b3b991d 1048 }
4801416c 1049
4801416c 1050 if (ath9k_uses_beacons(vif->type))
130ef6e9 1051 ath9k_beacon_remove_slot(sc, vif);
4801416c 1052
6b3b991d
RM		 1053 vif->type = new_type;
1054 vif->p2p = p2p;
1055
130ef6e9
SM		 1056 ath9k_calculate_summary_state(hw, vif);
1057 if (ath9k_uses_beacons(vif->type))
1058 ath9k_beacon_assign_slot(sc, vif);
1059
6dab55bf 1060out:
96f372c9 1061 ath9k_ps_restore(sc);
6b3b991d 1062 mutex_unlock(&sc->mutex);
6dab55bf 1063 return ret;
6b3b991d
RM		 1064}
1065
8feceb67 1066static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1067 struct ieee80211_vif *vif)
f078f209 1068{
9ac58615 1069 struct ath_softc *sc = hw->priv;
c46917bb 1070 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f078f209 1071
d2182b69 1072 ath_dbg(common, CONFIG, "Detach Interface\n");
f078f209 1073
96f372c9 1074 ath9k_ps_wakeup(sc);
141b38b6
S		 1075 mutex_lock(&sc->mutex);
1076
4801416c 1077 sc->nvifs--;
580f0b8a 1078
4801416c 1079 if (ath9k_uses_beacons(vif->type))
130ef6e9 1080 ath9k_beacon_remove_slot(sc, vif);
2c3db3d5 1081
4801416c 1082 ath9k_calculate_summary_state(hw, NULL);
141b38b6
S		 1083
1084 mutex_unlock(&sc->mutex);
96f372c9 1085 ath9k_ps_restore(sc);
f078f209
LR		 1086}
1087
fbab7390 1088static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1089{
3069168c 1090 struct ath_hw *ah = sc->sc_ah;
ad128860 1091 struct ath_common *common = ath9k_hw_common(ah);
3069168c 1092
3f7c5c10 1093 sc->ps_enabled = true;
3069168c
PR		 1094 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1095 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1096 ah->imask |= ATH9K_INT_TIM_TIMER;
72d874c6 1097 ath9k_hw_set_interrupts(ah);
3f7c5c10 1098 }
fdf76622 1099 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1100 }
ad128860 1101 ath_dbg(common, PS, "PowerSave enabled\n");
3f7c5c10
SB		 1102}
1103
845d708e
SB		 1104static void ath9k_disable_ps(struct ath_softc *sc)
1105{
1106 struct ath_hw *ah = sc->sc_ah;
ad128860 1107 struct ath_common *common = ath9k_hw_common(ah);
845d708e
SB		 1108
1109 sc->ps_enabled = false;
1110 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1111 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1112 ath9k_hw_setrxabort(ah, 0);
1113 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1114 PS_WAIT_FOR_CAB |
1115 PS_WAIT_FOR_PSPOLL_DATA |
1116 PS_WAIT_FOR_TX_ACK);
1117 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1118 ah->imask &= ~ATH9K_INT_TIM_TIMER;
72d874c6 1119 ath9k_hw_set_interrupts(ah);
845d708e
SB		 1120 }
1121 }
ad128860 1122 ath_dbg(common, PS, "PowerSave disabled\n");
845d708e
SB		 1123}
1124
e8975581 1125static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1126{
9ac58615 1127 struct ath_softc *sc = hw->priv;
3430098a
FF		 1128 struct ath_hw *ah = sc->sc_ah;
1129 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1130 struct ieee80211_conf *conf = &hw->conf;
75600abf 1131 bool reset_channel = false;
f078f209 1132
c0c11741 1133 ath9k_ps_wakeup(sc);
aa33de09 1134 mutex_lock(&sc->mutex);
141b38b6 1135
daa1b6ee 1136 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4 1137 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
b73f3e78 1138 if (sc->ps_idle) {
daa1b6ee 1139 ath_cancel_work(sc);
b73f3e78
RM		 1140 ath9k_stop_btcoex(sc);
1141 } else {
1142 ath9k_start_btcoex(sc);
75600abf
FF		 1143 /*
1144 * The chip needs a reset to properly wake up from
1145 * full sleep
1146 */
1147 reset_channel = ah->chip_fullsleep;
b73f3e78 1148 }
daa1b6ee 1149 }
64839170 1150
e7824a50
LR		 1151 /*
1152 * We just prepare to enable PS. We have to wait until our AP has
1153 * ACK'd our null data frame to disable RX otherwise we'll ignore
1154 * those ACKs and end up retransmitting the same null data frames.
1155 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1156 */
3cbb5dd7 1157 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR		 1158 unsigned long flags;
1159 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB		 1160 if (conf->flags & IEEE80211_CONF_PS)
1161 ath9k_enable_ps(sc);
845d708e
SB		 1162 else
1163 ath9k_disable_ps(sc);
8ab2cd09 1164 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN		 1165 }
1166
199afd9d
S		 1167 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1168 if (conf->flags & IEEE80211_CONF_MONITOR) {
d2182b69 1169 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
5f841b41
RM		 1170 sc->sc_ah->is_monitoring = true;
1171 } else {
d2182b69 1172 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
5f841b41 1173 sc->sc_ah->is_monitoring = false;
199afd9d
S		 1174 }
1175 }
1176
75600abf 1177 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
99405f93 1178 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1179 int pos = curchan->hw_value;
3430098a
FF		 1180 int old_pos = -1;
1181 unsigned long flags;
1182
1183 if (ah->curchan)
1184 old_pos = ah->curchan - &ah->channels[0];
ae5eb026 1185
d2182b69 1186 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
8c79a610 1187 curchan->center_freq, conf->channel_type);
f078f209 1188
3430098a
FF		 1189 /* update survey stats for the old channel before switching */
1190 spin_lock_irqsave(&common->cc_lock, flags);
1191 ath_update_survey_stats(sc);
1192 spin_unlock_irqrestore(&common->cc_lock, flags);
1193
e338a85e
RM		 1194 /*
1195 * Preserve the current channel values, before updating
1196 * the same channel
1197 */
1a19f77f
RM		 1198 if (ah->curchan && (old_pos == pos))
1199 ath9k_hw_getnf(ah, ah->curchan);
e338a85e
RM		 1200
1201 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1202 curchan, conf->channel_type);
1203
3430098a
FF		 1204 /*
1205 * If the operating channel changes, change the survey in-use flags
1206 * along with it.
1207 * Reset the survey data for the new channel, unless we're switching
1208 * back to the operating channel from an off-channel operation.
1209 */
1210 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1211 sc->cur_survey != &sc->survey[pos]) {
1212
1213 if (sc->cur_survey)
1214 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1215
1216 sc->cur_survey = &sc->survey[pos];
1217
1218 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1219 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1220 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1221 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1222 }
1223
0e2dedf9 1224 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
3800276a 1225 ath_err(common, "Unable to set channel\n");
aa33de09 1226 mutex_unlock(&sc->mutex);
8389fb3f 1227 ath9k_ps_restore(sc);
e11602b7
S		 1228 return -EINVAL;
1229 }
3430098a
FF		 1230
1231 /*
1232 * The most recent snapshot of channel->noisefloor for the old
1233 * channel is only available after the hardware reset. Copy it to
1234 * the survey stats now.
1235 */
1236 if (old_pos >= 0)
1237 ath_update_survey_nf(sc, old_pos);
094d05dc 1238 }
f078f209 1239
c9f6a656 1240 if (changed & IEEE80211_CONF_CHANGE_POWER) {
d2182b69 1241 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
17d7904d 1242 sc->config.txpowlimit = 2 * conf->power_level;
5048e8c3
RM		 1243 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1244 sc->config.txpowlimit, &sc->curtxpow);
64839170
LR		 1245 }
1246
aa33de09 1247 mutex_unlock(&sc->mutex);
c0c11741 1248 ath9k_ps_restore(sc);
141b38b6 1249
f078f209
LR		 1250 return 0;
1251}
1252
8feceb67
VT		 1253#define SUPPORTED_FILTERS \
1254 (FIF_PROMISC_IN_BSS | \
1255 FIF_ALLMULTI | \
1256 FIF_CONTROL | \
af6a3fc7 1257 FIF_PSPOLL | \
8feceb67
VT		 1258 FIF_OTHER_BSS | \
1259 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1260 FIF_PROBE_REQ | \
8feceb67 1261 FIF_FCSFAIL)
c83be688 1262
8feceb67
VT		 1263/* FIXME: sc->sc_full_reset ? */
1264static void ath9k_configure_filter(struct ieee80211_hw *hw,
1265 unsigned int changed_flags,
1266 unsigned int *total_flags,
3ac64bee 1267 u64 multicast)
8feceb67 1268{
9ac58615 1269 struct ath_softc *sc = hw->priv;
8feceb67 1270 u32 rfilt;
f078f209 1271
8feceb67
VT		 1272 changed_flags &= SUPPORTED_FILTERS;
1273 *total_flags &= SUPPORTED_FILTERS;
f078f209 1274
b77f483f 1275 sc->rx.rxfilter = *total_flags;
aa68aeaa 1276 ath9k_ps_wakeup(sc);
8feceb67
VT		 1277 rfilt = ath_calcrxfilter(sc);
1278 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1279 ath9k_ps_restore(sc);
f078f209 1280
d2182b69
JP		 1281 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1282 rfilt);
8feceb67 1283}
f078f209 1284
4ca77860
JB		 1285static int ath9k_sta_add(struct ieee80211_hw *hw,
1286 struct ieee80211_vif *vif,
1287 struct ieee80211_sta *sta)
8feceb67 1288{
9ac58615 1289 struct ath_softc *sc = hw->priv;
93ae2dd2
FF		 1290 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1291 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1292 struct ieee80211_key_conf ps_key = { };
f078f209 1293
7e1e3864 1294 ath_node_attach(sc, sta, vif);
f59a59fe
FF		 1295
1296 if (vif->type != NL80211_IFTYPE_AP &&
1297 vif->type != NL80211_IFTYPE_AP_VLAN)
1298 return 0;
1299
93ae2dd2 1300 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
4ca77860
JB		 1301
1302 return 0;
1303}
1304
93ae2dd2
FF		 1305static void ath9k_del_ps_key(struct ath_softc *sc,
1306 struct ieee80211_vif *vif,
1307 struct ieee80211_sta *sta)
1308{
1309 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1310 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1311 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1312
1313 if (!an->ps_key)
1314 return;
1315
1316 ath_key_delete(common, &ps_key);
1317}
1318
4ca77860
JB		 1319static int ath9k_sta_remove(struct ieee80211_hw *hw,
1320 struct ieee80211_vif *vif,
1321 struct ieee80211_sta *sta)
1322{
9ac58615 1323 struct ath_softc *sc = hw->priv;
4ca77860 1324
93ae2dd2 1325 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB		 1326 ath_node_detach(sc, sta);
1327
1328 return 0;
f078f209
LR		 1329}
1330
5519541d
FF		 1331static void ath9k_sta_notify(struct ieee80211_hw *hw,
1332 struct ieee80211_vif *vif,
1333 enum sta_notify_cmd cmd,
1334 struct ieee80211_sta *sta)
1335{
1336 struct ath_softc *sc = hw->priv;
1337 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1338
3d4e20f2 1339 if (!sta->ht_cap.ht_supported)
b25bfda3
MSS		 1340 return;
1341
5519541d
FF		 1342 switch (cmd) {
1343 case STA_NOTIFY_SLEEP:
1344 an->sleeping = true;
042ec453 1345 ath_tx_aggr_sleep(sta, sc, an);
5519541d
FF		 1346 break;
1347 case STA_NOTIFY_AWAKE:
1348 an->sleeping = false;
1349 ath_tx_aggr_wakeup(sc, an);
1350 break;
1351 }
1352}
1353
8a3a3c85
EP		 1354static int ath9k_conf_tx(struct ieee80211_hw *hw,
1355 struct ieee80211_vif *vif, u16 queue,
8feceb67 1356 const struct ieee80211_tx_queue_params *params)
f078f209 1357{
9ac58615 1358 struct ath_softc *sc = hw->priv;
c46917bb 1359 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1360 struct ath_txq *txq;
8feceb67 1361 struct ath9k_tx_queue_info qi;
066dae93 1362 int ret = 0;
f078f209 1363
8feceb67
VT		 1364 if (queue >= WME_NUM_AC)
1365 return 0;
f078f209 1366
066dae93
FF		 1367 txq = sc->tx.txq_map[queue];
1368
96f372c9 1369 ath9k_ps_wakeup(sc);
141b38b6
S		 1370 mutex_lock(&sc->mutex);
1371
1ffb0610
S		 1372 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1373
8feceb67
VT		 1374 qi.tqi_aifs = params->aifs;
1375 qi.tqi_cwmin = params->cw_min;
1376 qi.tqi_cwmax = params->cw_max;
531bd079 1377 qi.tqi_burstTime = params->txop * 32;
f078f209 1378
d2182b69 1379 ath_dbg(common, CONFIG,
226afe68
JP		 1380 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1381 queue, txq->axq_qnum, params->aifs, params->cw_min,
1382 params->cw_max, params->txop);
f078f209 1383
aa5955c3 1384 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
066dae93 1385 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1386 if (ret)
3800276a 1387 ath_err(common, "TXQ Update failed\n");
f078f209 1388
141b38b6 1389 mutex_unlock(&sc->mutex);
96f372c9 1390 ath9k_ps_restore(sc);
141b38b6 1391
8feceb67
VT		 1392 return ret;
1393}
f078f209 1394
8feceb67
VT		 1395static int ath9k_set_key(struct ieee80211_hw *hw,
1396 enum set_key_cmd cmd,
dc822b5d
JB		 1397 struct ieee80211_vif *vif,
1398 struct ieee80211_sta *sta,
8feceb67
VT		 1399 struct ieee80211_key_conf *key)
1400{
9ac58615 1401 struct ath_softc *sc = hw->priv;
c46917bb 1402 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1403 int ret = 0;
f078f209 1404
3e6109c5 1405 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM		 1406 return -ENOSPC;
1407
5bd5e9a6
CYY		 1408 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1409 vif->type == NL80211_IFTYPE_MESH_POINT) &&
cfdc9a8b
JM		 1410 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1411 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1412 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1413 /*
1414 * For now, disable hw crypto for the RSN IBSS group keys. This
1415 * could be optimized in the future to use a modified key cache
1416 * design to support per-STA RX GTK, but until that gets
1417 * implemented, use of software crypto for group addressed
1418 * frames is a acceptable to allow RSN IBSS to be used.
1419 */
1420 return -EOPNOTSUPP;
1421 }
1422
141b38b6 1423 mutex_lock(&sc->mutex);
3cbb5dd7 1424 ath9k_ps_wakeup(sc);
d2182b69 1425 ath_dbg(common, CONFIG, "Set HW Key\n");
f078f209 1426
8feceb67
VT		 1427 switch (cmd) {
1428 case SET_KEY:
93ae2dd2
FF		 1429 if (sta)
1430 ath9k_del_ps_key(sc, vif, sta);
1431
040e539e 1432 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM		 1433 if (ret >= 0) {
1434 key->hw_key_idx = ret;
8feceb67
VT		 1435 /* push IV and Michael MIC generation to stack */
1436 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1437 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1438 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB		 1439 if (sc->sc_ah->sw_mgmt_crypto &&
1440 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 1441 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1442 ret = 0;
8feceb67
VT		 1443 }
1444 break;
1445 case DISABLE_KEY:
040e539e 1446 ath_key_delete(common, key);
8feceb67
VT		 1447 break;
1448 default:
1449 ret = -EINVAL;
1450 }
f078f209 1451
3cbb5dd7 1452 ath9k_ps_restore(sc);
141b38b6
S		 1453 mutex_unlock(&sc->mutex);
1454
8feceb67
VT		 1455 return ret;
1456}
6c43c090
SM		 1457
1458static void ath9k_set_assoc_state(struct ath_softc *sc,
1459 struct ieee80211_vif *vif)
4f5ef75b 1460{
4f5ef75b 1461 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
4f5ef75b 1462 struct ath_vif *avp = (void *)vif->drv_priv;
6c43c090 1463 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
07c15a3f 1464 unsigned long flags;
6c43c090
SM		 1465
1466 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1467 avp->primary_sta_vif = true;
1468
2e5ef459 1469 /*
6c43c090
SM		 1470 * Set the AID, BSSID and do beacon-sync only when
1471 * the HW opmode is STATION.
1472 *
1473 * But the primary bit is set above in any case.
2e5ef459 1474 */
6c43c090 1475 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
2e5ef459
RM		 1476 return;
1477
6c43c090
SM		 1478 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1479 common->curaid = bss_conf->aid;
1480 ath9k_hw_write_associd(sc->sc_ah);
07c15a3f 1481
6c43c090
SM		 1482 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1483 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
99e4d43a 1484
6c43c090
SM		 1485 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1486 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1487 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
05c0be2f 1488
6c43c090
SM		 1489 ath_dbg(common, CONFIG,
1490 "Primary Station interface: %pM, BSSID: %pM\n",
1491 vif->addr, common->curbssid);
4f5ef75b
RM		 1492}
1493
6c43c090 1494static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
4f5ef75b 1495{
6c43c090 1496 struct ath_softc *sc = data;
4f5ef75b 1497 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
4f5ef75b 1498
6c43c090 1499 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
2e5ef459
RM		 1500 return;
1501
6c43c090
SM		 1502 if (bss_conf->assoc)
1503 ath9k_set_assoc_state(sc, vif);
4f5ef75b 1504}
f078f209 1505
8feceb67
VT		 1506static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1507 struct ieee80211_vif *vif,
1508 struct ieee80211_bss_conf *bss_conf,
1509 u32 changed)
1510{
da0d45f7
SM		 1511#define CHECK_ANI \
1512 (BSS_CHANGED_ASSOC | \
1513 BSS_CHANGED_IBSS | \
1514 BSS_CHANGED_BEACON_ENABLED)
1515
9ac58615 1516 struct ath_softc *sc = hw->priv;
2d0ddec5 1517 struct ath_hw *ah = sc->sc_ah;
1510718d 1518 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1519 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 1520 int slottime;
f078f209 1521
96f372c9 1522 ath9k_ps_wakeup(sc);
141b38b6
S		 1523 mutex_lock(&sc->mutex);
1524
9f61903c 1525 if (changed & BSS_CHANGED_ASSOC) {
6c43c090
SM		 1526 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1527 bss_conf->bssid, bss_conf->assoc);
1528
1529 if (avp->primary_sta_vif && !bss_conf->assoc) {
1530 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1531 avp->primary_sta_vif = false;
1532
1533 if (ah->opmode == NL80211_IFTYPE_STATION)
1534 clear_bit(SC_OP_BEACONS, &sc->sc_flags);
1535 }
1536
1537 ieee80211_iterate_active_interfaces_atomic(sc->hw,
1538 ath9k_bss_assoc_iter, sc);
2d0ddec5 1539
6c43c090
SM		 1540 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
1541 ah->opmode == NL80211_IFTYPE_STATION) {
1542 memset(common->curbssid, 0, ETH_ALEN);
1543 common->curaid = 0;
1544 ath9k_hw_write_associd(sc->sc_ah);
1545 }
c6089ccc 1546 }
2d0ddec5 1547
2e5ef459 1548 if (changed & BSS_CHANGED_IBSS) {
2e5ef459
RM		 1549 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1550 common->curaid = bss_conf->aid;
1551 ath9k_hw_write_associd(sc->sc_ah);
2e5ef459
RM		 1552 }
1553
ef4ad633
SM		 1554 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1555 (changed & BSS_CHANGED_BEACON_INT)) {
2f8e82e8
SM		 1556 if (ah->opmode == NL80211_IFTYPE_AP &&
1557 bss_conf->enable_beacon)
1558 ath9k_set_tsfadjust(sc, vif);
ef4ad633
SM		 1559 if (ath9k_allow_beacon_config(sc, vif))
1560 ath9k_beacon_config(sc, vif, changed);
0005baf4
FF		 1561 }
1562
1563 if (changed & BSS_CHANGED_ERP_SLOT) {
1564 if (bss_conf->use_short_slot)
1565 slottime = 9;
1566 else
1567 slottime = 20;
1568 if (vif->type == NL80211_IFTYPE_AP) {
1569 /*
1570 * Defer update, so that connected stations can adjust
1571 * their settings at the same time.
1572 * See beacon.c for more details
1573 */
1574 sc->beacon.slottime = slottime;
1575 sc->beacon.updateslot = UPDATE;
1576 } else {
1577 ah->slottime = slottime;
1578 ath9k_hw_init_global_settings(ah);
1579 }
2d0ddec5
JB		 1580 }
1581
da0d45f7
SM		 1582 if (changed & CHECK_ANI)
1583 ath_check_ani(sc);
1584
141b38b6 1585 mutex_unlock(&sc->mutex);
96f372c9 1586 ath9k_ps_restore(sc);
da0d45f7
SM		 1587
1588#undef CHECK_ANI
8feceb67 1589}
f078f209 1590
37a41b4a 1591static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1592{
9ac58615 1593 struct ath_softc *sc = hw->priv;
8feceb67 1594 u64 tsf;
f078f209 1595
141b38b6 1596 mutex_lock(&sc->mutex);
9abbfb27 1597 ath9k_ps_wakeup(sc);
141b38b6 1598 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 1599 ath9k_ps_restore(sc);
141b38b6 1600 mutex_unlock(&sc->mutex);
f078f209 1601
8feceb67
VT		 1602 return tsf;
1603}
f078f209 1604
37a41b4a
EP		 1605static void ath9k_set_tsf(struct ieee80211_hw *hw,
1606 struct ieee80211_vif *vif,
1607 u64 tsf)
3b5d665b 1608{
9ac58615 1609 struct ath_softc *sc = hw->priv;
3b5d665b 1610
141b38b6 1611 mutex_lock(&sc->mutex);
9abbfb27 1612 ath9k_ps_wakeup(sc);
141b38b6 1613 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 1614 ath9k_ps_restore(sc);
141b38b6 1615 mutex_unlock(&sc->mutex);
3b5d665b
AF		 1616}
1617
37a41b4a 1618static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1619{
9ac58615 1620 struct ath_softc *sc = hw->priv;
c83be688 1621
141b38b6 1622 mutex_lock(&sc->mutex);
21526d57
LR		 1623
1624 ath9k_ps_wakeup(sc);
141b38b6 1625 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR		 1626 ath9k_ps_restore(sc);
1627
141b38b6 1628 mutex_unlock(&sc->mutex);
8feceb67 1629}
f078f209 1630
8feceb67 1631static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 1632 struct ieee80211_vif *vif,
141b38b6
S		 1633 enum ieee80211_ampdu_mlme_action action,
1634 struct ieee80211_sta *sta,
0b01f030 1635 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 1636{
9ac58615 1637 struct ath_softc *sc = hw->priv;
8feceb67 1638 int ret = 0;
f078f209 1639
85ad181e
JB		 1640 local_bh_disable();
1641
8feceb67
VT		 1642 switch (action) {
1643 case IEEE80211_AMPDU_RX_START:
8feceb67
VT		 1644 break;
1645 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 1646 break;
1647 case IEEE80211_AMPDU_TX_START:
8b685ba9 1648 ath9k_ps_wakeup(sc);
231c3a1f
FF		 1649 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1650 if (!ret)
1651 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1652 ath9k_ps_restore(sc);
8feceb67
VT		 1653 break;
1654 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 1655 ath9k_ps_wakeup(sc);
f83da965 1656 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 1657 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1658 ath9k_ps_restore(sc);
8feceb67 1659 break;
b1720231 1660 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 1661 ath9k_ps_wakeup(sc);
8469cdef 1662 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 1663 ath9k_ps_restore(sc);
8469cdef 1664 break;
8feceb67 1665 default:
3800276a 1666 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT		 1667 }
1668
85ad181e
JB		 1669 local_bh_enable();
1670
8feceb67 1671 return ret;
f078f209
LR		 1672}
1673
62dad5b0
BP		 1674static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1675 struct survey_info *survey)
1676{
9ac58615 1677 struct ath_softc *sc = hw->priv;
3430098a 1678 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 1679 struct ieee80211_supported_band *sband;
3430098a
FF		 1680 struct ieee80211_channel *chan;
1681 unsigned long flags;
1682 int pos;
1683
1684 spin_lock_irqsave(&common->cc_lock, flags);
1685 if (idx == 0)
1686 ath_update_survey_stats(sc);
39162dbe
FF		 1687
1688 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1689 if (sband && idx >= sband->n_channels) {
1690 idx -= sband->n_channels;
1691 sband = NULL;
1692 }
62dad5b0 1693
39162dbe
FF		 1694 if (!sband)
1695 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 1696
3430098a
FF		 1697 if (!sband || idx >= sband->n_channels) {
1698 spin_unlock_irqrestore(&common->cc_lock, flags);
1699 return -ENOENT;
4f1a5a4b 1700 }
62dad5b0 1701
3430098a
FF		 1702 chan = &sband->channels[idx];
1703 pos = chan->hw_value;
1704 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1705 survey->channel = chan;
1706 spin_unlock_irqrestore(&common->cc_lock, flags);
1707
62dad5b0
BP		 1708 return 0;
1709}
1710
e239d859
FF		 1711static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
1712{
9ac58615 1713 struct ath_softc *sc = hw->priv;
e239d859
FF		 1714 struct ath_hw *ah = sc->sc_ah;
1715
1716 mutex_lock(&sc->mutex);
1717 ah->coverage_class = coverage_class;
8b2a3827
MSS		 1718
1719 ath9k_ps_wakeup(sc);
e239d859 1720 ath9k_hw_init_global_settings(ah);
8b2a3827
MSS		 1721 ath9k_ps_restore(sc);
1722
e239d859
FF		 1723 mutex_unlock(&sc->mutex);
1724}
1725
69081624
VT		 1726static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
1727{
69081624 1728 struct ath_softc *sc = hw->priv;
99aa55b6
MSS		 1729 struct ath_hw *ah = sc->sc_ah;
1730 struct ath_common *common = ath9k_hw_common(ah);
86271e46
FF		 1731 int timeout = 200; /* ms */
1732 int i, j;
2f6fc351 1733 bool drain_txq;
69081624
VT		 1734
1735 mutex_lock(&sc->mutex);
69081624
VT		 1736 cancel_delayed_work_sync(&sc->tx_complete_work);
1737
6a6b3f3e 1738 if (ah->ah_flags & AH_UNPLUGGED) {
d2182b69 1739 ath_dbg(common, ANY, "Device has been unplugged!\n");
6a6b3f3e
MSS		 1740 mutex_unlock(&sc->mutex);
1741 return;
1742 }
1743
781b14a3 1744 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
d2182b69 1745 ath_dbg(common, ANY, "Device not present\n");
99aa55b6
MSS		 1746 mutex_unlock(&sc->mutex);
1747 return;
1748 }
1749
86271e46 1750 for (j = 0; j < timeout; j++) {
108697c4 1751 bool npend = false;
86271e46
FF		 1752
1753 if (j)
1754 usleep_range(1000, 2000);
69081624 1755
86271e46
FF		 1756 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1757 if (!ATH_TXQ_SETUP(sc, i))
1758 continue;
1759
108697c4
MSS		 1760 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1761
1762 if (npend)
1763 break;
69081624 1764 }
86271e46
FF		 1765
1766 if (!npend)
9df0d6a2 1767 break;
69081624
VT		 1768 }
1769
9df0d6a2
FF		 1770 if (drop) {
1771 ath9k_ps_wakeup(sc);
1772 spin_lock_bh(&sc->sc_pcu_lock);
1773 drain_txq = ath_drain_all_txq(sc, false);
1774 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440 1775
9df0d6a2
FF		 1776 if (!drain_txq)
1777 ath_reset(sc, false);
9adcf440 1778
9df0d6a2
FF		 1779 ath9k_ps_restore(sc);
1780 ieee80211_wake_queues(hw);
1781 }
d78f4b3e 1782
69081624
VT		 1783 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
1784 mutex_unlock(&sc->mutex);
1785}
1786
15b91e83
VN		 1787static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
1788{
1789 struct ath_softc *sc = hw->priv;
1790 int i;
1791
1792 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1793 if (!ATH_TXQ_SETUP(sc, i))
1794 continue;
1795
1796 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
1797 return true;
1798 }
1799 return false;
1800}
1801
5595f119 1802static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
ba4903f9
FF		 1803{
1804 struct ath_softc *sc = hw->priv;
1805 struct ath_hw *ah = sc->sc_ah;
1806 struct ieee80211_vif *vif;
1807 struct ath_vif *avp;
1808 struct ath_buf *bf;
1809 struct ath_tx_status ts;
4286df60 1810 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
ba4903f9
FF		 1811 int status;
1812
1813 vif = sc->beacon.bslot[0];
1814 if (!vif)
1815 return 0;
1816
aa45fe96 1817 if (!vif->bss_conf.enable_beacon)
ba4903f9
FF		 1818 return 0;
1819
aa45fe96
SM		 1820 avp = (void *)vif->drv_priv;
1821
4286df60 1822 if (!sc->beacon.tx_processed && !edma) {
ba4903f9
FF		 1823 tasklet_disable(&sc->bcon_tasklet);
1824
1825 bf = avp->av_bcbuf;
1826 if (!bf || !bf->bf_mpdu)
1827 goto skip;
1828
1829 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
1830 if (status == -EINPROGRESS)
1831 goto skip;
1832
1833 sc->beacon.tx_processed = true;
1834 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
1835
1836skip:
1837 tasklet_enable(&sc->bcon_tasklet);
1838 }
1839
1840 return sc->beacon.tx_last;
1841}
1842
52c94f41
MSS		 1843static int ath9k_get_stats(struct ieee80211_hw *hw,
1844 struct ieee80211_low_level_stats *stats)
1845{
1846 struct ath_softc *sc = hw->priv;
1847 struct ath_hw *ah = sc->sc_ah;
1848 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
1849
1850 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
1851 stats->dot11RTSFailureCount = mib_stats->rts_bad;
1852 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
1853 stats->dot11RTSSuccessCount = mib_stats->rts_good;
1854 return 0;
1855}
1856
43c35284
FF		 1857static u32 fill_chainmask(u32 cap, u32 new)
1858{
1859 u32 filled = 0;
1860 int i;
1861
1862 for (i = 0; cap && new; i++, cap >>= 1) {
1863 if (!(cap & BIT(0)))
1864 continue;
1865
1866 if (new & BIT(0))
1867 filled |= BIT(i);
1868
1869 new >>= 1;
1870 }
1871
1872 return filled;
1873}
1874
5d9c7e3c
FF		 1875static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
1876{
1877 switch (val & 0x7) {
1878 case 0x1:
1879 case 0x3:
1880 case 0x7:
1881 return true;
1882 case 0x2:
1883 return (ah->caps.rx_chainmask == 1);
1884 default:
1885 return false;
1886 }
1887}
1888
43c35284
FF		 1889static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
1890{
1891 struct ath_softc *sc = hw->priv;
1892 struct ath_hw *ah = sc->sc_ah;
1893
5d9c7e3c
FF		 1894 if (ah->caps.rx_chainmask != 1)
1895 rx_ant |= tx_ant;
1896
1897 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
43c35284
FF		 1898 return -EINVAL;
1899
1900 sc->ant_rx = rx_ant;
1901 sc->ant_tx = tx_ant;
1902
1903 if (ah->caps.rx_chainmask == 1)
1904 return 0;
1905
1906 /* AR9100 runs into calibration issues if not all rx chains are enabled */
1907 if (AR_SREV_9100(ah))
1908 ah->rxchainmask = 0x7;
1909 else
1910 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
1911
1912 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
1913 ath9k_reload_chainmask_settings(sc);
1914
1915 return 0;
1916}
1917
1918static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
1919{
1920 struct ath_softc *sc = hw->priv;
1921
1922 *tx_ant = sc->ant_tx;
1923 *rx_ant = sc->ant_rx;
1924 return 0;
1925}
1926
b90bd9d1
BG		 1927#ifdef CONFIG_ATH9K_DEBUGFS
1928
1929/* Ethtool support for get-stats */
1930
1931#define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
1932static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
1933 "tx_pkts_nic",
1934 "tx_bytes_nic",
1935 "rx_pkts_nic",
1936 "rx_bytes_nic",
1937 AMKSTR(d_tx_pkts),
1938 AMKSTR(d_tx_bytes),
1939 AMKSTR(d_tx_mpdus_queued),
1940 AMKSTR(d_tx_mpdus_completed),
1941 AMKSTR(d_tx_mpdu_xretries),
1942 AMKSTR(d_tx_aggregates),
1943 AMKSTR(d_tx_ampdus_queued_hw),
1944 AMKSTR(d_tx_ampdus_queued_sw),
1945 AMKSTR(d_tx_ampdus_completed),
1946 AMKSTR(d_tx_ampdu_retries),
1947 AMKSTR(d_tx_ampdu_xretries),
1948 AMKSTR(d_tx_fifo_underrun),
1949 AMKSTR(d_tx_op_exceeded),
1950 AMKSTR(d_tx_timer_expiry),
1951 AMKSTR(d_tx_desc_cfg_err),
1952 AMKSTR(d_tx_data_underrun),
1953 AMKSTR(d_tx_delim_underrun),
1954
1955 "d_rx_decrypt_crc_err",
1956 "d_rx_phy_err",
1957 "d_rx_mic_err",
1958 "d_rx_pre_delim_crc_err",
1959 "d_rx_post_delim_crc_err",
1960 "d_rx_decrypt_busy_err",
1961
1962 "d_rx_phyerr_radar",
1963 "d_rx_phyerr_ofdm_timing",
1964 "d_rx_phyerr_cck_timing",
1965
1966};
1967#define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
1968
1969static void ath9k_get_et_strings(struct ieee80211_hw *hw,
1970 struct ieee80211_vif *vif,
1971 u32 sset, u8 *data)
1972{
1973 if (sset == ETH_SS_STATS)
1974 memcpy(data, *ath9k_gstrings_stats,
1975 sizeof(ath9k_gstrings_stats));
1976}
1977
1978static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
1979 struct ieee80211_vif *vif, int sset)
1980{
1981 if (sset == ETH_SS_STATS)
1982 return ATH9K_SSTATS_LEN;
1983 return 0;
1984}
1985
1986#define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
1987#define AWDATA(elem) \
1988 do { \
1989 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
1990 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
1991 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
1992 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
1993 } while (0)
1994
1995#define AWDATA_RX(elem) \
1996 do { \
1997 data[i++] = sc->debug.stats.rxstats.elem; \
1998 } while (0)
1999
2000static void ath9k_get_et_stats(struct ieee80211_hw *hw,
2001 struct ieee80211_vif *vif,
2002 struct ethtool_stats *stats, u64 *data)
2003{
2004 struct ath_softc *sc = hw->priv;
2005 int i = 0;
2006
2007 data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
2008 sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
2009 sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
2010 sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
2011 data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
2012 sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
2013 sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
2014 sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
2015 AWDATA_RX(rx_pkts_all);
2016 AWDATA_RX(rx_bytes_all);
2017
2018 AWDATA(tx_pkts_all);
2019 AWDATA(tx_bytes_all);
2020 AWDATA(queued);
2021 AWDATA(completed);
2022 AWDATA(xretries);
2023 AWDATA(a_aggr);
2024 AWDATA(a_queued_hw);
2025 AWDATA(a_queued_sw);
2026 AWDATA(a_completed);
2027 AWDATA(a_retries);
2028 AWDATA(a_xretries);
2029 AWDATA(fifo_underrun);
2030 AWDATA(xtxop);
2031 AWDATA(timer_exp);
2032 AWDATA(desc_cfg_err);
2033 AWDATA(data_underrun);
2034 AWDATA(delim_underrun);
2035
2036 AWDATA_RX(decrypt_crc_err);
2037 AWDATA_RX(phy_err);
2038 AWDATA_RX(mic_err);
2039 AWDATA_RX(pre_delim_crc_err);
2040 AWDATA_RX(post_delim_crc_err);
2041 AWDATA_RX(decrypt_busy_err);
2042
2043 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
2044 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
2045 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
2046
2047 WARN_ON(i != ATH9K_SSTATS_LEN);
2048}
2049
2050/* End of ethtool get-stats functions */
2051
2052#endif
2053
2054
b11e640a
MSS		 2055#ifdef CONFIG_PM_SLEEP
2056
2057static void ath9k_wow_map_triggers(struct ath_softc *sc,
2058 struct cfg80211_wowlan *wowlan,
2059 u32 *wow_triggers)
2060{
2061 if (wowlan->disconnect)
2062 *wow_triggers |= AH_WOW_LINK_CHANGE |
2063 AH_WOW_BEACON_MISS;
2064 if (wowlan->magic_pkt)
2065 *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
2066
2067 if (wowlan->n_patterns)
2068 *wow_triggers |= AH_WOW_USER_PATTERN_EN;
2069
2070 sc->wow_enabled = *wow_triggers;
2071
2072}
2073
2074static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
2075{
2076 struct ath_hw *ah = sc->sc_ah;
2077 struct ath_common *common = ath9k_hw_common(ah);
2078 struct ath9k_hw_capabilities *pcaps = &ah->caps;
2079 int pattern_count = 0;
2080 int i, byte_cnt;
2081 u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
2082 u8 dis_deauth_mask[MAX_PATTERN_SIZE];
2083
2084 memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
2085 memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
2086
2087 /*
2088 * Create Dissassociate / Deauthenticate packet filter
2089 *
2090 * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
2091 * +--------------+----------+---------+--------+--------+----
2092 * + Frame Control+ Duration + DA + SA + BSSID +
2093 * +--------------+----------+---------+--------+--------+----
2094 *
2095 * The above is the management frame format for disassociate/
2096 * deauthenticate pattern, from this we need to match the first byte
2097 * of 'Frame Control' and DA, SA, and BSSID fields
2098 * (skipping 2nd byte of FC and Duration feild.
2099 *
2100 * Disassociate pattern
2101 * --------------------
2102 * Frame control = 00 00 1010
2103 * DA, SA, BSSID = x:x:x:x:x:x
2104 * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2105 * | x:x:x:x:x:x -- 22 bytes
2106 *
2107 * Deauthenticate pattern
2108 * ----------------------
2109 * Frame control = 00 00 1100
2110 * DA, SA, BSSID = x:x:x:x:x:x
2111 * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2112 * | x:x:x:x:x:x -- 22 bytes
2113 */
2114
2115 /* Create Disassociate Pattern first */
2116
2117 byte_cnt = 0;
2118
2119 /* Fill out the mask with all FF's */
2120
2121 for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
2122 dis_deauth_mask[i] = 0xff;
2123
2124 /* copy the first byte of frame control field */
2125 dis_deauth_pattern[byte_cnt] = 0xa0;
2126 byte_cnt++;
2127
2128 /* skip 2nd byte of frame control and Duration field */
2129 byte_cnt += 3;
2130
2131 /*
2132 * need not match the destination mac address, it can be a broadcast
2133 * mac address or an unicast to this station
2134 */
2135 byte_cnt += 6;
2136
2137 /* copy the source mac address */
2138 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2139
2140 byte_cnt += 6;
2141
2142 /* copy the bssid, its same as the source mac address */
2143
2144 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2145
2146 /* Create Disassociate pattern mask */
2147
2148 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
2149
2150 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
2151 /*
2152 * for AR9280, because of hardware limitation, the
2153 * first 4 bytes have to be matched for all patterns.
2154 * the mask for disassociation and de-auth pattern
2155 * matching need to enable the first 4 bytes.
2156 * also the duration field needs to be filled.
2157 */
2158 dis_deauth_mask[0] = 0xf0;
2159
2160 /*
2161 * fill in duration field
2162 FIXME: what is the exact value ?
2163 */
2164 dis_deauth_pattern[2] = 0xff;
2165 dis_deauth_pattern[3] = 0xff;
2166 } else {
2167 dis_deauth_mask[0] = 0xfe;
2168 }
2169
2170 dis_deauth_mask[1] = 0x03;
2171 dis_deauth_mask[2] = 0xc0;
2172 } else {
2173 dis_deauth_mask[0] = 0xef;
2174 dis_deauth_mask[1] = 0x3f;
2175 dis_deauth_mask[2] = 0x00;
2176 dis_deauth_mask[3] = 0xfc;
2177 }
2178
2179 ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
2180
2181 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2182 pattern_count, byte_cnt);
2183
2184 pattern_count++;
2185 /*
2186 * for de-authenticate pattern, only the first byte of the frame
2187 * control field gets changed from 0xA0 to 0xC0
2188 */
2189 dis_deauth_pattern[0] = 0xC0;
2190
2191 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2192 pattern_count, byte_cnt);
2193
2194}
2195
2196static void ath9k_wow_add_pattern(struct ath_softc *sc,
2197 struct cfg80211_wowlan *wowlan)
2198{
2199 struct ath_hw *ah = sc->sc_ah;
2200 struct ath9k_wow_pattern *wow_pattern = NULL;
2201 struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
2202 int mask_len;
2203 s8 i = 0;
2204
2205 if (!wowlan->n_patterns)
2206 return;
2207
2208 /*
2209 * Add the new user configured patterns
2210 */
2211 for (i = 0; i < wowlan->n_patterns; i++) {
2212
2213 wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
2214
2215 if (!wow_pattern)
2216 return;
2217
2218 /*
2219 * TODO: convert the generic user space pattern to
2220 * appropriate chip specific/802.11 pattern.
2221 */
2222
2223 mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
2224 memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
2225 memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
2226 memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
2227 patterns[i].pattern_len);
2228 memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
2229 wow_pattern->pattern_len = patterns[i].pattern_len;
2230
2231 /*
2232 * just need to take care of deauth and disssoc pattern,
2233 * make sure we don't overwrite them.
2234 */
2235
2236 ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
2237 wow_pattern->mask_bytes,
2238 i + 2,
2239 wow_pattern->pattern_len);
2240 kfree(wow_pattern);
2241
2242 }
2243
2244}
2245
2246static int ath9k_suspend(struct ieee80211_hw *hw,
2247 struct cfg80211_wowlan *wowlan)
2248{
2249 struct ath_softc *sc = hw->priv;
2250 struct ath_hw *ah = sc->sc_ah;
2251 struct ath_common *common = ath9k_hw_common(ah);
2252 u32 wow_triggers_enabled = 0;
2253 int ret = 0;
2254
2255 mutex_lock(&sc->mutex);
2256
2257 ath_cancel_work(sc);
2258 del_timer_sync(&common->ani.timer);
2259 del_timer_sync(&sc->rx_poll_timer);
2260
2261 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
2262 ath_dbg(common, ANY, "Device not present\n");
2263 ret = -EINVAL;
2264 goto fail_wow;
2265 }
2266
2267 if (WARN_ON(!wowlan)) {
2268 ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
2269 ret = -EINVAL;
2270 goto fail_wow;
2271 }
2272
2273 if (!device_can_wakeup(sc->dev)) {
2274 ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
2275 ret = 1;
2276 goto fail_wow;
2277 }
2278
2279 /*
2280 * none of the sta vifs are associated
2281 * and we are not currently handling multivif
2282 * cases, for instance we have to seperately
2283 * configure 'keep alive frame' for each
2284 * STA.
2285 */
2286
2287 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
2288 ath_dbg(common, WOW, "None of the STA vifs are associated\n");
2289 ret = 1;
2290 goto fail_wow;
2291 }
2292
2293 if (sc->nvifs > 1) {
2294 ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
2295 ret = 1;
2296 goto fail_wow;
2297 }
2298
2299 ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
2300
2301 ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
2302 wow_triggers_enabled);
2303
2304 ath9k_ps_wakeup(sc);
2305
2306 ath9k_stop_btcoex(sc);
2307
2308 /*
2309 * Enable wake up on recieving disassoc/deauth
2310 * frame by default.
2311 */
2312 ath9k_wow_add_disassoc_deauth_pattern(sc);
2313
2314 if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
2315 ath9k_wow_add_pattern(sc, wowlan);
2316
2317 spin_lock_bh(&sc->sc_pcu_lock);
2318 /*
2319 * To avoid false wake, we enable beacon miss interrupt only
2320 * when we go to sleep. We save the current interrupt mask
2321 * so we can restore it after the system wakes up
2322 */
2323 sc->wow_intr_before_sleep = ah->imask;
2324 ah->imask &= ~ATH9K_INT_GLOBAL;
2325 ath9k_hw_disable_interrupts(ah);
2326 ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
2327 ath9k_hw_set_interrupts(ah);
2328 ath9k_hw_enable_interrupts(ah);
2329
2330 spin_unlock_bh(&sc->sc_pcu_lock);
2331
2332 /*
2333 * we can now sync irq and kill any running tasklets, since we already
2334 * disabled interrupts and not holding a spin lock
2335 */
2336 synchronize_irq(sc->irq);
2337 tasklet_kill(&sc->intr_tq);
2338
2339 ath9k_hw_wow_enable(ah, wow_triggers_enabled);
2340
2341 ath9k_ps_restore(sc);
2342 ath_dbg(common, ANY, "WoW enabled in ath9k\n");
2343 atomic_inc(&sc->wow_sleep_proc_intr);
2344
2345fail_wow:
2346 mutex_unlock(&sc->mutex);
2347 return ret;
2348}
2349
2350static int ath9k_resume(struct ieee80211_hw *hw)
2351{
2352 struct ath_softc *sc = hw->priv;
2353 struct ath_hw *ah = sc->sc_ah;
2354 struct ath_common *common = ath9k_hw_common(ah);
2355 u32 wow_status;
2356
2357 mutex_lock(&sc->mutex);
2358
2359 ath9k_ps_wakeup(sc);
2360
2361 spin_lock_bh(&sc->sc_pcu_lock);
2362
2363 ath9k_hw_disable_interrupts(ah);
2364 ah->imask = sc->wow_intr_before_sleep;
2365 ath9k_hw_set_interrupts(ah);
2366 ath9k_hw_enable_interrupts(ah);
2367
2368 spin_unlock_bh(&sc->sc_pcu_lock);
2369
2370 wow_status = ath9k_hw_wow_wakeup(ah);
2371
2372 if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
2373 /*
2374 * some devices may not pick beacon miss
2375 * as the reason they woke up so we add
2376 * that here for that shortcoming.
2377 */
2378 wow_status |= AH_WOW_BEACON_MISS;
2379 atomic_dec(&sc->wow_got_bmiss_intr);
2380 ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
2381 }
2382
2383 atomic_dec(&sc->wow_sleep_proc_intr);
2384
2385 if (wow_status) {
2386 ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
2387 ath9k_hw_wow_event_to_string(wow_status), wow_status);
2388 }
2389
2390 ath_restart_work(sc);
2391 ath9k_start_btcoex(sc);
2392
2393 ath9k_ps_restore(sc);
2394 mutex_unlock(&sc->mutex);
2395
2396 return 0;
2397}
2398
2399static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
2400{
2401 struct ath_softc *sc = hw->priv;
2402
2403 mutex_lock(&sc->mutex);
2404 device_init_wakeup(sc->dev, 1);
2405 device_set_wakeup_enable(sc->dev, enabled);
2406 mutex_unlock(&sc->mutex);
2407}
2408
2409#endif
2410
6baff7f9 2411struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2412 .tx = ath9k_tx,
2413 .start = ath9k_start,
2414 .stop = ath9k_stop,
2415 .add_interface = ath9k_add_interface,
6b3b991d 2416 .change_interface = ath9k_change_interface,
8feceb67
VT		 2417 .remove_interface = ath9k_remove_interface,
2418 .config = ath9k_config,
8feceb67 2419 .configure_filter = ath9k_configure_filter,
4ca77860
JB		 2420 .sta_add = ath9k_sta_add,
2421 .sta_remove = ath9k_sta_remove,
5519541d 2422 .sta_notify = ath9k_sta_notify,
8feceb67 2423 .conf_tx = ath9k_conf_tx,
8feceb67 2424 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2425 .set_key = ath9k_set_key,
8feceb67 2426 .get_tsf = ath9k_get_tsf,
3b5d665b 2427 .set_tsf = ath9k_set_tsf,
8feceb67 2428 .reset_tsf = ath9k_reset_tsf,
4233df6b 2429 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2430 .get_survey = ath9k_get_survey,
3b319aae 2431 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2432 .set_coverage_class = ath9k_set_coverage_class,
69081624 2433 .flush = ath9k_flush,
15b91e83 2434 .tx_frames_pending = ath9k_tx_frames_pending,
52c94f41
MSS		 2435 .tx_last_beacon = ath9k_tx_last_beacon,
2436 .get_stats = ath9k_get_stats,
43c35284
FF		 2437 .set_antenna = ath9k_set_antenna,
2438 .get_antenna = ath9k_get_antenna,
b90bd9d1 2439
b11e640a
MSS		 2440#ifdef CONFIG_PM_SLEEP
2441 .suspend = ath9k_suspend,
2442 .resume = ath9k_resume,
2443 .set_wakeup = ath9k_set_wakeup,
2444#endif
2445
b90bd9d1
BG		 2446#ifdef CONFIG_ATH9K_DEBUGFS
2447 .get_et_sset_count = ath9k_get_et_sset_count,
2448 .get_et_stats = ath9k_get_et_stats,
2449 .get_et_strings = ath9k_get_et_strings,
2450#endif
8feceb67 2451};
Linux kernel - Deliverables
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