Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
394cf0a1 | 18 | #include "ath9k.h" |
af03abec | 19 | #include "btcoex.h" |
f078f209 | 20 | |
f078f209 LR |
21 | static char *dev_info = "ath9k"; |
22 | ||
23 | MODULE_AUTHOR("Atheros Communications"); | |
24 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
25 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
26 | MODULE_LICENSE("Dual BSD/GPL"); | |
27 | ||
b3bd89ce JM |
28 | static int modparam_nohwcrypt; |
29 | module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); | |
30 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); | |
31 | ||
5f8e077c LR |
32 | /* We use the hw_value as an index into our private channel structure */ |
33 | ||
34 | #define CHAN2G(_freq, _idx) { \ | |
35 | .center_freq = (_freq), \ | |
36 | .hw_value = (_idx), \ | |
eeddfd9d | 37 | .max_power = 20, \ |
5f8e077c LR |
38 | } |
39 | ||
40 | #define CHAN5G(_freq, _idx) { \ | |
41 | .band = IEEE80211_BAND_5GHZ, \ | |
42 | .center_freq = (_freq), \ | |
43 | .hw_value = (_idx), \ | |
eeddfd9d | 44 | .max_power = 20, \ |
5f8e077c LR |
45 | } |
46 | ||
47 | /* Some 2 GHz radios are actually tunable on 2312-2732 | |
48 | * on 5 MHz steps, we support the channels which we know | |
49 | * we have calibration data for all cards though to make | |
50 | * this static */ | |
51 | static struct ieee80211_channel ath9k_2ghz_chantable[] = { | |
52 | CHAN2G(2412, 0), /* Channel 1 */ | |
53 | CHAN2G(2417, 1), /* Channel 2 */ | |
54 | CHAN2G(2422, 2), /* Channel 3 */ | |
55 | CHAN2G(2427, 3), /* Channel 4 */ | |
56 | CHAN2G(2432, 4), /* Channel 5 */ | |
57 | CHAN2G(2437, 5), /* Channel 6 */ | |
58 | CHAN2G(2442, 6), /* Channel 7 */ | |
59 | CHAN2G(2447, 7), /* Channel 8 */ | |
60 | CHAN2G(2452, 8), /* Channel 9 */ | |
61 | CHAN2G(2457, 9), /* Channel 10 */ | |
62 | CHAN2G(2462, 10), /* Channel 11 */ | |
63 | CHAN2G(2467, 11), /* Channel 12 */ | |
64 | CHAN2G(2472, 12), /* Channel 13 */ | |
65 | CHAN2G(2484, 13), /* Channel 14 */ | |
66 | }; | |
67 | ||
68 | /* Some 5 GHz radios are actually tunable on XXXX-YYYY | |
69 | * on 5 MHz steps, we support the channels which we know | |
70 | * we have calibration data for all cards though to make | |
71 | * this static */ | |
72 | static struct ieee80211_channel ath9k_5ghz_chantable[] = { | |
73 | /* _We_ call this UNII 1 */ | |
74 | CHAN5G(5180, 14), /* Channel 36 */ | |
75 | CHAN5G(5200, 15), /* Channel 40 */ | |
76 | CHAN5G(5220, 16), /* Channel 44 */ | |
77 | CHAN5G(5240, 17), /* Channel 48 */ | |
78 | /* _We_ call this UNII 2 */ | |
79 | CHAN5G(5260, 18), /* Channel 52 */ | |
80 | CHAN5G(5280, 19), /* Channel 56 */ | |
81 | CHAN5G(5300, 20), /* Channel 60 */ | |
82 | CHAN5G(5320, 21), /* Channel 64 */ | |
83 | /* _We_ call this "Middle band" */ | |
84 | CHAN5G(5500, 22), /* Channel 100 */ | |
85 | CHAN5G(5520, 23), /* Channel 104 */ | |
86 | CHAN5G(5540, 24), /* Channel 108 */ | |
87 | CHAN5G(5560, 25), /* Channel 112 */ | |
88 | CHAN5G(5580, 26), /* Channel 116 */ | |
89 | CHAN5G(5600, 27), /* Channel 120 */ | |
90 | CHAN5G(5620, 28), /* Channel 124 */ | |
91 | CHAN5G(5640, 29), /* Channel 128 */ | |
92 | CHAN5G(5660, 30), /* Channel 132 */ | |
93 | CHAN5G(5680, 31), /* Channel 136 */ | |
94 | CHAN5G(5700, 32), /* Channel 140 */ | |
95 | /* _We_ call this UNII 3 */ | |
96 | CHAN5G(5745, 33), /* Channel 149 */ | |
97 | CHAN5G(5765, 34), /* Channel 153 */ | |
98 | CHAN5G(5785, 35), /* Channel 157 */ | |
99 | CHAN5G(5805, 36), /* Channel 161 */ | |
100 | CHAN5G(5825, 37), /* Channel 165 */ | |
101 | }; | |
102 | ||
ce111bad LR |
103 | static void ath_cache_conf_rate(struct ath_softc *sc, |
104 | struct ieee80211_conf *conf) | |
ff37e337 | 105 | { |
030bb495 LR |
106 | switch (conf->channel->band) { |
107 | case IEEE80211_BAND_2GHZ: | |
108 | if (conf_is_ht20(conf)) | |
109 | sc->cur_rate_table = | |
110 | sc->hw_rate_table[ATH9K_MODE_11NG_HT20]; | |
111 | else if (conf_is_ht40_minus(conf)) | |
112 | sc->cur_rate_table = | |
113 | sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS]; | |
114 | else if (conf_is_ht40_plus(conf)) | |
115 | sc->cur_rate_table = | |
116 | sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS]; | |
96742256 | 117 | else |
030bb495 LR |
118 | sc->cur_rate_table = |
119 | sc->hw_rate_table[ATH9K_MODE_11G]; | |
030bb495 LR |
120 | break; |
121 | case IEEE80211_BAND_5GHZ: | |
122 | if (conf_is_ht20(conf)) | |
123 | sc->cur_rate_table = | |
124 | sc->hw_rate_table[ATH9K_MODE_11NA_HT20]; | |
125 | else if (conf_is_ht40_minus(conf)) | |
126 | sc->cur_rate_table = | |
127 | sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS]; | |
128 | else if (conf_is_ht40_plus(conf)) | |
129 | sc->cur_rate_table = | |
130 | sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS]; | |
131 | else | |
96742256 LR |
132 | sc->cur_rate_table = |
133 | sc->hw_rate_table[ATH9K_MODE_11A]; | |
030bb495 LR |
134 | break; |
135 | default: | |
ce111bad | 136 | BUG_ON(1); |
030bb495 LR |
137 | break; |
138 | } | |
ff37e337 S |
139 | } |
140 | ||
141 | static void ath_update_txpow(struct ath_softc *sc) | |
142 | { | |
cbe61d8a | 143 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
144 | u32 txpow; |
145 | ||
17d7904d S |
146 | if (sc->curtxpow != sc->config.txpowlimit) { |
147 | ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit); | |
ff37e337 S |
148 | /* read back in case value is clamped */ |
149 | ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow); | |
17d7904d | 150 | sc->curtxpow = txpow; |
ff37e337 S |
151 | } |
152 | } | |
153 | ||
154 | static u8 parse_mpdudensity(u8 mpdudensity) | |
155 | { | |
156 | /* | |
157 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
158 | * 0 for no restriction | |
159 | * 1 for 1/4 us | |
160 | * 2 for 1/2 us | |
161 | * 3 for 1 us | |
162 | * 4 for 2 us | |
163 | * 5 for 4 us | |
164 | * 6 for 8 us | |
165 | * 7 for 16 us | |
166 | */ | |
167 | switch (mpdudensity) { | |
168 | case 0: | |
169 | return 0; | |
170 | case 1: | |
171 | case 2: | |
172 | case 3: | |
173 | /* Our lower layer calculations limit our precision to | |
174 | 1 microsecond */ | |
175 | return 1; | |
176 | case 4: | |
177 | return 2; | |
178 | case 5: | |
179 | return 4; | |
180 | case 6: | |
181 | return 8; | |
182 | case 7: | |
183 | return 16; | |
184 | default: | |
185 | return 0; | |
186 | } | |
187 | } | |
188 | ||
189 | static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band) | |
190 | { | |
4f0fc7c3 | 191 | const struct ath_rate_table *rate_table = NULL; |
ff37e337 S |
192 | struct ieee80211_supported_band *sband; |
193 | struct ieee80211_rate *rate; | |
194 | int i, maxrates; | |
195 | ||
196 | switch (band) { | |
197 | case IEEE80211_BAND_2GHZ: | |
198 | rate_table = sc->hw_rate_table[ATH9K_MODE_11G]; | |
199 | break; | |
200 | case IEEE80211_BAND_5GHZ: | |
201 | rate_table = sc->hw_rate_table[ATH9K_MODE_11A]; | |
202 | break; | |
203 | default: | |
204 | break; | |
205 | } | |
206 | ||
207 | if (rate_table == NULL) | |
208 | return; | |
209 | ||
210 | sband = &sc->sbands[band]; | |
211 | rate = sc->rates[band]; | |
212 | ||
213 | if (rate_table->rate_cnt > ATH_RATE_MAX) | |
214 | maxrates = ATH_RATE_MAX; | |
215 | else | |
216 | maxrates = rate_table->rate_cnt; | |
217 | ||
218 | for (i = 0; i < maxrates; i++) { | |
219 | rate[i].bitrate = rate_table->info[i].ratekbps / 100; | |
220 | rate[i].hw_value = rate_table->info[i].ratecode; | |
f46730d1 S |
221 | if (rate_table->info[i].short_preamble) { |
222 | rate[i].hw_value_short = rate_table->info[i].ratecode | | |
223 | rate_table->info[i].short_preamble; | |
224 | rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE; | |
225 | } | |
ff37e337 | 226 | sband->n_bitrates++; |
f46730d1 | 227 | |
4d6b228d | 228 | DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n", |
04bd4638 | 229 | rate[i].bitrate / 10, rate[i].hw_value); |
ff37e337 S |
230 | } |
231 | } | |
232 | ||
82880a7c VT |
233 | static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc, |
234 | struct ieee80211_hw *hw) | |
235 | { | |
236 | struct ieee80211_channel *curchan = hw->conf.channel; | |
237 | struct ath9k_channel *channel; | |
238 | u8 chan_idx; | |
239 | ||
240 | chan_idx = curchan->hw_value; | |
241 | channel = &sc->sc_ah->channels[chan_idx]; | |
242 | ath9k_update_ichannel(sc, hw, channel); | |
243 | return channel; | |
244 | } | |
245 | ||
9ecdef4b | 246 | static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
247 | { |
248 | unsigned long flags; | |
249 | bool ret; | |
250 | ||
9ecdef4b LR |
251 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
252 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
253 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
254 | |
255 | return ret; | |
256 | } | |
257 | ||
a91d75ae LR |
258 | void ath9k_ps_wakeup(struct ath_softc *sc) |
259 | { | |
260 | unsigned long flags; | |
261 | ||
262 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
263 | if (++sc->ps_usecount != 1) | |
264 | goto unlock; | |
265 | ||
9ecdef4b | 266 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae LR |
267 | |
268 | unlock: | |
269 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
270 | } | |
271 | ||
272 | void ath9k_ps_restore(struct ath_softc *sc) | |
273 | { | |
274 | unsigned long flags; | |
275 | ||
276 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
277 | if (--sc->ps_usecount != 0) | |
278 | goto unlock; | |
279 | ||
280 | if (sc->ps_enabled && | |
281 | !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | | |
282 | SC_OP_WAIT_FOR_CAB | | |
283 | SC_OP_WAIT_FOR_PSPOLL_DATA | | |
284 | SC_OP_WAIT_FOR_TX_ACK))) | |
9ecdef4b | 285 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); |
a91d75ae LR |
286 | |
287 | unlock: | |
288 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
289 | } | |
290 | ||
ff37e337 S |
291 | /* |
292 | * Set/change channels. If the channel is really being changed, it's done | |
293 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
294 | * DMA, then restart stuff. | |
295 | */ | |
0e2dedf9 JM |
296 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, |
297 | struct ath9k_channel *hchan) | |
ff37e337 | 298 | { |
cbe61d8a | 299 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 | 300 | bool fastcc = true, stopped; |
ae8d2858 LR |
301 | struct ieee80211_channel *channel = hw->conf.channel; |
302 | int r; | |
ff37e337 S |
303 | |
304 | if (sc->sc_flags & SC_OP_INVALID) | |
305 | return -EIO; | |
306 | ||
3cbb5dd7 VN |
307 | ath9k_ps_wakeup(sc); |
308 | ||
c0d7c7af LR |
309 | /* |
310 | * This is only performed if the channel settings have | |
311 | * actually changed. | |
312 | * | |
313 | * To switch channels clear any pending DMA operations; | |
314 | * wait long enough for the RX fifo to drain, reset the | |
315 | * hardware at the new frequency, and then re-enable | |
316 | * the relevant bits of the h/w. | |
317 | */ | |
318 | ath9k_hw_set_interrupts(ah, 0); | |
043a0405 | 319 | ath_drain_all_txq(sc, false); |
c0d7c7af | 320 | stopped = ath_stoprecv(sc); |
ff37e337 | 321 | |
c0d7c7af LR |
322 | /* XXX: do not flush receive queue here. We don't want |
323 | * to flush data frames already in queue because of | |
324 | * changing channel. */ | |
ff37e337 | 325 | |
c0d7c7af LR |
326 | if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET)) |
327 | fastcc = false; | |
328 | ||
4d6b228d | 329 | DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, |
c0d7c7af | 330 | "(%u MHz) -> (%u MHz), chanwidth: %d\n", |
2660b81a | 331 | sc->sc_ah->curchan->channel, |
c0d7c7af | 332 | channel->center_freq, sc->tx_chan_width); |
ff37e337 | 333 | |
c0d7c7af LR |
334 | spin_lock_bh(&sc->sc_resetlock); |
335 | ||
336 | r = ath9k_hw_reset(ah, hchan, fastcc); | |
337 | if (r) { | |
4d6b228d | 338 | DPRINTF(sc->sc_ah, ATH_DBG_FATAL, |
c0d7c7af | 339 | "Unable to reset channel (%u Mhz) " |
6b45784f | 340 | "reset status %d\n", |
c0d7c7af LR |
341 | channel->center_freq, r); |
342 | spin_unlock_bh(&sc->sc_resetlock); | |
3989279c | 343 | goto ps_restore; |
ff37e337 | 344 | } |
c0d7c7af LR |
345 | spin_unlock_bh(&sc->sc_resetlock); |
346 | ||
c0d7c7af LR |
347 | sc->sc_flags &= ~SC_OP_FULL_RESET; |
348 | ||
349 | if (ath_startrecv(sc) != 0) { | |
4d6b228d | 350 | DPRINTF(sc->sc_ah, ATH_DBG_FATAL, |
c0d7c7af | 351 | "Unable to restart recv logic\n"); |
3989279c GJ |
352 | r = -EIO; |
353 | goto ps_restore; | |
c0d7c7af LR |
354 | } |
355 | ||
356 | ath_cache_conf_rate(sc, &hw->conf); | |
357 | ath_update_txpow(sc); | |
17d7904d | 358 | ath9k_hw_set_interrupts(ah, sc->imask); |
3989279c GJ |
359 | |
360 | ps_restore: | |
3cbb5dd7 | 361 | ath9k_ps_restore(sc); |
3989279c | 362 | return r; |
ff37e337 S |
363 | } |
364 | ||
365 | /* | |
366 | * This routine performs the periodic noise floor calibration function | |
367 | * that is used to adjust and optimize the chip performance. This | |
368 | * takes environmental changes (location, temperature) into account. | |
369 | * When the task is complete, it reschedules itself depending on the | |
370 | * appropriate interval that was calculated. | |
371 | */ | |
372 | static void ath_ani_calibrate(unsigned long data) | |
373 | { | |
20977d3e S |
374 | struct ath_softc *sc = (struct ath_softc *)data; |
375 | struct ath_hw *ah = sc->sc_ah; | |
ff37e337 S |
376 | bool longcal = false; |
377 | bool shortcal = false; | |
378 | bool aniflag = false; | |
379 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
20977d3e | 380 | u32 cal_interval, short_cal_interval; |
ff37e337 | 381 | |
20977d3e S |
382 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
383 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 S |
384 | |
385 | /* | |
386 | * don't calibrate when we're scanning. | |
387 | * we are most likely not on our home channel. | |
388 | */ | |
e5f0921a | 389 | spin_lock(&sc->ani_lock); |
0c98de65 | 390 | if (sc->sc_flags & SC_OP_SCANNING) |
20977d3e | 391 | goto set_timer; |
ff37e337 | 392 | |
1ffc1c61 JM |
393 | /* Only calibrate if awake */ |
394 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
395 | goto set_timer; | |
396 | ||
397 | ath9k_ps_wakeup(sc); | |
398 | ||
ff37e337 | 399 | /* Long calibration runs independently of short calibration. */ |
17d7904d | 400 | if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { |
ff37e337 | 401 | longcal = true; |
4d6b228d | 402 | DPRINTF(sc->sc_ah, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
17d7904d | 403 | sc->ani.longcal_timer = timestamp; |
ff37e337 S |
404 | } |
405 | ||
17d7904d S |
406 | /* Short calibration applies only while caldone is false */ |
407 | if (!sc->ani.caldone) { | |
20977d3e | 408 | if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) { |
ff37e337 | 409 | shortcal = true; |
4d6b228d | 410 | DPRINTF(sc->sc_ah, ATH_DBG_ANI, "shortcal @%lu\n", jiffies); |
17d7904d S |
411 | sc->ani.shortcal_timer = timestamp; |
412 | sc->ani.resetcal_timer = timestamp; | |
ff37e337 S |
413 | } |
414 | } else { | |
17d7904d | 415 | if ((timestamp - sc->ani.resetcal_timer) >= |
ff37e337 | 416 | ATH_RESTART_CALINTERVAL) { |
17d7904d S |
417 | sc->ani.caldone = ath9k_hw_reset_calvalid(ah); |
418 | if (sc->ani.caldone) | |
419 | sc->ani.resetcal_timer = timestamp; | |
ff37e337 S |
420 | } |
421 | } | |
422 | ||
423 | /* Verify whether we must check ANI */ | |
20977d3e | 424 | if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) { |
ff37e337 | 425 | aniflag = true; |
17d7904d | 426 | sc->ani.checkani_timer = timestamp; |
ff37e337 S |
427 | } |
428 | ||
429 | /* Skip all processing if there's nothing to do. */ | |
430 | if (longcal || shortcal || aniflag) { | |
431 | /* Call ANI routine if necessary */ | |
432 | if (aniflag) | |
22e66a4c | 433 | ath9k_hw_ani_monitor(ah, ah->curchan); |
ff37e337 S |
434 | |
435 | /* Perform calibration if necessary */ | |
436 | if (longcal || shortcal) { | |
379f0440 S |
437 | sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan, |
438 | sc->rx_chainmask, longcal); | |
439 | ||
440 | if (longcal) | |
441 | sc->ani.noise_floor = ath9k_hw_getchan_noise(ah, | |
442 | ah->curchan); | |
443 | ||
4d6b228d | 444 | DPRINTF(sc->sc_ah, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n", |
379f0440 S |
445 | ah->curchan->channel, ah->curchan->channelFlags, |
446 | sc->ani.noise_floor); | |
ff37e337 S |
447 | } |
448 | } | |
449 | ||
1ffc1c61 JM |
450 | ath9k_ps_restore(sc); |
451 | ||
20977d3e | 452 | set_timer: |
e5f0921a | 453 | spin_unlock(&sc->ani_lock); |
ff37e337 S |
454 | /* |
455 | * Set timer interval based on previous results. | |
456 | * The interval must be the shortest necessary to satisfy ANI, | |
457 | * short calibration and long calibration. | |
458 | */ | |
aac9207e | 459 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 460 | if (sc->sc_ah->config.enable_ani) |
aac9207e | 461 | cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL); |
17d7904d | 462 | if (!sc->ani.caldone) |
20977d3e | 463 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 464 | |
17d7904d | 465 | mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
ff37e337 S |
466 | } |
467 | ||
415f738e S |
468 | static void ath_start_ani(struct ath_softc *sc) |
469 | { | |
470 | unsigned long timestamp = jiffies_to_msecs(jiffies); | |
471 | ||
472 | sc->ani.longcal_timer = timestamp; | |
473 | sc->ani.shortcal_timer = timestamp; | |
474 | sc->ani.checkani_timer = timestamp; | |
475 | ||
476 | mod_timer(&sc->ani.timer, | |
477 | jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL)); | |
478 | } | |
479 | ||
ff37e337 S |
480 | /* |
481 | * Update tx/rx chainmask. For legacy association, | |
482 | * hard code chainmask to 1x1, for 11n association, use | |
c97c92d9 VT |
483 | * the chainmask configuration, for bt coexistence, use |
484 | * the chainmask configuration even in legacy mode. | |
ff37e337 | 485 | */ |
0e2dedf9 | 486 | void ath_update_chainmask(struct ath_softc *sc, int is_ht) |
ff37e337 | 487 | { |
af03abec LR |
488 | struct ath_hw *ah = sc->sc_ah; |
489 | ||
3d832611 | 490 | if ((sc->sc_flags & SC_OP_SCANNING) || is_ht || |
766ec4a9 | 491 | (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) { |
2660b81a S |
492 | sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask; |
493 | sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask; | |
ff37e337 | 494 | } else { |
17d7904d S |
495 | sc->tx_chainmask = 1; |
496 | sc->rx_chainmask = 1; | |
ff37e337 S |
497 | } |
498 | ||
af03abec | 499 | DPRINTF(ah, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n", |
17d7904d | 500 | sc->tx_chainmask, sc->rx_chainmask); |
ff37e337 S |
501 | } |
502 | ||
503 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
504 | { | |
505 | struct ath_node *an; | |
506 | ||
507 | an = (struct ath_node *)sta->drv_priv; | |
508 | ||
87792efc | 509 | if (sc->sc_flags & SC_OP_TXAGGR) { |
ff37e337 | 510 | ath_tx_node_init(sc, an); |
9e98ac65 | 511 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc S |
512 | sta->ht_cap.ampdu_factor); |
513 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
a59b5a5e | 514 | an->last_rssi = ATH_RSSI_DUMMY_MARKER; |
87792efc | 515 | } |
ff37e337 S |
516 | } |
517 | ||
518 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
519 | { | |
520 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
521 | ||
522 | if (sc->sc_flags & SC_OP_TXAGGR) | |
523 | ath_tx_node_cleanup(sc, an); | |
524 | } | |
525 | ||
526 | static void ath9k_tasklet(unsigned long data) | |
527 | { | |
528 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec LR |
529 | struct ath_hw *ah = sc->sc_ah; |
530 | ||
17d7904d | 531 | u32 status = sc->intrstatus; |
ff37e337 | 532 | |
153e080d VT |
533 | ath9k_ps_wakeup(sc); |
534 | ||
ff37e337 | 535 | if (status & ATH9K_INT_FATAL) { |
ff37e337 | 536 | ath_reset(sc, false); |
153e080d | 537 | ath9k_ps_restore(sc); |
ff37e337 | 538 | return; |
063d8be3 | 539 | } |
ff37e337 | 540 | |
063d8be3 S |
541 | if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) { |
542 | spin_lock_bh(&sc->rx.rxflushlock); | |
543 | ath_rx_tasklet(sc, 0); | |
544 | spin_unlock_bh(&sc->rx.rxflushlock); | |
ff37e337 S |
545 | } |
546 | ||
063d8be3 S |
547 | if (status & ATH9K_INT_TX) |
548 | ath_tx_tasklet(sc); | |
549 | ||
96148326 | 550 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
54ce846e JM |
551 | /* |
552 | * TSF sync does not look correct; remain awake to sync with | |
553 | * the next Beacon. | |
554 | */ | |
af03abec | 555 | DPRINTF(ah, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n"); |
ccdfeab6 | 556 | sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC; |
54ce846e JM |
557 | } |
558 | ||
766ec4a9 | 559 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
ebb8e1d7 VT |
560 | if (status & ATH9K_INT_GENTIMER) |
561 | ath_gen_timer_isr(sc->sc_ah); | |
562 | ||
ff37e337 | 563 | /* re-enable hardware interrupt */ |
af03abec | 564 | ath9k_hw_set_interrupts(ah, sc->imask); |
153e080d | 565 | ath9k_ps_restore(sc); |
ff37e337 S |
566 | } |
567 | ||
6baff7f9 | 568 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 569 | { |
063d8be3 S |
570 | #define SCHED_INTR ( \ |
571 | ATH9K_INT_FATAL | \ | |
572 | ATH9K_INT_RXORN | \ | |
573 | ATH9K_INT_RXEOL | \ | |
574 | ATH9K_INT_RX | \ | |
575 | ATH9K_INT_TX | \ | |
576 | ATH9K_INT_BMISS | \ | |
577 | ATH9K_INT_CST | \ | |
ebb8e1d7 VT |
578 | ATH9K_INT_TSFOOR | \ |
579 | ATH9K_INT_GENTIMER) | |
063d8be3 | 580 | |
ff37e337 | 581 | struct ath_softc *sc = dev; |
cbe61d8a | 582 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
583 | enum ath9k_int status; |
584 | bool sched = false; | |
585 | ||
063d8be3 S |
586 | /* |
587 | * The hardware is not ready/present, don't | |
588 | * touch anything. Note this can happen early | |
589 | * on if the IRQ is shared. | |
590 | */ | |
591 | if (sc->sc_flags & SC_OP_INVALID) | |
592 | return IRQ_NONE; | |
ff37e337 | 593 | |
063d8be3 S |
594 | |
595 | /* shared irq, not for us */ | |
596 | ||
153e080d | 597 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 598 | return IRQ_NONE; |
063d8be3 S |
599 | |
600 | /* | |
601 | * Figure out the reason(s) for the interrupt. Note | |
602 | * that the hal returns a pseudo-ISR that may include | |
603 | * bits we haven't explicitly enabled so we mask the | |
604 | * value to insure we only process bits we requested. | |
605 | */ | |
606 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
607 | status &= sc->imask; /* discard unasked-for bits */ | |
ff37e337 | 608 | |
063d8be3 S |
609 | /* |
610 | * If there are no status bits set, then this interrupt was not | |
611 | * for me (should have been caught above). | |
612 | */ | |
153e080d | 613 | if (!status) |
063d8be3 | 614 | return IRQ_NONE; |
ff37e337 | 615 | |
063d8be3 S |
616 | /* Cache the status */ |
617 | sc->intrstatus = status; | |
618 | ||
619 | if (status & SCHED_INTR) | |
620 | sched = true; | |
621 | ||
622 | /* | |
623 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
624 | * chip immediately. | |
625 | */ | |
626 | if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN)) | |
627 | goto chip_reset; | |
628 | ||
629 | if (status & ATH9K_INT_SWBA) | |
630 | tasklet_schedule(&sc->bcon_tasklet); | |
631 | ||
632 | if (status & ATH9K_INT_TXURN) | |
633 | ath9k_hw_updatetxtriglevel(ah, true); | |
634 | ||
635 | if (status & ATH9K_INT_MIB) { | |
ff37e337 | 636 | /* |
063d8be3 S |
637 | * Disable interrupts until we service the MIB |
638 | * interrupt; otherwise it will continue to | |
639 | * fire. | |
ff37e337 | 640 | */ |
063d8be3 S |
641 | ath9k_hw_set_interrupts(ah, 0); |
642 | /* | |
643 | * Let the hal handle the event. We assume | |
644 | * it will clear whatever condition caused | |
645 | * the interrupt. | |
646 | */ | |
22e66a4c | 647 | ath9k_hw_procmibevent(ah); |
063d8be3 S |
648 | ath9k_hw_set_interrupts(ah, sc->imask); |
649 | } | |
ff37e337 | 650 | |
153e080d VT |
651 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
652 | if (status & ATH9K_INT_TIM_TIMER) { | |
063d8be3 S |
653 | /* Clear RxAbort bit so that we can |
654 | * receive frames */ | |
9ecdef4b | 655 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
153e080d | 656 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
063d8be3 | 657 | sc->sc_flags |= SC_OP_WAIT_FOR_BEACON; |
ff37e337 | 658 | } |
063d8be3 S |
659 | |
660 | chip_reset: | |
ff37e337 | 661 | |
817e11de S |
662 | ath_debug_stat_interrupt(sc, status); |
663 | ||
ff37e337 S |
664 | if (sched) { |
665 | /* turn off every interrupt except SWBA */ | |
17d7904d | 666 | ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA)); |
ff37e337 S |
667 | tasklet_schedule(&sc->intr_tq); |
668 | } | |
669 | ||
670 | return IRQ_HANDLED; | |
063d8be3 S |
671 | |
672 | #undef SCHED_INTR | |
ff37e337 S |
673 | } |
674 | ||
f078f209 | 675 | static u32 ath_get_extchanmode(struct ath_softc *sc, |
99405f93 | 676 | struct ieee80211_channel *chan, |
094d05dc | 677 | enum nl80211_channel_type channel_type) |
f078f209 LR |
678 | { |
679 | u32 chanmode = 0; | |
f078f209 LR |
680 | |
681 | switch (chan->band) { | |
682 | case IEEE80211_BAND_2GHZ: | |
094d05dc S |
683 | switch(channel_type) { |
684 | case NL80211_CHAN_NO_HT: | |
685 | case NL80211_CHAN_HT20: | |
f078f209 | 686 | chanmode = CHANNEL_G_HT20; |
094d05dc S |
687 | break; |
688 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 689 | chanmode = CHANNEL_G_HT40PLUS; |
094d05dc S |
690 | break; |
691 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 692 | chanmode = CHANNEL_G_HT40MINUS; |
094d05dc S |
693 | break; |
694 | } | |
f078f209 LR |
695 | break; |
696 | case IEEE80211_BAND_5GHZ: | |
094d05dc S |
697 | switch(channel_type) { |
698 | case NL80211_CHAN_NO_HT: | |
699 | case NL80211_CHAN_HT20: | |
f078f209 | 700 | chanmode = CHANNEL_A_HT20; |
094d05dc S |
701 | break; |
702 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 703 | chanmode = CHANNEL_A_HT40PLUS; |
094d05dc S |
704 | break; |
705 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 706 | chanmode = CHANNEL_A_HT40MINUS; |
094d05dc S |
707 | break; |
708 | } | |
f078f209 LR |
709 | break; |
710 | default: | |
711 | break; | |
712 | } | |
713 | ||
714 | return chanmode; | |
715 | } | |
716 | ||
6ace2891 | 717 | static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key, |
3f53dd64 JM |
718 | struct ath9k_keyval *hk, const u8 *addr, |
719 | bool authenticator) | |
f078f209 | 720 | { |
6ace2891 JM |
721 | const u8 *key_rxmic; |
722 | const u8 *key_txmic; | |
f078f209 | 723 | |
6ace2891 JM |
724 | key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY; |
725 | key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY; | |
f078f209 LR |
726 | |
727 | if (addr == NULL) { | |
d216aaa6 JM |
728 | /* |
729 | * Group key installation - only two key cache entries are used | |
730 | * regardless of splitmic capability since group key is only | |
731 | * used either for TX or RX. | |
732 | */ | |
3f53dd64 JM |
733 | if (authenticator) { |
734 | memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); | |
735 | memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic)); | |
736 | } else { | |
737 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); | |
738 | memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic)); | |
739 | } | |
d216aaa6 | 740 | return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr); |
f078f209 | 741 | } |
17d7904d | 742 | if (!sc->splitmic) { |
d216aaa6 | 743 | /* TX and RX keys share the same key cache entry. */ |
f078f209 LR |
744 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); |
745 | memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic)); | |
d216aaa6 | 746 | return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr); |
f078f209 | 747 | } |
d216aaa6 JM |
748 | |
749 | /* Separate key cache entries for TX and RX */ | |
750 | ||
751 | /* TX key goes at first index, RX key at +32. */ | |
f078f209 | 752 | memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); |
d216aaa6 JM |
753 | if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) { |
754 | /* TX MIC entry failed. No need to proceed further */ | |
4d6b228d | 755 | DPRINTF(sc->sc_ah, ATH_DBG_FATAL, |
04bd4638 | 756 | "Setting TX MIC Key Failed\n"); |
f078f209 LR |
757 | return 0; |
758 | } | |
759 | ||
760 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); | |
761 | /* XXX delete tx key on failure? */ | |
d216aaa6 | 762 | return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr); |
6ace2891 JM |
763 | } |
764 | ||
765 | static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc) | |
766 | { | |
767 | int i; | |
768 | ||
17d7904d S |
769 | for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) { |
770 | if (test_bit(i, sc->keymap) || | |
771 | test_bit(i + 64, sc->keymap)) | |
6ace2891 | 772 | continue; /* At least one part of TKIP key allocated */ |
17d7904d S |
773 | if (sc->splitmic && |
774 | (test_bit(i + 32, sc->keymap) || | |
775 | test_bit(i + 64 + 32, sc->keymap))) | |
6ace2891 JM |
776 | continue; /* At least one part of TKIP key allocated */ |
777 | ||
778 | /* Found a free slot for a TKIP key */ | |
779 | return i; | |
780 | } | |
781 | return -1; | |
782 | } | |
783 | ||
784 | static int ath_reserve_key_cache_slot(struct ath_softc *sc) | |
785 | { | |
786 | int i; | |
787 | ||
788 | /* First, try to find slots that would not be available for TKIP. */ | |
17d7904d S |
789 | if (sc->splitmic) { |
790 | for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) { | |
791 | if (!test_bit(i, sc->keymap) && | |
792 | (test_bit(i + 32, sc->keymap) || | |
793 | test_bit(i + 64, sc->keymap) || | |
794 | test_bit(i + 64 + 32, sc->keymap))) | |
6ace2891 | 795 | return i; |
17d7904d S |
796 | if (!test_bit(i + 32, sc->keymap) && |
797 | (test_bit(i, sc->keymap) || | |
798 | test_bit(i + 64, sc->keymap) || | |
799 | test_bit(i + 64 + 32, sc->keymap))) | |
6ace2891 | 800 | return i + 32; |
17d7904d S |
801 | if (!test_bit(i + 64, sc->keymap) && |
802 | (test_bit(i , sc->keymap) || | |
803 | test_bit(i + 32, sc->keymap) || | |
804 | test_bit(i + 64 + 32, sc->keymap))) | |
ea612132 | 805 | return i + 64; |
17d7904d S |
806 | if (!test_bit(i + 64 + 32, sc->keymap) && |
807 | (test_bit(i, sc->keymap) || | |
808 | test_bit(i + 32, sc->keymap) || | |
809 | test_bit(i + 64, sc->keymap))) | |
ea612132 | 810 | return i + 64 + 32; |
6ace2891 JM |
811 | } |
812 | } else { | |
17d7904d S |
813 | for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) { |
814 | if (!test_bit(i, sc->keymap) && | |
815 | test_bit(i + 64, sc->keymap)) | |
6ace2891 | 816 | return i; |
17d7904d S |
817 | if (test_bit(i, sc->keymap) && |
818 | !test_bit(i + 64, sc->keymap)) | |
6ace2891 JM |
819 | return i + 64; |
820 | } | |
821 | } | |
822 | ||
823 | /* No partially used TKIP slots, pick any available slot */ | |
17d7904d | 824 | for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) { |
be2864cf JM |
825 | /* Do not allow slots that could be needed for TKIP group keys |
826 | * to be used. This limitation could be removed if we know that | |
827 | * TKIP will not be used. */ | |
828 | if (i >= 64 && i < 64 + IEEE80211_WEP_NKID) | |
829 | continue; | |
17d7904d | 830 | if (sc->splitmic) { |
be2864cf JM |
831 | if (i >= 32 && i < 32 + IEEE80211_WEP_NKID) |
832 | continue; | |
833 | if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID) | |
834 | continue; | |
835 | } | |
836 | ||
17d7904d | 837 | if (!test_bit(i, sc->keymap)) |
6ace2891 JM |
838 | return i; /* Found a free slot for a key */ |
839 | } | |
840 | ||
841 | /* No free slot found */ | |
842 | return -1; | |
f078f209 LR |
843 | } |
844 | ||
845 | static int ath_key_config(struct ath_softc *sc, | |
3f53dd64 | 846 | struct ieee80211_vif *vif, |
dc822b5d | 847 | struct ieee80211_sta *sta, |
f078f209 LR |
848 | struct ieee80211_key_conf *key) |
849 | { | |
f078f209 LR |
850 | struct ath9k_keyval hk; |
851 | const u8 *mac = NULL; | |
852 | int ret = 0; | |
6ace2891 | 853 | int idx; |
f078f209 LR |
854 | |
855 | memset(&hk, 0, sizeof(hk)); | |
856 | ||
857 | switch (key->alg) { | |
858 | case ALG_WEP: | |
859 | hk.kv_type = ATH9K_CIPHER_WEP; | |
860 | break; | |
861 | case ALG_TKIP: | |
862 | hk.kv_type = ATH9K_CIPHER_TKIP; | |
863 | break; | |
864 | case ALG_CCMP: | |
865 | hk.kv_type = ATH9K_CIPHER_AES_CCM; | |
866 | break; | |
867 | default: | |
ca470b29 | 868 | return -EOPNOTSUPP; |
f078f209 LR |
869 | } |
870 | ||
6ace2891 | 871 | hk.kv_len = key->keylen; |
f078f209 LR |
872 | memcpy(hk.kv_val, key->key, key->keylen); |
873 | ||
6ace2891 JM |
874 | if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { |
875 | /* For now, use the default keys for broadcast keys. This may | |
876 | * need to change with virtual interfaces. */ | |
877 | idx = key->keyidx; | |
878 | } else if (key->keyidx) { | |
dc822b5d JB |
879 | if (WARN_ON(!sta)) |
880 | return -EOPNOTSUPP; | |
881 | mac = sta->addr; | |
882 | ||
6ace2891 JM |
883 | if (vif->type != NL80211_IFTYPE_AP) { |
884 | /* Only keyidx 0 should be used with unicast key, but | |
885 | * allow this for client mode for now. */ | |
886 | idx = key->keyidx; | |
887 | } else | |
888 | return -EIO; | |
f078f209 | 889 | } else { |
dc822b5d JB |
890 | if (WARN_ON(!sta)) |
891 | return -EOPNOTSUPP; | |
892 | mac = sta->addr; | |
893 | ||
6ace2891 JM |
894 | if (key->alg == ALG_TKIP) |
895 | idx = ath_reserve_key_cache_slot_tkip(sc); | |
896 | else | |
897 | idx = ath_reserve_key_cache_slot(sc); | |
898 | if (idx < 0) | |
ca470b29 | 899 | return -ENOSPC; /* no free key cache entries */ |
f078f209 LR |
900 | } |
901 | ||
902 | if (key->alg == ALG_TKIP) | |
3f53dd64 JM |
903 | ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac, |
904 | vif->type == NL80211_IFTYPE_AP); | |
f078f209 | 905 | else |
d216aaa6 | 906 | ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac); |
f078f209 LR |
907 | |
908 | if (!ret) | |
909 | return -EIO; | |
910 | ||
17d7904d | 911 | set_bit(idx, sc->keymap); |
6ace2891 | 912 | if (key->alg == ALG_TKIP) { |
17d7904d S |
913 | set_bit(idx + 64, sc->keymap); |
914 | if (sc->splitmic) { | |
915 | set_bit(idx + 32, sc->keymap); | |
916 | set_bit(idx + 64 + 32, sc->keymap); | |
6ace2891 JM |
917 | } |
918 | } | |
919 | ||
920 | return idx; | |
f078f209 LR |
921 | } |
922 | ||
923 | static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key) | |
924 | { | |
6ace2891 JM |
925 | ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx); |
926 | if (key->hw_key_idx < IEEE80211_WEP_NKID) | |
927 | return; | |
928 | ||
17d7904d | 929 | clear_bit(key->hw_key_idx, sc->keymap); |
6ace2891 JM |
930 | if (key->alg != ALG_TKIP) |
931 | return; | |
f078f209 | 932 | |
17d7904d S |
933 | clear_bit(key->hw_key_idx + 64, sc->keymap); |
934 | if (sc->splitmic) { | |
935 | clear_bit(key->hw_key_idx + 32, sc->keymap); | |
936 | clear_bit(key->hw_key_idx + 64 + 32, sc->keymap); | |
6ace2891 | 937 | } |
f078f209 LR |
938 | } |
939 | ||
eb2599ca S |
940 | static void setup_ht_cap(struct ath_softc *sc, |
941 | struct ieee80211_sta_ht_cap *ht_info) | |
f078f209 | 942 | { |
140add21 | 943 | u8 tx_streams, rx_streams; |
f078f209 | 944 | |
d9fe60de JB |
945 | ht_info->ht_supported = true; |
946 | ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | | |
947 | IEEE80211_HT_CAP_SM_PS | | |
948 | IEEE80211_HT_CAP_SGI_40 | | |
949 | IEEE80211_HT_CAP_DSSSCCK40; | |
f078f209 | 950 | |
9e98ac65 S |
951 | ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; |
952 | ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; | |
eb2599ca | 953 | |
d9fe60de JB |
954 | /* set up supported mcs set */ |
955 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | |
140add21 SB |
956 | tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2; |
957 | rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2; | |
958 | ||
959 | if (tx_streams != rx_streams) { | |
4d6b228d | 960 | DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n", |
140add21 SB |
961 | tx_streams, rx_streams); |
962 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; | |
963 | ht_info->mcs.tx_params |= ((tx_streams - 1) << | |
964 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
965 | } | |
eb2599ca | 966 | |
140add21 SB |
967 | ht_info->mcs.rx_mask[0] = 0xff; |
968 | if (rx_streams >= 2) | |
eb2599ca | 969 | ht_info->mcs.rx_mask[1] = 0xff; |
eb2599ca | 970 | |
140add21 | 971 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; |
f078f209 LR |
972 | } |
973 | ||
8feceb67 | 974 | static void ath9k_bss_assoc_info(struct ath_softc *sc, |
5640b08e | 975 | struct ieee80211_vif *vif, |
8feceb67 | 976 | struct ieee80211_bss_conf *bss_conf) |
f078f209 | 977 | { |
f078f209 | 978 | |
8feceb67 | 979 | if (bss_conf->assoc) { |
4d6b228d | 980 | DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n", |
17d7904d | 981 | bss_conf->aid, sc->curbssid); |
f078f209 | 982 | |
8feceb67 | 983 | /* New association, store aid */ |
2664f201 SB |
984 | sc->curaid = bss_conf->aid; |
985 | ath9k_hw_write_associd(sc); | |
986 | ||
987 | /* | |
988 | * Request a re-configuration of Beacon related timers | |
989 | * on the receipt of the first Beacon frame (i.e., | |
990 | * after time sync with the AP). | |
991 | */ | |
992 | sc->sc_flags |= SC_OP_BEACON_SYNC; | |
f078f209 | 993 | |
8feceb67 | 994 | /* Configure the beacon */ |
2c3db3d5 | 995 | ath_beacon_config(sc, vif); |
f078f209 | 996 | |
8feceb67 | 997 | /* Reset rssi stats */ |
22e66a4c | 998 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; |
f078f209 | 999 | |
415f738e | 1000 | ath_start_ani(sc); |
8feceb67 | 1001 | } else { |
4d6b228d | 1002 | DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); |
17d7904d | 1003 | sc->curaid = 0; |
f38faa31 SB |
1004 | /* Stop ANI */ |
1005 | del_timer_sync(&sc->ani.timer); | |
f078f209 | 1006 | } |
8feceb67 | 1007 | } |
f078f209 | 1008 | |
8feceb67 VT |
1009 | /********************************/ |
1010 | /* LED functions */ | |
1011 | /********************************/ | |
f078f209 | 1012 | |
f2bffa7e VT |
1013 | static void ath_led_blink_work(struct work_struct *work) |
1014 | { | |
1015 | struct ath_softc *sc = container_of(work, struct ath_softc, | |
1016 | ath_led_blink_work.work); | |
1017 | ||
1018 | if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED)) | |
1019 | return; | |
85067c06 VT |
1020 | |
1021 | if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) || | |
1022 | (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE)) | |
08fc5c1b | 1023 | ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0); |
85067c06 | 1024 | else |
08fc5c1b | 1025 | ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, |
85067c06 | 1026 | (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0); |
f2bffa7e | 1027 | |
42935eca LR |
1028 | ieee80211_queue_delayed_work(sc->hw, |
1029 | &sc->ath_led_blink_work, | |
1030 | (sc->sc_flags & SC_OP_LED_ON) ? | |
1031 | msecs_to_jiffies(sc->led_off_duration) : | |
1032 | msecs_to_jiffies(sc->led_on_duration)); | |
f2bffa7e | 1033 | |
85067c06 VT |
1034 | sc->led_on_duration = sc->led_on_cnt ? |
1035 | max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) : | |
1036 | ATH_LED_ON_DURATION_IDLE; | |
1037 | sc->led_off_duration = sc->led_off_cnt ? | |
1038 | max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) : | |
1039 | ATH_LED_OFF_DURATION_IDLE; | |
f2bffa7e VT |
1040 | sc->led_on_cnt = sc->led_off_cnt = 0; |
1041 | if (sc->sc_flags & SC_OP_LED_ON) | |
1042 | sc->sc_flags &= ~SC_OP_LED_ON; | |
1043 | else | |
1044 | sc->sc_flags |= SC_OP_LED_ON; | |
1045 | } | |
1046 | ||
8feceb67 VT |
1047 | static void ath_led_brightness(struct led_classdev *led_cdev, |
1048 | enum led_brightness brightness) | |
1049 | { | |
1050 | struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev); | |
1051 | struct ath_softc *sc = led->sc; | |
f078f209 | 1052 | |
8feceb67 VT |
1053 | switch (brightness) { |
1054 | case LED_OFF: | |
1055 | if (led->led_type == ATH_LED_ASSOC || | |
f2bffa7e | 1056 | led->led_type == ATH_LED_RADIO) { |
08fc5c1b | 1057 | ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, |
f2bffa7e | 1058 | (led->led_type == ATH_LED_RADIO)); |
8feceb67 | 1059 | sc->sc_flags &= ~SC_OP_LED_ASSOCIATED; |
f2bffa7e VT |
1060 | if (led->led_type == ATH_LED_RADIO) |
1061 | sc->sc_flags &= ~SC_OP_LED_ON; | |
1062 | } else { | |
1063 | sc->led_off_cnt++; | |
1064 | } | |
8feceb67 VT |
1065 | break; |
1066 | case LED_FULL: | |
f2bffa7e | 1067 | if (led->led_type == ATH_LED_ASSOC) { |
8feceb67 | 1068 | sc->sc_flags |= SC_OP_LED_ASSOCIATED; |
42935eca LR |
1069 | ieee80211_queue_delayed_work(sc->hw, |
1070 | &sc->ath_led_blink_work, 0); | |
f2bffa7e | 1071 | } else if (led->led_type == ATH_LED_RADIO) { |
08fc5c1b | 1072 | ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0); |
f2bffa7e VT |
1073 | sc->sc_flags |= SC_OP_LED_ON; |
1074 | } else { | |
1075 | sc->led_on_cnt++; | |
1076 | } | |
8feceb67 VT |
1077 | break; |
1078 | default: | |
1079 | break; | |
f078f209 | 1080 | } |
8feceb67 | 1081 | } |
f078f209 | 1082 | |
8feceb67 VT |
1083 | static int ath_register_led(struct ath_softc *sc, struct ath_led *led, |
1084 | char *trigger) | |
1085 | { | |
1086 | int ret; | |
f078f209 | 1087 | |
8feceb67 VT |
1088 | led->sc = sc; |
1089 | led->led_cdev.name = led->name; | |
1090 | led->led_cdev.default_trigger = trigger; | |
1091 | led->led_cdev.brightness_set = ath_led_brightness; | |
f078f209 | 1092 | |
8feceb67 VT |
1093 | ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev); |
1094 | if (ret) | |
4d6b228d | 1095 | DPRINTF(sc->sc_ah, ATH_DBG_FATAL, |
8feceb67 VT |
1096 | "Failed to register led:%s", led->name); |
1097 | else | |
1098 | led->registered = 1; | |
1099 | return ret; | |
1100 | } | |
f078f209 | 1101 | |
8feceb67 VT |
1102 | static void ath_unregister_led(struct ath_led *led) |
1103 | { | |
1104 | if (led->registered) { | |
1105 | led_classdev_unregister(&led->led_cdev); | |
1106 | led->registered = 0; | |
f078f209 | 1107 | } |
f078f209 LR |
1108 | } |
1109 | ||
8feceb67 | 1110 | static void ath_deinit_leds(struct ath_softc *sc) |
f078f209 | 1111 | { |
8feceb67 VT |
1112 | ath_unregister_led(&sc->assoc_led); |
1113 | sc->sc_flags &= ~SC_OP_LED_ASSOCIATED; | |
1114 | ath_unregister_led(&sc->tx_led); | |
1115 | ath_unregister_led(&sc->rx_led); | |
1116 | ath_unregister_led(&sc->radio_led); | |
08fc5c1b | 1117 | ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1); |
8feceb67 | 1118 | } |
f078f209 | 1119 | |
8feceb67 VT |
1120 | static void ath_init_leds(struct ath_softc *sc) |
1121 | { | |
1122 | char *trigger; | |
1123 | int ret; | |
f078f209 | 1124 | |
08fc5c1b VN |
1125 | if (AR_SREV_9287(sc->sc_ah)) |
1126 | sc->sc_ah->led_pin = ATH_LED_PIN_9287; | |
1127 | else | |
1128 | sc->sc_ah->led_pin = ATH_LED_PIN_DEF; | |
1129 | ||
8feceb67 | 1130 | /* Configure gpio 1 for output */ |
08fc5c1b | 1131 | ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin, |
8feceb67 VT |
1132 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
1133 | /* LED off, active low */ | |
08fc5c1b | 1134 | ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1); |
7dcfdcd9 | 1135 | |
f2bffa7e VT |
1136 | INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work); |
1137 | ||
8feceb67 VT |
1138 | trigger = ieee80211_get_radio_led_name(sc->hw); |
1139 | snprintf(sc->radio_led.name, sizeof(sc->radio_led.name), | |
0818cb8a | 1140 | "ath9k-%s::radio", wiphy_name(sc->hw->wiphy)); |
8feceb67 VT |
1141 | ret = ath_register_led(sc, &sc->radio_led, trigger); |
1142 | sc->radio_led.led_type = ATH_LED_RADIO; | |
1143 | if (ret) | |
1144 | goto fail; | |
7dcfdcd9 | 1145 | |
8feceb67 VT |
1146 | trigger = ieee80211_get_assoc_led_name(sc->hw); |
1147 | snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name), | |
0818cb8a | 1148 | "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy)); |
8feceb67 VT |
1149 | ret = ath_register_led(sc, &sc->assoc_led, trigger); |
1150 | sc->assoc_led.led_type = ATH_LED_ASSOC; | |
1151 | if (ret) | |
1152 | goto fail; | |
f078f209 | 1153 | |
8feceb67 VT |
1154 | trigger = ieee80211_get_tx_led_name(sc->hw); |
1155 | snprintf(sc->tx_led.name, sizeof(sc->tx_led.name), | |
0818cb8a | 1156 | "ath9k-%s::tx", wiphy_name(sc->hw->wiphy)); |
8feceb67 VT |
1157 | ret = ath_register_led(sc, &sc->tx_led, trigger); |
1158 | sc->tx_led.led_type = ATH_LED_TX; | |
1159 | if (ret) | |
1160 | goto fail; | |
f078f209 | 1161 | |
8feceb67 VT |
1162 | trigger = ieee80211_get_rx_led_name(sc->hw); |
1163 | snprintf(sc->rx_led.name, sizeof(sc->rx_led.name), | |
0818cb8a | 1164 | "ath9k-%s::rx", wiphy_name(sc->hw->wiphy)); |
8feceb67 VT |
1165 | ret = ath_register_led(sc, &sc->rx_led, trigger); |
1166 | sc->rx_led.led_type = ATH_LED_RX; | |
1167 | if (ret) | |
1168 | goto fail; | |
f078f209 | 1169 | |
8feceb67 VT |
1170 | return; |
1171 | ||
1172 | fail: | |
35c95ab9 | 1173 | cancel_delayed_work_sync(&sc->ath_led_blink_work); |
8feceb67 | 1174 | ath_deinit_leds(sc); |
f078f209 LR |
1175 | } |
1176 | ||
7ec3e514 | 1177 | void ath_radio_enable(struct ath_softc *sc) |
500c064d | 1178 | { |
cbe61d8a | 1179 | struct ath_hw *ah = sc->sc_ah; |
ae8d2858 LR |
1180 | struct ieee80211_channel *channel = sc->hw->conf.channel; |
1181 | int r; | |
500c064d | 1182 | |
3cbb5dd7 | 1183 | ath9k_ps_wakeup(sc); |
93b1b37f | 1184 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ae8d2858 | 1185 | |
159cd468 VT |
1186 | if (!ah->curchan) |
1187 | ah->curchan = ath_get_curchannel(sc, sc->hw); | |
1188 | ||
d2f5b3a6 | 1189 | spin_lock_bh(&sc->sc_resetlock); |
2660b81a | 1190 | r = ath9k_hw_reset(ah, ah->curchan, false); |
ae8d2858 | 1191 | if (r) { |
4d6b228d | 1192 | DPRINTF(sc->sc_ah, ATH_DBG_FATAL, |
ae8d2858 | 1193 | "Unable to reset channel %u (%uMhz) ", |
6b45784f | 1194 | "reset status %d\n", |
ae8d2858 | 1195 | channel->center_freq, r); |
500c064d VT |
1196 | } |
1197 | spin_unlock_bh(&sc->sc_resetlock); | |
1198 | ||
1199 | ath_update_txpow(sc); | |
1200 | if (ath_startrecv(sc) != 0) { | |
4d6b228d | 1201 | DPRINTF(sc->sc_ah, ATH_DBG_FATAL, |
04bd4638 | 1202 | "Unable to restart recv logic\n"); |
500c064d VT |
1203 | return; |
1204 | } | |
1205 | ||
1206 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 1207 | ath_beacon_config(sc, NULL); /* restart beacons */ |
500c064d VT |
1208 | |
1209 | /* Re-Enable interrupts */ | |
17d7904d | 1210 | ath9k_hw_set_interrupts(ah, sc->imask); |
500c064d VT |
1211 | |
1212 | /* Enable LED */ | |
08fc5c1b | 1213 | ath9k_hw_cfg_output(ah, ah->led_pin, |
500c064d | 1214 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
08fc5c1b | 1215 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); |
500c064d VT |
1216 | |
1217 | ieee80211_wake_queues(sc->hw); | |
3cbb5dd7 | 1218 | ath9k_ps_restore(sc); |
500c064d VT |
1219 | } |
1220 | ||
7ec3e514 | 1221 | void ath_radio_disable(struct ath_softc *sc) |
500c064d | 1222 | { |
cbe61d8a | 1223 | struct ath_hw *ah = sc->sc_ah; |
ae8d2858 LR |
1224 | struct ieee80211_channel *channel = sc->hw->conf.channel; |
1225 | int r; | |
500c064d | 1226 | |
3cbb5dd7 | 1227 | ath9k_ps_wakeup(sc); |
500c064d VT |
1228 | ieee80211_stop_queues(sc->hw); |
1229 | ||
1230 | /* Disable LED */ | |
08fc5c1b VN |
1231 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); |
1232 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
500c064d VT |
1233 | |
1234 | /* Disable interrupts */ | |
1235 | ath9k_hw_set_interrupts(ah, 0); | |
1236 | ||
043a0405 | 1237 | ath_drain_all_txq(sc, false); /* clear pending tx frames */ |
500c064d VT |
1238 | ath_stoprecv(sc); /* turn off frame recv */ |
1239 | ath_flushrecv(sc); /* flush recv queue */ | |
1240 | ||
159cd468 VT |
1241 | if (!ah->curchan) |
1242 | ah->curchan = ath_get_curchannel(sc, sc->hw); | |
1243 | ||
500c064d | 1244 | spin_lock_bh(&sc->sc_resetlock); |
2660b81a | 1245 | r = ath9k_hw_reset(ah, ah->curchan, false); |
ae8d2858 | 1246 | if (r) { |
4d6b228d | 1247 | DPRINTF(sc->sc_ah, ATH_DBG_FATAL, |
04bd4638 | 1248 | "Unable to reset channel %u (%uMhz) " |
6b45784f | 1249 | "reset status %d\n", |
ae8d2858 | 1250 | channel->center_freq, r); |
500c064d VT |
1251 | } |
1252 | spin_unlock_bh(&sc->sc_resetlock); | |
1253 | ||
1254 | ath9k_hw_phy_disable(ah); | |
93b1b37f | 1255 | ath9k_hw_configpcipowersave(ah, 1, 1); |
3cbb5dd7 | 1256 | ath9k_ps_restore(sc); |
9ecdef4b | 1257 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
500c064d VT |
1258 | } |
1259 | ||
5077fd35 GJ |
1260 | /*******************/ |
1261 | /* Rfkill */ | |
1262 | /*******************/ | |
1263 | ||
500c064d VT |
1264 | static bool ath_is_rfkill_set(struct ath_softc *sc) |
1265 | { | |
cbe61d8a | 1266 | struct ath_hw *ah = sc->sc_ah; |
500c064d | 1267 | |
2660b81a S |
1268 | return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) == |
1269 | ah->rfkill_polarity; | |
500c064d VT |
1270 | } |
1271 | ||
3b319aae | 1272 | static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw) |
500c064d | 1273 | { |
3b319aae JB |
1274 | struct ath_wiphy *aphy = hw->priv; |
1275 | struct ath_softc *sc = aphy->sc; | |
19d337df | 1276 | bool blocked = !!ath_is_rfkill_set(sc); |
500c064d | 1277 | |
3b319aae | 1278 | wiphy_rfkill_set_hw_state(hw->wiphy, blocked); |
500c064d VT |
1279 | } |
1280 | ||
3b319aae | 1281 | static void ath_start_rfkill_poll(struct ath_softc *sc) |
500c064d | 1282 | { |
3b319aae | 1283 | struct ath_hw *ah = sc->sc_ah; |
9c84b797 | 1284 | |
3b319aae JB |
1285 | if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) |
1286 | wiphy_rfkill_start_polling(sc->hw->wiphy); | |
9c84b797 | 1287 | } |
500c064d | 1288 | |
6baff7f9 | 1289 | void ath_cleanup(struct ath_softc *sc) |
39c3c2f2 GJ |
1290 | { |
1291 | ath_detach(sc); | |
1292 | free_irq(sc->irq, sc); | |
1293 | ath_bus_cleanup(sc); | |
c52f33d0 | 1294 | kfree(sc->sec_wiphy); |
39c3c2f2 GJ |
1295 | ieee80211_free_hw(sc->hw); |
1296 | } | |
1297 | ||
6baff7f9 | 1298 | void ath_detach(struct ath_softc *sc) |
f078f209 | 1299 | { |
8feceb67 | 1300 | struct ieee80211_hw *hw = sc->hw; |
4d6b228d | 1301 | struct ath_hw *ah = sc->sc_ah; |
9c84b797 | 1302 | int i = 0; |
f078f209 | 1303 | |
3cbb5dd7 VN |
1304 | ath9k_ps_wakeup(sc); |
1305 | ||
4d6b228d | 1306 | dev_dbg(sc->dev, "Detach ATH hw\n"); |
f078f209 | 1307 | |
35c95ab9 | 1308 | ath_deinit_leds(sc); |
e31f7b96 | 1309 | wiphy_rfkill_stop_polling(sc->hw->wiphy); |
35c95ab9 | 1310 | |
c52f33d0 JM |
1311 | for (i = 0; i < sc->num_sec_wiphy; i++) { |
1312 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
1313 | if (aphy == NULL) | |
1314 | continue; | |
1315 | sc->sec_wiphy[i] = NULL; | |
1316 | ieee80211_unregister_hw(aphy->hw); | |
1317 | ieee80211_free_hw(aphy->hw); | |
1318 | } | |
3fcdfb4b | 1319 | ieee80211_unregister_hw(hw); |
8feceb67 VT |
1320 | ath_rx_cleanup(sc); |
1321 | ath_tx_cleanup(sc); | |
f078f209 | 1322 | |
9c84b797 S |
1323 | tasklet_kill(&sc->intr_tq); |
1324 | tasklet_kill(&sc->bcon_tasklet); | |
f078f209 | 1325 | |
9c84b797 | 1326 | if (!(sc->sc_flags & SC_OP_INVALID)) |
9ecdef4b | 1327 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
8feceb67 | 1328 | |
9c84b797 S |
1329 | /* cleanup tx queues */ |
1330 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
1331 | if (ATH_TXQ_SETUP(sc, i)) | |
b77f483f | 1332 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); |
9c84b797 | 1333 | |
75d7839f | 1334 | if ((sc->btcoex.no_stomp_timer) && |
766ec4a9 | 1335 | ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1336 | ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer); |
1773912b | 1337 | |
4d6b228d | 1338 | ath9k_hw_detach(ah); |
af03abec | 1339 | ath9k_exit_debug(ah); |
3ce1b1a9 | 1340 | sc->sc_ah = NULL; |
f078f209 LR |
1341 | } |
1342 | ||
e3bb249b BC |
1343 | static int ath9k_reg_notifier(struct wiphy *wiphy, |
1344 | struct regulatory_request *request) | |
1345 | { | |
1346 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); | |
1347 | struct ath_wiphy *aphy = hw->priv; | |
1348 | struct ath_softc *sc = aphy->sc; | |
608b88cb | 1349 | struct ath_regulatory *reg = &sc->common.regulatory; |
e3bb249b BC |
1350 | |
1351 | return ath_reg_notifier_apply(wiphy, request, reg); | |
1352 | } | |
1353 | ||
75d7839f LR |
1354 | /* |
1355 | * Detects if there is any priority bt traffic | |
1356 | */ | |
1357 | static void ath_detect_bt_priority(struct ath_softc *sc) | |
1358 | { | |
1359 | struct ath_btcoex *btcoex = &sc->btcoex; | |
1360 | struct ath_hw *ah = sc->sc_ah; | |
1361 | ||
766ec4a9 | 1362 | if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio)) |
75d7839f LR |
1363 | btcoex->bt_priority_cnt++; |
1364 | ||
1365 | if (time_after(jiffies, btcoex->bt_priority_time + | |
1366 | msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) { | |
1367 | if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) { | |
1368 | DPRINTF(sc->sc_ah, ATH_DBG_BTCOEX, | |
1369 | "BT priority traffic detected"); | |
1370 | sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED; | |
1371 | } else { | |
1372 | sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED; | |
1373 | } | |
1374 | ||
1375 | btcoex->bt_priority_cnt = 0; | |
1376 | btcoex->bt_priority_time = jiffies; | |
1377 | } | |
1378 | } | |
1379 | ||
75d7839f LR |
1380 | /* |
1381 | * Configures appropriate weight based on stomp type. | |
1382 | */ | |
269ad812 LR |
1383 | static void ath9k_btcoex_bt_stomp(struct ath_softc *sc, |
1384 | enum ath_stomp_type stomp_type) | |
75d7839f | 1385 | { |
269ad812 | 1386 | struct ath_hw *ah = sc->sc_ah; |
75d7839f LR |
1387 | |
1388 | switch (stomp_type) { | |
1389 | case ATH_BTCOEX_STOMP_ALL: | |
269ad812 LR |
1390 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, |
1391 | AR_STOMP_ALL_WLAN_WGHT); | |
75d7839f LR |
1392 | break; |
1393 | case ATH_BTCOEX_STOMP_LOW: | |
269ad812 LR |
1394 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, |
1395 | AR_STOMP_LOW_WLAN_WGHT); | |
75d7839f LR |
1396 | break; |
1397 | case ATH_BTCOEX_STOMP_NONE: | |
269ad812 LR |
1398 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, |
1399 | AR_STOMP_NONE_WLAN_WGHT); | |
75d7839f LR |
1400 | break; |
1401 | default: | |
269ad812 | 1402 | DPRINTF(ah, ATH_DBG_BTCOEX, "Invalid Stomptype\n"); |
75d7839f LR |
1403 | break; |
1404 | } | |
1405 | ||
269ad812 | 1406 | ath9k_hw_btcoex_enable(ah); |
75d7839f LR |
1407 | } |
1408 | ||
1409 | /* | |
1410 | * This is the master bt coex timer which runs for every | |
1411 | * 45ms, bt traffic will be given priority during 55% of this | |
1412 | * period while wlan gets remaining 45% | |
1413 | */ | |
1414 | static void ath_btcoex_period_timer(unsigned long data) | |
1415 | { | |
1416 | struct ath_softc *sc = (struct ath_softc *) data; | |
1417 | struct ath_hw *ah = sc->sc_ah; | |
1418 | struct ath_btcoex *btcoex = &sc->btcoex; | |
75d7839f LR |
1419 | |
1420 | ath_detect_bt_priority(sc); | |
1421 | ||
1422 | spin_lock_bh(&btcoex->btcoex_lock); | |
1423 | ||
269ad812 | 1424 | ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type); |
75d7839f LR |
1425 | |
1426 | spin_unlock_bh(&btcoex->btcoex_lock); | |
1427 | ||
1428 | if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) { | |
1429 | if (btcoex->hw_timer_enabled) | |
1430 | ath_gen_timer_stop(ah, btcoex->no_stomp_timer); | |
1431 | ||
1432 | ath_gen_timer_start(ah, | |
1433 | btcoex->no_stomp_timer, | |
1434 | (ath9k_hw_gettsf32(ah) + | |
1435 | btcoex->btcoex_no_stomp), | |
1436 | btcoex->btcoex_no_stomp * 10); | |
1437 | btcoex->hw_timer_enabled = true; | |
1438 | } | |
1439 | ||
1440 | mod_timer(&btcoex->period_timer, jiffies + | |
1441 | msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD)); | |
1442 | } | |
1443 | ||
1444 | /* | |
1445 | * Generic tsf based hw timer which configures weight | |
1446 | * registers to time slice between wlan and bt traffic | |
1447 | */ | |
1448 | static void ath_btcoex_no_stomp_timer(void *arg) | |
1449 | { | |
1450 | struct ath_softc *sc = (struct ath_softc *)arg; | |
1451 | struct ath_hw *ah = sc->sc_ah; | |
1452 | struct ath_btcoex *btcoex = &sc->btcoex; | |
75d7839f LR |
1453 | |
1454 | DPRINTF(ah, ATH_DBG_BTCOEX, "no stomp timer running \n"); | |
1455 | ||
1456 | spin_lock_bh(&btcoex->btcoex_lock); | |
1457 | ||
e08a6ace | 1458 | if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW) |
269ad812 | 1459 | ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE); |
e08a6ace | 1460 | else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL) |
269ad812 | 1461 | ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW); |
75d7839f LR |
1462 | |
1463 | spin_unlock_bh(&btcoex->btcoex_lock); | |
1464 | } | |
1465 | ||
1466 | static int ath_init_btcoex_timer(struct ath_softc *sc) | |
1467 | { | |
1468 | struct ath_btcoex *btcoex = &sc->btcoex; | |
1469 | ||
1470 | btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000; | |
1471 | btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) * | |
1472 | btcoex->btcoex_period / 100; | |
1473 | ||
1474 | setup_timer(&btcoex->period_timer, ath_btcoex_period_timer, | |
1475 | (unsigned long) sc); | |
1476 | ||
1477 | spin_lock_init(&btcoex->btcoex_lock); | |
1478 | ||
1479 | btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah, | |
1480 | ath_btcoex_no_stomp_timer, | |
1481 | ath_btcoex_no_stomp_timer, | |
1482 | (void *) sc, AR_FIRST_NDP_TIMER); | |
1483 | ||
1484 | if (!btcoex->no_stomp_timer) | |
1485 | return -ENOMEM; | |
1486 | ||
1487 | return 0; | |
1488 | } | |
1489 | ||
1e40bcfa LR |
1490 | /* |
1491 | * Initialize and fill ath_softc, ath_sofct is the | |
1492 | * "Software Carrier" struct. Historically it has existed | |
1493 | * to allow the separation between hardware specific | |
1494 | * variables (now in ath_hw) and driver specific variables. | |
1495 | */ | |
aeac355d | 1496 | static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid) |
ff37e337 | 1497 | { |
cbe61d8a | 1498 | struct ath_hw *ah = NULL; |
4f3acf81 | 1499 | int r = 0, i; |
ff37e337 | 1500 | int csz = 0; |
75d7839f | 1501 | int qnum; |
ff37e337 S |
1502 | |
1503 | /* XXX: hardware will not be ready until ath_open() being called */ | |
1504 | sc->sc_flags |= SC_OP_INVALID; | |
88b126af | 1505 | |
c52f33d0 | 1506 | spin_lock_init(&sc->wiphy_lock); |
ff37e337 | 1507 | spin_lock_init(&sc->sc_resetlock); |
6158425b | 1508 | spin_lock_init(&sc->sc_serial_rw); |
e5f0921a | 1509 | spin_lock_init(&sc->ani_lock); |
04717ccd | 1510 | spin_lock_init(&sc->sc_pm_lock); |
aa33de09 | 1511 | mutex_init(&sc->mutex); |
ff37e337 | 1512 | tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); |
9fc9ab0a | 1513 | tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet, |
ff37e337 S |
1514 | (unsigned long)sc); |
1515 | ||
1516 | /* | |
1517 | * Cache line size is used to size and align various | |
1518 | * structures used to communicate with the hardware. | |
1519 | */ | |
88d15707 | 1520 | ath_read_cachesize(sc, &csz); |
ff37e337 | 1521 | /* XXX assert csz is non-zero */ |
d15dd3e5 | 1522 | sc->common.cachelsz = csz << 2; /* convert to bytes */ |
ff37e337 | 1523 | |
4f3acf81 LR |
1524 | ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); |
1525 | if (!ah) { | |
4f3acf81 LR |
1526 | r = -ENOMEM; |
1527 | goto bad_no_ah; | |
1528 | } | |
1529 | ||
1530 | ah->ah_sc = sc; | |
8df5d1b7 | 1531 | ah->hw_version.devid = devid; |
aeac355d | 1532 | ah->hw_version.subsysid = subsysid; |
e1e2f93f | 1533 | sc->sc_ah = ah; |
4f3acf81 | 1534 | |
4d6b228d LR |
1535 | if (ath9k_init_debug(ah) < 0) |
1536 | dev_err(sc->dev, "Unable to create debugfs files\n"); | |
1537 | ||
f637cfd6 | 1538 | r = ath9k_hw_init(ah); |
4f3acf81 | 1539 | if (r) { |
4d6b228d | 1540 | DPRINTF(ah, ATH_DBG_FATAL, |
f637cfd6 | 1541 | "Unable to initialize hardware; " |
4f3acf81 | 1542 | "initialization status: %d\n", r); |
ff37e337 S |
1543 | goto bad; |
1544 | } | |
ff37e337 S |
1545 | |
1546 | /* Get the hardware key cache size. */ | |
2660b81a | 1547 | sc->keymax = ah->caps.keycache_size; |
17d7904d | 1548 | if (sc->keymax > ATH_KEYMAX) { |
4d6b228d | 1549 | DPRINTF(ah, ATH_DBG_ANY, |
04bd4638 | 1550 | "Warning, using only %u entries in %u key cache\n", |
17d7904d S |
1551 | ATH_KEYMAX, sc->keymax); |
1552 | sc->keymax = ATH_KEYMAX; | |
ff37e337 S |
1553 | } |
1554 | ||
1555 | /* | |
1556 | * Reset the key cache since some parts do not | |
1557 | * reset the contents on initial power up. | |
1558 | */ | |
17d7904d | 1559 | for (i = 0; i < sc->keymax; i++) |
ff37e337 | 1560 | ath9k_hw_keyreset(ah, (u16) i); |
ff37e337 | 1561 | |
ff37e337 | 1562 | /* default to MONITOR mode */ |
2660b81a | 1563 | sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR; |
d97809db | 1564 | |
ff37e337 S |
1565 | /* Setup rate tables */ |
1566 | ||
1567 | ath_rate_attach(sc); | |
1568 | ath_setup_rates(sc, IEEE80211_BAND_2GHZ); | |
1569 | ath_setup_rates(sc, IEEE80211_BAND_5GHZ); | |
1570 | ||
1571 | /* | |
1572 | * Allocate hardware transmit queues: one queue for | |
1573 | * beacon frames and one data queue for each QoS | |
1574 | * priority. Note that the hal handles reseting | |
1575 | * these queues at the needed time. | |
1576 | */ | |
b77f483f S |
1577 | sc->beacon.beaconq = ath_beaconq_setup(ah); |
1578 | if (sc->beacon.beaconq == -1) { | |
4d6b228d | 1579 | DPRINTF(ah, ATH_DBG_FATAL, |
04bd4638 | 1580 | "Unable to setup a beacon xmit queue\n"); |
4f3acf81 | 1581 | r = -EIO; |
ff37e337 S |
1582 | goto bad2; |
1583 | } | |
b77f483f S |
1584 | sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); |
1585 | if (sc->beacon.cabq == NULL) { | |
4d6b228d | 1586 | DPRINTF(ah, ATH_DBG_FATAL, |
04bd4638 | 1587 | "Unable to setup CAB xmit queue\n"); |
4f3acf81 | 1588 | r = -EIO; |
ff37e337 S |
1589 | goto bad2; |
1590 | } | |
1591 | ||
17d7904d | 1592 | sc->config.cabqReadytime = ATH_CABQ_READY_TIME; |
ff37e337 S |
1593 | ath_cabq_update(sc); |
1594 | ||
b77f483f S |
1595 | for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++) |
1596 | sc->tx.hwq_map[i] = -1; | |
ff37e337 S |
1597 | |
1598 | /* Setup data queues */ | |
1599 | /* NB: ensure BK queue is the lowest priority h/w queue */ | |
1600 | if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) { | |
4d6b228d | 1601 | DPRINTF(ah, ATH_DBG_FATAL, |
04bd4638 | 1602 | "Unable to setup xmit queue for BK traffic\n"); |
4f3acf81 | 1603 | r = -EIO; |
ff37e337 S |
1604 | goto bad2; |
1605 | } | |
1606 | ||
1607 | if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) { | |
4d6b228d | 1608 | DPRINTF(ah, ATH_DBG_FATAL, |
04bd4638 | 1609 | "Unable to setup xmit queue for BE traffic\n"); |
4f3acf81 | 1610 | r = -EIO; |
ff37e337 S |
1611 | goto bad2; |
1612 | } | |
1613 | if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) { | |
4d6b228d | 1614 | DPRINTF(ah, ATH_DBG_FATAL, |
04bd4638 | 1615 | "Unable to setup xmit queue for VI traffic\n"); |
4f3acf81 | 1616 | r = -EIO; |
ff37e337 S |
1617 | goto bad2; |
1618 | } | |
1619 | if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) { | |
4d6b228d | 1620 | DPRINTF(ah, ATH_DBG_FATAL, |
04bd4638 | 1621 | "Unable to setup xmit queue for VO traffic\n"); |
4f3acf81 | 1622 | r = -EIO; |
ff37e337 S |
1623 | goto bad2; |
1624 | } | |
1625 | ||
1626 | /* Initializes the noise floor to a reasonable default value. | |
1627 | * Later on this will be updated during ANI processing. */ | |
1628 | ||
17d7904d S |
1629 | sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR; |
1630 | setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc); | |
ff37e337 S |
1631 | |
1632 | if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, | |
1633 | ATH9K_CIPHER_TKIP, NULL)) { | |
1634 | /* | |
1635 | * Whether we should enable h/w TKIP MIC. | |
1636 | * XXX: if we don't support WME TKIP MIC, then we wouldn't | |
1637 | * report WMM capable, so it's always safe to turn on | |
1638 | * TKIP MIC in this case. | |
1639 | */ | |
1640 | ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC, | |
1641 | 0, 1, NULL); | |
1642 | } | |
1643 | ||
1644 | /* | |
1645 | * Check whether the separate key cache entries | |
1646 | * are required to handle both tx+rx MIC keys. | |
1647 | * With split mic keys the number of stations is limited | |
1648 | * to 27 otherwise 59. | |
1649 | */ | |
1650 | if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, | |
1651 | ATH9K_CIPHER_TKIP, NULL) | |
1652 | && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, | |
1653 | ATH9K_CIPHER_MIC, NULL) | |
1654 | && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT, | |
1655 | 0, NULL)) | |
17d7904d | 1656 | sc->splitmic = 1; |
ff37e337 S |
1657 | |
1658 | /* turn on mcast key search if possible */ | |
1659 | if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL)) | |
1660 | (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1, | |
1661 | 1, NULL); | |
1662 | ||
17d7904d | 1663 | sc->config.txpowlimit = ATH_TXPOWER_MAX; |
ff37e337 S |
1664 | |
1665 | /* 11n Capabilities */ | |
2660b81a | 1666 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
ff37e337 S |
1667 | sc->sc_flags |= SC_OP_TXAGGR; |
1668 | sc->sc_flags |= SC_OP_RXAGGR; | |
1669 | } | |
1670 | ||
2660b81a S |
1671 | sc->tx_chainmask = ah->caps.tx_chainmask; |
1672 | sc->rx_chainmask = ah->caps.rx_chainmask; | |
ff37e337 S |
1673 | |
1674 | ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL); | |
b77f483f | 1675 | sc->rx.defant = ath9k_hw_getdefantenna(ah); |
ff37e337 | 1676 | |
8ca21f01 | 1677 | if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
ba52da58 | 1678 | memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN); |
ff37e337 | 1679 | |
b77f483f | 1680 | sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */ |
ff37e337 S |
1681 | |
1682 | /* initialize beacon slots */ | |
c52f33d0 | 1683 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { |
2c3db3d5 | 1684 | sc->beacon.bslot[i] = NULL; |
c52f33d0 JM |
1685 | sc->beacon.bslot_aphy[i] = NULL; |
1686 | } | |
ff37e337 | 1687 | |
ff37e337 S |
1688 | /* setup channels and rates */ |
1689 | ||
5f8e077c | 1690 | sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable; |
ff37e337 S |
1691 | sc->sbands[IEEE80211_BAND_2GHZ].bitrates = |
1692 | sc->rates[IEEE80211_BAND_2GHZ]; | |
1693 | sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; | |
5f8e077c LR |
1694 | sc->sbands[IEEE80211_BAND_2GHZ].n_channels = |
1695 | ARRAY_SIZE(ath9k_2ghz_chantable); | |
ff37e337 | 1696 | |
2660b81a | 1697 | if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) { |
5f8e077c | 1698 | sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable; |
ff37e337 S |
1699 | sc->sbands[IEEE80211_BAND_5GHZ].bitrates = |
1700 | sc->rates[IEEE80211_BAND_5GHZ]; | |
1701 | sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; | |
5f8e077c LR |
1702 | sc->sbands[IEEE80211_BAND_5GHZ].n_channels = |
1703 | ARRAY_SIZE(ath9k_5ghz_chantable); | |
ff37e337 S |
1704 | } |
1705 | ||
766ec4a9 | 1706 | switch (ah->btcoex_hw.scheme) { |
75d7839f LR |
1707 | case ATH_BTCOEX_CFG_NONE: |
1708 | break; | |
1709 | case ATH_BTCOEX_CFG_2WIRE: | |
1710 | ath9k_hw_btcoex_init_2wire(ah); | |
1711 | break; | |
1712 | case ATH_BTCOEX_CFG_3WIRE: | |
1713 | ath9k_hw_btcoex_init_3wire(ah); | |
1714 | r = ath_init_btcoex_timer(sc); | |
1773912b VT |
1715 | if (r) |
1716 | goto bad2; | |
75d7839f | 1717 | qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE); |
766ec4a9 | 1718 | ath9k_hw_init_btcoex_hw(ah, qnum); |
e08a6ace | 1719 | sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW; |
75d7839f LR |
1720 | break; |
1721 | default: | |
1722 | WARN_ON(1); | |
1723 | break; | |
1773912b | 1724 | } |
c97c92d9 | 1725 | |
ff37e337 S |
1726 | return 0; |
1727 | bad2: | |
1728 | /* cleanup tx queues */ | |
1729 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
1730 | if (ATH_TXQ_SETUP(sc, i)) | |
b77f483f | 1731 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); |
ff37e337 | 1732 | bad: |
95fafca2 | 1733 | ath9k_hw_detach(ah); |
4f3acf81 | 1734 | bad_no_ah: |
4d6b228d LR |
1735 | ath9k_exit_debug(sc->sc_ah); |
1736 | sc->sc_ah = NULL; | |
ff37e337 | 1737 | |
4f3acf81 | 1738 | return r; |
ff37e337 S |
1739 | } |
1740 | ||
c52f33d0 | 1741 | void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw) |
f078f209 | 1742 | { |
9c84b797 S |
1743 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | |
1744 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | | |
1745 | IEEE80211_HW_SIGNAL_DBM | | |
3cbb5dd7 VN |
1746 | IEEE80211_HW_AMPDU_AGGREGATION | |
1747 | IEEE80211_HW_SUPPORTS_PS | | |
eeee1320 S |
1748 | IEEE80211_HW_PS_NULLFUNC_STACK | |
1749 | IEEE80211_HW_SPECTRUM_MGMT; | |
f078f209 | 1750 | |
b3bd89ce | 1751 | if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt) |
0ced0e17 JM |
1752 | hw->flags |= IEEE80211_HW_MFP_CAPABLE; |
1753 | ||
9c84b797 S |
1754 | hw->wiphy->interface_modes = |
1755 | BIT(NL80211_IFTYPE_AP) | | |
1756 | BIT(NL80211_IFTYPE_STATION) | | |
9cb5412b PE |
1757 | BIT(NL80211_IFTYPE_ADHOC) | |
1758 | BIT(NL80211_IFTYPE_MESH_POINT); | |
f078f209 | 1759 | |
8feceb67 | 1760 | hw->queues = 4; |
e63835b0 | 1761 | hw->max_rates = 4; |
171387ef | 1762 | hw->channel_change_time = 5000; |
465ca84d | 1763 | hw->max_listen_interval = 10; |
dd190183 LR |
1764 | /* Hardware supports 10 but we use 4 */ |
1765 | hw->max_rate_tries = 4; | |
528f0c6b | 1766 | hw->sta_data_size = sizeof(struct ath_node); |
17d7904d | 1767 | hw->vif_data_size = sizeof(struct ath_vif); |
f078f209 | 1768 | |
8feceb67 | 1769 | hw->rate_control_algorithm = "ath9k_rate_control"; |
f078f209 | 1770 | |
c52f33d0 JM |
1771 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = |
1772 | &sc->sbands[IEEE80211_BAND_2GHZ]; | |
1773 | if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) | |
1774 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
1775 | &sc->sbands[IEEE80211_BAND_5GHZ]; | |
1776 | } | |
1777 | ||
1e40bcfa | 1778 | /* Device driver core initialization */ |
aeac355d | 1779 | int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid) |
c52f33d0 JM |
1780 | { |
1781 | struct ieee80211_hw *hw = sc->hw; | |
4d6b228d | 1782 | struct ath_hw *ah; |
c52f33d0 | 1783 | int error = 0, i; |
3a702e49 | 1784 | struct ath_regulatory *reg; |
c52f33d0 | 1785 | |
4d6b228d | 1786 | dev_dbg(sc->dev, "Attach ATH hw\n"); |
c52f33d0 | 1787 | |
aeac355d | 1788 | error = ath_init_softc(devid, sc, subsysid); |
c52f33d0 JM |
1789 | if (error != 0) |
1790 | return error; | |
1791 | ||
4d6b228d LR |
1792 | ah = sc->sc_ah; |
1793 | ||
c52f33d0 JM |
1794 | /* get mac address from hardware and set in mac80211 */ |
1795 | ||
4d6b228d | 1796 | SET_IEEE80211_PERM_ADDR(hw, ah->macaddr); |
c52f33d0 JM |
1797 | |
1798 | ath_set_hw_capab(sc, hw); | |
1799 | ||
608b88cb | 1800 | error = ath_regd_init(&sc->common.regulatory, sc->hw->wiphy, |
c26c2e57 LR |
1801 | ath9k_reg_notifier); |
1802 | if (error) | |
1803 | return error; | |
1804 | ||
608b88cb | 1805 | reg = &sc->common.regulatory; |
c26c2e57 | 1806 | |
4d6b228d | 1807 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) { |
eb2599ca | 1808 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); |
4d6b228d | 1809 | if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) |
eb2599ca | 1810 | setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); |
9c84b797 S |
1811 | } |
1812 | ||
db93e7b5 SB |
1813 | /* initialize tx/rx engine */ |
1814 | error = ath_tx_init(sc, ATH_TXBUF); | |
1815 | if (error != 0) | |
40b130a9 | 1816 | goto error_attach; |
8feceb67 | 1817 | |
db93e7b5 SB |
1818 | error = ath_rx_init(sc, ATH_RXBUF); |
1819 | if (error != 0) | |
40b130a9 | 1820 | goto error_attach; |
8feceb67 | 1821 | |
0e2dedf9 | 1822 | INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work); |
f98c3bd2 JM |
1823 | INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work); |
1824 | sc->wiphy_scheduler_int = msecs_to_jiffies(500); | |
0e2dedf9 | 1825 | |
db93e7b5 | 1826 | error = ieee80211_register_hw(hw); |
8feceb67 | 1827 | |
3a702e49 | 1828 | if (!ath_is_world_regd(reg)) { |
c02cf373 | 1829 | error = regulatory_hint(hw->wiphy, reg->alpha2); |
fe33eb39 LR |
1830 | if (error) |
1831 | goto error_attach; | |
1832 | } | |
5f8e077c | 1833 | |
db93e7b5 SB |
1834 | /* Initialize LED control */ |
1835 | ath_init_leds(sc); | |
8feceb67 | 1836 | |
3b319aae | 1837 | ath_start_rfkill_poll(sc); |
5f8e077c | 1838 | |
8feceb67 | 1839 | return 0; |
40b130a9 VT |
1840 | |
1841 | error_attach: | |
1842 | /* cleanup tx queues */ | |
1843 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
1844 | if (ATH_TXQ_SETUP(sc, i)) | |
1845 | ath_tx_cleanupq(sc, &sc->tx.txq[i]); | |
1846 | ||
4d6b228d LR |
1847 | ath9k_hw_detach(ah); |
1848 | ath9k_exit_debug(ah); | |
3ce1b1a9 | 1849 | sc->sc_ah = NULL; |
40b130a9 | 1850 | |
8feceb67 | 1851 | return error; |
f078f209 LR |
1852 | } |
1853 | ||
ff37e337 S |
1854 | int ath_reset(struct ath_softc *sc, bool retry_tx) |
1855 | { | |
cbe61d8a | 1856 | struct ath_hw *ah = sc->sc_ah; |
030bb495 | 1857 | struct ieee80211_hw *hw = sc->hw; |
ae8d2858 | 1858 | int r; |
ff37e337 S |
1859 | |
1860 | ath9k_hw_set_interrupts(ah, 0); | |
043a0405 | 1861 | ath_drain_all_txq(sc, retry_tx); |
ff37e337 S |
1862 | ath_stoprecv(sc); |
1863 | ath_flushrecv(sc); | |
1864 | ||
1865 | spin_lock_bh(&sc->sc_resetlock); | |
2660b81a | 1866 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false); |
ae8d2858 | 1867 | if (r) |
4d6b228d | 1868 | DPRINTF(ah, ATH_DBG_FATAL, |
6b45784f | 1869 | "Unable to reset hardware; reset status %d\n", r); |
ff37e337 S |
1870 | spin_unlock_bh(&sc->sc_resetlock); |
1871 | ||
1872 | if (ath_startrecv(sc) != 0) | |
4d6b228d | 1873 | DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n"); |
ff37e337 S |
1874 | |
1875 | /* | |
1876 | * We may be doing a reset in response to a request | |
1877 | * that changes the channel so update any state that | |
1878 | * might change as a result. | |
1879 | */ | |
ce111bad | 1880 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
1881 | |
1882 | ath_update_txpow(sc); | |
1883 | ||
1884 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 1885 | ath_beacon_config(sc, NULL); /* restart beacons */ |
ff37e337 | 1886 | |
17d7904d | 1887 | ath9k_hw_set_interrupts(ah, sc->imask); |
ff37e337 S |
1888 | |
1889 | if (retry_tx) { | |
1890 | int i; | |
1891 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1892 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
1893 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
1894 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
1895 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
1896 | } |
1897 | } | |
1898 | } | |
1899 | ||
ae8d2858 | 1900 | return r; |
ff37e337 S |
1901 | } |
1902 | ||
1903 | /* | |
1904 | * This function will allocate both the DMA descriptor structure, and the | |
1905 | * buffers it contains. These are used to contain the descriptors used | |
1906 | * by the system. | |
1907 | */ | |
1908 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
1909 | struct list_head *head, const char *name, | |
1910 | int nbuf, int ndesc) | |
1911 | { | |
1912 | #define DS2PHYS(_dd, _ds) \ | |
1913 | ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) | |
1914 | #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) | |
1915 | #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) | |
1916 | ||
1917 | struct ath_desc *ds; | |
1918 | struct ath_buf *bf; | |
1919 | int i, bsize, error; | |
1920 | ||
4d6b228d | 1921 | DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n", |
04bd4638 | 1922 | name, nbuf, ndesc); |
ff37e337 | 1923 | |
b03a9db9 | 1924 | INIT_LIST_HEAD(head); |
ff37e337 S |
1925 | /* ath_desc must be a multiple of DWORDs */ |
1926 | if ((sizeof(struct ath_desc) % 4) != 0) { | |
4d6b228d | 1927 | DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n"); |
ff37e337 S |
1928 | ASSERT((sizeof(struct ath_desc) % 4) == 0); |
1929 | error = -ENOMEM; | |
1930 | goto fail; | |
1931 | } | |
1932 | ||
ff37e337 S |
1933 | dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; |
1934 | ||
1935 | /* | |
1936 | * Need additional DMA memory because we can't use | |
1937 | * descriptors that cross the 4K page boundary. Assume | |
1938 | * one skipped descriptor per 4K page. | |
1939 | */ | |
2660b81a | 1940 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { |
ff37e337 S |
1941 | u32 ndesc_skipped = |
1942 | ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); | |
1943 | u32 dma_len; | |
1944 | ||
1945 | while (ndesc_skipped) { | |
1946 | dma_len = ndesc_skipped * sizeof(struct ath_desc); | |
1947 | dd->dd_desc_len += dma_len; | |
1948 | ||
1949 | ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); | |
1950 | }; | |
1951 | } | |
1952 | ||
1953 | /* allocate descriptors */ | |
7da3c55c | 1954 | dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len, |
f0e6ce13 | 1955 | &dd->dd_desc_paddr, GFP_KERNEL); |
ff37e337 S |
1956 | if (dd->dd_desc == NULL) { |
1957 | error = -ENOMEM; | |
1958 | goto fail; | |
1959 | } | |
1960 | ds = dd->dd_desc; | |
4d6b228d | 1961 | DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", |
ae459af1 | 1962 | name, ds, (u32) dd->dd_desc_len, |
ff37e337 S |
1963 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); |
1964 | ||
1965 | /* allocate buffers */ | |
1966 | bsize = sizeof(struct ath_buf) * nbuf; | |
f0e6ce13 | 1967 | bf = kzalloc(bsize, GFP_KERNEL); |
ff37e337 S |
1968 | if (bf == NULL) { |
1969 | error = -ENOMEM; | |
1970 | goto fail2; | |
1971 | } | |
ff37e337 S |
1972 | dd->dd_bufptr = bf; |
1973 | ||
ff37e337 S |
1974 | for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { |
1975 | bf->bf_desc = ds; | |
1976 | bf->bf_daddr = DS2PHYS(dd, ds); | |
1977 | ||
2660b81a | 1978 | if (!(sc->sc_ah->caps.hw_caps & |
ff37e337 S |
1979 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { |
1980 | /* | |
1981 | * Skip descriptor addresses which can cause 4KB | |
1982 | * boundary crossing (addr + length) with a 32 dword | |
1983 | * descriptor fetch. | |
1984 | */ | |
1985 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
1986 | ASSERT((caddr_t) bf->bf_desc < | |
1987 | ((caddr_t) dd->dd_desc + | |
1988 | dd->dd_desc_len)); | |
1989 | ||
1990 | ds += ndesc; | |
1991 | bf->bf_desc = ds; | |
1992 | bf->bf_daddr = DS2PHYS(dd, ds); | |
1993 | } | |
1994 | } | |
1995 | list_add_tail(&bf->list, head); | |
1996 | } | |
1997 | return 0; | |
1998 | fail2: | |
7da3c55c GJ |
1999 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, |
2000 | dd->dd_desc_paddr); | |
ff37e337 S |
2001 | fail: |
2002 | memset(dd, 0, sizeof(*dd)); | |
2003 | return error; | |
2004 | #undef ATH_DESC_4KB_BOUND_CHECK | |
2005 | #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED | |
2006 | #undef DS2PHYS | |
2007 | } | |
2008 | ||
2009 | void ath_descdma_cleanup(struct ath_softc *sc, | |
2010 | struct ath_descdma *dd, | |
2011 | struct list_head *head) | |
2012 | { | |
7da3c55c GJ |
2013 | dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc, |
2014 | dd->dd_desc_paddr); | |
ff37e337 S |
2015 | |
2016 | INIT_LIST_HEAD(head); | |
2017 | kfree(dd->dd_bufptr); | |
2018 | memset(dd, 0, sizeof(*dd)); | |
2019 | } | |
2020 | ||
2021 | int ath_get_hal_qnum(u16 queue, struct ath_softc *sc) | |
2022 | { | |
2023 | int qnum; | |
2024 | ||
2025 | switch (queue) { | |
2026 | case 0: | |
b77f483f | 2027 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO]; |
ff37e337 S |
2028 | break; |
2029 | case 1: | |
b77f483f | 2030 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI]; |
ff37e337 S |
2031 | break; |
2032 | case 2: | |
b77f483f | 2033 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE]; |
ff37e337 S |
2034 | break; |
2035 | case 3: | |
b77f483f | 2036 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK]; |
ff37e337 S |
2037 | break; |
2038 | default: | |
b77f483f | 2039 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE]; |
ff37e337 S |
2040 | break; |
2041 | } | |
2042 | ||
2043 | return qnum; | |
2044 | } | |
2045 | ||
2046 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc) | |
2047 | { | |
2048 | int qnum; | |
2049 | ||
2050 | switch (queue) { | |
2051 | case ATH9K_WME_AC_VO: | |
2052 | qnum = 0; | |
2053 | break; | |
2054 | case ATH9K_WME_AC_VI: | |
2055 | qnum = 1; | |
2056 | break; | |
2057 | case ATH9K_WME_AC_BE: | |
2058 | qnum = 2; | |
2059 | break; | |
2060 | case ATH9K_WME_AC_BK: | |
2061 | qnum = 3; | |
2062 | break; | |
2063 | default: | |
2064 | qnum = -1; | |
2065 | break; | |
2066 | } | |
2067 | ||
2068 | return qnum; | |
2069 | } | |
2070 | ||
5f8e077c LR |
2071 | /* XXX: Remove me once we don't depend on ath9k_channel for all |
2072 | * this redundant data */ | |
0e2dedf9 JM |
2073 | void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, |
2074 | struct ath9k_channel *ichan) | |
5f8e077c | 2075 | { |
5f8e077c LR |
2076 | struct ieee80211_channel *chan = hw->conf.channel; |
2077 | struct ieee80211_conf *conf = &hw->conf; | |
2078 | ||
2079 | ichan->channel = chan->center_freq; | |
2080 | ichan->chan = chan; | |
2081 | ||
2082 | if (chan->band == IEEE80211_BAND_2GHZ) { | |
2083 | ichan->chanmode = CHANNEL_G; | |
8813262e | 2084 | ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G; |
5f8e077c LR |
2085 | } else { |
2086 | ichan->chanmode = CHANNEL_A; | |
2087 | ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM; | |
2088 | } | |
2089 | ||
2090 | sc->tx_chan_width = ATH9K_HT_MACMODE_20; | |
2091 | ||
2092 | if (conf_is_ht(conf)) { | |
2093 | if (conf_is_ht40(conf)) | |
2094 | sc->tx_chan_width = ATH9K_HT_MACMODE_2040; | |
2095 | ||
2096 | ichan->chanmode = ath_get_extchanmode(sc, chan, | |
2097 | conf->channel_type); | |
2098 | } | |
2099 | } | |
2100 | ||
ff37e337 S |
2101 | /**********************/ |
2102 | /* mac80211 callbacks */ | |
2103 | /**********************/ | |
2104 | ||
75d7839f LR |
2105 | /* |
2106 | * (Re)start btcoex timers | |
2107 | */ | |
2108 | static void ath9k_btcoex_timer_resume(struct ath_softc *sc) | |
2109 | { | |
2110 | struct ath_btcoex *btcoex = &sc->btcoex; | |
2111 | struct ath_hw *ah = sc->sc_ah; | |
2112 | ||
2113 | DPRINTF(ah, ATH_DBG_BTCOEX, "Starting btcoex timers"); | |
2114 | ||
2115 | /* make sure duty cycle timer is also stopped when resuming */ | |
2116 | if (btcoex->hw_timer_enabled) | |
2117 | ath_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer); | |
2118 | ||
2119 | btcoex->bt_priority_cnt = 0; | |
2120 | btcoex->bt_priority_time = jiffies; | |
2121 | sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED; | |
2122 | ||
2123 | mod_timer(&btcoex->period_timer, jiffies); | |
2124 | } | |
2125 | ||
8feceb67 | 2126 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 2127 | { |
bce048d7 JM |
2128 | struct ath_wiphy *aphy = hw->priv; |
2129 | struct ath_softc *sc = aphy->sc; | |
af03abec | 2130 | struct ath_hw *ah = sc->sc_ah; |
8feceb67 | 2131 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 2132 | struct ath9k_channel *init_channel; |
82880a7c | 2133 | int r; |
f078f209 | 2134 | |
af03abec | 2135 | DPRINTF(ah, ATH_DBG_CONFIG, "Starting driver with " |
04bd4638 | 2136 | "initial channel: %d MHz\n", curchan->center_freq); |
f078f209 | 2137 | |
141b38b6 S |
2138 | mutex_lock(&sc->mutex); |
2139 | ||
9580a222 JM |
2140 | if (ath9k_wiphy_started(sc)) { |
2141 | if (sc->chan_idx == curchan->hw_value) { | |
2142 | /* | |
2143 | * Already on the operational channel, the new wiphy | |
2144 | * can be marked active. | |
2145 | */ | |
2146 | aphy->state = ATH_WIPHY_ACTIVE; | |
2147 | ieee80211_wake_queues(hw); | |
2148 | } else { | |
2149 | /* | |
2150 | * Another wiphy is on another channel, start the new | |
2151 | * wiphy in paused state. | |
2152 | */ | |
2153 | aphy->state = ATH_WIPHY_PAUSED; | |
2154 | ieee80211_stop_queues(hw); | |
2155 | } | |
2156 | mutex_unlock(&sc->mutex); | |
2157 | return 0; | |
2158 | } | |
2159 | aphy->state = ATH_WIPHY_ACTIVE; | |
2160 | ||
8feceb67 | 2161 | /* setup initial channel */ |
f078f209 | 2162 | |
82880a7c | 2163 | sc->chan_idx = curchan->hw_value; |
f078f209 | 2164 | |
82880a7c | 2165 | init_channel = ath_get_curchannel(sc, hw); |
ff37e337 S |
2166 | |
2167 | /* Reset SERDES registers */ | |
af03abec | 2168 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ff37e337 S |
2169 | |
2170 | /* | |
2171 | * The basic interface to setting the hardware in a good | |
2172 | * state is ``reset''. On return the hardware is known to | |
2173 | * be powered up and with interrupts disabled. This must | |
2174 | * be followed by initialization of the appropriate bits | |
2175 | * and then setup of the interrupt mask. | |
2176 | */ | |
2177 | spin_lock_bh(&sc->sc_resetlock); | |
af03abec | 2178 | r = ath9k_hw_reset(ah, init_channel, false); |
ae8d2858 | 2179 | if (r) { |
af03abec | 2180 | DPRINTF(ah, ATH_DBG_FATAL, |
6b45784f | 2181 | "Unable to reset hardware; reset status %d " |
ae8d2858 LR |
2182 | "(freq %u MHz)\n", r, |
2183 | curchan->center_freq); | |
ff37e337 | 2184 | spin_unlock_bh(&sc->sc_resetlock); |
141b38b6 | 2185 | goto mutex_unlock; |
ff37e337 S |
2186 | } |
2187 | spin_unlock_bh(&sc->sc_resetlock); | |
2188 | ||
2189 | /* | |
2190 | * This is needed only to setup initial state | |
2191 | * but it's best done after a reset. | |
2192 | */ | |
2193 | ath_update_txpow(sc); | |
8feceb67 | 2194 | |
ff37e337 S |
2195 | /* |
2196 | * Setup the hardware after reset: | |
2197 | * The receive engine is set going. | |
2198 | * Frame transmit is handled entirely | |
2199 | * in the frame output path; there's nothing to do | |
2200 | * here except setup the interrupt mask. | |
2201 | */ | |
2202 | if (ath_startrecv(sc) != 0) { | |
af03abec | 2203 | DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n"); |
141b38b6 S |
2204 | r = -EIO; |
2205 | goto mutex_unlock; | |
f078f209 | 2206 | } |
8feceb67 | 2207 | |
ff37e337 | 2208 | /* Setup our intr mask. */ |
17d7904d | 2209 | sc->imask = ATH9K_INT_RX | ATH9K_INT_TX |
ff37e337 S |
2210 | | ATH9K_INT_RXEOL | ATH9K_INT_RXORN |
2211 | | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL; | |
2212 | ||
af03abec | 2213 | if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT) |
17d7904d | 2214 | sc->imask |= ATH9K_INT_GTT; |
ff37e337 | 2215 | |
af03abec | 2216 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
17d7904d | 2217 | sc->imask |= ATH9K_INT_CST; |
ff37e337 | 2218 | |
ce111bad | 2219 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
2220 | |
2221 | sc->sc_flags &= ~SC_OP_INVALID; | |
2222 | ||
2223 | /* Disable BMISS interrupt when we're not associated */ | |
17d7904d | 2224 | sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
af03abec | 2225 | ath9k_hw_set_interrupts(ah, sc->imask); |
ff37e337 | 2226 | |
bce048d7 | 2227 | ieee80211_wake_queues(hw); |
ff37e337 | 2228 | |
42935eca | 2229 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
164ace38 | 2230 | |
766ec4a9 LR |
2231 | if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && |
2232 | !ah->btcoex_hw.enabled) { | |
5e197292 LR |
2233 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, |
2234 | AR_STOMP_LOW_WLAN_WGHT); | |
af03abec | 2235 | ath9k_hw_btcoex_enable(ah); |
f985ad12 | 2236 | |
7b6840ab | 2237 | ath_pcie_aspm_disable(sc); |
766ec4a9 | 2238 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 2239 | ath9k_btcoex_timer_resume(sc); |
1773912b VT |
2240 | } |
2241 | ||
141b38b6 S |
2242 | mutex_unlock: |
2243 | mutex_unlock(&sc->mutex); | |
2244 | ||
ae8d2858 | 2245 | return r; |
f078f209 LR |
2246 | } |
2247 | ||
8feceb67 VT |
2248 | static int ath9k_tx(struct ieee80211_hw *hw, |
2249 | struct sk_buff *skb) | |
f078f209 | 2250 | { |
528f0c6b | 2251 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
bce048d7 JM |
2252 | struct ath_wiphy *aphy = hw->priv; |
2253 | struct ath_softc *sc = aphy->sc; | |
528f0c6b | 2254 | struct ath_tx_control txctl; |
8feceb67 | 2255 | int hdrlen, padsize; |
528f0c6b | 2256 | |
8089cc47 | 2257 | if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { |
ee166a0e JM |
2258 | printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state " |
2259 | "%d\n", wiphy_name(hw->wiphy), aphy->state); | |
2260 | goto exit; | |
2261 | } | |
2262 | ||
96148326 | 2263 | if (sc->ps_enabled) { |
dc8c4585 JM |
2264 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
2265 | /* | |
2266 | * mac80211 does not set PM field for normal data frames, so we | |
2267 | * need to update that based on the current PS mode. | |
2268 | */ | |
2269 | if (ieee80211_is_data(hdr->frame_control) && | |
2270 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
2271 | !ieee80211_has_pm(hdr->frame_control)) { | |
4d6b228d | 2272 | DPRINTF(sc->sc_ah, ATH_DBG_PS, "Add PM=1 for a TX frame " |
dc8c4585 JM |
2273 | "while in PS mode\n"); |
2274 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); | |
2275 | } | |
2276 | } | |
2277 | ||
9a23f9ca JM |
2278 | if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { |
2279 | /* | |
2280 | * We are using PS-Poll and mac80211 can request TX while in | |
2281 | * power save mode. Need to wake up hardware for the TX to be | |
2282 | * completed and if needed, also for RX of buffered frames. | |
2283 | */ | |
2284 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
2285 | ath9k_ps_wakeup(sc); | |
2286 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
2287 | if (ieee80211_is_pspoll(hdr->frame_control)) { | |
4d6b228d | 2288 | DPRINTF(sc->sc_ah, ATH_DBG_PS, "Sending PS-Poll to pick a " |
9a23f9ca JM |
2289 | "buffered frame\n"); |
2290 | sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA; | |
2291 | } else { | |
4d6b228d | 2292 | DPRINTF(sc->sc_ah, ATH_DBG_PS, "Wake up to complete TX\n"); |
9a23f9ca JM |
2293 | sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK; |
2294 | } | |
2295 | /* | |
2296 | * The actual restore operation will happen only after | |
2297 | * the sc_flags bit is cleared. We are just dropping | |
2298 | * the ps_usecount here. | |
2299 | */ | |
2300 | ath9k_ps_restore(sc); | |
2301 | } | |
2302 | ||
528f0c6b | 2303 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 | 2304 | |
8feceb67 VT |
2305 | /* |
2306 | * As a temporary workaround, assign seq# here; this will likely need | |
2307 | * to be cleaned up to work better with Beacon transmission and virtual | |
2308 | * BSSes. | |
2309 | */ | |
2310 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
2311 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
2312 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) | |
b77f483f | 2313 | sc->tx.seq_no += 0x10; |
8feceb67 | 2314 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
b77f483f | 2315 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); |
8feceb67 | 2316 | } |
f078f209 | 2317 | |
8feceb67 VT |
2318 | /* Add the padding after the header if this is not already done */ |
2319 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
2320 | if (hdrlen & 3) { | |
2321 | padsize = hdrlen % 4; | |
2322 | if (skb_headroom(skb) < padsize) | |
2323 | return -1; | |
2324 | skb_push(skb, padsize); | |
2325 | memmove(skb->data, skb->data + padsize, hdrlen); | |
2326 | } | |
2327 | ||
528f0c6b S |
2328 | /* Check if a tx queue is available */ |
2329 | ||
2330 | txctl.txq = ath_test_get_txq(sc, skb); | |
2331 | if (!txctl.txq) | |
2332 | goto exit; | |
2333 | ||
4d6b228d | 2334 | DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 2335 | |
c52f33d0 | 2336 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
4d6b228d | 2337 | DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 2338 | goto exit; |
8feceb67 VT |
2339 | } |
2340 | ||
528f0c6b S |
2341 | return 0; |
2342 | exit: | |
2343 | dev_kfree_skb_any(skb); | |
8feceb67 | 2344 | return 0; |
f078f209 LR |
2345 | } |
2346 | ||
75d7839f LR |
2347 | /* |
2348 | * Pause btcoex timer and bt duty cycle timer | |
2349 | */ | |
2350 | static void ath9k_btcoex_timer_pause(struct ath_softc *sc) | |
2351 | { | |
2352 | struct ath_btcoex *btcoex = &sc->btcoex; | |
2353 | struct ath_hw *ah = sc->sc_ah; | |
2354 | ||
2355 | del_timer_sync(&btcoex->period_timer); | |
2356 | ||
2357 | if (btcoex->hw_timer_enabled) | |
2358 | ath_gen_timer_stop(ah, btcoex->no_stomp_timer); | |
2359 | ||
2360 | btcoex->hw_timer_enabled = false; | |
2361 | } | |
2362 | ||
8feceb67 | 2363 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 2364 | { |
bce048d7 JM |
2365 | struct ath_wiphy *aphy = hw->priv; |
2366 | struct ath_softc *sc = aphy->sc; | |
af03abec | 2367 | struct ath_hw *ah = sc->sc_ah; |
f078f209 | 2368 | |
4c483817 S |
2369 | mutex_lock(&sc->mutex); |
2370 | ||
9580a222 JM |
2371 | aphy->state = ATH_WIPHY_INACTIVE; |
2372 | ||
c94dbff7 LR |
2373 | cancel_delayed_work_sync(&sc->ath_led_blink_work); |
2374 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
2375 | ||
2376 | if (!sc->num_sec_wiphy) { | |
2377 | cancel_delayed_work_sync(&sc->wiphy_work); | |
2378 | cancel_work_sync(&sc->chan_work); | |
2379 | } | |
2380 | ||
9c84b797 | 2381 | if (sc->sc_flags & SC_OP_INVALID) { |
af03abec | 2382 | DPRINTF(ah, ATH_DBG_ANY, "Device not present\n"); |
4c483817 | 2383 | mutex_unlock(&sc->mutex); |
9c84b797 S |
2384 | return; |
2385 | } | |
8feceb67 | 2386 | |
9580a222 JM |
2387 | if (ath9k_wiphy_started(sc)) { |
2388 | mutex_unlock(&sc->mutex); | |
2389 | return; /* another wiphy still in use */ | |
2390 | } | |
2391 | ||
766ec4a9 | 2392 | if (ah->btcoex_hw.enabled) { |
af03abec | 2393 | ath9k_hw_btcoex_disable(ah); |
766ec4a9 | 2394 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 2395 | ath9k_btcoex_timer_pause(sc); |
1773912b VT |
2396 | } |
2397 | ||
ff37e337 S |
2398 | /* make sure h/w will not generate any interrupt |
2399 | * before setting the invalid flag. */ | |
af03abec | 2400 | ath9k_hw_set_interrupts(ah, 0); |
ff37e337 S |
2401 | |
2402 | if (!(sc->sc_flags & SC_OP_INVALID)) { | |
043a0405 | 2403 | ath_drain_all_txq(sc, false); |
ff37e337 | 2404 | ath_stoprecv(sc); |
af03abec | 2405 | ath9k_hw_phy_disable(ah); |
ff37e337 | 2406 | } else |
b77f483f | 2407 | sc->rx.rxlink = NULL; |
ff37e337 | 2408 | |
ff37e337 | 2409 | /* disable HAL and put h/w to sleep */ |
af03abec LR |
2410 | ath9k_hw_disable(ah); |
2411 | ath9k_hw_configpcipowersave(ah, 1, 1); | |
9ecdef4b | 2412 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
ff37e337 S |
2413 | |
2414 | sc->sc_flags |= SC_OP_INVALID; | |
500c064d | 2415 | |
141b38b6 S |
2416 | mutex_unlock(&sc->mutex); |
2417 | ||
af03abec | 2418 | DPRINTF(ah, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
2419 | } |
2420 | ||
8feceb67 VT |
2421 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
2422 | struct ieee80211_if_init_conf *conf) | |
f078f209 | 2423 | { |
bce048d7 JM |
2424 | struct ath_wiphy *aphy = hw->priv; |
2425 | struct ath_softc *sc = aphy->sc; | |
17d7904d | 2426 | struct ath_vif *avp = (void *)conf->vif->drv_priv; |
d97809db | 2427 | enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; |
2c3db3d5 | 2428 | int ret = 0; |
8feceb67 | 2429 | |
141b38b6 S |
2430 | mutex_lock(&sc->mutex); |
2431 | ||
8ca21f01 JM |
2432 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) && |
2433 | sc->nvifs > 0) { | |
2434 | ret = -ENOBUFS; | |
2435 | goto out; | |
2436 | } | |
2437 | ||
8feceb67 | 2438 | switch (conf->type) { |
05c914fe | 2439 | case NL80211_IFTYPE_STATION: |
d97809db | 2440 | ic_opmode = NL80211_IFTYPE_STATION; |
f078f209 | 2441 | break; |
05c914fe | 2442 | case NL80211_IFTYPE_ADHOC: |
05c914fe | 2443 | case NL80211_IFTYPE_AP: |
9cb5412b | 2444 | case NL80211_IFTYPE_MESH_POINT: |
2c3db3d5 JM |
2445 | if (sc->nbcnvifs >= ATH_BCBUF) { |
2446 | ret = -ENOBUFS; | |
2447 | goto out; | |
2448 | } | |
9cb5412b | 2449 | ic_opmode = conf->type; |
f078f209 LR |
2450 | break; |
2451 | default: | |
4d6b228d | 2452 | DPRINTF(sc->sc_ah, ATH_DBG_FATAL, |
04bd4638 | 2453 | "Interface type %d not yet supported\n", conf->type); |
2c3db3d5 JM |
2454 | ret = -EOPNOTSUPP; |
2455 | goto out; | |
f078f209 LR |
2456 | } |
2457 | ||
4d6b228d | 2458 | DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode); |
8feceb67 | 2459 | |
17d7904d | 2460 | /* Set the VIF opmode */ |
5640b08e S |
2461 | avp->av_opmode = ic_opmode; |
2462 | avp->av_bslot = -1; | |
2463 | ||
2c3db3d5 | 2464 | sc->nvifs++; |
8ca21f01 JM |
2465 | |
2466 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) | |
2467 | ath9k_set_bssid_mask(hw); | |
2468 | ||
2c3db3d5 JM |
2469 | if (sc->nvifs > 1) |
2470 | goto out; /* skip global settings for secondary vif */ | |
2471 | ||
b238e90e | 2472 | if (ic_opmode == NL80211_IFTYPE_AP) { |
5640b08e | 2473 | ath9k_hw_set_tsfadjust(sc->sc_ah, 1); |
b238e90e S |
2474 | sc->sc_flags |= SC_OP_TSF_RESET; |
2475 | } | |
5640b08e | 2476 | |
5640b08e | 2477 | /* Set the device opmode */ |
2660b81a | 2478 | sc->sc_ah->opmode = ic_opmode; |
5640b08e | 2479 | |
4e30ffa2 VN |
2480 | /* |
2481 | * Enable MIB interrupts when there are hardware phy counters. | |
2482 | * Note we only do this (at the moment) for station mode. | |
2483 | */ | |
4af9cf4f | 2484 | if ((conf->type == NL80211_IFTYPE_STATION) || |
9cb5412b PE |
2485 | (conf->type == NL80211_IFTYPE_ADHOC) || |
2486 | (conf->type == NL80211_IFTYPE_MESH_POINT)) { | |
1aa8e847 | 2487 | sc->imask |= ATH9K_INT_MIB; |
4af9cf4f S |
2488 | sc->imask |= ATH9K_INT_TSFOOR; |
2489 | } | |
2490 | ||
17d7904d | 2491 | ath9k_hw_set_interrupts(sc->sc_ah, sc->imask); |
4e30ffa2 | 2492 | |
f38faa31 SB |
2493 | if (conf->type == NL80211_IFTYPE_AP || |
2494 | conf->type == NL80211_IFTYPE_ADHOC || | |
2495 | conf->type == NL80211_IFTYPE_MONITOR) | |
415f738e | 2496 | ath_start_ani(sc); |
6f255425 | 2497 | |
2c3db3d5 | 2498 | out: |
141b38b6 | 2499 | mutex_unlock(&sc->mutex); |
2c3db3d5 | 2500 | return ret; |
f078f209 LR |
2501 | } |
2502 | ||
8feceb67 VT |
2503 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
2504 | struct ieee80211_if_init_conf *conf) | |
f078f209 | 2505 | { |
bce048d7 JM |
2506 | struct ath_wiphy *aphy = hw->priv; |
2507 | struct ath_softc *sc = aphy->sc; | |
17d7904d | 2508 | struct ath_vif *avp = (void *)conf->vif->drv_priv; |
2c3db3d5 | 2509 | int i; |
f078f209 | 2510 | |
4d6b228d | 2511 | DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 2512 | |
141b38b6 S |
2513 | mutex_lock(&sc->mutex); |
2514 | ||
6f255425 | 2515 | /* Stop ANI */ |
17d7904d | 2516 | del_timer_sync(&sc->ani.timer); |
580f0b8a | 2517 | |
8feceb67 | 2518 | /* Reclaim beacon resources */ |
9cb5412b PE |
2519 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || |
2520 | (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) || | |
2521 | (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) { | |
b77f483f | 2522 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); |
8feceb67 | 2523 | ath_beacon_return(sc, avp); |
580f0b8a | 2524 | } |
f078f209 | 2525 | |
8feceb67 | 2526 | sc->sc_flags &= ~SC_OP_BEACONS; |
f078f209 | 2527 | |
2c3db3d5 JM |
2528 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { |
2529 | if (sc->beacon.bslot[i] == conf->vif) { | |
2530 | printk(KERN_DEBUG "%s: vif had allocated beacon " | |
2531 | "slot\n", __func__); | |
2532 | sc->beacon.bslot[i] = NULL; | |
c52f33d0 | 2533 | sc->beacon.bslot_aphy[i] = NULL; |
2c3db3d5 JM |
2534 | } |
2535 | } | |
2536 | ||
17d7904d | 2537 | sc->nvifs--; |
141b38b6 S |
2538 | |
2539 | mutex_unlock(&sc->mutex); | |
f078f209 LR |
2540 | } |
2541 | ||
e8975581 | 2542 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 2543 | { |
bce048d7 JM |
2544 | struct ath_wiphy *aphy = hw->priv; |
2545 | struct ath_softc *sc = aphy->sc; | |
e8975581 | 2546 | struct ieee80211_conf *conf = &hw->conf; |
8782b41d | 2547 | struct ath_hw *ah = sc->sc_ah; |
64839170 | 2548 | bool all_wiphys_idle = false, disable_radio = false; |
f078f209 | 2549 | |
aa33de09 | 2550 | mutex_lock(&sc->mutex); |
141b38b6 | 2551 | |
64839170 LR |
2552 | /* Leave this as the first check */ |
2553 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { | |
2554 | ||
2555 | spin_lock_bh(&sc->wiphy_lock); | |
2556 | all_wiphys_idle = ath9k_all_wiphys_idle(sc); | |
2557 | spin_unlock_bh(&sc->wiphy_lock); | |
2558 | ||
2559 | if (conf->flags & IEEE80211_CONF_IDLE){ | |
2560 | if (all_wiphys_idle) | |
2561 | disable_radio = true; | |
2562 | } | |
2563 | else if (all_wiphys_idle) { | |
2564 | ath_radio_enable(sc); | |
4d6b228d | 2565 | DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, |
64839170 LR |
2566 | "not-idle: enabling radio\n"); |
2567 | } | |
2568 | } | |
2569 | ||
3cbb5dd7 VN |
2570 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
2571 | if (conf->flags & IEEE80211_CONF_PS) { | |
8782b41d VN |
2572 | if (!(ah->caps.hw_caps & |
2573 | ATH9K_HW_CAP_AUTOSLEEP)) { | |
2574 | if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
2575 | sc->imask |= ATH9K_INT_TIM_TIMER; | |
2576 | ath9k_hw_set_interrupts(sc->sc_ah, | |
2577 | sc->imask); | |
2578 | } | |
2579 | ath9k_hw_setrxabort(sc->sc_ah, 1); | |
3cbb5dd7 | 2580 | } |
96148326 | 2581 | sc->ps_enabled = true; |
3cbb5dd7 | 2582 | } else { |
96148326 | 2583 | sc->ps_enabled = false; |
9ecdef4b | 2584 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
8782b41d VN |
2585 | if (!(ah->caps.hw_caps & |
2586 | ATH9K_HW_CAP_AUTOSLEEP)) { | |
2587 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca JM |
2588 | sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON | |
2589 | SC_OP_WAIT_FOR_CAB | | |
2590 | SC_OP_WAIT_FOR_PSPOLL_DATA | | |
2591 | SC_OP_WAIT_FOR_TX_ACK); | |
8782b41d VN |
2592 | if (sc->imask & ATH9K_INT_TIM_TIMER) { |
2593 | sc->imask &= ~ATH9K_INT_TIM_TIMER; | |
2594 | ath9k_hw_set_interrupts(sc->sc_ah, | |
2595 | sc->imask); | |
2596 | } | |
3cbb5dd7 VN |
2597 | } |
2598 | } | |
2599 | } | |
2600 | ||
4797938c | 2601 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
99405f93 | 2602 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 2603 | int pos = curchan->hw_value; |
ae5eb026 | 2604 | |
0e2dedf9 JM |
2605 | aphy->chan_idx = pos; |
2606 | aphy->chan_is_ht = conf_is_ht(conf); | |
2607 | ||
8089cc47 JM |
2608 | if (aphy->state == ATH_WIPHY_SCAN || |
2609 | aphy->state == ATH_WIPHY_ACTIVE) | |
2610 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
2611 | else { | |
2612 | /* | |
2613 | * Do not change operational channel based on a paused | |
2614 | * wiphy changes. | |
2615 | */ | |
2616 | goto skip_chan_change; | |
2617 | } | |
0e2dedf9 | 2618 | |
4d6b228d | 2619 | DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set channel: %d MHz\n", |
04bd4638 | 2620 | curchan->center_freq); |
f078f209 | 2621 | |
5f8e077c | 2622 | /* XXX: remove me eventualy */ |
0e2dedf9 | 2623 | ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); |
e11602b7 | 2624 | |
ecf70441 | 2625 | ath_update_chainmask(sc, conf_is_ht(conf)); |
86060f0d | 2626 | |
0e2dedf9 | 2627 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
4d6b228d | 2628 | DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unable to set channel\n"); |
aa33de09 | 2629 | mutex_unlock(&sc->mutex); |
e11602b7 S |
2630 | return -EINVAL; |
2631 | } | |
094d05dc | 2632 | } |
f078f209 | 2633 | |
8089cc47 | 2634 | skip_chan_change: |
5c020dc6 | 2635 | if (changed & IEEE80211_CONF_CHANGE_POWER) |
17d7904d | 2636 | sc->config.txpowlimit = 2 * conf->power_level; |
f078f209 | 2637 | |
64839170 | 2638 | if (disable_radio) { |
4d6b228d | 2639 | DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "idle: disabling radio\n"); |
64839170 LR |
2640 | ath_radio_disable(sc); |
2641 | } | |
2642 | ||
aa33de09 | 2643 | mutex_unlock(&sc->mutex); |
141b38b6 | 2644 | |
f078f209 LR |
2645 | return 0; |
2646 | } | |
2647 | ||
8feceb67 VT |
2648 | #define SUPPORTED_FILTERS \ |
2649 | (FIF_PROMISC_IN_BSS | \ | |
2650 | FIF_ALLMULTI | \ | |
2651 | FIF_CONTROL | \ | |
af6a3fc7 | 2652 | FIF_PSPOLL | \ |
8feceb67 VT |
2653 | FIF_OTHER_BSS | \ |
2654 | FIF_BCN_PRBRESP_PROMISC | \ | |
2655 | FIF_FCSFAIL) | |
c83be688 | 2656 | |
8feceb67 VT |
2657 | /* FIXME: sc->sc_full_reset ? */ |
2658 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
2659 | unsigned int changed_flags, | |
2660 | unsigned int *total_flags, | |
3ac64bee | 2661 | u64 multicast) |
8feceb67 | 2662 | { |
bce048d7 JM |
2663 | struct ath_wiphy *aphy = hw->priv; |
2664 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 2665 | u32 rfilt; |
f078f209 | 2666 | |
8feceb67 VT |
2667 | changed_flags &= SUPPORTED_FILTERS; |
2668 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 2669 | |
b77f483f | 2670 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 2671 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
2672 | rfilt = ath_calcrxfilter(sc); |
2673 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 2674 | ath9k_ps_restore(sc); |
f078f209 | 2675 | |
4d6b228d | 2676 | DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", rfilt); |
8feceb67 | 2677 | } |
f078f209 | 2678 | |
8feceb67 VT |
2679 | static void ath9k_sta_notify(struct ieee80211_hw *hw, |
2680 | struct ieee80211_vif *vif, | |
2681 | enum sta_notify_cmd cmd, | |
17741cdc | 2682 | struct ieee80211_sta *sta) |
8feceb67 | 2683 | { |
bce048d7 JM |
2684 | struct ath_wiphy *aphy = hw->priv; |
2685 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 2686 | |
8feceb67 VT |
2687 | switch (cmd) { |
2688 | case STA_NOTIFY_ADD: | |
5640b08e | 2689 | ath_node_attach(sc, sta); |
8feceb67 VT |
2690 | break; |
2691 | case STA_NOTIFY_REMOVE: | |
b5aa9bf9 | 2692 | ath_node_detach(sc, sta); |
8feceb67 VT |
2693 | break; |
2694 | default: | |
2695 | break; | |
2696 | } | |
f078f209 LR |
2697 | } |
2698 | ||
141b38b6 | 2699 | static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
8feceb67 | 2700 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 2701 | { |
bce048d7 JM |
2702 | struct ath_wiphy *aphy = hw->priv; |
2703 | struct ath_softc *sc = aphy->sc; | |
8feceb67 VT |
2704 | struct ath9k_tx_queue_info qi; |
2705 | int ret = 0, qnum; | |
f078f209 | 2706 | |
8feceb67 VT |
2707 | if (queue >= WME_NUM_AC) |
2708 | return 0; | |
f078f209 | 2709 | |
141b38b6 S |
2710 | mutex_lock(&sc->mutex); |
2711 | ||
1ffb0610 S |
2712 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
2713 | ||
8feceb67 VT |
2714 | qi.tqi_aifs = params->aifs; |
2715 | qi.tqi_cwmin = params->cw_min; | |
2716 | qi.tqi_cwmax = params->cw_max; | |
2717 | qi.tqi_burstTime = params->txop; | |
2718 | qnum = ath_get_hal_qnum(queue, sc); | |
f078f209 | 2719 | |
4d6b228d | 2720 | DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, |
04bd4638 | 2721 | "Configure tx [queue/halq] [%d/%d], " |
8feceb67 | 2722 | "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", |
04bd4638 S |
2723 | queue, qnum, params->aifs, params->cw_min, |
2724 | params->cw_max, params->txop); | |
f078f209 | 2725 | |
8feceb67 VT |
2726 | ret = ath_txq_update(sc, qnum, &qi); |
2727 | if (ret) | |
4d6b228d | 2728 | DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "TXQ Update failed\n"); |
f078f209 | 2729 | |
141b38b6 S |
2730 | mutex_unlock(&sc->mutex); |
2731 | ||
8feceb67 VT |
2732 | return ret; |
2733 | } | |
f078f209 | 2734 | |
8feceb67 VT |
2735 | static int ath9k_set_key(struct ieee80211_hw *hw, |
2736 | enum set_key_cmd cmd, | |
dc822b5d JB |
2737 | struct ieee80211_vif *vif, |
2738 | struct ieee80211_sta *sta, | |
8feceb67 VT |
2739 | struct ieee80211_key_conf *key) |
2740 | { | |
bce048d7 JM |
2741 | struct ath_wiphy *aphy = hw->priv; |
2742 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 2743 | int ret = 0; |
f078f209 | 2744 | |
b3bd89ce JM |
2745 | if (modparam_nohwcrypt) |
2746 | return -ENOSPC; | |
2747 | ||
141b38b6 | 2748 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 2749 | ath9k_ps_wakeup(sc); |
4d6b228d | 2750 | DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW Key\n"); |
f078f209 | 2751 | |
8feceb67 VT |
2752 | switch (cmd) { |
2753 | case SET_KEY: | |
3f53dd64 | 2754 | ret = ath_key_config(sc, vif, sta, key); |
6ace2891 JM |
2755 | if (ret >= 0) { |
2756 | key->hw_key_idx = ret; | |
8feceb67 VT |
2757 | /* push IV and Michael MIC generation to stack */ |
2758 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
2759 | if (key->alg == ALG_TKIP) | |
2760 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; | |
0ced0e17 JM |
2761 | if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP) |
2762 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; | |
6ace2891 | 2763 | ret = 0; |
8feceb67 VT |
2764 | } |
2765 | break; | |
2766 | case DISABLE_KEY: | |
2767 | ath_key_delete(sc, key); | |
8feceb67 VT |
2768 | break; |
2769 | default: | |
2770 | ret = -EINVAL; | |
2771 | } | |
f078f209 | 2772 | |
3cbb5dd7 | 2773 | ath9k_ps_restore(sc); |
141b38b6 S |
2774 | mutex_unlock(&sc->mutex); |
2775 | ||
8feceb67 VT |
2776 | return ret; |
2777 | } | |
f078f209 | 2778 | |
8feceb67 VT |
2779 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
2780 | struct ieee80211_vif *vif, | |
2781 | struct ieee80211_bss_conf *bss_conf, | |
2782 | u32 changed) | |
2783 | { | |
bce048d7 JM |
2784 | struct ath_wiphy *aphy = hw->priv; |
2785 | struct ath_softc *sc = aphy->sc; | |
2d0ddec5 JB |
2786 | struct ath_hw *ah = sc->sc_ah; |
2787 | struct ath_vif *avp = (void *)vif->drv_priv; | |
2788 | u32 rfilt = 0; | |
2789 | int error, i; | |
f078f209 | 2790 | |
141b38b6 S |
2791 | mutex_lock(&sc->mutex); |
2792 | ||
2d0ddec5 JB |
2793 | /* |
2794 | * TODO: Need to decide which hw opmode to use for | |
2795 | * multi-interface cases | |
2796 | * XXX: This belongs into add_interface! | |
2797 | */ | |
2798 | if (vif->type == NL80211_IFTYPE_AP && | |
2799 | ah->opmode != NL80211_IFTYPE_AP) { | |
2800 | ah->opmode = NL80211_IFTYPE_STATION; | |
2801 | ath9k_hw_setopmode(ah); | |
2802 | memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN); | |
2803 | sc->curaid = 0; | |
2804 | ath9k_hw_write_associd(sc); | |
2805 | /* Request full reset to get hw opmode changed properly */ | |
2806 | sc->sc_flags |= SC_OP_FULL_RESET; | |
2807 | } | |
2808 | ||
2809 | if ((changed & BSS_CHANGED_BSSID) && | |
2810 | !is_zero_ether_addr(bss_conf->bssid)) { | |
2811 | switch (vif->type) { | |
2812 | case NL80211_IFTYPE_STATION: | |
2813 | case NL80211_IFTYPE_ADHOC: | |
2814 | case NL80211_IFTYPE_MESH_POINT: | |
2815 | /* Set BSSID */ | |
2816 | memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN); | |
2817 | memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); | |
2818 | sc->curaid = 0; | |
2819 | ath9k_hw_write_associd(sc); | |
2820 | ||
2821 | /* Set aggregation protection mode parameters */ | |
2822 | sc->config.ath_aggr_prot = 0; | |
2823 | ||
4d6b228d | 2824 | DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, |
2d0ddec5 JB |
2825 | "RX filter 0x%x bssid %pM aid 0x%x\n", |
2826 | rfilt, sc->curbssid, sc->curaid); | |
2827 | ||
2828 | /* need to reconfigure the beacon */ | |
2829 | sc->sc_flags &= ~SC_OP_BEACONS ; | |
2830 | ||
2831 | break; | |
2832 | default: | |
2833 | break; | |
2834 | } | |
2835 | } | |
2836 | ||
2837 | if ((vif->type == NL80211_IFTYPE_ADHOC) || | |
2838 | (vif->type == NL80211_IFTYPE_AP) || | |
2839 | (vif->type == NL80211_IFTYPE_MESH_POINT)) { | |
2840 | if ((changed & BSS_CHANGED_BEACON) || | |
2841 | (changed & BSS_CHANGED_BEACON_ENABLED && | |
2842 | bss_conf->enable_beacon)) { | |
2843 | /* | |
2844 | * Allocate and setup the beacon frame. | |
2845 | * | |
2846 | * Stop any previous beacon DMA. This may be | |
2847 | * necessary, for example, when an ibss merge | |
2848 | * causes reconfiguration; we may be called | |
2849 | * with beacon transmission active. | |
2850 | */ | |
2851 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2852 | ||
2853 | error = ath_beacon_alloc(aphy, vif); | |
2854 | if (!error) | |
2855 | ath_beacon_config(sc, vif); | |
2856 | } | |
2857 | } | |
2858 | ||
2859 | /* Check for WLAN_CAPABILITY_PRIVACY ? */ | |
2860 | if ((avp->av_opmode != NL80211_IFTYPE_STATION)) { | |
2861 | for (i = 0; i < IEEE80211_WEP_NKID; i++) | |
2862 | if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i)) | |
2863 | ath9k_hw_keysetmac(sc->sc_ah, | |
2864 | (u16)i, | |
2865 | sc->curbssid); | |
2866 | } | |
2867 | ||
2868 | /* Only legacy IBSS for now */ | |
2869 | if (vif->type == NL80211_IFTYPE_ADHOC) | |
2870 | ath_update_chainmask(sc, 0); | |
2871 | ||
8feceb67 | 2872 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
4d6b228d | 2873 | DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
8feceb67 VT |
2874 | bss_conf->use_short_preamble); |
2875 | if (bss_conf->use_short_preamble) | |
2876 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
2877 | else | |
2878 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
2879 | } | |
f078f209 | 2880 | |
8feceb67 | 2881 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
4d6b228d | 2882 | DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
8feceb67 VT |
2883 | bss_conf->use_cts_prot); |
2884 | if (bss_conf->use_cts_prot && | |
2885 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
2886 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
2887 | else | |
2888 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
2889 | } | |
f078f209 | 2890 | |
8feceb67 | 2891 | if (changed & BSS_CHANGED_ASSOC) { |
4d6b228d | 2892 | DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", |
8feceb67 | 2893 | bss_conf->assoc); |
5640b08e | 2894 | ath9k_bss_assoc_info(sc, vif, bss_conf); |
8feceb67 | 2895 | } |
141b38b6 | 2896 | |
57c4d7b4 JB |
2897 | /* |
2898 | * The HW TSF has to be reset when the beacon interval changes. | |
2899 | * We set the flag here, and ath_beacon_config_ap() would take this | |
2900 | * into account when it gets called through the subsequent | |
2901 | * config_interface() call - with IFCC_BEACON in the changed field. | |
2902 | */ | |
2903 | ||
2904 | if (changed & BSS_CHANGED_BEACON_INT) { | |
2905 | sc->sc_flags |= SC_OP_TSF_RESET; | |
2906 | sc->beacon_interval = bss_conf->beacon_int; | |
2907 | } | |
2908 | ||
141b38b6 | 2909 | mutex_unlock(&sc->mutex); |
8feceb67 | 2910 | } |
f078f209 | 2911 | |
8feceb67 VT |
2912 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) |
2913 | { | |
2914 | u64 tsf; | |
bce048d7 JM |
2915 | struct ath_wiphy *aphy = hw->priv; |
2916 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 2917 | |
141b38b6 S |
2918 | mutex_lock(&sc->mutex); |
2919 | tsf = ath9k_hw_gettsf64(sc->sc_ah); | |
2920 | mutex_unlock(&sc->mutex); | |
f078f209 | 2921 | |
8feceb67 VT |
2922 | return tsf; |
2923 | } | |
f078f209 | 2924 | |
3b5d665b AF |
2925 | static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) |
2926 | { | |
bce048d7 JM |
2927 | struct ath_wiphy *aphy = hw->priv; |
2928 | struct ath_softc *sc = aphy->sc; | |
3b5d665b | 2929 | |
141b38b6 S |
2930 | mutex_lock(&sc->mutex); |
2931 | ath9k_hw_settsf64(sc->sc_ah, tsf); | |
2932 | mutex_unlock(&sc->mutex); | |
3b5d665b AF |
2933 | } |
2934 | ||
8feceb67 VT |
2935 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) |
2936 | { | |
bce048d7 JM |
2937 | struct ath_wiphy *aphy = hw->priv; |
2938 | struct ath_softc *sc = aphy->sc; | |
c83be688 | 2939 | |
141b38b6 | 2940 | mutex_lock(&sc->mutex); |
21526d57 LR |
2941 | |
2942 | ath9k_ps_wakeup(sc); | |
141b38b6 | 2943 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
2944 | ath9k_ps_restore(sc); |
2945 | ||
141b38b6 | 2946 | mutex_unlock(&sc->mutex); |
8feceb67 | 2947 | } |
f078f209 | 2948 | |
8feceb67 | 2949 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
141b38b6 S |
2950 | enum ieee80211_ampdu_mlme_action action, |
2951 | struct ieee80211_sta *sta, | |
2952 | u16 tid, u16 *ssn) | |
8feceb67 | 2953 | { |
bce048d7 JM |
2954 | struct ath_wiphy *aphy = hw->priv; |
2955 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 2956 | int ret = 0; |
f078f209 | 2957 | |
8feceb67 VT |
2958 | switch (action) { |
2959 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
2960 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
2961 | ret = -ENOTSUPP; | |
8feceb67 VT |
2962 | break; |
2963 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
2964 | break; |
2965 | case IEEE80211_AMPDU_TX_START: | |
f83da965 S |
2966 | ath_tx_aggr_start(sc, sta, tid, ssn); |
2967 | ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid); | |
8feceb67 VT |
2968 | break; |
2969 | case IEEE80211_AMPDU_TX_STOP: | |
f83da965 | 2970 | ath_tx_aggr_stop(sc, sta, tid); |
17741cdc | 2971 | ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid); |
8feceb67 | 2972 | break; |
b1720231 | 2973 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8469cdef S |
2974 | ath_tx_aggr_resume(sc, sta, tid); |
2975 | break; | |
8feceb67 | 2976 | default: |
4d6b228d | 2977 | DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unknown AMPDU action\n"); |
8feceb67 VT |
2978 | } |
2979 | ||
2980 | return ret; | |
f078f209 LR |
2981 | } |
2982 | ||
0c98de65 S |
2983 | static void ath9k_sw_scan_start(struct ieee80211_hw *hw) |
2984 | { | |
bce048d7 JM |
2985 | struct ath_wiphy *aphy = hw->priv; |
2986 | struct ath_softc *sc = aphy->sc; | |
0c98de65 | 2987 | |
3d832611 | 2988 | mutex_lock(&sc->mutex); |
8089cc47 JM |
2989 | if (ath9k_wiphy_scanning(sc)) { |
2990 | printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the " | |
2991 | "same time\n"); | |
2992 | /* | |
2993 | * Do not allow the concurrent scanning state for now. This | |
2994 | * could be improved with scanning control moved into ath9k. | |
2995 | */ | |
3d832611 | 2996 | mutex_unlock(&sc->mutex); |
8089cc47 JM |
2997 | return; |
2998 | } | |
2999 | ||
3000 | aphy->state = ATH_WIPHY_SCAN; | |
3001 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
3002 | ||
e5f0921a | 3003 | spin_lock_bh(&sc->ani_lock); |
0c98de65 | 3004 | sc->sc_flags |= SC_OP_SCANNING; |
e5f0921a | 3005 | spin_unlock_bh(&sc->ani_lock); |
3d832611 | 3006 | mutex_unlock(&sc->mutex); |
0c98de65 S |
3007 | } |
3008 | ||
3009 | static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) | |
3010 | { | |
bce048d7 JM |
3011 | struct ath_wiphy *aphy = hw->priv; |
3012 | struct ath_softc *sc = aphy->sc; | |
0c98de65 | 3013 | |
3d832611 | 3014 | mutex_lock(&sc->mutex); |
e5f0921a | 3015 | spin_lock_bh(&sc->ani_lock); |
8089cc47 | 3016 | aphy->state = ATH_WIPHY_ACTIVE; |
0c98de65 | 3017 | sc->sc_flags &= ~SC_OP_SCANNING; |
9c07a777 | 3018 | sc->sc_flags |= SC_OP_FULL_RESET; |
e5f0921a | 3019 | spin_unlock_bh(&sc->ani_lock); |
d0bec342 | 3020 | ath_beacon_config(sc, NULL); |
3d832611 | 3021 | mutex_unlock(&sc->mutex); |
0c98de65 S |
3022 | } |
3023 | ||
6baff7f9 | 3024 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
3025 | .tx = ath9k_tx, |
3026 | .start = ath9k_start, | |
3027 | .stop = ath9k_stop, | |
3028 | .add_interface = ath9k_add_interface, | |
3029 | .remove_interface = ath9k_remove_interface, | |
3030 | .config = ath9k_config, | |
8feceb67 | 3031 | .configure_filter = ath9k_configure_filter, |
8feceb67 VT |
3032 | .sta_notify = ath9k_sta_notify, |
3033 | .conf_tx = ath9k_conf_tx, | |
8feceb67 | 3034 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 3035 | .set_key = ath9k_set_key, |
8feceb67 | 3036 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 3037 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 3038 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 3039 | .ampdu_action = ath9k_ampdu_action, |
0c98de65 S |
3040 | .sw_scan_start = ath9k_sw_scan_start, |
3041 | .sw_scan_complete = ath9k_sw_scan_complete, | |
3b319aae | 3042 | .rfkill_poll = ath9k_rfkill_poll_state, |
8feceb67 VT |
3043 | }; |
3044 | ||
392dff83 BP |
3045 | static struct { |
3046 | u32 version; | |
3047 | const char * name; | |
3048 | } ath_mac_bb_names[] = { | |
3049 | { AR_SREV_VERSION_5416_PCI, "5416" }, | |
3050 | { AR_SREV_VERSION_5416_PCIE, "5418" }, | |
3051 | { AR_SREV_VERSION_9100, "9100" }, | |
3052 | { AR_SREV_VERSION_9160, "9160" }, | |
3053 | { AR_SREV_VERSION_9280, "9280" }, | |
ac88b6ec VN |
3054 | { AR_SREV_VERSION_9285, "9285" }, |
3055 | { AR_SREV_VERSION_9287, "9287" } | |
392dff83 BP |
3056 | }; |
3057 | ||
3058 | static struct { | |
3059 | u16 version; | |
3060 | const char * name; | |
3061 | } ath_rf_names[] = { | |
3062 | { 0, "5133" }, | |
3063 | { AR_RAD5133_SREV_MAJOR, "5133" }, | |
3064 | { AR_RAD5122_SREV_MAJOR, "5122" }, | |
3065 | { AR_RAD2133_SREV_MAJOR, "2133" }, | |
3066 | { AR_RAD2122_SREV_MAJOR, "2122" } | |
3067 | }; | |
3068 | ||
3069 | /* | |
3070 | * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. | |
3071 | */ | |
6baff7f9 | 3072 | const char * |
392dff83 BP |
3073 | ath_mac_bb_name(u32 mac_bb_version) |
3074 | { | |
3075 | int i; | |
3076 | ||
3077 | for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { | |
3078 | if (ath_mac_bb_names[i].version == mac_bb_version) { | |
3079 | return ath_mac_bb_names[i].name; | |
3080 | } | |
3081 | } | |
3082 | ||
3083 | return "????"; | |
3084 | } | |
3085 | ||
3086 | /* | |
3087 | * Return the RF name. "????" is returned if the RF is unknown. | |
3088 | */ | |
6baff7f9 | 3089 | const char * |
392dff83 BP |
3090 | ath_rf_name(u16 rf_version) |
3091 | { | |
3092 | int i; | |
3093 | ||
3094 | for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { | |
3095 | if (ath_rf_names[i].version == rf_version) { | |
3096 | return ath_rf_names[i].name; | |
3097 | } | |
3098 | } | |
3099 | ||
3100 | return "????"; | |
3101 | } | |
3102 | ||
6baff7f9 | 3103 | static int __init ath9k_init(void) |
f078f209 | 3104 | { |
ca8a8560 VT |
3105 | int error; |
3106 | ||
ca8a8560 VT |
3107 | /* Register rate control algorithm */ |
3108 | error = ath_rate_control_register(); | |
3109 | if (error != 0) { | |
3110 | printk(KERN_ERR | |
b51bb3cd LR |
3111 | "ath9k: Unable to register rate control " |
3112 | "algorithm: %d\n", | |
ca8a8560 | 3113 | error); |
6baff7f9 | 3114 | goto err_out; |
ca8a8560 VT |
3115 | } |
3116 | ||
19d8bc22 GJ |
3117 | error = ath9k_debug_create_root(); |
3118 | if (error) { | |
3119 | printk(KERN_ERR | |
3120 | "ath9k: Unable to create debugfs root: %d\n", | |
3121 | error); | |
3122 | goto err_rate_unregister; | |
3123 | } | |
3124 | ||
6baff7f9 GJ |
3125 | error = ath_pci_init(); |
3126 | if (error < 0) { | |
f078f209 | 3127 | printk(KERN_ERR |
b51bb3cd | 3128 | "ath9k: No PCI devices found, driver not installed.\n"); |
6baff7f9 | 3129 | error = -ENODEV; |
19d8bc22 | 3130 | goto err_remove_root; |
f078f209 LR |
3131 | } |
3132 | ||
09329d37 GJ |
3133 | error = ath_ahb_init(); |
3134 | if (error < 0) { | |
3135 | error = -ENODEV; | |
3136 | goto err_pci_exit; | |
3137 | } | |
3138 | ||
f078f209 | 3139 | return 0; |
6baff7f9 | 3140 | |
09329d37 GJ |
3141 | err_pci_exit: |
3142 | ath_pci_exit(); | |
3143 | ||
19d8bc22 GJ |
3144 | err_remove_root: |
3145 | ath9k_debug_remove_root(); | |
6baff7f9 GJ |
3146 | err_rate_unregister: |
3147 | ath_rate_control_unregister(); | |
3148 | err_out: | |
3149 | return error; | |
f078f209 | 3150 | } |
6baff7f9 | 3151 | module_init(ath9k_init); |
f078f209 | 3152 | |
6baff7f9 | 3153 | static void __exit ath9k_exit(void) |
f078f209 | 3154 | { |
09329d37 | 3155 | ath_ahb_exit(); |
6baff7f9 | 3156 | ath_pci_exit(); |
19d8bc22 | 3157 | ath9k_debug_remove_root(); |
ca8a8560 | 3158 | ath_rate_control_unregister(); |
04bd4638 | 3159 | printk(KERN_INFO "%s: Driver unloaded\n", dev_info); |
f078f209 | 3160 | } |
6baff7f9 | 3161 | module_exit(ath9k_exit); |