Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
394cf0a1 | 18 | #include "ath9k.h" |
af03abec | 19 | #include "btcoex.h" |
f078f209 | 20 | |
ce111bad LR |
21 | static void ath_cache_conf_rate(struct ath_softc *sc, |
22 | struct ieee80211_conf *conf) | |
ff37e337 | 23 | { |
030bb495 LR |
24 | switch (conf->channel->band) { |
25 | case IEEE80211_BAND_2GHZ: | |
26 | if (conf_is_ht20(conf)) | |
545750d3 | 27 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT20; |
030bb495 | 28 | else if (conf_is_ht40_minus(conf)) |
545750d3 | 29 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS; |
030bb495 | 30 | else if (conf_is_ht40_plus(conf)) |
545750d3 | 31 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS; |
96742256 | 32 | else |
545750d3 | 33 | sc->cur_rate_mode = ATH9K_MODE_11G; |
030bb495 LR |
34 | break; |
35 | case IEEE80211_BAND_5GHZ: | |
36 | if (conf_is_ht20(conf)) | |
545750d3 | 37 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT20; |
030bb495 | 38 | else if (conf_is_ht40_minus(conf)) |
545750d3 | 39 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS; |
030bb495 | 40 | else if (conf_is_ht40_plus(conf)) |
545750d3 | 41 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS; |
030bb495 | 42 | else |
545750d3 | 43 | sc->cur_rate_mode = ATH9K_MODE_11A; |
030bb495 LR |
44 | break; |
45 | default: | |
ce111bad | 46 | BUG_ON(1); |
030bb495 LR |
47 | break; |
48 | } | |
ff37e337 S |
49 | } |
50 | ||
51 | static void ath_update_txpow(struct ath_softc *sc) | |
52 | { | |
cbe61d8a | 53 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 | 54 | |
17d7904d S |
55 | if (sc->curtxpow != sc->config.txpowlimit) { |
56 | ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit); | |
ff37e337 | 57 | /* read back in case value is clamped */ |
9cc3271f | 58 | sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit; |
ff37e337 S |
59 | } |
60 | } | |
61 | ||
62 | static u8 parse_mpdudensity(u8 mpdudensity) | |
63 | { | |
64 | /* | |
65 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
66 | * 0 for no restriction | |
67 | * 1 for 1/4 us | |
68 | * 2 for 1/2 us | |
69 | * 3 for 1 us | |
70 | * 4 for 2 us | |
71 | * 5 for 4 us | |
72 | * 6 for 8 us | |
73 | * 7 for 16 us | |
74 | */ | |
75 | switch (mpdudensity) { | |
76 | case 0: | |
77 | return 0; | |
78 | case 1: | |
79 | case 2: | |
80 | case 3: | |
81 | /* Our lower layer calculations limit our precision to | |
82 | 1 microsecond */ | |
83 | return 1; | |
84 | case 4: | |
85 | return 2; | |
86 | case 5: | |
87 | return 4; | |
88 | case 6: | |
89 | return 8; | |
90 | case 7: | |
91 | return 16; | |
92 | default: | |
93 | return 0; | |
94 | } | |
95 | } | |
96 | ||
82880a7c VT |
97 | static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc, |
98 | struct ieee80211_hw *hw) | |
99 | { | |
100 | struct ieee80211_channel *curchan = hw->conf.channel; | |
101 | struct ath9k_channel *channel; | |
102 | u8 chan_idx; | |
103 | ||
104 | chan_idx = curchan->hw_value; | |
105 | channel = &sc->sc_ah->channels[chan_idx]; | |
106 | ath9k_update_ichannel(sc, hw, channel); | |
107 | return channel; | |
108 | } | |
109 | ||
55624204 | 110 | bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
111 | { |
112 | unsigned long flags; | |
113 | bool ret; | |
114 | ||
9ecdef4b LR |
115 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
116 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
117 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
118 | |
119 | return ret; | |
120 | } | |
121 | ||
a91d75ae LR |
122 | void ath9k_ps_wakeup(struct ath_softc *sc) |
123 | { | |
124 | unsigned long flags; | |
125 | ||
126 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
127 | if (++sc->ps_usecount != 1) | |
128 | goto unlock; | |
129 | ||
9ecdef4b | 130 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae LR |
131 | |
132 | unlock: | |
133 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
134 | } | |
135 | ||
136 | void ath9k_ps_restore(struct ath_softc *sc) | |
137 | { | |
138 | unsigned long flags; | |
139 | ||
140 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
141 | if (--sc->ps_usecount != 0) | |
142 | goto unlock; | |
143 | ||
1dbfd9d4 VN |
144 | if (sc->ps_idle) |
145 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); | |
146 | else if (sc->ps_enabled && | |
147 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
1b04b930 S |
148 | PS_WAIT_FOR_CAB | |
149 | PS_WAIT_FOR_PSPOLL_DATA | | |
150 | PS_WAIT_FOR_TX_ACK))) | |
9ecdef4b | 151 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); |
a91d75ae LR |
152 | |
153 | unlock: | |
154 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
155 | } | |
156 | ||
ff37e337 S |
157 | /* |
158 | * Set/change channels. If the channel is really being changed, it's done | |
159 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
160 | * DMA, then restart stuff. | |
161 | */ | |
0e2dedf9 JM |
162 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, |
163 | struct ath9k_channel *hchan) | |
ff37e337 | 164 | { |
cbe61d8a | 165 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 166 | struct ath_common *common = ath9k_hw_common(ah); |
25c56eec | 167 | struct ieee80211_conf *conf = &common->hw->conf; |
ff37e337 | 168 | bool fastcc = true, stopped; |
ae8d2858 LR |
169 | struct ieee80211_channel *channel = hw->conf.channel; |
170 | int r; | |
ff37e337 S |
171 | |
172 | if (sc->sc_flags & SC_OP_INVALID) | |
173 | return -EIO; | |
174 | ||
3cbb5dd7 VN |
175 | ath9k_ps_wakeup(sc); |
176 | ||
c0d7c7af LR |
177 | /* |
178 | * This is only performed if the channel settings have | |
179 | * actually changed. | |
180 | * | |
181 | * To switch channels clear any pending DMA operations; | |
182 | * wait long enough for the RX fifo to drain, reset the | |
183 | * hardware at the new frequency, and then re-enable | |
184 | * the relevant bits of the h/w. | |
185 | */ | |
186 | ath9k_hw_set_interrupts(ah, 0); | |
043a0405 | 187 | ath_drain_all_txq(sc, false); |
c0d7c7af | 188 | stopped = ath_stoprecv(sc); |
ff37e337 | 189 | |
c0d7c7af LR |
190 | /* XXX: do not flush receive queue here. We don't want |
191 | * to flush data frames already in queue because of | |
192 | * changing channel. */ | |
ff37e337 | 193 | |
c0d7c7af LR |
194 | if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET)) |
195 | fastcc = false; | |
196 | ||
c46917bb | 197 | ath_print(common, ATH_DBG_CONFIG, |
25c56eec | 198 | "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n", |
c46917bb | 199 | sc->sc_ah->curchan->channel, |
25c56eec | 200 | channel->center_freq, conf_is_ht40(conf)); |
ff37e337 | 201 | |
c0d7c7af LR |
202 | spin_lock_bh(&sc->sc_resetlock); |
203 | ||
204 | r = ath9k_hw_reset(ah, hchan, fastcc); | |
205 | if (r) { | |
c46917bb | 206 | ath_print(common, ATH_DBG_FATAL, |
f643e51d | 207 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
208 | "reset status %d\n", |
209 | channel->center_freq, r); | |
c0d7c7af | 210 | spin_unlock_bh(&sc->sc_resetlock); |
3989279c | 211 | goto ps_restore; |
ff37e337 | 212 | } |
c0d7c7af LR |
213 | spin_unlock_bh(&sc->sc_resetlock); |
214 | ||
c0d7c7af LR |
215 | sc->sc_flags &= ~SC_OP_FULL_RESET; |
216 | ||
217 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
218 | ath_print(common, ATH_DBG_FATAL, |
219 | "Unable to restart recv logic\n"); | |
3989279c GJ |
220 | r = -EIO; |
221 | goto ps_restore; | |
c0d7c7af LR |
222 | } |
223 | ||
224 | ath_cache_conf_rate(sc, &hw->conf); | |
225 | ath_update_txpow(sc); | |
3069168c | 226 | ath9k_hw_set_interrupts(ah, ah->imask); |
3989279c GJ |
227 | |
228 | ps_restore: | |
3cbb5dd7 | 229 | ath9k_ps_restore(sc); |
3989279c | 230 | return r; |
ff37e337 S |
231 | } |
232 | ||
9f42c2b6 FF |
233 | static void ath_paprd_activate(struct ath_softc *sc) |
234 | { | |
235 | struct ath_hw *ah = sc->sc_ah; | |
236 | int chain; | |
237 | ||
238 | if (!ah->curchan->paprd_done) | |
239 | return; | |
240 | ||
241 | ath9k_ps_wakeup(sc); | |
242 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { | |
243 | if (!(ah->caps.tx_chainmask & BIT(chain))) | |
244 | continue; | |
245 | ||
246 | ar9003_paprd_populate_single_table(ah, ah->curchan, chain); | |
247 | } | |
248 | ||
249 | ar9003_paprd_enable(ah, true); | |
250 | ath9k_ps_restore(sc); | |
251 | } | |
252 | ||
253 | void ath_paprd_calibrate(struct work_struct *work) | |
254 | { | |
255 | struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work); | |
256 | struct ieee80211_hw *hw = sc->hw; | |
257 | struct ath_hw *ah = sc->sc_ah; | |
258 | struct ieee80211_hdr *hdr; | |
259 | struct sk_buff *skb = NULL; | |
260 | struct ieee80211_tx_info *tx_info; | |
261 | int band = hw->conf.channel->band; | |
262 | struct ieee80211_supported_band *sband = &sc->sbands[band]; | |
263 | struct ath_tx_control txctl; | |
264 | int qnum, ftype; | |
265 | int chain_ok = 0; | |
266 | int chain; | |
267 | int len = 1800; | |
268 | int time_left; | |
269 | int i; | |
270 | ||
271 | ath9k_ps_wakeup(sc); | |
272 | skb = alloc_skb(len, GFP_KERNEL); | |
273 | if (!skb) | |
274 | return; | |
275 | ||
276 | tx_info = IEEE80211_SKB_CB(skb); | |
277 | ||
278 | skb_put(skb, len); | |
279 | memset(skb->data, 0, len); | |
280 | hdr = (struct ieee80211_hdr *)skb->data; | |
281 | ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC; | |
282 | hdr->frame_control = cpu_to_le16(ftype); | |
283 | hdr->duration_id = 10; | |
284 | memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN); | |
285 | memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN); | |
286 | memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN); | |
287 | ||
288 | memset(&txctl, 0, sizeof(txctl)); | |
289 | qnum = sc->tx.hwq_map[WME_AC_BE]; | |
290 | txctl.txq = &sc->tx.txq[qnum]; | |
291 | ||
292 | ar9003_paprd_init_table(ah); | |
293 | for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { | |
294 | if (!(ah->caps.tx_chainmask & BIT(chain))) | |
295 | continue; | |
296 | ||
297 | chain_ok = 0; | |
298 | memset(tx_info, 0, sizeof(*tx_info)); | |
299 | tx_info->band = band; | |
300 | ||
301 | for (i = 0; i < 4; i++) { | |
302 | tx_info->control.rates[i].idx = sband->n_bitrates - 1; | |
303 | tx_info->control.rates[i].count = 6; | |
304 | } | |
305 | ||
306 | init_completion(&sc->paprd_complete); | |
307 | ar9003_paprd_setup_gain_table(ah, chain); | |
308 | txctl.paprd = BIT(chain); | |
309 | if (ath_tx_start(hw, skb, &txctl) != 0) | |
310 | break; | |
311 | ||
312 | time_left = wait_for_completion_timeout(&sc->paprd_complete, | |
313 | 100); | |
314 | if (!time_left) { | |
315 | ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, | |
316 | "Timeout waiting for paprd training on " | |
317 | "TX chain %d\n", | |
318 | chain); | |
319 | break; | |
320 | } | |
321 | ||
322 | if (!ar9003_paprd_is_done(ah)) | |
323 | break; | |
324 | ||
325 | if (ar9003_paprd_create_curve(ah, ah->curchan, chain) != 0) | |
326 | break; | |
327 | ||
328 | chain_ok = 1; | |
329 | } | |
330 | kfree_skb(skb); | |
331 | ||
332 | if (chain_ok) { | |
333 | ah->curchan->paprd_done = true; | |
334 | ath_paprd_activate(sc); | |
335 | } | |
336 | ||
337 | ath9k_ps_restore(sc); | |
338 | } | |
339 | ||
ff37e337 S |
340 | /* |
341 | * This routine performs the periodic noise floor calibration function | |
342 | * that is used to adjust and optimize the chip performance. This | |
343 | * takes environmental changes (location, temperature) into account. | |
344 | * When the task is complete, it reschedules itself depending on the | |
345 | * appropriate interval that was calculated. | |
346 | */ | |
55624204 | 347 | void ath_ani_calibrate(unsigned long data) |
ff37e337 | 348 | { |
20977d3e S |
349 | struct ath_softc *sc = (struct ath_softc *)data; |
350 | struct ath_hw *ah = sc->sc_ah; | |
c46917bb | 351 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
352 | bool longcal = false; |
353 | bool shortcal = false; | |
354 | bool aniflag = false; | |
355 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
20977d3e | 356 | u32 cal_interval, short_cal_interval; |
ff37e337 | 357 | |
20977d3e S |
358 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
359 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 | 360 | |
1ffc1c61 JM |
361 | /* Only calibrate if awake */ |
362 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
363 | goto set_timer; | |
364 | ||
365 | ath9k_ps_wakeup(sc); | |
366 | ||
ff37e337 | 367 | /* Long calibration runs independently of short calibration. */ |
3d536acf | 368 | if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { |
ff37e337 | 369 | longcal = true; |
c46917bb | 370 | ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
3d536acf | 371 | common->ani.longcal_timer = timestamp; |
ff37e337 S |
372 | } |
373 | ||
17d7904d | 374 | /* Short calibration applies only while caldone is false */ |
3d536acf LR |
375 | if (!common->ani.caldone) { |
376 | if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { | |
ff37e337 | 377 | shortcal = true; |
c46917bb LR |
378 | ath_print(common, ATH_DBG_ANI, |
379 | "shortcal @%lu\n", jiffies); | |
3d536acf LR |
380 | common->ani.shortcal_timer = timestamp; |
381 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
382 | } |
383 | } else { | |
3d536acf | 384 | if ((timestamp - common->ani.resetcal_timer) >= |
ff37e337 | 385 | ATH_RESTART_CALINTERVAL) { |
3d536acf LR |
386 | common->ani.caldone = ath9k_hw_reset_calvalid(ah); |
387 | if (common->ani.caldone) | |
388 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
389 | } |
390 | } | |
391 | ||
392 | /* Verify whether we must check ANI */ | |
e36b27af LR |
393 | if ((timestamp - common->ani.checkani_timer) >= |
394 | ah->config.ani_poll_interval) { | |
ff37e337 | 395 | aniflag = true; |
3d536acf | 396 | common->ani.checkani_timer = timestamp; |
ff37e337 S |
397 | } |
398 | ||
399 | /* Skip all processing if there's nothing to do. */ | |
400 | if (longcal || shortcal || aniflag) { | |
401 | /* Call ANI routine if necessary */ | |
402 | if (aniflag) | |
22e66a4c | 403 | ath9k_hw_ani_monitor(ah, ah->curchan); |
ff37e337 S |
404 | |
405 | /* Perform calibration if necessary */ | |
406 | if (longcal || shortcal) { | |
3d536acf | 407 | common->ani.caldone = |
43c27613 LR |
408 | ath9k_hw_calibrate(ah, |
409 | ah->curchan, | |
410 | common->rx_chainmask, | |
411 | longcal); | |
379f0440 S |
412 | |
413 | if (longcal) | |
3d536acf | 414 | common->ani.noise_floor = ath9k_hw_getchan_noise(ah, |
379f0440 S |
415 | ah->curchan); |
416 | ||
c46917bb LR |
417 | ath_print(common, ATH_DBG_ANI, |
418 | " calibrate chan %u/%x nf: %d\n", | |
419 | ah->curchan->channel, | |
420 | ah->curchan->channelFlags, | |
3d536acf | 421 | common->ani.noise_floor); |
ff37e337 S |
422 | } |
423 | } | |
424 | ||
1ffc1c61 JM |
425 | ath9k_ps_restore(sc); |
426 | ||
20977d3e | 427 | set_timer: |
ff37e337 S |
428 | /* |
429 | * Set timer interval based on previous results. | |
430 | * The interval must be the shortest necessary to satisfy ANI, | |
431 | * short calibration and long calibration. | |
432 | */ | |
aac9207e | 433 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 434 | if (sc->sc_ah->config.enable_ani) |
e36b27af LR |
435 | cal_interval = min(cal_interval, |
436 | (u32)ah->config.ani_poll_interval); | |
3d536acf | 437 | if (!common->ani.caldone) |
20977d3e | 438 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 439 | |
3d536acf | 440 | mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
9f42c2b6 FF |
441 | if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && |
442 | !(sc->sc_flags & SC_OP_SCANNING)) { | |
443 | if (!sc->sc_ah->curchan->paprd_done) | |
444 | ieee80211_queue_work(sc->hw, &sc->paprd_work); | |
445 | else | |
446 | ath_paprd_activate(sc); | |
447 | } | |
ff37e337 S |
448 | } |
449 | ||
3d536acf | 450 | static void ath_start_ani(struct ath_common *common) |
415f738e | 451 | { |
e36b27af | 452 | struct ath_hw *ah = common->ah; |
415f738e S |
453 | unsigned long timestamp = jiffies_to_msecs(jiffies); |
454 | ||
3d536acf LR |
455 | common->ani.longcal_timer = timestamp; |
456 | common->ani.shortcal_timer = timestamp; | |
457 | common->ani.checkani_timer = timestamp; | |
415f738e | 458 | |
3d536acf | 459 | mod_timer(&common->ani.timer, |
e36b27af LR |
460 | jiffies + |
461 | msecs_to_jiffies((u32)ah->config.ani_poll_interval)); | |
415f738e S |
462 | } |
463 | ||
ff37e337 S |
464 | /* |
465 | * Update tx/rx chainmask. For legacy association, | |
466 | * hard code chainmask to 1x1, for 11n association, use | |
c97c92d9 VT |
467 | * the chainmask configuration, for bt coexistence, use |
468 | * the chainmask configuration even in legacy mode. | |
ff37e337 | 469 | */ |
0e2dedf9 | 470 | void ath_update_chainmask(struct ath_softc *sc, int is_ht) |
ff37e337 | 471 | { |
af03abec | 472 | struct ath_hw *ah = sc->sc_ah; |
43c27613 | 473 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 474 | |
3d832611 | 475 | if ((sc->sc_flags & SC_OP_SCANNING) || is_ht || |
766ec4a9 | 476 | (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) { |
43c27613 LR |
477 | common->tx_chainmask = ah->caps.tx_chainmask; |
478 | common->rx_chainmask = ah->caps.rx_chainmask; | |
ff37e337 | 479 | } else { |
43c27613 LR |
480 | common->tx_chainmask = 1; |
481 | common->rx_chainmask = 1; | |
ff37e337 S |
482 | } |
483 | ||
43c27613 | 484 | ath_print(common, ATH_DBG_CONFIG, |
c46917bb | 485 | "tx chmask: %d, rx chmask: %d\n", |
43c27613 LR |
486 | common->tx_chainmask, |
487 | common->rx_chainmask); | |
ff37e337 S |
488 | } |
489 | ||
490 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
491 | { | |
492 | struct ath_node *an; | |
493 | ||
494 | an = (struct ath_node *)sta->drv_priv; | |
495 | ||
87792efc | 496 | if (sc->sc_flags & SC_OP_TXAGGR) { |
ff37e337 | 497 | ath_tx_node_init(sc, an); |
9e98ac65 | 498 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc S |
499 | sta->ht_cap.ampdu_factor); |
500 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
a59b5a5e | 501 | an->last_rssi = ATH_RSSI_DUMMY_MARKER; |
87792efc | 502 | } |
ff37e337 S |
503 | } |
504 | ||
505 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
506 | { | |
507 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
508 | ||
509 | if (sc->sc_flags & SC_OP_TXAGGR) | |
510 | ath_tx_node_cleanup(sc, an); | |
511 | } | |
512 | ||
55624204 | 513 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
514 | { |
515 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 516 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 517 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 518 | |
17d7904d | 519 | u32 status = sc->intrstatus; |
b5c80475 | 520 | u32 rxmask; |
ff37e337 | 521 | |
153e080d VT |
522 | ath9k_ps_wakeup(sc); |
523 | ||
c9c99e5e FF |
524 | if ((status & ATH9K_INT_FATAL) || |
525 | !ath9k_hw_check_alive(ah)) { | |
ff37e337 | 526 | ath_reset(sc, false); |
153e080d | 527 | ath9k_ps_restore(sc); |
ff37e337 | 528 | return; |
063d8be3 | 529 | } |
ff37e337 | 530 | |
b5c80475 FF |
531 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
532 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
533 | ATH9K_INT_RXORN); | |
534 | else | |
535 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
536 | ||
537 | if (status & rxmask) { | |
063d8be3 | 538 | spin_lock_bh(&sc->rx.rxflushlock); |
b5c80475 FF |
539 | |
540 | /* Check for high priority Rx first */ | |
541 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
542 | (status & ATH9K_INT_RXHP)) | |
543 | ath_rx_tasklet(sc, 0, true); | |
544 | ||
545 | ath_rx_tasklet(sc, 0, false); | |
063d8be3 | 546 | spin_unlock_bh(&sc->rx.rxflushlock); |
ff37e337 S |
547 | } |
548 | ||
e5003249 VT |
549 | if (status & ATH9K_INT_TX) { |
550 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
551 | ath_tx_edma_tasklet(sc); | |
552 | else | |
553 | ath_tx_tasklet(sc); | |
554 | } | |
063d8be3 | 555 | |
96148326 | 556 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
54ce846e JM |
557 | /* |
558 | * TSF sync does not look correct; remain awake to sync with | |
559 | * the next Beacon. | |
560 | */ | |
c46917bb LR |
561 | ath_print(common, ATH_DBG_PS, |
562 | "TSFOOR - Sync with next Beacon\n"); | |
1b04b930 | 563 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
54ce846e JM |
564 | } |
565 | ||
766ec4a9 | 566 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
ebb8e1d7 VT |
567 | if (status & ATH9K_INT_GENTIMER) |
568 | ath_gen_timer_isr(sc->sc_ah); | |
569 | ||
ff37e337 | 570 | /* re-enable hardware interrupt */ |
3069168c | 571 | ath9k_hw_set_interrupts(ah, ah->imask); |
153e080d | 572 | ath9k_ps_restore(sc); |
ff37e337 S |
573 | } |
574 | ||
6baff7f9 | 575 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 576 | { |
063d8be3 S |
577 | #define SCHED_INTR ( \ |
578 | ATH9K_INT_FATAL | \ | |
579 | ATH9K_INT_RXORN | \ | |
580 | ATH9K_INT_RXEOL | \ | |
581 | ATH9K_INT_RX | \ | |
b5c80475 FF |
582 | ATH9K_INT_RXLP | \ |
583 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
584 | ATH9K_INT_TX | \ |
585 | ATH9K_INT_BMISS | \ | |
586 | ATH9K_INT_CST | \ | |
ebb8e1d7 VT |
587 | ATH9K_INT_TSFOOR | \ |
588 | ATH9K_INT_GENTIMER) | |
063d8be3 | 589 | |
ff37e337 | 590 | struct ath_softc *sc = dev; |
cbe61d8a | 591 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
592 | enum ath9k_int status; |
593 | bool sched = false; | |
594 | ||
063d8be3 S |
595 | /* |
596 | * The hardware is not ready/present, don't | |
597 | * touch anything. Note this can happen early | |
598 | * on if the IRQ is shared. | |
599 | */ | |
600 | if (sc->sc_flags & SC_OP_INVALID) | |
601 | return IRQ_NONE; | |
ff37e337 | 602 | |
063d8be3 S |
603 | |
604 | /* shared irq, not for us */ | |
605 | ||
153e080d | 606 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 607 | return IRQ_NONE; |
063d8be3 S |
608 | |
609 | /* | |
610 | * Figure out the reason(s) for the interrupt. Note | |
611 | * that the hal returns a pseudo-ISR that may include | |
612 | * bits we haven't explicitly enabled so we mask the | |
613 | * value to insure we only process bits we requested. | |
614 | */ | |
615 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 616 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 617 | |
063d8be3 S |
618 | /* |
619 | * If there are no status bits set, then this interrupt was not | |
620 | * for me (should have been caught above). | |
621 | */ | |
153e080d | 622 | if (!status) |
063d8be3 | 623 | return IRQ_NONE; |
ff37e337 | 624 | |
063d8be3 S |
625 | /* Cache the status */ |
626 | sc->intrstatus = status; | |
627 | ||
628 | if (status & SCHED_INTR) | |
629 | sched = true; | |
630 | ||
631 | /* | |
632 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
633 | * chip immediately. | |
634 | */ | |
b5c80475 FF |
635 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
636 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
637 | goto chip_reset; |
638 | ||
08578b8f LR |
639 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && |
640 | (status & ATH9K_INT_BB_WATCHDOG)) { | |
641 | ar9003_hw_bb_watchdog_dbg_info(ah); | |
642 | goto chip_reset; | |
643 | } | |
644 | ||
063d8be3 S |
645 | if (status & ATH9K_INT_SWBA) |
646 | tasklet_schedule(&sc->bcon_tasklet); | |
647 | ||
648 | if (status & ATH9K_INT_TXURN) | |
649 | ath9k_hw_updatetxtriglevel(ah, true); | |
650 | ||
b5c80475 FF |
651 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
652 | if (status & ATH9K_INT_RXEOL) { | |
653 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
654 | ath9k_hw_set_interrupts(ah, ah->imask); | |
655 | } | |
656 | } | |
657 | ||
063d8be3 | 658 | if (status & ATH9K_INT_MIB) { |
ff37e337 | 659 | /* |
063d8be3 S |
660 | * Disable interrupts until we service the MIB |
661 | * interrupt; otherwise it will continue to | |
662 | * fire. | |
ff37e337 | 663 | */ |
063d8be3 S |
664 | ath9k_hw_set_interrupts(ah, 0); |
665 | /* | |
666 | * Let the hal handle the event. We assume | |
667 | * it will clear whatever condition caused | |
668 | * the interrupt. | |
669 | */ | |
22e66a4c | 670 | ath9k_hw_procmibevent(ah); |
3069168c | 671 | ath9k_hw_set_interrupts(ah, ah->imask); |
063d8be3 | 672 | } |
ff37e337 | 673 | |
153e080d VT |
674 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
675 | if (status & ATH9K_INT_TIM_TIMER) { | |
063d8be3 S |
676 | /* Clear RxAbort bit so that we can |
677 | * receive frames */ | |
9ecdef4b | 678 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
153e080d | 679 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 680 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
ff37e337 | 681 | } |
063d8be3 S |
682 | |
683 | chip_reset: | |
ff37e337 | 684 | |
817e11de S |
685 | ath_debug_stat_interrupt(sc, status); |
686 | ||
ff37e337 S |
687 | if (sched) { |
688 | /* turn off every interrupt except SWBA */ | |
3069168c | 689 | ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA)); |
ff37e337 S |
690 | tasklet_schedule(&sc->intr_tq); |
691 | } | |
692 | ||
693 | return IRQ_HANDLED; | |
063d8be3 S |
694 | |
695 | #undef SCHED_INTR | |
ff37e337 S |
696 | } |
697 | ||
f078f209 | 698 | static u32 ath_get_extchanmode(struct ath_softc *sc, |
99405f93 | 699 | struct ieee80211_channel *chan, |
094d05dc | 700 | enum nl80211_channel_type channel_type) |
f078f209 LR |
701 | { |
702 | u32 chanmode = 0; | |
f078f209 LR |
703 | |
704 | switch (chan->band) { | |
705 | case IEEE80211_BAND_2GHZ: | |
094d05dc S |
706 | switch(channel_type) { |
707 | case NL80211_CHAN_NO_HT: | |
708 | case NL80211_CHAN_HT20: | |
f078f209 | 709 | chanmode = CHANNEL_G_HT20; |
094d05dc S |
710 | break; |
711 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 712 | chanmode = CHANNEL_G_HT40PLUS; |
094d05dc S |
713 | break; |
714 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 715 | chanmode = CHANNEL_G_HT40MINUS; |
094d05dc S |
716 | break; |
717 | } | |
f078f209 LR |
718 | break; |
719 | case IEEE80211_BAND_5GHZ: | |
094d05dc S |
720 | switch(channel_type) { |
721 | case NL80211_CHAN_NO_HT: | |
722 | case NL80211_CHAN_HT20: | |
f078f209 | 723 | chanmode = CHANNEL_A_HT20; |
094d05dc S |
724 | break; |
725 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 726 | chanmode = CHANNEL_A_HT40PLUS; |
094d05dc S |
727 | break; |
728 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 729 | chanmode = CHANNEL_A_HT40MINUS; |
094d05dc S |
730 | break; |
731 | } | |
f078f209 LR |
732 | break; |
733 | default: | |
734 | break; | |
735 | } | |
736 | ||
737 | return chanmode; | |
738 | } | |
739 | ||
8feceb67 | 740 | static void ath9k_bss_assoc_info(struct ath_softc *sc, |
5640b08e | 741 | struct ieee80211_vif *vif, |
8feceb67 | 742 | struct ieee80211_bss_conf *bss_conf) |
f078f209 | 743 | { |
f2b2143e | 744 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 745 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 746 | |
8feceb67 | 747 | if (bss_conf->assoc) { |
c46917bb LR |
748 | ath_print(common, ATH_DBG_CONFIG, |
749 | "Bss Info ASSOC %d, bssid: %pM\n", | |
750 | bss_conf->aid, common->curbssid); | |
f078f209 | 751 | |
8feceb67 | 752 | /* New association, store aid */ |
1510718d | 753 | common->curaid = bss_conf->aid; |
f2b2143e | 754 | ath9k_hw_write_associd(ah); |
2664f201 SB |
755 | |
756 | /* | |
757 | * Request a re-configuration of Beacon related timers | |
758 | * on the receipt of the first Beacon frame (i.e., | |
759 | * after time sync with the AP). | |
760 | */ | |
1b04b930 | 761 | sc->ps_flags |= PS_BEACON_SYNC; |
f078f209 | 762 | |
8feceb67 | 763 | /* Configure the beacon */ |
2c3db3d5 | 764 | ath_beacon_config(sc, vif); |
f078f209 | 765 | |
8feceb67 | 766 | /* Reset rssi stats */ |
22e66a4c | 767 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; |
f078f209 | 768 | |
3d536acf | 769 | ath_start_ani(common); |
8feceb67 | 770 | } else { |
c46917bb | 771 | ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); |
1510718d | 772 | common->curaid = 0; |
f38faa31 | 773 | /* Stop ANI */ |
3d536acf | 774 | del_timer_sync(&common->ani.timer); |
f078f209 | 775 | } |
8feceb67 | 776 | } |
f078f209 | 777 | |
68a89116 | 778 | void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 779 | { |
cbe61d8a | 780 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 781 | struct ath_common *common = ath9k_hw_common(ah); |
68a89116 | 782 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 783 | int r; |
500c064d | 784 | |
3cbb5dd7 | 785 | ath9k_ps_wakeup(sc); |
93b1b37f | 786 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ae8d2858 | 787 | |
159cd468 VT |
788 | if (!ah->curchan) |
789 | ah->curchan = ath_get_curchannel(sc, sc->hw); | |
790 | ||
d2f5b3a6 | 791 | spin_lock_bh(&sc->sc_resetlock); |
2660b81a | 792 | r = ath9k_hw_reset(ah, ah->curchan, false); |
ae8d2858 | 793 | if (r) { |
c46917bb | 794 | ath_print(common, ATH_DBG_FATAL, |
f643e51d | 795 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
796 | "reset status %d\n", |
797 | channel->center_freq, r); | |
500c064d VT |
798 | } |
799 | spin_unlock_bh(&sc->sc_resetlock); | |
800 | ||
801 | ath_update_txpow(sc); | |
802 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
803 | ath_print(common, ATH_DBG_FATAL, |
804 | "Unable to restart recv logic\n"); | |
500c064d VT |
805 | return; |
806 | } | |
807 | ||
808 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 809 | ath_beacon_config(sc, NULL); /* restart beacons */ |
500c064d VT |
810 | |
811 | /* Re-Enable interrupts */ | |
3069168c | 812 | ath9k_hw_set_interrupts(ah, ah->imask); |
500c064d VT |
813 | |
814 | /* Enable LED */ | |
08fc5c1b | 815 | ath9k_hw_cfg_output(ah, ah->led_pin, |
500c064d | 816 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
08fc5c1b | 817 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); |
500c064d | 818 | |
68a89116 | 819 | ieee80211_wake_queues(hw); |
3cbb5dd7 | 820 | ath9k_ps_restore(sc); |
500c064d VT |
821 | } |
822 | ||
68a89116 | 823 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 824 | { |
cbe61d8a | 825 | struct ath_hw *ah = sc->sc_ah; |
68a89116 | 826 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 827 | int r; |
500c064d | 828 | |
3cbb5dd7 | 829 | ath9k_ps_wakeup(sc); |
68a89116 | 830 | ieee80211_stop_queues(hw); |
500c064d VT |
831 | |
832 | /* Disable LED */ | |
08fc5c1b VN |
833 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); |
834 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
500c064d VT |
835 | |
836 | /* Disable interrupts */ | |
837 | ath9k_hw_set_interrupts(ah, 0); | |
838 | ||
043a0405 | 839 | ath_drain_all_txq(sc, false); /* clear pending tx frames */ |
500c064d VT |
840 | ath_stoprecv(sc); /* turn off frame recv */ |
841 | ath_flushrecv(sc); /* flush recv queue */ | |
842 | ||
159cd468 | 843 | if (!ah->curchan) |
68a89116 | 844 | ah->curchan = ath_get_curchannel(sc, hw); |
159cd468 | 845 | |
500c064d | 846 | spin_lock_bh(&sc->sc_resetlock); |
2660b81a | 847 | r = ath9k_hw_reset(ah, ah->curchan, false); |
ae8d2858 | 848 | if (r) { |
c46917bb | 849 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
f643e51d | 850 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
851 | "reset status %d\n", |
852 | channel->center_freq, r); | |
500c064d VT |
853 | } |
854 | spin_unlock_bh(&sc->sc_resetlock); | |
855 | ||
856 | ath9k_hw_phy_disable(ah); | |
93b1b37f | 857 | ath9k_hw_configpcipowersave(ah, 1, 1); |
3cbb5dd7 | 858 | ath9k_ps_restore(sc); |
9ecdef4b | 859 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
500c064d VT |
860 | } |
861 | ||
ff37e337 S |
862 | int ath_reset(struct ath_softc *sc, bool retry_tx) |
863 | { | |
cbe61d8a | 864 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 865 | struct ath_common *common = ath9k_hw_common(ah); |
030bb495 | 866 | struct ieee80211_hw *hw = sc->hw; |
ae8d2858 | 867 | int r; |
ff37e337 | 868 | |
2ab81d4a S |
869 | /* Stop ANI */ |
870 | del_timer_sync(&common->ani.timer); | |
871 | ||
cc9c378a S |
872 | ieee80211_stop_queues(hw); |
873 | ||
ff37e337 | 874 | ath9k_hw_set_interrupts(ah, 0); |
043a0405 | 875 | ath_drain_all_txq(sc, retry_tx); |
ff37e337 S |
876 | ath_stoprecv(sc); |
877 | ath_flushrecv(sc); | |
878 | ||
879 | spin_lock_bh(&sc->sc_resetlock); | |
2660b81a | 880 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false); |
ae8d2858 | 881 | if (r) |
c46917bb LR |
882 | ath_print(common, ATH_DBG_FATAL, |
883 | "Unable to reset hardware; reset status %d\n", r); | |
ff37e337 S |
884 | spin_unlock_bh(&sc->sc_resetlock); |
885 | ||
886 | if (ath_startrecv(sc) != 0) | |
c46917bb LR |
887 | ath_print(common, ATH_DBG_FATAL, |
888 | "Unable to start recv logic\n"); | |
ff37e337 S |
889 | |
890 | /* | |
891 | * We may be doing a reset in response to a request | |
892 | * that changes the channel so update any state that | |
893 | * might change as a result. | |
894 | */ | |
ce111bad | 895 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
896 | |
897 | ath_update_txpow(sc); | |
898 | ||
899 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 900 | ath_beacon_config(sc, NULL); /* restart beacons */ |
ff37e337 | 901 | |
3069168c | 902 | ath9k_hw_set_interrupts(ah, ah->imask); |
ff37e337 S |
903 | |
904 | if (retry_tx) { | |
905 | int i; | |
906 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
907 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
908 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
909 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
910 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
911 | } |
912 | } | |
913 | } | |
914 | ||
cc9c378a S |
915 | ieee80211_wake_queues(hw); |
916 | ||
2ab81d4a S |
917 | /* Start ANI */ |
918 | ath_start_ani(common); | |
919 | ||
ae8d2858 | 920 | return r; |
ff37e337 S |
921 | } |
922 | ||
ebe297c3 | 923 | static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc) |
ff37e337 S |
924 | { |
925 | int qnum; | |
926 | ||
927 | switch (queue) { | |
928 | case 0: | |
1d2231e2 | 929 | qnum = sc->tx.hwq_map[WME_AC_VO]; |
ff37e337 S |
930 | break; |
931 | case 1: | |
1d2231e2 | 932 | qnum = sc->tx.hwq_map[WME_AC_VI]; |
ff37e337 S |
933 | break; |
934 | case 2: | |
1d2231e2 | 935 | qnum = sc->tx.hwq_map[WME_AC_BE]; |
ff37e337 S |
936 | break; |
937 | case 3: | |
1d2231e2 | 938 | qnum = sc->tx.hwq_map[WME_AC_BK]; |
ff37e337 S |
939 | break; |
940 | default: | |
1d2231e2 | 941 | qnum = sc->tx.hwq_map[WME_AC_BE]; |
ff37e337 S |
942 | break; |
943 | } | |
944 | ||
945 | return qnum; | |
946 | } | |
947 | ||
948 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc) | |
949 | { | |
950 | int qnum; | |
951 | ||
952 | switch (queue) { | |
1d2231e2 | 953 | case WME_AC_VO: |
ff37e337 S |
954 | qnum = 0; |
955 | break; | |
1d2231e2 | 956 | case WME_AC_VI: |
ff37e337 S |
957 | qnum = 1; |
958 | break; | |
1d2231e2 | 959 | case WME_AC_BE: |
ff37e337 S |
960 | qnum = 2; |
961 | break; | |
1d2231e2 | 962 | case WME_AC_BK: |
ff37e337 S |
963 | qnum = 3; |
964 | break; | |
965 | default: | |
966 | qnum = -1; | |
967 | break; | |
968 | } | |
969 | ||
970 | return qnum; | |
971 | } | |
972 | ||
5f8e077c LR |
973 | /* XXX: Remove me once we don't depend on ath9k_channel for all |
974 | * this redundant data */ | |
0e2dedf9 JM |
975 | void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, |
976 | struct ath9k_channel *ichan) | |
5f8e077c | 977 | { |
5f8e077c LR |
978 | struct ieee80211_channel *chan = hw->conf.channel; |
979 | struct ieee80211_conf *conf = &hw->conf; | |
980 | ||
981 | ichan->channel = chan->center_freq; | |
982 | ichan->chan = chan; | |
983 | ||
984 | if (chan->band == IEEE80211_BAND_2GHZ) { | |
985 | ichan->chanmode = CHANNEL_G; | |
8813262e | 986 | ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G; |
5f8e077c LR |
987 | } else { |
988 | ichan->chanmode = CHANNEL_A; | |
989 | ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM; | |
990 | } | |
991 | ||
25c56eec | 992 | if (conf_is_ht(conf)) |
5f8e077c LR |
993 | ichan->chanmode = ath_get_extchanmode(sc, chan, |
994 | conf->channel_type); | |
5f8e077c LR |
995 | } |
996 | ||
ff37e337 S |
997 | /**********************/ |
998 | /* mac80211 callbacks */ | |
999 | /**********************/ | |
1000 | ||
8feceb67 | 1001 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 1002 | { |
bce048d7 JM |
1003 | struct ath_wiphy *aphy = hw->priv; |
1004 | struct ath_softc *sc = aphy->sc; | |
af03abec | 1005 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1006 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 1007 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 1008 | struct ath9k_channel *init_channel; |
82880a7c | 1009 | int r; |
f078f209 | 1010 | |
c46917bb LR |
1011 | ath_print(common, ATH_DBG_CONFIG, |
1012 | "Starting driver with initial channel: %d MHz\n", | |
1013 | curchan->center_freq); | |
f078f209 | 1014 | |
141b38b6 S |
1015 | mutex_lock(&sc->mutex); |
1016 | ||
9580a222 JM |
1017 | if (ath9k_wiphy_started(sc)) { |
1018 | if (sc->chan_idx == curchan->hw_value) { | |
1019 | /* | |
1020 | * Already on the operational channel, the new wiphy | |
1021 | * can be marked active. | |
1022 | */ | |
1023 | aphy->state = ATH_WIPHY_ACTIVE; | |
1024 | ieee80211_wake_queues(hw); | |
1025 | } else { | |
1026 | /* | |
1027 | * Another wiphy is on another channel, start the new | |
1028 | * wiphy in paused state. | |
1029 | */ | |
1030 | aphy->state = ATH_WIPHY_PAUSED; | |
1031 | ieee80211_stop_queues(hw); | |
1032 | } | |
1033 | mutex_unlock(&sc->mutex); | |
1034 | return 0; | |
1035 | } | |
1036 | aphy->state = ATH_WIPHY_ACTIVE; | |
1037 | ||
8feceb67 | 1038 | /* setup initial channel */ |
f078f209 | 1039 | |
82880a7c | 1040 | sc->chan_idx = curchan->hw_value; |
f078f209 | 1041 | |
82880a7c | 1042 | init_channel = ath_get_curchannel(sc, hw); |
ff37e337 S |
1043 | |
1044 | /* Reset SERDES registers */ | |
af03abec | 1045 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ff37e337 S |
1046 | |
1047 | /* | |
1048 | * The basic interface to setting the hardware in a good | |
1049 | * state is ``reset''. On return the hardware is known to | |
1050 | * be powered up and with interrupts disabled. This must | |
1051 | * be followed by initialization of the appropriate bits | |
1052 | * and then setup of the interrupt mask. | |
1053 | */ | |
1054 | spin_lock_bh(&sc->sc_resetlock); | |
af03abec | 1055 | r = ath9k_hw_reset(ah, init_channel, false); |
ae8d2858 | 1056 | if (r) { |
c46917bb LR |
1057 | ath_print(common, ATH_DBG_FATAL, |
1058 | "Unable to reset hardware; reset status %d " | |
1059 | "(freq %u MHz)\n", r, | |
1060 | curchan->center_freq); | |
ff37e337 | 1061 | spin_unlock_bh(&sc->sc_resetlock); |
141b38b6 | 1062 | goto mutex_unlock; |
ff37e337 S |
1063 | } |
1064 | spin_unlock_bh(&sc->sc_resetlock); | |
1065 | ||
1066 | /* | |
1067 | * This is needed only to setup initial state | |
1068 | * but it's best done after a reset. | |
1069 | */ | |
1070 | ath_update_txpow(sc); | |
8feceb67 | 1071 | |
ff37e337 S |
1072 | /* |
1073 | * Setup the hardware after reset: | |
1074 | * The receive engine is set going. | |
1075 | * Frame transmit is handled entirely | |
1076 | * in the frame output path; there's nothing to do | |
1077 | * here except setup the interrupt mask. | |
1078 | */ | |
1079 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
1080 | ath_print(common, ATH_DBG_FATAL, |
1081 | "Unable to start recv logic\n"); | |
141b38b6 S |
1082 | r = -EIO; |
1083 | goto mutex_unlock; | |
f078f209 | 1084 | } |
8feceb67 | 1085 | |
ff37e337 | 1086 | /* Setup our intr mask. */ |
b5c80475 FF |
1087 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
1088 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
1089 | ATH9K_INT_GLOBAL; | |
1090 | ||
1091 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
08578b8f LR |
1092 | ah->imask |= ATH9K_INT_RXHP | |
1093 | ATH9K_INT_RXLP | | |
1094 | ATH9K_INT_BB_WATCHDOG; | |
b5c80475 FF |
1095 | else |
1096 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 1097 | |
af03abec | 1098 | if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT) |
3069168c | 1099 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 1100 | |
af03abec | 1101 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 1102 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 1103 | |
ce111bad | 1104 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
1105 | |
1106 | sc->sc_flags &= ~SC_OP_INVALID; | |
1107 | ||
1108 | /* Disable BMISS interrupt when we're not associated */ | |
3069168c PR |
1109 | ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
1110 | ath9k_hw_set_interrupts(ah, ah->imask); | |
ff37e337 | 1111 | |
bce048d7 | 1112 | ieee80211_wake_queues(hw); |
ff37e337 | 1113 | |
42935eca | 1114 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
164ace38 | 1115 | |
766ec4a9 LR |
1116 | if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && |
1117 | !ah->btcoex_hw.enabled) { | |
5e197292 LR |
1118 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, |
1119 | AR_STOMP_LOW_WLAN_WGHT); | |
af03abec | 1120 | ath9k_hw_btcoex_enable(ah); |
f985ad12 | 1121 | |
5bb12791 LR |
1122 | if (common->bus_ops->bt_coex_prep) |
1123 | common->bus_ops->bt_coex_prep(common); | |
766ec4a9 | 1124 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1125 | ath9k_btcoex_timer_resume(sc); |
1773912b VT |
1126 | } |
1127 | ||
141b38b6 S |
1128 | mutex_unlock: |
1129 | mutex_unlock(&sc->mutex); | |
1130 | ||
ae8d2858 | 1131 | return r; |
f078f209 LR |
1132 | } |
1133 | ||
8feceb67 VT |
1134 | static int ath9k_tx(struct ieee80211_hw *hw, |
1135 | struct sk_buff *skb) | |
f078f209 | 1136 | { |
528f0c6b | 1137 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
bce048d7 JM |
1138 | struct ath_wiphy *aphy = hw->priv; |
1139 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1140 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1141 | struct ath_tx_control txctl; |
1bc14880 BP |
1142 | int padpos, padsize; |
1143 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
84642d6b | 1144 | int qnum; |
528f0c6b | 1145 | |
8089cc47 | 1146 | if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { |
c46917bb LR |
1147 | ath_print(common, ATH_DBG_XMIT, |
1148 | "ath9k: %s: TX in unexpected wiphy state " | |
1149 | "%d\n", wiphy_name(hw->wiphy), aphy->state); | |
ee166a0e JM |
1150 | goto exit; |
1151 | } | |
1152 | ||
96148326 | 1153 | if (sc->ps_enabled) { |
dc8c4585 JM |
1154 | /* |
1155 | * mac80211 does not set PM field for normal data frames, so we | |
1156 | * need to update that based on the current PS mode. | |
1157 | */ | |
1158 | if (ieee80211_is_data(hdr->frame_control) && | |
1159 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
1160 | !ieee80211_has_pm(hdr->frame_control)) { | |
c46917bb LR |
1161 | ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame " |
1162 | "while in PS mode\n"); | |
dc8c4585 JM |
1163 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
1164 | } | |
1165 | } | |
1166 | ||
9a23f9ca JM |
1167 | if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { |
1168 | /* | |
1169 | * We are using PS-Poll and mac80211 can request TX while in | |
1170 | * power save mode. Need to wake up hardware for the TX to be | |
1171 | * completed and if needed, also for RX of buffered frames. | |
1172 | */ | |
9a23f9ca | 1173 | ath9k_ps_wakeup(sc); |
fdf76622 VT |
1174 | if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
1175 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
9a23f9ca | 1176 | if (ieee80211_is_pspoll(hdr->frame_control)) { |
c46917bb LR |
1177 | ath_print(common, ATH_DBG_PS, |
1178 | "Sending PS-Poll to pick a buffered frame\n"); | |
1b04b930 | 1179 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 1180 | } else { |
c46917bb LR |
1181 | ath_print(common, ATH_DBG_PS, |
1182 | "Wake up to complete TX\n"); | |
1b04b930 | 1183 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
1184 | } |
1185 | /* | |
1186 | * The actual restore operation will happen only after | |
1187 | * the sc_flags bit is cleared. We are just dropping | |
1188 | * the ps_usecount here. | |
1189 | */ | |
1190 | ath9k_ps_restore(sc); | |
1191 | } | |
1192 | ||
528f0c6b | 1193 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 | 1194 | |
8feceb67 VT |
1195 | /* |
1196 | * As a temporary workaround, assign seq# here; this will likely need | |
1197 | * to be cleaned up to work better with Beacon transmission and virtual | |
1198 | * BSSes. | |
1199 | */ | |
1200 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
8feceb67 | 1201 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) |
b77f483f | 1202 | sc->tx.seq_no += 0x10; |
8feceb67 | 1203 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
b77f483f | 1204 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); |
8feceb67 | 1205 | } |
f078f209 | 1206 | |
8feceb67 | 1207 | /* Add the padding after the header if this is not already done */ |
1bc14880 BP |
1208 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
1209 | padsize = padpos & 3; | |
1210 | if (padsize && skb->len>padpos) { | |
8feceb67 VT |
1211 | if (skb_headroom(skb) < padsize) |
1212 | return -1; | |
1213 | skb_push(skb, padsize); | |
1bc14880 | 1214 | memmove(skb->data, skb->data + padsize, padpos); |
8feceb67 VT |
1215 | } |
1216 | ||
84642d6b FF |
1217 | qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); |
1218 | txctl.txq = &sc->tx.txq[qnum]; | |
528f0c6b | 1219 | |
c46917bb | 1220 | ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 1221 | |
c52f33d0 | 1222 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
c46917bb | 1223 | ath_print(common, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 1224 | goto exit; |
8feceb67 VT |
1225 | } |
1226 | ||
528f0c6b S |
1227 | return 0; |
1228 | exit: | |
1229 | dev_kfree_skb_any(skb); | |
8feceb67 | 1230 | return 0; |
f078f209 LR |
1231 | } |
1232 | ||
8feceb67 | 1233 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 1234 | { |
bce048d7 JM |
1235 | struct ath_wiphy *aphy = hw->priv; |
1236 | struct ath_softc *sc = aphy->sc; | |
af03abec | 1237 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1238 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 1239 | |
4c483817 S |
1240 | mutex_lock(&sc->mutex); |
1241 | ||
9580a222 JM |
1242 | aphy->state = ATH_WIPHY_INACTIVE; |
1243 | ||
c94dbff7 LR |
1244 | cancel_delayed_work_sync(&sc->ath_led_blink_work); |
1245 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
9f42c2b6 | 1246 | cancel_work_sync(&sc->paprd_work); |
c94dbff7 LR |
1247 | |
1248 | if (!sc->num_sec_wiphy) { | |
1249 | cancel_delayed_work_sync(&sc->wiphy_work); | |
1250 | cancel_work_sync(&sc->chan_work); | |
1251 | } | |
1252 | ||
9c84b797 | 1253 | if (sc->sc_flags & SC_OP_INVALID) { |
c46917bb | 1254 | ath_print(common, ATH_DBG_ANY, "Device not present\n"); |
4c483817 | 1255 | mutex_unlock(&sc->mutex); |
9c84b797 S |
1256 | return; |
1257 | } | |
8feceb67 | 1258 | |
9580a222 JM |
1259 | if (ath9k_wiphy_started(sc)) { |
1260 | mutex_unlock(&sc->mutex); | |
1261 | return; /* another wiphy still in use */ | |
1262 | } | |
1263 | ||
3867cf6a S |
1264 | /* Ensure HW is awake when we try to shut it down. */ |
1265 | ath9k_ps_wakeup(sc); | |
1266 | ||
766ec4a9 | 1267 | if (ah->btcoex_hw.enabled) { |
af03abec | 1268 | ath9k_hw_btcoex_disable(ah); |
766ec4a9 | 1269 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1270 | ath9k_btcoex_timer_pause(sc); |
1773912b VT |
1271 | } |
1272 | ||
ff37e337 S |
1273 | /* make sure h/w will not generate any interrupt |
1274 | * before setting the invalid flag. */ | |
af03abec | 1275 | ath9k_hw_set_interrupts(ah, 0); |
ff37e337 S |
1276 | |
1277 | if (!(sc->sc_flags & SC_OP_INVALID)) { | |
043a0405 | 1278 | ath_drain_all_txq(sc, false); |
ff37e337 | 1279 | ath_stoprecv(sc); |
af03abec | 1280 | ath9k_hw_phy_disable(ah); |
ff37e337 | 1281 | } else |
b77f483f | 1282 | sc->rx.rxlink = NULL; |
ff37e337 | 1283 | |
ff37e337 | 1284 | /* disable HAL and put h/w to sleep */ |
af03abec LR |
1285 | ath9k_hw_disable(ah); |
1286 | ath9k_hw_configpcipowersave(ah, 1, 1); | |
3867cf6a S |
1287 | ath9k_ps_restore(sc); |
1288 | ||
1289 | /* Finally, put the chip in FULL SLEEP mode */ | |
9ecdef4b | 1290 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
ff37e337 S |
1291 | |
1292 | sc->sc_flags |= SC_OP_INVALID; | |
500c064d | 1293 | |
141b38b6 S |
1294 | mutex_unlock(&sc->mutex); |
1295 | ||
c46917bb | 1296 | ath_print(common, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
1297 | } |
1298 | ||
8feceb67 | 1299 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1300 | struct ieee80211_vif *vif) |
f078f209 | 1301 | { |
bce048d7 JM |
1302 | struct ath_wiphy *aphy = hw->priv; |
1303 | struct ath_softc *sc = aphy->sc; | |
3069168c PR |
1304 | struct ath_hw *ah = sc->sc_ah; |
1305 | struct ath_common *common = ath9k_hw_common(ah); | |
1ed32e4f | 1306 | struct ath_vif *avp = (void *)vif->drv_priv; |
d97809db | 1307 | enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; |
2c3db3d5 | 1308 | int ret = 0; |
8feceb67 | 1309 | |
141b38b6 S |
1310 | mutex_lock(&sc->mutex); |
1311 | ||
3069168c | 1312 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) && |
8ca21f01 JM |
1313 | sc->nvifs > 0) { |
1314 | ret = -ENOBUFS; | |
1315 | goto out; | |
1316 | } | |
1317 | ||
1ed32e4f | 1318 | switch (vif->type) { |
05c914fe | 1319 | case NL80211_IFTYPE_STATION: |
d97809db | 1320 | ic_opmode = NL80211_IFTYPE_STATION; |
f078f209 | 1321 | break; |
05c914fe | 1322 | case NL80211_IFTYPE_ADHOC: |
05c914fe | 1323 | case NL80211_IFTYPE_AP: |
9cb5412b | 1324 | case NL80211_IFTYPE_MESH_POINT: |
2c3db3d5 JM |
1325 | if (sc->nbcnvifs >= ATH_BCBUF) { |
1326 | ret = -ENOBUFS; | |
1327 | goto out; | |
1328 | } | |
1ed32e4f | 1329 | ic_opmode = vif->type; |
f078f209 LR |
1330 | break; |
1331 | default: | |
c46917bb | 1332 | ath_print(common, ATH_DBG_FATAL, |
1ed32e4f | 1333 | "Interface type %d not yet supported\n", vif->type); |
2c3db3d5 JM |
1334 | ret = -EOPNOTSUPP; |
1335 | goto out; | |
f078f209 LR |
1336 | } |
1337 | ||
c46917bb LR |
1338 | ath_print(common, ATH_DBG_CONFIG, |
1339 | "Attach a VIF of type: %d\n", ic_opmode); | |
8feceb67 | 1340 | |
17d7904d | 1341 | /* Set the VIF opmode */ |
5640b08e S |
1342 | avp->av_opmode = ic_opmode; |
1343 | avp->av_bslot = -1; | |
1344 | ||
2c3db3d5 | 1345 | sc->nvifs++; |
8ca21f01 | 1346 | |
3069168c | 1347 | if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
8ca21f01 JM |
1348 | ath9k_set_bssid_mask(hw); |
1349 | ||
2c3db3d5 JM |
1350 | if (sc->nvifs > 1) |
1351 | goto out; /* skip global settings for secondary vif */ | |
1352 | ||
b238e90e | 1353 | if (ic_opmode == NL80211_IFTYPE_AP) { |
3069168c | 1354 | ath9k_hw_set_tsfadjust(ah, 1); |
b238e90e S |
1355 | sc->sc_flags |= SC_OP_TSF_RESET; |
1356 | } | |
5640b08e | 1357 | |
5640b08e | 1358 | /* Set the device opmode */ |
3069168c | 1359 | ah->opmode = ic_opmode; |
5640b08e | 1360 | |
4e30ffa2 VN |
1361 | /* |
1362 | * Enable MIB interrupts when there are hardware phy counters. | |
1363 | * Note we only do this (at the moment) for station mode. | |
1364 | */ | |
1ed32e4f JB |
1365 | if ((vif->type == NL80211_IFTYPE_STATION) || |
1366 | (vif->type == NL80211_IFTYPE_ADHOC) || | |
1367 | (vif->type == NL80211_IFTYPE_MESH_POINT)) { | |
3448f912 LR |
1368 | if (ah->config.enable_ani) |
1369 | ah->imask |= ATH9K_INT_MIB; | |
3069168c | 1370 | ah->imask |= ATH9K_INT_TSFOOR; |
4af9cf4f S |
1371 | } |
1372 | ||
3069168c | 1373 | ath9k_hw_set_interrupts(ah, ah->imask); |
4e30ffa2 | 1374 | |
1ed32e4f JB |
1375 | if (vif->type == NL80211_IFTYPE_AP || |
1376 | vif->type == NL80211_IFTYPE_ADHOC || | |
1377 | vif->type == NL80211_IFTYPE_MONITOR) | |
3d536acf | 1378 | ath_start_ani(common); |
6f255425 | 1379 | |
2c3db3d5 | 1380 | out: |
141b38b6 | 1381 | mutex_unlock(&sc->mutex); |
2c3db3d5 | 1382 | return ret; |
f078f209 LR |
1383 | } |
1384 | ||
8feceb67 | 1385 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1386 | struct ieee80211_vif *vif) |
f078f209 | 1387 | { |
bce048d7 JM |
1388 | struct ath_wiphy *aphy = hw->priv; |
1389 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1390 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1ed32e4f | 1391 | struct ath_vif *avp = (void *)vif->drv_priv; |
2c3db3d5 | 1392 | int i; |
f078f209 | 1393 | |
c46917bb | 1394 | ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 1395 | |
141b38b6 S |
1396 | mutex_lock(&sc->mutex); |
1397 | ||
6f255425 | 1398 | /* Stop ANI */ |
3d536acf | 1399 | del_timer_sync(&common->ani.timer); |
580f0b8a | 1400 | |
8feceb67 | 1401 | /* Reclaim beacon resources */ |
9cb5412b PE |
1402 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || |
1403 | (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) || | |
1404 | (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) { | |
5f70a88f | 1405 | ath9k_ps_wakeup(sc); |
b77f483f | 1406 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); |
5f70a88f | 1407 | ath9k_ps_restore(sc); |
580f0b8a | 1408 | } |
f078f209 | 1409 | |
74401773 | 1410 | ath_beacon_return(sc, avp); |
8feceb67 | 1411 | sc->sc_flags &= ~SC_OP_BEACONS; |
f078f209 | 1412 | |
2c3db3d5 | 1413 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { |
1ed32e4f | 1414 | if (sc->beacon.bslot[i] == vif) { |
2c3db3d5 JM |
1415 | printk(KERN_DEBUG "%s: vif had allocated beacon " |
1416 | "slot\n", __func__); | |
1417 | sc->beacon.bslot[i] = NULL; | |
c52f33d0 | 1418 | sc->beacon.bslot_aphy[i] = NULL; |
2c3db3d5 JM |
1419 | } |
1420 | } | |
1421 | ||
17d7904d | 1422 | sc->nvifs--; |
141b38b6 S |
1423 | |
1424 | mutex_unlock(&sc->mutex); | |
f078f209 LR |
1425 | } |
1426 | ||
3f7c5c10 SB |
1427 | void ath9k_enable_ps(struct ath_softc *sc) |
1428 | { | |
3069168c PR |
1429 | struct ath_hw *ah = sc->sc_ah; |
1430 | ||
3f7c5c10 | 1431 | sc->ps_enabled = true; |
3069168c PR |
1432 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1433 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1434 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
1435 | ath9k_hw_set_interrupts(ah, ah->imask); | |
3f7c5c10 | 1436 | } |
fdf76622 | 1437 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 | 1438 | } |
3f7c5c10 SB |
1439 | } |
1440 | ||
e8975581 | 1441 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1442 | { |
bce048d7 JM |
1443 | struct ath_wiphy *aphy = hw->priv; |
1444 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1445 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8975581 | 1446 | struct ieee80211_conf *conf = &hw->conf; |
8782b41d | 1447 | struct ath_hw *ah = sc->sc_ah; |
194b7c13 | 1448 | bool disable_radio; |
f078f209 | 1449 | |
aa33de09 | 1450 | mutex_lock(&sc->mutex); |
141b38b6 | 1451 | |
194b7c13 LR |
1452 | /* |
1453 | * Leave this as the first check because we need to turn on the | |
1454 | * radio if it was disabled before prior to processing the rest | |
1455 | * of the changes. Likewise we must only disable the radio towards | |
1456 | * the end. | |
1457 | */ | |
64839170 | 1458 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
194b7c13 LR |
1459 | bool enable_radio; |
1460 | bool all_wiphys_idle; | |
1461 | bool idle = !!(conf->flags & IEEE80211_CONF_IDLE); | |
64839170 LR |
1462 | |
1463 | spin_lock_bh(&sc->wiphy_lock); | |
1464 | all_wiphys_idle = ath9k_all_wiphys_idle(sc); | |
194b7c13 LR |
1465 | ath9k_set_wiphy_idle(aphy, idle); |
1466 | ||
11446011 | 1467 | enable_radio = (!idle && all_wiphys_idle); |
194b7c13 LR |
1468 | |
1469 | /* | |
1470 | * After we unlock here its possible another wiphy | |
1471 | * can be re-renabled so to account for that we will | |
1472 | * only disable the radio toward the end of this routine | |
1473 | * if by then all wiphys are still idle. | |
1474 | */ | |
64839170 LR |
1475 | spin_unlock_bh(&sc->wiphy_lock); |
1476 | ||
194b7c13 | 1477 | if (enable_radio) { |
1dbfd9d4 | 1478 | sc->ps_idle = false; |
68a89116 | 1479 | ath_radio_enable(sc, hw); |
c46917bb LR |
1480 | ath_print(common, ATH_DBG_CONFIG, |
1481 | "not-idle: enabling radio\n"); | |
64839170 LR |
1482 | } |
1483 | } | |
1484 | ||
e7824a50 LR |
1485 | /* |
1486 | * We just prepare to enable PS. We have to wait until our AP has | |
1487 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1488 | * those ACKs and end up retransmitting the same null data frames. | |
1489 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1490 | */ | |
3cbb5dd7 VN |
1491 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
1492 | if (conf->flags & IEEE80211_CONF_PS) { | |
1b04b930 | 1493 | sc->ps_flags |= PS_ENABLED; |
e7824a50 LR |
1494 | /* |
1495 | * At this point we know hardware has received an ACK | |
1496 | * of a previously sent null data frame. | |
1497 | */ | |
1b04b930 S |
1498 | if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) { |
1499 | sc->ps_flags &= ~PS_NULLFUNC_COMPLETED; | |
3f7c5c10 | 1500 | ath9k_enable_ps(sc); |
e7824a50 | 1501 | } |
3cbb5dd7 | 1502 | } else { |
96148326 | 1503 | sc->ps_enabled = false; |
1b04b930 S |
1504 | sc->ps_flags &= ~(PS_ENABLED | |
1505 | PS_NULLFUNC_COMPLETED); | |
9ecdef4b | 1506 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
8782b41d VN |
1507 | if (!(ah->caps.hw_caps & |
1508 | ATH9K_HW_CAP_AUTOSLEEP)) { | |
1509 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
1b04b930 S |
1510 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | |
1511 | PS_WAIT_FOR_CAB | | |
1512 | PS_WAIT_FOR_PSPOLL_DATA | | |
1513 | PS_WAIT_FOR_TX_ACK); | |
3069168c PR |
1514 | if (ah->imask & ATH9K_INT_TIM_TIMER) { |
1515 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
8782b41d | 1516 | ath9k_hw_set_interrupts(sc->sc_ah, |
3069168c | 1517 | ah->imask); |
8782b41d | 1518 | } |
3cbb5dd7 VN |
1519 | } |
1520 | } | |
1521 | } | |
1522 | ||
199afd9d S |
1523 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1524 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
1525 | ath_print(common, ATH_DBG_CONFIG, | |
1526 | "HW opmode set to Monitor mode\n"); | |
1527 | sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR; | |
1528 | } | |
1529 | } | |
1530 | ||
4797938c | 1531 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
99405f93 | 1532 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 1533 | int pos = curchan->hw_value; |
ae5eb026 | 1534 | |
0e2dedf9 JM |
1535 | aphy->chan_idx = pos; |
1536 | aphy->chan_is_ht = conf_is_ht(conf); | |
1537 | ||
8089cc47 JM |
1538 | if (aphy->state == ATH_WIPHY_SCAN || |
1539 | aphy->state == ATH_WIPHY_ACTIVE) | |
1540 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
1541 | else { | |
1542 | /* | |
1543 | * Do not change operational channel based on a paused | |
1544 | * wiphy changes. | |
1545 | */ | |
1546 | goto skip_chan_change; | |
1547 | } | |
0e2dedf9 | 1548 | |
c46917bb LR |
1549 | ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", |
1550 | curchan->center_freq); | |
f078f209 | 1551 | |
5f8e077c | 1552 | /* XXX: remove me eventualy */ |
0e2dedf9 | 1553 | ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); |
e11602b7 | 1554 | |
ecf70441 | 1555 | ath_update_chainmask(sc, conf_is_ht(conf)); |
86060f0d | 1556 | |
0e2dedf9 | 1557 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
c46917bb LR |
1558 | ath_print(common, ATH_DBG_FATAL, |
1559 | "Unable to set channel\n"); | |
aa33de09 | 1560 | mutex_unlock(&sc->mutex); |
e11602b7 S |
1561 | return -EINVAL; |
1562 | } | |
094d05dc | 1563 | } |
f078f209 | 1564 | |
8089cc47 | 1565 | skip_chan_change: |
c9f6a656 | 1566 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
17d7904d | 1567 | sc->config.txpowlimit = 2 * conf->power_level; |
c9f6a656 LR |
1568 | ath_update_txpow(sc); |
1569 | } | |
f078f209 | 1570 | |
194b7c13 LR |
1571 | spin_lock_bh(&sc->wiphy_lock); |
1572 | disable_radio = ath9k_all_wiphys_idle(sc); | |
1573 | spin_unlock_bh(&sc->wiphy_lock); | |
1574 | ||
64839170 | 1575 | if (disable_radio) { |
c46917bb | 1576 | ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); |
1dbfd9d4 | 1577 | sc->ps_idle = true; |
68a89116 | 1578 | ath_radio_disable(sc, hw); |
64839170 LR |
1579 | } |
1580 | ||
aa33de09 | 1581 | mutex_unlock(&sc->mutex); |
141b38b6 | 1582 | |
f078f209 LR |
1583 | return 0; |
1584 | } | |
1585 | ||
8feceb67 VT |
1586 | #define SUPPORTED_FILTERS \ |
1587 | (FIF_PROMISC_IN_BSS | \ | |
1588 | FIF_ALLMULTI | \ | |
1589 | FIF_CONTROL | \ | |
af6a3fc7 | 1590 | FIF_PSPOLL | \ |
8feceb67 VT |
1591 | FIF_OTHER_BSS | \ |
1592 | FIF_BCN_PRBRESP_PROMISC | \ | |
1593 | FIF_FCSFAIL) | |
c83be688 | 1594 | |
8feceb67 VT |
1595 | /* FIXME: sc->sc_full_reset ? */ |
1596 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1597 | unsigned int changed_flags, | |
1598 | unsigned int *total_flags, | |
3ac64bee | 1599 | u64 multicast) |
8feceb67 | 1600 | { |
bce048d7 JM |
1601 | struct ath_wiphy *aphy = hw->priv; |
1602 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 1603 | u32 rfilt; |
f078f209 | 1604 | |
8feceb67 VT |
1605 | changed_flags &= SUPPORTED_FILTERS; |
1606 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1607 | |
b77f483f | 1608 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1609 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1610 | rfilt = ath_calcrxfilter(sc); |
1611 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1612 | ath9k_ps_restore(sc); |
f078f209 | 1613 | |
c46917bb LR |
1614 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, |
1615 | "Set HW RX filter: 0x%x\n", rfilt); | |
8feceb67 | 1616 | } |
f078f209 | 1617 | |
4ca77860 JB |
1618 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1619 | struct ieee80211_vif *vif, | |
1620 | struct ieee80211_sta *sta) | |
8feceb67 | 1621 | { |
bce048d7 JM |
1622 | struct ath_wiphy *aphy = hw->priv; |
1623 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 1624 | |
4ca77860 JB |
1625 | ath_node_attach(sc, sta); |
1626 | ||
1627 | return 0; | |
1628 | } | |
1629 | ||
1630 | static int ath9k_sta_remove(struct ieee80211_hw *hw, | |
1631 | struct ieee80211_vif *vif, | |
1632 | struct ieee80211_sta *sta) | |
1633 | { | |
1634 | struct ath_wiphy *aphy = hw->priv; | |
1635 | struct ath_softc *sc = aphy->sc; | |
1636 | ||
1637 | ath_node_detach(sc, sta); | |
1638 | ||
1639 | return 0; | |
f078f209 LR |
1640 | } |
1641 | ||
141b38b6 | 1642 | static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
8feceb67 | 1643 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1644 | { |
bce048d7 JM |
1645 | struct ath_wiphy *aphy = hw->priv; |
1646 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1647 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 VT |
1648 | struct ath9k_tx_queue_info qi; |
1649 | int ret = 0, qnum; | |
f078f209 | 1650 | |
8feceb67 VT |
1651 | if (queue >= WME_NUM_AC) |
1652 | return 0; | |
f078f209 | 1653 | |
141b38b6 S |
1654 | mutex_lock(&sc->mutex); |
1655 | ||
1ffb0610 S |
1656 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1657 | ||
8feceb67 VT |
1658 | qi.tqi_aifs = params->aifs; |
1659 | qi.tqi_cwmin = params->cw_min; | |
1660 | qi.tqi_cwmax = params->cw_max; | |
1661 | qi.tqi_burstTime = params->txop; | |
1662 | qnum = ath_get_hal_qnum(queue, sc); | |
f078f209 | 1663 | |
c46917bb LR |
1664 | ath_print(common, ATH_DBG_CONFIG, |
1665 | "Configure tx [queue/halq] [%d/%d], " | |
1666 | "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | |
1667 | queue, qnum, params->aifs, params->cw_min, | |
1668 | params->cw_max, params->txop); | |
f078f209 | 1669 | |
8feceb67 VT |
1670 | ret = ath_txq_update(sc, qnum, &qi); |
1671 | if (ret) | |
c46917bb | 1672 | ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n"); |
f078f209 | 1673 | |
94db2936 | 1674 | if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) |
1d2231e2 | 1675 | if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret) |
94db2936 VN |
1676 | ath_beaconq_config(sc); |
1677 | ||
141b38b6 S |
1678 | mutex_unlock(&sc->mutex); |
1679 | ||
8feceb67 VT |
1680 | return ret; |
1681 | } | |
f078f209 | 1682 | |
8feceb67 VT |
1683 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1684 | enum set_key_cmd cmd, | |
dc822b5d JB |
1685 | struct ieee80211_vif *vif, |
1686 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1687 | struct ieee80211_key_conf *key) |
1688 | { | |
bce048d7 JM |
1689 | struct ath_wiphy *aphy = hw->priv; |
1690 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1691 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1692 | int ret = 0; |
f078f209 | 1693 | |
b3bd89ce JM |
1694 | if (modparam_nohwcrypt) |
1695 | return -ENOSPC; | |
1696 | ||
141b38b6 | 1697 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1698 | ath9k_ps_wakeup(sc); |
c46917bb | 1699 | ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n"); |
f078f209 | 1700 | |
8feceb67 VT |
1701 | switch (cmd) { |
1702 | case SET_KEY: | |
1f03baad | 1703 | ret = ath9k_cmn_key_config(common, vif, sta, key); |
6ace2891 JM |
1704 | if (ret >= 0) { |
1705 | key->hw_key_idx = ret; | |
8feceb67 VT |
1706 | /* push IV and Michael MIC generation to stack */ |
1707 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
1708 | if (key->alg == ALG_TKIP) | |
1709 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; | |
0ced0e17 JM |
1710 | if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP) |
1711 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; | |
6ace2891 | 1712 | ret = 0; |
8feceb67 VT |
1713 | } |
1714 | break; | |
1715 | case DISABLE_KEY: | |
1f03baad | 1716 | ath9k_cmn_key_delete(common, key); |
8feceb67 VT |
1717 | break; |
1718 | default: | |
1719 | ret = -EINVAL; | |
1720 | } | |
f078f209 | 1721 | |
3cbb5dd7 | 1722 | ath9k_ps_restore(sc); |
141b38b6 S |
1723 | mutex_unlock(&sc->mutex); |
1724 | ||
8feceb67 VT |
1725 | return ret; |
1726 | } | |
f078f209 | 1727 | |
8feceb67 VT |
1728 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1729 | struct ieee80211_vif *vif, | |
1730 | struct ieee80211_bss_conf *bss_conf, | |
1731 | u32 changed) | |
1732 | { | |
bce048d7 JM |
1733 | struct ath_wiphy *aphy = hw->priv; |
1734 | struct ath_softc *sc = aphy->sc; | |
2d0ddec5 | 1735 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1736 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1737 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1738 | int slottime; |
c6089ccc | 1739 | int error; |
f078f209 | 1740 | |
141b38b6 S |
1741 | mutex_lock(&sc->mutex); |
1742 | ||
c6089ccc S |
1743 | if (changed & BSS_CHANGED_BSSID) { |
1744 | /* Set BSSID */ | |
1745 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | |
1746 | memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); | |
1510718d | 1747 | common->curaid = 0; |
f2b2143e | 1748 | ath9k_hw_write_associd(ah); |
2d0ddec5 | 1749 | |
c6089ccc S |
1750 | /* Set aggregation protection mode parameters */ |
1751 | sc->config.ath_aggr_prot = 0; | |
2d0ddec5 | 1752 | |
c6089ccc S |
1753 | /* Only legacy IBSS for now */ |
1754 | if (vif->type == NL80211_IFTYPE_ADHOC) | |
1755 | ath_update_chainmask(sc, 0); | |
2d0ddec5 | 1756 | |
c6089ccc S |
1757 | ath_print(common, ATH_DBG_CONFIG, |
1758 | "BSSID: %pM aid: 0x%x\n", | |
1759 | common->curbssid, common->curaid); | |
2d0ddec5 | 1760 | |
c6089ccc S |
1761 | /* need to reconfigure the beacon */ |
1762 | sc->sc_flags &= ~SC_OP_BEACONS ; | |
1763 | } | |
2d0ddec5 | 1764 | |
c6089ccc S |
1765 | /* Enable transmission of beacons (AP, IBSS, MESH) */ |
1766 | if ((changed & BSS_CHANGED_BEACON) || | |
1767 | ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { | |
1768 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1769 | error = ath_beacon_alloc(aphy, vif); | |
1770 | if (!error) | |
1771 | ath_beacon_config(sc, vif); | |
0005baf4 FF |
1772 | } |
1773 | ||
1774 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
1775 | if (bss_conf->use_short_slot) | |
1776 | slottime = 9; | |
1777 | else | |
1778 | slottime = 20; | |
1779 | if (vif->type == NL80211_IFTYPE_AP) { | |
1780 | /* | |
1781 | * Defer update, so that connected stations can adjust | |
1782 | * their settings at the same time. | |
1783 | * See beacon.c for more details | |
1784 | */ | |
1785 | sc->beacon.slottime = slottime; | |
1786 | sc->beacon.updateslot = UPDATE; | |
1787 | } else { | |
1788 | ah->slottime = slottime; | |
1789 | ath9k_hw_init_global_settings(ah); | |
1790 | } | |
2d0ddec5 JB |
1791 | } |
1792 | ||
c6089ccc S |
1793 | /* Disable transmission of beacons */ |
1794 | if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon) | |
1795 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 | 1796 | |
c6089ccc S |
1797 | if (changed & BSS_CHANGED_BEACON_INT) { |
1798 | sc->beacon_interval = bss_conf->beacon_int; | |
1799 | /* | |
1800 | * In case of AP mode, the HW TSF has to be reset | |
1801 | * when the beacon interval changes. | |
1802 | */ | |
1803 | if (vif->type == NL80211_IFTYPE_AP) { | |
1804 | sc->sc_flags |= SC_OP_TSF_RESET; | |
1805 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 JB |
1806 | error = ath_beacon_alloc(aphy, vif); |
1807 | if (!error) | |
1808 | ath_beacon_config(sc, vif); | |
c6089ccc S |
1809 | } else { |
1810 | ath_beacon_config(sc, vif); | |
2d0ddec5 JB |
1811 | } |
1812 | } | |
1813 | ||
8feceb67 | 1814 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
c46917bb LR |
1815 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
1816 | bss_conf->use_short_preamble); | |
8feceb67 VT |
1817 | if (bss_conf->use_short_preamble) |
1818 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
1819 | else | |
1820 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
1821 | } | |
f078f209 | 1822 | |
8feceb67 | 1823 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
c46917bb LR |
1824 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
1825 | bss_conf->use_cts_prot); | |
8feceb67 VT |
1826 | if (bss_conf->use_cts_prot && |
1827 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
1828 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
1829 | else | |
1830 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
1831 | } | |
f078f209 | 1832 | |
8feceb67 | 1833 | if (changed & BSS_CHANGED_ASSOC) { |
c46917bb | 1834 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", |
8feceb67 | 1835 | bss_conf->assoc); |
5640b08e | 1836 | ath9k_bss_assoc_info(sc, vif, bss_conf); |
8feceb67 | 1837 | } |
141b38b6 S |
1838 | |
1839 | mutex_unlock(&sc->mutex); | |
8feceb67 | 1840 | } |
f078f209 | 1841 | |
8feceb67 VT |
1842 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) |
1843 | { | |
1844 | u64 tsf; | |
bce048d7 JM |
1845 | struct ath_wiphy *aphy = hw->priv; |
1846 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 1847 | |
141b38b6 S |
1848 | mutex_lock(&sc->mutex); |
1849 | tsf = ath9k_hw_gettsf64(sc->sc_ah); | |
1850 | mutex_unlock(&sc->mutex); | |
f078f209 | 1851 | |
8feceb67 VT |
1852 | return tsf; |
1853 | } | |
f078f209 | 1854 | |
3b5d665b AF |
1855 | static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) |
1856 | { | |
bce048d7 JM |
1857 | struct ath_wiphy *aphy = hw->priv; |
1858 | struct ath_softc *sc = aphy->sc; | |
3b5d665b | 1859 | |
141b38b6 S |
1860 | mutex_lock(&sc->mutex); |
1861 | ath9k_hw_settsf64(sc->sc_ah, tsf); | |
1862 | mutex_unlock(&sc->mutex); | |
3b5d665b AF |
1863 | } |
1864 | ||
8feceb67 VT |
1865 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) |
1866 | { | |
bce048d7 JM |
1867 | struct ath_wiphy *aphy = hw->priv; |
1868 | struct ath_softc *sc = aphy->sc; | |
c83be688 | 1869 | |
141b38b6 | 1870 | mutex_lock(&sc->mutex); |
21526d57 LR |
1871 | |
1872 | ath9k_ps_wakeup(sc); | |
141b38b6 | 1873 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
1874 | ath9k_ps_restore(sc); |
1875 | ||
141b38b6 | 1876 | mutex_unlock(&sc->mutex); |
8feceb67 | 1877 | } |
f078f209 | 1878 | |
8feceb67 | 1879 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 1880 | struct ieee80211_vif *vif, |
141b38b6 S |
1881 | enum ieee80211_ampdu_mlme_action action, |
1882 | struct ieee80211_sta *sta, | |
1883 | u16 tid, u16 *ssn) | |
8feceb67 | 1884 | { |
bce048d7 JM |
1885 | struct ath_wiphy *aphy = hw->priv; |
1886 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 1887 | int ret = 0; |
f078f209 | 1888 | |
85ad181e JB |
1889 | local_bh_disable(); |
1890 | ||
8feceb67 VT |
1891 | switch (action) { |
1892 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
1893 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
1894 | ret = -ENOTSUPP; | |
8feceb67 VT |
1895 | break; |
1896 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
1897 | break; |
1898 | case IEEE80211_AMPDU_TX_START: | |
8b685ba9 | 1899 | ath9k_ps_wakeup(sc); |
f83da965 | 1900 | ath_tx_aggr_start(sc, sta, tid, ssn); |
c951ad35 | 1901 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1902 | ath9k_ps_restore(sc); |
8feceb67 VT |
1903 | break; |
1904 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 1905 | ath9k_ps_wakeup(sc); |
f83da965 | 1906 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 1907 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 1908 | ath9k_ps_restore(sc); |
8feceb67 | 1909 | break; |
b1720231 | 1910 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 1911 | ath9k_ps_wakeup(sc); |
8469cdef | 1912 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 1913 | ath9k_ps_restore(sc); |
8469cdef | 1914 | break; |
8feceb67 | 1915 | default: |
c46917bb LR |
1916 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
1917 | "Unknown AMPDU action\n"); | |
8feceb67 VT |
1918 | } |
1919 | ||
85ad181e JB |
1920 | local_bh_enable(); |
1921 | ||
8feceb67 | 1922 | return ret; |
f078f209 LR |
1923 | } |
1924 | ||
62dad5b0 BP |
1925 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
1926 | struct survey_info *survey) | |
1927 | { | |
1928 | struct ath_wiphy *aphy = hw->priv; | |
1929 | struct ath_softc *sc = aphy->sc; | |
1930 | struct ath_hw *ah = sc->sc_ah; | |
1931 | struct ath_common *common = ath9k_hw_common(ah); | |
1932 | struct ieee80211_conf *conf = &hw->conf; | |
1933 | ||
1934 | if (idx != 0) | |
1935 | return -ENOENT; | |
1936 | ||
1937 | survey->channel = conf->channel; | |
1938 | survey->filled = SURVEY_INFO_NOISE_DBM; | |
1939 | survey->noise = common->ani.noise_floor; | |
1940 | ||
1941 | return 0; | |
1942 | } | |
1943 | ||
0c98de65 S |
1944 | static void ath9k_sw_scan_start(struct ieee80211_hw *hw) |
1945 | { | |
bce048d7 JM |
1946 | struct ath_wiphy *aphy = hw->priv; |
1947 | struct ath_softc *sc = aphy->sc; | |
05c78d6d | 1948 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
0c98de65 | 1949 | |
3d832611 | 1950 | mutex_lock(&sc->mutex); |
8089cc47 JM |
1951 | if (ath9k_wiphy_scanning(sc)) { |
1952 | printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the " | |
1953 | "same time\n"); | |
1954 | /* | |
1955 | * Do not allow the concurrent scanning state for now. This | |
1956 | * could be improved with scanning control moved into ath9k. | |
1957 | */ | |
3d832611 | 1958 | mutex_unlock(&sc->mutex); |
8089cc47 JM |
1959 | return; |
1960 | } | |
1961 | ||
1962 | aphy->state = ATH_WIPHY_SCAN; | |
1963 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
0c98de65 | 1964 | sc->sc_flags |= SC_OP_SCANNING; |
05c78d6d | 1965 | del_timer_sync(&common->ani.timer); |
9f42c2b6 | 1966 | cancel_work_sync(&sc->paprd_work); |
b6ce5c33 | 1967 | cancel_delayed_work_sync(&sc->tx_complete_work); |
3d832611 | 1968 | mutex_unlock(&sc->mutex); |
0c98de65 S |
1969 | } |
1970 | ||
1971 | static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) | |
1972 | { | |
bce048d7 JM |
1973 | struct ath_wiphy *aphy = hw->priv; |
1974 | struct ath_softc *sc = aphy->sc; | |
05c78d6d | 1975 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
0c98de65 | 1976 | |
3d832611 | 1977 | mutex_lock(&sc->mutex); |
8089cc47 | 1978 | aphy->state = ATH_WIPHY_ACTIVE; |
0c98de65 | 1979 | sc->sc_flags &= ~SC_OP_SCANNING; |
9c07a777 | 1980 | sc->sc_flags |= SC_OP_FULL_RESET; |
05c78d6d | 1981 | ath_start_ani(common); |
b6ce5c33 | 1982 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
d0bec342 | 1983 | ath_beacon_config(sc, NULL); |
3d832611 | 1984 | mutex_unlock(&sc->mutex); |
0c98de65 S |
1985 | } |
1986 | ||
e239d859 FF |
1987 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
1988 | { | |
1989 | struct ath_wiphy *aphy = hw->priv; | |
1990 | struct ath_softc *sc = aphy->sc; | |
1991 | struct ath_hw *ah = sc->sc_ah; | |
1992 | ||
1993 | mutex_lock(&sc->mutex); | |
1994 | ah->coverage_class = coverage_class; | |
1995 | ath9k_hw_init_global_settings(ah); | |
1996 | mutex_unlock(&sc->mutex); | |
1997 | } | |
1998 | ||
6baff7f9 | 1999 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2000 | .tx = ath9k_tx, |
2001 | .start = ath9k_start, | |
2002 | .stop = ath9k_stop, | |
2003 | .add_interface = ath9k_add_interface, | |
2004 | .remove_interface = ath9k_remove_interface, | |
2005 | .config = ath9k_config, | |
8feceb67 | 2006 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2007 | .sta_add = ath9k_sta_add, |
2008 | .sta_remove = ath9k_sta_remove, | |
8feceb67 | 2009 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2010 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2011 | .set_key = ath9k_set_key, |
8feceb67 | 2012 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2013 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2014 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2015 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2016 | .get_survey = ath9k_get_survey, |
0c98de65 S |
2017 | .sw_scan_start = ath9k_sw_scan_start, |
2018 | .sw_scan_complete = ath9k_sw_scan_complete, | |
3b319aae | 2019 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2020 | .set_coverage_class = ath9k_set_coverage_class, |
8feceb67 | 2021 | }; |